From 0373afa7a5f3f5eb9c0e84bb2594f727a9b05b81 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Thu, 18 Nov 2010 21:36:48 +0100 Subject: update routerboard patches and kernel configs --- target/rb4xx/kernel.config | 103 +- target/rb4xx/patches/ar71xx.patch | 43501 ++++++++++++------------------------ 2 files changed, 13999 insertions(+), 29605 deletions(-) (limited to 'target/rb4xx') diff --git a/target/rb4xx/kernel.config b/target/rb4xx/kernel.config index 7604854c6..4284af347 100644 --- a/target/rb4xx/kernel.config +++ b/target/rb4xx/kernel.config @@ -1,14 +1,14 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.35.7 -# Thu Oct 14 20:34:11 2010 +# Linux kernel version: 2.6.36 +# Thu Nov 18 21:36:13 2010 # CONFIG_MIPS=y # # Machine selection # -# CONFIG_MACH_ALCHEMY is not set +# CONFIG_MIPS_ALCHEMY is not set # CONFIG_AR7 is not set CONFIG_ATHEROS_AR71XX=y # CONFIG_BCM47XX is not set @@ -16,6 +16,7 @@ CONFIG_ATHEROS_AR71XX=y # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_MACH_JZ4740 is not set # CONFIG_LASAT is not set # CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set @@ -91,6 +92,7 @@ CONFIG_AR71XX_DEV_LEDS_GPIO=y # CONFIG_AR71XX_DEV_PB9X_PCI is not set CONFIG_AR71XX_DEV_USB=y # CONFIG_AR71XX_NVRAM is not set +CONFIG_CAVIUM_OCTEON_HELPER=y CONFIG_LOONGSON_UART_BASE=y # CONFIG_LOONGSON_MC146818 is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y @@ -101,7 +103,6 @@ CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y @@ -116,7 +117,6 @@ CONFIG_MIPS_MACHINE=y # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_GPIO=y CONFIG_CPU_BIG_ENDIAN=y -# CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 @@ -124,29 +124,8 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # -# CONFIG_CPU_LOONGSON2E is not set -# CONFIG_CPU_LOONGSON2F is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_SYS_HAS_CPU_MIPS32_R2=y CONFIG_CPU_MIPS32=y @@ -159,16 +138,11 @@ CONFIG_HARDWARE_WATCHPOINTS=y # Kernel type # CONFIG_32BIT=y -# CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y -# CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set -# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set # CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y @@ -178,8 +152,6 @@ CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y @@ -232,7 +204,6 @@ CONFIG_SYSVIPC_SYSCTL=y # RCU Subsystem # CONFIG_TREE_RCU=y -# CONFIG_TREE_PREEMPT_RCU is not set # CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=32 @@ -277,11 +248,13 @@ CONFIG_SLAB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y # # GCOV-based kernel profiling # -# CONFIG_SLOW_WORK is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y @@ -303,8 +276,6 @@ CONFIG_BLOCK=y CONFIG_IOSCHED_NOOP=y # CONFIG_IOSCHED_DEADLINE is not set # CONFIG_IOSCHED_CFQ is not set -# CONFIG_DEFAULT_DEADLINE is not set -# CONFIG_DEFAULT_CFQ is not set CONFIG_DEFAULT_NOOP=y CONFIG_DEFAULT_IOSCHED="noop" # CONFIG_INLINE_SPIN_TRYLOCK is not set @@ -399,6 +370,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set @@ -535,7 +507,6 @@ CONFIG_MTD_NAND=y # CONFIG_MTD_SM_COMMON is not set # CONFIG_MTD_NAND_MUSEUM_IDS is not set # CONFIG_MTD_NAND_DENALI is not set -CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018 CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_RICOH is not set # CONFIG_MTD_NAND_DISKONCHIP is not set @@ -601,6 +572,7 @@ CONFIG_SCSI_MOD=y # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set +# CONFIG_FIREWIRE_NOSY is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set @@ -673,7 +645,6 @@ CONFIG_NET_PCI=y # CONFIG_SMSC9420 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set -# CONFIG_KS8842 is not set # CONFIG_KS8851_MLL is not set # CONFIG_VIA_RHINE is not set # CONFIG_SC92031 is not set @@ -716,6 +687,10 @@ CONFIG_WLAN=y # Enable WiMAX (Networking options) to see the WiMAX drivers # # CONFIG_WAN is not set + +# +# CAIF transport drivers +# # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set @@ -760,6 +735,7 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # # Non-8250 serial port support # +# CONFIG_SERIAL_MFD_HSU is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set @@ -843,16 +819,7 @@ CONFIG_SSB_POSSIBLE=y # Sonics Silicon Backplane # # CONFIG_SSB is not set -CONFIG_MFD_SUPPORT=y -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_ABX500_CORE is not set -# CONFIG_MFD_TIMBERDALE is not set -# CONFIG_LPC_SCH is not set -# CONFIG_MFD_RDC321X is not set -# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_SUPPORT is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set @@ -871,26 +838,7 @@ CONFIG_MFD_SUPPORT=y # # CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set - -# -# Enable Host or Gadget support to see Inventra options -# - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# -# CONFIG_USB_GADGET is not set - -# -# OTG and related infrastructure -# +# CONFIG_USB_SUPPORT is not set # CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set @@ -917,11 +865,9 @@ CONFIG_RTC_LIB=y # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set -# CONFIG_AUFS_FS is not set CONFIG_FILE_LOCKING=y # CONFIG_FSNOTIFY is not set # CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY is not set # CONFIG_INOTIFY_USER is not set # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set @@ -972,10 +918,12 @@ CONFIG_YAFFS_YAFFS1=y # CONFIG_YAFFS_DOES_ECC is not set CONFIG_YAFFS_YAFFS2=y CONFIG_YAFFS_AUTO_YAFFS2=y -# CONFIG_YAFFS_DISABLE_LAZY_LOAD is not set -# CONFIG_YAFFS_DISABLE_WIDE_TNODES is not set +# CONFIG_YAFFS_DISABLE_TAGS_ECC is not set # CONFIG_YAFFS_ALWAYS_CHECK_CHUNK_ERASED is not set -CONFIG_YAFFS_SHORT_NAMES_IN_RAM=y +# CONFIG_YAFFS_EMPTY_LOST_AND_FOUND is not set +# CONFIG_YAFFS_DISABLE_BLOCK_REFRESHING is not set +# CONFIG_YAFFS_DISABLE_BACKGROUND is not set +CONFIG_YAFFS_XATTR=y # CONFIG_JFFS2_FS is not set # CONFIG_LOGFS is not set # CONFIG_CRAMFS is not set @@ -1014,12 +962,13 @@ CONFIG_PRINTK_TIME=y # CONFIG_ENABLE_WARN_DEPRECATED is not set # CONFIG_ENABLE_MUST_CHECK is not set CONFIG_FRAME_WARN=0 -CONFIG_MAGIC_SYSRQ=y +# CONFIG_MAGIC_SYSRQ is not set # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set +# CONFIG_HARDLOCKUP_DETECTOR is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_SYSCTL_SYSCALL_CHECK is not set @@ -1044,9 +993,6 @@ CONFIG_CMDLINE="console=ttyS0,115200" # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set -# CONFIG_DEFAULT_SECURITY_SELINUX is not set -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_DEFAULT_SECURITY="" CONFIG_CRYPTO=y @@ -1159,3 +1105,4 @@ CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y +CONFIG_GENERIC_ATOMIC64=y diff --git a/target/rb4xx/patches/ar71xx.patch b/target/rb4xx/patches/ar71xx.patch index 697379d36..f53e86f81 100644 --- a/target/rb4xx/patches/ar71xx.patch +++ b/target/rb4xx/patches/ar71xx.patch @@ -1,11500 +1,1290 @@ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/ar71xx.c linux-2.6.35.7/arch/mips/ar71xx/ar71xx.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/ar71xx.c 2010-10-14 20:27:55.855601218 +0200 -@@ -0,0 +1,177 @@ -+/* -+ * AR71xx SoC routines -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+ -+static DEFINE_MUTEX(ar71xx_flash_mutex); -+ -+void __iomem *ar71xx_ddr_base; -+EXPORT_SYMBOL_GPL(ar71xx_ddr_base); -+ -+void __iomem *ar71xx_pll_base; -+EXPORT_SYMBOL_GPL(ar71xx_pll_base); -+ -+void __iomem *ar71xx_reset_base; -+EXPORT_SYMBOL_GPL(ar71xx_reset_base); -+ -+void __iomem *ar71xx_gpio_base; -+EXPORT_SYMBOL_GPL(ar71xx_gpio_base); -+ -+void __iomem *ar71xx_usb_ctrl_base; -+EXPORT_SYMBOL_GPL(ar71xx_usb_ctrl_base); -+ -+void ar71xx_device_stop(u32 mask) -+{ -+ unsigned long flags; -+ u32 mask_inv; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ t |= mask; -+ t &= ~mask_inv; -+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t | mask); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_stop); -+ -+void ar71xx_device_start(u32 mask) -+{ -+ unsigned long flags; -+ u32 mask_inv; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ t &= ~mask; -+ t |= mask_inv; -+ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_start); -+ -+int ar71xx_device_stopped(u32 mask) -+{ -+ unsigned long flags; -+ u32 t; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ local_irq_save(flags); -+ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); -+ local_irq_restore(flags); -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ return ((t & mask) == mask); -+} -+EXPORT_SYMBOL_GPL(ar71xx_device_stopped); -+ -+void ar71xx_ddr_flush(u32 reg) -+{ -+ ar71xx_ddr_wr(reg, 1); -+ while ((ar71xx_ddr_rr(reg) & 0x1)); -+ -+ ar71xx_ddr_wr(reg, 1); -+ while ((ar71xx_ddr_rr(reg) & 0x1)); -+} -+EXPORT_SYMBOL_GPL(ar71xx_ddr_flush); -+ -+void ar71xx_flash_acquire(void) -+{ -+ mutex_lock(&ar71xx_flash_mutex); -+} -+EXPORT_SYMBOL_GPL(ar71xx_flash_acquire); -+ -+void ar71xx_flash_release(void) -+{ -+ mutex_unlock(&ar71xx_flash_mutex); -+} -+EXPORT_SYMBOL_GPL(ar71xx_flash_release); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap91-eth.c linux-2.6.35.7/arch/mips/ar71xx/dev-ap91-eth.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap91-eth.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-ap91-eth.c 2010-10-14 20:27:55.876851074 +0200 -@@ -0,0 +1,70 @@ -+/* -+ * Atheros AP91 reference board ethernet initialization -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-ap91-eth.h" -+ -+static struct dsa_chip_data ap91_dsa_chip = { -+ .port_names[0] = "cpu", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+}; -+ -+static struct dsa_platform_data ap91_dsa_data = { -+ .nr_chips = 1, -+ .chip = &ap91_dsa_chip, -+}; -+ -+static void ap91_eth_set_port_name(unsigned port, const char *name) -+{ -+ if (port < 1 || port > 5) -+ return; -+ -+ if (name) -+ ap91_dsa_chip.port_names[port] = (char *) name; -+} -+ -+void __init ap91_eth_init(u8 *mac_addr, const char *port_names[]) -+{ -+ if (mac_addr) -+ ar71xx_set_mac_base(mac_addr); -+ -+ if (port_names) { -+ int i; -+ -+ for (i = 0; i < AP91_ETH_NUM_PORT_NAMES; i++) -+ ap91_eth_set_port_name(i + 1, port_names[i]); -+ } -+ -+ /* WAN port */ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.fifo_cfg1 = 0x0fff0000; -+ ar71xx_eth0_data.fifo_cfg2 = 0x00001fff; -+ ar71xx_eth0_data.fifo_cfg3 = 0x008001ff; -+ -+ /* LAN ports */ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.fifo_cfg1 = 0x0fff0000; -+ ar71xx_eth1_data.fifo_cfg2 = 0x00001fff; -+ ar71xx_eth1_data.fifo_cfg3 = 0x008001ff; -+ -+ ar71xx_add_device_mdio(0x0); -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_dsa(1, &ap91_dsa_data); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap91-eth.h linux-2.6.35.7/arch/mips/ar71xx/dev-ap91-eth.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap91-eth.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-ap91-eth.h 2010-10-14 20:27:55.918101097 +0200 -@@ -0,0 +1,23 @@ -+/* -+ * Atheros AP91 reference board ethernet initialization -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP91_ETH_H -+#define _AR71XX_DEV_AP91_ETH_H -+ -+#define AP91_ETH_NUM_PORT_NAMES 4 -+ -+#if defined(CONFIG_AR71XX_DEV_AP91_ETH) -+void ap91_eth_init(u8 *mac_addr, const char *port_names[]) __init; -+#else -+static inline void ap91_eth_init(u8 *mac_addr) { } -+#endif -+ -+#endif /* _AR71XX_DEV_AP91_ETH_H */ -+ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap91-pci.c linux-2.6.35.7/arch/mips/ar71xx/dev-ap91-pci.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap91-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-ap91-pci.c 2010-10-14 20:27:55.964356595 +0200 -@@ -0,0 +1,114 @@ -+/* -+ * Atheros AP91 reference board PCI initialization -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-ap91-pci.h" -+ -+static struct ath9k_platform_data ap91_wmac_data; -+static char ap91_wmac_mac[6]; -+static int ap91_pci_fixup_enabled; -+ -+static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+static int ap91_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch(PCI_SLOT(dev->devfn)) { -+ case 0: -+ dev->dev.platform_data = &ap91_wmac_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+static void ap91_pci_fixup(struct pci_dev *dev) -+{ -+ void __iomem *mem; -+ u16 *cal_data; -+ u16 cmd; -+ u32 val; -+ -+ if (!ap91_pci_fixup_enabled) -+ return; -+ -+ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); -+ -+ cal_data = ap91_wmac_data.eeprom_data; -+ if (*cal_data != 0xa55a) { -+ printk(KERN_ERR "PCI: no calibration data found for %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); -+ if (!mem) { -+ printk(KERN_ERR "PCI: ioremap error for device %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ /* Setup the PCI device to allow access to the internal registers */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ /* set pointer to first reg address */ -+ cal_data += 3; -+ while (*cal_data != 0xffff) { -+ u32 reg; -+ reg = *cal_data++; -+ val = *cal_data++; -+ val |= (*cal_data++) << 16; -+ -+ __raw_writel(val, mem + reg); -+ udelay(100); -+ } -+ -+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); -+ dev->vendor = val & 0xffff; -+ dev->device = (val >> 16) & 0xffff; -+ -+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); -+ dev->revision = val & 0xff; -+ dev->class = val >> 8; /* upper 3 bytes */ -+ -+ iounmap(mem); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap91_pci_fixup); -+ -+void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr) -+{ -+ if (cal_data) -+ memcpy(ap91_wmac_data.eeprom_data, cal_data, -+ sizeof(ap91_wmac_data.eeprom_data)); -+ -+ if (mac_addr) { -+ memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac)); -+ ap91_wmac_data.macaddr = ap91_wmac_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs); -+ -+ ap91_pci_fixup_enabled = 1; -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap91-pci.h linux-2.6.35.7/arch/mips/ar71xx/dev-ap91-pci.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap91-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-ap91-pci.h 2010-10-14 20:27:56.005601094 +0200 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros AP91 reference board PCI initialization -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP91_PCI_H -+#define _AR71XX_DEV_AP91_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_AP91_PCI) -+void ap91_pci_init(u8 *cal_data, u8 *mac_addr) __init; -+#else -+static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) { } -+#endif -+ -+#endif /* _AR71XX_DEV_AP91_PCI_H */ -+ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap94-pci.c linux-2.6.35.7/arch/mips/ar71xx/dev-ap94-pci.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap94-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-ap94-pci.c 2010-10-14 20:27:56.056135764 +0200 -@@ -0,0 +1,159 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-ap94-pci.h" -+ -+static struct ath9k_platform_data ap94_wmac0_data; -+static struct ath9k_platform_data ap94_wmac1_data; -+static char ap94_wmac0_mac[6]; -+static char ap94_wmac1_mac[6]; -+static int ap94_pci_fixup_enabled; -+ -+static struct ar71xx_pci_irq ap94_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ } -+}; -+ -+static int ap94_pci_plat_dev_init(struct pci_dev *dev) -+{ -+ switch(PCI_SLOT(dev->devfn)) { -+ case 17: -+ dev->dev.platform_data = &ap94_wmac0_data; -+ break; -+ -+ case 18: -+ dev->dev.platform_data = &ap94_wmac1_data; -+ break; -+ } -+ -+ return 0; -+} -+ -+static void ap94_pci_fixup(struct pci_dev *dev) -+{ -+ void __iomem *mem; -+ u16 *cal_data; -+ u16 cmd; -+ u32 bar0; -+ u32 val; -+ -+ if (!ap94_pci_fixup_enabled) -+ return; -+ -+ switch (PCI_SLOT(dev->devfn)) { -+ case 17: -+ cal_data = ap94_wmac0_data.eeprom_data; -+ break; -+ case 18: -+ cal_data = ap94_wmac1_data.eeprom_data; -+ break; -+ default: -+ return; -+ } -+ -+ if (*cal_data != 0xa55a) { -+ printk(KERN_ERR "PCI: no calibration data found for %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); -+ if (!mem) { -+ printk(KERN_ERR "PCI: ioremap error for device %s\n", -+ pci_name(dev)); -+ return; -+ } -+ -+ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); -+ -+ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); -+ -+ /* Setup the PCI device to allow access to the internal registers */ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE); -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ /* set pointer to first reg address */ -+ cal_data += 3; -+ while (*cal_data != 0xffff) { -+ u32 reg; -+ reg = *cal_data++; -+ val = *cal_data++; -+ val |= (*cal_data++) << 16; -+ -+ __raw_writel(val, mem + reg); -+ udelay(100); -+ } -+ -+ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); -+ dev->vendor = val & 0xffff; -+ dev->device = (val >> 16) & 0xffff; -+ -+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); -+ dev->revision = val & 0xff; -+ dev->class = val >> 8; /* upper 3 bytes */ -+ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+ -+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); -+ -+ iounmap(mem); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap94_pci_fixup); -+ -+void __init ap94_pci_enable_quirk_wndr3700(void) -+{ -+ ap94_wmac0_data.quirk_wndr3700 = 1; -+ ap94_wmac1_data.quirk_wndr3700 = 1; -+} -+ -+void __init ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) -+{ -+ if (cal_data0) -+ memcpy(ap94_wmac0_data.eeprom_data, cal_data0, -+ sizeof(ap94_wmac0_data.eeprom_data)); -+ -+ if (cal_data1) -+ memcpy(ap94_wmac1_data.eeprom_data, cal_data1, -+ sizeof(ap94_wmac1_data.eeprom_data)); -+ -+ if (mac_addr0) { -+ memcpy(ap94_wmac0_mac, mac_addr0, sizeof(ap94_wmac0_mac)); -+ ap94_wmac0_data.macaddr = ap94_wmac0_mac; -+ } -+ -+ if (mac_addr1) { -+ memcpy(ap94_wmac1_mac, mac_addr1, sizeof(ap94_wmac1_mac)); -+ ap94_wmac1_data.macaddr = ap94_wmac1_mac; -+ } -+ -+ ar71xx_pci_plat_dev_init = ap94_pci_plat_dev_init; -+ ar71xx_pci_init(ARRAY_SIZE(ap94_pci_irqs), ap94_pci_irqs); -+ -+ ap94_pci_fixup_enabled = 1; -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap94-pci.h linux-2.6.35.7/arch/mips/ar71xx/dev-ap94-pci.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ap94-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-ap94-pci.h 2010-10-14 20:27:56.105939718 +0200 -@@ -0,0 +1,28 @@ -+/* -+ * Atheros AP94 reference board PCI initialization -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AP94_PCI_H -+#define _AR71XX_DEV_AP94_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_AP94_PCI) -+void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) __init; -+ -+void ap94_pci_enable_quirk_wndr3700(void) __init; -+ -+#else -+static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, -+ u8 *cal_data1, u8 *mac_addr1) {} -+ -+static inline void ap94_pci_enable_quirk_wndr3700(void) {} -+#endif -+ -+#endif /* _AR71XX_DEV_AP94_PCI_H */ -+ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ar913x-wmac.c linux-2.6.35.7/arch/mips/ar71xx/dev-ar913x-wmac.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ar913x-wmac.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-ar913x-wmac.c 2010-10-14 20:27:56.154378236 +0200 -@@ -0,0 +1,68 @@ -+/* -+ * Atheros AR913x SoC built-in WMAC device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "dev-ar913x-wmac.h" -+ -+static struct ath9k_platform_data ar913x_wmac_data; -+static char ar913x_wmac_mac[6]; -+ -+static struct resource ar913x_wmac_resources[] = { -+ { -+ .start = AR91XX_WMAC_BASE, -+ .end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, { -+ .start = AR71XX_CPU_IRQ_IP2, -+ .end = AR71XX_CPU_IRQ_IP2, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct platform_device ar913x_wmac_device = { -+ .name = "ath9k", -+ .id = -1, -+ .resource = ar913x_wmac_resources, -+ .num_resources = ARRAY_SIZE(ar913x_wmac_resources), -+ .dev = { -+ .platform_data = &ar913x_wmac_data, -+ }, -+}; -+ -+void __init ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) -+{ -+ if (cal_data) -+ memcpy(ar913x_wmac_data.eeprom_data, cal_data, -+ sizeof(ar913x_wmac_data.eeprom_data)); -+ -+ if (mac_addr) { -+ memcpy(ar913x_wmac_mac, mac_addr, sizeof(ar913x_wmac_mac)); -+ ar913x_wmac_data.macaddr = ar913x_wmac_mac; -+ } -+ -+ ar71xx_device_stop(RESET_MODULE_AMBA2WMAC); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_AMBA2WMAC); -+ mdelay(10); -+ -+ platform_device_register(&ar913x_wmac_device); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ar913x-wmac.h linux-2.6.35.7/arch/mips/ar71xx/dev-ar913x-wmac.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-ar913x-wmac.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-ar913x-wmac.h 2010-10-14 20:27:56.205590855 +0200 -@@ -0,0 +1,19 @@ -+/* -+ * Atheros AR913x SoC built-in WMAC device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_AR913X_WMAC_H -+#define _AR71XX_DEV_AR913X_WMAC_H -+ -+void ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) __init; -+ -+#endif /* _AR71XX_DEV_AR913X_WMAC_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-dsa.c linux-2.6.35.7/arch/mips/ar71xx/dev-dsa.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-dsa.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-dsa.c 2010-10-14 20:27:56.255387205 +0200 -@@ -0,0 +1,50 @@ -+/* -+ * Atheros AR71xx DSA switch device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+#include "dev-dsa.h" -+ -+static struct platform_device ar71xx_dsa_switch_device = { -+ .name = "dsa", -+ .id = 0, -+}; -+ -+void __init ar71xx_add_device_dsa(unsigned int id, -+ struct dsa_platform_data *d) -+{ -+ int i; -+ -+ switch (id) { -+ case 0: -+ d->netdev = &ar71xx_eth0_device.dev; -+ break; -+ case 1: -+ d->netdev = &ar71xx_eth1_device.dev; -+ break; -+ default: -+ printk(KERN_ERR -+ "ar71xx: invalid ethernet id %d for DSA switch\n", -+ id); -+ return; -+ } -+ -+ for (i = 0; i < d->nr_chips; i++) -+ d->chip[i].mii_bus = &ar71xx_mdio_device.dev; -+ -+ ar71xx_dsa_switch_device.dev.platform_data = d; -+ -+ platform_device_register(&ar71xx_dsa_switch_device); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-dsa.h linux-2.6.35.7/arch/mips/ar71xx/dev-dsa.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-dsa.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-dsa.h 2010-10-14 20:27:56.305200658 +0200 -@@ -0,0 +1,20 @@ -+/* -+ * Atheros AR71xx DSA switch device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_DSA_H -+#define _AR71XX_DEV_DSA_H -+ -+#include -+ -+void ar71xx_add_device_dsa(unsigned int id, -+ struct dsa_platform_data *d) __init; -+ -+#endif /* _AR71XX_DEV_DSA_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-gpio-buttons.c linux-2.6.35.7/arch/mips/ar71xx/dev-gpio-buttons.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-gpio-buttons.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-gpio-buttons.c 2010-10-14 20:27:56.355043092 +0200 -@@ -0,0 +1,58 @@ -+/* -+ * Atheros AR71xx GPIO button support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include "linux/init.h" -+#include -+ -+#include "dev-gpio-buttons.h" -+ -+void __init ar71xx_add_device_gpio_buttons(int id, -+ unsigned poll_interval, -+ unsigned nbuttons, -+ struct gpio_button *buttons) -+{ -+ struct platform_device *pdev; -+ struct gpio_buttons_platform_data pdata; -+ struct gpio_button *p; -+ int err; -+ -+ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return; -+ -+ memcpy(p, buttons, nbuttons * sizeof(*p)); -+ -+ pdev = platform_device_alloc("gpio-buttons", id); -+ if (!pdev) -+ goto err_free_buttons; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.poll_interval = poll_interval; -+ pdata.nbuttons = nbuttons; -+ pdata.buttons = p; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+ -+err_free_buttons: -+ kfree(p); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-gpio-buttons.h linux-2.6.35.7/arch/mips/ar71xx/dev-gpio-buttons.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-gpio-buttons.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-gpio-buttons.h 2010-10-14 20:27:56.404843567 +0200 -@@ -0,0 +1,25 @@ -+/* -+ * Atheros AR71xx GPIO button support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_GPIO_BUTTONS_H -+#define _AR71XX_DEV_GPIO_BUTTONS_H -+ -+#include -+#include -+ -+#include -+ -+void ar71xx_add_device_gpio_buttons(int id, -+ unsigned poll_interval, -+ unsigned nbuttons, -+ struct gpio_button *buttons) __init; -+ -+#endif /* _AR71XX_DEV_GPIO_BUTTONS_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/devices.c linux-2.6.35.7/arch/mips/ar71xx/devices.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/devices.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/devices.c 2010-10-14 20:27:56.454649960 +0200 -@@ -0,0 +1,575 @@ -+/* -+ * Atheros AR71xx SoC platform devices -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "devices.h" -+ -+static u8 ar71xx_mac_base[ETH_ALEN] __initdata; -+ -+static struct resource ar71xx_uart_resources[] = { -+ { -+ .start = AR71XX_UART_BASE, -+ .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) -+static struct plat_serial8250_port ar71xx_uart_data[] = { -+ { -+ .mapbase = AR71XX_UART_BASE, -+ .irq = AR71XX_MISC_IRQ_UART, -+ .flags = AR71XX_UART_FLAGS, -+ .iotype = UPIO_MEM32, -+ .regshift = 2, -+ }, { -+ /* terminating entry */ -+ } -+}; -+ -+static struct platform_device ar71xx_uart_device = { -+ .name = "serial8250", -+ .id = PLAT8250_DEV_PLATFORM, -+ .resource = ar71xx_uart_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_uart_resources), -+ .dev = { -+ .platform_data = ar71xx_uart_data -+ }, -+}; -+ -+void __init ar71xx_add_device_uart(void) -+{ -+ ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; -+ platform_device_register(&ar71xx_uart_device); -+} -+ -+static struct resource ar71xx_mdio_resources[] = { -+ { -+ .name = "mdio_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE0_BASE, -+ .end = AR71XX_GE0_BASE + 0x200 - 1, -+ } -+}; -+ -+static struct ag71xx_mdio_platform_data ar71xx_mdio_data; -+ -+struct platform_device ar71xx_mdio_device = { -+ .name = "ag71xx-mdio", -+ .id = -1, -+ .resource = ar71xx_mdio_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_mdio_resources), -+ .dev = { -+ .platform_data = &ar71xx_mdio_data, -+ }, -+}; -+ -+void __init ar71xx_add_device_mdio(u32 phy_mask) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_mdio_data.is_ar7240 = 1; -+ break; -+ default: -+ break; -+ } -+ -+ ar71xx_mdio_data.phy_mask = phy_mask; -+ -+ platform_device_register(&ar71xx_mdio_device); -+} -+ -+static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) -+{ -+ void __iomem *base; -+ u32 t; -+ -+ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); -+ -+ t = __raw_readl(base + cfg_reg); -+ t &= ~(3 << shift); -+ t |= (2 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ __raw_writel(pll_val, base + pll_reg); -+ -+ t |= (3 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ t &= ~(3 << shift); -+ __raw_writel(t, base + cfg_reg); -+ udelay(100); -+ -+ printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", -+ (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); -+ -+ iounmap(base); -+} -+ -+struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; -+struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; -+ -+static u32 ar71xx_get_eth_pll(unsigned int mac, int speed) -+{ -+ struct ar71xx_eth_pll_data *pll_data; -+ u32 pll_val; -+ -+ switch (mac) { -+ case 0: -+ pll_data = &ar71xx_eth0_pll_data; -+ break; -+ case 1: -+ pll_data = &ar71xx_eth1_pll_data; -+ break; -+ default: -+ BUG(); -+ } -+ -+ switch (speed) { -+ case SPEED_10: -+ pll_val = pll_data->pll_10; -+ break; -+ case SPEED_100: -+ pll_val = pll_data->pll_100; -+ break; -+ case SPEED_1000: -+ pll_val = pll_data->pll_1000; -+ break; -+ default: -+ BUG(); -+ } -+ -+ return pll_val; -+} -+ -+static void ar71xx_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, -+ val, AR71XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar71xx_set_pll_ge1(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(1, speed); -+ -+ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, -+ val, AR71XX_ETH1_PLL_SHIFT); -+} -+ -+static void ar724x_set_pll_ge0(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar724x_set_pll_ge1(int speed) -+{ -+ /* TODO */ -+} -+ -+static void ar91xx_set_pll_ge0(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(0, speed); -+ -+ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, -+ val, AR91XX_ETH0_PLL_SHIFT); -+} -+ -+static void ar91xx_set_pll_ge1(int speed) -+{ -+ u32 val = ar71xx_get_eth_pll(1, speed); -+ -+ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, -+ val, AR91XX_ETH1_PLL_SHIFT); -+} -+ -+static void ar71xx_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar71xx_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar724x_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar724x_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); -+} -+ -+static void ar91xx_ddr_flush_ge0(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); -+} -+ -+static void ar91xx_ddr_flush_ge1(void) -+{ -+ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); -+} -+ -+static struct resource ar71xx_eth0_resources[] = { -+ { -+ .name = "mac_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE0_BASE, -+ .end = AR71XX_GE0_BASE + 0x200 - 1, -+ }, { -+ .name = "mii_ctrl", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL, -+ .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3, -+ }, { -+ .name = "mac_irq", -+ .flags = IORESOURCE_IRQ, -+ .start = AR71XX_CPU_IRQ_GE0, -+ .end = AR71XX_CPU_IRQ_GE0, -+ }, -+}; -+ -+struct ag71xx_platform_data ar71xx_eth0_data = { -+ .reset_bit = RESET_MODULE_GE0_MAC, -+}; -+ -+struct platform_device ar71xx_eth0_device = { -+ .name = "ag71xx", -+ .id = 0, -+ .resource = ar71xx_eth0_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_eth0_resources), -+ .dev = { -+ .platform_data = &ar71xx_eth0_data, -+ }, -+}; -+ -+static struct resource ar71xx_eth1_resources[] = { -+ { -+ .name = "mac_base", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_GE1_BASE, -+ .end = AR71XX_GE1_BASE + 0x200 - 1, -+ }, { -+ .name = "mii_ctrl", -+ .flags = IORESOURCE_MEM, -+ .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL, -+ .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3, -+ }, { -+ .name = "mac_irq", -+ .flags = IORESOURCE_IRQ, -+ .start = AR71XX_CPU_IRQ_GE1, -+ .end = AR71XX_CPU_IRQ_GE1, -+ }, -+}; -+ -+struct ag71xx_platform_data ar71xx_eth1_data = { -+ .reset_bit = RESET_MODULE_GE1_MAC, -+}; -+ -+struct platform_device ar71xx_eth1_device = { -+ .name = "ag71xx", -+ .id = 1, -+ .resource = ar71xx_eth1_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_eth1_resources), -+ .dev = { -+ .platform_data = &ar71xx_eth1_data, -+ }, -+}; -+ -+#define AR71XX_PLL_VAL_1000 0x00110000 -+#define AR71XX_PLL_VAL_100 0x00001099 -+#define AR71XX_PLL_VAL_10 0x00991099 -+ -+#define AR724X_PLL_VAL_1000 0x00110000 -+#define AR724X_PLL_VAL_100 0x00001099 -+#define AR724X_PLL_VAL_10 0x00991099 -+ -+#define AR91XX_PLL_VAL_1000 0x1a000000 -+#define AR91XX_PLL_VAL_100 0x13000a44 -+#define AR91XX_PLL_VAL_10 0x00441099 -+ -+static void __init ar71xx_init_eth_pll_data(unsigned int id) -+{ -+ struct ar71xx_eth_pll_data *pll_data; -+ u32 pll_10, pll_100, pll_1000; -+ -+ switch (id) { -+ case 0: -+ pll_data = &ar71xx_eth0_pll_data; -+ break; -+ case 1: -+ pll_data = &ar71xx_eth1_pll_data; -+ break; -+ default: -+ BUG(); -+ } -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ pll_10 = AR71XX_PLL_VAL_10; -+ pll_100 = AR71XX_PLL_VAL_100; -+ pll_1000 = AR71XX_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ pll_10 = AR724X_PLL_VAL_10; -+ pll_100 = AR724X_PLL_VAL_100; -+ pll_1000 = AR724X_PLL_VAL_1000; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ pll_10 = AR91XX_PLL_VAL_10; -+ pll_100 = AR91XX_PLL_VAL_100; -+ pll_1000 = AR91XX_PLL_VAL_1000; -+ break; -+ default: -+ BUG(); -+ } -+ -+ if (!pll_data->pll_10) -+ pll_data->pll_10 = pll_10; -+ -+ if (!pll_data->pll_100) -+ pll_data->pll_100 = pll_100; -+ -+ if (!pll_data->pll_1000) -+ pll_data->pll_1000 = pll_1000; -+} -+ -+static int ar71xx_eth_instance __initdata; -+void __init ar71xx_add_device_eth(unsigned int id) -+{ -+ struct platform_device *pdev; -+ struct ag71xx_platform_data *pdata; -+ -+ ar71xx_init_eth_pll_data(id); -+ -+ switch (id) { -+ case 0: -+ switch (ar71xx_eth0_data.phy_if_mode) { -+ case PHY_INTERFACE_MODE_MII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII; -+ break; -+ case PHY_INTERFACE_MODE_GMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII; -+ break; -+ case PHY_INTERFACE_MODE_RMII: -+ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid PHY interface mode " -+ "for eth0\n"); -+ return; -+ } -+ pdev = &ar71xx_eth0_device; -+ break; -+ case 1: -+ switch (ar71xx_eth1_data.phy_if_mode) { -+ case PHY_INTERFACE_MODE_RMII: -+ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII; -+ break; -+ case PHY_INTERFACE_MODE_RGMII: -+ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid PHY interface mode " -+ "for eth1\n"); -+ return; -+ } -+ pdev = &ar71xx_eth1_device; -+ break; -+ default: -+ printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); -+ return; -+ } -+ -+ pdata = pdev->dev.platform_data; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 -+ : ar71xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar71xx_set_pll_ge1 -+ : ar71xx_set_pll_ge0; -+ break; -+ -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 -+ : ar71xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar71xx_set_pll_ge1 -+ : ar71xx_set_pll_ge0; -+ pdata->has_gbit = 1; -+ break; -+ -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; -+ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; -+ /* fall through */ -+ case AR71XX_SOC_AR7240: -+ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 -+ : ar724x_ddr_flush_ge0; -+ pdata->set_pll = id ? ar724x_set_pll_ge1 -+ : ar724x_set_pll_ge0; -+ pdata->is_ar724x = 1; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 -+ : ar91xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar91xx_set_pll_ge1 -+ : ar91xx_set_pll_ge0; -+ pdata->is_ar91xx = 1; -+ break; -+ -+ case AR71XX_SOC_AR9132: -+ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 -+ : ar91xx_ddr_flush_ge0; -+ pdata->set_pll = id ? ar91xx_set_pll_ge1 -+ : ar91xx_set_pll_ge0; -+ pdata->is_ar91xx = 1; -+ pdata->has_gbit = 1; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ switch (pdata->phy_if_mode) { -+ case PHY_INTERFACE_MODE_GMII: -+ case PHY_INTERFACE_MODE_RGMII: -+ if (!pdata->has_gbit) { -+ printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", -+ id); -+ return; -+ } -+ /* fallthrough */ -+ default: -+ break; -+ } -+ -+ if (is_valid_ether_addr(ar71xx_mac_base)) { -+ memcpy(pdata->mac_addr, ar71xx_mac_base, ETH_ALEN); -+ pdata->mac_addr[5] += ar71xx_eth_instance; -+ } else { -+ random_ether_addr(pdata->mac_addr); -+ printk(KERN_DEBUG -+ "ar71xx: using random MAC address for eth%d\n", -+ ar71xx_eth_instance); -+ } -+ -+ if (pdata->mii_bus_dev == NULL) -+ pdata->mii_bus_dev = &ar71xx_mdio_device.dev; -+ -+ /* Reset the device */ -+ ar71xx_device_stop(pdata->reset_bit); -+ mdelay(100); -+ -+ ar71xx_device_start(pdata->reset_bit); -+ mdelay(100); -+ -+ platform_device_register(pdev); -+ ar71xx_eth_instance++; -+} -+ -+static struct resource ar71xx_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ar71xx_spi_device = { -+ .name = "ar71xx-spi", -+ .id = -1, -+ .resource = ar71xx_spi_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_spi_resources), -+}; -+ -+void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, -+ struct spi_board_info const *info, -+ unsigned n) -+{ -+ spi_register_board_info(info, n); -+ ar71xx_spi_device.dev.platform_data = pdata; -+ platform_device_register(&ar71xx_spi_device); -+} -+ -+void __init ar71xx_add_device_wdt(void) -+{ -+ platform_device_register_simple("ar71xx-wdt", -1, NULL, 0); -+} -+ -+void __init ar71xx_set_mac_base(unsigned char *mac) -+{ -+ memcpy(ar71xx_mac_base, mac, ETH_ALEN); -+} -+ -+void __init ar71xx_parse_mac_addr(char *mac_str) -+{ -+ u8 tmp[ETH_ALEN]; -+ int t; -+ -+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); -+ -+ if (t != ETH_ALEN) -+ t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", -+ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); -+ -+ if (t == ETH_ALEN) -+ ar71xx_set_mac_base(tmp); -+ else -+ printk(KERN_DEBUG "ar71xx: failed to parse mac address " -+ "\"%s\"\n", mac_str); -+} -+ -+static int __init ar71xx_ethaddr_setup(char *str) -+{ -+ ar71xx_parse_mac_addr(str); -+ return 1; -+} -+__setup("ethaddr=", ar71xx_ethaddr_setup); -+ -+static int __init ar71xx_kmac_setup(char *str) -+{ -+ ar71xx_parse_mac_addr(str); -+ return 1; -+} -+__setup("kmac=", ar71xx_kmac_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/devices.h linux-2.6.35.7/arch/mips/ar71xx/devices.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/devices.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/devices.h 2010-10-14 20:27:56.504463432 +0200 -@@ -0,0 +1,48 @@ -+/* -+ * Atheros AR71xx SoC device definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR71XX_DEVICES_H -+#define __AR71XX_DEVICES_H -+ -+#include -+ -+struct platform_device; -+ -+void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, -+ struct spi_board_info const *info, -+ unsigned n) __init; -+ -+void ar71xx_set_mac_base(unsigned char *mac) __init; -+void ar71xx_parse_mac_addr(char *mac_str) __init; -+ -+struct ar71xx_eth_pll_data { -+ u32 pll_10; -+ u32 pll_100; -+ u32 pll_1000; -+}; -+ -+extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; -+extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; -+ -+extern struct ag71xx_platform_data ar71xx_eth0_data; -+extern struct ag71xx_platform_data ar71xx_eth1_data; -+extern struct platform_device ar71xx_eth0_device; -+extern struct platform_device ar71xx_eth1_device; -+void ar71xx_add_device_eth(unsigned int id) __init; -+ -+extern struct platform_device ar71xx_mdio_device; -+void ar71xx_add_device_mdio(u32 phy_mask) __init; -+ -+void ar71xx_add_device_uart(void) __init; -+ -+void ar71xx_add_device_wdt(void) __init; -+ -+#endif /* __AR71XX_DEVICES_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-leds-gpio.c linux-2.6.35.7/arch/mips/ar71xx/dev-leds-gpio.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-leds-gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-leds-gpio.c 2010-10-14 20:27:56.545601257 +0200 -@@ -0,0 +1,57 @@ -+/* -+ * Atheros AR71xx GPIO LED device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "dev-leds-gpio.h" -+ -+void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds, -+ struct gpio_led *leds) -+{ -+ struct platform_device *pdev; -+ struct gpio_led_platform_data pdata; -+ struct gpio_led *p; -+ int err; -+ -+ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); -+ if (!p) -+ return; -+ -+ memcpy(p, leds, num_leds * sizeof(*p)); -+ -+ pdev = platform_device_alloc("leds-gpio", id); -+ if (!pdev) -+ goto err_free_leds; -+ -+ memset(&pdata, 0, sizeof(pdata)); -+ pdata.num_leds = num_leds; -+ pdata.leds = p; -+ -+ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); -+ if (err) -+ goto err_put_pdev; -+ -+ err = platform_device_add(pdev); -+ if (err) -+ goto err_put_pdev; -+ -+ return; -+ -+err_put_pdev: -+ platform_device_put(pdev); -+ -+err_free_leds: -+ kfree(p); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-leds-gpio.h linux-2.6.35.7/arch/mips/ar71xx/dev-leds-gpio.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-leds-gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-leds-gpio.h 2010-10-14 20:27:56.595814317 +0200 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros AR71xx GPIO LED device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_LEDS_GPIO_H -+#define _AR71XX_DEV_LEDS_GPIO_H -+ -+#include -+ -+void ar71xx_add_device_leds_gpio(int id, -+ unsigned num_leds, -+ struct gpio_led *leds) __init; -+ -+#endif /* _AR71XX_DEV_LEDS_GPIO_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-m25p80.c linux-2.6.35.7/arch/mips/ar71xx/dev-m25p80.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-m25p80.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-m25p80.c 2010-10-14 20:27:56.645623230 +0200 -@@ -0,0 +1,30 @@ -+/* -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "devices.h" -+#include "dev-m25p80.h" -+ -+static struct spi_board_info ar71xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ } -+}; -+ -+void __init ar71xx_add_device_m25p80(struct flash_platform_data *pdata) -+{ -+ ar71xx_spi_info[0].platform_data = pdata; -+ ar71xx_add_device_spi(NULL, ar71xx_spi_info, -+ ARRAY_SIZE(ar71xx_spi_info)); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-m25p80.h linux-2.6.35.7/arch/mips/ar71xx/dev-m25p80.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-m25p80.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-m25p80.h 2010-10-14 20:27:56.695412366 +0200 -@@ -0,0 +1,16 @@ -+/* -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_M25P80_H -+#define _AR71XX_DEV_M25P80_H -+ -+#include -+ -+void ar71xx_add_device_m25p80(struct flash_platform_data *pdata) __init; -+ -+#endif /* _AR71XX_DEV_M25P80_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-pb42-pci.c linux-2.6.35.7/arch/mips/ar71xx/dev-pb42-pci.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-pb42-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-pb42-pci.c 2010-10-14 20:27:56.745266514 +0200 -@@ -0,0 +1,40 @@ -+/* -+ * Atheros PB42 reference board PCI initialization -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-pb42-pci.h" -+ -+static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 2, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ } -+}; -+ -+void __init pb42_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-pb42-pci.h linux-2.6.35.7/arch/mips/ar71xx/dev-pb42-pci.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-pb42-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-pb42-pci.h 2010-10-14 20:27:56.795082429 +0200 -@@ -0,0 +1,21 @@ -+/* -+ * Atheros PB42 reference board PCI initialization -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_PB42_PCI_H -+#define _AR71XX_DEV_PB42_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_PB42_PCI) -+void pb42_pci_init(void) __init; -+#else -+static inline void pb42_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_PB42_PCI_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-pb9x-pci.c linux-2.6.35.7/arch/mips/ar71xx/dev-pb9x-pci.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-pb9x-pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-pb9x-pci.c 2010-10-14 20:27:56.844918541 +0200 -@@ -0,0 +1,33 @@ -+/* -+ * Atheros PB9x reference board PCI initialization -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+#include -+ -+#include "dev-pb9x-pci.h" -+ -+static struct ar71xx_pci_irq pb9x_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ } -+}; -+ -+void __init pb9x_pci_init(void) -+{ -+ ar71xx_pci_init(ARRAY_SIZE(pb9x_pci_irqs), pb9x_pci_irqs); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-pb9x-pci.h linux-2.6.35.7/arch/mips/ar71xx/dev-pb9x-pci.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-pb9x-pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-pb9x-pci.h 2010-10-14 20:27:56.894720777 +0200 -@@ -0,0 +1,22 @@ -+/* -+ * Atheros PB9x reference board PCI initialization -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_PB9X_PCI_H -+#define _AR71XX_DEV_PB9X_PCI_H -+ -+#if defined(CONFIG_AR71XX_DEV_PB9X_PCI) -+void pb9x_pci_init(void) __init; -+#else -+static inline void pb9x_pci_init(void) { } -+#endif -+ -+#endif /* _AR71XX_DEV_PB9X_PCI_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-usb.c linux-2.6.35.7/arch/mips/ar71xx/dev-usb.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-usb.c 2010-10-14 20:27:56.944533864 +0200 -@@ -0,0 +1,181 @@ -+/* -+ * Atheros AR71xx USB host device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "dev-usb.h" -+ -+/* -+ * OHCI (USB full speed host controller) -+ */ -+static struct resource ar71xx_ohci_resources[] = { -+ [0] = { -+ .start = AR71XX_OHCI_BASE, -+ .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_MISC_IRQ_OHCI, -+ .end = AR71XX_MISC_IRQ_OHCI, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static struct resource ar7240_ohci_resources[] = { -+ [0] = { -+ .start = AR7240_OHCI_BASE, -+ .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_CPU_IRQ_USB, -+ .end = AR71XX_CPU_IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32); -+static struct platform_device ar71xx_ohci_device = { -+ .name = "ar71xx-ohci", -+ .id = -1, -+ .resource = ar71xx_ohci_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), -+ .dev = { -+ .dma_mask = &ar71xx_ohci_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ }, -+}; -+ -+/* -+ * EHCI (USB full speed host controller) -+ */ -+static struct resource ar71xx_ehci_resources[] = { -+ [0] = { -+ .start = AR71XX_EHCI_BASE, -+ .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+ [1] = { -+ .start = AR71XX_CPU_IRQ_USB, -+ .end = AR71XX_CPU_IRQ_USB, -+ .flags = IORESOURCE_IRQ, -+ }, -+}; -+ -+static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32); -+static struct ar71xx_ehci_platform_data ar71xx_ehci_data; -+ -+static struct platform_device ar71xx_ehci_device = { -+ .name = "ar71xx-ehci", -+ .id = -1, -+ .resource = ar71xx_ehci_resources, -+ .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), -+ .dev = { -+ .dma_mask = &ar71xx_ehci_dmamask, -+ .coherent_dma_mask = DMA_BIT_MASK(32), -+ .platform_data = &ar71xx_ehci_data, -+ }, -+}; -+ -+#define AR71XX_USB_RESET_MASK \ -+ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \ -+ | RESET_MODULE_USB_OHCI_DLL) -+ -+#define AR7240_USB_RESET_MASK \ -+ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240) -+ -+static void __init ar71xx_usb_setup(void) -+{ -+ ar71xx_device_stop(AR71XX_USB_RESET_MASK); -+ mdelay(1000); -+ ar71xx_device_start(AR71XX_USB_RESET_MASK); -+ -+ /* Turning on the Buff and Desc swap bits */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000); -+ -+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00); -+ -+ mdelay(900); -+ -+ platform_device_register(&ar71xx_ohci_device); -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+static void __init ar7240_usb_setup(void) -+{ -+ ar71xx_device_stop(AR7240_USB_RESET_MASK); -+ mdelay(1000); -+ ar71xx_device_start(AR7240_USB_RESET_MASK); -+ -+ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ -+ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3); -+ -+ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { -+ ar71xx_ehci_data.is_ar91xx = 1; -+ ar71xx_ehci_device.resource = ar7240_ohci_resources; -+ ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); -+ platform_device_register(&ar71xx_ehci_device); -+ } else { -+ ar71xx_ohci_device.resource = ar7240_ohci_resources; -+ ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); -+ platform_device_register(&ar71xx_ohci_device); -+ } -+} -+ -+static void __init ar91xx_usb_setup(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_USB_HOST); -+ mdelay(10); -+ -+ ar71xx_device_start(RESET_MODULE_USB_PHY); -+ mdelay(10); -+ -+ ar71xx_ehci_data.is_ar91xx = 1; -+ platform_device_register(&ar71xx_ehci_device); -+} -+ -+void __init ar71xx_add_device_usb(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar7240_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_usb_setup(); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar91xx_usb_setup(); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/dev-usb.h linux-2.6.35.7/arch/mips/ar71xx/dev-usb.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/dev-usb.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/dev-usb.h 2010-10-14 20:27:56.994353425 +0200 -@@ -0,0 +1,17 @@ -+/* -+ * Atheros AR71xx USB host device support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_DEV_USB_H -+#define _AR71XX_DEV_USB_H -+ -+void ar71xx_add_device_usb(void) __init; -+ -+#endif /* _AR71XX_DEV_USB_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/early_printk.c linux-2.6.35.7/arch/mips/ar71xx/early_printk.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/early_printk.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/early_printk.c 2010-10-14 20:27:57.044356938 +0200 -@@ -0,0 +1,30 @@ -+/* -+ * Atheros AR71xx SoC early printk support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+ -+#define UART_READ(r) \ -+ __raw_readl((void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4 * (r))) -+ -+#define UART_WRITE(r, v) \ -+ __raw_writel((v), (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4*(r))) -+ -+void prom_putchar(unsigned char ch) -+{ -+ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); -+ UART_WRITE(UART_TX, ch); -+ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); -+} -+ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/gpio.c linux-2.6.35.7/arch/mips/ar71xx/gpio.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/gpio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/gpio.c 2010-10-14 20:27:57.084356695 +0200 -@@ -0,0 +1,182 @@ -+/* -+ * Atheros AR71xx SoC GPIO API support -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+static DEFINE_SPINLOCK(ar71xx_gpio_lock); -+ -+unsigned long ar71xx_gpio_count; -+EXPORT_SYMBOL(ar71xx_gpio_count); -+ -+void __ar71xx_gpio_set_value(unsigned gpio, int value) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ -+ if (value) -+ __raw_writel(1 << gpio, base + GPIO_REG_SET); -+ else -+ __raw_writel(1 << gpio, base + GPIO_REG_CLEAR); -+} -+EXPORT_SYMBOL(__ar71xx_gpio_set_value); -+ -+int __ar71xx_gpio_get_value(unsigned gpio) -+{ -+ return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1; -+} -+EXPORT_SYMBOL(__ar71xx_gpio_get_value); -+ -+static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset) -+{ -+ return __ar71xx_gpio_get_value(offset); -+} -+ -+static void ar71xx_gpio_set_value(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ __ar71xx_gpio_set_value(offset, value); -+} -+ -+static int ar71xx_gpio_direction_input(struct gpio_chip *chip, -+ unsigned offset) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset), -+ base + GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static int ar71xx_gpio_direction_output(struct gpio_chip *chip, -+ unsigned offset, int value) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ if (value) -+ __raw_writel(1 << offset, base + GPIO_REG_SET); -+ else -+ __raw_writel(1 << offset, base + GPIO_REG_CLEAR); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset), -+ base + GPIO_REG_OE); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+ -+ return 0; -+} -+ -+static struct gpio_chip ar71xx_gpio_chip = { -+ .label = "ar71xx", -+ .get = ar71xx_gpio_get_value, -+ .set = ar71xx_gpio_set_value, -+ .direction_input = ar71xx_gpio_direction_input, -+ .direction_output = ar71xx_gpio_direction_output, -+ .base = 0, -+ .ngpio = AR71XX_GPIO_COUNT, -+}; -+ -+void ar71xx_gpio_function_enable(u32 mask) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+ -+void ar71xx_gpio_function_disable(u32 mask) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+ -+void ar71xx_gpio_function_setup(u32 set, u32 clear) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ar71xx_gpio_lock, flags); -+ -+ __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set, -+ base + GPIO_REG_FUNC); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_FUNC); -+ -+ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); -+} -+EXPORT_SYMBOL(ar71xx_gpio_function_setup); -+ -+void __init ar71xx_gpio_init(void) -+{ -+ int err; -+ -+ if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, -+ "AR71xx GPIO controller")) -+ panic("cannot allocate AR71xx GPIO registers page"); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT; -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT; -+ break; -+ -+ default: -+ BUG(); -+ } -+ -+ err = gpiochip_add(&ar71xx_gpio_chip); -+ if (err) -+ panic("cannot add AR71xx GPIO chip, error=%d", err); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/irq.c linux-2.6.35.7/arch/mips/ar71xx/irq.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/irq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/irq.c 2010-10-14 20:27:57.135484452 +0200 -@@ -0,0 +1,295 @@ -+/* -+ * Atheros AR71xx SoC specific interrupt handling -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+static int ip2_flush_reg; -+ -+static void ar71xx_gpio_irq_dispatch(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + GPIO_REG_INT_PENDING) & -+ __raw_readl(base + GPIO_REG_INT_ENABLE); -+ -+ if (pending) -+ do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1); -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_gpio_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ irq -= AR71XX_GPIO_IRQ_BASE; -+ -+ t = __raw_readl(base + GPIO_REG_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); -+} -+ -+static void ar71xx_gpio_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; -+ -+ irq -= AR71XX_GPIO_IRQ_BASE; -+ -+ t = __raw_readl(base + GPIO_REG_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); -+} -+ -+#if 0 -+static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) -+{ -+ /* TODO: implement */ -+ return 0; -+} -+#else -+#define ar71xx_gpio_irq_set_type NULL -+#endif -+ -+static struct irq_chip ar71xx_gpio_irq_chip = { -+ .name = "AR71XX GPIO", -+ .unmask = ar71xx_gpio_irq_unmask, -+ .mask = ar71xx_gpio_irq_mask, -+ .mask_ack = ar71xx_gpio_irq_mask, -+ .set_type = ar71xx_gpio_irq_set_type, -+}; -+ -+static struct irqaction ar71xx_gpio_irqaction = { -+ .handler = no_action, -+ .name = "cascade [AR71XX GPIO]", -+}; -+ -+#define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED) -+#define GPIO_INT_ALL 0xffff -+ -+static void __init ar71xx_gpio_irq_init(void) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ int i; -+ -+ __raw_writel(0, base + GPIO_REG_INT_ENABLE); -+ __raw_writel(0, base + GPIO_REG_INT_PENDING); -+ -+ /* setup type of all GPIO interrupts to level sensitive */ -+ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE); -+ -+ /* setup polarity of all GPIO interrupts to active high */ -+ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY); -+ -+ for (i = AR71XX_GPIO_IRQ_BASE; -+ i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) { -+ irq_desc[i].status = GPIO_IRQ_INIT_STATUS; -+ set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip, -+ handle_level_irq); -+ } -+ -+ setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction); -+} -+ -+static void ar71xx_misc_irq_dispatch(void) -+{ -+ u32 pending; -+ -+ pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) -+ & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ if (pending & MISC_INT_UART) -+ do_IRQ(AR71XX_MISC_IRQ_UART); -+ -+ else if (pending & MISC_INT_DMA) -+ do_IRQ(AR71XX_MISC_IRQ_DMA); -+ -+ else if (pending & MISC_INT_PERFC) -+ do_IRQ(AR71XX_MISC_IRQ_PERFC); -+ -+ else if (pending & MISC_INT_TIMER) -+ do_IRQ(AR71XX_MISC_IRQ_TIMER); -+ -+ else if (pending & MISC_INT_OHCI) -+ do_IRQ(AR71XX_MISC_IRQ_OHCI); -+ -+ else if (pending & MISC_INT_ERROR) -+ do_IRQ(AR71XX_MISC_IRQ_ERROR); -+ -+ else if (pending & MISC_INT_GPIO) -+ ar71xx_gpio_irq_dispatch(); -+ -+ else if (pending & MISC_INT_WDOG) -+ do_IRQ(AR71XX_MISC_IRQ_WDOG); -+ -+ else -+ spurious_interrupt(); -+} -+ -+static void ar71xx_misc_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+} -+ -+static void ar71xx_misc_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+} -+ -+static void ar724x_misc_irq_ack(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; -+ -+ irq -= AR71XX_MISC_IRQ_BASE; -+ -+ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); -+} -+ -+static struct irq_chip ar71xx_misc_irq_chip = { -+ .name = "AR71XX MISC", -+ .unmask = ar71xx_misc_irq_unmask, -+ .mask = ar71xx_misc_irq_mask, -+}; -+ -+static struct irqaction ar71xx_misc_irqaction = { -+ .handler = no_action, -+ .name = "cascade [AR71XX MISC]", -+}; -+ -+static void __init ar71xx_misc_irq_init(void) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ int i; -+ -+ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack; -+ break; -+ default: -+ ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; -+ break; -+ } -+ -+ for (i = AR71XX_MISC_IRQ_BASE; -+ i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip, -+ handle_level_irq); -+ } -+ -+ setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction); -+} -+ -+asmlinkage void plat_irq_dispatch(void) -+{ -+ unsigned long pending; -+ -+ pending = read_c0_status() & read_c0_cause() & ST0_IM; -+ -+ if (pending & STATUSF_IP7) -+ do_IRQ(AR71XX_CPU_IRQ_TIMER); -+ -+ else if (pending & STATUSF_IP2) { -+ /* -+ * This IRQ is meant for a PCI device. Drivers for PCI devices -+ * typically allocate coherent DMA memory for the descriptor -+ * ring, however the DMA controller may still have some -+ * unsynchronized data in the FIFO. -+ * Issue a flush here to ensure that the driver sees the update. -+ */ -+ ar71xx_ddr_flush(ip2_flush_reg); -+ do_IRQ(AR71XX_CPU_IRQ_IP2); -+ } -+ -+ else if (pending & STATUSF_IP4) -+ do_IRQ(AR71XX_CPU_IRQ_GE0); -+ -+ else if (pending & STATUSF_IP5) -+ do_IRQ(AR71XX_CPU_IRQ_GE1); -+ -+ else if (pending & STATUSF_IP3) -+ do_IRQ(AR71XX_CPU_IRQ_USB); -+ -+ else if (pending & STATUSF_IP6) -+ ar71xx_misc_irq_dispatch(); -+ -+ else -+ spurious_interrupt(); -+} -+ -+void __init arch_init_irq(void) -+{ -+ switch(ar71xx_soc) { -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; -+ break; -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC; -+ break; -+ default: -+ ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; -+ break; -+ } -+ mips_cpu_irq_init(); -+ -+ ar71xx_misc_irq_init(); -+ -+ cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC; -+ -+ ar71xx_gpio_irq_init(); -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/Kconfig linux-2.6.35.7/arch/mips/ar71xx/Kconfig ---- linux-2.6.35.7.orig/arch/mips/ar71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/Kconfig 2010-10-14 20:27:57.185337757 +0200 -@@ -0,0 +1,264 @@ -+if ATHEROS_AR71XX -+ -+menu "Atheros AR71xx machine selection" -+ -+config AR71XX_MACH_AP81 -+ bool "Atheros AP81 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AP83 -+ bool "Atheros AP83 board support" -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_DIR_600_A1 -+ bool "D-Link DIR-600 rev. A1 support" -+ select AR71XX_DEV_AP91_ETH -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_DIR_615_C1 -+ bool "D-Link DIR-615 rev. C1 support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_DIR_825_B1 -+ bool "D-Link DIR-825 rev. B1 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_PB42 -+ bool "Atheros PB42 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ default n -+ -+config AR71XX_MACH_PB44 -+ bool "Atheros PB44 board support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_PB92 -+ bool "Atheros PB92 board support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB9X_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_AW_NR580 -+ bool "AzureWave AW-NR580 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_WZR_HP_G300NH -+ bool "Buffalo WZR-HP-G300NH board support" -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default y -+ -+config AR71XX_MACH_WP543 -+ bool "Compex WP543/WPJ543 board support" -+ select MYLOADER -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WRT160NL -+ bool "Linksys WRT160NL board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_WRT400N -+ bool "Linksys WRT400N board support" -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_RB4XX -+ bool "MikroTik RouterBOARD 4xx series support" -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_RB750 -+ bool "MikroTik RouterBOARD 750 support" -+ select AR71XX_DEV_AP91_ETH -+ default n -+ -+config AR71XX_MACH_WNDR3700 -+ bool "NETGEAR WNDR3700 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP94_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_WNR2000 -+ bool "NETGEAR WNR2000 board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_MZK_W04NU -+ bool "Planex MZK-W04NU board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_MZK_W300NH -+ bool "Planex MZK-W300NH board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_NBG460N -+ bool "Zyxel NBG460N/550N/550NH board support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR741ND -+ bool "TP-LINK TL-WR741ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_ETH -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR841N_V1 -+ bool "TP-LINK TL-WR841N v1 support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_DSA -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR941ND -+ bool "TP-LINK TL-WR941ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_DSA -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ default n -+ -+config AR71XX_MACH_TL_WR1043ND -+ bool "TP-LINK TL-WR1043ND support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_USB -+ default n -+ -+config AR71XX_MACH_TEW_632BRP -+ bool "TRENDnet TEW-632BRP support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AR913X_WMAC -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_NVRAM -+ default n -+ -+config AR71XX_MACH_UBNT -+ bool "Ubiquiti AR71xx based boards support" -+ select AR71XX_DEV_M25P80 -+ select AR71XX_DEV_AP91_PCI if PCI -+ select AR71XX_DEV_GPIO_BUTTONS -+ select AR71XX_DEV_LEDS_GPIO -+ select AR71XX_DEV_PB42_PCI if PCI -+ select AR71XX_DEV_USB -+ default n -+ -+endmenu -+ -+config AR71XX_DEV_M25P80 -+ def_bool n -+ -+config AR71XX_DEV_AP91_PCI -+ def_bool n -+ -+config AR71XX_DEV_AP91_ETH -+ def_bool n -+ -+config AR71XX_DEV_AP94_PCI -+ def_bool n -+ -+config AR71XX_DEV_AR913X_WMAC -+ def_bool n -+ -+config AR71XX_DEV_DSA -+ def_bool n -+ -+config AR71XX_DEV_GPIO_BUTTONS -+ def_bool n -+ -+config AR71XX_DEV_LEDS_GPIO -+ def_bool n -+ -+config AR71XX_DEV_PB42_PCI -+ def_bool n -+ -+config AR71XX_DEV_PB9X_PCI -+ def_bool n -+ -+config AR71XX_DEV_USB -+ def_bool n -+ -+config AR71XX_NVRAM -+ def_bool n -+ -+endif -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-ap81.c linux-2.6.35.7/arch/mips/ar71xx/mach-ap81.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-ap81.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-ap81.c 2010-10-14 20:27:57.235141599 +0200 -@@ -0,0 +1,140 @@ -+/* -+ * Atheros AP81 board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * Copyright (C) 2009 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP81_GPIO_LED_STATUS 1 -+#define AP81_GPIO_LED_AOSS 3 -+#define AP81_GPIO_LED_WLAN 6 -+#define AP81_GPIO_LED_POWER 14 -+ -+#define AP81_GPIO_BTN_SW4 12 -+#define AP81_GPIO_BTN_SW1 21 -+ -+#define AP81_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap81_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x500000, -+ } , { -+ .name = "uImage", -+ .offset = 0x550000, -+ .size = 0x100000, -+ } , { -+ .name = "ART", -+ .offset = 0x650000, -+ .size = 0x1b0000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data ap81_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap81_partitions, -+ .nr_parts = ARRAY_SIZE(ap81_partitions), -+#endif -+}; -+ -+static struct gpio_led ap81_leds_gpio[] __initdata = { -+ { -+ .name = "ap81:green:status", -+ .gpio = AP81_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "ap81:amber:aoss", -+ .gpio = AP81_GPIO_LED_AOSS, -+ .active_low = 1, -+ }, { -+ .name = "ap81:green:wlan", -+ .gpio = AP81_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "ap81:green:power", -+ .gpio = AP81_GPIO_LED_POWER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button ap81_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw1", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = AP81_GPIO_BTN_SW1, -+ .active_low = 1, -+ } , { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = AP81_GPIO_BTN_SW4, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ap81_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&ap81_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), -+ ap81_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AP81_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ap81_gpio_buttons), -+ ap81_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP81, "AP81", "Atheros AP81", ap81_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-ap83.c linux-2.6.35.7/arch/mips/ar71xx/mach-ap83.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-ap83.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-ap83.c 2010-10-14 20:27:57.284350521 +0200 -@@ -0,0 +1,266 @@ -+/* -+ * Atheros AP83 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define AP83_GPIO_LED_WLAN 6 -+#define AP83_GPIO_LED_POWER 14 -+#define AP83_GPIO_LED_JUMPSTART 15 -+#define AP83_GPIO_BTN_JUMPSTART 12 -+#define AP83_GPIO_BTN_RESET 21 -+ -+#define AP83_050_GPIO_VSC7385_CS 1 -+#define AP83_050_GPIO_VSC7385_MISO 3 -+#define AP83_050_GPIO_VSC7385_MOSI 16 -+#define AP83_050_GPIO_VSC7385_SCK 17 -+ -+#define AP83_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition ap83_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x060000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1a0000, -+ .size = 0x650000, -+ } , { -+ .name = "art", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x060000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct ar91xx_flash_platform_data ap83_flash_data = { -+ .width = 2, -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = ap83_flash_partitions, -+ .nr_parts = ARRAY_SIZE(ap83_flash_partitions), -+#endif -+}; -+ -+static struct resource ap83_flash_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ap83_flash_device = { -+ .name = "ar91xx-flash", -+ .id = -1, -+ .resource = ap83_flash_resources, -+ .num_resources = ARRAY_SIZE(ap83_flash_resources), -+ .dev = { -+ .platform_data = &ap83_flash_data, -+ } -+}; -+ -+static struct gpio_led ap83_leds_gpio[] __initdata = { -+ { -+ .name = "ap83:green:jumpstart", -+ .gpio = AP83_GPIO_LED_JUMPSTART, -+ .active_low = 0, -+ }, { -+ .name = "ap83:green:power", -+ .gpio = AP83_GPIO_LED_POWER, -+ .active_low = 0, -+ }, { -+ .name = "ap83:green:wlan", -+ .gpio = AP83_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_button ap83_gpio_buttons[] __initdata = { -+ { -+ .desc = "soft_reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = AP83_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "jumpstart", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = AP83_GPIO_BTN_JUMPSTART, -+ .active_low = 1, -+ } -+}; -+ -+static struct resource ap83_040_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device ap83_040_spi_device = { -+ .name = "ap83-spi", -+ .id = 0, -+ .resource = ap83_040_spi_resources, -+ .num_resources = ARRAY_SIZE(ap83_040_spi_resources), -+}; -+ -+static struct spi_gpio_platform_data ap83_050_spi_data = { -+ .miso = AP83_050_GPIO_VSC7385_MISO, -+ .mosi = AP83_050_GPIO_VSC7385_MOSI, -+ .sck = AP83_050_GPIO_VSC7385_SCK, -+ .num_chipselect = 1, -+}; -+ -+static struct platform_device ap83_050_spi_device = { -+ .name = "spi_gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &ap83_050_spi_data, -+ } -+}; -+ -+static void ap83_vsc7385_reset(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+ udelay(10); -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data ap83_vsc7385_data = { -+ .reset = ap83_vsc7385_reset, -+ .ucode_name = "vsc7385_ucode_ap83.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 0, -+ .clk_sel = 3, -+ }, -+}; -+ -+static struct spi_board_info ap83_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &ap83_vsc7385_data, -+ .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, -+ } -+}; -+ -+static void __init ap83_generic_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(0xfffffffe); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = 0x1; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), -+ ap83_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AP83_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ap83_gpio_buttons), -+ ap83_gpio_buttons); -+ -+ ar71xx_add_device_usb(); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ platform_device_register(&ap83_flash_device); -+ -+ spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); -+} -+ -+static void __init ap83_040_setup(void) -+{ -+ ap83_flash_data.is_shared=1; -+ ap83_generic_setup(); -+ platform_device_register(&ap83_040_spi_device); -+} -+ -+static void __init ap83_050_setup(void) -+{ -+ ap83_generic_setup(); -+ platform_device_register(&ap83_050_spi_device); -+} -+ -+static void __init ap83_setup(void) -+{ -+ u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); -+ unsigned int board_version; -+ -+ board_version = (unsigned int)(board_id[0] - '0'); -+ board_version += ((unsigned int)(board_id[1] - '0')) * 10; -+ -+ switch (board_version) { -+ case 40: -+ ap83_040_setup(); -+ break; -+ case 50: -+ ap83_050_setup(); -+ break; -+ default: -+ printk(KERN_WARNING "AP83-%03u board is not yet supported\n", -+ board_version); -+ } -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-aw-nr580.c linux-2.6.35.7/arch/mips/ar71xx/mach-aw-nr580.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-aw-nr580.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-aw-nr580.c 2010-10-14 20:27:57.334787684 +0200 -@@ -0,0 +1,101 @@ -+/* -+ * AzureWave AW-NR580 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+ -+#define AW_NR580_GPIO_LED_READY_RED 0 -+#define AW_NR580_GPIO_LED_WLAN 1 -+#define AW_NR580_GPIO_LED_READY_GREEN 2 -+#define AW_NR580_GPIO_LED_WPS_GREEN 4 -+#define AW_NR580_GPIO_LED_WPS_AMBER 5 -+ -+#define AW_NR580_GPIO_BTN_WPS 3 -+#define AW_NR580_GPIO_BTN_RESET 11 -+ -+#define AW_NR580_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led aw_nr580_leds_gpio[] __initdata = { -+ { -+ .name = "aw-nr580:red:ready", -+ .gpio = AW_NR580_GPIO_LED_READY_RED, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:ready", -+ .gpio = AW_NR580_GPIO_LED_READY_GREEN, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:wps", -+ .gpio = AW_NR580_GPIO_LED_WPS_GREEN, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:amber:wps", -+ .gpio = AW_NR580_GPIO_LED_WPS_AMBER, -+ .active_low = 0, -+ }, { -+ .name = "aw-nr580:green:wlan", -+ .gpio = AW_NR580_GPIO_LED_WLAN, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button aw_nr580_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = AW_NR580_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = AW_NR580_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init aw_nr580_setup(void) -+{ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ pb42_pci_init(); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), -+ aw_nr580_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, AW_NR580_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(aw_nr580_gpio_buttons), -+ aw_nr580_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", -+ aw_nr580_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-dir-600-a1.c linux-2.6.35.7/arch/mips/ar71xx/mach-dir-600-a1.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-dir-600-a1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-dir-600-a1.c 2010-10-14 20:27:57.384602615 +0200 -@@ -0,0 +1,138 @@ -+/* -+ * D-Link DIR-600 rev. A1 board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-eth.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define DIR_600_A1_GPIO_LED_WPS 0 -+#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 -+#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 -+ -+#define DIR_600_A1_GPIO_BTN_RESET 8 -+#define DIR_600_A1_GPIO_BTN_WPS 12 -+ -+#define DIR_600_A1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR_600_A1_NVRAM_ADDR 0x1f030000 -+#define DIR_600_A1_NVRAM_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir_600_a1_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "nvram", -+ .offset = 0x030000, -+ .size = 0x010000, -+ }, { -+ .name = "kernel", -+ .offset = 0x040000, -+ .size = 0x0e0000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x120000, -+ .size = 0x2c0000, -+ }, { -+ .name = "mac", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x3a0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir_600_a1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir_600_a1_partitions, -+ .nr_parts = ARRAY_SIZE(dir_600_a1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { -+ { -+ .name = "dir-600-a1:green:power", -+ .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, -+ }, { -+ .name = "dir-600-a1:amber:power", -+ .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, -+ }, { -+ .name = "dir-600-a1:blue:wps", -+ .gpio = DIR_600_A1_GPIO_LED_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button dir_600_a1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR_600_A1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = DIR_600_A1_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init dir_600_a1_setup(void) -+{ -+ const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac_buff[6]; -+ u8 *mac = NULL; -+ -+ if (nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, -+ "lan_mac=", mac_buff) == 0) -+ mac = mac_buff; -+ -+ ar71xx_add_device_m25p80(&dir_600_a1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), -+ dir_600_a1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR_600_A1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir_600_a1_gpio_buttons), -+ dir_600_a1_gpio_buttons); -+ -+ ap91_eth_init(mac, NULL); -+ ap91_pci_init(ee, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", -+ dir_600_a1_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-dir-615-c1.c linux-2.6.35.7/arch/mips/ar71xx/mach-dir-615-c1.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-dir-615-c1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-dir-615-c1.c 2010-10-14 20:27:57.434406850 +0200 -@@ -0,0 +1,173 @@ -+/* -+ * D-Link DIR-615 rev C1 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ -+#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ -+#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ -+#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ -+ -+/* buttons may need refinement */ -+ -+#define DIR_615C1_GPIO_BTN_WPS 12 -+#define DIR_615C1_GPIO_BTN_RESET 21 -+ -+#define DIR_615C1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR_615C1_CONFIG_ADDR 0x1f020000 -+#define DIR_615C1_CONFIG_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir_615c1_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x020000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x030000, -+ .size = 0x0d0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x100000, -+ .size = 0x2f0000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x030000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir_615c1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir_615c1_partitions, -+ .nr_parts = ARRAY_SIZE(dir_615c1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir_615c1_leds_gpio[] __initdata = { -+ { -+ .name = "dir-615c1:orange:status", -+ .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:blue:wps", -+ .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wan", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wancpu", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:wlan", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:green:status", -+ .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "dir-615c1:orange:wan", -+ .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, -+ .active_low = 1, -+ } -+ -+}; -+ -+static struct gpio_button dir_615c1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR_615C1_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = DIR_615C1_GPIO_BTN_WPS, -+ } -+}; -+ -+#define DIR_615C1_LAN_PHYMASK BIT(0) -+#define DIR_615C1_WAN_PHYMASK BIT(4) -+#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ -+ DIR_615C1_WAN_PHYMASK)) -+ -+static void __init dir_615c1_setup(void) -+{ -+ const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ u8 *wlan_mac = NULL; -+ -+ if (nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, -+ "lan_mac=", mac) == 0) { -+ ar71xx_set_mac_base(mac); -+ wlan_mac = mac; -+ } -+ -+ ar71xx_add_device_mdio(DIR_615C1_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&dir_615c1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), -+ dir_615c1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR_615C1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir_615c1_gpio_buttons), -+ dir_615c1_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, wlan_mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", -+ dir_615c1_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-dir-825-b1.c linux-2.6.35.7/arch/mips/ar71xx/mach-dir-825-b1.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-dir-825-b1.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-dir-825-b1.c 2010-10-14 20:27:57.478101111 +0200 -@@ -0,0 +1,192 @@ -+/* -+ * D-Link DIR-825 rev. B1 board support -+ * -+ * Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o. -+ * -+ * based on mach-wndr3700.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define DIR825B1_GPIO_LED_BLUE_USB 0 -+#define DIR825B1_GPIO_LED_ORANGE_POWER 1 -+#define DIR825B1_GPIO_LED_BLUE_POWER 2 -+#define DIR825B1_GPIO_LED_BLUE_POWERSAVE 4 -+#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 -+#define DIR825B1_GPIO_LED_BLUE_PLANET 11 -+ -+#define DIR825B1_GPIO_BTN_RESET 3 -+#define DIR825B1_GPIO_BTN_POWERSAVE 8 -+ -+#define DIR825B1_GPIO_RTL8366_SDA 5 -+#define DIR825B1_GPIO_RTL8366_SCK 7 -+ -+#define DIR825B1_BUTTONS_POLL_INTERVAL 20 -+ -+#define DIR825B1_CAL_LOCATION_0 0x1f661000 -+#define DIR825B1_CAL_LOCATION_1 0x1f665000 -+ -+#define DIR825B1_MAC_LOCATION_0 0x2ffa81b8 -+#define DIR825B1_MAC_LOCATION_1 0x2ffa8370 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition dir825b1_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x040000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x610000, -+ } , { -+ .name = "caldata", -+ .offset = 0x660000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "unknown", -+ .offset = 0x670000, -+ .size = 0x190000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data dir825b1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = dir825b1_partitions, -+ .nr_parts = ARRAY_SIZE(dir825b1_partitions), -+#endif -+}; -+ -+static struct gpio_led dir825b1_leds_gpio[] __initdata = { -+ { -+ .name = "dir825b1:blue:usb", -+ .gpio = DIR825B1_GPIO_LED_BLUE_USB, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:orange:power", -+ .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:power", -+ .gpio = DIR825B1_GPIO_LED_BLUE_POWER, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:powersave", -+ .gpio = DIR825B1_GPIO_LED_BLUE_POWERSAVE, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:orange:planet", -+ .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, -+ .active_low = 1, -+ }, { -+ .name = "dir825b1:blue:planet", -+ .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button dir825b1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = DIR825B1_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "powersave", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = DIR825B1_GPIO_BTN_POWERSAVE, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366s_platform_data dir825b1_rtl8366s_data = { -+ .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, -+ .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device dir825b1_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &dir825b1_rtl8366s_data, -+ } -+}; -+ -+static void __init dir825b1_setup(void) -+{ -+ u8 mac[6], i; -+ -+ memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6); -+ for(i = 5; i >= 3; i--) -+ if(++mac[i] != 0x00) break; -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; -+ -+ ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&dir825b1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), -+ dir825b1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(dir825b1_gpio_buttons), -+ dir825b1_gpio_buttons); -+ -+ ar71xx_add_device_usb(); -+ -+ platform_device_register(&dir825b1_rtl8366s_device); -+ -+ ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), -+ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_0), -+ (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), -+ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_1)); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", -+ dir825b1_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-mzk-w04nu.c linux-2.6.35.7/arch/mips/ar71xx/mach-mzk-w04nu.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-mzk-w04nu.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-mzk-w04nu.c 2010-10-14 20:27:57.518101300 +0200 -@@ -0,0 +1,165 @@ -+/* -+ * Planex MZK-W04NU board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-m25p80.h" -+#include "dev-usb.h" -+ -+#define MZK_W04NU_GPIO_LED_USB 0 -+#define MZK_W04NU_GPIO_LED_STATUS 1 -+#define MZK_W04NU_GPIO_LED_WPS 3 -+#define MZK_W04NU_GPIO_LED_WLAN 6 -+#define MZK_W04NU_GPIO_LED_AP 15 -+#define MZK_W04NU_GPIO_LED_ROUTER 16 -+ -+#define MZK_W04NU_GPIO_BTN_APROUTER 5 -+#define MZK_W04NU_GPIO_BTN_WPS 12 -+#define MZK_W04NU_GPIO_BTN_RESET 21 -+ -+#define MZK_W04NU_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition mzk_w04nu_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x050000, -+ .size = 0x160000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1b0000, -+ .size = 0x630000, -+ } , { -+ .name = "art", -+ .offset = 0x7e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data mzk_w04nu_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = mzk_w04nu_partitions, -+ .nr_parts = ARRAY_SIZE(mzk_w04nu_partitions), -+#endif -+}; -+ -+static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { -+ { -+ .name = "mzk-w04nu:green:status", -+ .gpio = MZK_W04NU_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:blue:wps", -+ .gpio = MZK_W04NU_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:wlan", -+ .gpio = MZK_W04NU_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:usb", -+ .gpio = MZK_W04NU_GPIO_LED_USB, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:ap", -+ .gpio = MZK_W04NU_GPIO_LED_AP, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w04nu:green:router", -+ .gpio = MZK_W04NU_GPIO_LED_ROUTER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button mzk_w04nu_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "aprouter", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = MZK_W04NU_GPIO_BTN_APROUTER, -+ .active_low = 0, -+ } -+}; -+ -+#define MZK_W04NU_WAN_PHYMASK BIT(4) -+#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) -+ -+static void __init mzk_w04nu_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(MZK_W04NU_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&mzk_w04nu_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), -+ mzk_w04nu_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, MZK_W04NU_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(mzk_w04nu_gpio_buttons), -+ mzk_w04nu_gpio_buttons); -+ ar71xx_add_device_usb(); -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", -+ mzk_w04nu_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-mzk-w300nh.c linux-2.6.35.7/arch/mips/ar71xx/mach-mzk-w300nh.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-mzk-w300nh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-mzk-w300nh.c 2010-10-14 20:27:57.565601159 +0200 -@@ -0,0 +1,158 @@ -+/* -+ * Planex MZK-W300NH board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define MZK_W300NH_GPIO_LED_STATUS 1 -+#define MZK_W300NH_GPIO_LED_WPS 3 -+#define MZK_W300NH_GPIO_LED_WLAN 6 -+#define MZK_W300NH_GPIO_LED_AP 15 -+#define MZK_W300NH_GPIO_LED_ROUTER 16 -+ -+#define MZK_W300NH_GPIO_BTN_APROUTER 5 -+#define MZK_W300NH_GPIO_BTN_WPS 12 -+#define MZK_W300NH_GPIO_BTN_RESET 21 -+ -+#define MZK_W04NU_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition mzk_w300nh_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x050000, -+ .size = 0x160000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x1b0000, -+ .size = 0x630000, -+ } , { -+ .name = "art", -+ .offset = 0x7e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x050000, -+ .size = 0x790000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data mzk_w300nh_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = mzk_w300nh_partitions, -+ .nr_parts = ARRAY_SIZE(mzk_w300nh_partitions), -+#endif -+}; -+ -+static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { -+ { -+ .name = "mzk-w300nh:green:status", -+ .gpio = MZK_W300NH_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:blue:wps", -+ .gpio = MZK_W300NH_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:wlan", -+ .gpio = MZK_W300NH_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:ap", -+ .gpio = MZK_W300NH_GPIO_LED_AP, -+ .active_low = 1, -+ }, { -+ .name = "mzk-w300nh:green:router", -+ .gpio = MZK_W300NH_GPIO_LED_ROUTER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button mzk_w300nh_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_WPS, -+ .active_low = 1, -+ }, { -+ .desc = "aprouter", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = MZK_W300NH_GPIO_BTN_APROUTER, -+ .active_low = 0, -+ } -+}; -+ -+#define MZK_W300NH_WAN_PHYMASK BIT(4) -+#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) -+ -+static void __init mzk_w300nh_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ -+ ar71xx_add_device_mdio(MZK_W300NH_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&mzk_w300nh_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), -+ mzk_w300nh_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, MZK_W04NU_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(mzk_w300nh_gpio_buttons), -+ mzk_w300nh_gpio_buttons); -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", -+ mzk_w300nh_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-nbg460n.c linux-2.6.35.7/arch/mips/ar71xx/mach-nbg460n.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-nbg460n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-nbg460n.c 2010-10-14 20:27:57.617104398 +0200 -@@ -0,0 +1,222 @@ -+/* -+ * Zyxel NBG 460N/550N/550NH board support -+ * -+ * Copyright (C) 2010 Michael Kurz -+ * -+ * based on mach-tl-wr1043nd.c -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+/* LEDs */ -+#define NBG460N_GPIO_LED_WPS 3 -+#define NBG460N_GPIO_LED_WAN 6 -+#define NBG460N_GPIO_LED_POWER 14 -+#define NBG460N_GPIO_LED_WLAN 15 -+ -+/* Buttons */ -+#define NBG460N_GPIO_BTN_WPS 12 -+#define NBG460N_GPIO_BTN_RESET 21 -+#define NBG460N_BUTTONS_POLL_INTERVAL 20 -+ -+/* RTC chip PCF8563 I2C interface */ -+#define NBG460N_GPIO_PCF8563_SDA 8 -+#define NBG460N_GPIO_PCF8563_SCK 7 -+ -+/* Switch configuration I2C interface */ -+#define NBG460N_GPIO_RTL8366_SDA 16 -+#define NBG460N_GPIO_RTL8366_SCK 18 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition nbg460n_partitions[] = { -+ { -+ .name = "Bootbase", -+ .offset = 0, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "U-Boot Config", -+ .offset = 0x010000, -+ .size = 0x030000, -+ } , { -+ .name = "U-Boot", -+ .offset = 0x040000, -+ .size = 0x030000, -+ } , { -+ .name = "linux", -+ .offset = 0x070000, -+ .size = 0x0e0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x150000, -+ .size = 0x2a0000, -+ } , { -+ .name = "CalibData", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x070000, -+ .size = 0x380000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data nbg460n_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = nbg460n_partitions, -+ .nr_parts = ARRAY_SIZE(nbg460n_partitions), -+#endif -+}; -+ -+static struct gpio_led nbg460n_leds_gpio[] __initdata = { -+ { -+ .name = "nbg460n:green:power", -+ .gpio = NBG460N_GPIO_LED_POWER, -+ .active_low = 0, -+ .default_trigger = "default-on", -+ }, { -+ .name = "nbg460n:green:wps", -+ .gpio = NBG460N_GPIO_LED_WPS, -+ .active_low = 0, -+ }, { -+ .name = "nbg460n:green:wlan", -+ .gpio = NBG460N_GPIO_LED_WLAN, -+ .active_low = 0, -+ }, { -+ /* Not really for controlling the LED, -+ when set low the LED blinks uncontrollable */ -+ .name = "nbg460n:green:wan", -+ .gpio = NBG460N_GPIO_LED_WAN, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button nbg460n_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = NBG460N_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = NBG460N_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { -+ .sda_pin = NBG460N_GPIO_PCF8563_SDA, -+ .scl_pin = NBG460N_GPIO_PCF8563_SCK, -+ .udelay = 10, -+}; -+ -+static struct platform_device nbg460n_i2c_device = { -+ .name = "i2c-gpio", -+ .id = -1, -+ .num_resources = 0, -+ .resource = NULL, -+ .dev = { -+ .platform_data = &nbg460n_i2c_device_platdata, -+ }, -+}; -+ -+static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { -+ { -+ I2C_BOARD_INFO("pcf8563", 0x51), -+ }, -+}; -+ -+static void __devinit nbg460n_i2c_init(void) -+{ -+ /* The gpio interface */ -+ platform_device_register(&nbg460n_i2c_device); -+ /* I2C devices */ -+ i2c_register_board_info(0, nbg460n_i2c_devs, -+ ARRAY_SIZE(nbg460n_i2c_devs)); -+} -+ -+ -+static struct rtl8366s_platform_data nbg460n_rtl8366s_data = { -+ .gpio_sda = NBG460N_GPIO_RTL8366_SDA, -+ .gpio_sck = NBG460N_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device nbg460n_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &nbg460n_rtl8366s_data, -+ } -+}; -+ -+static void __init nbg460n_setup(void) -+{ -+ /* end of bootloader sector contains mac address*/ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); -+ /* last sector contains wlan calib data */ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ /* LAN Port */ -+ ar71xx_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ /* WAN Port */ -+ ar71xx_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ /* register the switch phy */ -+ platform_device_register(&nbg460n_rtl8366s_device); -+ -+ /* register flash */ -+ ar71xx_add_device_m25p80(&nbg460n_flash_data); -+ -+ ar913x_add_device_wmac(eeprom, mac); -+ -+ /* register RTC chip */ -+ nbg460n_i2c_init(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), -+ nbg460n_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, NBG460N_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(nbg460n_gpio_buttons), -+ nbg460n_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", nbg460n_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-pb42.c linux-2.6.35.7/arch/mips/ar71xx/mach-pb42.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-pb42.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-pb42.c 2010-10-14 20:27:57.665601166 +0200 -@@ -0,0 +1,71 @@ -+/* -+ * Atheros PB42 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-usb.h" -+ -+#define PB42_BUTTONS_POLL_INTERVAL 20 -+ -+#define PB42_GPIO_BTN_SW4 8 -+#define PB42_GPIO_BTN_SW5 3 -+ -+static struct gpio_button pb42_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = PB42_GPIO_BTN_SW4, -+ .active_low = 1, -+ } , { -+ .desc = "sw5", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = PB42_GPIO_BTN_SW5, -+ .active_low = 1, -+ } -+}; -+ -+#define PB42_WAN_PHYMASK BIT(20) -+#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) -+#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) -+ -+static void __init pb42_init(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(pb42_gpio_buttons), -+ pb42_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB42, "PB42", "Atheros PB42", pb42_init); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-pb44.c linux-2.6.35.7/arch/mips/ar71xx/mach-pb44.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-pb44.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-pb44.c 2010-10-14 20:27:57.725015448 +0200 -@@ -0,0 +1,207 @@ -+/* -+ * Atheros PB44 board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-pb42-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define PB44_PCF8757_VSC7395_CS 0 -+#define PB44_PCF8757_STEREO_CS 1 -+#define PB44_PCF8757_SLIC_CS0 2 -+#define PB44_PCF8757_SLIC_TEST 3 -+#define PB44_PCF8757_SLIC_INT0 4 -+#define PB44_PCF8757_SLIC_INT1 5 -+#define PB44_PCF8757_SW_RESET 6 -+#define PB44_PCF8757_SW_JUMP 8 -+#define PB44_PCF8757_LED_JUMP1 9 -+#define PB44_PCF8757_LED_JUMP2 10 -+#define PB44_PCF8757_TP24 11 -+#define PB44_PCF8757_TP25 12 -+#define PB44_PCF8757_TP26 13 -+#define PB44_PCF8757_TP27 14 -+#define PB44_PCF8757_TP28 15 -+ -+#define PB44_GPIO_I2C_SCL 0 -+#define PB44_GPIO_I2C_SDA 1 -+ -+#define PB44_GPIO_EXP_BASE 16 -+#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) -+#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_RESET) -+#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_JUMP) -+#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP1) -+#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP2) -+ -+static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { -+ .sda_pin = PB44_GPIO_I2C_SDA, -+ .scl_pin = PB44_GPIO_I2C_SCL, -+}; -+ -+static struct platform_device pb44_i2c_gpio_device = { -+ .name = "i2c-gpio", -+ .id = 0, -+ .dev = { -+ .platform_data = &pb44_i2c_gpio_data, -+ } -+}; -+ -+static struct pcf857x_platform_data pb44_pcf857x_data = { -+ .gpio_base = PB44_GPIO_EXP_BASE, -+}; -+ -+static struct i2c_board_info pb44_i2c_board_info[] __initdata = { -+ { -+ I2C_BOARD_INFO("pcf8575", 0x20), -+ .platform_data = &pb44_pcf857x_data, -+ }, -+}; -+ -+static struct gpio_led pb44_leds_gpio[] __initdata = { -+ { -+ .name = "pb44:amber:jump1", -+ .gpio = PB44_GPIO_LED_JUMP1, -+ .active_low = 1, -+ }, { -+ .name = "pb44:green:jump2", -+ .gpio = PB44_GPIO_LED_JUMP2, -+ .active_low = 1, -+ }, -+}; -+ -+static struct gpio_button pb44_gpio_buttons[] __initdata = { -+ { -+ .desc = "soft_reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = PB44_GPIO_SW_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "jumpstart", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = PB44_GPIO_SW_JUMP, -+ .active_low = 1, -+ } -+}; -+ -+static void pb44_vsc7395_reset(void) -+{ -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+ udelay(10); -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ mdelay(50); -+} -+ -+static struct vsc7385_platform_data pb44_vsc7395_data = { -+ .reset = pb44_vsc7395_reset, -+ .ucode_name = "vsc7395_ucode_pb44.bin", -+ .mac_cfg = { -+ .tx_ipg = 6, -+ .bit2 = 1, -+ .clk_sel = 0, -+ }, -+}; -+ -+static struct spi_board_info pb44_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ }, { -+ .bus_num = 0, -+ .chip_select = 1, -+ .max_speed_hz = 25000000, -+ .modalias = "spi-vsc7385", -+ .platform_data = &pb44_vsc7395_data, -+ .controller_data = (void *) PB44_GPIO_VSC7395_CS, -+ }, -+}; -+ -+static struct resource pb44_spi_resources[] = { -+ [0] = { -+ .start = AR71XX_SPI_BASE, -+ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct ar71xx_spi_platform_data pb44_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 2, -+}; -+ -+static struct platform_device pb44_spi_device = { -+ .name = "pb44-spi", -+ .id = -1, -+ .resource = pb44_spi_resources, -+ .num_resources = ARRAY_SIZE(pb44_spi_resources), -+ .dev = { -+ .platform_data = &pb44_spi_data, -+ }, -+}; -+ -+#define PB44_WAN_PHYMASK BIT(0) -+#define PB44_LAN_PHYMASK 0 -+#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) -+ -+static void __init pb44_init(void) -+{ -+ ar71xx_add_device_mdio(~PB44_MDIO_PHYMASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = PB44_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_pll_data.pll_1000 = 0x110000; -+ -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ pb42_pci_init(); -+ -+ i2c_register_board_info(0, pb44_i2c_board_info, -+ ARRAY_SIZE(pb44_i2c_board_info)); -+ -+ platform_device_register(&pb44_i2c_gpio_device); -+ -+ spi_register_board_info(pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); -+ platform_device_register(&pb44_spi_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), -+ pb44_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, 20, ARRAY_SIZE(pb44_gpio_buttons), -+ pb44_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB44, "PB44", "Atheros PB44", pb44_init); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-pb92.c linux-2.6.35.7/arch/mips/ar71xx/mach-pb92.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-pb92.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-pb92.c 2010-10-14 20:27:57.774807434 +0200 -@@ -0,0 +1,109 @@ -+/* -+ * Atheros PB92 board support -+ * -+ * Copyright (C) 2010 Felix Fietkau -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb9x-pci.h" -+#include "dev-usb.h" -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition pb92_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x2b0000, -+ } , { -+ .name = "uImage", -+ .offset = 0x300000, -+ .size = 0x0e0000, -+ } , { -+ .name = "ART", -+ .offset = 0x3e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data pb92_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = pb92_partitions, -+ .nr_parts = ARRAY_SIZE(pb92_partitions), -+#endif -+}; -+ -+ -+#define PB92_BUTTONS_POLL_INTERVAL 20 -+ -+#define PB92_GPIO_BTN_SW4 8 -+#define PB92_GPIO_BTN_SW5 3 -+ -+static struct gpio_button pb92_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = PB92_GPIO_BTN_SW4, -+ .active_low = 1, -+ } , { -+ .desc = "sw5", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = PB92_GPIO_BTN_SW5, -+ .active_low = 1, -+ } -+}; -+ -+static void __init pb92_init(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_set_mac_base(mac); -+ ar71xx_add_device_m25p80(&pb92_flash_data); -+ -+ ar71xx_add_device_mdio(~0); -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_gpio_buttons(-1, PB92_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(pb92_gpio_buttons), -+ pb92_gpio_buttons); -+ -+ pb9x_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_PB92, "PB92", "Atheros PB92", pb92_init); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-rb4xx.c linux-2.6.35.7/arch/mips/ar71xx/mach-rb4xx.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-rb4xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-rb4xx.c 2010-10-14 20:27:57.824611115 +0200 -@@ -0,0 +1,290 @@ -+/* -+ * MikroTik RouterBOARD 4xx series support -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define RB4XX_GPIO_USER_LED 4 -+#define RB4XX_GPIO_RESET_SWITCH 7 -+ -+#define RB4XX_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led rb4xx_leds_gpio[] __initdata = { -+ { -+ .name = "rb4xx:yellow:user", -+ .gpio = RB4XX_GPIO_USER_LED, -+ .active_low = 0, -+ }, -+}; -+ -+static struct gpio_button rb4xx_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset_switch", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = RB4XX_GPIO_RESET_SWITCH, -+ .active_low = 1, -+ } -+}; -+ -+static struct platform_device rb4xx_nand_device = { -+ .name = "rb4xx-nand", -+ .id = -1, -+}; -+ -+static struct ar71xx_pci_irq rb4xx_pci_irqs[] __initdata = { -+ { -+ .slot = 0, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ }, { -+ .slot = 1, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV0, -+ }, { -+ .slot = 1, -+ .pin = 2, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 2, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV1, -+ }, { -+ .slot = 3, -+ .pin = 1, -+ .irq = AR71XX_PCI_IRQ_DEV2, -+ } -+}; -+ -+#if 0 -+/* -+ * SPI device support is experimental -+ */ -+static struct flash_platform_data rb4xx_flash_data = { -+ .type = "pm25lv512", -+}; -+ -+static struct spi_board_info rb4xx_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ .platform_data = &rb4xx_flash_data, -+ } -+}; -+ -+static struct mmc_spi_platform_data rb433_mmc_data = { -+ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, -+}; -+ -+static struct spi_board_info rb433_spi_info[] = { -+ { -+ .bus_num = 0, -+ .chip_select = 0, -+ .max_speed_hz = 25000000, -+ .modalias = "m25p80", -+ .platform_data = &rb433_flash_data, -+ }, { -+ .bus_num = 0, -+ .chip_select = 2, -+ .max_speed_hz = 25000000, -+ .modalias = "mmc_spi", -+ .platform_data = &rb433_mmc_data, -+ } -+}; -+ -+static u32 rb433_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) -+{ -+ u32 ret; -+ -+ if (is_on == AR71XX_SPI_CS_INACTIVE) { -+ ret = SPI_IOC_CS0 | SPI_IOC_CS1; -+ } else { -+ if (cs_high) { -+ ret = SPI_IOC_CS0 | SPI_IOC_CS1; -+ } else { -+ if ((chip_select ^ 2) == 0) -+ ret = SPI_IOC_CS1 ^ (SPI_IOC_CS0 | SPI_IOC_CS1); -+ else -+ ret = SPI_IOC_CS0 ^ (SPI_IOC_CS0 | SPI_IOC_CS1); -+ } -+ } -+ -+ return ret; -+} -+ -+struct ar71xx_spi_platform_data rb433_spi_data = { -+ .bus_num = 0, -+ .num_chipselect = 3, -+ .get_ioc_base = rb433_spi_get_ioc_base, -+}; -+ -+static void rb4xx_add_device_spi(void) -+{ -+ ar71xx_add_device_spi(NULL, rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); -+} -+ -+static void rb433_add_device_spi(void) -+{ -+ ar71xx_add_device_spi(&rb433_spi_data, rb433_spi_info, -+ ARRAY_SIZE(rb433_spi_info)); -+} -+#else -+static inline void rb4xx_add_device_spi(void) {} -+static inline void rb433_add_device_spi(void) {} -+#endif -+ -+static void __init rb4xx_generic_setup(void) -+{ -+ ar71xx_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | -+ AR71XX_GPIO_FUNC_SPI_CS2_EN); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), -+ rb4xx_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, RB4XX_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(rb4xx_gpio_buttons), -+ rb4xx_gpio_buttons); -+ -+ platform_device_register(&rb4xx_nand_device); -+} -+ -+static void __init rb411_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xfffffffc); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x00000003; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", -+ rb411_setup); -+ -+static void __init rb411u_setup(void) -+{ -+ rb411_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", -+ rb411u_setup); -+ -+static void __init rb433_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb433_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xffffffe9); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000010; -+ -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", -+ rb433_setup); -+ -+static void __init rb433u_setup(void) -+{ -+ rb433_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", -+ rb433u_setup); -+ -+static void __init rb450_generic_setup(int gige) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0xffffffe0); -+ -+ ar71xx_eth0_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = (gige) ? (1 << 0) : 0; -+ ar71xx_eth0_data.speed = (gige) ? SPEED_1000 : SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000010; -+ -+ ar71xx_add_device_eth(1); -+ ar71xx_add_device_eth(0); -+} -+ -+static void __init rb450_setup(void) -+{ -+ rb450_generic_setup(0); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_450, "450", "MikroTik RouterBOARD 450", -+ rb450_setup); -+ -+static void __init rb450g_setup(void) -+{ -+ rb450_generic_setup(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", -+ rb450g_setup); -+ -+static void __init rb493_setup(void) -+{ -+ rb4xx_generic_setup(); -+ rb4xx_add_device_spi(); -+ -+ ar71xx_add_device_mdio(0x3fffff00); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x00000001; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", -+ rb493_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-rb750.c linux-2.6.35.7/arch/mips/ar71xx/mach-rb750.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-rb750.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-rb750.c 2010-10-14 20:27:57.874416755 +0200 -@@ -0,0 +1,133 @@ -+/* -+ * MikroTik RouterBOARD 750 support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "dev-ap91-eth.h" -+ -+static struct rb750_led_data rb750_leds[] = { -+ { -+ .name = "rb750:green:act", -+ .mask = RB750_LED_ACT, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port1", -+ .mask = RB750_LED_PORT5, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port2", -+ .mask = RB750_LED_PORT4, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port3", -+ .mask = RB750_LED_PORT3, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port4", -+ .mask = RB750_LED_PORT2, -+ .active_low = 1, -+ }, { -+ .name = "rb750:green:port5", -+ .mask = RB750_LED_PORT1, -+ .active_low = 1, -+ } -+}; -+ -+static struct rb750_led_platform_data rb750_leds_data = { -+ .num_leds = ARRAY_SIZE(rb750_leds), -+ .leds = rb750_leds, -+}; -+ -+static struct platform_device rb750_leds_device = { -+ .name = "leds-rb750", -+ .dev = { -+ .platform_data = &rb750_leds_data, -+ } -+}; -+ -+static const char *rb750_port_names[AP91_ETH_NUM_PORT_NAMES] __initdata = { -+ "port5", -+ "port4", -+ "port3", -+ "port2", -+}; -+ -+static struct platform_device rb750_nand_device = { -+ .name = "rb750-nand", -+ .id = -1, -+}; -+ -+int rb750_latch_change(u32 mask_clr, u32 mask_set) -+{ -+ static DEFINE_SPINLOCK(lock); -+ static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; -+ static u32 latch_oe; -+ static u32 latch_clr; -+ unsigned long flags; -+ u32 t; -+ int ret = 0; -+ -+ spin_lock_irqsave(&lock, flags); -+ -+ if ((mask_clr & BIT(31)) != 0 && -+ (latch_set & RB750_LVC573_LE) == 0) { -+ goto unlock; -+ } -+ -+ latch_set = (latch_set | mask_set) & ~mask_clr; -+ latch_clr = (latch_clr | mask_clr) & ~mask_set; -+ -+ if (latch_oe == 0) -+ latch_oe = __raw_readl(ar71xx_gpio_base + GPIO_REG_OE); -+ -+ if (likely(latch_set & RB750_LVC573_LE)) { -+ void __iomem *base = ar71xx_gpio_base; -+ -+ t = __raw_readl(base + GPIO_REG_OE); -+ t |= mask_clr | latch_oe | mask_set; -+ -+ __raw_writel(t, base + GPIO_REG_OE); -+ __raw_writel(latch_clr, base + GPIO_REG_CLEAR); -+ __raw_writel(latch_set, base + GPIO_REG_SET); -+ } else if (mask_clr & RB750_LVC573_LE) { -+ void __iomem *base = ar71xx_gpio_base; -+ -+ latch_oe = __raw_readl(base + GPIO_REG_OE); -+ __raw_writel(RB750_LVC573_LE, base + GPIO_REG_CLEAR); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_CLEAR); -+ } -+ -+ ret = 1; -+ -+ unlock: -+ spin_unlock_irqrestore(&lock, flags); -+ return ret; -+} -+EXPORT_SYMBOL_GPL(rb750_latch_change); -+ -+static void __init rb750_setup(void) -+{ -+ ar71xx_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | -+ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); -+ -+ ap91_eth_init(NULL, rb750_port_names); -+ platform_device_register(&rb750_leds_device); -+ platform_device_register(&rb750_nand_device); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", -+ rb750_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tew-632brp.c linux-2.6.35.7/arch/mips/ar71xx/mach-tew-632brp.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tew-632brp.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-tew-632brp.c 2010-10-14 20:27:57.916006386 +0200 -@@ -0,0 +1,149 @@ -+/* -+ * TrendNET TEW-632BRP board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "nvram.h" -+ -+#define TEW_632BRP_GPIO_LED_STATUS 1 -+#define TEW_632BRP_GPIO_LED_WPS 3 -+#define TEW_632BRP_GPIO_LED_WLAN 6 -+#define TEW_632BRP_GPIO_BTN_WPS 12 -+#define TEW_632BRP_GPIO_BTN_RESET 21 -+ -+#define TEW_632BRP_BUTTONS_POLL_INTERVAL 20 -+ -+#define TEW_632BRP_CONFIG_ADDR 0x1f020000 -+#define TEW_632BRP_CONFIG_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tew_632brp_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config", -+ .offset = 0x020000, -+ .size = 0x010000, -+ } , { -+ .name = "kernel", -+ .offset = 0x030000, -+ .size = 0x0d0000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x100000, -+ .size = 0x2f0000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x030000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tew_632brp_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tew_632brp_partitions, -+ .nr_parts = ARRAY_SIZE(tew_632brp_partitions), -+#endif -+}; -+ -+static struct gpio_led tew_632brp_leds_gpio[] __initdata = { -+ { -+ .name = "tew-632brp:green:status", -+ .gpio = TEW_632BRP_GPIO_LED_STATUS, -+ .active_low = 1, -+ }, { -+ .name = "tew-632brp:blue:wps", -+ .gpio = TEW_632BRP_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "tew-632brp:green:wlan", -+ .gpio = TEW_632BRP_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tew_632brp_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TEW_632BRP_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TEW_632BRP_GPIO_BTN_WPS, -+ } -+}; -+ -+#define TEW_632BRP_LAN_PHYMASK BIT(0) -+#define TEW_632BRP_WAN_PHYMASK BIT(4) -+#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ -+ TEW_632BRP_WAN_PHYMASK)) -+ -+static void __init tew_632brp_setup(void) -+{ -+ const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ u8 *wlan_mac = NULL; -+ -+ if (nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, -+ "lan_mac=", mac) == 0) { -+ ar71xx_set_mac_base(mac); -+ wlan_mac = mac; -+ } -+ -+ ar71xx_add_device_mdio(TEW_632BRP_MDIO_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&tew_632brp_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), -+ tew_632brp_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TEW_632BRP_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tew_632brp_gpio_buttons), -+ tew_632brp_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, wlan_mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", -+ tew_632brp_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c linux-2.6.35.7/arch/mips/ar71xx/mach-tl-wr1043nd.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-tl-wr1043nd.c 2010-10-14 20:27:57.964353043 +0200 -@@ -0,0 +1,156 @@ -+/* -+ * TP-LINK TL-WR1043ND board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define TL_WR1043ND_GPIO_LED_USB 1 -+#define TL_WR1043ND_GPIO_LED_SYSTEM 2 -+#define TL_WR1043ND_GPIO_LED_QSS 5 -+#define TL_WR1043ND_GPIO_LED_WLAN 9 -+ -+#define TL_WR1043ND_GPIO_BTN_RESET 3 -+#define TL_WR1043ND_GPIO_BTN_QSS 7 -+ -+#define TL_WR1043ND_GPIO_RTL8366_SDA 18 -+#define TL_WR1043ND_GPIO_RTL8366_SCK 19 -+ -+#define TL_WR1043ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr1043nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x690000, -+ } , { -+ .name = "art", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x7d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr1043nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr1043nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr1043nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr1043nd:green:usb", -+ .gpio = TL_WR1043ND_GPIO_LED_USB, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr1043nd:green:system", -+ .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr1043nd:green:qss", -+ .gpio = TL_WR1043ND_GPIO_LED_QSS, -+ .active_low = 0, -+ }, { -+ .name = "tl-wr1043nd:green:wlan", -+ .gpio = TL_WR1043ND_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tl_wr1043nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR1043ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR1043ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366rb_platform_data tl_wr1043nd_rtl8366rb_data = { -+ .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, -+ .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device tl_wr1043nd_rtl8366rb_device = { -+ .name = RTL8366RB_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &tl_wr1043nd_rtl8366rb_data, -+ } -+}; -+ -+static void __init tl_wr1043nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_pll_data.pll_1000 = 0x1a000000; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&tl_wr1043nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), -+ tl_wr1043nd_leds_gpio); -+ -+ platform_device_register(&tl_wr1043nd_rtl8366rb_device); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR1043ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr1043nd_gpio_buttons), -+ tl_wr1043nd_gpio_buttons); -+ -+ ar913x_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", -+ tl_wr1043nd_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tl-wr741nd.c linux-2.6.35.7/arch/mips/ar71xx/mach-tl-wr741nd.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tl-wr741nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-tl-wr741nd.c 2010-10-14 20:27:58.005601016 +0200 -@@ -0,0 +1,115 @@ -+/* -+ * TP-LINK TL-WR741ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-eth.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR741ND_GPIO_LED_QSS 0 -+#define TL_WR741ND_GPIO_LED_SYSTEM 1 -+ -+#define TL_WR741ND_GPIO_BTN_RESET 11 -+#define TL_WR741ND_GPIO_BTN_QSS 12 -+ -+#define TL_WR741ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr741nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr741nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr741nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr741nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr741nd:green:system", -+ .gpio = TL_WR741ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr741nd:green:qss", -+ .gpio = TL_WR741ND_GPIO_LED_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button tl_wr741nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR741ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR741ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init tl_wr741nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_add_device_m25p80(&tl_wr741nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), -+ tl_wr741nd_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR741ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr741nd_gpio_buttons), -+ tl_wr741nd_gpio_buttons); -+ -+ ap91_eth_init(mac, NULL); -+ ap91_pci_init(ee, mac); -+} -+MIPS_MACHINE(AR71XX_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", -+ tl_wr741nd_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tl-wr841n.c linux-2.6.35.7/arch/mips/ar71xx/mach-tl-wr841n.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tl-wr841n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-tl-wr841n.c 2010-10-14 20:27:58.057141646 +0200 -@@ -0,0 +1,143 @@ -+/* -+ * TP-LINK TL-WR841N board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 -+#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 -+#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 -+ -+#define TL_WR841ND_V1_GPIO_BTN_RESET 3 -+#define TL_WR841ND_V1_GPIO_BTN_QSS 7 -+ -+#define TL_WR841ND_V1_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr841n_v1_partitions[] = { -+ { -+ .name = "redboot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x280000, -+ } , { -+ .name = "config", -+ .offset = 0x3e0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3c0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr841n_v1_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr841n_v1_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr841n:green:system", -+ .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr841n:red:qss", -+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, -+ }, { -+ .name = "tl-wr841n:green:qss", -+ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, -+ } -+}; -+ -+static struct gpio_button tl_wr841n_v1_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { -+ .port_names[0] = "wan", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+ .port_names[5] = "cpu", -+}; -+ -+static struct dsa_platform_data tl_wr841n_v1_dsa_data = { -+ .nr_chips = 1, -+ .chip = &tl_wr841n_v1_dsa_chip, -+}; -+ -+static void __init tl_wr841n_v1_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_dsa(0, &tl_wr841n_v1_dsa_data); -+ -+ ar71xx_add_device_m25p80(&tl_wr841n_v1_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), -+ tl_wr841n_v1_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR841ND_V1_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr841n_v1_gpio_buttons), -+ tl_wr841n_v1_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", -+ tl_wr841n_v1_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tl-wr941nd.c linux-2.6.35.7/arch/mips/ar71xx/mach-tl-wr941nd.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-tl-wr941nd.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-tl-wr941nd.c 2010-10-14 20:27:58.095601080 +0200 -@@ -0,0 +1,142 @@ -+/* -+ * TP-LINK TL-WR941ND board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-dsa.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define TL_WR941ND_GPIO_LED_SYSTEM 2 -+#define TL_WR941ND_GPIO_LED_QSS_RED 4 -+#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 -+ -+#define TL_WR941ND_GPIO_BTN_RESET 3 -+#define TL_WR941ND_GPIO_BTN_QSS 7 -+ -+#define TL_WR941ND_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition tl_wr941nd_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x020000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x160000, -+ .size = 0x290000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x020000, -+ .size = 0x3d0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data tl_wr941nd_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = tl_wr941nd_partitions, -+ .nr_parts = ARRAY_SIZE(tl_wr941nd_partitions), -+#endif -+}; -+ -+static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { -+ { -+ .name = "tl-wr941nd:green:system", -+ .gpio = TL_WR941ND_GPIO_LED_SYSTEM, -+ .active_low = 1, -+ }, { -+ .name = "tl-wr941nd:red:qss", -+ .gpio = TL_WR941ND_GPIO_LED_QSS_RED, -+ }, { -+ .name = "tl-wr941nd:green:qss", -+ .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, -+ } -+}; -+ -+static struct gpio_button tl_wr941nd_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = TL_WR941ND_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "qss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = TL_WR941ND_GPIO_BTN_QSS, -+ .active_low = 1, -+ } -+}; -+ -+static struct dsa_chip_data tl_wr941nd_dsa_chip = { -+ .port_names[0] = "wan", -+ .port_names[1] = "lan1", -+ .port_names[2] = "lan2", -+ .port_names[3] = "lan3", -+ .port_names[4] = "lan4", -+ .port_names[5] = "cpu", -+}; -+ -+static struct dsa_platform_data tl_wr941nd_dsa_data = { -+ .nr_chips = 1, -+ .chip = &tl_wr941nd_dsa_chip, -+}; -+ -+static void __init tl_wr941nd_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_dsa(0, &tl_wr941nd_dsa_data); -+ -+ ar71xx_add_device_m25p80(&tl_wr941nd_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), -+ tl_wr941nd_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, TL_WR941ND_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(tl_wr941nd_gpio_buttons), -+ tl_wr941nd_gpio_buttons); -+ ar913x_add_device_wmac(eeprom, mac); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", -+ tl_wr941nd_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/machtype.h linux-2.6.35.7/arch/mips/ar71xx/machtype.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/machtype.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/machtype.h 2010-10-14 20:27:58.135601194 +0200 -@@ -0,0 +1,60 @@ -+/* -+ * Atheros AR71xx machine type definitions -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_MACHTYPE_H -+#define _AR71XX_MACHTYPE_H -+ -+#include -+ -+enum ar71xx_mach_type { -+ AR71XX_MACH_GENERIC = 0, -+ AR71XX_MACH_AP81, /* Atheros AP81 */ -+ AR71XX_MACH_AP83, /* Atheros AP83 */ -+ AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */ -+ AR71XX_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ -+ AR71XX_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ -+ AR71XX_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ -+ AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ -+ AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ -+ AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ -+ AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ -+ AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */ -+ AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ -+ AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ -+ AR71XX_MACH_RB_750, /* MikroTik RouterBOARD 750 */ -+ AR71XX_MACH_PB42, /* Atheros PB42 */ -+ AR71XX_MACH_PB44, /* Atheros PB44 */ -+ AR71XX_MACH_PB92, /* Atheros PB92 */ -+ AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */ -+ AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */ -+ AR71XX_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ -+ AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ -+ AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ -+ AR71XX_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ -+ AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ -+ AR71XX_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */ -+ AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ -+ AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */ -+ AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */ -+ AR71XX_MACH_UBNT_AR71XX, /* Ubiquiti AR71xx-based board */ -+ AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ -+ AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ -+ AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ -+ AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ -+ AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */ -+ AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */ -+ AR71XX_MACH_WP543, /* Compex WP543 */ -+ AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */ -+ AR71XX_MACH_WRT400N, /* Linksys WRT400N */ -+ AR71XX_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ -+}; -+ -+#endif /* _AR71XX_MACHTYPE_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-ubnt.c linux-2.6.35.7/arch/mips/ar71xx/mach-ubnt.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-ubnt.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-ubnt.c 2010-10-14 20:27:58.190029906 +0200 -@@ -0,0 +1,281 @@ -+/* -+ * Ubiquiti RouterStation support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2008 Ubiquiti -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap91-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-pb42-pci.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define UBNT_RS_GPIO_LED_RF 2 -+#define UBNT_RS_GPIO_SW4 8 -+ -+#define UBNT_LS_SR71_GPIO_LED_D25 0 -+#define UBNT_LS_SR71_GPIO_LED_D26 1 -+#define UBNT_LS_SR71_GPIO_LED_D24 2 -+#define UBNT_LS_SR71_GPIO_LED_D23 4 -+#define UBNT_LS_SR71_GPIO_LED_D22 5 -+#define UBNT_LS_SR71_GPIO_LED_D27 6 -+#define UBNT_LS_SR71_GPIO_LED_D28 7 -+ -+#define UBNT_M_GPIO_LED_L1 0 -+#define UBNT_M_GPIO_LED_L2 1 -+#define UBNT_M_GPIO_LED_L3 11 -+#define UBNT_M_GPIO_LED_L4 7 -+#define UBNT_M_GPIO_BTN_RESET 12 -+ -+#define UBNT_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:green:rf", -+ .gpio = UBNT_RS_GPIO_LED_RF, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:green:d22", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D22, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d23", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D23, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d24", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D24, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:red:d25", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D25, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:red:d26", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D26, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d27", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D27, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:d28", -+ .gpio = UBNT_LS_SR71_GPIO_LED_D28, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_led ubnt_m_leds_gpio[] __initdata = { -+ { -+ .name = "ubnt:red:link1", -+ .gpio = UBNT_M_GPIO_LED_L1, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:orange:link2", -+ .gpio = UBNT_M_GPIO_LED_L2, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:link3", -+ .gpio = UBNT_M_GPIO_LED_L3, -+ .active_low = 0, -+ }, { -+ .name = "ubnt:green:link4", -+ .gpio = UBNT_M_GPIO_LED_L4, -+ .active_low = 0, -+ } -+}; -+ -+static struct gpio_button ubnt_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = UBNT_RS_GPIO_SW4, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button ubnt_m_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = UBNT_M_GPIO_BTN_RESET, -+ .active_low = 1, -+ } -+}; -+ -+static void __init ubnt_generic_setup(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_gpio_buttons(-1, UBNT_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ubnt_gpio_buttons), -+ ubnt_gpio_buttons); -+ -+ pb42_pci_init(); -+} -+ -+#define UBNT_RS_WAN_PHYMASK (1 << 20) -+#define UBNT_RS_LAN_PHYMASK ((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19)) -+ -+static void __init ubnt_rs_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_100; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), -+ ubnt_rs_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", -+ ubnt_rs_setup); -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_AR71XX, "Ubiquiti AR71xx-based board", -+ "Ubiquiti RouterStation", ubnt_rs_setup); -+ -+#define UBNT_RSPRO_WAN_PHYMASK (1 << 4) -+#define UBNT_RSPRO_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) -+ -+static void __init ubnt_rspro_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~(UBNT_RSPRO_WAN_PHYMASK | UBNT_RSPRO_LAN_PHYMASK)); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), -+ ubnt_rs_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", -+ ubnt_rspro_setup); -+ -+static void __init ubnt_lsx_setup(void) -+{ -+ ubnt_generic_setup(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); -+ -+#define UBNT_LSSR71_PHY_MASK (1 << 1) -+ -+static void __init ubnt_lssr71_setup(void) -+{ -+ ubnt_generic_setup(); -+ -+ ar71xx_add_device_mdio(~UBNT_LSSR71_PHY_MASK); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; -+ -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), -+ ubnt_ls_sr71_leds_gpio); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", -+ ubnt_lssr71_setup); -+ -+static void __init ubnt_m_setup(void) -+{ -+ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(~0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.fifo_cfg1 = 0x0010ffff; -+ ar71xx_eth0_data.fifo_cfg2 = 0x015500aa; -+ ar71xx_eth0_data.fifo_cfg3 = 0x01f00140; -+ -+ ar71xx_add_device_eth(0); -+ -+ ap91_pci_init(ee, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_m_leds_gpio), -+ ubnt_m_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, UBNT_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(ubnt_m_gpio_buttons), -+ ubnt_m_gpio_buttons); -+} -+ -+static void __init ubnt_rocket_m_setup(void) -+{ -+ ubnt_m_setup(); -+ ar71xx_add_device_usb(); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", -+ ubnt_m_setup); -+MIPS_MACHINE(AR71XX_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", -+ ubnt_rocket_m_setup); -+ -+/* TODO detect the second ethernet port and use one -+ init function for all Ubiquiti MIMO series products */ -+static void __init ubnt_nano_m_setup(void) -+{ -+ ubnt_m_setup(); -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.speed = SPEED_1000; -+ ar71xx_eth1_data.duplex = DUPLEX_FULL; -+ ar71xx_eth1_data.fifo_cfg1 = 0x0010ffff; -+ ar71xx_eth1_data.fifo_cfg2 = 0x015500aa; -+ ar71xx_eth1_data.fifo_cfg3 = 0x01f00140; -+ -+ ar71xx_add_device_eth(1); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", -+ ubnt_nano_m_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wndr3700.c linux-2.6.35.7/arch/mips/ar71xx/mach-wndr3700.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wndr3700.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-wndr3700.c 2010-10-14 20:27:58.228101285 +0200 -@@ -0,0 +1,209 @@ -+/* -+ * Netgear WNDR3700 board support -+ * -+ * Copyright (C) 2009 Marco Porsch -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ap94-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WNDR3700_GPIO_LED_WPS_ORANGE 0 -+#define WNDR3700_GPIO_LED_POWER_ORANGE 1 -+#define WNDR3700_GPIO_LED_POWER_GREEN 2 -+#define WNDR3700_GPIO_LED_WPS_GREEN 4 -+#define WNDR3700_GPIO_LED_WAN_GREEN 6 -+ -+#define WNDR3700_GPIO_BTN_WPS 3 -+#define WNDR3700_GPIO_BTN_RESET 8 -+#define WNDR3700_GPIO_BTN_WIFI 11 -+ -+#define WNDR3700_GPIO_RTL8366_SDA 5 -+#define WNDR3700_GPIO_RTL8366_SCK 7 -+ -+#define WNDR3700_BUTTONS_POLL_INTERVAL 20 -+ -+#define WNDR3700_WMAC0_MAC_OFFSET 0 -+#define WNDR3700_WMAC1_MAC_OFFSET 0xc -+#define WNDR3700_CALDATA0_OFFSET 0x1000 -+#define WNDR3700_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wndr3700_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x050000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "env", -+ .offset = 0x050000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "rootfs", -+ .offset = 0x070000, -+ .size = 0x720000, -+ } , { -+ .name = "config", -+ .offset = 0x790000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "config_bak", -+ .offset = 0x7a0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "pot", -+ .offset = 0x7b0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "traffic_meter", -+ .offset = 0x7c0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "language", -+ .offset = 0x7d0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wndr3700_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wndr3700_partitions, -+ .nr_parts = ARRAY_SIZE(wndr3700_partitions), -+#endif -+}; -+ -+static struct gpio_led wndr3700_leds_gpio[] __initdata = { -+ { -+ .name = "wndr3700:green:power", -+ .gpio = WNDR3700_GPIO_LED_POWER_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:orange:power", -+ .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:green:wps", -+ .gpio = WNDR3700_GPIO_LED_WPS_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:orange:wps", -+ .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wndr3700:green:wan", -+ .gpio = WNDR3700_GPIO_LED_WAN_GREEN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wndr3700_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_WPS, -+ .active_low = 1, -+ } , { -+ .desc = "wifi", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = WNDR3700_GPIO_BTN_WIFI, -+ .active_low = 1, -+ } -+}; -+ -+static struct rtl8366s_platform_data wndr3700_rtl8366s_data = { -+ .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, -+ .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device wndr3700_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wndr3700_rtl8366s_data, -+ } -+}; -+ -+static void __init wndr3700_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ -+ ar71xx_set_mac_base(art); -+ -+ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; -+ ar71xx_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; -+ ar71xx_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ -+ ar71xx_add_device_m25p80(&wndr3700_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), -+ wndr3700_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WNDR3700_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wndr3700_gpio_buttons), -+ wndr3700_gpio_buttons); -+ -+ platform_device_register(&wndr3700_rtl8366s_device); -+ platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); -+ -+ ap94_pci_enable_quirk_wndr3700(); -+ ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, -+ art + WNDR3700_WMAC0_MAC_OFFSET, -+ art + WNDR3700_CALDATA1_OFFSET, -+ art + WNDR3700_WMAC1_MAC_OFFSET); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNDR3700, "WNDR3700", "NETGEAR WNDR3700", -+ wndr3700_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wnr2000.c linux-2.6.35.7/arch/mips/ar71xx/mach-wnr2000.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wnr2000.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-wnr2000.c 2010-10-14 20:27:58.268101150 +0200 -@@ -0,0 +1,148 @@ -+/* -+ * NETGEAR WNR2000 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * Copyright (C) 2008-2009 Andy Boyett -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define WNR2000_GPIO_LED_PWR_GREEN 14 -+#define WNR2000_GPIO_LED_PWR_AMBER 7 -+#define WNR2000_GPIO_LED_WPS 4 -+#define WNR2000_GPIO_LED_WLAN 6 -+#define WNR2000_GPIO_BTN_RESET 21 -+#define WNR2000_GPIO_BTN_WPS 8 -+ -+#define WNR2000_BUTTONS_POLL_INTERVAL 20 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wnr2000_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "u-boot-env", -+ .offset = 0x040000, -+ .size = 0x010000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x050000, -+ .size = 0x240000, -+ } , { -+ .name = "user-config", -+ .offset = 0x290000, -+ .size = 0x010000, -+ } , { -+ .name = "uImage", -+ .offset = 0x2a0000, -+ .size = 0x120000, -+ } , { -+ .name = "language_table", -+ .offset = 0x3c0000, -+ .size = 0x020000, -+ } , { -+ .name = "rootfs_checksum", -+ .offset = 0x3e0000, -+ .size = 0x010000, -+ } , { -+ .name = "art", -+ .offset = 0x3f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wnr2000_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wnr2000_partitions, -+ .nr_parts = ARRAY_SIZE(wnr2000_partitions), -+#endif -+}; -+ -+static struct gpio_led wnr2000_leds_gpio[] __initdata = { -+ { -+ .name = "wnr2000:green:power", -+ .gpio = WNR2000_GPIO_LED_PWR_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:amber:power", -+ .gpio = WNR2000_GPIO_LED_PWR_AMBER, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:green:wps", -+ .gpio = WNR2000_GPIO_LED_WPS, -+ .active_low = 1, -+ }, { -+ .name = "wnr2000:blue:wlan", -+ .gpio = WNR2000_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wnr2000_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WNR2000_GPIO_BTN_RESET, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WNR2000_GPIO_BTN_WPS, -+ } -+}; -+ -+static void __init wnr2000_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom); -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ ar71xx_eth0_data.has_ar8216 = 1; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wnr2000_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), -+ wnr2000_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WNR2000_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wnr2000_gpio_buttons), -+ wnr2000_gpio_buttons); -+ -+ -+ ar913x_add_device_wmac(eeprom, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wp543.c linux-2.6.35.7/arch/mips/ar71xx/mach-wp543.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wp543.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-wp543.c 2010-10-14 20:27:58.314545632 +0200 -@@ -0,0 +1,99 @@ -+/* -+ * Compex WP543/WPJ543 board support -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-pb42-pci.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WP543_GPIO_SW6 2 -+#define WP543_GPIO_LED_1 3 -+#define WP543_GPIO_LED_2 4 -+#define WP543_GPIO_LED_WLAN 5 -+#define WP543_GPIO_LED_CONN 6 -+#define WP543_GPIO_LED_DIAG 7 -+#define WP543_GPIO_SW4 8 -+ -+#define WP543_BUTTONS_POLL_INTERVAL 20 -+ -+static struct gpio_led wp543_leds_gpio[] __initdata = { -+ { -+ .name = "wp543:green:led1", -+ .gpio = WP543_GPIO_LED_1, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:led2", -+ .gpio = WP543_GPIO_LED_2, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:wlan", -+ .gpio = WP543_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:conn", -+ .gpio = WP543_GPIO_LED_CONN, -+ .active_low = 1, -+ }, { -+ .name = "wp543:green:diag", -+ .gpio = WP543_GPIO_LED_DIAG, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wp543_gpio_buttons[] __initdata = { -+ { -+ .desc = "sw6", -+ .type = EV_KEY, -+ .code = BTN_0, -+ .threshold = 3, -+ .gpio = WP543_GPIO_SW6, -+ }, { -+ .desc = "sw4", -+ .type = EV_KEY, -+ .code = BTN_1, -+ .threshold = 3, -+ .gpio = WP543_GPIO_SW4, -+ } -+}; -+ -+static void __init wp543_setup(void) -+{ -+ ar71xx_add_device_m25p80(NULL); -+ -+ ar71xx_add_device_mdio(0xfffffff7); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; -+ ar71xx_eth0_data.phy_mask = 0x08; -+ ar71xx_eth0_data.reset_bit = RESET_MODULE_GE0_MAC | -+ RESET_MODULE_GE0_PHY; -+ ar71xx_add_device_eth(0); -+ -+ ar71xx_add_device_usb(); -+ -+ pb42_pci_init(); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), -+ wp543_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WP543_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wp543_gpio_buttons), -+ wp543_gpio_buttons); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WP543, "WP543", "Compex WP543", wp543_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wrt160nl.c linux-2.6.35.7/arch/mips/ar71xx/mach-wrt160nl.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wrt160nl.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-wrt160nl.c 2010-10-14 20:27:58.364348612 +0200 -@@ -0,0 +1,158 @@ -+/* -+ * Linksys WRT160NL board support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-m25p80.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+#include "nvram.h" -+ -+#define WRT160NL_GPIO_LED_POWER 14 -+#define WRT160NL_GPIO_LED_WPS_AMBER 9 -+#define WRT160NL_GPIO_LED_WPS_BLUE 8 -+#define WRT160NL_GPIO_LED_WLAN 6 -+ -+#define WRT160NL_GPIO_BTN_WPS 7 -+#define WRT160NL_GPIO_BTN_RESET 21 -+ -+#define WRT160NL_BUTTONS_POLL_INTERVAL 20 -+ -+#define WRT160NL_NVRAM_ADDR 0x1f7e0000 -+#define WRT160NL_NVRAM_SIZE 0x10000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wrt160nl_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x040000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "kernel", -+ .offset = 0x040000, -+ .size = 0x0e0000, -+ } , { -+ .name = "filesytem", -+ .offset = 0x120000, -+ .size = 0x6c0000, -+ } , { -+ .name = "nvram", -+ .offset = 0x7e0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "ART", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x7a0000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wrt160nl_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wrt160nl_partitions, -+ .nr_parts = ARRAY_SIZE(wrt160nl_partitions), -+#endif -+}; -+ -+static struct gpio_led wrt160nl_leds_gpio[] __initdata = { -+ { -+ .name = "wrt160nl:blue:power", -+ .gpio = WRT160NL_GPIO_LED_POWER, -+ .active_low = 1, -+ .default_trigger = "default-on", -+ }, { -+ .name = "wrt160nl:amber:wps", -+ .gpio = WRT160NL_GPIO_LED_WPS_AMBER, -+ .active_low = 1, -+ }, { -+ .name = "wrt160nl:blue:wps", -+ .gpio = WRT160NL_GPIO_LED_WPS_BLUE, -+ .active_low = 1, -+ }, { -+ .name = "wrt160nl:blue:wlan", -+ .gpio = WRT160NL_GPIO_LED_WLAN, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wrt160nl_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WRT160NL_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "wps", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WRT160NL_GPIO_BTN_WPS, -+ .active_low = 1, -+ } -+}; -+ -+static void __init wrt160nl_setup(void) -+{ -+ const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ u8 mac[6]; -+ -+ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, -+ "lan_hwaddr=", mac) == 0) -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.phy_mask = 0x01; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wrt160nl_flash_data); -+ -+ ar71xx_add_device_usb(); -+ -+ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, -+ "wl0_hwaddr=", mac) == 0) -+ ar913x_add_device_wmac(eeprom, mac); -+ else -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), -+ wrt160nl_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WRT160NL_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wrt160nl_gpio_buttons), -+ wrt160nl_gpio_buttons); -+ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", -+ wrt160nl_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wrt400n.c linux-2.6.35.7/arch/mips/ar71xx/mach-wrt400n.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wrt400n.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-wrt400n.c 2010-10-14 20:27:58.414355031 +0200 -@@ -0,0 +1,168 @@ -+/* -+ * Linksys WRT400N board support -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos -+ * Copyright (C) 2009 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ap94-pci.h" -+#include "dev-m25p80.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+ -+#define WRT400N_GPIO_LED_ORANGE 5 -+#define WRT400N_GPIO_LED_GREEN 4 -+#define WRT400N_GPIO_LED_POWER 1 -+#define WRT400N_GPIO_LED_WLAN 0 -+ -+#define WRT400N_GPIO_BTN_RESET 8 -+#define WRT400N_GPIO_BTN_WLSEC 3 -+ -+#define WRT400N_BUTTONS_POLL_INTERVAL 20 -+ -+#define WRT400N_MAC_ADDR_OFFSET 0x120c -+#define WRT400N_CALDATA0_OFFSET 0x1000 -+#define WRT400N_CALDATA1_OFFSET 0x5000 -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wrt400n_partitions[] = { -+ { -+ .name = "uboot", -+ .offset = 0, -+ .size = 0x030000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "env", -+ .offset = 0x030000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "linux", -+ .offset = 0x040000, -+ .size = 0x140000, -+ } , { -+ .name = "rootfs", -+ .offset = 0x180000, -+ .size = 0x630000, -+ } , { -+ .name = "nvram", -+ .offset = 0x7b0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "factory", -+ .offset = 0x7c0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "language", -+ .offset = 0x7d0000, -+ .size = 0x020000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "caldata", -+ .offset = 0x7f0000, -+ .size = 0x010000, -+ .mask_flags = MTD_WRITEABLE, -+ } , { -+ .name = "firmware", -+ .offset = 0x040000, -+ .size = 0x770000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct flash_platform_data wrt400n_flash_data = { -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wrt400n_partitions, -+ .nr_parts = ARRAY_SIZE(wrt400n_partitions), -+#endif -+}; -+ -+static struct gpio_led wrt400n_leds_gpio[] __initdata = { -+ { -+ .name = "wrt400n:green:status", -+ .gpio = WRT400N_GPIO_LED_GREEN, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:amber:aoss", -+ .gpio = WRT400N_GPIO_LED_ORANGE, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:green:wlan", -+ .gpio = WRT400N_GPIO_LED_WLAN, -+ .active_low = 1, -+ }, { -+ .name = "wrt400n:green:power", -+ .gpio = WRT400N_GPIO_LED_POWER, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wrt400n_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WRT400N_GPIO_BTN_RESET, -+ .active_low = 1, -+ } , { -+ .desc = "wlsec", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WRT400N_GPIO_BTN_WLSEC, -+ .active_low = 1, -+ } -+}; -+ -+static void __init wrt400n_setup(void) -+{ -+ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); -+ u8 mac[6]; -+ int i; -+ -+ memcpy(mac, art + WRT400N_MAC_ADDR_OFFSET, 6); -+ for (i = 5; i >= 3; i--) -+ if (++mac[i] != 0x00) break; -+ -+ ar71xx_set_mac_base(mac); -+ -+ ar71xx_add_device_mdio(0x0); -+ -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth0_data.speed = SPEED_100; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_m25p80(&wrt400n_flash_data); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), -+ wrt400n_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WRT400N_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wrt400n_gpio_buttons), -+ wrt400n_gpio_buttons); -+ -+ ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, -+ art + WRT400N_CALDATA1_OFFSET, NULL); -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c linux-2.6.35.7/arch/mips/ar71xx/mach-wzr-hp-g300nh.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 2010-10-14 20:27:58.455673598 +0200 -@@ -0,0 +1,265 @@ -+/* -+ * Buffalo WZR-HP-G300NH board support -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+#include "dev-ar913x-wmac.h" -+#include "dev-gpio-buttons.h" -+#include "dev-leds-gpio.h" -+#include "dev-usb.h" -+ -+#define WZRHPG300NH_GPIO_LED_USB 0 -+#define WZRHPG300NH_GPIO_LED_DIAG 1 -+#define WZRHPG300NH_GPIO_LED_WIRELESS 6 -+#define WZRHPG300NH_GPIO_LED_SECURITY 17 -+#define WZRHPG300NH_GPIO_LED_ROUTER 18 -+ -+#define WZRHPG300NH_GPIO_RTL8366_SDA 19 -+#define WZRHPG300NH_GPIO_RTL8366_SCK 20 -+ -+#define WZRHPG300NH_GPIO_74HC153_S0 9 -+#define WZRHPG300NH_GPIO_74HC153_S1 11 -+#define WZRHPG300NH_GPIO_74HC153_1Y 12 -+#define WZRHPG300NH_GPIO_74HC153_2Y 14 -+ -+#define WZRHPG300NH_GPIO_EXP_BASE 32 -+#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) -+#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) -+#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) -+#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) -+#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) -+#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) -+#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) -+ -+#define WZRHPG300NH_BUTTONS_POLL_INTERVAL 20 -+ -+#define WZRHPG300NH_MAC_OFFSET 0x20c -+ -+#ifdef CONFIG_MTD_PARTITIONS -+static struct mtd_partition wzrhpg300nh_flash_partitions[] = { -+ { -+ .name = "u-boot", -+ .offset = 0, -+ .size = 0x0040000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "u-boot-env", -+ .offset = 0x0040000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = 0x0060000, -+ .size = 0x0100000, -+ }, { -+ .name = "rootfs", -+ .offset = 0x0160000, -+ .size = 0x1e60000, -+ }, { -+ .name = "user_property", -+ .offset = 0x1fc0000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "art", -+ .offset = 0x1fe0000, -+ .size = 0x0020000, -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "firmware", -+ .offset = 0x0060000, -+ .size = 0x1f60000, -+ } -+}; -+#endif /* CONFIG_MTD_PARTITIONS */ -+ -+static struct ar91xx_flash_platform_data wzrhpg300nh_flash_data = { -+ .width = 2, -+#ifdef CONFIG_MTD_PARTITIONS -+ .parts = wzrhpg300nh_flash_partitions, -+ .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), -+#endif -+}; -+ -+#define WZRHPG300NH_FLASH_BASE 0x1e000000 -+#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) -+ -+static struct resource wzrhpg300nh_flash_resources[] = { -+ [0] = { -+ .start = WZRHPG300NH_FLASH_BASE, -+ .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, -+ .flags = IORESOURCE_MEM, -+ }, -+}; -+ -+static struct platform_device wzrhpg300nh_flash_device = { -+ .name = "ar91xx-flash", -+ .id = -1, -+ .resource = wzrhpg300nh_flash_resources, -+ .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), -+ .dev = { -+ .platform_data = &wzrhpg300nh_flash_data, -+ } -+}; -+ -+static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { -+ { -+ .name = "wzr-hp-g300nh:orange:security", -+ .gpio = WZRHPG300NH_GPIO_LED_SECURITY, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:green:wireless", -+ .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:green:router", -+ .gpio = WZRHPG300NH_GPIO_LED_ROUTER, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:red:diag", -+ .gpio = WZRHPG300NH_GPIO_LED_DIAG, -+ .active_low = 1, -+ }, { -+ .name = "wzr-hp-g300nh:blue:usb", -+ .gpio = WZRHPG300NH_GPIO_LED_USB, -+ .active_low = 1, -+ } -+}; -+ -+static struct gpio_button wzrhpg300nh_gpio_buttons[] __initdata = { -+ { -+ .desc = "reset", -+ .type = EV_KEY, -+ .code = KEY_RESTART, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_RESET, -+ .active_low = 1, -+ }, { -+ .desc = "aoss", -+ .type = EV_KEY, -+ .code = KEY_WPS_BUTTON, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_AOSS, -+ .active_low = 1, -+ }, { -+ .desc = "usb", -+ .type = EV_KEY, -+ .code = BTN_2, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_USB, -+ .active_low = 1, -+ }, { -+ .desc = "qos_on", -+ .type = EV_KEY, -+ .code = BTN_3, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, -+ .active_low = 0, -+ }, { -+ .desc = "qos_off", -+ .type = EV_KEY, -+ .code = BTN_4, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, -+ .active_low = 0, -+ }, { -+ .desc = "router_on", -+ .type = EV_KEY, -+ .code = BTN_5, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, -+ .active_low = 0, -+ }, { -+ .desc = "router_auto", -+ .type = EV_KEY, -+ .code = BTN_6, -+ .threshold = 3, -+ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, -+ .active_low = 0, -+ } -+}; -+ -+static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { -+ .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, -+ .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, -+ .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, -+ .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, -+ .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, -+}; -+ -+static struct platform_device wzrhpg300nh_74hc153_device = { -+ .name = NXP_74HC153_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_74hc153_data, -+ } -+}; -+ -+static struct rtl8366s_platform_data wzrhpg300nh_rtl8366s_data = { -+ .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, -+ .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, -+}; -+ -+static struct platform_device wzrhpg300nh_rtl8366s_device = { -+ .name = RTL8366S_DRIVER_NAME, -+ .id = -1, -+ .dev = { -+ .platform_data = &wzrhpg300nh_rtl8366s_data, -+ } -+}; -+ -+static void __init wzrhpg300nh_setup(void) -+{ -+ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); -+ -+ ar71xx_set_mac_base(eeprom + WZRHPG300NH_MAC_OFFSET); -+ -+ ar71xx_eth0_pll_data.pll_1000 = 0x1e000100; -+ ar71xx_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; -+ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth0_data.speed = SPEED_1000; -+ ar71xx_eth0_data.duplex = DUPLEX_FULL; -+ -+ ar71xx_eth1_pll_data.pll_1000 = 0x1e000100; -+ ar71xx_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; -+ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; -+ ar71xx_eth1_data.phy_mask = 0x10; -+ -+ ar71xx_add_device_eth(0); -+ ar71xx_add_device_eth(1); -+ -+ ar71xx_add_device_usb(); -+ ar913x_add_device_wmac(eeprom, NULL); -+ -+ platform_device_register(&wzrhpg300nh_74hc153_device); -+ platform_device_register(&wzrhpg300nh_flash_device); -+ platform_device_register(&wzrhpg300nh_rtl8366s_device); -+ -+ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), -+ wzrhpg300nh_leds_gpio); -+ -+ ar71xx_add_device_gpio_buttons(-1, WZRHPG300NH_BUTTONS_POLL_INTERVAL, -+ ARRAY_SIZE(wzrhpg300nh_gpio_buttons), -+ wzrhpg300nh_gpio_buttons); -+ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", -+ "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/Makefile linux-2.6.35.7/arch/mips/ar71xx/Makefile ---- linux-2.6.35.7.orig/arch/mips/ar71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/Makefile 2010-10-14 20:27:58.505507309 +0200 -@@ -0,0 +1,54 @@ -+# -+# Makefile for the Atheros AR71xx SoC specific parts of the kernel -+# -+# Copyright (C) 2008-2009 Gabor Juhos -+# Copyright (C) 2008 Imre Kaloz -+# -+# This program is free software; you can redistribute it and/or modify it -+# under the terms of the GNU General Public License version 2 as published -+# by the Free Software Foundation. -+ -+obj-y := prom.o irq.o setup.o devices.o gpio.o ar71xx.o -+ -+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+obj-$(CONFIG_PCI) += pci.o -+ -+obj-$(CONFIG_AR71XX_DEV_AP91_ETH) += dev-ap91-eth.o -+obj-$(CONFIG_AR71XX_DEV_AP91_PCI) += dev-ap91-pci.o -+obj-$(CONFIG_AR71XX_DEV_AP94_PCI) += dev-ap94-pci.o -+obj-$(CONFIG_AR71XX_DEV_AR913X_WMAC) += dev-ar913x-wmac.o -+obj-$(CONFIG_AR71XX_DEV_DSA) += dev-dsa.o -+obj-$(CONFIG_AR71XX_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o -+obj-$(CONFIG_AR71XX_DEV_LEDS_GPIO) += dev-leds-gpio.o -+obj-$(CONFIG_AR71XX_DEV_M25P80) += dev-m25p80.o -+obj-$(CONFIG_AR71XX_DEV_PB42_PCI) += dev-pb42-pci.o -+obj-$(CONFIG_AR71XX_DEV_PB9X_PCI) += dev-pb9x-pci.o -+obj-$(CONFIG_AR71XX_DEV_USB) += dev-usb.o -+ -+obj-$(CONFIG_AR71XX_NVRAM) += nvram.o -+ -+obj-$(CONFIG_AR71XX_MACH_AP81) += mach-ap81.o -+obj-$(CONFIG_AR71XX_MACH_AP83) += mach-ap83.o -+obj-$(CONFIG_AR71XX_MACH_AW_NR580) += mach-aw-nr580.o -+obj-$(CONFIG_AR71XX_MACH_DIR_600_A1) += mach-dir-600-a1.o -+obj-$(CONFIG_AR71XX_MACH_DIR_615_C1) += mach-dir-615-c1.o -+obj-$(CONFIG_AR71XX_MACH_DIR_825_B1) += mach-dir-825-b1.o -+obj-$(CONFIG_AR71XX_MACH_MZK_W04NU) += mach-mzk-w04nu.o -+obj-$(CONFIG_AR71XX_MACH_MZK_W300NH) += mach-mzk-w300nh.o -+obj-$(CONFIG_AR71XX_MACH_NBG460N) += mach-nbg460n.o -+obj-$(CONFIG_AR71XX_MACH_PB42) += mach-pb42.o -+obj-$(CONFIG_AR71XX_MACH_PB44) += mach-pb44.o -+obj-$(CONFIG_AR71XX_MACH_PB92) += mach-pb92.o -+obj-$(CONFIG_AR71XX_MACH_RB4XX) += mach-rb4xx.o -+obj-$(CONFIG_AR71XX_MACH_RB750) += mach-rb750.o -+obj-$(CONFIG_AR71XX_MACH_TEW_632BRP) += mach-tew-632brp.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR741ND) += mach-tl-wr741nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR841N_V1) += mach-tl-wr841n.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR941ND) += mach-tl-wr941nd.o -+obj-$(CONFIG_AR71XX_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o -+obj-$(CONFIG_AR71XX_MACH_UBNT) += mach-ubnt.o -+obj-$(CONFIG_AR71XX_MACH_WNDR3700) += mach-wndr3700.o -+obj-$(CONFIG_AR71XX_MACH_WNR2000) += mach-wnr2000.o -+obj-$(CONFIG_AR71XX_MACH_WP543) += mach-wp543.o -+obj-$(CONFIG_AR71XX_MACH_WRT160NL) += mach-wrt160nl.o -+obj-$(CONFIG_AR71XX_MACH_WRT400N) += mach-wrt400n.o -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/nvram.c linux-2.6.35.7/arch/mips/ar71xx/nvram.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/nvram.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/nvram.c 2010-10-14 20:27:58.555317270 +0200 -@@ -0,0 +1,75 @@ -+/* -+ * Atheros AR71xx minimal nvram support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include "nvram.h" -+ -+char *nvram_find_var(const char *name, const char *buf, unsigned buf_len) -+{ -+ unsigned len = strlen(name); -+ char *cur, *last; -+ -+ if (buf_len == 0 || len == 0) -+ return NULL; -+ -+ if (buf_len < len) -+ return NULL; -+ -+ if (len == 1) -+ return memchr(buf, (int) *name, buf_len); -+ -+ last = (char *) buf + buf_len - len; -+ for (cur = (char *) buf; cur <= last; cur++) -+ if (cur[0] == name[0] && memcmp(cur, name, len) == 0) -+ return cur + len; -+ -+ return NULL; -+} -+ -+int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, -+ const char *name, char *mac) -+{ -+ char *buf; -+ char *mac_str; -+ int ret; -+ int t; -+ -+ buf = vmalloc(nvram_len); -+ if (!buf) -+ return -ENOMEM; -+ -+ memcpy(buf, nvram, nvram_len); -+ buf[nvram_len - 1] = '\0'; -+ -+ mac_str = nvram_find_var(name, buf, nvram_len); -+ if (!mac_str) { -+ ret = -EINVAL; -+ goto free; -+ } -+ -+ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", -+ &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); -+ -+ if (t != 6) { -+ ret = -EINVAL; -+ goto free; -+ } -+ -+ ret = 0; -+ -+ free: -+ vfree(buf); -+ return ret; -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/nvram.h linux-2.6.35.7/arch/mips/ar71xx/nvram.h ---- linux-2.6.35.7.orig/arch/mips/ar71xx/nvram.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/nvram.h 2010-10-14 20:27:58.608101134 +0200 -@@ -0,0 +1,19 @@ -+/* -+ * Atheros AR71xx minimal nvram support -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef _AR71XX_NVRAM_H -+#define _AR71XX_NVRAM_H -+ -+char *nvram_find_var(const char *name, const char *buf, -+ unsigned buf_len) __init; -+int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, -+ const char *name, char *mac) __init; -+ -+#endif /* _AR71XX_NVRAM_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/pci.c linux-2.6.35.7/arch/mips/ar71xx/pci.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/pci.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/pci.c 2010-10-14 20:27:58.654350228 +0200 -@@ -0,0 +1,93 @@ -+/* -+ * Atheros AR71xx PCI setup code -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+ -+#include -+ -+#include -+#include -+ -+unsigned ar71xx_pci_nr_irqs __initdata; -+struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; -+ -+int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); -+ -+static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup) -+{ -+ int err = 0; -+ -+ err = ar71xx_pci_be_handler(is_fixup); -+ -+ return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL; -+} -+ -+int pcibios_plat_dev_init(struct pci_dev *dev) -+{ -+ if (ar71xx_pci_plat_dev_init) -+ return ar71xx_pci_plat_dev_init(dev); -+ -+ return 0; -+} -+ -+int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) -+{ -+ int ret = 0; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ret = ar71xx_pcibios_map_irq(dev, slot, pin); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ret = ar724x_pcibios_map_irq(dev, slot, pin); -+ break; -+ -+ default: -+ break; -+ } -+ -+ return ret; -+} -+ -+int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) -+{ -+ int ret = 0; -+ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ board_be_handler = ar71xx_be_handler; -+ ret = ar71xx_pcibios_init(); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ret = ar724x_pcibios_init(); -+ break; -+ -+ default: -+ return 0; -+ } -+ -+ ar71xx_pci_nr_irqs = nr_irqs; -+ ar71xx_pci_irq_map = map; -+ -+ return ret; -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/prom.c linux-2.6.35.7/arch/mips/ar71xx/prom.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/prom.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/prom.c 2010-10-14 20:27:58.704773879 +0200 -@@ -0,0 +1,105 @@ -+/* -+ * Atheros AR71xx SoC specific prom routines -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+#include -+#include -+ -+#include -+ -+static inline int is_valid_ram_addr(void *addr) -+{ -+ if (((u32) addr > KSEG0) && -+ ((u32) addr < (KSEG0 + AR71XX_MEM_SIZE_MAX))) -+ return 1; -+ -+ if (((u32) addr > KSEG1) && -+ ((u32) addr < (KSEG1 + AR71XX_MEM_SIZE_MAX))) -+ return 1; -+ -+ return 0; -+} -+ -+static void __init ar71xx_prom_append_cmdline(const char *name, -+ const char *value) -+{ -+ char buf[COMMAND_LINE_SIZE]; -+ -+ snprintf(buf, sizeof(buf), " %s=%s", name, value); -+ strlcat(arcs_cmdline, buf, sizeof(arcs_cmdline)); -+} -+ -+static void __init ar71xx_prom_find_env(char **envp, const char *name) -+{ -+ int len = strlen(name); -+ char **p; -+ -+ if (!is_valid_ram_addr(envp)) -+ return; -+ -+ for (p = envp; is_valid_ram_addr(*p); p++) { -+ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') { -+ ar71xx_prom_append_cmdline(name, *p + len + 1); -+ break; -+ } -+ -+ /* RedBoot env comes in pointer pairs - key, value */ -+ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0) -+ if (is_valid_ram_addr(*(++p))) { -+ ar71xx_prom_append_cmdline(name, *p); -+ break; -+ } -+ } -+} -+ -+static int inline ar71xx_use__image_cmdline(void) { return 0; } -+ -+static __init void ar71xx_prom_init_cmdline(int argc, char **argv) -+{ -+ int i; -+ -+ if (ar71xx_use__image_cmdline()) -+ return; -+ -+ if (!is_valid_ram_addr(argv)) -+ return; -+ -+ for (i = 0; i < argc; i++) -+ if (is_valid_ram_addr(argv[i])) { -+ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); -+ strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); -+ } -+} -+ -+void __init prom_init(void) -+{ -+ char **envp; -+ -+ printk(KERN_DEBUG "prom: fw_arg0=%08x, fw_arg1=%08x, " -+ "fw_arg2=%08x, fw_arg3=%08x\n", -+ (unsigned int)fw_arg0, (unsigned int)fw_arg1, -+ (unsigned int)fw_arg2, (unsigned int)fw_arg3); -+ -+ -+ ar71xx_prom_init_cmdline(fw_arg0, (char **)fw_arg1); -+ -+ envp = (char **)fw_arg2; -+ ar71xx_prom_find_env(envp, "board"); -+} -+ -+void __init prom_free_prom_memory(void) -+{ -+ /* We do not have to prom memory to free */ -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/ar71xx/setup.c linux-2.6.35.7/arch/mips/ar71xx/setup.c ---- linux-2.6.35.7.orig/arch/mips/ar71xx/setup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/ar71xx/setup.c 2010-10-14 20:27:58.754579813 +0200 -@@ -0,0 +1,310 @@ -+/* -+ * Atheros AR71xx SoC specific setup -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#include -+#include -+#include -+ -+#include -+#include /* for mips_hpt_frequency */ -+#include /* for _machine_{restart,halt} */ -+#include -+ -+#include -+ -+#include "machtype.h" -+#include "devices.h" -+ -+#define AR71XX_SYS_TYPE_LEN 64 -+#define AR71XX_BASE_FREQ 40000000 -+#define AR91XX_BASE_FREQ 5000000 -+#define AR724X_BASE_FREQ 5000000 -+ -+u32 ar71xx_cpu_freq; -+EXPORT_SYMBOL_GPL(ar71xx_cpu_freq); -+ -+u32 ar71xx_ahb_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ahb_freq); -+ -+u32 ar71xx_ddr_freq; -+EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); -+ -+enum ar71xx_soc_type ar71xx_soc; -+EXPORT_SYMBOL_GPL(ar71xx_soc); -+ -+static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; -+ -+static void ar71xx_restart(char *command) -+{ -+ ar71xx_device_stop(RESET_MODULE_FULL_CHIP); -+ for (;;) -+ if (cpu_wait) -+ cpu_wait(); -+} -+ -+static void ar71xx_halt(void) -+{ -+ while (1) -+ cpu_wait(); -+} -+ -+static void __init ar71xx_detect_mem_size(void) -+{ -+ unsigned long size; -+ -+ for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; -+ size <<= 1 ) { -+ if (!memcmp(ar71xx_detect_mem_size, -+ ar71xx_detect_mem_size + size, 1024)) -+ break; -+ } -+ -+ add_memory_region(0, size, BOOT_MEM_RAM); -+} -+ -+static void __init ar71xx_detect_sys_type(void) -+{ -+ char *chip = "????"; -+ u32 id; -+ u32 major; -+ u32 minor; -+ u32 rev = 0; -+ -+ id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID); -+ major = id & REV_ID_MAJOR_MASK; -+ -+ switch (major) { -+ case REV_ID_MAJOR_AR71XX: -+ minor = id & AR71XX_REV_ID_MINOR_MASK; -+ rev = id >> AR71XX_REV_ID_REVISION_SHIFT; -+ rev &= AR71XX_REV_ID_REVISION_MASK; -+ switch (minor) { -+ case AR71XX_REV_ID_MINOR_AR7130: -+ ar71xx_soc = AR71XX_SOC_AR7130; -+ chip = "7130"; -+ break; -+ -+ case AR71XX_REV_ID_MINOR_AR7141: -+ ar71xx_soc = AR71XX_SOC_AR7141; -+ chip = "7141"; -+ break; -+ -+ case AR71XX_REV_ID_MINOR_AR7161: -+ ar71xx_soc = AR71XX_SOC_AR7161; -+ chip = "7161"; -+ break; -+ } -+ break; -+ -+ case REV_ID_MAJOR_AR7240: -+ ar71xx_soc = AR71XX_SOC_AR7240; -+ chip = "7240"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR7241: -+ ar71xx_soc = AR71XX_SOC_AR7241; -+ chip = "7241"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR7242: -+ ar71xx_soc = AR71XX_SOC_AR7242; -+ chip = "7242"; -+ rev = (id & AR724X_REV_ID_REVISION_MASK); -+ break; -+ -+ case REV_ID_MAJOR_AR913X: -+ minor = id & AR91XX_REV_ID_MINOR_MASK; -+ rev = id >> AR91XX_REV_ID_REVISION_SHIFT; -+ rev &= AR91XX_REV_ID_REVISION_MASK; -+ switch (minor) { -+ case AR91XX_REV_ID_MINOR_AR9130: -+ ar71xx_soc = AR71XX_SOC_AR9130; -+ chip = "9130"; -+ break; -+ -+ case AR91XX_REV_ID_MINOR_AR9132: -+ ar71xx_soc = AR71XX_SOC_AR9132; -+ chip = "9132"; -+ break; -+ } -+ break; -+ -+ default: -+ panic("ar71xx: unknown chip id:0x%08x\n", id); -+ } -+ -+ sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); -+} -+ -+static void __init ar91xx_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); -+ freq = div * AR91XX_BASE_FREQ; -+ -+ ar71xx_cpu_freq = freq; -+ -+ div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar71xx_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; -+ freq = div * AR71XX_BASE_FREQ; -+ -+ div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; -+ ar71xx_cpu_freq = freq / div; -+ -+ div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init ar724x_detect_sys_frequency(void) -+{ -+ u32 pll; -+ u32 freq; -+ u32 div; -+ -+ pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG); -+ -+ div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); -+ freq = div * AR724X_BASE_FREQ; -+ -+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); -+ freq *= div; -+ -+ ar71xx_cpu_freq = freq; -+ -+ div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; -+ ar71xx_ddr_freq = freq / div; -+ -+ div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; -+ ar71xx_ahb_freq = ar71xx_cpu_freq / div; -+} -+ -+static void __init detect_sys_frequency(void) -+{ -+ switch (ar71xx_soc) { -+ case AR71XX_SOC_AR7130: -+ case AR71XX_SOC_AR7141: -+ case AR71XX_SOC_AR7161: -+ ar71xx_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR7240: -+ case AR71XX_SOC_AR7241: -+ case AR71XX_SOC_AR7242: -+ ar724x_detect_sys_frequency(); -+ break; -+ -+ case AR71XX_SOC_AR9130: -+ case AR71XX_SOC_AR9132: -+ ar91xx_detect_sys_frequency(); -+ break; -+ -+ default: -+ BUG(); -+ } -+} -+ -+const char *get_system_type(void) -+{ -+ return ar71xx_sys_type; -+} -+ -+unsigned int __cpuinit get_c0_compare_irq(void) -+{ -+ return CP0_LEGACY_COMPARE_IRQ; -+} -+ -+void __init plat_mem_setup(void) -+{ -+ set_io_port_base(KSEG1); -+ -+ ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, -+ AR71XX_DDR_CTRL_SIZE); -+ -+ ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE, -+ AR71XX_PLL_SIZE); -+ -+ ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE, -+ AR71XX_RESET_SIZE); -+ -+ ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); -+ -+ ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE, -+ AR71XX_USB_CTRL_SIZE); -+ -+ ar71xx_detect_mem_size(); -+ ar71xx_detect_sys_type(); -+ detect_sys_frequency(); -+ -+ printk(KERN_INFO -+ "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n", -+ ar71xx_sys_type, -+ ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000, -+ ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000, -+ ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000); -+ -+ _machine_restart = ar71xx_restart; -+ _machine_halt = ar71xx_halt; -+ pm_power_off = ar71xx_halt; -+} -+ -+void __init plat_time_init(void) -+{ -+ mips_hpt_frequency = ar71xx_cpu_freq / 2; -+} -+ -+__setup("board=", mips_machtype_setup); -+ -+static int __init ar71xx_machine_setup(void) -+{ -+ ar71xx_gpio_init(); -+ -+ ar71xx_add_device_uart(); -+ ar71xx_add_device_wdt(); -+ -+ mips_machine_setup(); -+ return 0; -+} -+ -+arch_initcall(ar71xx_machine_setup); -+ -+static void __init ar71xx_generic_init(void) -+{ -+ /* Nothing to do */ -+} -+ -+MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board", -+ ar71xx_generic_init); -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/ar71xx.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/ar71xx.h 2010-10-14 20:27:58.804410665 +0200 -@@ -0,0 +1,514 @@ -+/* -+ * Atheros AR71xx SoC specific definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_H -+#define __ASM_MACH_AR71XX_H -+ -+#include -+#include -+#include -+#include -+ -+#ifndef __ASSEMBLER__ -+ -+#define AR71XX_PCI_MEM_BASE 0x10000000 -+#define AR71XX_PCI_MEM_SIZE 0x08000000 -+#define AR71XX_APB_BASE 0x18000000 -+#define AR71XX_GE0_BASE 0x19000000 -+#define AR71XX_GE0_SIZE 0x01000000 -+#define AR71XX_GE1_BASE 0x1a000000 -+#define AR71XX_GE1_SIZE 0x01000000 -+#define AR71XX_EHCI_BASE 0x1b000000 -+#define AR71XX_EHCI_SIZE 0x01000000 -+#define AR71XX_OHCI_BASE 0x1c000000 -+#define AR71XX_OHCI_SIZE 0x01000000 -+#define AR7240_OHCI_BASE 0x1b000000 -+#define AR7240_OHCI_SIZE 0x01000000 -+#define AR71XX_SPI_BASE 0x1f000000 -+#define AR71XX_SPI_SIZE 0x01000000 -+ -+#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) -+#define AR71XX_DDR_CTRL_SIZE 0x10000 -+#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000) -+#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) -+#define AR71XX_UART_SIZE 0x10000 -+#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) -+#define AR71XX_USB_CTRL_SIZE 0x10000 -+#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) -+#define AR71XX_GPIO_SIZE 0x10000 -+#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) -+#define AR71XX_PLL_SIZE 0x10000 -+#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) -+#define AR71XX_RESET_SIZE 0x10000 -+#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) -+#define AR71XX_MII_SIZE 0x10000 -+#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000) -+#define AR71XX_SLIC_SIZE 0x10000 -+#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000) -+#define AR71XX_DMA_SIZE 0x10000 -+#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) -+#define AR71XX_STEREO_SIZE 0x10000 -+ -+#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) -+#define AR724X_PCI_CRP_SIZE 0x100 -+ -+#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) -+#define AR724X_PCI_CTRL_SIZE 0x100 -+ -+#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) -+#define AR91XX_WMAC_SIZE 0x30000 -+ -+#define AR71XX_MEM_SIZE_MIN 0x0200000 -+#define AR71XX_MEM_SIZE_MAX 0x10000000 -+ -+#define AR71XX_CPU_IRQ_BASE 0 -+#define AR71XX_MISC_IRQ_BASE 8 -+#define AR71XX_MISC_IRQ_COUNT 8 -+#define AR71XX_GPIO_IRQ_BASE 16 -+#define AR71XX_GPIO_IRQ_COUNT 32 -+#define AR71XX_PCI_IRQ_BASE 48 -+#define AR71XX_PCI_IRQ_COUNT 8 -+ -+#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) -+#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) -+#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) -+#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) -+#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6) -+#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7) -+ -+#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0) -+#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1) -+#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2) -+#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3) -+#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4) -+#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) -+#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) -+#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) -+ -+#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) -+ -+#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0) -+#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1) -+#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2) -+#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4) -+ -+extern u32 ar71xx_ahb_freq; -+extern u32 ar71xx_cpu_freq; -+extern u32 ar71xx_ddr_freq; -+ -+enum ar71xx_soc_type { -+ AR71XX_SOC_UNKNOWN, -+ AR71XX_SOC_AR7130, -+ AR71XX_SOC_AR7141, -+ AR71XX_SOC_AR7161, -+ AR71XX_SOC_AR7240, -+ AR71XX_SOC_AR7241, -+ AR71XX_SOC_AR7242, -+ AR71XX_SOC_AR9130, -+ AR71XX_SOC_AR9132 -+}; -+ -+extern enum ar71xx_soc_type ar71xx_soc; -+ -+/* -+ * PLL block -+ */ -+#define AR71XX_PLL_REG_CPU_CONFIG 0x00 -+#define AR71XX_PLL_REG_SEC_CONFIG 0x04 -+#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 -+#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 -+ -+#define AR71XX_PLL_DIV_SHIFT 3 -+#define AR71XX_PLL_DIV_MASK 0x1f -+#define AR71XX_CPU_DIV_SHIFT 16 -+#define AR71XX_CPU_DIV_MASK 0x3 -+#define AR71XX_DDR_DIV_SHIFT 18 -+#define AR71XX_DDR_DIV_MASK 0x3 -+#define AR71XX_AHB_DIV_SHIFT 20 -+#define AR71XX_AHB_DIV_MASK 0x7 -+ -+#define AR71XX_ETH0_PLL_SHIFT 17 -+#define AR71XX_ETH1_PLL_SHIFT 19 -+ -+#define AR724X_PLL_REG_CPU_CONFIG 0x00 -+#define AR724X_PLL_REG_PCIE_CONFIG 0x18 -+ -+#define AR724X_PLL_DIV_SHIFT 0 -+#define AR724X_PLL_DIV_MASK 0x3ff -+#define AR724X_PLL_REF_DIV_SHIFT 10 -+#define AR724X_PLL_REF_DIV_MASK 0xf -+#define AR724X_AHB_DIV_SHIFT 19 -+#define AR724X_AHB_DIV_MASK 0x1 -+#define AR724X_DDR_DIV_SHIFT 22 -+#define AR724X_DDR_DIV_MASK 0x3 -+ -+#define AR91XX_PLL_REG_CPU_CONFIG 0x00 -+#define AR91XX_PLL_REG_ETH_CONFIG 0x04 -+#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 -+#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 -+ -+#define AR91XX_PLL_DIV_SHIFT 0 -+#define AR91XX_PLL_DIV_MASK 0x3ff -+#define AR91XX_DDR_DIV_SHIFT 22 -+#define AR91XX_DDR_DIV_MASK 0x3 -+#define AR91XX_AHB_DIV_SHIFT 19 -+#define AR91XX_AHB_DIV_MASK 0x1 -+ -+#define AR91XX_ETH0_PLL_SHIFT 20 -+#define AR91XX_ETH1_PLL_SHIFT 22 -+ -+extern void __iomem *ar71xx_pll_base; -+ -+static inline void ar71xx_pll_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_pll_base + reg); -+} -+ -+static inline u32 ar71xx_pll_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_pll_base + reg); -+} -+ -+/* -+ * USB_CONFIG block -+ */ -+#define USB_CTRL_REG_FLADJ 0x00 -+#define USB_CTRL_REG_CONFIG 0x04 -+ -+extern void __iomem *ar71xx_usb_ctrl_base; -+ -+static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_usb_ctrl_base + reg); -+} -+ -+static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_usb_ctrl_base + reg); -+} -+ -+/* -+ * GPIO block -+ */ -+#define GPIO_REG_OE 0x00 -+#define GPIO_REG_IN 0x04 -+#define GPIO_REG_OUT 0x08 -+#define GPIO_REG_SET 0x0c -+#define GPIO_REG_CLEAR 0x10 -+#define GPIO_REG_INT_MODE 0x14 -+#define GPIO_REG_INT_TYPE 0x18 -+#define GPIO_REG_INT_POLARITY 0x1c -+#define GPIO_REG_INT_PENDING 0x20 -+#define GPIO_REG_INT_ENABLE 0x24 -+#define GPIO_REG_FUNC 0x28 -+ -+#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) -+#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) -+#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) -+#define AR71XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) -+#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) -+ -+#define AR71XX_GPIO_COUNT 16 -+ -+#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) -+#define AR724X_GPIO_FUNC_SPI_EN BIT(18) -+#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) -+#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) -+#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) -+#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) -+#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) -+#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) -+#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) -+#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) -+#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) -+#define AR724X_GPIO_FUNC_UART_EN BIT(1) -+#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) -+ -+#define AR724X_GPIO_COUNT 18 -+ -+#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22) -+#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) -+#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20) -+#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19) -+#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18) -+#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17) -+#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16) -+#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9) -+#define AR91XX_GPIO_FUNC_UART_EN BIT(8) -+#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4) -+ -+#define AR91XX_GPIO_COUNT 22 -+ -+extern void __iomem *ar71xx_gpio_base; -+ -+static inline void ar71xx_gpio_wr(unsigned reg, u32 value) -+{ -+ __raw_writel(value, ar71xx_gpio_base + reg); -+} -+ -+static inline u32 ar71xx_gpio_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_gpio_base + reg); -+} -+ -+void ar71xx_gpio_init(void) __init; -+void ar71xx_gpio_function_enable(u32 mask); -+void ar71xx_gpio_function_disable(u32 mask); -+void ar71xx_gpio_function_setup(u32 set, u32 clear); -+ -+/* -+ * DDR_CTRL block -+ */ -+#define AR71XX_DDR_REG_PCI_WIN0 0x7c -+#define AR71XX_DDR_REG_PCI_WIN1 0x80 -+#define AR71XX_DDR_REG_PCI_WIN2 0x84 -+#define AR71XX_DDR_REG_PCI_WIN3 0x88 -+#define AR71XX_DDR_REG_PCI_WIN4 0x8c -+#define AR71XX_DDR_REG_PCI_WIN5 0x90 -+#define AR71XX_DDR_REG_PCI_WIN6 0x94 -+#define AR71XX_DDR_REG_PCI_WIN7 0x98 -+#define AR71XX_DDR_REG_FLUSH_GE0 0x9c -+#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 -+#define AR71XX_DDR_REG_FLUSH_USB 0xa4 -+#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 -+ -+#define AR724X_DDR_REG_FLUSH_GE0 0x7c -+#define AR724X_DDR_REG_FLUSH_GE1 0x80 -+#define AR724X_DDR_REG_FLUSH_USB 0x84 -+#define AR724X_DDR_REG_FLUSH_PCIE 0x88 -+ -+#define AR91XX_DDR_REG_FLUSH_GE0 0x7c -+#define AR91XX_DDR_REG_FLUSH_GE1 0x80 -+#define AR91XX_DDR_REG_FLUSH_USB 0x84 -+#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 -+ -+#define PCI_WIN0_OFFS 0x10000000 -+#define PCI_WIN1_OFFS 0x11000000 -+#define PCI_WIN2_OFFS 0x12000000 -+#define PCI_WIN3_OFFS 0x13000000 -+#define PCI_WIN4_OFFS 0x14000000 -+#define PCI_WIN5_OFFS 0x15000000 -+#define PCI_WIN6_OFFS 0x16000000 -+#define PCI_WIN7_OFFS 0x07000000 -+ -+extern void __iomem *ar71xx_ddr_base; -+ -+static inline void ar71xx_ddr_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_ddr_base + reg); -+} -+ -+static inline u32 ar71xx_ddr_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_ddr_base + reg); -+} -+ -+void ar71xx_ddr_flush(u32 reg); -+ -+/* -+ * PCI block -+ */ -+#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000) -+#define AR71XX_PCI_CFG_SIZE 0x100 -+ -+#define PCI_REG_CRP_AD_CBE 0x00 -+#define PCI_REG_CRP_WRDATA 0x04 -+#define PCI_REG_CRP_RDDATA 0x08 -+#define PCI_REG_CFG_AD 0x0c -+#define PCI_REG_CFG_CBE 0x10 -+#define PCI_REG_CFG_WRDATA 0x14 -+#define PCI_REG_CFG_RDDATA 0x18 -+#define PCI_REG_PCI_ERR 0x1c -+#define PCI_REG_PCI_ERR_ADDR 0x20 -+#define PCI_REG_AHB_ERR 0x24 -+#define PCI_REG_AHB_ERR_ADDR 0x28 -+ -+#define PCI_CRP_CMD_WRITE 0x00010000 -+#define PCI_CRP_CMD_READ 0x00000000 -+#define PCI_CFG_CMD_READ 0x0000000a -+#define PCI_CFG_CMD_WRITE 0x0000000b -+ -+#define PCI_IDSEL_ADL_START 17 -+ -+#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000) -+#define AR724X_PCI_CFG_SIZE 0x1000 -+ -+#define AR724X_PCI_REG_APP 0x00 -+#define AR724X_PCI_REG_RESET 0x18 -+#define AR724X_PCI_REG_INT_STATUS 0x4c -+#define AR724X_PCI_REG_INT_MASK 0x50 -+ -+#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) -+#define AR724X_PCI_RESET_LINK_UP BIT(0) -+ -+#define AR724X_PCI_INT_DEV0 BIT(14) -+ -+/* -+ * RESET block -+ */ -+#define AR71XX_RESET_REG_TIMER 0x00 -+#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 -+#define AR71XX_RESET_REG_WDOG_CTRL 0x08 -+#define AR71XX_RESET_REG_WDOG 0x0c -+#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 -+#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 -+#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 -+#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c -+#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 -+#define AR71XX_RESET_REG_RESET_MODULE 0x24 -+#define AR71XX_RESET_REG_PERFC_CTRL 0x2c -+#define AR71XX_RESET_REG_PERFC0 0x30 -+#define AR71XX_RESET_REG_PERFC1 0x34 -+#define AR71XX_RESET_REG_REV_ID 0x90 -+ -+#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18 -+#define AR91XX_RESET_REG_RESET_MODULE 0x1c -+#define AR91XX_RESET_REG_PERF_CTRL 0x20 -+#define AR91XX_RESET_REG_PERFC0 0x24 -+#define AR91XX_RESET_REG_PERFC1 0x28 -+ -+#define AR724X_RESET_REG_RESET_MODULE 0x1c -+ -+#define WDOG_CTRL_LAST_RESET BIT(31) -+#define WDOG_CTRL_ACTION_MASK 3 -+#define WDOG_CTRL_ACTION_NONE 0 /* no action */ -+#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ -+#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ -+#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ -+ -+#define MISC_INT_DMA BIT(7) -+#define MISC_INT_OHCI BIT(6) -+#define MISC_INT_PERFC BIT(5) -+#define MISC_INT_WDOG BIT(4) -+#define MISC_INT_UART BIT(3) -+#define MISC_INT_GPIO BIT(2) -+#define MISC_INT_ERROR BIT(1) -+#define MISC_INT_TIMER BIT(0) -+ -+#define PCI_INT_CORE BIT(4) -+#define PCI_INT_DEV2 BIT(2) -+#define PCI_INT_DEV1 BIT(1) -+#define PCI_INT_DEV0 BIT(0) -+ -+#define RESET_MODULE_EXTERNAL BIT(28) -+#define RESET_MODULE_FULL_CHIP BIT(24) -+#define RESET_MODULE_AMBA2WMAC BIT(22) -+#define RESET_MODULE_CPU_NMI BIT(21) -+#define RESET_MODULE_CPU_COLD BIT(20) -+#define RESET_MODULE_DMA BIT(19) -+#define RESET_MODULE_SLIC BIT(18) -+#define RESET_MODULE_STEREO BIT(17) -+#define RESET_MODULE_DDR BIT(16) -+#define RESET_MODULE_GE1_MAC BIT(13) -+#define RESET_MODULE_GE1_PHY BIT(12) -+#define RESET_MODULE_USBSUS_OVERRIDE BIT(10) -+#define RESET_MODULE_GE0_MAC BIT(9) -+#define RESET_MODULE_GE0_PHY BIT(8) -+#define RESET_MODULE_USB_OHCI_DLL BIT(6) -+#define RESET_MODULE_USB_HOST BIT(5) -+#define RESET_MODULE_USB_PHY BIT(4) -+#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3) -+#define RESET_MODULE_PCI_BUS BIT(1) -+#define RESET_MODULE_PCI_CORE BIT(0) -+ -+#define AR724X_RESET_GE1_MDIO BIT(23) -+#define AR724X_RESET_GE0_MDIO BIT(22) -+#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) -+#define AR724X_RESET_PCIE_PHY BIT(7) -+#define AR724X_RESET_PCIE BIT(6) -+ -+#define REV_ID_MAJOR_MASK 0xfff0 -+#define REV_ID_MAJOR_AR71XX 0x00a0 -+#define REV_ID_MAJOR_AR913X 0x00b0 -+#define REV_ID_MAJOR_AR7240 0x00c0 -+#define REV_ID_MAJOR_AR7241 0x0100 -+#define REV_ID_MAJOR_AR7242 0x1100 -+ -+#define AR71XX_REV_ID_MINOR_MASK 0x3 -+#define AR71XX_REV_ID_MINOR_AR7130 0x0 -+#define AR71XX_REV_ID_MINOR_AR7141 0x1 -+#define AR71XX_REV_ID_MINOR_AR7161 0x2 -+#define AR71XX_REV_ID_REVISION_MASK 0x3 -+#define AR71XX_REV_ID_REVISION_SHIFT 2 -+ -+#define AR91XX_REV_ID_MINOR_MASK 0x3 -+#define AR91XX_REV_ID_MINOR_AR9130 0x0 -+#define AR91XX_REV_ID_MINOR_AR9132 0x1 -+#define AR91XX_REV_ID_REVISION_MASK 0x3 -+#define AR91XX_REV_ID_REVISION_SHIFT 2 -+ -+#define AR724X_REV_ID_REVISION_MASK 0x3 -+ -+extern void __iomem *ar71xx_reset_base; -+ -+static inline void ar71xx_reset_wr(unsigned reg, u32 val) -+{ -+ __raw_writel(val, ar71xx_reset_base + reg); -+} -+ -+static inline u32 ar71xx_reset_rr(unsigned reg) -+{ -+ return __raw_readl(ar71xx_reset_base + reg); -+} -+ -+void ar71xx_device_stop(u32 mask); -+void ar71xx_device_start(u32 mask); -+int ar71xx_device_stopped(u32 mask); -+ -+/* -+ * SPI block -+ */ -+#define SPI_REG_FS 0x00 /* Function Select */ -+#define SPI_REG_CTRL 0x04 /* SPI Control */ -+#define SPI_REG_IOC 0x08 /* SPI I/O Control */ -+#define SPI_REG_RDS 0x0c /* Read Data Shift */ -+ -+#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ -+ -+#define SPI_CTRL_RD BIT(6) /* Remap Disable */ -+#define SPI_CTRL_DIV_MASK 0x3f -+ -+#define SPI_IOC_DO BIT(0) /* Data Out pin */ -+#define SPI_IOC_CLK BIT(8) /* CLK pin */ -+#define SPI_IOC_CS(n) BIT(16 + (n)) -+#define SPI_IOC_CS0 SPI_IOC_CS(0) -+#define SPI_IOC_CS1 SPI_IOC_CS(1) -+#define SPI_IOC_CS2 SPI_IOC_CS(2) -+#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2) -+ -+void ar71xx_flash_acquire(void); -+void ar71xx_flash_release(void); -+ -+/* -+ * MII_CTRL block -+ */ -+#define MII_REG_MII0_CTRL 0x00 -+#define MII_REG_MII1_CTRL 0x04 -+ -+#define MII0_CTRL_IF_GMII 0 -+#define MII0_CTRL_IF_MII 1 -+#define MII0_CTRL_IF_RGMII 2 -+#define MII0_CTRL_IF_RMII 3 -+ -+#define MII1_CTRL_IF_RGMII 0 -+#define MII1_CTRL_IF_RMII 1 -+ -+#endif /* __ASSEMBLER__ */ -+ -+#endif /* __ASM_MACH_AR71XX_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 2010-10-14 20:27:58.848101151 +0200 -@@ -0,0 +1,26 @@ -+/* -+ * AR91xx parallel flash driver platform data definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __AR91XX_FLASH_H -+#define __AR91XX_FLASH_H -+ -+struct mtd_partition; -+ -+struct ar91xx_flash_platform_data { -+ unsigned int width; -+ u8 is_shared:1; -+#ifdef CONFIG_MTD_PARTITIONS -+ unsigned int nr_parts; -+ struct mtd_partition *parts; -+#endif -+}; -+ -+#endif /* __AR91XX_FLASH_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 2010-10-14 20:27:58.895601086 +0200 -@@ -0,0 +1,56 @@ -+/* -+ * Atheros AR71xx specific CPU feature overrides -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H -+ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+#define cpu_has_watch 1 -+#define cpu_has_divec 1 -+ -+#define cpu_has_prefetch 1 -+#define cpu_has_ejtag 1 -+#define cpu_has_llsc 1 -+ -+#define cpu_has_mips16 1 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+#define cpu_has_mips32r1 1 -+#define cpu_has_mips32r2 1 -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 0 -+#define cpu_has_mipsmt 0 -+ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+#define cpu_dcache_line_size() 32 -+#define cpu_icache_line_size() 32 -+ -+#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/gpio.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/gpio.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/gpio.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/gpio.h 2010-10-14 20:27:58.945582628 +0200 -@@ -0,0 +1,53 @@ -+/* -+ * Atheros AR71xx GPIO API definitions -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_GPIO_H -+#define __ASM_MACH_AR71XX_GPIO_H -+ -+#define ARCH_NR_GPIOS 64 -+#include -+ -+#include -+ -+extern unsigned long ar71xx_gpio_count; -+extern void __ar71xx_gpio_set_value(unsigned gpio, int value); -+extern int __ar71xx_gpio_get_value(unsigned gpio); -+ -+static inline int gpio_to_irq(unsigned gpio) -+{ -+ return AR71XX_GPIO_IRQ(gpio); -+} -+ -+static inline int irq_to_gpio(unsigned irq) -+{ -+ return irq - AR71XX_GPIO_IRQ_BASE; -+} -+ -+static inline int gpio_get_value(unsigned gpio) -+{ -+ if (gpio < ar71xx_gpio_count) -+ return __ar71xx_gpio_get_value(gpio); -+ -+ return __gpio_get_value(gpio); -+} -+ -+static inline void gpio_set_value(unsigned gpio, int value) -+{ -+ if (gpio < ar71xx_gpio_count) -+ __ar71xx_gpio_set_value(gpio, value); -+ else -+ __gpio_set_value(gpio, value); -+} -+ -+#define gpio_cansleep __gpio_cansleep -+ -+#endif /* __ASM_MACH_AR71XX_GPIO_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/irq.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/irq.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/irq.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/irq.h 2010-10-14 20:27:58.994356523 +0200 -@@ -0,0 +1,17 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#ifndef __ASM_MACH_AR71XX_IRQ_H -+#define __ASM_MACH_AR71XX_IRQ_H -+ -+#define MIPS_CPU_IRQ_BASE 0 -+#define NR_IRQS 56 -+ -+#include_next -+ -+#endif /* __ASM_MACH_AR71XX_IRQ_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 2010-10-14 20:27:59.045181409 +0200 -@@ -0,0 +1,32 @@ -+/* -+ * Atheros AR71xx specific kernel entry setup -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H -+#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H -+ -+ /* -+ * Some bootloaders set the 'Kseg0 coherency algorithm' to -+ * 'Cacheable, noncoherent, write-through, no write allocate' -+ * and this cause performance issues. Let's go and change it to -+ * 'Cacheable, noncoherent, write-back, write allocate' -+ */ -+ .macro kernel_entry_setup -+ mfc0 t0, CP0_CONFIG -+ li t1, ~CONF_CM_CMASK -+ and t0, t1 -+ ori t0, CONF_CM_CACHABLE_NONCOHERENT -+ mtc0 t0, CP0_CONFIG -+ nop -+ .endm -+ -+ .macro smp_slave_setup -+ .endm -+ -+#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/mach-rb750.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 2010-10-14 20:27:59.095024740 +0200 -@@ -0,0 +1,66 @@ -+/* -+ * MikroTik RouterBOARD 750 definitions -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+#ifndef _MACH_RB750_H -+#define _MACH_RB750_H -+ -+#include -+ -+#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ -+#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ -+#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ -+#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ -+#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ -+#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ -+#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ -+#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ -+#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ -+#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ -+#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ -+#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ -+#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ -+#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ -+#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ -+ -+#define RB750_GPIO_BTN_RESET 1 -+#define RB750_GPIO_SPI_CS0 2 -+#define RB750_GPIO_LED_ACT 12 -+#define RB750_GPIO_LED_PORT1 13 -+#define RB750_GPIO_LED_PORT2 14 -+#define RB750_GPIO_LED_PORT3 15 -+#define RB750_GPIO_LED_PORT4 16 -+#define RB750_GPIO_LED_PORT5 17 -+ -+#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) -+#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) -+#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) -+#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) -+#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) -+#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) -+ -+#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) -+ -+#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ -+ RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) -+ -+struct rb750_led_data { -+ char *name; -+ char *default_trigger; -+ u32 mask; -+ int active_low; -+}; -+ -+struct rb750_led_platform_data { -+ int num_leds; -+ struct rb750_led_data *leds; -+}; -+ -+int rb750_latch_change(u32 mask_clr, u32 mask_set); -+ -+#endif /* _MACH_RB750_H */ -\ No newline at end of file -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/mangle-port.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/mangle-port.h 2010-10-14 20:27:59.144833241 +0200 -@@ -0,0 +1,45 @@ -+/* -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H -+#define __ASM_MACH_AR71XX_MANGLE_PORT_H -+ -+#define __swizzle_addr_b(port) ((port) ^ 3) -+#define __swizzle_addr_w(port) ((port) ^ 2) -+#define __swizzle_addr_l(port) (port) -+#define __swizzle_addr_q(port) (port) -+ -+#if defined(CONFIG_SWAP_IO_SPACE) -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) le16_to_cpu(x) -+# define __mem_ioswabw(a, x) (x) -+# define ioswabl(a, x) le32_to_cpu(x) -+# define __mem_ioswabl(a, x) (x) -+# define ioswabq(a, x) le64_to_cpu(x) -+# define __mem_ioswabq(a, x) (x) -+ -+#else -+ -+# define ioswabb(a, x) (x) -+# define __mem_ioswabb(a, x) (x) -+# define ioswabw(a, x) (x) -+# define __mem_ioswabw(a, x) cpu_to_le16(x) -+# define ioswabl(a, x) (x) -+# define __mem_ioswabl(a, x) cpu_to_le32(x) -+# define ioswabq(a, x) (x) -+# define __mem_ioswabq(a, x) cpu_to_le64(x) -+ -+#endif -+ -+#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/pci.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/pci.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/pci.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/pci.h 2010-10-14 20:27:59.194642423 +0200 -@@ -0,0 +1,39 @@ -+/* -+ * Atheros AR71xx SoC specific PCI definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_PCI_H -+#define __ASM_MACH_AR71XX_PCI_H -+ -+struct pci_dev; -+ -+struct ar71xx_pci_irq { -+ int irq; -+ u8 slot; -+ u8 pin; -+}; -+ -+extern int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); -+extern unsigned ar71xx_pci_nr_irqs __initdata; -+extern struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; -+ -+int ar71xx_pcibios_map_irq(const struct pci_dev *dev, -+ uint8_t slot, uint8_t pin) __init; -+int ar71xx_pcibios_init(void) __init; -+ -+int ar71xx_pci_be_handler(int is_fixup); -+ -+int ar724x_pcibios_map_irq(const struct pci_dev *dev, -+ uint8_t slot, uint8_t pin) __init; -+int ar724x_pcibios_init(void) __init; -+ -+int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init; -+ -+#endif /* __ASM_MACH_AR71XX_PCI_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/platform.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/platform.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/platform.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/platform.h 2010-10-14 20:27:59.252778691 +0200 -@@ -0,0 +1,61 @@ -+/* -+ * Atheros AR71xx SoC specific platform data definitions -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ -+ -+#ifndef __ASM_MACH_AR71XX_PLATFORM_H -+#define __ASM_MACH_AR71XX_PLATFORM_H -+ -+#include -+#include -+#include -+#include -+ -+struct ag71xx_platform_data { -+ phy_interface_t phy_if_mode; -+ u32 phy_mask; -+ int speed; -+ int duplex; -+ u32 reset_bit; -+ u32 mii_if; -+ u8 mac_addr[ETH_ALEN]; -+ struct device *mii_bus_dev; -+ -+ u8 has_gbit:1; -+ u8 is_ar91xx:1; -+ u8 is_ar724x:1; -+ u8 has_ar8216:1; -+ -+ void (* ddr_flush)(void); -+ void (* set_pll)(int speed); -+ -+ u32 fifo_cfg1; -+ u32 fifo_cfg2; -+ u32 fifo_cfg3; -+}; -+ -+struct ag71xx_mdio_platform_data { -+ u32 phy_mask; -+ int is_ar7240; -+}; -+ -+struct ar71xx_ehci_platform_data { -+ u8 is_ar91xx; -+}; -+ -+struct ar71xx_spi_platform_data { -+ unsigned bus_num; -+ unsigned num_chipselect; -+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on); -+}; -+ -+#define AR71XX_SPI_CS_INACTIVE 0 -+#define AR71XX_SPI_CS_ACTIVE 1 -+ -+#endif /* __ASM_MACH_AR71XX_PLATFORM_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/war.h linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/war.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mach-ar71xx/war.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mach-ar71xx/war.h 2010-10-14 20:27:59.295939760 +0200 -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle -+ */ -+#ifndef __ASM_MACH_AR71XX_WAR_H -+#define __ASM_MACH_AR71XX_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MACH_AR71XX_WAR_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/mips_machine.h linux-2.6.35.7/arch/mips/include/asm/mips_machine.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/mips_machine.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/include/asm/mips_machine.h 2010-10-14 20:27:59.335601098 +0200 -@@ -0,0 +1,54 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+ -+#ifndef __ASM_MIPS_MACHINE_H -+#define __ASM_MIPS_MACHINE_H -+ -+#include -+#include -+ -+#include -+ -+struct mips_machine { -+ unsigned long mach_type; -+ char *mach_id; -+ char *mach_name; -+ void (*mach_setup)(void); -+ struct list_head list; -+}; -+ -+void mips_machine_register(struct mips_machine *) __init; -+void mips_machine_setup(void) __init; -+int mips_machtype_setup(char *id) __init; -+void mips_machine_set_name(char *name) __init; -+ -+extern char *mips_machine_name; -+ -+#define MIPS_MACHINE(_type, _id, _name, _setup) \ -+static const char machine_name_##_type[] __initconst \ -+ __aligned(1) = _name; \ -+static const char machine_id_##_type[] __initconst \ -+ __aligned(1) = _id; \ -+static struct mips_machine machine_##_type __initdata = \ -+{ \ -+ .mach_type = _type, \ -+ .mach_id = (char *) machine_id_##_type, \ -+ .mach_name = (char *) machine_name_##_type, \ -+ .mach_setup = _setup, \ -+}; \ -+ \ -+static int __init register_machine_##_type(void) \ -+{ \ -+ mips_machine_register(&machine_##_type); \ -+ return 0; \ -+} \ -+ \ -+pure_initcall(register_machine_##_type) -+ -+#endif /* __ASM_MIPS_MACHINE_H */ -diff -Nur linux-2.6.35.7.orig/arch/mips/include/asm/time.h linux-2.6.35.7/arch/mips/include/asm/time.h ---- linux-2.6.35.7.orig/arch/mips/include/asm/time.h 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/arch/mips/include/asm/time.h 2010-10-14 20:27:59.385601208 +0200 -@@ -52,6 +52,7 @@ - */ - #ifdef CONFIG_CEVT_R4K_LIB - extern unsigned int __weak get_c0_compare_int(void); -+extern unsigned int __weak get_c0_compare_irq(void); - extern int r4k_clockevent_init(void); - #endif - -diff -Nur linux-2.6.35.7.orig/arch/mips/Kconfig linux-2.6.35.7/arch/mips/Kconfig ---- linux-2.6.35.7.orig/arch/mips/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/arch/mips/Kconfig 2010-10-14 20:27:59.436851139 +0200 -@@ -48,6 +48,23 @@ - Support for the Texas Instruments AR7 System-on-a-Chip - family: TNETD7100, 7200 and 7300. - -+config ATHEROS_AR71XX -+ bool "Atheros AR71xx based boards" -+ select CEVT_R4K -+ select CSRC_R4K -+ select DMA_NONCOHERENT -+ select HW_HAS_PCI -+ select IRQ_CPU -+ select ARCH_REQUIRE_GPIOLIB -+ select SYS_HAS_CPU_MIPS32_R1 -+ select SYS_HAS_CPU_MIPS32_R2 -+ select SYS_SUPPORTS_32BIT_KERNEL -+ select SYS_SUPPORTS_BIG_ENDIAN -+ select SYS_HAS_EARLY_PRINTK -+ select MIPS_MACHINE -+ help -+ Support for Atheros AR71xx based boards. -+ - config BCM47XX - bool "Broadcom BCM47XX based boards" - select CEVT_R4K -@@ -684,6 +701,7 @@ - endchoice - - source "arch/mips/alchemy/Kconfig" -+source "arch/mips/ar71xx/Kconfig" - source "arch/mips/bcm63xx/Kconfig" - source "arch/mips/jazz/Kconfig" - source "arch/mips/lasat/Kconfig" -@@ -850,9 +868,15 @@ - config MIPS_DISABLE_OBSOLETE_IDE - bool - -+config MYLOADER -+ bool -+ - config SYNC_R4K - bool - -+config MIPS_MACHINE -+ def_bool n -+ - config NO_IOPORT - def_bool n - -diff -Nur linux-2.6.35.7.orig/arch/mips/kernel/Makefile linux-2.6.35.7/arch/mips/kernel/Makefile ---- linux-2.6.35.7.orig/arch/mips/kernel/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/arch/mips/kernel/Makefile 2010-10-14 20:27:59.485313916 +0200 -@@ -93,6 +93,7 @@ - - obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o - obj-$(CONFIG_EARLY_PRINTK) += early_printk.o -+obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o - obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o - - CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) -diff -Nur linux-2.6.35.7.orig/arch/mips/kernel/mips_machine.c linux-2.6.35.7/arch/mips/kernel/mips_machine.c ---- linux-2.6.35.7.orig/arch/mips/kernel/mips_machine.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/kernel/mips_machine.c 2010-10-14 20:27:59.536722433 +0200 -@@ -0,0 +1,121 @@ -+/* -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+ -+#include -+ -+static struct list_head mips_machines __initdata = -+ LIST_HEAD_INIT(mips_machines); -+static char *mips_machid __initdata; -+ -+char *mips_machine_name = "Unknown"; -+ -+static struct mips_machine * __init mips_machine_find(unsigned long machtype) -+{ -+ struct list_head *this; -+ -+ list_for_each(this, &mips_machines) { -+ struct mips_machine *mach; -+ -+ mach = list_entry(this, struct mips_machine, list); -+ if (mach->mach_type == machtype) -+ return mach; -+ } -+ -+ return NULL; -+} -+ -+void __init mips_machine_register(struct mips_machine *mach) -+{ -+ list_add_tail(&mach->list, &mips_machines); -+} -+ -+void __init mips_machine_set_name(char *name) -+{ -+ unsigned int len; -+ char *p; -+ -+ if (name == NULL) -+ return; -+ -+ len = strlen(name); -+ p = kmalloc(len + 1, GFP_KERNEL); -+ if (p) { -+ strncpy(p, name, len); -+ p[len] = '\0'; -+ mips_machine_name = p; -+ } else { -+ printk(KERN_WARNING "MIPS: no memory for machine_name\n"); -+ } -+} -+ -+void __init mips_machine_setup(void) -+{ -+ struct mips_machine *mach; -+ -+ mach = mips_machine_find(mips_machtype); -+ if (!mach) { -+ printk(KERN_WARNING "MIPS: no machine registered for " -+ "machtype %lu\n", mips_machtype); -+ return; -+ } -+ -+ mips_machine_set_name(mach->mach_name); -+ printk(KERN_NOTICE "MIPS: machine is %s\n", mips_machine_name); -+ -+ if (mach->mach_setup) -+ mach->mach_setup(); -+} -+ -+int __init mips_machtype_setup(char *id) -+{ -+ if (mips_machid == NULL) -+ mips_machid = id; -+ -+ return 1; -+} -+ -+__setup("machtype=", mips_machtype_setup); -+ -+static int __init mips_machtype_init(void) -+{ -+ struct list_head *this; -+ struct mips_machine *mach; -+ -+ if (mips_machid == NULL) -+ return 0; -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ if (mach->mach_id == NULL) -+ continue; -+ -+ if (strcmp(mach->mach_id, mips_machid) == 0) { -+ mips_machtype = mach->mach_type; -+ return 0; -+ } -+ } -+ -+ printk(KERN_WARNING -+ "MIPS: no machine found for id: '%s', registered machines:\n", -+ mips_machid); -+ printk(KERN_WARNING "%32s %s\n", "id", "name"); -+ -+ list_for_each(this, &mips_machines) { -+ mach = list_entry(this, struct mips_machine, list); -+ printk(KERN_WARNING "%32s %s\n", -+ mach->mach_id ? mach->mach_id : "", mach->mach_name); -+ } -+ -+ return 0; -+} -+ -+core_initcall(mips_machtype_init); -diff -Nur linux-2.6.35.7.orig/arch/mips/kernel/proc.c linux-2.6.35.7/arch/mips/kernel/proc.c ---- linux-2.6.35.7.orig/arch/mips/kernel/proc.c 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/arch/mips/kernel/proc.c 2010-10-14 20:27:59.578101125 +0200 -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - - unsigned int vced_count, vcei_count; - -@@ -31,8 +32,12 @@ - /* - * For the first processor also print the system type - */ -- if (n == 0) -+ if (n == 0) { - seq_printf(m, "system type\t\t: %s\n", get_system_type()); -+#ifdef CONFIG_MIPS_MACHINE -+ seq_printf(m, "machine\t\t\t: %s\n", mips_machine_name); -+#endif -+ } - - seq_printf(m, "processor\t\t: %ld\n", n); - sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", -diff -Nur linux-2.6.35.7.orig/arch/mips/kernel/traps.c linux-2.6.35.7/arch/mips/kernel/traps.c ---- linux-2.6.35.7.orig/arch/mips/kernel/traps.c 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/arch/mips/kernel/traps.c 2010-10-14 20:27:59.634370215 +0200 -@@ -51,6 +51,7 @@ - #include - #include - #include -+#include - #include - - extern void check_wait(void); -@@ -1519,6 +1520,8 @@ - if (cpu_has_mips_r2) { - cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; - cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; -+ if (get_c0_compare_irq) -+ cp0_compare_irq = get_c0_compare_irq(); - cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; - if (cp0_perfcount_irq == cp0_compare_irq) - cp0_perfcount_irq = -1; -diff -Nur linux-2.6.35.7.orig/arch/mips/kernel/traps.c.orig linux-2.6.35.7/arch/mips/kernel/traps.c.orig ---- linux-2.6.35.7.orig/arch/mips/kernel/traps.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/kernel/traps.c.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,1738 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle -+ * Copyright (C) 1995, 1996 Paul M. Antoine -+ * Copyright (C) 1998 Ulf Carlsson -+ * Copyright (C) 1999 Silicon Graphics, Inc. -+ * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com -+ * Copyright (C) 2000, 01 MIPS Technologies, Inc. -+ * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+extern void check_wait(void); -+extern asmlinkage void r4k_wait(void); -+extern asmlinkage void rollback_handle_int(void); -+extern asmlinkage void handle_int(void); -+extern asmlinkage void handle_tlbm(void); -+extern asmlinkage void handle_tlbl(void); -+extern asmlinkage void handle_tlbs(void); -+extern asmlinkage void handle_adel(void); -+extern asmlinkage void handle_ades(void); -+extern asmlinkage void handle_ibe(void); -+extern asmlinkage void handle_dbe(void); -+extern asmlinkage void handle_sys(void); -+extern asmlinkage void handle_bp(void); -+extern asmlinkage void handle_ri(void); -+extern asmlinkage void handle_ri_rdhwr_vivt(void); -+extern asmlinkage void handle_ri_rdhwr(void); -+extern asmlinkage void handle_cpu(void); -+extern asmlinkage void handle_ov(void); -+extern asmlinkage void handle_tr(void); -+extern asmlinkage void handle_fpe(void); -+extern asmlinkage void handle_mdmx(void); -+extern asmlinkage void handle_watch(void); -+extern asmlinkage void handle_mt(void); -+extern asmlinkage void handle_dsp(void); -+extern asmlinkage void handle_mcheck(void); -+extern asmlinkage void handle_reserved(void); -+ -+extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, -+ struct mips_fpu_struct *ctx, int has_fpu); -+ -+void (*board_be_init)(void); -+int (*board_be_handler)(struct pt_regs *regs, int is_fixup); -+void (*board_nmi_handler_setup)(void); -+void (*board_ejtag_handler_setup)(void); -+void (*board_bind_eic_interrupt)(int irq, int regset); -+ -+ -+static void show_raw_backtrace(unsigned long reg29) -+{ -+ unsigned long *sp = (unsigned long *)(reg29 & ~3); -+ unsigned long addr; -+ -+ printk("Call Trace:"); -+#ifdef CONFIG_KALLSYMS -+ printk("\n"); -+#endif -+ while (!kstack_end(sp)) { -+ unsigned long __user *p = -+ (unsigned long __user *)(unsigned long)sp++; -+ if (__get_user(addr, p)) { -+ printk(" (Bad stack address)"); -+ break; -+ } -+ if (__kernel_text_address(addr)) -+ print_ip_sym(addr); -+ } -+ printk("\n"); -+} -+ -+#ifdef CONFIG_KALLSYMS -+int raw_show_trace; -+static int __init set_raw_show_trace(char *str) -+{ -+ raw_show_trace = 1; -+ return 1; -+} -+__setup("raw_show_trace", set_raw_show_trace); -+#endif -+ -+static void show_backtrace(struct task_struct *task, const struct pt_regs *regs) -+{ -+ unsigned long sp = regs->regs[29]; -+ unsigned long ra = regs->regs[31]; -+ unsigned long pc = regs->cp0_epc; -+ -+ if (raw_show_trace || !__kernel_text_address(pc)) { -+ show_raw_backtrace(sp); -+ return; -+ } -+ printk("Call Trace:\n"); -+ do { -+ print_ip_sym(pc); -+ pc = unwind_stack(task, &sp, pc, &ra); -+ } while (pc); -+ printk("\n"); -+} -+ -+/* -+ * This routine abuses get_user()/put_user() to reference pointers -+ * with at least a bit of error checking ... -+ */ -+static void show_stacktrace(struct task_struct *task, -+ const struct pt_regs *regs) -+{ -+ const int field = 2 * sizeof(unsigned long); -+ long stackdata; -+ int i; -+ unsigned long __user *sp = (unsigned long __user *)regs->regs[29]; -+ -+ printk("Stack :"); -+ i = 0; -+ while ((unsigned long) sp & (PAGE_SIZE - 1)) { -+ if (i && ((i % (64 / field)) == 0)) -+ printk("\n "); -+ if (i > 39) { -+ printk(" ..."); -+ break; -+ } -+ -+ if (__get_user(stackdata, sp++)) { -+ printk(" (Bad stack address)"); -+ break; -+ } -+ -+ printk(" %0*lx", field, stackdata); -+ i++; -+ } -+ printk("\n"); -+ show_backtrace(task, regs); -+} -+ -+void show_stack(struct task_struct *task, unsigned long *sp) -+{ -+ struct pt_regs regs; -+ if (sp) { -+ regs.regs[29] = (unsigned long)sp; -+ regs.regs[31] = 0; -+ regs.cp0_epc = 0; -+ } else { -+ if (task && task != current) { -+ regs.regs[29] = task->thread.reg29; -+ regs.regs[31] = 0; -+ regs.cp0_epc = task->thread.reg31; -+#ifdef CONFIG_KGDB_KDB -+ } else if (atomic_read(&kgdb_active) != -1 && -+ kdb_current_regs) { -+ memcpy(®s, kdb_current_regs, sizeof(regs)); -+#endif /* CONFIG_KGDB_KDB */ -+ } else { -+ prepare_frametrace(®s); -+ } -+ } -+ show_stacktrace(task, ®s); -+} -+ -+/* -+ * The architecture-independent dump_stack generator -+ */ -+void dump_stack(void) -+{ -+ struct pt_regs regs; -+ -+ prepare_frametrace(®s); -+ show_backtrace(current, ®s); -+} -+ -+EXPORT_SYMBOL(dump_stack); -+ -+static void show_code(unsigned int __user *pc) -+{ -+ long i; -+ unsigned short __user *pc16 = NULL; -+ -+ printk("\nCode:"); -+ -+ if ((unsigned long)pc & 1) -+ pc16 = (unsigned short __user *)((unsigned long)pc & ~1); -+ for(i = -3 ; i < 6 ; i++) { -+ unsigned int insn; -+ if (pc16 ? __get_user(insn, pc16 + i) : __get_user(insn, pc + i)) { -+ printk(" (Bad address in epc)\n"); -+ break; -+ } -+ printk("%c%0*x%c", (i?' ':'<'), pc16 ? 4 : 8, insn, (i?' ':'>')); -+ } -+} -+ -+static void __show_regs(const struct pt_regs *regs) -+{ -+ const int field = 2 * sizeof(unsigned long); -+ unsigned int cause = regs->cp0_cause; -+ int i; -+ -+ printk("Cpu %d\n", smp_processor_id()); -+ -+ /* -+ * Saved main processor registers -+ */ -+ for (i = 0; i < 32; ) { -+ if ((i % 4) == 0) -+ printk("$%2d :", i); -+ if (i == 0) -+ printk(" %0*lx", field, 0UL); -+ else if (i == 26 || i == 27) -+ printk(" %*s", field, ""); -+ else -+ printk(" %0*lx", field, regs->regs[i]); -+ -+ i++; -+ if ((i % 4) == 0) -+ printk("\n"); -+ } -+ -+#ifdef CONFIG_CPU_HAS_SMARTMIPS -+ printk("Acx : %0*lx\n", field, regs->acx); -+#endif -+ printk("Hi : %0*lx\n", field, regs->hi); -+ printk("Lo : %0*lx\n", field, regs->lo); -+ -+ /* -+ * Saved cp0 registers -+ */ -+ printk("epc : %0*lx %pS\n", field, regs->cp0_epc, -+ (void *) regs->cp0_epc); -+ printk(" %s\n", print_tainted()); -+ printk("ra : %0*lx %pS\n", field, regs->regs[31], -+ (void *) regs->regs[31]); -+ -+ printk("Status: %08x ", (uint32_t) regs->cp0_status); -+ -+ if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) { -+ if (regs->cp0_status & ST0_KUO) -+ printk("KUo "); -+ if (regs->cp0_status & ST0_IEO) -+ printk("IEo "); -+ if (regs->cp0_status & ST0_KUP) -+ printk("KUp "); -+ if (regs->cp0_status & ST0_IEP) -+ printk("IEp "); -+ if (regs->cp0_status & ST0_KUC) -+ printk("KUc "); -+ if (regs->cp0_status & ST0_IEC) -+ printk("IEc "); -+ } else { -+ if (regs->cp0_status & ST0_KX) -+ printk("KX "); -+ if (regs->cp0_status & ST0_SX) -+ printk("SX "); -+ if (regs->cp0_status & ST0_UX) -+ printk("UX "); -+ switch (regs->cp0_status & ST0_KSU) { -+ case KSU_USER: -+ printk("USER "); -+ break; -+ case KSU_SUPERVISOR: -+ printk("SUPERVISOR "); -+ break; -+ case KSU_KERNEL: -+ printk("KERNEL "); -+ break; -+ default: -+ printk("BAD_MODE "); -+ break; -+ } -+ if (regs->cp0_status & ST0_ERL) -+ printk("ERL "); -+ if (regs->cp0_status & ST0_EXL) -+ printk("EXL "); -+ if (regs->cp0_status & ST0_IE) -+ printk("IE "); -+ } -+ printk("\n"); -+ -+ printk("Cause : %08x\n", cause); -+ -+ cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; -+ if (1 <= cause && cause <= 5) -+ printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr); -+ -+ printk("PrId : %08x (%s)\n", read_c0_prid(), -+ cpu_name_string()); -+} -+ -+/* -+ * FIXME: really the generic show_regs should take a const pointer argument. -+ */ -+void show_regs(struct pt_regs *regs) -+{ -+ __show_regs((struct pt_regs *)regs); -+} -+ -+void show_registers(const struct pt_regs *regs) -+{ -+ const int field = 2 * sizeof(unsigned long); -+ -+ __show_regs(regs); -+ print_modules(); -+ printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n", -+ current->comm, current->pid, current_thread_info(), current, -+ field, current_thread_info()->tp_value); -+ if (cpu_has_userlocal) { -+ unsigned long tls; -+ -+ tls = read_c0_userlocal(); -+ if (tls != current_thread_info()->tp_value) -+ printk("*HwTLS: %0*lx\n", field, tls); -+ } -+ -+ show_stacktrace(current, regs); -+ show_code((unsigned int __user *) regs->cp0_epc); -+ printk("\n"); -+} -+ -+static DEFINE_SPINLOCK(die_lock); -+ -+void __noreturn die(const char * str, struct pt_regs * regs) -+{ -+ static int die_counter; -+ int sig = SIGSEGV; -+#ifdef CONFIG_MIPS_MT_SMTC -+ unsigned long dvpret = dvpe(); -+#endif /* CONFIG_MIPS_MT_SMTC */ -+ -+ notify_die(DIE_OOPS, str, (struct pt_regs *)regs, SIGSEGV, 0, 0); -+ -+ console_verbose(); -+ spin_lock_irq(&die_lock); -+ bust_spinlocks(1); -+#ifdef CONFIG_MIPS_MT_SMTC -+ mips_mt_regdump(dvpret); -+#endif /* CONFIG_MIPS_MT_SMTC */ -+ -+ if (notify_die(DIE_OOPS, str, regs, 0, current->thread.trap_no, SIGSEGV) == NOTIFY_STOP) -+ sig = 0; -+ -+ printk("%s[#%d]:\n", str, ++die_counter); -+ show_registers(regs); -+ add_taint(TAINT_DIE); -+ spin_unlock_irq(&die_lock); -+ -+ if (in_interrupt()) -+ panic("Fatal exception in interrupt"); -+ -+ if (panic_on_oops) { -+ printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n"); -+ ssleep(5); -+ panic("Fatal exception"); -+ } -+ -+ do_exit(sig); -+} -+ -+extern struct exception_table_entry __start___dbe_table[]; -+extern struct exception_table_entry __stop___dbe_table[]; -+ -+__asm__( -+" .section __dbe_table, \"a\"\n" -+" .previous \n"); -+ -+/* Given an address, look for it in the exception tables. */ -+static const struct exception_table_entry *search_dbe_tables(unsigned long addr) -+{ -+ const struct exception_table_entry *e; -+ -+ e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr); -+ if (!e) -+ e = search_module_dbetables(addr); -+ return e; -+} -+ -+asmlinkage void do_be(struct pt_regs *regs) -+{ -+ const int field = 2 * sizeof(unsigned long); -+ const struct exception_table_entry *fixup = NULL; -+ int data = regs->cp0_cause & 4; -+ int action = MIPS_BE_FATAL; -+ -+ /* XXX For now. Fixme, this searches the wrong table ... */ -+ if (data && !user_mode(regs)) -+ fixup = search_dbe_tables(exception_epc(regs)); -+ -+ if (fixup) -+ action = MIPS_BE_FIXUP; -+ -+ if (board_be_handler) -+ action = board_be_handler(regs, fixup != NULL); -+ -+ switch (action) { -+ case MIPS_BE_DISCARD: -+ return; -+ case MIPS_BE_FIXUP: -+ if (fixup) { -+ regs->cp0_epc = fixup->nextinsn; -+ return; -+ } -+ break; -+ default: -+ break; -+ } -+ -+ /* -+ * Assume it would be too dangerous to continue ... -+ */ -+ printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n", -+ data ? "Data" : "Instruction", -+ field, regs->cp0_epc, field, regs->regs[31]); -+ if (notify_die(DIE_OOPS, "bus error", regs, SIGBUS, 0, 0) -+ == NOTIFY_STOP) -+ return; -+ -+ die_if_kernel("Oops", regs); -+ force_sig(SIGBUS, current); -+} -+ -+/* -+ * ll/sc, rdhwr, sync emulation -+ */ -+ -+#define OPCODE 0xfc000000 -+#define BASE 0x03e00000 -+#define RT 0x001f0000 -+#define OFFSET 0x0000ffff -+#define LL 0xc0000000 -+#define SC 0xe0000000 -+#define SPEC0 0x00000000 -+#define SPEC3 0x7c000000 -+#define RD 0x0000f800 -+#define FUNC 0x0000003f -+#define SYNC 0x0000000f -+#define RDHWR 0x0000003b -+ -+/* -+ * The ll_bit is cleared by r*_switch.S -+ */ -+ -+unsigned int ll_bit; -+struct task_struct *ll_task; -+ -+static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode) -+{ -+ unsigned long value, __user *vaddr; -+ long offset; -+ -+ /* -+ * analyse the ll instruction that just caused a ri exception -+ * and put the referenced address to addr. -+ */ -+ -+ /* sign extend offset */ -+ offset = opcode & OFFSET; -+ offset <<= 16; -+ offset >>= 16; -+ -+ vaddr = (unsigned long __user *) -+ ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); -+ -+ if ((unsigned long)vaddr & 3) -+ return SIGBUS; -+ if (get_user(value, vaddr)) -+ return SIGSEGV; -+ -+ preempt_disable(); -+ -+ if (ll_task == NULL || ll_task == current) { -+ ll_bit = 1; -+ } else { -+ ll_bit = 0; -+ } -+ ll_task = current; -+ -+ preempt_enable(); -+ -+ regs->regs[(opcode & RT) >> 16] = value; -+ -+ return 0; -+} -+ -+static inline int simulate_sc(struct pt_regs *regs, unsigned int opcode) -+{ -+ unsigned long __user *vaddr; -+ unsigned long reg; -+ long offset; -+ -+ /* -+ * analyse the sc instruction that just caused a ri exception -+ * and put the referenced address to addr. -+ */ -+ -+ /* sign extend offset */ -+ offset = opcode & OFFSET; -+ offset <<= 16; -+ offset >>= 16; -+ -+ vaddr = (unsigned long __user *) -+ ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); -+ reg = (opcode & RT) >> 16; -+ -+ if ((unsigned long)vaddr & 3) -+ return SIGBUS; -+ -+ preempt_disable(); -+ -+ if (ll_bit == 0 || ll_task != current) { -+ regs->regs[reg] = 0; -+ preempt_enable(); -+ return 0; -+ } -+ -+ preempt_enable(); -+ -+ if (put_user(regs->regs[reg], vaddr)) -+ return SIGSEGV; -+ -+ regs->regs[reg] = 1; -+ -+ return 0; -+} -+ -+/* -+ * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both -+ * opcodes are supposed to result in coprocessor unusable exceptions if -+ * executed on ll/sc-less processors. That's the theory. In practice a -+ * few processors such as NEC's VR4100 throw reserved instruction exceptions -+ * instead, so we're doing the emulation thing in both exception handlers. -+ */ -+static int simulate_llsc(struct pt_regs *regs, unsigned int opcode) -+{ -+ if ((opcode & OPCODE) == LL) -+ return simulate_ll(regs, opcode); -+ if ((opcode & OPCODE) == SC) -+ return simulate_sc(regs, opcode); -+ -+ return -1; /* Must be something else ... */ -+} -+ -+/* -+ * Simulate trapping 'rdhwr' instructions to provide user accessible -+ * registers not implemented in hardware. -+ */ -+static int simulate_rdhwr(struct pt_regs *regs, unsigned int opcode) -+{ -+ struct thread_info *ti = task_thread_info(current); -+ -+ if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) { -+ int rd = (opcode & RD) >> 11; -+ int rt = (opcode & RT) >> 16; -+ switch (rd) { -+ case 0: /* CPU number */ -+ regs->regs[rt] = smp_processor_id(); -+ return 0; -+ case 1: /* SYNCI length */ -+ regs->regs[rt] = min(current_cpu_data.dcache.linesz, -+ current_cpu_data.icache.linesz); -+ return 0; -+ case 2: /* Read count register */ -+ regs->regs[rt] = read_c0_count(); -+ return 0; -+ case 3: /* Count register resolution */ -+ switch (current_cpu_data.cputype) { -+ case CPU_20KC: -+ case CPU_25KF: -+ regs->regs[rt] = 1; -+ break; -+ default: -+ regs->regs[rt] = 2; -+ } -+ return 0; -+ case 29: -+ regs->regs[rt] = ti->tp_value; -+ return 0; -+ default: -+ return -1; -+ } -+ } -+ -+ /* Not ours. */ -+ return -1; -+} -+ -+static int simulate_sync(struct pt_regs *regs, unsigned int opcode) -+{ -+ if ((opcode & OPCODE) == SPEC0 && (opcode & FUNC) == SYNC) -+ return 0; -+ -+ return -1; /* Must be something else ... */ -+} -+ -+asmlinkage void do_ov(struct pt_regs *regs) -+{ -+ siginfo_t info; -+ -+ die_if_kernel("Integer overflow", regs); -+ -+ info.si_code = FPE_INTOVF; -+ info.si_signo = SIGFPE; -+ info.si_errno = 0; -+ info.si_addr = (void __user *) regs->cp0_epc; -+ force_sig_info(SIGFPE, &info, current); -+} -+ -+/* -+ * XXX Delayed fp exceptions when doing a lazy ctx switch XXX -+ */ -+asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31) -+{ -+ siginfo_t info; -+ -+ if (notify_die(DIE_FP, "FP exception", regs, SIGFPE, 0, 0) -+ == NOTIFY_STOP) -+ return; -+ die_if_kernel("FP exception in kernel code", regs); -+ -+ if (fcr31 & FPU_CSR_UNI_X) { -+ int sig; -+ -+ /* -+ * Unimplemented operation exception. If we've got the full -+ * software emulator on-board, let's use it... -+ * -+ * Force FPU to dump state into task/thread context. We're -+ * moving a lot of data here for what is probably a single -+ * instruction, but the alternative is to pre-decode the FP -+ * register operands before invoking the emulator, which seems -+ * a bit extreme for what should be an infrequent event. -+ */ -+ /* Ensure 'resume' not overwrite saved fp context again. */ -+ lose_fpu(1); -+ -+ /* Run the emulator */ -+ sig = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1); -+ -+ /* -+ * We can't allow the emulated instruction to leave any of -+ * the cause bit set in $fcr31. -+ */ -+ current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; -+ -+ /* Restore the hardware register state */ -+ own_fpu(1); /* Using the FPU again. */ -+ -+ /* If something went wrong, signal */ -+ if (sig) -+ force_sig(sig, current); -+ -+ return; -+ } else if (fcr31 & FPU_CSR_INV_X) -+ info.si_code = FPE_FLTINV; -+ else if (fcr31 & FPU_CSR_DIV_X) -+ info.si_code = FPE_FLTDIV; -+ else if (fcr31 & FPU_CSR_OVF_X) -+ info.si_code = FPE_FLTOVF; -+ else if (fcr31 & FPU_CSR_UDF_X) -+ info.si_code = FPE_FLTUND; -+ else if (fcr31 & FPU_CSR_INE_X) -+ info.si_code = FPE_FLTRES; -+ else -+ info.si_code = __SI_FAULT; -+ info.si_signo = SIGFPE; -+ info.si_errno = 0; -+ info.si_addr = (void __user *) regs->cp0_epc; -+ force_sig_info(SIGFPE, &info, current); -+} -+ -+static void do_trap_or_bp(struct pt_regs *regs, unsigned int code, -+ const char *str) -+{ -+ siginfo_t info; -+ char b[40]; -+ -+#ifdef CONFIG_KGDB_LOW_LEVEL_TRAP -+ if (kgdb_ll_trap(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) -+ return; -+#endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ -+ -+ if (notify_die(DIE_TRAP, str, regs, code, 0, 0) == NOTIFY_STOP) -+ return; -+ -+ /* -+ * A short test says that IRIX 5.3 sends SIGTRAP for all trap -+ * insns, even for trap and break codes that indicate arithmetic -+ * failures. Weird ... -+ * But should we continue the brokenness??? --macro -+ */ -+ switch (code) { -+ case BRK_OVERFLOW: -+ case BRK_DIVZERO: -+ scnprintf(b, sizeof(b), "%s instruction in kernel code", str); -+ die_if_kernel(b, regs); -+ if (code == BRK_DIVZERO) -+ info.si_code = FPE_INTDIV; -+ else -+ info.si_code = FPE_INTOVF; -+ info.si_signo = SIGFPE; -+ info.si_errno = 0; -+ info.si_addr = (void __user *) regs->cp0_epc; -+ force_sig_info(SIGFPE, &info, current); -+ break; -+ case BRK_BUG: -+ die_if_kernel("Kernel bug detected", regs); -+ force_sig(SIGTRAP, current); -+ break; -+ case BRK_MEMU: -+ /* -+ * Address errors may be deliberately induced by the FPU -+ * emulator to retake control of the CPU after executing the -+ * instruction in the delay slot of an emulated branch. -+ * -+ * Terminate if exception was recognized as a delay slot return -+ * otherwise handle as normal. -+ */ -+ if (do_dsemulret(regs)) -+ return; -+ -+ die_if_kernel("Math emu break/trap", regs); -+ force_sig(SIGTRAP, current); -+ break; -+ default: -+ scnprintf(b, sizeof(b), "%s instruction in kernel code", str); -+ die_if_kernel(b, regs); -+ force_sig(SIGTRAP, current); -+ } -+} -+ -+asmlinkage void do_bp(struct pt_regs *regs) -+{ -+ unsigned int opcode, bcode; -+ -+ if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) -+ goto out_sigsegv; -+ -+ /* -+ * There is the ancient bug in the MIPS assemblers that the break -+ * code starts left to bit 16 instead to bit 6 in the opcode. -+ * Gas is bug-compatible, but not always, grrr... -+ * We handle both cases with a simple heuristics. --macro -+ */ -+ bcode = ((opcode >> 6) & ((1 << 20) - 1)); -+ if (bcode >= (1 << 10)) -+ bcode >>= 10; -+ -+ do_trap_or_bp(regs, bcode, "Break"); -+ return; -+ -+out_sigsegv: -+ force_sig(SIGSEGV, current); -+} -+ -+asmlinkage void do_tr(struct pt_regs *regs) -+{ -+ unsigned int opcode, tcode = 0; -+ -+ if (__get_user(opcode, (unsigned int __user *) exception_epc(regs))) -+ goto out_sigsegv; -+ -+ /* Immediate versions don't provide a code. */ -+ if (!(opcode & OPCODE)) -+ tcode = ((opcode >> 6) & ((1 << 10) - 1)); -+ -+ do_trap_or_bp(regs, tcode, "Trap"); -+ return; -+ -+out_sigsegv: -+ force_sig(SIGSEGV, current); -+} -+ -+asmlinkage void do_ri(struct pt_regs *regs) -+{ -+ unsigned int __user *epc = (unsigned int __user *)exception_epc(regs); -+ unsigned long old_epc = regs->cp0_epc; -+ unsigned int opcode = 0; -+ int status = -1; -+ -+ if (notify_die(DIE_RI, "RI Fault", regs, SIGSEGV, 0, 0) -+ == NOTIFY_STOP) -+ return; -+ -+ die_if_kernel("Reserved instruction in kernel code", regs); -+ -+ if (unlikely(compute_return_epc(regs) < 0)) -+ return; -+ -+ if (unlikely(get_user(opcode, epc) < 0)) -+ status = SIGSEGV; +diff -Nur linux-2.6.36.orig/arch/mips/Kconfig linux-2.6.36/arch/mips/Kconfig +--- linux-2.6.36.orig/arch/mips/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/Kconfig 2010-11-18 21:16:05.000000000 +0100 +@@ -60,6 +60,23 @@ + Support for the Texas Instruments AR7 System-on-a-Chip + family: TNETD7100, 7200 and 7300. + ++config ATHEROS_AR71XX ++ bool "Atheros AR71xx based boards" ++ select CEVT_R4K ++ select CSRC_R4K ++ select DMA_NONCOHERENT ++ select HW_HAS_PCI ++ select IRQ_CPU ++ select ARCH_REQUIRE_GPIOLIB ++ select SYS_HAS_CPU_MIPS32_R1 ++ select SYS_HAS_CPU_MIPS32_R2 ++ select SYS_SUPPORTS_32BIT_KERNEL ++ select SYS_SUPPORTS_BIG_ENDIAN ++ select SYS_HAS_EARLY_PRINTK ++ select MIPS_MACHINE ++ help ++ Support for Atheros AR71xx based boards. + -+ if (!cpu_has_llsc && status < 0) -+ status = simulate_llsc(regs, opcode); + config BCM47XX + bool "Broadcom BCM47XX based boards" + select CEVT_R4K +@@ -709,6 +726,7 @@ + endchoice + + source "arch/mips/alchemy/Kconfig" ++source "arch/mips/ar71xx/Kconfig" + source "arch/mips/bcm63xx/Kconfig" + source "arch/mips/jazz/Kconfig" + source "arch/mips/jz4740/Kconfig" +@@ -872,9 +890,15 @@ + config MIPS_DISABLE_OBSOLETE_IDE + bool + ++config MYLOADER ++ bool + -+ if (status < 0) -+ status = simulate_rdhwr(regs, opcode); + config SYNC_R4K + bool + ++config MIPS_MACHINE ++ def_bool n + -+ if (status < 0) -+ status = simulate_sync(regs, opcode); + config NO_IOPORT + def_bool n + +diff -Nur linux-2.6.36.orig/arch/mips/Makefile linux-2.6.36/arch/mips/Makefile +--- linux-2.6.36.orig/arch/mips/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/Makefile 2010-11-18 21:16:07.000000000 +0100 +@@ -160,6 +160,13 @@ + cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon + endif + ++# ++# Atheros AR71xx ++# ++core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ ++cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx ++load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 + -+ if (status < 0) -+ status = SIGILL; + cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) + cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) + cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/Kconfig linux-2.6.36/arch/mips/ar71xx/Kconfig +--- linux-2.6.36.orig/arch/mips/ar71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/Kconfig 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,264 @@ ++if ATHEROS_AR71XX + -+ if (unlikely(status > 0)) { -+ regs->cp0_epc = old_epc; /* Undo skip-over. */ -+ force_sig(status, current); -+ } -+} ++menu "Atheros AR71xx machine selection" + -+/* -+ * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've -+ * emulated more than some threshold number of instructions, force migration to -+ * a "CPU" that has FP support. -+ */ -+static void mt_ase_fp_affinity(void) -+{ -+#ifdef CONFIG_MIPS_MT_FPAFF -+ if (mt_fpemul_threshold > 0 && -+ ((current->thread.emulated_fp++ > mt_fpemul_threshold))) { -+ /* -+ * If there's no FPU present, or if the application has already -+ * restricted the allowed set to exclude any CPUs with FPUs, -+ * we'll skip the procedure. -+ */ -+ if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) { -+ cpumask_t tmask; -+ -+ current->thread.user_cpus_allowed -+ = current->cpus_allowed; -+ cpus_and(tmask, current->cpus_allowed, -+ mt_fpu_cpumask); -+ set_cpus_allowed_ptr(current, &tmask); -+ set_thread_flag(TIF_FPUBOUND); -+ } -+ } -+#endif /* CONFIG_MIPS_MT_FPAFF */ -+} ++config AR71XX_MACH_AP81 ++ bool "Atheros AP81 board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+/* -+ * No lock; only written during early bootup by CPU 0. -+ */ -+static RAW_NOTIFIER_HEAD(cu2_chain); ++config AR71XX_MACH_AP83 ++ bool "Atheros AP83 board support" ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+int __ref register_cu2_notifier(struct notifier_block *nb) -+{ -+ return raw_notifier_chain_register(&cu2_chain, nb); -+} ++config AR71XX_MACH_DIR_600_A1 ++ bool "D-Link DIR-600 rev. A1 support" ++ select AR71XX_DEV_AP91_ETH ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_NVRAM ++ default n + -+int cu2_notifier_call_chain(unsigned long val, void *v) -+{ -+ return raw_notifier_call_chain(&cu2_chain, val, v); -+} ++config AR71XX_MACH_DIR_615_C1 ++ bool "D-Link DIR-615 rev. C1 support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_NVRAM ++ default n + -+static int default_cu2_call(struct notifier_block *nfb, unsigned long action, -+ void *data) -+{ -+ struct pt_regs *regs = data; ++config AR71XX_MACH_DIR_825_B1 ++ bool "D-Link DIR-825 rev. B1 board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP94_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+ switch (action) { -+ default: -+ die_if_kernel("Unhandled kernel unaligned access or invalid " -+ "instruction", regs); -+ /* Fall through */ ++config AR71XX_MACH_PB42 ++ bool "Atheros PB42 board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ default n + -+ case CU2_EXCEPTION: -+ force_sig(SIGILL, current); -+ } ++config AR71XX_MACH_PB44 ++ bool "Atheros PB44 board support" ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+ return NOTIFY_OK; -+} ++config AR71XX_MACH_PB92 ++ bool "Atheros PB92 board support" ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB9X_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+static struct notifier_block default_cu2_notifier = { -+ .notifier_call = default_cu2_call, -+ .priority = 0x80000000, /* Run last */ -+}; ++config AR71XX_MACH_AW_NR580 ++ bool "AzureWave AW-NR580 board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ default n + -+asmlinkage void do_cpu(struct pt_regs *regs) -+{ -+ unsigned int __user *epc; -+ unsigned long old_epc; -+ unsigned int opcode; -+ unsigned int cpid; -+ int status; -+ unsigned long __maybe_unused flags; ++config AR71XX_MACH_WZR_HP_G300NH ++ bool "Buffalo WZR-HP-G300NH board support" ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default y + -+ die_if_kernel("do_cpu invoked from kernel context!", regs); ++config AR71XX_MACH_WP543 ++ bool "Compex WP543/WPJ543 board support" ++ select MYLOADER ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+ cpid = (regs->cp0_cause >> CAUSEB_CE) & 3; ++config AR71XX_MACH_WRT160NL ++ bool "Linksys WRT160NL board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ select AR71XX_NVRAM ++ default n + -+ switch (cpid) { -+ case 0: -+ epc = (unsigned int __user *)exception_epc(regs); -+ old_epc = regs->cp0_epc; -+ opcode = 0; -+ status = -1; ++config AR71XX_MACH_WRT400N ++ bool "Linksys WRT400N board support" ++ select AR71XX_DEV_AP94_PCI if PCI ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n + -+ if (unlikely(compute_return_epc(regs) < 0)) -+ return; ++config AR71XX_MACH_RB4XX ++ bool "MikroTik RouterBOARD 4xx series support" ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+ if (unlikely(get_user(opcode, epc) < 0)) -+ status = SIGSEGV; ++config AR71XX_MACH_RB750 ++ bool "MikroTik RouterBOARD 750 support" ++ select AR71XX_DEV_AP91_ETH ++ default n + -+ if (!cpu_has_llsc && status < 0) -+ status = simulate_llsc(regs, opcode); ++config AR71XX_MACH_WNDR3700 ++ bool "NETGEAR WNDR3700 board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP94_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+ if (status < 0) -+ status = simulate_rdhwr(regs, opcode); ++config AR71XX_MACH_WNR2000 ++ bool "NETGEAR WNR2000 board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n + -+ if (status < 0) -+ status = SIGILL; ++config AR71XX_MACH_MZK_W04NU ++ bool "Planex MZK-W04NU board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+ if (unlikely(status > 0)) { -+ regs->cp0_epc = old_epc; /* Undo skip-over. */ -+ force_sig(status, current); -+ } ++config AR71XX_MACH_MZK_W300NH ++ bool "Planex MZK-W300NH board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n + -+ return; ++config AR71XX_MACH_NBG460N ++ bool "Zyxel NBG460N/550N/550NH board support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n ++ ++config AR71XX_MACH_TL_WR741ND ++ bool "TP-LINK TL-WR741ND support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP91_ETH ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n + -+ case 1: -+ if (used_math()) /* Using the FPU again. */ -+ own_fpu(1); -+ else { /* First time FPU user. */ -+ init_fpu(); -+ set_used_math(); -+ } ++config AR71XX_MACH_TL_WR841N_V1 ++ bool "TP-LINK TL-WR841N v1 support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_DSA ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n + -+ if (!raw_cpu_has_fpu) { -+ int sig; -+ sig = fpu_emulator_cop1Handler(regs, -+ ¤t->thread.fpu, 0); -+ if (sig) -+ force_sig(sig, current); -+ else -+ mt_ase_fp_affinity(); -+ } ++config AR71XX_MACH_TL_WR941ND ++ bool "TP-LINK TL-WR941ND support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_DSA ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ default n + -+ return; ++config AR71XX_MACH_TL_WR1043ND ++ bool "TP-LINK TL-WR1043ND support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_USB ++ default n + -+ case 2: -+ raw_notifier_call_chain(&cu2_chain, CU2_EXCEPTION, regs); -+ return; ++config AR71XX_MACH_TEW_632BRP ++ bool "TRENDnet TEW-632BRP support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AR913X_WMAC ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_NVRAM ++ default n + -+ case 3: -+ break; -+ } ++config AR71XX_MACH_UBNT ++ bool "Ubiquiti AR71xx based boards support" ++ select AR71XX_DEV_M25P80 ++ select AR71XX_DEV_AP91_PCI if PCI ++ select AR71XX_DEV_GPIO_BUTTONS ++ select AR71XX_DEV_LEDS_GPIO ++ select AR71XX_DEV_PB42_PCI if PCI ++ select AR71XX_DEV_USB ++ default n + -+ force_sig(SIGILL, current); -+} ++endmenu + -+asmlinkage void do_mdmx(struct pt_regs *regs) -+{ -+ force_sig(SIGILL, current); -+} ++config AR71XX_DEV_M25P80 ++ def_bool n + -+/* -+ * Called with interrupts disabled. -+ */ -+asmlinkage void do_watch(struct pt_regs *regs) -+{ -+ u32 cause; ++config AR71XX_DEV_AP91_PCI ++ def_bool n + -+ /* -+ * Clear WP (bit 22) bit of cause register so we don't loop -+ * forever. -+ */ -+ cause = read_c0_cause(); -+ cause &= ~(1 << 22); -+ write_c0_cause(cause); ++config AR71XX_DEV_AP91_ETH ++ def_bool n + -+ /* -+ * If the current thread has the watch registers loaded, save -+ * their values and send SIGTRAP. Otherwise another thread -+ * left the registers set, clear them and continue. -+ */ -+ if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { -+ mips_read_watch_registers(); -+ local_irq_enable(); -+ force_sig(SIGTRAP, current); -+ } else { -+ mips_clear_watch_registers(); -+ local_irq_enable(); -+ } -+} ++config AR71XX_DEV_AP94_PCI ++ def_bool n + -+asmlinkage void do_mcheck(struct pt_regs *regs) -+{ -+ const int field = 2 * sizeof(unsigned long); -+ int multi_match = regs->cp0_status & ST0_TS; ++config AR71XX_DEV_AR913X_WMAC ++ def_bool n + -+ show_regs(regs); ++config AR71XX_DEV_DSA ++ def_bool n + -+ if (multi_match) { -+ printk("Index : %0x\n", read_c0_index()); -+ printk("Pagemask: %0x\n", read_c0_pagemask()); -+ printk("EntryHi : %0*lx\n", field, read_c0_entryhi()); -+ printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0()); -+ printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1()); -+ printk("\n"); -+ dump_tlb_all(); -+ } ++config AR71XX_DEV_GPIO_BUTTONS ++ def_bool n + -+ show_code((unsigned int __user *) regs->cp0_epc); ++config AR71XX_DEV_LEDS_GPIO ++ def_bool n + -+ /* -+ * Some chips may have other causes of machine check (e.g. SB1 -+ * graduation timer) -+ */ -+ panic("Caught Machine Check exception - %scaused by multiple " -+ "matching entries in the TLB.", -+ (multi_match) ? "" : "not "); -+} ++config AR71XX_DEV_PB42_PCI ++ def_bool n + -+asmlinkage void do_mt(struct pt_regs *regs) -+{ -+ int subcode; ++config AR71XX_DEV_PB9X_PCI ++ def_bool n + -+ subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT) -+ >> VPECONTROL_EXCPT_SHIFT; -+ switch (subcode) { -+ case 0: -+ printk(KERN_DEBUG "Thread Underflow\n"); -+ break; -+ case 1: -+ printk(KERN_DEBUG "Thread Overflow\n"); -+ break; -+ case 2: -+ printk(KERN_DEBUG "Invalid YIELD Qualifier\n"); -+ break; -+ case 3: -+ printk(KERN_DEBUG "Gating Storage Exception\n"); -+ break; -+ case 4: -+ printk(KERN_DEBUG "YIELD Scheduler Exception\n"); -+ break; -+ case 5: -+ printk(KERN_DEBUG "Gating Storage Schedulier Exception\n"); -+ break; -+ default: -+ printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n", -+ subcode); -+ break; -+ } -+ die_if_kernel("MIPS MT Thread exception in kernel", regs); ++config AR71XX_DEV_USB ++ def_bool n + -+ force_sig(SIGILL, current); -+} ++config AR71XX_NVRAM ++ def_bool n + ++endif +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/Makefile linux-2.6.36/arch/mips/ar71xx/Makefile +--- linux-2.6.36.orig/arch/mips/ar71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/Makefile 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,54 @@ ++# ++# Makefile for the Atheros AR71xx SoC specific parts of the kernel ++# ++# Copyright (C) 2008-2009 Gabor Juhos ++# Copyright (C) 2008 Imre Kaloz ++# ++# This program is free software; you can redistribute it and/or modify it ++# under the terms of the GNU General Public License version 2 as published ++# by the Free Software Foundation. + -+asmlinkage void do_dsp(struct pt_regs *regs) -+{ -+ if (cpu_has_dsp) -+ panic("Unexpected DSP exception\n"); ++obj-y := prom.o irq.o setup.o devices.o gpio.o ar71xx.o + -+ force_sig(SIGILL, current); -+} ++obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++obj-$(CONFIG_PCI) += pci.o + -+asmlinkage void do_reserved(struct pt_regs *regs) -+{ -+ /* -+ * Game over - no way to handle this if it ever occurs. Most probably -+ * caused by a new unknown cpu type or after another deadly -+ * hard/software error. -+ */ -+ show_regs(regs); -+ panic("Caught reserved exception %ld - should not happen.", -+ (regs->cp0_cause & 0x7f) >> 2); -+} ++obj-$(CONFIG_AR71XX_DEV_AP91_ETH) += dev-ap91-eth.o ++obj-$(CONFIG_AR71XX_DEV_AP91_PCI) += dev-ap91-pci.o ++obj-$(CONFIG_AR71XX_DEV_AP94_PCI) += dev-ap94-pci.o ++obj-$(CONFIG_AR71XX_DEV_AR913X_WMAC) += dev-ar913x-wmac.o ++obj-$(CONFIG_AR71XX_DEV_DSA) += dev-dsa.o ++obj-$(CONFIG_AR71XX_DEV_GPIO_BUTTONS) += dev-gpio-buttons.o ++obj-$(CONFIG_AR71XX_DEV_LEDS_GPIO) += dev-leds-gpio.o ++obj-$(CONFIG_AR71XX_DEV_M25P80) += dev-m25p80.o ++obj-$(CONFIG_AR71XX_DEV_PB42_PCI) += dev-pb42-pci.o ++obj-$(CONFIG_AR71XX_DEV_PB9X_PCI) += dev-pb9x-pci.o ++obj-$(CONFIG_AR71XX_DEV_USB) += dev-usb.o + -+static int __initdata l1parity = 1; -+static int __init nol1parity(char *s) -+{ -+ l1parity = 0; -+ return 1; -+} -+__setup("nol1par", nol1parity); -+static int __initdata l2parity = 1; -+static int __init nol2parity(char *s) -+{ -+ l2parity = 0; -+ return 1; -+} -+__setup("nol2par", nol2parity); ++obj-$(CONFIG_AR71XX_NVRAM) += nvram.o + ++obj-$(CONFIG_AR71XX_MACH_AP81) += mach-ap81.o ++obj-$(CONFIG_AR71XX_MACH_AP83) += mach-ap83.o ++obj-$(CONFIG_AR71XX_MACH_AW_NR580) += mach-aw-nr580.o ++obj-$(CONFIG_AR71XX_MACH_DIR_600_A1) += mach-dir-600-a1.o ++obj-$(CONFIG_AR71XX_MACH_DIR_615_C1) += mach-dir-615-c1.o ++obj-$(CONFIG_AR71XX_MACH_DIR_825_B1) += mach-dir-825-b1.o ++obj-$(CONFIG_AR71XX_MACH_MZK_W04NU) += mach-mzk-w04nu.o ++obj-$(CONFIG_AR71XX_MACH_MZK_W300NH) += mach-mzk-w300nh.o ++obj-$(CONFIG_AR71XX_MACH_NBG460N) += mach-nbg460n.o ++obj-$(CONFIG_AR71XX_MACH_PB42) += mach-pb42.o ++obj-$(CONFIG_AR71XX_MACH_PB44) += mach-pb44.o ++obj-$(CONFIG_AR71XX_MACH_PB92) += mach-pb92.o ++obj-$(CONFIG_AR71XX_MACH_RB4XX) += mach-rb4xx.o ++obj-$(CONFIG_AR71XX_MACH_RB750) += mach-rb750.o ++obj-$(CONFIG_AR71XX_MACH_TEW_632BRP) += mach-tew-632brp.o ++obj-$(CONFIG_AR71XX_MACH_TL_WR741ND) += mach-tl-wr741nd.o ++obj-$(CONFIG_AR71XX_MACH_TL_WR841N_V1) += mach-tl-wr841n.o ++obj-$(CONFIG_AR71XX_MACH_TL_WR941ND) += mach-tl-wr941nd.o ++obj-$(CONFIG_AR71XX_MACH_TL_WR1043ND) += mach-tl-wr1043nd.o ++obj-$(CONFIG_AR71XX_MACH_UBNT) += mach-ubnt.o ++obj-$(CONFIG_AR71XX_MACH_WNDR3700) += mach-wndr3700.o ++obj-$(CONFIG_AR71XX_MACH_WNR2000) += mach-wnr2000.o ++obj-$(CONFIG_AR71XX_MACH_WP543) += mach-wp543.o ++obj-$(CONFIG_AR71XX_MACH_WRT160NL) += mach-wrt160nl.o ++obj-$(CONFIG_AR71XX_MACH_WRT400N) += mach-wrt400n.o +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/ar71xx.c linux-2.6.36/arch/mips/ar71xx/ar71xx.c +--- linux-2.6.36.orig/arch/mips/ar71xx/ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/ar71xx.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,177 @@ +/* -+ * Some MIPS CPUs can enable/disable for cache parity detection, but do -+ * it different ways. ++ * AR71xx SoC routines ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ -+static inline void parity_protection_init(void) -+{ -+ switch (current_cpu_type()) { -+ case CPU_24K: -+ case CPU_34K: -+ case CPU_74K: -+ case CPU_1004K: -+ { -+#define ERRCTL_PE 0x80000000 -+#define ERRCTL_L2P 0x00800000 -+ unsigned long errctl; -+ unsigned int l1parity_present, l2parity_present; -+ -+ errctl = read_c0_ecc(); -+ errctl &= ~(ERRCTL_PE|ERRCTL_L2P); -+ -+ /* probe L1 parity support */ -+ write_c0_ecc(errctl | ERRCTL_PE); -+ back_to_back_c0_hazard(); -+ l1parity_present = (read_c0_ecc() & ERRCTL_PE); -+ -+ /* probe L2 parity support */ -+ write_c0_ecc(errctl|ERRCTL_L2P); -+ back_to_back_c0_hazard(); -+ l2parity_present = (read_c0_ecc() & ERRCTL_L2P); -+ -+ if (l1parity_present && l2parity_present) { -+ if (l1parity) -+ errctl |= ERRCTL_PE; -+ if (l1parity ^ l2parity) -+ errctl |= ERRCTL_L2P; -+ } else if (l1parity_present) { -+ if (l1parity) -+ errctl |= ERRCTL_PE; -+ } else if (l2parity_present) { -+ if (l2parity) -+ errctl |= ERRCTL_L2P; -+ } else { -+ /* No parity available */ -+ } + -+ printk(KERN_INFO "Writing ErrCtl register=%08lx\n", errctl); -+ -+ write_c0_ecc(errctl); -+ back_to_back_c0_hazard(); -+ errctl = read_c0_ecc(); -+ printk(KERN_INFO "Readback ErrCtl register=%08lx\n", errctl); ++#include ++#include ++#include ++#include + -+ if (l1parity_present) -+ printk(KERN_INFO "Cache parity protection %sabled\n", -+ (errctl & ERRCTL_PE) ? "en" : "dis"); ++#include + -+ if (l2parity_present) { -+ if (l1parity_present && l1parity) -+ errctl ^= ERRCTL_L2P; -+ printk(KERN_INFO "L2 cache parity protection %sabled\n", -+ (errctl & ERRCTL_L2P) ? "en" : "dis"); -+ } -+ } -+ break; ++static DEFINE_MUTEX(ar71xx_flash_mutex); + -+ case CPU_5KC: -+ write_c0_ecc(0x80000000); -+ back_to_back_c0_hazard(); -+ /* Set the PE bit (bit 31) in the c0_errctl register. */ -+ printk(KERN_INFO "Cache parity protection %sabled\n", -+ (read_c0_ecc() & 0x80000000) ? "en" : "dis"); -+ break; -+ case CPU_20KC: -+ case CPU_25KF: -+ /* Clear the DE bit (bit 16) in the c0_status register. */ -+ printk(KERN_INFO "Enable cache parity protection for " -+ "MIPS 20KC/25KF CPUs.\n"); -+ clear_c0_status(ST0_DE); -+ break; -+ default: -+ break; -+ } -+} ++void __iomem *ar71xx_ddr_base; ++EXPORT_SYMBOL_GPL(ar71xx_ddr_base); + -+asmlinkage void cache_parity_error(void) -+{ -+ const int field = 2 * sizeof(unsigned long); -+ unsigned int reg_val; ++void __iomem *ar71xx_pll_base; ++EXPORT_SYMBOL_GPL(ar71xx_pll_base); + -+ /* For the moment, report the problem and hang. */ -+ printk("Cache error exception:\n"); -+ printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc()); -+ reg_val = read_c0_cacheerr(); -+ printk("c0_cacheerr == %08x\n", reg_val); ++void __iomem *ar71xx_reset_base; ++EXPORT_SYMBOL_GPL(ar71xx_reset_base); + -+ printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n", -+ reg_val & (1<<30) ? "secondary" : "primary", -+ reg_val & (1<<31) ? "data" : "insn"); -+ printk("Error bits: %s%s%s%s%s%s%s\n", -+ reg_val & (1<<29) ? "ED " : "", -+ reg_val & (1<<28) ? "ET " : "", -+ reg_val & (1<<26) ? "EE " : "", -+ reg_val & (1<<25) ? "EB " : "", -+ reg_val & (1<<24) ? "EI " : "", -+ reg_val & (1<<23) ? "E1 " : "", -+ reg_val & (1<<22) ? "E0 " : ""); -+ printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1)); ++void __iomem *ar71xx_gpio_base; ++EXPORT_SYMBOL_GPL(ar71xx_gpio_base); + -+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) -+ if (reg_val & (1<<22)) -+ printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0()); ++void __iomem *ar71xx_usb_ctrl_base; ++EXPORT_SYMBOL_GPL(ar71xx_usb_ctrl_base); + -+ if (reg_val & (1<<23)) -+ printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1()); -+#endif ++void ar71xx_device_stop(u32 mask) ++{ ++ unsigned long flags; ++ u32 mask_inv; ++ u32 t; + -+ panic("Can't handle the cache error!"); -+} ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t | mask); ++ local_irq_restore(flags); ++ break; + -+/* -+ * SDBBP EJTAG debug exception handler. -+ * We skip the instruction and return to the next instruction. -+ */ -+void ejtag_exception_handler(struct pt_regs *regs) -+{ -+ const int field = 2 * sizeof(unsigned long); -+ unsigned long depc, old_epc; -+ unsigned int debug; ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ t |= mask; ++ t &= ~mask_inv; ++ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); ++ local_irq_restore(flags); ++ break; + -+ printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n"); -+ depc = read_c0_depc(); -+ debug = read_c0_debug(); -+ printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug); -+ if (debug & 0x80000000) { -+ /* -+ * In branch delay slot. -+ * We cheat a little bit here and use EPC to calculate the -+ * debug return address (DEPC). EPC is restored after the -+ * calculation. -+ */ -+ old_epc = regs->cp0_epc; -+ regs->cp0_epc = depc; -+ __compute_return_epc(regs); -+ depc = regs->cp0_epc; -+ regs->cp0_epc = old_epc; -+ } else -+ depc += 4; -+ write_c0_depc(depc); ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t | mask); ++ local_irq_restore(flags); ++ break; + -+#if 0 -+ printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n"); -+ write_c0_debug(debug | 0x100); -+#endif ++ default: ++ BUG(); ++ } +} ++EXPORT_SYMBOL_GPL(ar71xx_device_stop); + -+/* -+ * NMI exception handler. -+ */ -+NORET_TYPE void ATTRIB_NORET nmi_exception_handler(struct pt_regs *regs) ++void ar71xx_device_start(u32 mask) +{ -+ bust_spinlocks(1); -+ printk("NMI taken!!!!\n"); -+ die("NMI", regs); -+} ++ unsigned long flags; ++ u32 mask_inv; ++ u32 t; + -+#define VECTORSPACING 0x100 /* for EI/VI mode */ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR71XX_RESET_REG_RESET_MODULE, t & ~mask); ++ local_irq_restore(flags); ++ break; + -+unsigned long ebase; -+unsigned long exception_handlers[32]; -+unsigned long vi_handlers[64]; ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ mask_inv = mask & RESET_MODULE_USB_OHCI_DLL_7240; ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ t &= ~mask; ++ t |= mask_inv; ++ ar71xx_reset_wr(AR724X_RESET_REG_RESET_MODULE, t); ++ local_irq_restore(flags); ++ break; + -+void __init *set_except_vector(int n, void *addr) -+{ -+ unsigned long handler = (unsigned long) addr; -+ unsigned long old_handler = exception_handlers[n]; ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ ar71xx_reset_wr(AR91XX_RESET_REG_RESET_MODULE, t & ~mask); ++ local_irq_restore(flags); ++ break; + -+ exception_handlers[n] = handler; -+ if (n == 0 && cpu_has_divec) { -+ unsigned long jump_mask = ~((1 << 28) - 1); -+ u32 *buf = (u32 *)(ebase + 0x200); -+ unsigned int k0 = 26; -+ if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { -+ uasm_i_j(&buf, handler & ~jump_mask); -+ uasm_i_nop(&buf); -+ } else { -+ UASM_i_LA(&buf, k0, handler); -+ uasm_i_jr(&buf, k0); -+ uasm_i_nop(&buf); -+ } -+ local_flush_icache_range(ebase + 0x200, (unsigned long)buf); ++ default: ++ BUG(); + } -+ return (void *)old_handler; -+} -+ -+static asmlinkage void do_default_vi(void) -+{ -+ show_regs(get_irq_regs()); -+ panic("Caught unexpected vectored interrupt."); +} ++EXPORT_SYMBOL_GPL(ar71xx_device_start); + -+static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) ++int ar71xx_device_stopped(u32 mask) +{ -+ unsigned long handler; -+ unsigned long old_handler = vi_handlers[n]; -+ int srssets = current_cpu_data.srsets; -+ u32 *w; -+ unsigned char *b; -+ -+ BUG_ON(!cpu_has_veic && !cpu_has_vint); ++ unsigned long flags; ++ u32 t; + -+ if (addr == NULL) { -+ handler = (unsigned long) do_default_vi; -+ srs = 0; -+ } else -+ handler = (unsigned long) addr; -+ vi_handlers[n] = (unsigned long) addr; ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR71XX_RESET_REG_RESET_MODULE); ++ local_irq_restore(flags); ++ break; + -+ b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ local_irq_restore(flags); ++ break; + -+ if (srs >= srssets) -+ panic("Shadow register set %d not supported", srs); ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ local_irq_save(flags); ++ t = ar71xx_reset_rr(AR91XX_RESET_REG_RESET_MODULE); ++ local_irq_restore(flags); ++ break; + -+ if (cpu_has_veic) { -+ if (board_bind_eic_interrupt) -+ board_bind_eic_interrupt(n, srs); -+ } else if (cpu_has_vint) { -+ /* SRSMap is only defined if shadow sets are implemented */ -+ if (srssets > 1) -+ change_c0_srsmap(0xf << n*4, srs << n*4); ++ default: ++ BUG(); + } + -+ if (srs == 0) { -+ /* -+ * If no shadow set is selected then use the default handler -+ * that does normal register saving and a standard interrupt exit -+ */ -+ -+ extern char except_vec_vi, except_vec_vi_lui; -+ extern char except_vec_vi_ori, except_vec_vi_end; -+ extern char rollback_except_vec_vi; -+ char *vec_start = (cpu_wait == r4k_wait) ? -+ &rollback_except_vec_vi : &except_vec_vi; -+#ifdef CONFIG_MIPS_MT_SMTC -+ /* -+ * We need to provide the SMTC vectored interrupt handler -+ * not only with the address of the handler, but with the -+ * Status.IM bit to be masked before going there. -+ */ -+ extern char except_vec_vi_mori; -+ const int mori_offset = &except_vec_vi_mori - vec_start; -+#endif /* CONFIG_MIPS_MT_SMTC */ -+ const int handler_len = &except_vec_vi_end - vec_start; -+ const int lui_offset = &except_vec_vi_lui - vec_start; -+ const int ori_offset = &except_vec_vi_ori - vec_start; -+ -+ if (handler_len > VECTORSPACING) { -+ /* -+ * Sigh... panicing won't help as the console -+ * is probably not configured :( -+ */ -+ panic("VECTORSPACING too small"); -+ } ++ return ((t & mask) == mask); ++} ++EXPORT_SYMBOL_GPL(ar71xx_device_stopped); + -+ memcpy(b, vec_start, handler_len); -+#ifdef CONFIG_MIPS_MT_SMTC -+ BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */ -+ -+ w = (u32 *)(b + mori_offset); -+ *w = (*w & 0xffff0000) | (0x100 << n); -+#endif /* CONFIG_MIPS_MT_SMTC */ -+ w = (u32 *)(b + lui_offset); -+ *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); -+ w = (u32 *)(b + ori_offset); -+ *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); -+ local_flush_icache_range((unsigned long)b, -+ (unsigned long)(b+handler_len)); -+ } -+ else { -+ /* -+ * In other cases jump directly to the interrupt handler -+ * -+ * It is the handlers responsibility to save registers if required -+ * (eg hi/lo) and return from the exception using "eret" -+ */ -+ w = (u32 *)b; -+ *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ -+ *w = 0; -+ local_flush_icache_range((unsigned long)b, -+ (unsigned long)(b+8)); -+ } ++void ar71xx_ddr_flush(u32 reg) ++{ ++ ar71xx_ddr_wr(reg, 1); ++ while ((ar71xx_ddr_rr(reg) & 0x1)); + -+ return (void *)old_handler; ++ ar71xx_ddr_wr(reg, 1); ++ while ((ar71xx_ddr_rr(reg) & 0x1)); +} ++EXPORT_SYMBOL_GPL(ar71xx_ddr_flush); + -+void *set_vi_handler(int n, vi_handler_t addr) ++void ar71xx_flash_acquire(void) +{ -+ return set_vi_srs_handler(n, addr, 0); ++ mutex_lock(&ar71xx_flash_mutex); +} ++EXPORT_SYMBOL_GPL(ar71xx_flash_acquire); + -+extern void cpu_cache_init(void); -+extern void tlb_init(void); -+extern void flush_tlb_handlers(void); -+ ++void ar71xx_flash_release(void) ++{ ++ mutex_unlock(&ar71xx_flash_mutex); ++} ++EXPORT_SYMBOL_GPL(ar71xx_flash_release); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-eth.c linux-2.6.36/arch/mips/ar71xx/dev-ap91-eth.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-eth.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-ap91-eth.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,70 @@ +/* -+ * Timer interrupt ++ * Atheros AP91 reference board ethernet initialization ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ -+int cp0_compare_irq; -+int cp0_compare_irq_shift; + -+/* -+ * Performance counter IRQ or -1 if shared with timer -+ */ -+int cp0_perfcount_irq; -+EXPORT_SYMBOL_GPL(cp0_perfcount_irq); ++#include "devices.h" ++#include "dev-dsa.h" ++#include "dev-ap91-eth.h" ++ ++static struct dsa_chip_data ap91_dsa_chip = { ++ .port_names[0] = "cpu", ++ .port_names[1] = "lan1", ++ .port_names[2] = "lan2", ++ .port_names[3] = "lan3", ++ .port_names[4] = "lan4", ++}; + -+static int __cpuinitdata noulri; ++static struct dsa_platform_data ap91_dsa_data = { ++ .nr_chips = 1, ++ .chip = &ap91_dsa_chip, ++}; + -+static int __init ulri_disable(char *s) ++static void ap91_eth_set_port_name(unsigned port, const char *name) +{ -+ pr_info("Disabling ulri\n"); -+ noulri = 1; ++ if (port < 1 || port > 5) ++ return; + -+ return 1; ++ if (name) ++ ap91_dsa_chip.port_names[port] = (char *) name; +} -+__setup("noulri", ulri_disable); + -+void __cpuinit per_cpu_trap_init(void) ++void __init ap91_eth_init(u8 *mac_addr, const char *port_names[]) +{ -+ unsigned int cpu = smp_processor_id(); -+ unsigned int status_set = ST0_CU0; -+#ifdef CONFIG_MIPS_MT_SMTC -+ int secondaryTC = 0; -+ int bootTC = (cpu == 0); -+ -+ /* -+ * Only do per_cpu_trap_init() for first TC of Each VPE. -+ * Note that this hack assumes that the SMTC init code -+ * assigns TCs consecutively and in ascending order. -+ */ -+ -+ if (((read_c0_tcbind() & TCBIND_CURTC) != 0) && -+ ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id)) -+ secondaryTC = 1; -+#endif /* CONFIG_MIPS_MT_SMTC */ -+ -+ /* -+ * Disable coprocessors and select 32-bit or 64-bit addressing -+ * and the 16/32 or 32/32 FPR register model. Reset the BEV -+ * flag that some firmware may have left set and the TS bit (for -+ * IP27). Set XX for ISA IV code to work. -+ */ -+#ifdef CONFIG_64BIT -+ status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX; -+#endif -+ if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV) -+ status_set |= ST0_XX; -+ if (cpu_has_dsp) -+ status_set |= ST0_MX; -+ -+ change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX, -+ status_set); -+ -+ if (cpu_has_mips_r2) { -+ unsigned int enable = 0x0000000f | cpu_hwrena_impl_bits; -+ -+ if (!noulri && cpu_has_userlocal) -+ enable |= (1 << 29); -+ -+ write_c0_hwrena(enable); -+ } -+ -+#ifdef CONFIG_MIPS_MT_SMTC -+ if (!secondaryTC) { -+#endif /* CONFIG_MIPS_MT_SMTC */ -+ -+ if (cpu_has_veic || cpu_has_vint) { -+ unsigned long sr = set_c0_status(ST0_BEV); -+ write_c0_ebase(ebase); -+ write_c0_status(sr); -+ /* Setting vector spacing enables EI/VI mode */ -+ change_c0_intctl(0x3e0, VECTORSPACING); -+ } -+ if (cpu_has_divec) { -+ if (cpu_has_mipsmt) { -+ unsigned int vpflags = dvpe(); -+ set_c0_cause(CAUSEF_IV); -+ evpe(vpflags); -+ } else -+ set_c0_cause(CAUSEF_IV); -+ } ++ if (mac_addr) ++ ar71xx_set_mac_base(mac_addr); + -+ /* -+ * Before R2 both interrupt numbers were fixed to 7, so on R2 only: -+ * -+ * o read IntCtl.IPTI to determine the timer interrupt -+ * o read IntCtl.IPPCI to determine the performance counter interrupt -+ */ -+ if (cpu_has_mips_r2) { -+ cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; -+ cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; -+ cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; -+ if (cp0_perfcount_irq == cp0_compare_irq) -+ cp0_perfcount_irq = -1; -+ } else { -+ cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; -+ cp0_compare_irq_shift = cp0_compare_irq; -+ cp0_perfcount_irq = -1; -+ } ++ if (port_names) { ++ int i; + -+#ifdef CONFIG_MIPS_MT_SMTC ++ for (i = 0; i < AP91_ETH_NUM_PORT_NAMES; i++) ++ ap91_eth_set_port_name(i + 1, port_names[i]); + } -+#endif /* CONFIG_MIPS_MT_SMTC */ + -+ cpu_data[cpu].asid_cache = ASID_FIRST_VERSION; -+ TLBMISS_HANDLER_SETUP(); ++ /* WAN port */ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.fifo_cfg1 = 0x0fff0000; ++ ar71xx_eth0_data.fifo_cfg2 = 0x00001fff; ++ ar71xx_eth0_data.fifo_cfg3 = 0x008001ff; + -+ atomic_inc(&init_mm.mm_count); -+ current->active_mm = &init_mm; -+ BUG_ON(current->mm); -+ enter_lazy_tlb(&init_mm, current); ++ /* LAN ports */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ar71xx_eth1_data.fifo_cfg1 = 0x0fff0000; ++ ar71xx_eth1_data.fifo_cfg2 = 0x00001fff; ++ ar71xx_eth1_data.fifo_cfg3 = 0x008001ff; + -+#ifdef CONFIG_MIPS_MT_SMTC -+ if (bootTC) { -+#endif /* CONFIG_MIPS_MT_SMTC */ -+ cpu_cache_init(); -+ tlb_init(); -+#ifdef CONFIG_MIPS_MT_SMTC -+ } else if (!secondaryTC) { -+ /* -+ * First TC in non-boot VPE must do subset of tlb_init() -+ * for MMU countrol registers. -+ */ -+ write_c0_pagemask(PM_DEFAULT_MASK); -+ write_c0_wired(0); -+ } -+#endif /* CONFIG_MIPS_MT_SMTC */ -+} ++ ar71xx_add_device_mdio(0x0); ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); + -+/* Install CPU exception handler */ -+void __init set_handler(unsigned long offset, void *addr, unsigned long size) -+{ -+ memcpy((void *)(ebase + offset), addr, size); -+ local_flush_icache_range(ebase + offset, ebase + offset + size); ++ ar71xx_add_device_dsa(1, &ap91_dsa_data); +} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-eth.h linux-2.6.36/arch/mips/ar71xx/dev-ap91-eth.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-eth.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-ap91-eth.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,23 @@ ++/* ++ * Atheros AP91 reference board ethernet initialization ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static char panic_null_cerr[] __cpuinitdata = -+ "Trying to set NULL cache error exception handler"; ++#ifndef _AR71XX_DEV_AP91_ETH_H ++#define _AR71XX_DEV_AP91_ETH_H + -+/* -+ * Install uncached CPU exception handler. -+ * This is suitable only for the cache error exception which is the only -+ * exception handler that is being run uncached. -+ */ -+void __cpuinit set_uncached_handler(unsigned long offset, void *addr, -+ unsigned long size) -+{ -+ unsigned long uncached_ebase = CKSEG1ADDR(ebase); ++#define AP91_ETH_NUM_PORT_NAMES 4 + -+ if (!addr) -+ panic(panic_null_cerr); ++#if defined(CONFIG_AR71XX_DEV_AP91_ETH) ++void ap91_eth_init(u8 *mac_addr, const char *port_names[]) __init; ++#else ++static inline void ap91_eth_init(u8 *mac_addr) { } ++#endif + -+ memcpy((void *)(uncached_ebase + offset), addr, size); -+} ++#endif /* _AR71XX_DEV_AP91_ETH_H */ + -+static int __initdata rdhwr_noopt; -+static int __init set_rdhwr_noopt(char *str) -+{ -+ rdhwr_noopt = 1; -+ return 1; -+} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-pci.c linux-2.6.36/arch/mips/ar71xx/dev-ap91-pci.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-ap91-pci.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,114 @@ ++/* ++ * Atheros AP91 reference board PCI initialization ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+__setup("rdhwr_noopt", set_rdhwr_noopt); ++#include ++#include ++#include + -+void __init trap_init(void) -+{ -+ extern char except_vec3_generic, except_vec3_r4000; -+ extern char except_vec4; -+ unsigned long i; -+ int rollback; ++#include ++#include + -+ check_wait(); -+ rollback = (cpu_wait == r4k_wait); ++#include "dev-ap91-pci.h" + -+#if defined(CONFIG_KGDB) -+ if (kgdb_early_setup) -+ return; /* Already done */ -+#endif ++static struct ath9k_platform_data ap91_wmac_data; ++static char ap91_wmac_mac[6]; ++static int ap91_pci_fixup_enabled; + -+ if (cpu_has_veic || cpu_has_vint) { -+ unsigned long size = 0x200 + VECTORSPACING*64; -+ ebase = (unsigned long) -+ __alloc_bootmem(size, 1 << fls(size), 0); -+ } else { -+ ebase = CKSEG0; -+ if (cpu_has_mips_r2) -+ ebase += (read_c0_ebase() & 0x3ffff000); ++static struct ar71xx_pci_irq ap91_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, + } ++}; + -+ per_cpu_trap_init(); ++static int ap91_pci_plat_dev_init(struct pci_dev *dev) ++{ ++ switch(PCI_SLOT(dev->devfn)) { ++ case 0: ++ dev->dev.platform_data = &ap91_wmac_data; ++ break; ++ } + -+ /* -+ * Copy the generic exception handlers to their final destination. -+ * This will be overriden later as suitable for a particular -+ * configuration. -+ */ -+ set_handler(0x180, &except_vec3_generic, 0x80); ++ return 0; ++} + -+ /* -+ * Setup default vectors -+ */ -+ for (i = 0; i <= 31; i++) -+ set_except_vector(i, handle_reserved); ++static void ap91_pci_fixup(struct pci_dev *dev) ++{ ++ void __iomem *mem; ++ u16 *cal_data; ++ u16 cmd; ++ u32 val; + -+ /* -+ * Copy the EJTAG debug exception vector handler code to it's final -+ * destination. -+ */ -+ if (cpu_has_ejtag && board_ejtag_handler_setup) -+ board_ejtag_handler_setup(); ++ if (!ap91_pci_fixup_enabled) ++ return; + -+ /* -+ * Only some CPUs have the watch exceptions. -+ */ -+ if (cpu_has_watch) -+ set_except_vector(23, handle_watch); ++ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); + -+ /* -+ * Initialise interrupt handlers -+ */ -+ if (cpu_has_veic || cpu_has_vint) { -+ int nvec = cpu_has_veic ? 64 : 8; -+ for (i = 0; i < nvec; i++) -+ set_vi_handler(i, NULL); ++ cal_data = ap91_wmac_data.eeprom_data; ++ if (*cal_data != 0xa55a) { ++ printk(KERN_ERR "PCI: no calibration data found for %s\n", ++ pci_name(dev)); ++ return; + } -+ else if (cpu_has_divec) -+ set_handler(0x200, &except_vec4, 0x8); -+ -+ /* -+ * Some CPUs can enable/disable for cache parity detection, but does -+ * it different ways. -+ */ -+ parity_protection_init(); + -+ /* -+ * The Data Bus Errors / Instruction Bus Errors are signaled -+ * by external hardware. Therefore these two exceptions -+ * may have board specific handlers. -+ */ -+ if (board_be_init) -+ board_be_init(); -+ -+ set_except_vector(0, rollback ? rollback_handle_int : handle_int); -+ set_except_vector(1, handle_tlbm); -+ set_except_vector(2, handle_tlbl); -+ set_except_vector(3, handle_tlbs); -+ -+ set_except_vector(4, handle_adel); -+ set_except_vector(5, handle_ades); -+ -+ set_except_vector(6, handle_ibe); -+ set_except_vector(7, handle_dbe); -+ -+ set_except_vector(8, handle_sys); -+ set_except_vector(9, handle_bp); -+ set_except_vector(10, rdhwr_noopt ? handle_ri : -+ (cpu_has_vtag_icache ? -+ handle_ri_rdhwr_vivt : handle_ri_rdhwr)); -+ set_except_vector(11, handle_cpu); -+ set_except_vector(12, handle_ov); -+ set_except_vector(13, handle_tr); -+ -+ if (current_cpu_type() == CPU_R6000 || -+ current_cpu_type() == CPU_R6000A) { -+ /* -+ * The R6000 is the only R-series CPU that features a machine -+ * check exception (similar to the R4000 cache error) and -+ * unaligned ldc1/sdc1 exception. The handlers have not been -+ * written yet. Well, anyway there is no R6000 machine on the -+ * current list of targets for Linux/MIPS. -+ * (Duh, crap, there is someone with a triple R6k machine) -+ */ -+ //set_except_vector(14, handle_mc); -+ //set_except_vector(15, handle_ndc); ++ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); ++ if (!mem) { ++ printk(KERN_ERR "PCI: ioremap error for device %s\n", ++ pci_name(dev)); ++ return; + } + ++ /* Setup the PCI device to allow access to the internal registers */ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0xffff); ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); + -+ if (board_nmi_handler_setup) -+ board_nmi_handler_setup(); -+ -+ if (cpu_has_fpu && !cpu_has_nofpuex) -+ set_except_vector(15, handle_fpe); ++ /* set pointer to first reg address */ ++ cal_data += 3; ++ while (*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; + -+ set_except_vector(22, handle_mdmx); ++ __raw_writel(val, mem + reg); ++ udelay(100); ++ } + -+ if (cpu_has_mcheck) -+ set_except_vector(24, handle_mcheck); ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; + -+ if (cpu_has_mipsmt) -+ set_except_vector(25, handle_mt); ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ + -+ set_except_vector(26, handle_dsp); ++ iounmap(mem); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap91_pci_fixup); + -+ if (cpu_has_vce) -+ /* Special exception: R4[04]00 uses also the divec space. */ -+ memcpy((void *)(ebase + 0x180), &except_vec3_r4000, 0x100); -+ else if (cpu_has_4kex) -+ memcpy((void *)(ebase + 0x180), &except_vec3_generic, 0x80); -+ else -+ memcpy((void *)(ebase + 0x080), &except_vec3_generic, 0x80); ++void __init ap91_pci_init(u8 *cal_data, u8 *mac_addr) ++{ ++ if (cal_data) ++ memcpy(ap91_wmac_data.eeprom_data, cal_data, ++ sizeof(ap91_wmac_data.eeprom_data)); + -+ local_flush_icache_range(ebase, ebase + 0x400); -+ flush_tlb_handlers(); ++ if (mac_addr) { ++ memcpy(ap91_wmac_mac, mac_addr, sizeof(ap91_wmac_mac)); ++ ap91_wmac_data.macaddr = ap91_wmac_mac; ++ } + -+ sort_extable(__start___dbe_table, __stop___dbe_table); ++ ar71xx_pci_plat_dev_init = ap91_pci_plat_dev_init; ++ ar71xx_pci_init(ARRAY_SIZE(ap91_pci_irqs), ap91_pci_irqs); + -+ register_cu2_notifier(&default_cu2_notifier); ++ ap91_pci_fixup_enabled = 1; +} -diff -Nur linux-2.6.35.7.orig/arch/mips/Makefile linux-2.6.35.7/arch/mips/Makefile ---- linux-2.6.35.7.orig/arch/mips/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/arch/mips/Makefile 2010-10-14 20:27:59.685601082 +0200 -@@ -179,6 +179,13 @@ - cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon - endif - -+# -+# Atheros AR71xx -+# -+core-$(CONFIG_ATHEROS_AR71XX) += arch/mips/ar71xx/ -+cflags-$(CONFIG_ATHEROS_AR71XX) += -I$(srctree)/arch/mips/include/asm/mach-ar71xx -+load-$(CONFIG_ATHEROS_AR71XX) += 0xffffffff80060000 -+ - cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) - cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) - cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) -diff -Nur linux-2.6.35.7.orig/arch/mips/pci/Makefile linux-2.6.35.7/arch/mips/pci/Makefile ---- linux-2.6.35.7.orig/arch/mips/pci/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/arch/mips/pci/Makefile 2010-10-14 20:27:59.718092160 +0200 -@@ -18,6 +18,7 @@ - obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o - obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ - ops-bcm63xx.o -+obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o - - # - # These are still pretty much in the old state, watch, go blind. -diff -Nur linux-2.6.35.7.orig/arch/mips/pci/pci-ar71xx.c linux-2.6.35.7/arch/mips/pci/pci-ar71xx.c ---- linux-2.6.35.7.orig/arch/mips/pci/pci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/pci/pci-ar71xx.c 2010-10-14 20:27:59.758101117 +0200 -@@ -0,0 +1,409 @@ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-pci.h linux-2.6.36/arch/mips/ar71xx/dev-ap91-pci.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap91-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-ap91-pci.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,21 @@ +/* -+ * Atheros AR71xx PCI host controller driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz ++ * Atheros AP91 reference board PCI initialization + * -+ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include ++#ifndef _AR71XX_DEV_AP91_PCI_H ++#define _AR71XX_DEV_AP91_PCI_H + -+#undef DEBUG -+#ifdef DEBUG -+#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) ++#if defined(CONFIG_AR71XX_DEV_AP91_PCI) ++void ap91_pci_init(u8 *cal_data, u8 *mac_addr) __init; +#else -+#define DBG(fmt, args...) ++static inline void ap91_pci_init(u8 *cal_data, u8 *mac_addr) { } +#endif + -+#define AR71XX_PCI_DELAY 100 /* msecs */ ++#endif /* _AR71XX_DEV_AP91_PCI_H */ + -+#if 0 -+#define PCI_IDSEL_BASE PCI_IDSEL_ADL_START -+#else -+#define PCI_IDSEL_BASE 0 -+#endif +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap94-pci.c linux-2.6.36/arch/mips/ar71xx/dev-ap94-pci.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap94-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-ap94-pci.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,159 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static void __iomem *ar71xx_pcicfg_base; -+static DEFINE_SPINLOCK(ar71xx_pci_lock); -+static int ar71xx_pci_fixup_enable; ++#include ++#include ++#include + -+static inline void ar71xx_pci_delay(void) -+{ -+ mdelay(AR71XX_PCI_DELAY); -+} ++#include ++#include + -+/* Byte lane enable bits */ -+static u8 ble_table[4][4] = { -+ {0x0, 0xf, 0xf, 0xf}, -+ {0xe, 0xd, 0xb, 0x7}, -+ {0xc, 0xf, 0x3, 0xf}, -+ {0xf, 0xf, 0xf, 0xf}, -+}; ++#include "dev-ap94-pci.h" + -+static inline u32 ar71xx_pci_get_ble(int where, int size, int local) -+{ -+ u32 t; ++static struct ath9k_platform_data ap94_wmac0_data; ++static struct ath9k_platform_data ap94_wmac1_data; ++static char ap94_wmac0_mac[6]; ++static char ap94_wmac1_mac[6]; ++static int ap94_pci_fixup_enabled; + -+ t = ble_table[size & 3][where & 3]; -+ BUG_ON(t == 0xf); -+ t <<= (local) ? 20 : 4; -+ return t; -+} ++static struct ar71xx_pci_irq ap94_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ } ++}; + -+static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, -+ int where) ++static int ap94_pci_plat_dev_init(struct pci_dev *dev) +{ -+ u32 ret; -+ -+ if (!bus->number) { -+ /* type 0 */ -+ ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn))) -+ | (PCI_FUNC(devfn) << 8) | (where & ~3); -+ } else { -+ /* type 1 */ -+ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) -+ | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; ++ switch(PCI_SLOT(dev->devfn)) { ++ case 17: ++ dev->dev.platform_data = &ap94_wmac0_data; ++ break; ++ ++ case 18: ++ dev->dev.platform_data = &ap94_wmac1_data; ++ break; + } + -+ return ret; ++ return 0; +} + -+int ar71xx_pci_be_handler(int is_fixup) ++static void ap94_pci_fixup(struct pci_dev *dev) +{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 pci_err; -+ u32 ahb_err; ++ void __iomem *mem; ++ u16 *cal_data; ++ u16 cmd; ++ u32 bar0; ++ u32 val; + -+ pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3; -+ if (pci_err) { -+ if (!is_fixup) -+ printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n", -+ pci_err, -+ __raw_readl(base + PCI_REG_PCI_ERR_ADDR)); ++ if (!ap94_pci_fixup_enabled) ++ return; + -+ __raw_writel(pci_err, base + PCI_REG_PCI_ERR); ++ switch (PCI_SLOT(dev->devfn)) { ++ case 17: ++ cal_data = ap94_wmac0_data.eeprom_data; ++ break; ++ case 18: ++ cal_data = ap94_wmac1_data.eeprom_data; ++ break; ++ default: ++ return; + } + -+ ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1; -+ if (ahb_err) { -+ if (!is_fixup) -+ printk(KERN_ALERT "AHB error at AHB address 0x%x\n", -+ __raw_readl(base + PCI_REG_AHB_ERR_ADDR)); -+ -+ __raw_writel(ahb_err, base + PCI_REG_AHB_ERR); ++ if (*cal_data != 0xa55a) { ++ printk(KERN_ERR "PCI: no calibration data found for %s\n", ++ pci_name(dev)); ++ return; + } + -+ return ((ahb_err | pci_err) ? 1 : 0); -+} -+ -+static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, -+ unsigned int devfn, int where, int size, u32 cmd) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ u32 addr; ++ mem = ioremap(AR71XX_PCI_MEM_BASE, 0x10000); ++ if (!mem) { ++ printk(KERN_ERR "PCI: ioremap error for device %s\n", ++ pci_name(dev)); ++ return; ++ } + -+ addr = ar71xx_pci_bus_addr(bus, devfn, where); ++ printk(KERN_INFO "PCI: fixup device %s\n", pci_name(dev)); + -+ DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, addr); ++ pci_read_config_dword(dev, PCI_BASE_ADDRESS_0, &bar0); + -+ __raw_writel(addr, base + PCI_REG_CFG_AD); -+ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), -+ base + PCI_REG_CFG_CBE); ++ /* Setup the PCI device to allow access to the internal registers */ ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, AR71XX_PCI_MEM_BASE); ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ++ pci_write_config_word(dev, PCI_COMMAND, cmd); + -+ return ar71xx_pci_be_handler(1); -+} ++ /* set pointer to first reg address */ ++ cal_data += 3; ++ while (*cal_data != 0xffff) { ++ u32 reg; ++ reg = *cal_data++; ++ val = *cal_data++; ++ val |= (*cal_data++) << 16; + -+static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; -+ unsigned long flags; -+ u32 data; -+ int ret; ++ __raw_writel(val, mem + reg); ++ udelay(100); ++ } + -+ ret = PCIBIOS_SUCCESSFUL; ++ pci_read_config_dword(dev, PCI_VENDOR_ID, &val); ++ dev->vendor = val & 0xffff; ++ dev->device = (val >> 16) & 0xffff; + -+ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number, -+ PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); ++ pci_read_config_dword(dev, PCI_CLASS_REVISION, &val); ++ dev->revision = val & 0xff; ++ dev->class = val >> 8; /* upper 3 bytes */ + -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); ++ pci_write_config_word(dev, PCI_COMMAND, cmd); + -+ if (bus->number == 0 && devfn == 0) { -+ u32 t; ++ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, bar0); + -+ t = PCI_CRP_CMD_READ | (where & ~3); ++ iounmap(mem); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ap94_pci_fixup); + -+ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); -+ data = __raw_readl(base + PCI_REG_CRP_RDDATA); ++void __init ap94_pci_enable_quirk_wndr3700(void) ++{ ++ ap94_wmac0_data.quirk_wndr3700 = 1; ++ ap94_wmac1_data.quirk_wndr3700 = 1; ++} + -+ DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data); ++void __init ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) ++{ ++ if (cal_data0) ++ memcpy(ap94_wmac0_data.eeprom_data, cal_data0, ++ sizeof(ap94_wmac0_data.eeprom_data)); + -+ } else { -+ int err; ++ if (cal_data1) ++ memcpy(ap94_wmac1_data.eeprom_data, cal_data1, ++ sizeof(ap94_wmac1_data.eeprom_data)); + -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ PCI_CFG_CMD_READ); ++ if (mac_addr0) { ++ memcpy(ap94_wmac0_mac, mac_addr0, sizeof(ap94_wmac0_mac)); ++ ap94_wmac0_data.macaddr = ap94_wmac0_mac; ++ } + -+ if (err == 0) { -+ data = __raw_readl(base + PCI_REG_CFG_RDDATA); -+ } else { -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ data = ~0; -+ } ++ if (mac_addr1) { ++ memcpy(ap94_wmac1_mac, mac_addr1, sizeof(ap94_wmac1_mac)); ++ ap94_wmac1_data.macaddr = ap94_wmac1_mac; + } + -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++ ar71xx_pci_plat_dev_init = ap94_pci_plat_dev_init; ++ ar71xx_pci_init(ARRAY_SIZE(ap94_pci_irqs), ap94_pci_irqs); + -+ DBG("PCI: read config: data=%08x raw=%08x\n", -+ (data >> (8 * (where & 3))) & mask[size & 7], data); ++ ap94_pci_fixup_enabled = 1; ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ap94-pci.h linux-2.6.36/arch/mips/ar71xx/dev-ap94-pci.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-ap94-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-ap94-pci.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,28 @@ ++/* ++ * Atheros AP94 reference board PCI initialization ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ *value = (data >> (8 * (where & 3))) & mask[size & 7]; ++#ifndef _AR71XX_DEV_AP94_PCI_H ++#define _AR71XX_DEV_AP94_PCI_H + -+ return ret; -+} ++#if defined(CONFIG_AR71XX_DEV_AP94_PCI) ++void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) __init; + -+static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ void __iomem *base = ar71xx_pcicfg_base; -+ unsigned long flags; -+ int ret; ++void ap94_pci_enable_quirk_wndr3700(void) __init; + -+ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, value); ++#else ++static inline void ap94_pci_init(u8 *cal_data0, u8 *mac_addr0, ++ u8 *cal_data1, u8 *mac_addr1) {} + -+ value = value << (8 * (where & 3)); -+ ret = PCIBIOS_SUCCESSFUL; ++static inline void ap94_pci_enable_quirk_wndr3700(void) {} ++#endif + -+ spin_lock_irqsave(&ar71xx_pci_lock, flags); -+ if (bus->number == 0 && devfn == 0) { -+ u32 t; ++#endif /* _AR71XX_DEV_AP94_PCI_H */ + -+ t = PCI_CRP_CMD_WRITE | (where & ~3); -+ t |= ar71xx_pci_get_ble(where, size, 1); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ar913x-wmac.c linux-2.6.36/arch/mips/ar71xx/dev-ar913x-wmac.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-ar913x-wmac.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-ar913x-wmac.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,68 @@ ++/* ++ * Atheros AR913x SoC built-in WMAC device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value); ++#include ++#include ++#include ++#include ++#include ++#include + -+ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); -+ __raw_writel(value, base + PCI_REG_CRP_WRDATA); -+ } else { -+ int err; ++#include + -+ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, -+ PCI_CFG_CMD_WRITE); ++#include "dev-ar913x-wmac.h" + -+ if (err == 0) -+ __raw_writel(value, base + PCI_REG_CFG_WRDATA); -+ else -+ ret = PCIBIOS_DEVICE_NOT_FOUND; -+ } -+ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); ++static struct ath9k_platform_data ar913x_wmac_data; ++static char ar913x_wmac_mac[6]; + -+ return ret; -+} ++static struct resource ar913x_wmac_resources[] = { ++ { ++ .start = AR91XX_WMAC_BASE, ++ .end = AR91XX_WMAC_BASE + AR91XX_WMAC_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = AR71XX_CPU_IRQ_IP2, ++ .end = AR71XX_CPU_IRQ_IP2, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; + -+static void ar71xx_pci_fixup(struct pci_dev *dev) -+{ -+ u32 t; ++static struct platform_device ar913x_wmac_device = { ++ .name = "ath9k", ++ .id = -1, ++ .resource = ar913x_wmac_resources, ++ .num_resources = ARRAY_SIZE(ar913x_wmac_resources), ++ .dev = { ++ .platform_data = &ar913x_wmac_data, ++ }, ++}; + -+ if (!ar71xx_pci_fixup_enable) -+ return; ++void __init ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) ++{ ++ if (cal_data) ++ memcpy(ar913x_wmac_data.eeprom_data, cal_data, ++ sizeof(ar913x_wmac_data.eeprom_data)); + -+ if (dev->bus->number != 0 || dev->devfn != 0) -+ return; ++ if (mac_addr) { ++ memcpy(ar913x_wmac_mac, mac_addr, sizeof(ar913x_wmac_mac)); ++ ar913x_wmac_data.macaddr = ar913x_wmac_mac; ++ } + -+ DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev), -+ dev->vendor, dev->device); ++ ar71xx_device_stop(RESET_MODULE_AMBA2WMAC); ++ mdelay(10); + -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE -+ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; ++ ar71xx_device_start(RESET_MODULE_AMBA2WMAC); ++ mdelay(10); + -+ pci_write_config_word(dev, PCI_COMMAND, t); ++ platform_device_register(&ar913x_wmac_device); +} -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup); -+ -+int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, -+ uint8_t pin) -+{ -+ int irq = -1; -+ int i; -+ -+ slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE; -+ -+ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { -+ struct ar71xx_pci_irq *entry; +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-ar913x-wmac.h linux-2.6.36/arch/mips/ar71xx/dev-ar913x-wmac.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-ar913x-wmac.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-ar913x-wmac.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,19 @@ ++/* ++ * Atheros AR913x SoC built-in WMAC device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ entry = &ar71xx_pci_irq_map[i]; -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } ++#ifndef _AR71XX_DEV_AR913X_WMAC_H ++#define _AR71XX_DEV_AR913X_WMAC_H + -+ if (irq < 0) { -+ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", -+ pin, pci_name((struct pci_dev *)dev)); -+ } else { -+ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", -+ irq, pin, pci_name((struct pci_dev *)dev)); -+ } ++void ar913x_add_device_wmac(u8 *cal_data, u8 *mac_addr) __init; + -+ return irq; -+} ++#endif /* _AR71XX_DEV_AR913X_WMAC_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-dsa.c linux-2.6.36/arch/mips/ar71xx/dev-dsa.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-dsa.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-dsa.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,50 @@ ++/* ++ * Atheros AR71xx DSA switch device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static struct pci_ops ar71xx_pci_ops = { -+ .read = ar71xx_pci_read_config, -+ .write = ar71xx_pci_write_config, -+}; ++#include ++#include + -+static struct resource ar71xx_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; ++#include + -+static struct resource ar71xx_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; ++#include "devices.h" ++#include "dev-dsa.h" + -+static struct pci_controller ar71xx_pci_controller = { -+ .pci_ops = &ar71xx_pci_ops, -+ .mem_resource = &ar71xx_pci_mem_resource, -+ .io_resource = &ar71xx_pci_io_resource, ++static struct platform_device ar71xx_dsa_switch_device = { ++ .name = "dsa", ++ .id = 0, +}; + -+static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++void __init ar71xx_add_device_dsa(unsigned int id, ++ struct dsa_platform_data *d) +{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 pending; -+ -+ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & -+ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ -+ if (pending & PCI_INT_DEV0) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); ++ int i; + -+ else if (pending & PCI_INT_DEV1) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV1); ++ switch (id) { ++ case 0: ++ d->netdev = &ar71xx_eth0_device.dev; ++ break; ++ case 1: ++ d->netdev = &ar71xx_eth1_device.dev; ++ break; ++ default: ++ printk(KERN_ERR ++ "ar71xx: invalid ethernet id %d for DSA switch\n", ++ id); ++ return; ++ } + -+ else if (pending & PCI_INT_DEV2) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV2); ++ for (i = 0; i < d->nr_chips; i++) ++ d->chip[i].mii_bus = &ar71xx_mdio_device.dev; + -+ else if (pending & PCI_INT_CORE) -+ generic_handle_irq(AR71XX_PCI_IRQ_CORE); ++ ar71xx_dsa_switch_device.dev.platform_data = d; + -+ else -+ spurious_interrupt(); ++ platform_device_register(&ar71xx_dsa_switch_device); +} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-dsa.h linux-2.6.36/arch/mips/ar71xx/dev-dsa.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-dsa.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-dsa.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,20 @@ ++/* ++ * Atheros AR71xx DSA switch device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static void ar71xx_pci_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; ++#ifndef _AR71XX_DEV_DSA_H ++#define _AR71XX_DEV_DSA_H + -+ irq -= AR71XX_PCI_IRQ_BASE; ++#include + -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++void ar71xx_add_device_dsa(unsigned int id, ++ struct dsa_platform_data *d) __init; + -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} ++#endif /* _AR71XX_DEV_DSA_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-gpio-buttons.c linux-2.6.36/arch/mips/ar71xx/dev-gpio-buttons.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-gpio-buttons.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-gpio-buttons.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,58 @@ ++/* ++ * Atheros AR71xx GPIO button support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static void ar71xx_pci_irq_mask(unsigned int irq) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ u32 t; ++#include "linux/init.h" ++#include + -+ irq -= AR71XX_PCI_IRQ_BASE; ++#include "dev-gpio-buttons.h" + -+ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++void __init ar71xx_add_device_gpio_buttons(int id, ++ unsigned poll_interval, ++ unsigned nbuttons, ++ struct gpio_button *buttons) ++{ ++ struct platform_device *pdev; ++ struct gpio_buttons_platform_data pdata; ++ struct gpio_button *p; ++ int err; + -+ /* flush write */ -+ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+} ++ p = kmalloc(nbuttons * sizeof(*p), GFP_KERNEL); ++ if (!p) ++ return; + -+static struct irq_chip ar71xx_pci_irq_chip = { -+ .name = "AR71XX PCI ", -+ .mask = ar71xx_pci_irq_mask, -+ .unmask = ar71xx_pci_irq_unmask, -+ .mask_ack = ar71xx_pci_irq_mask, -+}; ++ memcpy(p, buttons, nbuttons * sizeof(*p)); + -+static void __init ar71xx_pci_irq_init(void) -+{ -+ void __iomem *base = ar71xx_reset_base; -+ int i; ++ pdev = platform_device_alloc("gpio-buttons", id); ++ if (!pdev) ++ goto err_free_buttons; + -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); -+ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); ++ memset(&pdata, 0, sizeof(pdata)); ++ pdata.poll_interval = poll_interval; ++ pdata.nbuttons = nbuttons; ++ pdata.buttons = p; + -+ for (i = AR71XX_PCI_IRQ_BASE; -+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip, -+ handle_level_irq); -+ } ++ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); ++ if (err) ++ goto err_put_pdev; + -+ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); -+} + -+int __init ar71xx_pcibios_init(void) -+{ -+ void __iomem *ddr_base = ar71xx_ddr_base; ++ err = platform_device_add(pdev); ++ if (err) ++ goto err_put_pdev; + -+ ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); -+ ar71xx_pci_delay(); ++ return; + -+ ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); -+ ar71xx_pci_delay(); ++err_put_pdev: ++ platform_device_put(pdev); + -+ ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, -+ AR71XX_PCI_CFG_SIZE); -+ if (ar71xx_pcicfg_base == NULL) -+ return -ENOMEM; ++err_free_buttons: ++ kfree(p); ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-gpio-buttons.h linux-2.6.36/arch/mips/ar71xx/dev-gpio-buttons.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-gpio-buttons.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-gpio-buttons.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,25 @@ ++/* ++ * Atheros AR71xx GPIO button support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); -+ __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); -+ __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); -+ __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); -+ __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); -+ __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); -+ __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); -+ __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); ++#ifndef _AR71XX_DEV_GPIO_BUTTONS_H ++#define _AR71XX_DEV_GPIO_BUTTONS_H + -+ ar71xx_pci_delay(); ++#include ++#include + -+ /* clear bus errors */ -+ (void)ar71xx_pci_be_handler(1); ++#include + -+ ar71xx_pci_fixup_enable = 1; -+ ar71xx_pci_irq_init(); -+ register_pci_controller(&ar71xx_pci_controller); ++void ar71xx_add_device_gpio_buttons(int id, ++ unsigned poll_interval, ++ unsigned nbuttons, ++ struct gpio_button *buttons) __init; + -+ return 0; -+} -diff -Nur linux-2.6.35.7.orig/arch/mips/pci/pci-ar724x.c linux-2.6.35.7/arch/mips/pci/pci-ar724x.c ---- linux-2.6.35.7.orig/arch/mips/pci/pci-ar724x.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/arch/mips/pci/pci-ar724x.c 2010-10-14 20:27:59.798101290 +0200 -@@ -0,0 +1,395 @@ ++#endif /* _AR71XX_DEV_GPIO_BUTTONS_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-leds-gpio.c linux-2.6.36/arch/mips/ar71xx/dev-leds-gpio.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-leds-gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-leds-gpio.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,57 @@ +/* -+ * Atheros AR724x PCI host controller driver ++ * Atheros AR71xx GPIO LED device support + * -+ * Copyright (C) 2009-2010 Gabor Juhos ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * + * Parts of this file are based on Atheros' 2.6.15 BSP + * @@ -11503,11927 +1293,9646 @@ diff -Nur linux-2.6.35.7.orig/arch/mips/pci/pci-ar724x.c linux-2.6.35.7/arch/mip + * by the Free Software Foundation. + */ + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include ++#include ++#include ++#include + -+#undef DEBUG -+#ifdef DEBUG -+#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args) -+#else -+#define DBG(fmt, args...) -+#endif ++#include "dev-leds-gpio.h" + -+static void __iomem *ar724x_pci_localcfg_base; -+static void __iomem *ar724x_pci_devcfg_base; -+static void __iomem *ar724x_pci_ctrl_base; -+static int ar724x_pci_fixup_enable; ++void __init ar71xx_add_device_leds_gpio(int id, unsigned num_leds, ++ struct gpio_led *leds) ++{ ++ struct platform_device *pdev; ++ struct gpio_led_platform_data pdata; ++ struct gpio_led *p; ++ int err; + -+static DEFINE_SPINLOCK(ar724x_pci_lock); ++ p = kmalloc(num_leds * sizeof(*p), GFP_KERNEL); ++ if (!p) ++ return; + -+static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value) -+{ -+ unsigned long flags; -+ u32 data; ++ memcpy(p, leds, num_leds * sizeof(*p)); + -+ spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); ++ pdev = platform_device_alloc("leds-gpio", id); ++ if (!pdev) ++ goto err_free_leds; + -+ switch (size) { -+ case 1: -+ if (where & 1) -+ data >>= 8; -+ if (where & 2) -+ data >>= 16; -+ data &= 0xFF; -+ break; -+ case 2: -+ if (where & 2) -+ data >>= 16; -+ data &= 0xFFFF; -+ break; -+ } ++ memset(&pdata, 0, sizeof(pdata)); ++ pdata.num_leds = num_leds; ++ pdata.leds = p; + -+ *value = data; -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); -+} ++ err = platform_device_add_data(pdev, &pdata, sizeof(pdata)); ++ if (err) ++ goto err_put_pdev; + -+static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value) -+{ -+ unsigned long flags; -+ u32 data; -+ int s; ++ err = platform_device_add(pdev); ++ if (err) ++ goto err_put_pdev; + -+ spin_lock_irqsave(&ar724x_pci_lock, flags); -+ data = __raw_readl(base + (where & ~3)); ++ return; + -+ switch (size) { -+ case 1: -+ s = ((where & 3) << 3); -+ data &= ~(0xFF << s); -+ data |= ((value & 0xFF) << s); -+ break; -+ case 2: -+ s = ((where & 2) << 3); -+ data &= ~(0xFFFF << s); -+ data |= ((value & 0xFFFF) << s); -+ break; -+ case 4: -+ data = value; -+ break; -+ } ++err_put_pdev: ++ platform_device_put(pdev); + -+ __raw_writel(data, base + (where & ~3)); -+ /* flush write */ -+ (void)__raw_readl(base + (where & ~3)); -+ spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++err_free_leds: ++ kfree(p); +} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-leds-gpio.h linux-2.6.36/arch/mips/ar71xx/dev-leds-gpio.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-leds-gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-leds-gpio.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,21 @@ ++/* ++ * Atheros AR71xx GPIO LED device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 *value) -+{ ++#ifndef _AR71XX_DEV_LEDS_GPIO_H ++#define _AR71XX_DEV_LEDS_GPIO_H + -+ if (bus->number != 0 || devfn != 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; ++#include + -+ ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value); ++void ar71xx_add_device_leds_gpio(int id, ++ unsigned num_leds, ++ struct gpio_led *leds) __init; + -+ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, *value); ++#endif /* _AR71XX_DEV_LEDS_GPIO_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-m25p80.c linux-2.6.36/arch/mips/ar71xx/dev-m25p80.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-m25p80.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-m25p80.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ /* -+ * WAR for BAR issue - We are unable to access the PCI device space -+ * if we set the BAR with proper base address -+ */ -+ if ((where == 0x10) && (size == 4)) { -+ if (ar71xx_soc == AR71XX_SOC_AR7240) -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff); -+ else -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0x1000ffff); -+ } ++#include ++#include ++#include + -+ return PCIBIOS_SUCCESSFUL; -+} ++#include "devices.h" ++#include "dev-m25p80.h" + -+static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn, -+ int where, int size, u32 value) -+{ -+ if (bus->number != 0 || devfn != 0) -+ return PCIBIOS_DEVICE_NOT_FOUND; ++static struct spi_board_info ar71xx_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ } ++}; + -+ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", -+ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), -+ where, size, value); ++void __init ar71xx_add_device_m25p80(struct flash_platform_data *pdata) ++{ ++ ar71xx_spi_info[0].platform_data = pdata; ++ ar71xx_add_device_spi(NULL, ar71xx_spi_info, ++ ARRAY_SIZE(ar71xx_spi_info)); ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-m25p80.h linux-2.6.36/arch/mips/ar71xx/dev-m25p80.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-m25p80.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-m25p80.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,16 @@ ++/* ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value); ++#ifndef _AR71XX_DEV_M25P80_H ++#define _AR71XX_DEV_M25P80_H + -+ return PCIBIOS_SUCCESSFUL; -+} ++#include + -+static void ar724x_pci_fixup(struct pci_dev *dev) -+{ -+ u16 cmd; ++void ar71xx_add_device_m25p80(struct flash_platform_data *pdata) __init; + -+ if (!ar724x_pci_fixup_enable) -+ return; ++#endif /* _AR71XX_DEV_M25P80_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-pb42-pci.c linux-2.6.36/arch/mips/ar71xx/dev-pb42-pci.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-pb42-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-pb42-pci.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,40 @@ ++/* ++ * Atheros PB42 reference board PCI initialization ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ if (dev->bus->number != 0 || dev->devfn != 0) -+ return; ++#include + -+ /* setup COMMAND register */ -+ pci_read_config_word(dev, PCI_COMMAND, &cmd); -+ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | -+ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | -+ PCI_COMMAND_FAST_BACK; ++#include ++#include + -+ pci_write_config_word(dev, PCI_COMMAND, cmd); -+} -+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup); ++#include "dev-pb42-pci.h" + -+int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, -+ uint8_t pin) -+{ -+ int irq = -1; -+ int i; ++static struct ar71xx_pci_irq pb42_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ }, { ++ .slot = 2, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV2, ++ } ++}; + -+ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { -+ struct ar71xx_pci_irq *entry; -+ entry = &ar71xx_pci_irq_map[i]; ++void __init pb42_pci_init(void) ++{ ++ ar71xx_pci_init(ARRAY_SIZE(pb42_pci_irqs), pb42_pci_irqs); ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-pb42-pci.h linux-2.6.36/arch/mips/ar71xx/dev-pb42-pci.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-pb42-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-pb42-pci.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,21 @@ ++/* ++ * Atheros PB42 reference board PCI initialization ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ if (entry->slot == slot && entry->pin == pin) { -+ irq = entry->irq; -+ break; -+ } -+ } ++#ifndef _AR71XX_DEV_PB42_PCI_H ++#define _AR71XX_DEV_PB42_PCI_H + -+ if (irq < 0) -+ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", -+ pin, pci_name((struct pci_dev *)dev)); -+ else -+ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", -+ irq, pin, pci_name((struct pci_dev *)dev)); ++#if defined(CONFIG_AR71XX_DEV_PB42_PCI) ++void pb42_pci_init(void) __init; ++#else ++static inline void pb42_pci_init(void) { } ++#endif + -+ return irq; -+} ++#endif /* _AR71XX_DEV_PB42_PCI_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-pb9x-pci.c linux-2.6.36/arch/mips/ar71xx/dev-pb9x-pci.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-pb9x-pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-pb9x-pci.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,33 @@ ++/* ++ * Atheros PB9x reference board PCI initialization ++ * ++ * Copyright (C) 2010 Felix Fietkau ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static struct pci_ops ar724x_pci_ops = { -+ .read = ar724x_pci_read_config, -+ .write = ar724x_pci_write_config, -+}; ++#include + -+static struct resource ar724x_pci_io_resource = { -+ .name = "PCI IO space", -+ .start = 0, -+ .end = 0, -+ .flags = IORESOURCE_IO, -+}; ++#include ++#include + -+static struct resource ar724x_pci_mem_resource = { -+ .name = "PCI memory space", -+ .start = AR71XX_PCI_MEM_BASE, -+ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, -+ .flags = IORESOURCE_MEM -+}; ++#include "dev-pb9x-pci.h" + -+static struct pci_controller ar724x_pci_controller = { -+ .pci_ops = &ar724x_pci_ops, -+ .mem_resource = &ar724x_pci_mem_resource, -+ .io_resource = &ar724x_pci_io_resource, ++static struct ar71xx_pci_irq pb9x_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ } +}; + -+static void __init ar724x_pci_reset(void) ++void __init pb9x_pci_init(void) +{ -+ ar71xx_device_stop(AR724X_RESET_PCIE); -+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY); -+ ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL); -+ udelay(100); -+ -+ ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL); -+ udelay(100); -+ ar71xx_device_start(AR724X_RESET_PCIE_PHY); -+ ar71xx_device_start(AR724X_RESET_PCIE); ++ ar71xx_pci_init(ARRAY_SIZE(pb9x_pci_irqs), pb9x_pci_irqs); +} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-pb9x-pci.h linux-2.6.36/arch/mips/ar71xx/dev-pb9x-pci.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-pb9x-pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-pb9x-pci.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,22 @@ ++/* ++ * Atheros PB9x reference board PCI initialization ++ * ++ * Copyright (C) 2010 Felix Fietkau ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static int __init ar724x_pci_setup(void) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ /* setup COMMAND register */ -+ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | -+ PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK; ++#ifndef _AR71XX_DEV_PB9X_PCI_H ++#define _AR71XX_DEV_PB9X_PCI_H + -+ ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t); -+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000); -+ ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000); ++#if defined(CONFIG_AR71XX_DEV_PB9X_PCI) ++void pb9x_pci_init(void) __init; ++#else ++static inline void pb9x_pci_init(void) { } ++#endif + -+ t = __raw_readl(base + AR724X_PCI_REG_RESET); -+ if (t != 0x7) { -+ udelay(100000); -+ __raw_writel(0, base + AR724X_PCI_REG_RESET); -+ udelay(100); -+ __raw_writel(4, base + AR724X_PCI_REG_RESET); -+ udelay(100000); -+ } ++#endif /* _AR71XX_DEV_PB9X_PCI_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-usb.c linux-2.6.36/arch/mips/ar71xx/dev-usb.c +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-usb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-usb.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,181 @@ ++/* ++ * Atheros AR71xx USB host device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ if (ar71xx_soc == AR71XX_SOC_AR7240) -+ t = AR724X_PCI_APP_LTSSM_ENABLE; -+ else -+ t = 0x1ffc1; -+ __raw_writel(t, base + AR724X_PCI_REG_APP); -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_APP); -+ udelay(1000); ++#include ++#include ++#include ++#include ++#include + -+ t = __raw_readl(base + AR724X_PCI_REG_RESET); -+ if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) { -+ printk(KERN_WARNING "PCI: no PCIe module found\n"); -+ return -ENODEV; -+ } ++#include ++#include + -+ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { -+ t = __raw_readl(base + AR724X_PCI_REG_APP); -+ t |= BIT(16); -+ __raw_writel(t, base + AR724X_PCI_REG_APP); -+ } ++#include "dev-usb.h" + -+ return 0; -+} ++/* ++ * OHCI (USB full speed host controller) ++ */ ++static struct resource ar71xx_ohci_resources[] = { ++ [0] = { ++ .start = AR71XX_OHCI_BASE, ++ .end = AR71XX_OHCI_BASE + AR71XX_OHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_MISC_IRQ_OHCI, ++ .end = AR71XX_MISC_IRQ_OHCI, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; + -+static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 pending; ++static struct resource ar7240_ohci_resources[] = { ++ [0] = { ++ .start = AR7240_OHCI_BASE, ++ .end = AR7240_OHCI_BASE + AR7240_OHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_CPU_IRQ_USB, ++ .end = AR71XX_CPU_IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; + -+ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & -+ __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++static u64 ar71xx_ohci_dmamask = DMA_BIT_MASK(32); ++static struct platform_device ar71xx_ohci_device = { ++ .name = "ar71xx-ohci", ++ .id = -1, ++ .resource = ar71xx_ohci_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_ohci_resources), ++ .dev = { ++ .dma_mask = &ar71xx_ohci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ }, ++}; + -+ if (pending & AR724X_PCI_INT_DEV0) -+ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); ++/* ++ * EHCI (USB full speed host controller) ++ */ ++static struct resource ar71xx_ehci_resources[] = { ++ [0] = { ++ .start = AR71XX_EHCI_BASE, ++ .end = AR71XX_EHCI_BASE + AR71XX_EHCI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = AR71XX_CPU_IRQ_USB, ++ .end = AR71XX_CPU_IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; + -+ else -+ spurious_interrupt(); -+} ++static u64 ar71xx_ehci_dmamask = DMA_BIT_MASK(32); ++static struct ar71xx_ehci_platform_data ar71xx_ehci_data; + -+static void ar724x_pci_irq_unmask(unsigned int irq) -+{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; ++static struct platform_device ar71xx_ehci_device = { ++ .name = "ar71xx-ehci", ++ .id = -1, ++ .resource = ar71xx_ehci_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_ehci_resources), ++ .dev = { ++ .dma_mask = &ar71xx_ehci_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(32), ++ .platform_data = &ar71xx_ehci_data, ++ }, ++}; + -+ switch (irq) { -+ case AR71XX_PCI_IRQ_DEV0: -+ irq -= AR71XX_PCI_IRQ_BASE; ++#define AR71XX_USB_RESET_MASK \ ++ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_PHY \ ++ | RESET_MODULE_USB_OHCI_DLL) + -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ } -+} ++#define AR7240_USB_RESET_MASK \ ++ (RESET_MODULE_USB_HOST | RESET_MODULE_USB_OHCI_DLL_7240) + -+static void ar724x_pci_irq_mask(unsigned int irq) ++static void __init ar71xx_usb_setup(void) +{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ -+ switch (irq) { -+ case AR71XX_PCI_IRQ_DEV0: -+ irq -= AR71XX_PCI_IRQ_BASE; ++ ar71xx_device_stop(AR71XX_USB_RESET_MASK); ++ mdelay(1000); ++ ar71xx_device_start(AR71XX_USB_RESET_MASK); + -+ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(t & ~AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_MASK); ++ /* Turning on the Buff and Desc swap bits */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_CONFIG, 0xf0000); + -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x20c00); + -+ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ __raw_writel(t | AR724X_PCI_INT_DEV0, -+ base + AR724X_PCI_REG_INT_STATUS); ++ mdelay(900); + -+ /* flush write */ -+ (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS); -+ } ++ platform_device_register(&ar71xx_ohci_device); ++ platform_device_register(&ar71xx_ehci_device); +} + -+static struct irq_chip ar724x_pci_irq_chip = { -+ .name = "AR724X PCI ", -+ .mask = ar724x_pci_irq_mask, -+ .unmask = ar724x_pci_irq_unmask, -+ .mask_ack = ar724x_pci_irq_mask, -+}; -+ -+static void __init ar724x_pci_irq_init(void) ++static void __init ar7240_usb_setup(void) +{ -+ void __iomem *base = ar724x_pci_ctrl_base; -+ u32 t; -+ int i; -+ -+ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); -+ if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY | -+ AR724X_RESET_PCIE_PHY_SERIAL)) { -+ return; -+ } ++ ar71xx_device_stop(AR7240_USB_RESET_MASK); ++ mdelay(1000); ++ ar71xx_device_start(AR7240_USB_RESET_MASK); + -+ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); -+ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); ++ /* WAR for HW bug. Here it adjusts the duration between two SOFS */ ++ ar71xx_usb_ctrl_wr(USB_CTRL_REG_FLADJ, 0x3); + -+ for (i = AR71XX_PCI_IRQ_BASE; -+ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { -+ irq_desc[i].status = IRQ_DISABLED; -+ set_irq_chip_and_handler(i, &ar724x_pci_irq_chip, -+ handle_level_irq); ++ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { ++ ar71xx_ehci_data.is_ar91xx = 1; ++ ar71xx_ehci_device.resource = ar7240_ohci_resources; ++ ar71xx_ehci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); ++ platform_device_register(&ar71xx_ehci_device); ++ } else { ++ ar71xx_ohci_device.resource = ar7240_ohci_resources; ++ ar71xx_ohci_device.num_resources = ARRAY_SIZE(ar7240_ohci_resources); ++ platform_device_register(&ar71xx_ohci_device); + } -+ -+ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler); +} + -+int __init ar724x_pcibios_init(void) ++static void __init ar91xx_usb_setup(void) +{ -+ int ret = -ENOMEM; -+ -+ ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE, -+ AR724X_PCI_CRP_SIZE); -+ if (ar724x_pci_localcfg_base == NULL) -+ goto err; -+ -+ ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE, -+ AR724X_PCI_CFG_SIZE); -+ if (ar724x_pci_devcfg_base == NULL) -+ goto err_unmap_localcfg; -+ -+ ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE, -+ AR724X_PCI_CTRL_SIZE); -+ if (ar724x_pci_ctrl_base == NULL) -+ goto err_unmap_devcfg; -+ -+ ar724x_pci_reset(); -+ ret = ar724x_pci_setup(); -+ if (ret) -+ goto err_unmap_ctrl; ++ ar71xx_device_stop(RESET_MODULE_USBSUS_OVERRIDE); ++ mdelay(10); + -+ ar724x_pci_fixup_enable = 1; -+ ar724x_pci_irq_init(); -+ register_pci_controller(&ar724x_pci_controller); ++ ar71xx_device_start(RESET_MODULE_USB_HOST); ++ mdelay(10); + -+ return 0; ++ ar71xx_device_start(RESET_MODULE_USB_PHY); ++ mdelay(10); + -+ err_unmap_ctrl: -+ iounmap(ar724x_pci_ctrl_base); -+ err_unmap_devcfg: -+ iounmap(ar724x_pci_devcfg_base); -+ err_unmap_localcfg: -+ iounmap(ar724x_pci_localcfg_base); -+ err: -+ return ret; ++ ar71xx_ehci_data.is_ar91xx = 1; ++ platform_device_register(&ar71xx_ehci_device); +} -diff -Nur linux-2.6.35.7.orig/drivers/char/Kconfig linux-2.6.35.7/drivers/char/Kconfig ---- linux-2.6.35.7.orig/drivers/char/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/char/Kconfig 2010-10-14 20:27:59.828101117 +0200 -@@ -1032,6 +1032,14 @@ - - If compiled as a module, it will be called cs5535_gpio. - -+config GPIO_DEVICE -+ tristate "GPIO device support" -+ depends on GENERIC_GPIO -+ help -+ Say Y to enable Linux GPIO device support. This allows control of -+ GPIO pins using a character device -+ -+ - config RAW_DRIVER - tristate "RAW driver (/dev/raw/rawN)" - depends on BLOCK -diff -Nur linux-2.6.35.7.orig/drivers/char/Kconfig.orig linux-2.6.35.7/drivers/char/Kconfig.orig ---- linux-2.6.35.7.orig/drivers/char/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/char/Kconfig.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,1133 @@ -+# -+# Character device configuration -+# -+ -+menu "Character devices" -+ -+config VT -+ bool "Virtual terminal" if EMBEDDED -+ depends on !S390 -+ select INPUT -+ default y -+ ---help--- -+ If you say Y here, you will get support for terminal devices with -+ display and keyboard devices. These are called "virtual" because you -+ can run several virtual terminals (also called virtual consoles) on -+ one physical terminal. This is rather useful, for example one -+ virtual terminal can collect system messages and warnings, another -+ one can be used for a text-mode user session, and a third could run -+ an X session, all in parallel. Switching between virtual terminals -+ is done with certain key combinations, usually Alt-. -+ -+ The setterm command ("man setterm") can be used to change the -+ properties (such as colors or beeping) of a virtual terminal. The -+ man page console_codes(4) ("man console_codes") contains the special -+ character sequences that can be used to change those properties -+ directly. The fonts used on virtual terminals can be changed with -+ the setfont ("man setfont") command and the key bindings are defined -+ with the loadkeys ("man loadkeys") command. -+ -+ You need at least one virtual terminal device in order to make use -+ of your keyboard and monitor. Therefore, only people configuring an -+ embedded system would want to say N here in order to save some -+ memory; the only way to log into such a system is then via a serial -+ or network connection. -+ -+ If unsure, say Y, or else you won't be able to do much with your new -+ shiny Linux system :-) -+ -+config CONSOLE_TRANSLATIONS -+ depends on VT -+ default y -+ bool "Enable character translations in console" if EMBEDDED -+ ---help--- -+ This enables support for font mapping and Unicode translation -+ on virtual consoles. -+ -+config VT_CONSOLE -+ bool "Support for console on virtual terminal" if EMBEDDED -+ depends on VT -+ default y -+ ---help--- -+ The system console is the device which receives all kernel messages -+ and warnings and which allows logins in single user mode. If you -+ answer Y here, a virtual terminal (the device used to interact with -+ a physical terminal) can be used as system console. This is the most -+ common mode of operations, so you should say Y here unless you want -+ the kernel messages be output only to a serial port (in which case -+ you should say Y to "Console on serial port", below). -+ -+ If you do say Y here, by default the currently visible virtual -+ terminal (/dev/tty0) will be used as system console. You can change -+ that with a kernel command line option such as "console=tty3" which -+ would use the third virtual terminal as system console. (Try "man -+ bootparam" or see the documentation of your boot loader (lilo or -+ loadlin) about how to pass options to the kernel at boot time.) -+ -+ If unsure, say Y. -+ -+config HW_CONSOLE -+ bool -+ depends on VT && !S390 && !UML -+ default y -+ -+config VT_HW_CONSOLE_BINDING -+ bool "Support for binding and unbinding console drivers" -+ depends on HW_CONSOLE -+ default n -+ ---help--- -+ The virtual terminal is the device that interacts with the physical -+ terminal through console drivers. On these systems, at least one -+ console driver is loaded. In other configurations, additional console -+ drivers may be enabled, such as the framebuffer console. If more than -+ 1 console driver is enabled, setting this to 'y' will allow you to -+ select the console driver that will serve as the backend for the -+ virtual terminals. -+ -+ See for more -+ information. For framebuffer console users, please refer to -+ . -+ -+config DEVKMEM -+ bool "/dev/kmem virtual device support" -+ default y -+ help -+ Say Y here if you want to support the /dev/kmem device. The -+ /dev/kmem device is rarely used, but can be used for certain -+ kind of kernel debugging operations. -+ When in doubt, say "N". -+ -+config BFIN_JTAG_COMM -+ tristate "Blackfin JTAG Communication" -+ depends on BLACKFIN -+ help -+ Add support for emulating a TTY device over the Blackfin JTAG. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called bfin_jtag_comm. -+ -+config BFIN_JTAG_COMM_CONSOLE -+ bool "Console on Blackfin JTAG" -+ depends on BFIN_JTAG_COMM=y -+ -+config SERIAL_NONSTANDARD -+ bool "Non-standard serial port support" -+ depends on HAS_IOMEM -+ ---help--- -+ Say Y here if you have any non-standard serial boards -- boards -+ which aren't supported using the standard "dumb" serial driver. -+ This includes intelligent serial boards such as Cyclades, -+ Digiboards, etc. These are usually used for systems that need many -+ serial ports because they serve many terminals or dial-in -+ connections. -+ -+ Note that the answer to this question won't directly affect the -+ kernel: saying N will just cause the configurator to skip all -+ the questions about non-standard serial boards. -+ -+ Most people can say N here. -+ -+config COMPUTONE -+ tristate "Computone IntelliPort Plus serial support" -+ depends on SERIAL_NONSTANDARD && (ISA || EISA || PCI) -+ ---help--- -+ This driver supports the entire family of Intelliport II/Plus -+ controllers with the exception of the MicroChannel controllers and -+ products previous to the Intelliport II. These are multiport cards, -+ which give you many serial ports. You would need something like this -+ to connect more than two modems to your Linux box, for instance in -+ order to become a dial-in server. If you have a card like that, say -+ Y here and read . -+ -+ To compile this driver as module, choose M here: the -+ module will be called ip2. -+ -+config ROCKETPORT -+ tristate "Comtrol RocketPort support" -+ depends on SERIAL_NONSTANDARD && (ISA || EISA || PCI) -+ help -+ This driver supports Comtrol RocketPort and RocketModem PCI boards. -+ These boards provide 2, 4, 8, 16, or 32 high-speed serial ports or -+ modems. For information about the RocketPort/RocketModem boards -+ and this driver read . -+ -+ To compile this driver as a module, choose M here: the -+ module will be called rocket. -+ -+ If you want to compile this driver into the kernel, say Y here. If -+ you don't have a Comtrol RocketPort/RocketModem card installed, say N. + -+config CYCLADES -+ tristate "Cyclades async mux support" -+ depends on SERIAL_NONSTANDARD && (PCI || ISA) -+ select FW_LOADER -+ ---help--- -+ This driver supports Cyclades Z and Y multiserial boards. -+ You would need something like this to connect more than two modems to -+ your Linux box, for instance in order to become a dial-in server. ++void __init ar71xx_add_device_usb(void) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar7240_usb_setup(); ++ break; + -+ For information about the Cyclades-Z card, read -+ . ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ar71xx_usb_setup(); ++ break; + -+ To compile this driver as a module, choose M here: the -+ module will be called cyclades. ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ar91xx_usb_setup(); ++ break; + -+ If you haven't heard about it, it's safe to say N. ++ default: ++ BUG(); ++ } ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/dev-usb.h linux-2.6.36/arch/mips/ar71xx/dev-usb.h +--- linux-2.6.36.orig/arch/mips/ar71xx/dev-usb.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/dev-usb.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,17 @@ ++/* ++ * Atheros AR71xx USB host device support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+config CYZ_INTR -+ bool "Cyclades-Z interrupt mode operation (EXPERIMENTAL)" -+ depends on EXPERIMENTAL && CYCLADES -+ help -+ The Cyclades-Z family of multiport cards allows 2 (two) driver op -+ modes: polling and interrupt. In polling mode, the driver will check -+ the status of the Cyclades-Z ports every certain amount of time -+ (which is called polling cycle and is configurable). In interrupt -+ mode, it will use an interrupt line (IRQ) in order to check the -+ status of the Cyclades-Z ports. The default op mode is polling. If -+ unsure, say N. -+ -+config DIGIEPCA -+ tristate "Digiboard Intelligent Async Support" -+ depends on SERIAL_NONSTANDARD && (ISA || EISA || PCI) -+ ---help--- -+ This is a driver for Digi International's Xx, Xeve, and Xem series -+ of cards which provide multiple serial ports. You would need -+ something like this to connect more than two modems to your Linux -+ box, for instance in order to become a dial-in server. This driver -+ supports the original PC (ISA) boards as well as PCI, and EISA. If -+ you have a card like this, say Y here and read the file -+ . ++#ifndef _AR71XX_DEV_USB_H ++#define _AR71XX_DEV_USB_H + -+ To compile this driver as a module, choose M here: the -+ module will be called epca. ++void ar71xx_add_device_usb(void) __init; + -+config MOXA_INTELLIO -+ tristate "Moxa Intellio support" -+ depends on SERIAL_NONSTANDARD && (ISA || EISA || PCI) -+ select FW_LOADER -+ help -+ Say Y here if you have a Moxa Intellio multiport serial card. ++#endif /* _AR71XX_DEV_USB_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/devices.c linux-2.6.36/arch/mips/ar71xx/devices.c +--- linux-2.6.36.orig/arch/mips/ar71xx/devices.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/devices.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,575 @@ ++/* ++ * Atheros AR71xx SoC platform devices ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ To compile this driver as a module, choose M here: the -+ module will be called moxa. ++#include ++#include ++#include ++#include ++#include ++#include + -+config MOXA_SMARTIO -+ tristate "Moxa SmartIO support v. 2.0" -+ depends on SERIAL_NONSTANDARD && (PCI || EISA || ISA) -+ help -+ Say Y here if you have a Moxa SmartIO multiport serial card and/or -+ want to help develop a new version of this driver. ++#include + -+ This is upgraded (1.9.1) driver from original Moxa drivers with -+ changes finally resulting in PCI probing. ++#include "devices.h" + -+ This driver can also be built as a module. The module will be called -+ mxser. If you want to do that, say M here. ++static u8 ar71xx_mac_base[ETH_ALEN] __initdata; + -+config ISI -+ tristate "Multi-Tech multiport card support (EXPERIMENTAL)" -+ depends on SERIAL_NONSTANDARD && PCI -+ select FW_LOADER -+ help -+ This is a driver for the Multi-Tech cards which provide several -+ serial ports. The driver is experimental and can currently only be -+ built as a module. The module will be called isicom. -+ If you want to do that, choose M here. -+ -+config SYNCLINK -+ tristate "Microgate SyncLink card support" -+ depends on SERIAL_NONSTANDARD && PCI && ISA_DMA_API -+ help -+ Provides support for the SyncLink ISA and PCI multiprotocol serial -+ adapters. These adapters support asynchronous and HDLC bit -+ synchronous communication up to 10Mbps (PCI adapter). -+ -+ This driver can only be built as a module ( = code which can be -+ inserted in and removed from the running kernel whenever you want). -+ The module will be called synclink. If you want to do that, say M -+ here. -+ -+config SYNCLINKMP -+ tristate "SyncLink Multiport support" -+ depends on SERIAL_NONSTANDARD && PCI -+ help -+ Enable support for the SyncLink Multiport (2 or 4 ports) -+ serial adapter, running asynchronous and HDLC communications up -+ to 2.048Mbps. Each ports is independently selectable for -+ RS-232, V.35, RS-449, RS-530, and X.21 -+ -+ This driver may be built as a module ( = code which can be -+ inserted in and removed from the running kernel whenever you want). -+ The module will be called synclinkmp. If you want to do that, say M -+ here. -+ -+config SYNCLINK_GT -+ tristate "SyncLink GT/AC support" -+ depends on SERIAL_NONSTANDARD && PCI -+ help -+ Support for SyncLink GT and SyncLink AC families of -+ synchronous and asynchronous serial adapters -+ manufactured by Microgate Systems, Ltd. (www.microgate.com) ++static struct resource ar71xx_uart_resources[] = { ++ { ++ .start = AR71XX_UART_BASE, ++ .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; + -+config N_HDLC -+ tristate "HDLC line discipline support" -+ depends on SERIAL_NONSTANDARD -+ help -+ Allows synchronous HDLC communications with tty device drivers that -+ support synchronous HDLC such as the Microgate SyncLink adapter. -+ -+ This driver can be built as a module ( = code which can be -+ inserted in and removed from the running kernel whenever you want). -+ The module will be called n_hdlc. If you want to do that, say M -+ here. -+ -+config N_GSM -+ tristate "GSM MUX line discipline support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ depends on NET -+ help -+ This line discipline provides support for the GSM MUX protocol and -+ presents the mux as a set of 61 individual tty devices. ++#define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP) ++static struct plat_serial8250_port ar71xx_uart_data[] = { ++ { ++ .mapbase = AR71XX_UART_BASE, ++ .irq = AR71XX_MISC_IRQ_UART, ++ .flags = AR71XX_UART_FLAGS, ++ .iotype = UPIO_MEM32, ++ .regshift = 2, ++ }, { ++ /* terminating entry */ ++ } ++}; + -+config RISCOM8 -+ tristate "SDL RISCom/8 card support" -+ depends on SERIAL_NONSTANDARD -+ help -+ This is a driver for the SDL Communications RISCom/8 multiport card, -+ which gives you many serial ports. You would need something like -+ this to connect more than two modems to your Linux box, for instance -+ in order to become a dial-in server. If you have a card like that, -+ say Y here and read the file . -+ -+ Also it's possible to say M here and compile this driver as kernel -+ loadable module; the module will be called riscom8. -+ -+config SPECIALIX -+ tristate "Specialix IO8+ card support" -+ depends on SERIAL_NONSTANDARD -+ help -+ This is a driver for the Specialix IO8+ multiport card (both the -+ ISA and the PCI version) which gives you many serial ports. You -+ would need something like this to connect more than two modems to -+ your Linux box, for instance in order to become a dial-in server. -+ -+ If you have a card like that, say Y here and read the file -+ . Also it's possible to say -+ M here and compile this driver as kernel loadable module which will be -+ called specialix. -+ -+config SX -+ tristate "Specialix SX (and SI) card support" -+ depends on SERIAL_NONSTANDARD && (PCI || EISA || ISA) && BROKEN -+ help -+ This is a driver for the SX and SI multiport serial cards. -+ Please read the file for details. ++static struct platform_device ar71xx_uart_device = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .resource = ar71xx_uart_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_uart_resources), ++ .dev = { ++ .platform_data = ar71xx_uart_data ++ }, ++}; + -+ This driver can only be built as a module ( = code which can be -+ inserted in and removed from the running kernel whenever you want). -+ The module will be called sx. If you want to do that, say M here. ++void __init ar71xx_add_device_uart(void) ++{ ++ ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq; ++ platform_device_register(&ar71xx_uart_device); ++} + -+config RIO -+ tristate "Specialix RIO system support" -+ depends on SERIAL_NONSTANDARD && BROKEN -+ help -+ This is a driver for the Specialix RIO, a smart serial card which -+ drives an outboard box that can support up to 128 ports. Product -+ information is at . -+ There are both ISA and PCI versions. -+ -+config RIO_OLDPCI -+ bool "Support really old RIO/PCI cards" -+ depends on RIO -+ help -+ Older RIO PCI cards need some initialization-time configuration to -+ determine the IRQ and some control addresses. If you have a RIO and -+ this doesn't seem to work, try setting this to Y. ++static struct resource ar71xx_mdio_resources[] = { ++ { ++ .name = "mdio_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE0_BASE, ++ .end = AR71XX_GE0_BASE + 0x200 - 1, ++ } ++}; + -+config STALDRV -+ bool "Stallion multiport serial support" -+ depends on SERIAL_NONSTANDARD -+ help -+ Stallion cards give you many serial ports. You would need something -+ like this to connect more than two modems to your Linux box, for -+ instance in order to become a dial-in server. If you say Y here, -+ you will be asked for your specific card model in the next -+ questions. Make sure to read -+ in this case. If you have never heard about all this, it's safe to -+ say N. -+ -+config STALLION -+ tristate "Stallion EasyIO or EC8/32 support" -+ depends on STALDRV && (ISA || EISA || PCI) -+ help -+ If you have an EasyIO or EasyConnection 8/32 multiport Stallion -+ card, then this is for you; say Y. Make sure to read -+ . ++static struct ag71xx_mdio_platform_data ar71xx_mdio_data; + -+ To compile this driver as a module, choose M here: the -+ module will be called stallion. ++struct platform_device ar71xx_mdio_device = { ++ .name = "ag71xx-mdio", ++ .id = -1, ++ .resource = ar71xx_mdio_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_mdio_resources), ++ .dev = { ++ .platform_data = &ar71xx_mdio_data, ++ }, ++}; + -+config ISTALLION -+ tristate "Stallion EC8/64, ONboard, Brumby support" -+ depends on STALDRV && (ISA || EISA || PCI) -+ help -+ If you have an EasyConnection 8/64, ONboard, Brumby or Stallion -+ serial multiport card, say Y here. Make sure to read -+ . ++void __init ar71xx_add_device_mdio(u32 phy_mask) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar71xx_mdio_data.is_ar7240 = 1; ++ break; ++ default: ++ break; ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called istallion. ++ ar71xx_mdio_data.phy_mask = phy_mask; + -+config NOZOMI -+ tristate "HSDPA Broadband Wireless Data Card - Globe Trotter" -+ depends on PCI && EXPERIMENTAL -+ help -+ If you have a HSDPA driver Broadband Wireless Data Card - -+ Globe Trotter PCMCIA card, say Y here. -+ -+ To compile this driver as a module, choose M here, the module -+ will be called nozomi. -+ -+config A2232 -+ tristate "Commodore A2232 serial support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL && ZORRO && BROKEN -+ ---help--- -+ This option supports the 2232 7-port serial card shipped with the -+ Amiga 2000 and other Zorro-bus machines, dating from 1989. At -+ a max of 19,200 bps, the ports are served by a 6551 ACIA UART chip -+ each, plus a 8520 CIA, and a master 6502 CPU and buffer as well. The -+ ports were connected with 8 pin DIN connectors on the card bracket, -+ for which 8 pin to DB25 adapters were supplied. The card also had -+ jumpers internally to toggle various pinning configurations. -+ -+ This driver can be built as a module; but then "generic_serial" -+ will also be built as a module. This has to be loaded before -+ "ser_a2232". If you want to do this, answer M here. -+ -+config SGI_SNSC -+ bool "SGI Altix system controller communication support" -+ depends on (IA64_SGI_SN2 || IA64_GENERIC) -+ help -+ If you have an SGI Altix and you want to enable system -+ controller communication from user space (you want this!), -+ say Y. Otherwise, say N. -+ -+config SGI_TIOCX -+ bool "SGI TIO CX driver support" -+ depends on (IA64_SGI_SN2 || IA64_GENERIC) -+ help -+ If you have an SGI Altix and you have fpga devices attached -+ to your TIO, say Y here, otherwise say N. -+ -+config SGI_MBCS -+ tristate "SGI FPGA Core Services driver support" -+ depends on SGI_TIOCX -+ help -+ If you have an SGI Altix with an attached SABrick -+ say Y or M here, otherwise say N. -+ -+source "drivers/serial/Kconfig" -+ -+config UNIX98_PTYS -+ bool "Unix98 PTY support" if EMBEDDED -+ default y -+ ---help--- -+ A pseudo terminal (PTY) is a software device consisting of two -+ halves: a master and a slave. The slave device behaves identical to -+ a physical terminal; the master device is used by a process to -+ read data from and write data to the slave, thereby emulating a -+ terminal. Typical programs for the master side are telnet servers -+ and xterms. -+ -+ Linux has traditionally used the BSD-like names /dev/ptyxx for -+ masters and /dev/ttyxx for slaves of pseudo terminals. This scheme -+ has a number of problems. The GNU C library glibc 2.1 and later, -+ however, supports the Unix98 naming standard: in order to acquire a -+ pseudo terminal, a process opens /dev/ptmx; the number of the pseudo -+ terminal is then made available to the process and the pseudo -+ terminal slave can be accessed as /dev/pts/. What was -+ traditionally /dev/ttyp2 will then be /dev/pts/2, for example. -+ -+ All modern Linux systems use the Unix98 ptys. Say Y unless -+ you're on an embedded system and want to conserve memory. -+ -+config DEVPTS_MULTIPLE_INSTANCES -+ bool "Support multiple instances of devpts" -+ depends on UNIX98_PTYS -+ default n -+ ---help--- -+ Enable support for multiple instances of devpts filesystem. -+ If you want to have isolated PTY namespaces (eg: in containers), -+ say Y here. Otherwise, say N. If enabled, each mount of devpts -+ filesystem with the '-o newinstance' option will create an -+ independent PTY namespace. -+ -+config LEGACY_PTYS -+ bool "Legacy (BSD) PTY support" -+ default y -+ ---help--- -+ A pseudo terminal (PTY) is a software device consisting of two -+ halves: a master and a slave. The slave device behaves identical to -+ a physical terminal; the master device is used by a process to -+ read data from and write data to the slave, thereby emulating a -+ terminal. Typical programs for the master side are telnet servers -+ and xterms. -+ -+ Linux has traditionally used the BSD-like names /dev/ptyxx -+ for masters and /dev/ttyxx for slaves of pseudo -+ terminals. This scheme has a number of problems, including -+ security. This option enables these legacy devices; on most -+ systems, it is safe to say N. -+ -+ -+config LEGACY_PTY_COUNT -+ int "Maximum number of legacy PTY in use" -+ depends on LEGACY_PTYS -+ range 0 256 -+ default "256" -+ ---help--- -+ The maximum number of legacy PTYs that can be used at any one time. -+ The default is 256, and should be more than enough. Embedded -+ systems may want to reduce this to save memory. -+ -+ When not in use, each legacy PTY occupies 12 bytes on 32-bit -+ architectures and 24 bytes on 64-bit architectures. -+ -+config BRIQ_PANEL -+ tristate 'Total Impact briQ front panel driver' -+ depends on PPC_CHRP -+ ---help--- -+ The briQ is a small footprint CHRP computer with a frontpanel VFD, a -+ tristate led and two switches. It is the size of a CDROM drive. -+ -+ If you have such one and want anything showing on the VFD then you -+ must answer Y here. ++ platform_device_register(&ar71xx_mdio_device); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called briq_panel. ++static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift) ++{ ++ void __iomem *base; ++ u32 t; + -+ It's safe to say N here. ++ base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE); + -+config BFIN_OTP -+ tristate "Blackfin On-Chip OTP Memory Support" -+ depends on BLACKFIN && (BF51x || BF52x || BF54x) -+ default y -+ help -+ If you say Y here, you will get support for a character device -+ interface into the One Time Programmable memory pages that are -+ stored on the Blackfin processor. This will not get you access -+ to the secure memory pages however. You will need to write your -+ own secure code and reader for that. ++ t = __raw_readl(base + cfg_reg); ++ t &= ~(3 << shift); ++ t |= (2 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); + -+ To compile this driver as a module, choose M here: the module -+ will be called bfin-otp. ++ __raw_writel(pll_val, base + pll_reg); + -+ If unsure, it is safe to say Y. ++ t |= (3 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); + -+config BFIN_OTP_WRITE_ENABLE -+ bool "Enable writing support of OTP pages" -+ depends on BFIN_OTP -+ default n -+ help -+ If you say Y here, you will enable support for writing of the -+ OTP pages. This is dangerous by nature as you can only program -+ the pages once, so only enable this option when you actually -+ need it so as to not inadvertently clobber data. -+ -+ If unsure, say N. -+ -+config PRINTER -+ tristate "Parallel printer support" -+ depends on PARPORT -+ ---help--- -+ If you intend to attach a printer to the parallel port of your Linux -+ box (as opposed to using a serial printer; if the connector at the -+ printer has 9 or 25 holes ["female"], then it's serial), say Y. -+ Also read the Printing-HOWTO, available from -+ . -+ -+ It is possible to share one parallel port among several devices -+ (e.g. printer and ZIP drive) and it is safe to compile the -+ corresponding drivers into the kernel. -+ -+ To compile this driver as a module, choose M here and read -+ . The module will be called lp. -+ -+ If you have several parallel ports, you can specify which ports to -+ use with the "lp" kernel command line option. (Try "man bootparam" -+ or see the documentation of your boot loader (lilo or loadlin) about -+ how to pass options to the kernel at boot time.) The syntax of the -+ "lp" command line option can be found in . -+ -+ If you have more than 8 printers, you need to increase the LP_NO -+ macro in lp.c and the PARPORT_MAX macro in parport.h. -+ -+config LP_CONSOLE -+ bool "Support for console on line printer" -+ depends on PRINTER -+ ---help--- -+ If you want kernel messages to be printed out as they occur, you -+ can have a console on the printer. This option adds support for -+ doing that; to actually get it to happen you need to pass the -+ option "console=lp0" to the kernel at boot time. -+ -+ If the printer is out of paper (or off, or unplugged, or too -+ busy..) the kernel will stall until the printer is ready again. -+ By defining CONSOLE_LP_STRICT to 0 (at your own risk) you -+ can make the kernel continue when this happens, -+ but it'll lose the kernel messages. -+ -+ If unsure, say N. -+ -+config PPDEV -+ tristate "Support for user-space parallel port device drivers" -+ depends on PARPORT -+ ---help--- -+ Saying Y to this adds support for /dev/parport device nodes. This -+ is needed for programs that want portable access to the parallel -+ port, for instance deviceid (which displays Plug-and-Play device -+ IDs). -+ -+ This is the parallel port equivalent of SCSI generic support (sg). -+ It is safe to say N to this -- it is not needed for normal printing -+ or parallel port CD-ROM/disk support. ++ t &= ~(3 << shift); ++ __raw_writel(t, base + cfg_reg); ++ udelay(100); + -+ To compile this driver as a module, choose M here: the -+ module will be called ppdev. ++ printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n", ++ (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg)); + -+ If unsure, say N. ++ iounmap(base); ++} + -+config HVC_DRIVER -+ bool -+ help -+ Generic "hypervisor virtual console" infrastructure for various -+ hypervisors (pSeries, iSeries, Xen, lguest). -+ It will automatically be selected if one of the back-end console drivers -+ is selected. ++struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; ++struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; + -+config HVC_IRQ -+ bool ++static u32 ar71xx_get_eth_pll(unsigned int mac, int speed) ++{ ++ struct ar71xx_eth_pll_data *pll_data; ++ u32 pll_val; + -+config HVC_CONSOLE -+ bool "pSeries Hypervisor Virtual Console support" -+ depends on PPC_PSERIES -+ select HVC_DRIVER -+ select HVC_IRQ -+ help -+ pSeries machines when partitioned support a hypervisor virtual -+ console. This driver allows each pSeries partition to have a console -+ which is accessed via the HMC. ++ switch (mac) { ++ case 0: ++ pll_data = &ar71xx_eth0_pll_data; ++ break; ++ case 1: ++ pll_data = &ar71xx_eth1_pll_data; ++ break; ++ default: ++ BUG(); ++ } + -+config HVC_ISERIES -+ bool "iSeries Hypervisor Virtual Console support" -+ depends on PPC_ISERIES -+ default y -+ select HVC_DRIVER -+ select HVC_IRQ -+ select VIOPATH -+ help -+ iSeries machines support a hypervisor virtual console. ++ switch (speed) { ++ case SPEED_10: ++ pll_val = pll_data->pll_10; ++ break; ++ case SPEED_100: ++ pll_val = pll_data->pll_100; ++ break; ++ case SPEED_1000: ++ pll_val = pll_data->pll_1000; ++ break; ++ default: ++ BUG(); ++ } + -+config HVC_RTAS -+ bool "IBM RTAS Console support" -+ depends on PPC_RTAS -+ select HVC_DRIVER -+ help -+ IBM Console device driver which makes use of RTAS ++ return pll_val; ++} + -+config HVC_BEAT -+ bool "Toshiba's Beat Hypervisor Console support" -+ depends on PPC_CELLEB -+ select HVC_DRIVER -+ help -+ Toshiba's Cell Reference Set Beat Console device driver ++static void ar71xx_set_pll_ge0(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(0, speed); + -+config HVC_IUCV -+ bool "z/VM IUCV Hypervisor console support (VM only)" -+ depends on S390 -+ select HVC_DRIVER -+ select IUCV -+ default y -+ help -+ This driver provides a Hypervisor console (HVC) back-end to access -+ a Linux (console) terminal via a z/VM IUCV communication path. -+ -+config HVC_XEN -+ bool "Xen Hypervisor Console support" -+ depends on XEN -+ select HVC_DRIVER -+ select HVC_IRQ -+ default y -+ help -+ Xen virtual console device driver -+ -+config HVC_UDBG -+ bool "udbg based fake hypervisor console" -+ depends on PPC && EXPERIMENTAL -+ select HVC_DRIVER -+ default n -+ -+config VIRTIO_CONSOLE -+ tristate "Virtio console" -+ depends on VIRTIO -+ select HVC_DRIVER -+ help -+ Virtio console for use with lguest and other hypervisors. -+ -+ Also serves as a general-purpose serial device for data -+ transfer between the guest and host. Character devices at -+ /dev/vportNpn will be created when corresponding ports are -+ found, where N is the device number and n is the port number -+ within that device. If specified by the host, a sysfs -+ attribute called 'name' will be populated with a name for -+ the port which can be used by udev scripts to create a -+ symlink to the device. -+ -+config HVCS -+ tristate "IBM Hypervisor Virtual Console Server support" -+ depends on PPC_PSERIES && HVC_CONSOLE -+ help -+ Partitionable IBM Power5 ppc64 machines allow hosting of -+ firmware virtual consoles from one Linux partition by -+ another Linux partition. This driver allows console data -+ from Linux partitions to be accessed through TTY device -+ interfaces in the device tree of a Linux partition running -+ this driver. ++ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK, ++ val, AR71XX_ETH0_PLL_SHIFT); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called hvcs. Additionally, this module -+ will depend on arch specific APIs exported from hvcserver.ko -+ which will also be compiled when this driver is built as a -+ module. -+ -+config IBM_BSR -+ tristate "IBM POWER Barrier Synchronization Register support" -+ depends on PPC_PSERIES -+ help -+ This devices exposes a hardware mechanism for fast synchronization -+ of threads across a large system which avoids bouncing a cacheline -+ between several cores on a system ++static void ar71xx_set_pll_ge1(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(1, speed); + -+source "drivers/char/ipmi/Kconfig" ++ ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK, ++ val, AR71XX_ETH1_PLL_SHIFT); ++} + -+config DS1620 -+ tristate "NetWinder thermometer support" -+ depends on ARCH_NETWINDER -+ help -+ Say Y here to include support for the thermal management hardware -+ found in the NetWinder. This driver allows the user to control the -+ temperature set points and to read the current temperature. -+ -+ It is also possible to say M here to build it as a module (ds1620) -+ It is recommended to be used on a NetWinder, but it is not a -+ necessity. -+ -+config NWBUTTON -+ tristate "NetWinder Button" -+ depends on ARCH_NETWINDER -+ ---help--- -+ If you say Y here and create a character device node /dev/nwbutton -+ with major and minor numbers 10 and 158 ("man mknod"), then every -+ time the orange button is pressed a number of times, the number of -+ times the button was pressed will be written to that device. -+ -+ This is most useful for applications, as yet unwritten, which -+ perform actions based on how many times the button is pressed in a -+ row. -+ -+ Do not hold the button down for too long, as the driver does not -+ alter the behaviour of the hardware reset circuitry attached to the -+ button; it will still execute a hard reset if the button is held -+ down for longer than approximately five seconds. ++static void ar724x_set_pll_ge0(int speed) ++{ ++ /* TODO */ ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called nwbutton. ++static void ar724x_set_pll_ge1(int speed) ++{ ++ /* TODO */ ++} + -+ Most people will answer Y to this question and "Reboot Using Button" -+ below to be able to initiate a system shutdown from the button. ++static void ar91xx_set_pll_ge0(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(0, speed); + -+config NWBUTTON_REBOOT -+ bool "Reboot Using Button" -+ depends on NWBUTTON -+ help -+ If you say Y here, then you will be able to initiate a system -+ shutdown and reboot by pressing the orange button a number of times. -+ The number of presses to initiate the shutdown is two by default, -+ but this can be altered by modifying the value of NUM_PRESSES_REBOOT -+ in nwbutton.h and recompiling the driver or, if you compile the -+ driver as a module, you can specify the number of presses at load -+ time with "insmod button reboot_count=". -+ -+config NWFLASH -+ tristate "NetWinder flash support" -+ depends on ARCH_NETWINDER -+ ---help--- -+ If you say Y here and create a character device /dev/flash with -+ major 10 and minor 160 you can manipulate the flash ROM containing -+ the NetWinder firmware. Be careful as accidentally overwriting the -+ flash contents can render your computer unbootable. On no account -+ allow random users access to this device. :-) ++ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK, ++ val, AR91XX_ETH0_PLL_SHIFT); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called nwflash. -+ -+ If you're not sure, say N. -+ -+source "drivers/char/hw_random/Kconfig" -+ -+config NVRAM -+ tristate "/dev/nvram support" -+ depends on ATARI || X86 || (ARM && RTC_DRV_CMOS) || GENERIC_NVRAM -+ ---help--- -+ If you say Y here and create a character special file /dev/nvram -+ with major number 10 and minor number 144 using mknod ("man mknod"), -+ you get read and write access to the extra bytes of non-volatile -+ memory in the real time clock (RTC), which is contained in every PC -+ and most Ataris. The actual number of bytes varies, depending on the -+ nvram in the system, but is usually 114 (128-14 for the RTC). -+ -+ This memory is conventionally called "CMOS RAM" on PCs and "NVRAM" -+ on Ataris. /dev/nvram may be used to view settings there, or to -+ change them (with some utility). It could also be used to frequently -+ save a few bits of very important data that may not be lost over -+ power-off and for which writing to disk is too insecure. Note -+ however that most NVRAM space in a PC belongs to the BIOS and you -+ should NEVER idly tamper with it. See Ralf Brown's interrupt list -+ for a guide to the use of CMOS bytes by your BIOS. -+ -+ On Atari machines, /dev/nvram is always configured and does not need -+ to be selected. ++static void ar91xx_set_pll_ge1(int speed) ++{ ++ u32 val = ar71xx_get_eth_pll(1, speed); + -+ To compile this driver as a module, choose M here: the -+ module will be called nvram. ++ ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK, ++ val, AR91XX_ETH1_PLL_SHIFT); ++} + -+# -+# These legacy RTC drivers just cause too many conflicts with the generic -+# RTC framework ... let's not even try to coexist any more. -+# -+if RTC_LIB=n -+ -+config RTC -+ tristate "Enhanced Real Time Clock Support (legacy PC RTC driver)" -+ depends on !PPC && !PARISC && !IA64 && !M68K && !SPARC && !FRV \ -+ && !ARM && !SUPERH && !S390 && !AVR32 && !BLACKFIN -+ ---help--- -+ If you say Y here and create a character special file /dev/rtc with -+ major number 10 and minor number 135 using mknod ("man mknod"), you -+ will get access to the real time clock (or hardware clock) built -+ into your computer. -+ -+ Every PC has such a clock built in. It can be used to generate -+ signals from as low as 1Hz up to 8192Hz, and can also be used -+ as a 24 hour alarm. It reports status information via the file -+ /proc/driver/rtc and its behaviour is set by various ioctls on -+ /dev/rtc. -+ -+ If you run Linux on a multiprocessor machine and said Y to -+ "Symmetric Multi Processing" above, you should say Y here to read -+ and set the RTC in an SMP compatible fashion. -+ -+ If you think you have a use for such a device (such as periodic data -+ sampling), then say Y here, and read -+ for details. ++static void ar71xx_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called rtc. -+ -+config JS_RTC -+ tristate "Enhanced Real Time Clock Support" -+ depends on SPARC32 && PCI -+ ---help--- -+ If you say Y here and create a character special file /dev/rtc with -+ major number 10 and minor number 135 using mknod ("man mknod"), you -+ will get access to the real time clock (or hardware clock) built -+ into your computer. -+ -+ Every PC has such a clock built in. It can be used to generate -+ signals from as low as 1Hz up to 8192Hz, and can also be used -+ as a 24 hour alarm. It reports status information via the file -+ /proc/driver/rtc and its behaviour is set by various ioctls on -+ /dev/rtc. -+ -+ If you think you have a use for such a device (such as periodic data -+ sampling), then say Y here, and read -+ for details. ++static void ar71xx_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called js-rtc. -+ -+config GEN_RTC -+ tristate "Generic /dev/rtc emulation" -+ depends on RTC!=y && !IA64 && !ARM && !M32R && !MIPS && !SPARC && !FRV && !S390 && !SUPERH && !AVR32 && !BLACKFIN -+ ---help--- -+ If you say Y here and create a character special file /dev/rtc with -+ major number 10 and minor number 135 using mknod ("man mknod"), you -+ will get access to the real time clock (or hardware clock) built -+ into your computer. -+ -+ It reports status information via the file /proc/driver/rtc and its -+ behaviour is set by various ioctls on /dev/rtc. If you enable the -+ "extended RTC operation" below it will also provide an emulation -+ for RTC_UIE which is required by some programs and may improve -+ precision in some cases. ++static void ar724x_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called genrtc. ++static void ar724x_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1); ++} + -+config GEN_RTC_X -+ bool "Extended RTC operation" -+ depends on GEN_RTC -+ help -+ Provides an emulation for RTC_UIE which is required by some programs -+ and may improve precision of the generic RTC support in some cases. ++static void ar91xx_ddr_flush_ge0(void) ++{ ++ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0); ++} + -+config EFI_RTC -+ bool "EFI Real Time Clock Services" -+ depends on IA64 ++static void ar91xx_ddr_flush_ge1(void) ++{ ++ ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1); ++} + -+config DS1302 -+ tristate "DS1302 RTC support" -+ depends on M32R && (PLAT_M32700UT || PLAT_OPSPUT) -+ help -+ If you say Y here and create a character special file /dev/rtc with -+ major number 121 and minor number 0 using mknod ("man mknod"), you -+ will get access to the real time clock (or hardware clock) built -+ into your computer. ++static struct resource ar71xx_eth0_resources[] = { ++ { ++ .name = "mac_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE0_BASE, ++ .end = AR71XX_GE0_BASE + 0x200 - 1, ++ }, { ++ .name = "mii_ctrl", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL, ++ .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3, ++ }, { ++ .name = "mac_irq", ++ .flags = IORESOURCE_IRQ, ++ .start = AR71XX_CPU_IRQ_GE0, ++ .end = AR71XX_CPU_IRQ_GE0, ++ }, ++}; + -+endif # RTC_LIB ++struct ag71xx_platform_data ar71xx_eth0_data = { ++ .reset_bit = RESET_MODULE_GE0_MAC, ++}; + -+config DTLK -+ tristate "Double Talk PC internal speech card support" -+ depends on ISA -+ help -+ This driver is for the DoubleTalk PC, a speech synthesizer -+ manufactured by RC Systems (). It is also -+ called the `internal DoubleTalk'. ++struct platform_device ar71xx_eth0_device = { ++ .name = "ag71xx", ++ .id = 0, ++ .resource = ar71xx_eth0_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_eth0_resources), ++ .dev = { ++ .platform_data = &ar71xx_eth0_data, ++ }, ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called dtlk. ++static struct resource ar71xx_eth1_resources[] = { ++ { ++ .name = "mac_base", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_GE1_BASE, ++ .end = AR71XX_GE1_BASE + 0x200 - 1, ++ }, { ++ .name = "mii_ctrl", ++ .flags = IORESOURCE_MEM, ++ .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL, ++ .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3, ++ }, { ++ .name = "mac_irq", ++ .flags = IORESOURCE_IRQ, ++ .start = AR71XX_CPU_IRQ_GE1, ++ .end = AR71XX_CPU_IRQ_GE1, ++ }, ++}; + -+config XILINX_HWICAP -+ tristate "Xilinx HWICAP Support" -+ depends on XILINX_VIRTEX || MICROBLAZE -+ help -+ This option enables support for Xilinx Internal Configuration -+ Access Port (ICAP) driver. The ICAP is used on Xilinx Virtex -+ FPGA platforms to partially reconfigure the FPGA at runtime. ++struct ag71xx_platform_data ar71xx_eth1_data = { ++ .reset_bit = RESET_MODULE_GE1_MAC, ++}; + -+ If unsure, say N. ++struct platform_device ar71xx_eth1_device = { ++ .name = "ag71xx", ++ .id = 1, ++ .resource = ar71xx_eth1_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_eth1_resources), ++ .dev = { ++ .platform_data = &ar71xx_eth1_data, ++ }, ++}; + -+config R3964 -+ tristate "Siemens R3964 line discipline" -+ ---help--- -+ This driver allows synchronous communication with devices using the -+ Siemens R3964 packet protocol. Unless you are dealing with special -+ hardware like PLCs, you are unlikely to need this. ++#define AR71XX_PLL_VAL_1000 0x00110000 ++#define AR71XX_PLL_VAL_100 0x00001099 ++#define AR71XX_PLL_VAL_10 0x00991099 + -+ To compile this driver as a module, choose M here: the -+ module will be called n_r3964. ++#define AR724X_PLL_VAL_1000 0x00110000 ++#define AR724X_PLL_VAL_100 0x00001099 ++#define AR724X_PLL_VAL_10 0x00991099 + -+ If unsure, say N. ++#define AR91XX_PLL_VAL_1000 0x1a000000 ++#define AR91XX_PLL_VAL_100 0x13000a44 ++#define AR91XX_PLL_VAL_10 0x00441099 + -+config APPLICOM -+ tristate "Applicom intelligent fieldbus card support" -+ depends on PCI -+ ---help--- -+ This driver provides the kernel-side support for the intelligent -+ fieldbus cards made by Applicom International. More information -+ about these cards can be found on the WWW at the address -+ , or by email from David Woodhouse -+ . ++static void __init ar71xx_init_eth_pll_data(unsigned int id) ++{ ++ struct ar71xx_eth_pll_data *pll_data; ++ u32 pll_10, pll_100, pll_1000; + -+ To compile this driver as a module, choose M here: the -+ module will be called applicom. ++ switch (id) { ++ case 0: ++ pll_data = &ar71xx_eth0_pll_data; ++ break; ++ case 1: ++ pll_data = &ar71xx_eth1_pll_data; ++ break; ++ default: ++ BUG(); ++ } + -+ If unsure, say N. ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ pll_10 = AR71XX_PLL_VAL_10; ++ pll_100 = AR71XX_PLL_VAL_100; ++ pll_1000 = AR71XX_PLL_VAL_1000; ++ break; + -+config SONYPI -+ tristate "Sony Vaio Programmable I/O Control Device support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL && X86 && PCI && INPUT && !64BIT -+ ---help--- -+ This driver enables access to the Sony Programmable I/O Control -+ Device which can be found in many (all ?) Sony Vaio laptops. ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ pll_10 = AR724X_PLL_VAL_10; ++ pll_100 = AR724X_PLL_VAL_100; ++ pll_1000 = AR724X_PLL_VAL_1000; ++ break; + -+ If you have one of those laptops, read -+ , and say Y or M here. ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ pll_10 = AR91XX_PLL_VAL_10; ++ pll_100 = AR91XX_PLL_VAL_100; ++ pll_1000 = AR91XX_PLL_VAL_1000; ++ break; ++ default: ++ BUG(); ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called sonypi. ++ if (!pll_data->pll_10) ++ pll_data->pll_10 = pll_10; + -+config GPIO_TB0219 -+ tristate "TANBAC TB0219 GPIO support" -+ depends on TANBAC_TB022X -+ select GPIO_VR41XX ++ if (!pll_data->pll_100) ++ pll_data->pll_100 = pll_100; + -+source "drivers/char/pcmcia/Kconfig" ++ if (!pll_data->pll_1000) ++ pll_data->pll_1000 = pll_1000; ++} + -+config MWAVE -+ tristate "ACP Modem (Mwave) support" -+ depends on X86 -+ select SERIAL_8250 -+ ---help--- -+ The ACP modem (Mwave) for Linux is a WinModem. It is composed of a -+ kernel driver and a user level application. Together these components -+ support direct attachment to public switched telephone networks (PSTNs) -+ and support selected world wide countries. ++static int ar71xx_eth_instance __initdata; ++void __init ar71xx_add_device_eth(unsigned int id) ++{ ++ struct platform_device *pdev; ++ struct ag71xx_platform_data *pdata; + -+ This version of the ACP Modem driver supports the IBM Thinkpad 600E, -+ 600, and 770 that include on board ACP modem hardware. ++ ar71xx_init_eth_pll_data(id); + -+ The modem also supports the standard communications port interface -+ (ttySx) and is compatible with the Hayes AT Command Set. ++ switch (id) { ++ case 0: ++ switch (ar71xx_eth0_data.phy_if_mode) { ++ case PHY_INTERFACE_MODE_MII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII; ++ break; ++ case PHY_INTERFACE_MODE_GMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid PHY interface mode " ++ "for eth0\n"); ++ return; ++ } ++ pdev = &ar71xx_eth0_device; ++ break; ++ case 1: ++ switch (ar71xx_eth1_data.phy_if_mode) { ++ case PHY_INTERFACE_MODE_RMII: ++ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid PHY interface mode " ++ "for eth1\n"); ++ return; ++ } ++ pdev = &ar71xx_eth1_device; ++ break; ++ default: ++ printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id); ++ return; ++ } + -+ The user level application needed to use this driver can be found at -+ the IBM Linux Technology Center (LTC) web site: -+ . ++ pdata = pdev->dev.platform_data; + -+ If you own one of the above IBM Thinkpads which has the Mwave chipset -+ in it, say Y. ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 ++ : ar71xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar71xx_set_pll_ge1 ++ : ar71xx_set_pll_ge0; ++ break; + -+ To compile this driver as a module, choose M here: the -+ module will be called mwave. ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1 ++ : ar71xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar71xx_set_pll_ge1 ++ : ar71xx_set_pll_ge0; ++ pdata->has_gbit = 1; ++ break; + -+config SCx200_GPIO -+ tristate "NatSemi SCx200 GPIO Support" -+ depends on SCx200 -+ select NSC_GPIO -+ help -+ Give userspace access to the GPIO pins on the National -+ Semiconductor SCx200 processors. ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO; ++ ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO; ++ /* fall through */ ++ case AR71XX_SOC_AR7240: ++ pdata->ddr_flush = id ? ar724x_ddr_flush_ge1 ++ : ar724x_ddr_flush_ge0; ++ pdata->set_pll = id ? ar724x_set_pll_ge1 ++ : ar724x_set_pll_ge0; ++ pdata->is_ar724x = 1; ++ break; + -+ If compiled as a module, it will be called scx200_gpio. ++ case AR71XX_SOC_AR9130: ++ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 ++ : ar91xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar91xx_set_pll_ge1 ++ : ar91xx_set_pll_ge0; ++ pdata->is_ar91xx = 1; ++ break; + -+config PC8736x_GPIO -+ tristate "NatSemi PC8736x GPIO Support" -+ depends on X86 -+ default SCx200_GPIO # mostly N -+ select NSC_GPIO # needed for support routines -+ help -+ Give userspace access to the GPIO pins on the National -+ Semiconductor PC-8736x (x=[03456]) SuperIO chip. The chip -+ has multiple functional units, inc several managed by -+ hwmon/pc87360 driver. Tested with PC-87366 -+ -+ If compiled as a module, it will be called pc8736x_gpio. -+ -+config NSC_GPIO -+ tristate "NatSemi Base GPIO Support" -+ depends on X86_32 -+ # selected by SCx200_GPIO and PC8736x_GPIO -+ # what about 2 selectors differing: m != y -+ help -+ Common support used (and needed) by scx200_gpio and -+ pc8736x_gpio drivers. If those drivers are built as -+ modules, this one will be too, named nsc_gpio ++ case AR71XX_SOC_AR9132: ++ pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1 ++ : ar91xx_ddr_flush_ge0; ++ pdata->set_pll = id ? ar91xx_set_pll_ge1 ++ : ar91xx_set_pll_ge0; ++ pdata->is_ar91xx = 1; ++ pdata->has_gbit = 1; ++ break; + -+config CS5535_GPIO -+ tristate "AMD CS5535/CS5536 GPIO (Geode Companion Device)" -+ depends on X86_32 -+ help -+ Give userspace access to the GPIO pins on the AMD CS5535 and -+ CS5536 Geode companion devices. ++ default: ++ BUG(); ++ } + -+ If compiled as a module, it will be called cs5535_gpio. ++ switch (pdata->phy_if_mode) { ++ case PHY_INTERFACE_MODE_GMII: ++ case PHY_INTERFACE_MODE_RGMII: ++ if (!pdata->has_gbit) { ++ printk(KERN_ERR "ar71xx: no gbit available on eth%d\n", ++ id); ++ return; ++ } ++ /* fallthrough */ ++ default: ++ break; ++ } + -+config RAW_DRIVER -+ tristate "RAW driver (/dev/raw/rawN)" -+ depends on BLOCK -+ help -+ The raw driver permits block devices to be bound to /dev/raw/rawN. -+ Once bound, I/O against /dev/raw/rawN uses efficient zero-copy I/O. -+ See the raw(8) manpage for more details. ++ if (is_valid_ether_addr(ar71xx_mac_base)) { ++ memcpy(pdata->mac_addr, ar71xx_mac_base, ETH_ALEN); ++ pdata->mac_addr[5] += ar71xx_eth_instance; ++ } else { ++ random_ether_addr(pdata->mac_addr); ++ printk(KERN_DEBUG ++ "ar71xx: using random MAC address for eth%d\n", ++ ar71xx_eth_instance); ++ } + -+ Applications should preferably open the device (eg /dev/hda1) -+ with the O_DIRECT flag. ++ if (pdata->mii_bus_dev == NULL) ++ pdata->mii_bus_dev = &ar71xx_mdio_device.dev; + -+config MAX_RAW_DEVS -+ int "Maximum number of RAW devices to support (1-8192)" -+ depends on RAW_DRIVER -+ default "256" -+ help -+ The maximum number of RAW devices that are supported. -+ Default is 256. Increase this number in case you need lots of -+ raw devices. ++ /* Reset the device */ ++ ar71xx_device_stop(pdata->reset_bit); ++ mdelay(100); + -+config HPET -+ bool "HPET - High Precision Event Timer" if (X86 || IA64) -+ default n -+ depends on ACPI -+ help -+ If you say Y here, you will have a miscdevice named "/dev/hpet/". Each -+ open selects one of the timers supported by the HPET. The timers are -+ non-periodic and/or periodic. ++ ar71xx_device_start(pdata->reset_bit); ++ mdelay(100); + -+config HPET_MMAP -+ bool "Allow mmap of HPET" -+ default y -+ depends on HPET -+ help -+ If you say Y here, user applications will be able to mmap -+ the HPET registers. ++ platform_device_register(pdev); ++ ar71xx_eth_instance++; ++} + -+ In some hardware implementations, the page containing HPET -+ registers may also contain other things that shouldn't be -+ exposed to the user. If this applies to your hardware, -+ say N here. ++static struct resource ar71xx_spi_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; + -+config HANGCHECK_TIMER -+ tristate "Hangcheck timer" -+ depends on X86 || IA64 || PPC64 || S390 -+ help -+ The hangcheck-timer module detects when the system has gone -+ out to lunch past a certain margin. It can reboot the system -+ or merely print a warning. ++static struct platform_device ar71xx_spi_device = { ++ .name = "ar71xx-spi", ++ .id = -1, ++ .resource = ar71xx_spi_resources, ++ .num_resources = ARRAY_SIZE(ar71xx_spi_resources), ++}; + -+config MMTIMER -+ tristate "MMTIMER Memory mapped RTC for SGI Altix" -+ depends on IA64_GENERIC || IA64_SGI_SN2 -+ default y -+ help -+ The mmtimer device allows direct userspace access to the -+ Altix system timer. ++void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, ++ struct spi_board_info const *info, ++ unsigned n) ++{ ++ spi_register_board_info(info, n); ++ ar71xx_spi_device.dev.platform_data = pdata; ++ platform_device_register(&ar71xx_spi_device); ++} + -+config UV_MMTIMER -+ tristate "UV_MMTIMER Memory mapped RTC for SGI UV" -+ depends on X86_UV -+ default m -+ help -+ The uv_mmtimer device allows direct userspace access to the -+ UV system timer. ++void __init ar71xx_add_device_wdt(void) ++{ ++ platform_device_register_simple("ar71xx-wdt", -1, NULL, 0); ++} + -+source "drivers/char/tpm/Kconfig" ++void __init ar71xx_set_mac_base(unsigned char *mac) ++{ ++ memcpy(ar71xx_mac_base, mac, ETH_ALEN); ++} + -+config TELCLOCK -+ tristate "Telecom clock driver for ATCA SBC" -+ depends on EXPERIMENTAL && X86 -+ default n -+ help -+ The telecom clock device is specific to the MPCBL0010 and MPCBL0050 -+ ATCA computers and allows direct userspace access to the -+ configuration of the telecom clock configuration settings. This -+ device is used for hardware synchronization across the ATCA backplane -+ fabric. Upon loading, the driver exports a sysfs directory, -+ /sys/devices/platform/telco_clock, with a number of files for -+ controlling the behavior of this hardware. -+ -+config DEVPORT -+ bool -+ depends on !M68K -+ depends on ISA || PCI -+ default y ++void __init ar71xx_parse_mac_addr(char *mac_str) ++{ ++ u8 tmp[ETH_ALEN]; ++ int t; + -+source "drivers/s390/char/Kconfig" ++ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); + -+config RAMOOPS -+ tristate "Log panic/oops to a RAM buffer" -+ depends on HAS_IOMEM -+ default n -+ help -+ This enables panic and oops messages to be logged to a circular -+ buffer in RAM where it can be read back at some later point. ++ if (t != ETH_ALEN) ++ t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx", ++ &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]); + -+endmenu ++ if (t == ETH_ALEN) ++ ar71xx_set_mac_base(tmp); ++ else ++ printk(KERN_DEBUG "ar71xx: failed to parse mac address " ++ "\"%s\"\n", mac_str); ++} + -diff -Nur linux-2.6.35.7.orig/drivers/char/Makefile linux-2.6.35.7/drivers/char/Makefile ---- linux-2.6.35.7.orig/drivers/char/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/char/Makefile 2010-10-14 20:27:59.875601109 +0200 -@@ -96,6 +96,7 @@ - obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o - obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o - obj-$(CONFIG_CS5535_GPIO) += cs5535_gpio.o -+obj-$(CONFIG_GPIO_DEVICE) += gpio_dev.o - obj-$(CONFIG_GPIO_TB0219) += tb0219.o - obj-$(CONFIG_TELCLOCK) += tlclk.o - -diff -Nur linux-2.6.35.7.orig/drivers/char/Makefile.orig linux-2.6.35.7/drivers/char/Makefile.orig ---- linux-2.6.35.7.orig/drivers/char/Makefile.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/char/Makefile.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,139 @@ -+# -+# Makefile for the kernel character device drivers. -+# ++static int __init ar71xx_ethaddr_setup(char *str) ++{ ++ ar71xx_parse_mac_addr(str); ++ return 1; ++} ++__setup("ethaddr=", ar71xx_ethaddr_setup); + -+# -+# This file contains the font map for the default (hardware) font -+# -+FONTMAPFILE = cp437.uni -+ -+obj-y += mem.o random.o tty_io.o n_tty.o tty_ioctl.o tty_ldisc.o tty_buffer.o tty_port.o -+ -+obj-$(CONFIG_LEGACY_PTYS) += pty.o -+obj-$(CONFIG_UNIX98_PTYS) += pty.o -+obj-y += misc.o -+obj-$(CONFIG_VT) += vt_ioctl.o vc_screen.o selection.o keyboard.o -+obj-$(CONFIG_BFIN_JTAG_COMM) += bfin_jtag_comm.o -+obj-$(CONFIG_CONSOLE_TRANSLATIONS) += consolemap.o consolemap_deftbl.o -+obj-$(CONFIG_HW_CONSOLE) += vt.o defkeymap.o -+obj-$(CONFIG_AUDIT) += tty_audit.o -+obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o -+obj-$(CONFIG_MVME147_SCC) += generic_serial.o vme_scc.o -+obj-$(CONFIG_MVME162_SCC) += generic_serial.o vme_scc.o -+obj-$(CONFIG_BVME6000_SCC) += generic_serial.o vme_scc.o -+obj-$(CONFIG_ROCKETPORT) += rocket.o -+obj-$(CONFIG_SERIAL167) += serial167.o -+obj-$(CONFIG_CYCLADES) += cyclades.o -+obj-$(CONFIG_STALLION) += stallion.o -+obj-$(CONFIG_ISTALLION) += istallion.o -+obj-$(CONFIG_NOZOMI) += nozomi.o -+obj-$(CONFIG_DIGIEPCA) += epca.o -+obj-$(CONFIG_SPECIALIX) += specialix.o -+obj-$(CONFIG_MOXA_INTELLIO) += moxa.o -+obj-$(CONFIG_A2232) += ser_a2232.o generic_serial.o -+obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o -+obj-$(CONFIG_MOXA_SMARTIO) += mxser.o -+obj-$(CONFIG_COMPUTONE) += ip2/ -+obj-$(CONFIG_RISCOM8) += riscom8.o -+obj-$(CONFIG_ISI) += isicom.o -+obj-$(CONFIG_SYNCLINK) += synclink.o -+obj-$(CONFIG_SYNCLINKMP) += synclinkmp.o -+obj-$(CONFIG_SYNCLINK_GT) += synclink_gt.o -+obj-$(CONFIG_N_HDLC) += n_hdlc.o -+obj-$(CONFIG_N_GSM) += n_gsm.o -+obj-$(CONFIG_AMIGA_BUILTIN_SERIAL) += amiserial.o -+obj-$(CONFIG_SX) += sx.o generic_serial.o -+obj-$(CONFIG_RIO) += rio/ generic_serial.o -+obj-$(CONFIG_HVC_CONSOLE) += hvc_vio.o hvsi.o -+obj-$(CONFIG_HVC_ISERIES) += hvc_iseries.o -+obj-$(CONFIG_HVC_RTAS) += hvc_rtas.o -+obj-$(CONFIG_HVC_BEAT) += hvc_beat.o -+obj-$(CONFIG_HVC_DRIVER) += hvc_console.o -+obj-$(CONFIG_HVC_IRQ) += hvc_irq.o -+obj-$(CONFIG_HVC_XEN) += hvc_xen.o -+obj-$(CONFIG_HVC_IUCV) += hvc_iucv.o -+obj-$(CONFIG_HVC_UDBG) += hvc_udbg.o -+obj-$(CONFIG_VIRTIO_CONSOLE) += virtio_console.o -+obj-$(CONFIG_RAW_DRIVER) += raw.o -+obj-$(CONFIG_SGI_SNSC) += snsc.o snsc_event.o -+obj-$(CONFIG_MSPEC) += mspec.o -+obj-$(CONFIG_MMTIMER) += mmtimer.o -+obj-$(CONFIG_UV_MMTIMER) += uv_mmtimer.o -+obj-$(CONFIG_VIOTAPE) += viotape.o -+obj-$(CONFIG_HVCS) += hvcs.o -+obj-$(CONFIG_IBM_BSR) += bsr.o -+obj-$(CONFIG_SGI_MBCS) += mbcs.o -+obj-$(CONFIG_BRIQ_PANEL) += briq_panel.o -+obj-$(CONFIG_BFIN_OTP) += bfin-otp.o -+ -+obj-$(CONFIG_PRINTER) += lp.o -+ -+obj-$(CONFIG_APM_EMULATION) += apm-emulation.o -+ -+obj-$(CONFIG_DTLK) += dtlk.o -+obj-$(CONFIG_R3964) += n_r3964.o -+obj-$(CONFIG_APPLICOM) += applicom.o -+obj-$(CONFIG_SONYPI) += sonypi.o -+obj-$(CONFIG_RTC) += rtc.o -+obj-$(CONFIG_HPET) += hpet.o -+obj-$(CONFIG_GEN_RTC) += genrtc.o -+obj-$(CONFIG_EFI_RTC) += efirtc.o -+obj-$(CONFIG_DS1302) += ds1302.o -+obj-$(CONFIG_XILINX_HWICAP) += xilinx_hwicap/ -+ifeq ($(CONFIG_GENERIC_NVRAM),y) -+ obj-$(CONFIG_NVRAM) += generic_nvram.o -+else -+ obj-$(CONFIG_NVRAM) += nvram.o -+endif -+obj-$(CONFIG_TOSHIBA) += toshiba.o -+obj-$(CONFIG_I8K) += i8k.o -+obj-$(CONFIG_DS1620) += ds1620.o -+obj-$(CONFIG_HW_RANDOM) += hw_random/ -+obj-$(CONFIG_PPDEV) += ppdev.o -+obj-$(CONFIG_NWBUTTON) += nwbutton.o -+obj-$(CONFIG_NWFLASH) += nwflash.o -+obj-$(CONFIG_SCx200_GPIO) += scx200_gpio.o -+obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o -+obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o -+obj-$(CONFIG_CS5535_GPIO) += cs5535_gpio.o -+obj-$(CONFIG_GPIO_TB0219) += tb0219.o -+obj-$(CONFIG_TELCLOCK) += tlclk.o ++static int __init ar71xx_kmac_setup(char *str) ++{ ++ ar71xx_parse_mac_addr(str); ++ return 1; ++} ++__setup("kmac=", ar71xx_kmac_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/devices.h linux-2.6.36/arch/mips/ar71xx/devices.h +--- linux-2.6.36.orig/arch/mips/ar71xx/devices.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/devices.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,48 @@ ++/* ++ * Atheros AR71xx SoC device definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+obj-$(CONFIG_MWAVE) += mwave/ -+obj-$(CONFIG_AGP) += agp/ -+obj-$(CONFIG_PCMCIA) += pcmcia/ -+obj-$(CONFIG_IPMI_HANDLER) += ipmi/ ++#ifndef __AR71XX_DEVICES_H ++#define __AR71XX_DEVICES_H + -+obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o -+obj-$(CONFIG_TCG_TPM) += tpm/ ++#include + -+obj-$(CONFIG_PS3_FLASH) += ps3flash.o -+obj-$(CONFIG_RAMOOPS) += ramoops.o ++struct platform_device; + -+obj-$(CONFIG_JS_RTC) += js-rtc.o -+js-rtc-y = rtc.o ++void ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata, ++ struct spi_board_info const *info, ++ unsigned n) __init; + -+# Files generated that shall be removed upon make clean -+clean-files := consolemap_deftbl.c defkeymap.c ++void ar71xx_set_mac_base(unsigned char *mac) __init; ++void ar71xx_parse_mac_addr(char *mac_str) __init; + -+quiet_cmd_conmk = CONMK $@ -+ cmd_conmk = scripts/conmakehash $< > $@ ++struct ar71xx_eth_pll_data { ++ u32 pll_10; ++ u32 pll_100; ++ u32 pll_1000; ++}; + -+$(obj)/consolemap_deftbl.c: $(src)/$(FONTMAPFILE) -+ $(call cmd,conmk) ++extern struct ar71xx_eth_pll_data ar71xx_eth0_pll_data; ++extern struct ar71xx_eth_pll_data ar71xx_eth1_pll_data; + -+$(obj)/defkeymap.o: $(obj)/defkeymap.c ++extern struct ag71xx_platform_data ar71xx_eth0_data; ++extern struct ag71xx_platform_data ar71xx_eth1_data; ++extern struct platform_device ar71xx_eth0_device; ++extern struct platform_device ar71xx_eth1_device; ++void ar71xx_add_device_eth(unsigned int id) __init; + -+# Uncomment if you're changing the keymap and have an appropriate -+# loadkeys version for the map. By default, we'll use the shipped -+# versions. -+# GENERATE_KEYMAP := 1 ++extern struct platform_device ar71xx_mdio_device; ++void ar71xx_add_device_mdio(u32 phy_mask) __init; + -+ifdef GENERATE_KEYMAP ++void ar71xx_add_device_uart(void) __init; + -+$(obj)/defkeymap.c: $(obj)/%.c: $(src)/%.map -+ loadkeys --mktable $< > $@.tmp -+ sed -e 's/^static *//' $@.tmp > $@ -+ rm $@.tmp ++void ar71xx_add_device_wdt(void) __init; + -+endif -diff -Nur linux-2.6.35.7.orig/drivers/gpio/nxp_74hc153.c linux-2.6.35.7/drivers/gpio/nxp_74hc153.c ---- linux-2.6.35.7.orig/drivers/gpio/nxp_74hc153.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/gpio/nxp_74hc153.c 2010-10-14 20:27:59.918101359 +0200 -@@ -0,0 +1,246 @@ ++#endif /* __AR71XX_DEVICES_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/early_printk.c linux-2.6.36/arch/mips/ar71xx/early_printk.c +--- linux-2.6.36.orig/arch/mips/ar71xx/early_printk.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/early_printk.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,30 @@ +/* -+ * NXP 74HC153 - Dual 4-input multiplexer GPIO driver ++ * Atheros AR71xx SoC early printk support + * -+ * Copyright (C) 2010 Gabor Juhos ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ + -+#include -+#include -+#include -+#include -+#include -+ -+#define NXP_74HC153_NUM_GPIOS 8 -+#define NXP_74HC153_S0_MASK 0x1 -+#define NXP_74HC153_S1_MASK 0x2 -+#define NXP_74HC153_BANK_MASK 0x4 ++#include ++#include ++#include + -+struct nxp_74hc153_chip { -+ struct device *parent; -+ struct gpio_chip gpio_chip; -+ struct mutex lock; -+}; ++#include + -+static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) -+{ -+ return container_of(gc, struct nxp_74hc153_chip, gpio_chip); -+} ++#define UART_READ(r) \ ++ __raw_readl((void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4 * (r))) + -+static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) -+{ -+ return 0; -+} ++#define UART_WRITE(r, v) \ ++ __raw_writel((v), (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE) + 4*(r))) + -+static int nxp_74hc153_direction_output(struct gpio_chip *gc, -+ unsigned offset, int val) ++void prom_putchar(unsigned char ch) +{ -+ return -EINVAL; ++ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); ++ UART_WRITE(UART_TX, ch); ++ while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); +} + -+static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) -+{ -+ struct nxp_74hc153_chip *nxp; -+ struct nxp_74hc153_platform_data *pdata; -+ unsigned s0; -+ unsigned s1; -+ unsigned pin; -+ int ret; -+ -+ nxp = gpio_to_nxp(gc); -+ pdata = nxp->parent->platform_data; +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/gpio.c linux-2.6.36/arch/mips/ar71xx/gpio.c +--- linux-2.6.36.orig/arch/mips/ar71xx/gpio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/gpio.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,182 @@ ++/* ++ * Atheros AR71xx SoC GPIO API support ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ s0 = !!(offset & NXP_74HC153_S0_MASK); -+ s1 = !!(offset & NXP_74HC153_S1_MASK); -+ pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y -+ : pdata->gpio_pin_1y; ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+ mutex_lock(&nxp->lock); -+ gpio_set_value(pdata->gpio_pin_s0, s0); -+ gpio_set_value(pdata->gpio_pin_s1, s1); -+ ret = gpio_get_value(pin); -+ mutex_unlock(&nxp->lock); ++#include + -+ return ret; -+} ++static DEFINE_SPINLOCK(ar71xx_gpio_lock); + -+static void nxp_74hc153_set_value(struct gpio_chip *gc, -+ unsigned offset, int val) -+{ -+ /* not supported */ -+} ++unsigned long ar71xx_gpio_count; ++EXPORT_SYMBOL(ar71xx_gpio_count); + -+static int __devinit nxp_74hc153_probe(struct platform_device *pdev) ++void __ar71xx_gpio_set_value(unsigned gpio, int value) +{ -+ struct nxp_74hc153_platform_data *pdata; -+ struct nxp_74hc153_chip *nxp; -+ struct gpio_chip *gc; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (pdata == NULL) { -+ dev_dbg(&pdev->dev, "no platform data specified\n"); -+ return -EINVAL; -+ } -+ -+ nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); -+ if (nxp == NULL) { -+ dev_err(&pdev->dev, "no memory for private data\n"); -+ return -ENOMEM; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_s0, err); -+ goto err_free_nxp; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_s1, err); -+ goto err_free_s0; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_1y, err); -+ goto err_free_s1; -+ } -+ -+ err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); -+ if (err) { -+ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", -+ pdata->gpio_pin_2y, err); -+ goto err_free_1y; -+ } -+ -+ err = gpio_direction_output(pdata->gpio_pin_s0, 0); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_s0, err); -+ goto err_free_2y; -+ } ++ void __iomem *base = ar71xx_gpio_base; + -+ err = gpio_direction_output(pdata->gpio_pin_s1, 0); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_s1, err); -+ goto err_free_2y; -+ } ++ if (value) ++ __raw_writel(1 << gpio, base + GPIO_REG_SET); ++ else ++ __raw_writel(1 << gpio, base + GPIO_REG_CLEAR); ++} ++EXPORT_SYMBOL(__ar71xx_gpio_set_value); + -+ err = gpio_direction_input(pdata->gpio_pin_1y); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_1y, err); -+ goto err_free_2y; -+ } ++int __ar71xx_gpio_get_value(unsigned gpio) ++{ ++ return (__raw_readl(ar71xx_gpio_base + GPIO_REG_IN) >> gpio) & 1; ++} ++EXPORT_SYMBOL(__ar71xx_gpio_get_value); + -+ err = gpio_direction_input(pdata->gpio_pin_2y); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to set direction of gpio %u, err=%d\n", -+ pdata->gpio_pin_2y, err); -+ goto err_free_2y; -+ } ++static int ar71xx_gpio_get_value(struct gpio_chip *chip, unsigned offset) ++{ ++ return __ar71xx_gpio_get_value(offset); ++} + -+ nxp->parent = &pdev->dev; -+ mutex_init(&nxp->lock); ++static void ar71xx_gpio_set_value(struct gpio_chip *chip, ++ unsigned offset, int value) ++{ ++ __ar71xx_gpio_set_value(offset, value); ++} + -+ gc = &nxp->gpio_chip; ++static int ar71xx_gpio_direction_input(struct gpio_chip *chip, ++ unsigned offset) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; + -+ gc->direction_input = nxp_74hc153_direction_input; -+ gc->direction_output = nxp_74hc153_direction_output; -+ gc->get = nxp_74hc153_get_value; -+ gc->set = nxp_74hc153_set_value; -+ gc->can_sleep = 1; ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); + -+ gc->base = pdata->gpio_base; -+ gc->ngpio = NXP_74HC153_NUM_GPIOS; -+ gc->label = dev_name(nxp->parent); -+ gc->dev = nxp->parent; -+ gc->owner = THIS_MODULE; ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(1 << offset), ++ base + GPIO_REG_OE); + -+ err = gpiochip_add(&nxp->gpio_chip); -+ if (err) { -+ dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); -+ goto err_free_2y; -+ } ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); + -+ platform_set_drvdata(pdev, nxp); + return 0; -+ -+ err_free_2y: -+ gpio_free(pdata->gpio_pin_2y); -+ err_free_1y: -+ gpio_free(pdata->gpio_pin_1y); -+ err_free_s1: -+ gpio_free(pdata->gpio_pin_s1); -+ err_free_s0: -+ gpio_free(pdata->gpio_pin_s0); -+ err_free_nxp: -+ kfree(nxp); -+ return err; +} + -+static int nxp_74hc153_remove(struct platform_device *pdev) ++static int ar71xx_gpio_direction_output(struct gpio_chip *chip, ++ unsigned offset, int value) +{ -+ struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); -+ struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; + -+ if (nxp) { -+ int err; ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); + -+ err = gpiochip_remove(&nxp->gpio_chip); -+ if (err) { -+ dev_err(&pdev->dev, -+ "unable to remove gpio chip, err=%d\n", -+ err); -+ return err; -+ } ++ if (value) ++ __raw_writel(1 << offset, base + GPIO_REG_SET); ++ else ++ __raw_writel(1 << offset, base + GPIO_REG_CLEAR); + -+ gpio_free(pdata->gpio_pin_2y); -+ gpio_free(pdata->gpio_pin_1y); -+ gpio_free(pdata->gpio_pin_s1); -+ gpio_free(pdata->gpio_pin_s0); ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | (1 << offset), ++ base + GPIO_REG_OE); + -+ kfree(nxp); -+ platform_set_drvdata(pdev, NULL); -+ } ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); + + return 0; +} + -+static struct platform_driver nxp_74hc153_driver = { -+ .probe = nxp_74hc153_probe, -+ .remove = __devexit_p(nxp_74hc153_remove), -+ .driver = { -+ .name = NXP_74HC153_DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, ++static struct gpio_chip ar71xx_gpio_chip = { ++ .label = "ar71xx", ++ .get = ar71xx_gpio_get_value, ++ .set = ar71xx_gpio_set_value, ++ .direction_input = ar71xx_gpio_direction_input, ++ .direction_output = ar71xx_gpio_direction_output, ++ .base = 0, ++ .ngpio = AR71XX_GPIO_COUNT, +}; + -+static int __init nxp_74hc153_init(void) ++void ar71xx_gpio_function_enable(u32 mask) +{ -+ return platform_driver_register(&nxp_74hc153_driver); ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) | mask, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); +} -+subsys_initcall(nxp_74hc153_init); + -+static void __exit nxp_74hc153_exit(void) ++void ar71xx_gpio_function_disable(u32 mask) +{ -+ platform_driver_unregister(&nxp_74hc153_driver); ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel(__raw_readl(base + GPIO_REG_FUNC) & ~mask, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); +} -+module_exit(nxp_74hc153_exit); + -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); -diff -Nur linux-2.6.35.7.orig/drivers/input/misc/gpio_buttons.c linux-2.6.35.7/drivers/input/misc/gpio_buttons.c ---- linux-2.6.35.7.orig/drivers/input/misc/gpio_buttons.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/input/misc/gpio_buttons.c 2010-10-14 20:27:59.954442279 +0200 -@@ -0,0 +1,216 @@ ++void ar71xx_gpio_function_setup(u32 set, u32 clear) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&ar71xx_gpio_lock, flags); ++ ++ __raw_writel((__raw_readl(base + GPIO_REG_FUNC) & ~clear) | set, ++ base + GPIO_REG_FUNC); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_FUNC); ++ ++ spin_unlock_irqrestore(&ar71xx_gpio_lock, flags); ++} ++EXPORT_SYMBOL(ar71xx_gpio_function_setup); ++ ++void __init ar71xx_gpio_init(void) ++{ ++ int err; ++ ++ if (!request_mem_region(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE, ++ "AR71xx GPIO controller")) ++ panic("cannot allocate AR71xx GPIO registers page"); ++ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ar71xx_gpio_chip.ngpio = AR71XX_GPIO_COUNT; ++ break; ++ ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar71xx_gpio_chip.ngpio = AR724X_GPIO_COUNT; ++ break; ++ ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ar71xx_gpio_chip.ngpio = AR91XX_GPIO_COUNT; ++ break; ++ ++ default: ++ BUG(); ++ } ++ ++ err = gpiochip_add(&ar71xx_gpio_chip); ++ if (err) ++ panic("cannot add AR71xx GPIO chip, error=%d", err); ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/irq.c linux-2.6.36/arch/mips/ar71xx/irq.c +--- linux-2.6.36.orig/arch/mips/ar71xx/irq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/irq.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,295 @@ +/* -+ * Driver for buttons on GPIO lines not capable of generating interrupts -+ * -+ * Copyright (C) 2007-2010 Gabor Juhos -+ * Copyright (C) 2010 Nuno Goncalves -+ * -+ * This file was based on: /drivers/input/misc/cobalt_btns.c -+ * Copyright (C) 2007 Yoichi Yuasa ++ * Atheros AR71xx SoC specific interrupt handling + * -+ * also was based on: /drivers/input/keyboard/gpio_keys.c -+ * Copyright 2005 Phil Blundell ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. ++ * Parts of this file are based on Atheros' 2.6.15 BSP + * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ + +#include -+#include +#include -+#include ++#include ++#include + -+#include -+#include -+#include -+#include ++#include ++#include + -+#include ++#include + -+#include ++static int ip2_flush_reg; ++ ++static void ar71xx_gpio_irq_dispatch(void) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ u32 pending; ++ ++ pending = __raw_readl(base + GPIO_REG_INT_PENDING) & ++ __raw_readl(base + GPIO_REG_INT_ENABLE); ++ ++ if (pending) ++ do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1); ++ else ++ spurious_interrupt(); ++} ++ ++static void ar71xx_gpio_irq_unmask(unsigned int irq) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ u32 t; + -+#define DRV_NAME "gpio-buttons" -+#define DRV_VERSION "0.1.2" -+#define PFX DRV_NAME ": " ++ irq -= AR71XX_GPIO_IRQ_BASE; + -+struct gpio_button_data { -+ int last_state; -+ int count; -+}; ++ t = __raw_readl(base + GPIO_REG_INT_ENABLE); ++ __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE); + -+struct gpio_buttons_dev { -+ struct input_polled_dev *poll_dev; -+ struct gpio_buttons_platform_data *pdata; -+ struct gpio_button_data *data; -+}; ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); ++} + -+static void gpio_buttons_poll(struct input_polled_dev *dev) ++static void ar71xx_gpio_irq_mask(unsigned int irq) +{ -+ struct gpio_buttons_dev *bdev = dev->private; -+ struct gpio_buttons_platform_data *pdata = bdev->pdata; -+ struct input_dev *input = dev->input; -+ int i; ++ void __iomem *base = ar71xx_gpio_base; ++ u32 t; + -+ for (i = 0; i < bdev->pdata->nbuttons; i++) { -+ struct gpio_button *button = &pdata->buttons[i]; -+ unsigned int type = button->type ?: EV_KEY; -+ int state; ++ irq -= AR71XX_GPIO_IRQ_BASE; + -+ if (bdev->data[i].count < button->threshold) { -+ bdev->data[i].count++; -+ continue; -+ } ++ t = __raw_readl(base + GPIO_REG_INT_ENABLE); ++ __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE); + -+ state = gpio_get_value(button->gpio) ? 1 : 0; -+ if (state != bdev->data[i].last_state) { -+ input_event(input, type, button->code, -+ !!(state ^ button->active_low)); -+ input_sync(input); -+ bdev->data[i].count = 0; -+ bdev->data[i].last_state = state; -+ } -+ } ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_INT_ENABLE); +} + -+static int __devinit gpio_buttons_probe(struct platform_device *pdev) ++#if 0 ++static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) +{ -+ struct gpio_buttons_platform_data *pdata = pdev->dev.platform_data; -+ struct gpio_buttons_dev *bdev; -+ struct input_polled_dev *poll_dev; -+ struct input_dev *input; -+ int error, i; ++ /* TODO: implement */ ++ return 0; ++} ++#else ++#define ar71xx_gpio_irq_set_type NULL ++#endif + -+ if (!pdata) -+ return -ENXIO; ++static struct irq_chip ar71xx_gpio_irq_chip = { ++ .name = "AR71XX GPIO", ++ .unmask = ar71xx_gpio_irq_unmask, ++ .mask = ar71xx_gpio_irq_mask, ++ .mask_ack = ar71xx_gpio_irq_mask, ++ .set_type = ar71xx_gpio_irq_set_type, ++}; + -+ bdev = kzalloc(sizeof(struct gpio_buttons_dev) + -+ sizeof(struct gpio_button_data) * pdata->nbuttons, -+ GFP_KERNEL); -+ if (!bdev) { -+ printk(KERN_ERR DRV_NAME "no memory for device\n"); -+ return -ENOMEM; -+ } ++static struct irqaction ar71xx_gpio_irqaction = { ++ .handler = no_action, ++ .name = "cascade [AR71XX GPIO]", ++}; + -+ bdev->data = (struct gpio_button_data *) &bdev[1]; ++#define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED) ++#define GPIO_INT_ALL 0xffff + -+ poll_dev = input_allocate_polled_device(); -+ if (!poll_dev) { -+ printk(KERN_ERR DRV_NAME "no memory for polled device\n"); -+ error = -ENOMEM; -+ goto err_free_bdev; -+ } ++static void __init ar71xx_gpio_irq_init(void) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ int i; + -+ poll_dev->private = bdev; -+ poll_dev->poll = gpio_buttons_poll; -+ poll_dev->poll_interval = pdata->poll_interval; ++ __raw_writel(0, base + GPIO_REG_INT_ENABLE); ++ __raw_writel(0, base + GPIO_REG_INT_PENDING); + -+ input = poll_dev->input; ++ /* setup type of all GPIO interrupts to level sensitive */ ++ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE); + -+ input->evbit[0] = BIT(EV_KEY); -+ input->name = pdev->name; -+ input->phys = "gpio-buttons/input0"; -+ input->dev.parent = &pdev->dev; ++ /* setup polarity of all GPIO interrupts to active high */ ++ __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY); + -+ input->id.bustype = BUS_HOST; -+ input->id.vendor = 0x0001; -+ input->id.product = 0x0001; -+ input->id.version = 0x0100; ++ for (i = AR71XX_GPIO_IRQ_BASE; ++ i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++) { ++ irq_desc[i].status = GPIO_IRQ_INIT_STATUS; ++ set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip, ++ handle_level_irq); ++ } + -+ for (i = 0; i < pdata->nbuttons; i++) { -+ struct gpio_button *button = &pdata->buttons[i]; -+ unsigned int gpio = button->gpio; -+ unsigned int type = button->type ?: EV_KEY; ++ setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction); ++} + -+ error = gpio_request(gpio, button->desc ? -+ button->desc : DRV_NAME); -+ if (error) { -+ printk(KERN_ERR PFX "unable to claim gpio %u, " -+ "error %d\n", gpio, error); -+ goto err_free_gpio; -+ } ++static void ar71xx_misc_irq_dispatch(void) ++{ ++ u32 pending; + -+ error = gpio_direction_input(gpio); -+ if (error) { -+ printk(KERN_ERR PFX "unable to set direction on " -+ "gpio %u, error %d\n", gpio, error); -+ goto err_free_gpio; -+ } ++ pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS) ++ & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE); + -+ input_set_capability(input, type, button->code); -+ bdev->data[i].last_state = gpio_get_value(button->gpio) ? 1 : 0; -+ } ++ if (pending & MISC_INT_UART) ++ do_IRQ(AR71XX_MISC_IRQ_UART); + -+ bdev->poll_dev = poll_dev; -+ bdev->pdata = pdata; -+ platform_set_drvdata(pdev, bdev); ++ else if (pending & MISC_INT_DMA) ++ do_IRQ(AR71XX_MISC_IRQ_DMA); + -+ error = input_register_polled_device(poll_dev); -+ if (error) { -+ printk(KERN_ERR PFX "unable to register polled device, " -+ "error %d\n", error); -+ goto err_free_gpio; -+ } ++ else if (pending & MISC_INT_PERFC) ++ do_IRQ(AR71XX_MISC_IRQ_PERFC); + -+ return 0; ++ else if (pending & MISC_INT_TIMER) ++ do_IRQ(AR71XX_MISC_IRQ_TIMER); + -+err_free_gpio: -+ for (i = i - 1; i >= 0; i--) -+ gpio_free(pdata->buttons[i].gpio); ++ else if (pending & MISC_INT_OHCI) ++ do_IRQ(AR71XX_MISC_IRQ_OHCI); + -+ input_free_polled_device(poll_dev); ++ else if (pending & MISC_INT_ERROR) ++ do_IRQ(AR71XX_MISC_IRQ_ERROR); + -+err_free_bdev: -+ kfree(bdev); ++ else if (pending & MISC_INT_GPIO) ++ ar71xx_gpio_irq_dispatch(); + -+ platform_set_drvdata(pdev, NULL); -+ return error; ++ else if (pending & MISC_INT_WDOG) ++ do_IRQ(AR71XX_MISC_IRQ_WDOG); ++ ++ else ++ spurious_interrupt(); +} + -+static int __devexit gpio_buttons_remove(struct platform_device *pdev) ++static void ar71xx_misc_irq_unmask(unsigned int irq) +{ -+ struct gpio_buttons_dev *bdev = platform_get_drvdata(pdev); -+ struct gpio_buttons_platform_data *pdata = bdev->pdata; -+ int i; ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; + -+ input_unregister_polled_device(bdev->poll_dev); ++ irq -= AR71XX_MISC_IRQ_BASE; + -+ for (i = 0; i < pdata->nbuttons; i++) -+ gpio_free(pdata->buttons[i].gpio); ++ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + -+ input_free_polled_device(bdev->poll_dev); ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++} + -+ kfree(bdev); -+ platform_set_drvdata(pdev, NULL); ++static void ar71xx_misc_irq_mask(unsigned int irq) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; + -+ return 0; -+} ++ irq -= AR71XX_MISC_IRQ_BASE; + -+static struct platform_driver gpio_buttons_driver = { -+ .probe = gpio_buttons_probe, -+ .remove = __devexit_p(gpio_buttons_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; ++ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); + -+static int __init gpio_buttons_init(void) -+{ -+ printk(KERN_INFO DRV_NAME " driver version " DRV_VERSION "\n"); -+ return platform_driver_register(&gpio_buttons_driver); ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); +} + -+static void __exit gpio_buttons_exit(void) ++static void ar724x_misc_irq_ack(unsigned int irq) +{ -+ platform_driver_unregister(&gpio_buttons_driver); -+} ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; + -+module_init(gpio_buttons_init); -+module_exit(gpio_buttons_exit); ++ irq -= AR71XX_MISC_IRQ_BASE; + -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_VERSION(DRV_VERSION); -+MODULE_DESCRIPTION("Polled buttons driver for CPU GPIOs"); ++ t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); ++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS); + -diff -Nur linux-2.6.35.7.orig/drivers/input/misc/Kconfig linux-2.6.35.7/drivers/input/misc/Kconfig ---- linux-2.6.35.7.orig/drivers/input/misc/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/input/misc/Kconfig 2010-10-14 20:27:59.998101300 +0200 -@@ -390,4 +390,20 @@ - To compile this driver as a module, choose M here: the - module will be called pcap_keys. - -+config INPUT_GPIO_BUTTONS -+ tristate "Polled GPIO buttons interface" -+ depends on GENERIC_GPIO -+ select INPUT_POLLDEV -+ help -+ This driver implements support for buttons connected -+ to GPIO pins of various CPUs (and some other chips). ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); ++} ++ ++static struct irq_chip ar71xx_misc_irq_chip = { ++ .name = "AR71XX MISC", ++ .unmask = ar71xx_misc_irq_unmask, ++ .mask = ar71xx_misc_irq_mask, ++}; + -+ Say Y here if your device has buttons connected -+ directly to such GPIO pins. Your board-specific -+ setup logic must also provide a platform device, -+ with configuration data saying which GPIOs are used. ++static struct irqaction ar71xx_misc_irqaction = { ++ .handler = no_action, ++ .name = "cascade [AR71XX MISC]", ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called gpio-buttons. ++static void __init ar71xx_misc_irq_init(void) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ int i; + - endif -diff -Nur linux-2.6.35.7.orig/drivers/input/misc/Kconfig.orig linux-2.6.35.7/drivers/input/misc/Kconfig.orig ---- linux-2.6.35.7.orig/drivers/input/misc/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/input/misc/Kconfig.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,393 @@ -+# -+# Input misc drivers configuration -+# -+menuconfig INPUT_MISC -+ bool "Miscellaneous devices" -+ help -+ Say Y here, and a list of miscellaneous input drivers will be displayed. -+ Everything that didn't fit into the other categories is here. This option -+ doesn't affect the kernel. ++ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); ++ __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); + -+ If unsure, say Y. ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack; ++ break; ++ default: ++ ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask; ++ break; ++ } + -+if INPUT_MISC ++ for (i = AR71XX_MISC_IRQ_BASE; ++ i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++) { ++ irq_desc[i].status = IRQ_DISABLED; ++ set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip, ++ handle_level_irq); ++ } + -+config INPUT_88PM860X_ONKEY -+ tristate "88PM860x ONKEY support" -+ depends on MFD_88PM860X -+ help -+ Support the ONKEY of Marvell 88PM860x PMICs as an input device -+ reporting power button status. ++ setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction); ++} + -+ To compile this driver as a module, choose M here: the module -+ will be called 88pm860x_onkey. ++asmlinkage void plat_irq_dispatch(void) ++{ ++ unsigned long pending; + -+config INPUT_AD714X -+ tristate "Analog Devices AD714x Capacitance Touch Sensor" -+ help -+ Say Y here if you want to support an AD7142/3/7/8/7A touch sensor. ++ pending = read_c0_status() & read_c0_cause() & ST0_IM; + -+ You should select a bus connection too. ++ if (pending & STATUSF_IP7) ++ do_IRQ(AR71XX_CPU_IRQ_TIMER); + -+ To compile this driver as a module, choose M here: the -+ module will be called ad714x. ++ else if (pending & STATUSF_IP2) { ++ /* ++ * This IRQ is meant for a PCI device. Drivers for PCI devices ++ * typically allocate coherent DMA memory for the descriptor ++ * ring, however the DMA controller may still have some ++ * unsynchronized data in the FIFO. ++ * Issue a flush here to ensure that the driver sees the update. ++ */ ++ ar71xx_ddr_flush(ip2_flush_reg); ++ do_IRQ(AR71XX_CPU_IRQ_IP2); ++ } + -+config INPUT_AD714X_I2C -+ tristate "support I2C bus connection" -+ depends on INPUT_AD714X && I2C -+ default y -+ help -+ Say Y here if you have AD7142/AD7147 hooked to an I2C bus. ++ else if (pending & STATUSF_IP4) ++ do_IRQ(AR71XX_CPU_IRQ_GE0); + -+ To compile this driver as a module, choose M here: the -+ module will be called ad714x-i2c. ++ else if (pending & STATUSF_IP5) ++ do_IRQ(AR71XX_CPU_IRQ_GE1); + -+config INPUT_AD714X_SPI -+ tristate "support SPI bus connection" -+ depends on INPUT_AD714X && SPI -+ default y -+ help -+ Say Y here if you have AD7142/AD7147 hooked to a SPI bus. ++ else if (pending & STATUSF_IP3) ++ do_IRQ(AR71XX_CPU_IRQ_USB); + -+ To compile this driver as a module, choose M here: the -+ module will be called ad714x-spi. ++ else if (pending & STATUSF_IP6) ++ ar71xx_misc_irq_dispatch(); + -+config INPUT_PCSPKR -+ tristate "PC Speaker support" -+ depends on PCSPKR_PLATFORM -+ help -+ Say Y here if you want the standard PC Speaker to be used for -+ bells and whistles. ++ else ++ spurious_interrupt(); ++} + -+ If unsure, say Y. ++void __init arch_init_irq(void) ++{ ++ switch(ar71xx_soc) { ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE; ++ break; ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC; ++ break; ++ default: ++ ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI; ++ break; ++ } ++ mips_cpu_irq_init(); + -+ To compile this driver as a module, choose M here: the -+ module will be called pcspkr. ++ ar71xx_misc_irq_init(); + -+config INPUT_SPARCSPKR -+ tristate "SPARC Speaker support" -+ depends on PCI && SPARC64 -+ help -+ Say Y here if you want the standard Speaker on Sparc PCI systems -+ to be used for bells and whistles. ++ cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC; + -+ If unsure, say Y. ++ ar71xx_gpio_irq_init(); ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-ap81.c linux-2.6.36/arch/mips/ar71xx/mach-ap81.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-ap81.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-ap81.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,140 @@ ++/* ++ * Atheros AP81 board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * Copyright (C) 2009 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ To compile this driver as a module, choose M here: the -+ module will be called sparcspkr. ++#include ++#include + -+config INPUT_M68K_BEEP -+ tristate "M68k Beeper support" -+ depends on M68K ++#include + -+config INPUT_MAX8925_ONKEY -+ tristate "MAX8925 ONKEY support" -+ depends on MFD_MAX8925 -+ help -+ Support the ONKEY of MAX8925 PMICs as an input device -+ reporting power button status. ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+ To compile this driver as a module, choose M here: the module -+ will be called max8925_onkey. ++#define AP81_GPIO_LED_STATUS 1 ++#define AP81_GPIO_LED_AOSS 3 ++#define AP81_GPIO_LED_WLAN 6 ++#define AP81_GPIO_LED_POWER 14 + -+config INPUT_APANEL -+ tristate "Fujitsu Lifebook Application Panel buttons" -+ depends on X86 && I2C && LEDS_CLASS -+ select INPUT_POLLDEV -+ select CHECK_SIGNATURE -+ help -+ Say Y here for support of the Application Panel buttons, used on -+ Fujitsu Lifebook. These are attached to the mainboard through -+ an SMBus interface managed by the I2C Intel ICH (i801) driver, -+ which you should also build for this kernel. ++#define AP81_GPIO_BTN_SW4 12 ++#define AP81_GPIO_BTN_SW1 21 + -+ To compile this driver as a module, choose M here: the module will -+ be called apanel. ++#define AP81_BUTTONS_POLL_INTERVAL 20 + -+config INPUT_IXP4XX_BEEPER -+ tristate "IXP4XX Beeper support" -+ depends on ARCH_IXP4XX -+ help -+ If you say yes here, you can connect a beeper to the -+ ixp4xx gpio pins. This is used by the LinkSys NSLU2. ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition ap81_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x500000, ++ } , { ++ .name = "uImage", ++ .offset = 0x550000, ++ .size = 0x100000, ++ } , { ++ .name = "ART", ++ .offset = 0x650000, ++ .size = 0x1b0000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+ If unsure, say Y. ++static struct flash_platform_data ap81_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = ap81_partitions, ++ .nr_parts = ARRAY_SIZE(ap81_partitions), ++#endif ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called ixp4xx-beeper. ++static struct gpio_led ap81_leds_gpio[] __initdata = { ++ { ++ .name = "ap81:green:status", ++ .gpio = AP81_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "ap81:amber:aoss", ++ .gpio = AP81_GPIO_LED_AOSS, ++ .active_low = 1, ++ }, { ++ .name = "ap81:green:wlan", ++ .gpio = AP81_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "ap81:green:power", ++ .gpio = AP81_GPIO_LED_POWER, ++ .active_low = 1, ++ } ++}; + -+config INPUT_COBALT_BTNS -+ tristate "Cobalt button interface" -+ depends on MIPS_COBALT -+ select INPUT_POLLDEV -+ help -+ Say Y here if you want to support MIPS Cobalt button interface. ++static struct gpio_button ap81_gpio_buttons[] __initdata = { ++ { ++ .desc = "sw1", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .threshold = 3, ++ .gpio = AP81_GPIO_BTN_SW1, ++ .active_low = 1, ++ } , { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .threshold = 3, ++ .gpio = AP81_GPIO_BTN_SW4, ++ .active_low = 1, ++ } ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called cobalt_btns. ++static void __init ap81_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+config INPUT_WISTRON_BTNS -+ tristate "x86 Wistron laptop button interface" -+ depends on X86 && !X86_64 -+ select INPUT_POLLDEV -+ select INPUT_SPARSEKMAP -+ select NEW_LEDS -+ select LEDS_CLASS -+ select CHECK_SIGNATURE -+ help -+ Say Y here for support of Wistron laptop button interfaces, used on -+ laptops of various brands, including Acer and Fujitsu-Siemens. If -+ available, mail and wifi LEDs will be controllable via /sys/class/leds. ++ ar71xx_set_mac_base(eeprom); ++ ar71xx_add_device_mdio(0x0); + -+ To compile this driver as a module, choose M here: the module will -+ be called wistron_btns. ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; + -+config INPUT_ATLAS_BTNS -+ tristate "x86 Atlas button interface" -+ depends on X86 && ACPI -+ help -+ Say Y here for support of Atlas wallmount touchscreen buttons. -+ The events will show up as scancodes F1 through F9 via evdev. ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x10; + -+ To compile this driver as a module, choose M here: the module will -+ be called atlas_btns. ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+config INPUT_ATI_REMOTE -+ tristate "ATI / X10 USB RF remote control" -+ depends on USB_ARCH_HAS_HCD -+ select USB -+ help -+ Say Y here if you want to use an ATI or X10 "Lola" USB remote control. -+ These are RF remotes with USB receivers. -+ The ATI remote comes with many of ATI's All-In-Wonder video cards. -+ The X10 "Lola" remote is available at: -+ -+ This driver provides mouse pointer, left and right mouse buttons, -+ and maps all the other remote buttons to keypress events. -+ -+ To compile this driver as a module, choose M here: the module will be -+ called ati_remote. -+ -+config INPUT_ATI_REMOTE2 -+ tristate "ATI / Philips USB RF remote control" -+ depends on USB_ARCH_HAS_HCD -+ select USB -+ help -+ Say Y here if you want to use an ATI or Philips USB RF remote control. -+ These are RF remotes with USB receivers. -+ ATI Remote Wonder II comes with some ATI's All-In-Wonder video cards -+ and is also available as a separate product. -+ This driver provides mouse pointer, left and right mouse buttons, -+ and maps all the other remote buttons to keypress events. -+ -+ To compile this driver as a module, choose M here: the module will be -+ called ati_remote2. -+ -+config INPUT_KEYSPAN_REMOTE -+ tristate "Keyspan DMR USB remote control (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ depends on USB_ARCH_HAS_HCD -+ select USB -+ help -+ Say Y here if you want to use a Keyspan DMR USB remote control. -+ Currently only the UIA-11 type of receiver has been tested. The tag -+ on the receiver that connects to the USB port should have a P/N that -+ will tell you what type of DMR you have. The UIA-10 type is not -+ supported at this time. This driver maps all buttons to keypress -+ events. -+ -+ To compile this driver as a module, choose M here: the module will -+ be called keyspan_remote. -+ -+config INPUT_POWERMATE -+ tristate "Griffin PowerMate and Contour Jog support" -+ depends on USB_ARCH_HAS_HCD -+ select USB -+ help -+ Say Y here if you want to use Griffin PowerMate or Contour Jog devices. -+ These are aluminum dials which can measure clockwise and anticlockwise -+ rotation. The dial also acts as a pushbutton. The base contains an LED -+ which can be instructed to pulse or to switch to a particular intensity. ++ ar71xx_add_device_usb(); + -+ You can download userspace tools from -+ . ++ ar71xx_add_device_m25p80(&ap81_flash_data); + -+ To compile this driver as a module, choose M here: the -+ module will be called powermate. ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap81_leds_gpio), ++ ap81_leds_gpio); + -+config INPUT_YEALINK -+ tristate "Yealink usb-p1k voip phone" -+ depends on EXPERIMENTAL -+ depends on USB_ARCH_HAS_HCD -+ select USB -+ help -+ Say Y here if you want to enable keyboard and LCD functions of the -+ Yealink usb-p1k usb phones. The audio part is enabled by the generic -+ usb sound driver, so you might want to enable that as well. ++ ar71xx_add_device_gpio_buttons(-1, AP81_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(ap81_gpio_buttons), ++ ap81_gpio_buttons); + -+ For information about how to use these additional functions, see -+ . ++ ar913x_add_device_wmac(eeprom, NULL); ++} + -+ To compile this driver as a module, choose M here: the module will be -+ called yealink. ++MIPS_MACHINE(AR71XX_MACH_AP81, "AP81", "Atheros AP81", ap81_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-ap83.c linux-2.6.36/arch/mips/ar71xx/mach-ap83.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-ap83.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-ap83.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,266 @@ ++/* ++ * Atheros AP83 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+config INPUT_CM109 -+ tristate "C-Media CM109 USB I/O Controller" -+ depends on EXPERIMENTAL -+ depends on USB_ARCH_HAS_HCD -+ select USB -+ help -+ Say Y here if you want to enable keyboard and buzzer functions of the -+ C-Media CM109 usb phones. The audio part is enabled by the generic -+ usb sound driver, so you might want to enable that as well. ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+ To compile this driver as a module, choose M here: the module will be -+ called cm109. ++#include ++#include + -+config INPUT_TWL4030_PWRBUTTON -+ tristate "TWL4030 Power button Driver" -+ depends on TWL4030_CORE -+ help -+ Say Y here if you want to enable power key reporting via the -+ TWL4030 family of chips. ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+ To compile this driver as a module, choose M here. The module will -+ be called twl4030_pwrbutton. ++#define AP83_GPIO_LED_WLAN 6 ++#define AP83_GPIO_LED_POWER 14 ++#define AP83_GPIO_LED_JUMPSTART 15 ++#define AP83_GPIO_BTN_JUMPSTART 12 ++#define AP83_GPIO_BTN_RESET 21 + -+config INPUT_TWL4030_VIBRA -+ tristate "Support for TWL4030 Vibrator" -+ depends on TWL4030_CORE -+ select TWL4030_CODEC -+ select INPUT_FF_MEMLESS -+ help -+ This option enables support for TWL4030 Vibrator Driver. ++#define AP83_050_GPIO_VSC7385_CS 1 ++#define AP83_050_GPIO_VSC7385_MISO 3 ++#define AP83_050_GPIO_VSC7385_MOSI 16 ++#define AP83_050_GPIO_VSC7385_SCK 17 + -+ To compile this driver as a module, choose M here. The module will -+ be called twl4030_vibra. ++#define AP83_BUTTONS_POLL_INTERVAL 20 + -+config INPUT_UINPUT -+ tristate "User level driver support" -+ help -+ Say Y here if you want to support user level drivers for input -+ subsystem accessible under char device 10:223 - /dev/input/uinput. ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition ap83_flash_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "kernel", ++ .offset = 0x060000, ++ .size = 0x140000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x1a0000, ++ .size = 0x650000, ++ } , { ++ .name = "art", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x060000, ++ .size = 0x790000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+ To compile this driver as a module, choose M here: the -+ module will be called uinput. ++static struct ar91xx_flash_platform_data ap83_flash_data = { ++ .width = 2, ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = ap83_flash_partitions, ++ .nr_parts = ARRAY_SIZE(ap83_flash_partitions), ++#endif ++}; + -+config INPUT_SGI_BTNS -+ tristate "SGI Indy/O2 volume button interface" -+ depends on SGI_IP22 || SGI_IP32 -+ select INPUT_POLLDEV -+ help -+ Say Y here if you want to support SGI Indy/O2 volume button interface. ++static struct resource ap83_flash_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called sgi_btns. -+ -+config INPUT_WINBOND_CIR -+ tristate "Winbond IR remote control" -+ depends on X86 && PNP -+ select NEW_LEDS -+ select LEDS_CLASS -+ select LEDS_TRIGGERS -+ select BITREVERSE -+ help -+ Say Y here if you want to use the IR remote functionality found -+ in some Winbond SuperI/O chips. Currently only the WPCD376I -+ chip is supported (included in some Intel Media series motherboards). ++static struct platform_device ap83_flash_device = { ++ .name = "ar91xx-flash", ++ .id = -1, ++ .resource = ap83_flash_resources, ++ .num_resources = ARRAY_SIZE(ap83_flash_resources), ++ .dev = { ++ .platform_data = &ap83_flash_data, ++ } ++}; + -+ IR Receive and wake-on-IR from suspend and power-off is currently -+ supported. ++static struct gpio_led ap83_leds_gpio[] __initdata = { ++ { ++ .name = "ap83:green:jumpstart", ++ .gpio = AP83_GPIO_LED_JUMPSTART, ++ .active_low = 0, ++ }, { ++ .name = "ap83:green:power", ++ .gpio = AP83_GPIO_LED_POWER, ++ .active_low = 0, ++ }, { ++ .name = "ap83:green:wlan", ++ .gpio = AP83_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, ++}; + -+ To compile this driver as a module, choose M here: the module will be -+ called winbond_cir. ++static struct gpio_button ap83_gpio_buttons[] __initdata = { ++ { ++ .desc = "soft_reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = AP83_GPIO_BTN_RESET, ++ .active_low = 1, ++ } , { ++ .desc = "jumpstart", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = AP83_GPIO_BTN_JUMPSTART, ++ .active_low = 1, ++ } ++}; + -+config HP_SDC_RTC -+ tristate "HP SDC Real Time Clock" -+ depends on (GSC || HP300) && SERIO -+ select HP_SDC -+ help -+ Say Y here if you want to support the built-in real time clock -+ of the HP SDC controller. ++static struct resource ap83_040_spi_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; + -+config INPUT_PCF50633_PMU -+ tristate "PCF50633 PMU events" -+ depends on MFD_PCF50633 -+ help -+ Say Y to include support for delivering PMU events via input -+ layer on NXP PCF50633. ++static struct platform_device ap83_040_spi_device = { ++ .name = "ap83-spi", ++ .id = 0, ++ .resource = ap83_040_spi_resources, ++ .num_resources = ARRAY_SIZE(ap83_040_spi_resources), ++}; + -+config INPUT_PCF8574 -+ tristate "PCF8574 Keypad input device" -+ depends on I2C && EXPERIMENTAL -+ help -+ Say Y here if you want to support a keypad connetced via I2C -+ with a PCF8574. ++static struct spi_gpio_platform_data ap83_050_spi_data = { ++ .miso = AP83_050_GPIO_VSC7385_MISO, ++ .mosi = AP83_050_GPIO_VSC7385_MOSI, ++ .sck = AP83_050_GPIO_VSC7385_SCK, ++ .num_chipselect = 1, ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called pcf8574_keypad. ++static struct platform_device ap83_050_spi_device = { ++ .name = "spi_gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &ap83_050_spi_data, ++ } ++}; + -+config INPUT_GPIO_ROTARY_ENCODER -+ tristate "Rotary encoders connected to GPIO pins" -+ depends on GPIOLIB && GENERIC_GPIO -+ help -+ Say Y here to add support for rotary encoders connected to GPIO lines. -+ Check file:Documentation/input/rotary-encoder.txt for more -+ information. ++static void ap83_vsc7385_reset(void) ++{ ++ ar71xx_device_stop(RESET_MODULE_GE1_PHY); ++ udelay(10); ++ ar71xx_device_start(RESET_MODULE_GE1_PHY); ++ mdelay(50); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called rotary_encoder. ++static struct vsc7385_platform_data ap83_vsc7385_data = { ++ .reset = ap83_vsc7385_reset, ++ .ucode_name = "vsc7385_ucode_ap83.bin", ++ .mac_cfg = { ++ .tx_ipg = 6, ++ .bit2 = 0, ++ .clk_sel = 3, ++ }, ++}; + -+config INPUT_RB532_BUTTON -+ tristate "Mikrotik Routerboard 532 button interface" -+ depends on MIKROTIK_RB532 -+ depends on GPIOLIB && GENERIC_GPIO -+ select INPUT_POLLDEV -+ help -+ Say Y here if you want support for the S1 button built into -+ Mikrotik's Routerboard 532. ++static struct spi_board_info ap83_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "spi-vsc7385", ++ .platform_data = &ap83_vsc7385_data, ++ .controller_data = (void *) AP83_050_GPIO_VSC7385_CS, ++ } ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called rb532_button. ++static void __init ap83_generic_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+config INPUT_DM355EVM -+ tristate "TI DaVinci DM355 EVM Keypad and IR Remote" -+ depends on MFD_DM355EVM_MSP -+ select INPUT_SPARSEKMAP -+ help -+ Supports the pushbuttons and IR remote used with -+ the DM355 EVM board. ++ ar71xx_set_mac_base(eeprom); + -+ To compile this driver as a module, choose M here: the -+ module will be called dm355evm_keys. ++ ar71xx_add_device_mdio(0xfffffffe); + -+config INPUT_BFIN_ROTARY -+ tristate "Blackfin Rotary support" -+ depends on BF54x || BF52x -+ help -+ Say Y here if you want to use the Blackfin Rotary. ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = 0x1; + -+ To compile this driver as a module, choose M here: the -+ module will be called bfin-rotary. ++ ar71xx_add_device_eth(0); + -+config INPUT_WM831X_ON -+ tristate "WM831X ON pin" -+ depends on MFD_WM831X -+ help -+ Support the ON pin of WM831X PMICs as an input device -+ reporting power button status. ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; + -+ To compile this driver as a module, choose M here: the module -+ will be called wm831x_on. ++ ar71xx_eth1_pll_data.pll_1000 = 0x1f000000; + -+config INPUT_PCAP -+ tristate "Motorola EZX PCAP misc input events" -+ depends on EZX_PCAP -+ help -+ Say Y here if you want to use Power key and Headphone button -+ on Motorola EZX phones. ++ ar71xx_add_device_eth(1); + -+ To compile this driver as a module, choose M here: the -+ module will be called pcap_keys. ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ap83_leds_gpio), ++ ap83_leds_gpio); + -+endif -diff -Nur linux-2.6.35.7.orig/drivers/input/misc/Makefile linux-2.6.35.7/drivers/input/misc/Makefile ---- linux-2.6.35.7.orig/drivers/input/misc/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/input/misc/Makefile 2010-10-14 20:28:00.038101118 +0200 -@@ -37,4 +37,5 @@ - obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o - obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o - obj-$(CONFIG_INPUT_YEALINK) += yealink.o -+obj-$(CONFIG_INPUT_GPIO_BUTTONS) += gpio_buttons.o - -diff -Nur linux-2.6.35.7.orig/drivers/input/misc/Makefile.orig linux-2.6.35.7/drivers/input/misc/Makefile.orig ---- linux-2.6.35.7.orig/drivers/input/misc/Makefile.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/input/misc/Makefile.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,40 @@ -+# -+# Makefile for the input misc drivers. -+# ++ ar71xx_add_device_gpio_buttons(-1, AP83_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(ap83_gpio_buttons), ++ ap83_gpio_buttons); + -+# Each configuration option enables a list of files. -+ -+obj-$(CONFIG_INPUT_88PM860X_ONKEY) += 88pm860x_onkey.o -+obj-$(CONFIG_INPUT_AD714X) += ad714x.o -+obj-$(CONFIG_INPUT_AD714X_I2C) += ad714x-i2c.o -+obj-$(CONFIG_INPUT_AD714X_SPI) += ad714x-spi.o -+obj-$(CONFIG_INPUT_APANEL) += apanel.o -+obj-$(CONFIG_INPUT_ATI_REMOTE) += ati_remote.o -+obj-$(CONFIG_INPUT_ATI_REMOTE2) += ati_remote2.o -+obj-$(CONFIG_INPUT_ATLAS_BTNS) += atlas_btns.o -+obj-$(CONFIG_INPUT_BFIN_ROTARY) += bfin_rotary.o -+obj-$(CONFIG_INPUT_CM109) += cm109.o -+obj-$(CONFIG_INPUT_COBALT_BTNS) += cobalt_btns.o -+obj-$(CONFIG_INPUT_DM355EVM) += dm355evm_keys.o -+obj-$(CONFIG_HP_SDC_RTC) += hp_sdc_rtc.o -+obj-$(CONFIG_INPUT_IXP4XX_BEEPER) += ixp4xx-beeper.o -+obj-$(CONFIG_INPUT_KEYSPAN_REMOTE) += keyspan_remote.o -+obj-$(CONFIG_INPUT_M68K_BEEP) += m68kspkr.o -+obj-$(CONFIG_INPUT_MAX8925_ONKEY) += max8925_onkey.o -+obj-$(CONFIG_INPUT_PCAP) += pcap_keys.o -+obj-$(CONFIG_INPUT_PCF50633_PMU) += pcf50633-input.o -+obj-$(CONFIG_INPUT_PCF8574) += pcf8574_keypad.o -+obj-$(CONFIG_INPUT_PCSPKR) += pcspkr.o -+obj-$(CONFIG_INPUT_POWERMATE) += powermate.o -+obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o -+obj-$(CONFIG_INPUT_GPIO_ROTARY_ENCODER) += rotary_encoder.o -+obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o -+obj-$(CONFIG_INPUT_SPARCSPKR) += sparcspkr.o -+obj-$(CONFIG_INPUT_TWL4030_PWRBUTTON) += twl4030-pwrbutton.o -+obj-$(CONFIG_INPUT_TWL4030_VIBRA) += twl4030-vibra.o -+obj-$(CONFIG_INPUT_UINPUT) += uinput.o -+obj-$(CONFIG_INPUT_WINBOND_CIR) += winbond-cir.o -+obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o -+obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o -+obj-$(CONFIG_INPUT_YEALINK) += yealink.o -+ -diff -Nur linux-2.6.35.7.orig/drivers/leds/leds-rb750.c linux-2.6.35.7/drivers/leds/leds-rb750.c ---- linux-2.6.35.7.orig/drivers/leds/leds-rb750.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/leds/leds-rb750.c 2010-10-14 20:28:00.074930320 +0200 -@@ -0,0 +1,140 @@ -+/* -+ * LED driver for the RouterBOARD 750 -+ * -+ * Copyright (C) 2010 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+#include -+#include -+#include -+#include ++ ar71xx_add_device_usb(); + -+#include ++ ar913x_add_device_wmac(eeprom, NULL); + -+#define DRV_NAME "leds-rb750" ++ platform_device_register(&ap83_flash_device); + -+struct rb750_led_dev { -+ struct led_classdev cdev; -+ u32 mask; -+ int active_low; -+}; ++ spi_register_board_info(ap83_spi_info, ARRAY_SIZE(ap83_spi_info)); ++} + -+struct rb750_led_drvdata { -+ struct rb750_led_dev *led_devs; -+ int num_leds; -+}; ++static void __init ap83_040_setup(void) ++{ ++ ap83_flash_data.is_shared=1; ++ ap83_generic_setup(); ++ platform_device_register(&ap83_040_spi_device); ++} + -+static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) ++static void __init ap83_050_setup(void) +{ -+ return (struct rb750_led_dev *)container_of(led_cdev, -+ struct rb750_led_dev, cdev); ++ ap83_generic_setup(); ++ platform_device_register(&ap83_050_spi_device); +} + -+static void rb750_led_brightness_set(struct led_classdev *led_cdev, -+ enum led_brightness value) ++static void __init ap83_setup(void) +{ -+ struct rb750_led_dev *rbled = to_rbled(led_cdev); -+ int level; ++ u8 *board_id = (u8 *) KSEG1ADDR(0x1fff1244); ++ unsigned int board_version; + -+ level = (value == LED_OFF) ? 0 : 1; -+ level ^= rbled->active_low; ++ board_version = (unsigned int)(board_id[0] - '0'); ++ board_version += ((unsigned int)(board_id[1] - '0')) * 10; + -+ if (level) -+ rb750_latch_change(0, rbled->mask); -+ else -+ rb750_latch_change(rbled->mask, 0); ++ switch (board_version) { ++ case 40: ++ ap83_040_setup(); ++ break; ++ case 50: ++ ap83_050_setup(); ++ break; ++ default: ++ printk(KERN_WARNING "AP83-%03u board is not yet supported\n", ++ board_version); ++ } +} + -+static int __devinit rb750_led_probe(struct platform_device *pdev) -+{ -+ struct rb750_led_platform_data *pdata; -+ struct rb750_led_drvdata *drvdata; -+ int ret = 0; -+ int i; ++MIPS_MACHINE(AR71XX_MACH_AP83, "AP83", "Atheros AP83", ap83_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-aw-nr580.c linux-2.6.36/arch/mips/ar71xx/mach-aw-nr580.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-aw-nr580.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-aw-nr580.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,101 @@ ++/* ++ * AzureWave AW-NR580 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ pdata = pdev->dev.platform_data; -+ if (!pdata) -+ return -EINVAL; ++#include ++#include + -+ drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + -+ sizeof(struct rb750_led_dev) * pdata->num_leds, -+ GFP_KERNEL); -+ if (!drvdata) -+ return -ENOMEM; ++#include ++#include + -+ drvdata->num_leds = pdata->num_leds; -+ drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-leds-gpio.h" + -+ for (i = 0; i < drvdata->num_leds; i++) { -+ struct rb750_led_dev *rbled = &drvdata->led_devs[i]; -+ struct rb750_led_data *led_data = &pdata->leds[i]; ++#define AW_NR580_GPIO_LED_READY_RED 0 ++#define AW_NR580_GPIO_LED_WLAN 1 ++#define AW_NR580_GPIO_LED_READY_GREEN 2 ++#define AW_NR580_GPIO_LED_WPS_GREEN 4 ++#define AW_NR580_GPIO_LED_WPS_AMBER 5 + -+ rbled->cdev.name = led_data->name; -+ rbled->cdev.default_trigger = led_data->default_trigger; -+ rbled->cdev.brightness_set = rb750_led_brightness_set; -+ rbled->cdev.brightness = LED_OFF; ++#define AW_NR580_GPIO_BTN_WPS 3 ++#define AW_NR580_GPIO_BTN_RESET 11 + -+ rbled->mask = led_data->mask; -+ rbled->active_low = !!led_data->active_low; ++#define AW_NR580_BUTTONS_POLL_INTERVAL 20 + -+ ret = led_classdev_register(&pdev->dev, &rbled->cdev); -+ if (ret) -+ goto err; ++static struct gpio_led aw_nr580_leds_gpio[] __initdata = { ++ { ++ .name = "aw-nr580:red:ready", ++ .gpio = AW_NR580_GPIO_LED_READY_RED, ++ .active_low = 0, ++ }, { ++ .name = "aw-nr580:green:ready", ++ .gpio = AW_NR580_GPIO_LED_READY_GREEN, ++ .active_low = 0, ++ }, { ++ .name = "aw-nr580:green:wps", ++ .gpio = AW_NR580_GPIO_LED_WPS_GREEN, ++ .active_low = 0, ++ }, { ++ .name = "aw-nr580:amber:wps", ++ .gpio = AW_NR580_GPIO_LED_WPS_AMBER, ++ .active_low = 0, ++ }, { ++ .name = "aw-nr580:green:wlan", ++ .gpio = AW_NR580_GPIO_LED_WLAN, ++ .active_low = 0, + } ++}; + -+ platform_set_drvdata(pdev, drvdata); -+ return 0; -+ -+ err: -+ for (i = i - 1; i >= 0; i--) -+ led_classdev_unregister(&drvdata->led_devs[i].cdev); -+ -+ kfree(drvdata); -+ return ret; -+} ++static struct gpio_button aw_nr580_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = AW_NR580_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = AW_NR580_GPIO_BTN_WPS, ++ .active_low = 1, ++ } ++}; + -+static int __devexit rb750_led_remove(struct platform_device *pdev) ++static void __init aw_nr580_setup(void) +{ -+ struct rb750_led_drvdata *drvdata; -+ int i; ++ ar71xx_add_device_mdio(0x0); + -+ drvdata = platform_get_drvdata(pdev); -+ for (i = 0; i < drvdata->num_leds; i++) -+ led_classdev_unregister(&drvdata->led_devs[i].cdev); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+ kfree(drvdata); -+ return 0; -+} ++ ar71xx_add_device_eth(0); + -+static struct platform_driver rb750_led_driver = { -+ .probe = rb750_led_probe, -+ .remove = __devexit_p(rb750_led_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; ++ pb42_pci_init(); + -+MODULE_ALIAS("platform:leds-rb750"); ++ ar71xx_add_device_m25p80(NULL); + -+static int __init rb750_led_init(void) -+{ -+ return platform_driver_register(&rb750_led_driver); -+} ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(aw_nr580_leds_gpio), ++ aw_nr580_leds_gpio); + -+static void __exit rb750_led_exit(void) -+{ -+ platform_driver_unregister(&rb750_led_driver); ++ ar71xx_add_device_gpio_buttons(-1, AW_NR580_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(aw_nr580_gpio_buttons), ++ aw_nr580_gpio_buttons); +} + -+module_init(rb750_led_init); -+module_exit(rb750_led_exit); -+ -+MODULE_DESCRIPTION(DRV_NAME); -+MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.35.7.orig/drivers/leds/leds-wndr3700-usb.c linux-2.6.35.7/drivers/leds/leds-wndr3700-usb.c ---- linux-2.6.35.7.orig/drivers/leds/leds-wndr3700-usb.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/leds/leds-wndr3700-usb.c 2010-10-14 20:28:00.116443396 +0200 -@@ -0,0 +1,75 @@ ++MIPS_MACHINE(AR71XX_MACH_AW_NR580, "AW-NR580", "AzureWave AW-NR580", ++ aw_nr580_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-600-a1.c linux-2.6.36/arch/mips/ar71xx/mach-dir-600-a1.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-600-a1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-dir-600-a1.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,138 @@ +/* -+ * USB LED driver for the NETGEAR WNDR3700 ++ * D-Link DIR-600 rev. A1 board support + * -+ * Copyright (C) 2009 Gabor Juhos ++ * Copyright (C) 2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include -+#include -+#include ++#include ++#include + +#include + -+#define DRIVER_NAME "wndr3700-led-usb" ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-eth.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "nvram.h" + -+static void wndr3700_usb_led_set(struct led_classdev *cdev, -+ enum led_brightness brightness) -+{ -+ if (brightness) -+ ar71xx_device_start(RESET_MODULE_GE1_PHY); -+ else -+ ar71xx_device_stop(RESET_MODULE_GE1_PHY); -+} ++#define DIR_600_A1_GPIO_LED_WPS 0 ++#define DIR_600_A1_GPIO_LED_POWER_AMBER 1 ++#define DIR_600_A1_GPIO_LED_POWER_GREEN 6 ++ ++#define DIR_600_A1_GPIO_BTN_RESET 8 ++#define DIR_600_A1_GPIO_BTN_WPS 12 ++ ++#define DIR_600_A1_BUTTONS_POLL_INTERVAL 20 ++ ++#define DIR_600_A1_NVRAM_ADDR 0x1f030000 ++#define DIR_600_A1_NVRAM_SIZE 0x10000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition dir_600_a1_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x030000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "nvram", ++ .offset = 0x030000, ++ .size = 0x010000, ++ }, { ++ .name = "kernel", ++ .offset = 0x040000, ++ .size = 0x0e0000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x120000, ++ .size = 0x2c0000, ++ }, { ++ .name = "mac", ++ .offset = 0x3e0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x040000, ++ .size = 0x3a0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data dir_600_a1_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = dir_600_a1_partitions, ++ .nr_parts = ARRAY_SIZE(dir_600_a1_partitions), ++#endif ++}; + -+static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) -+{ -+ return ar71xx_device_stopped(RESET_MODULE_GE1_PHY) ? LED_OFF : LED_FULL; -+} ++static struct gpio_led dir_600_a1_leds_gpio[] __initdata = { ++ { ++ .name = "dir-600-a1:green:power", ++ .gpio = DIR_600_A1_GPIO_LED_POWER_GREEN, ++ }, { ++ .name = "dir-600-a1:amber:power", ++ .gpio = DIR_600_A1_GPIO_LED_POWER_AMBER, ++ }, { ++ .name = "dir-600-a1:blue:wps", ++ .gpio = DIR_600_A1_GPIO_LED_WPS, ++ .active_low = 1, ++ } ++}; + -+static struct led_classdev wndr3700_usb_led = { -+ .name = "wndr3700:green:usb", -+ .brightness_set = wndr3700_usb_led_set, -+ .brightness_get = wndr3700_usb_led_get, ++static struct gpio_button dir_600_a1_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = DIR_600_A1_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = DIR_600_A1_GPIO_BTN_WPS, ++ .active_low = 1, ++ } +}; + -+static int __devinit wndr3700_usb_led_probe(struct platform_device *pdev) ++static void __init dir_600_a1_setup(void) +{ -+ return led_classdev_register(&pdev->dev, &wndr3700_usb_led); -+} ++ const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 mac_buff[6]; ++ u8 *mac = NULL; + -+static int __devexit wndr3700_usb_led_remove(struct platform_device *pdev) -+{ -+ led_classdev_unregister(&wndr3700_usb_led); -+ return 0; -+} ++ if (nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE, ++ "lan_mac=", mac_buff) == 0) ++ mac = mac_buff; + -+static struct platform_driver wndr3700_usb_led_driver = { -+ .probe = wndr3700_usb_led_probe, -+ .remove = __devexit_p(wndr3700_usb_led_remove), -+ .driver = { -+ .name = DRIVER_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; ++ ar71xx_add_device_m25p80(&dir_600_a1_flash_data); + -+static int __init wndr3700_usb_led_init(void) -+{ -+ return platform_driver_register(&wndr3700_usb_led_driver); -+} ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio), ++ dir_600_a1_leds_gpio); + -+static void __exit wndr3700_usb_led_exit(void) -+{ -+ platform_driver_unregister(&wndr3700_usb_led_driver); -+} ++ ar71xx_add_device_gpio_buttons(-1, DIR_600_A1_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(dir_600_a1_gpio_buttons), ++ dir_600_a1_gpio_buttons); + -+module_init(wndr3700_usb_led_init); -+module_exit(wndr3700_usb_led_exit); ++ ap91_eth_init(mac, NULL); ++ ap91_pci_init(ee, mac); ++} + -+MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" DRIVER_NAME); -diff -Nur linux-2.6.35.7.orig/drivers/mtd/maps/ar91xx_flash.c linux-2.6.35.7/drivers/mtd/maps/ar91xx_flash.c ---- linux-2.6.35.7.orig/drivers/mtd/maps/ar91xx_flash.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/mtd/maps/ar91xx_flash.c 2010-10-14 20:28:00.154356608 +0200 -@@ -0,0 +1,310 @@ ++MIPS_MACHINE(AR71XX_MACH_DIR_600_A1, "DIR-600-A1", "D-Link DIR-600 rev. A1", ++ dir_600_a1_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-615-c1.c linux-2.6.36/arch/mips/ar71xx/mach-dir-615-c1.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-615-c1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-dir-615-c1.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,173 @@ +/* -+ * Parallel flash driver for the Atheros AR91xx SoC -+ * -+ * Copyright (C) 2009 Gabor Juhos ++ * D-Link DIR-615 rev C1 board support + * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ + -+#include -+#include -+#include -+#include -+#include -+#include -+#include +#include -+#include +#include -+#include + +#include -+#include -+ -+#define DRV_NAME "ar91xx-flash" -+ -+struct ar91xx_flash_info { -+ struct mtd_info *mtd; -+ struct map_info map; -+#ifdef CONFIG_MTD_PARTITIONS -+ int nr_parts; -+ struct mtd_partition *parts; -+#endif -+}; -+ -+static map_word ar91xx_flash_read(struct map_info *map, unsigned long ofs) -+{ -+ map_word val; -+ -+ if (map_bankwidth_is_1(map)) -+ val.x[0] = __raw_readb(map->virt + (ofs ^ 3)); -+ else if (map_bankwidth_is_2(map)) -+ val.x[0] = __raw_readw(map->virt + (ofs ^ 2)); -+ else -+ val = map_word_ff(map); -+ -+ return val; -+} -+ -+static void ar91xx_flash_write(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ if (map_bankwidth_is_1(map)) -+ __raw_writeb(d.x[0], map->virt + (ofs ^ 3)); -+ else if (map_bankwidth_is_2(map)) -+ __raw_writew(d.x[0], map->virt + (ofs ^ 2)); -+ -+ mb(); -+} -+ -+static map_word ar91xx_flash_read_lock(struct map_info *map, unsigned long ofs) -+{ -+ map_word ret; -+ -+ ar71xx_flash_acquire(); -+ ret = ar91xx_flash_read(map, ofs); -+ ar71xx_flash_release(); -+ -+ return ret; -+} -+ -+static void ar91xx_flash_write_lock(struct map_info *map, map_word d, -+ unsigned long ofs) -+{ -+ ar71xx_flash_acquire(); -+ ar91xx_flash_write(map, d, ofs); -+ ar71xx_flash_release(); -+} + -+static void ar91xx_flash_copy_from_lock(struct map_info *map, void *to, -+ unsigned long from, ssize_t len) -+{ -+ ar71xx_flash_acquire(); -+ inline_map_copy_from(map, to, from, len); -+ ar71xx_flash_release(); -+} ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "nvram.h" + -+static void ar91xx_flash_copy_to_lock(struct map_info *map, unsigned long to, -+ const void *from, ssize_t len) -+{ -+ ar71xx_flash_acquire(); -+ inline_map_copy_to(map, to, from, len); -+ ar71xx_flash_release(); -+} ++#define DIR_615C1_GPIO_LED_ORANGE_STATUS 1 /* ORANGE:STATUS:TRICOLOR */ ++#define DIR_615C1_GPIO_LED_BLUE_WPS 3 /* BLUE:WPS */ ++#define DIR_615C1_GPIO_LED_GREEN_WAN 4 /* GREEN:WAN:TRICOLOR */ ++#define DIR_615C1_GPIO_LED_GREEN_WANCPU 5 /* GREEN:WAN:CPU:TRICOLOR */ ++#define DIR_615C1_GPIO_LED_GREEN_WLAN 6 /* GREEN:WLAN */ ++#define DIR_615C1_GPIO_LED_GREEN_STATUS 14 /* GREEN:STATUS:TRICOLOR */ ++#define DIR_615C1_GPIO_LED_ORANGE_WAN 15 /* ORANGE:WAN:TRICOLOR */ + -+static int ar91xx_flash_remove(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_platform_data *pdata; -+ struct ar91xx_flash_info *info; ++/* buttons may need refinement */ + -+ info = platform_get_drvdata(pdev); -+ if (info == NULL) -+ return 0; ++#define DIR_615C1_GPIO_BTN_WPS 12 ++#define DIR_615C1_GPIO_BTN_RESET 21 + -+ platform_set_drvdata(pdev, NULL); ++#define DIR_615C1_BUTTONS_POLL_INTERVAL 20 + -+ if (info->mtd == NULL) -+ return 0; ++#define DIR_615C1_CONFIG_ADDR 0x1f020000 ++#define DIR_615C1_CONFIG_SIZE 0x10000 + -+ pdata = pdev->dev.platform_data; +#ifdef CONFIG_MTD_PARTITIONS -+ if (info->nr_parts) { -+ del_mtd_partitions(info->mtd); -+ kfree(info->parts); -+ } else if (pdata->nr_parts) { -+ del_mtd_partitions(info->mtd); -+ } else { -+ del_mtd_device(info->mtd); -+ } -+#else -+ del_mtd_device(info->mtd); -+#endif -+ map_destroy(info->mtd); -+ -+ return 0; -+} ++static struct mtd_partition dir_615c1_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "config", ++ .offset = 0x020000, ++ .size = 0x010000, ++ } , { ++ .name = "kernel", ++ .offset = 0x030000, ++ .size = 0x0d0000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x100000, ++ .size = 0x2f0000, ++ } , { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x030000, ++ .size = 0x3c0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; ++static struct flash_platform_data dir_615c1_flash_data = { +#ifdef CONFIG_MTD_PARTITIONS -+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; ++ .parts = dir_615c1_partitions, ++ .nr_parts = ARRAY_SIZE(dir_615c1_partitions), +#endif ++}; + -+static int ar91xx_flash_probe(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_platform_data *pdata; -+ struct ar91xx_flash_info *info; -+ struct resource *res; -+ struct resource *region; -+ const char **probe_type; -+ int err = 0; -+ -+ pdata = pdev->dev.platform_data; -+ if (pdata == NULL) -+ return -EINVAL; -+ -+ info = devm_kzalloc(&pdev->dev, sizeof(struct ar91xx_flash_info), -+ GFP_KERNEL); -+ if (info == NULL) { -+ err = -ENOMEM; -+ goto err_out; ++static struct gpio_led dir_615c1_leds_gpio[] __initdata = { ++ { ++ .name = "dir-615c1:orange:status", ++ .gpio = DIR_615C1_GPIO_LED_ORANGE_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:blue:wps", ++ .gpio = DIR_615C1_GPIO_LED_BLUE_WPS, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:green:wan", ++ .gpio = DIR_615C1_GPIO_LED_GREEN_WAN, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:green:wancpu", ++ .gpio = DIR_615C1_GPIO_LED_GREEN_WANCPU, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:green:wlan", ++ .gpio = DIR_615C1_GPIO_LED_GREEN_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:green:status", ++ .gpio = DIR_615C1_GPIO_LED_GREEN_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "dir-615c1:orange:wan", ++ .gpio = DIR_615C1_GPIO_LED_ORANGE_WAN, ++ .active_low = 1, + } + -+ platform_set_drvdata(pdev, info); ++}; + -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (res == NULL) { -+ err = -ENOENT; -+ goto err_out; ++static struct gpio_button dir_615c1_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = DIR_615C1_GPIO_BTN_RESET, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = DIR_615C1_GPIO_BTN_WPS, + } ++}; + -+ dev_info(&pdev->dev, "%.8llx at %.8llx\n", -+ (unsigned long long)(res->end - res->start + 1), -+ (unsigned long long)res->start); -+ -+ region = devm_request_mem_region(&pdev->dev, -+ res->start, res->end - res->start + 1, -+ dev_name(&pdev->dev)); -+ if (region == NULL) { -+ dev_err(&pdev->dev, "could not reserve memory region\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } ++#define DIR_615C1_LAN_PHYMASK BIT(0) ++#define DIR_615C1_WAN_PHYMASK BIT(4) ++#define DIR_615C1_MDIO_MASK (~(DIR_615C1_LAN_PHYMASK | \ ++ DIR_615C1_WAN_PHYMASK)) + -+ info->map.name = dev_name(&pdev->dev); -+ info->map.phys = res->start; -+ info->map.size = res->end - res->start + 1; -+ info->map.bankwidth = pdata->width; ++static void __init dir_615c1_setup(void) ++{ ++ const char *config = (char *) KSEG1ADDR(DIR_615C1_CONFIG_ADDR); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 mac[6]; ++ u8 *wlan_mac = NULL; + -+ info->map.virt = devm_ioremap(&pdev->dev, info->map.phys, -+ info->map.size); -+ if (info->map.virt == NULL) { -+ dev_err(&pdev->dev, "failed to ioremap flash region\n"); -+ err = -EIO; -+ goto err_out; ++ if (nvram_parse_mac_addr(config, DIR_615C1_CONFIG_SIZE, ++ "lan_mac=", mac) == 0) { ++ ar71xx_set_mac_base(mac); ++ wlan_mac = mac; + } + -+ simple_map_init(&info->map); -+ if (pdata->is_shared) { -+ info->map.read = ar91xx_flash_read_lock; -+ info->map.write = ar91xx_flash_write_lock; -+ info->map.copy_from = ar91xx_flash_copy_from_lock; -+ info->map.copy_to = ar91xx_flash_copy_to_lock; -+ } else { -+ info->map.read = ar91xx_flash_read; -+ info->map.write = ar91xx_flash_write; -+ } ++ ar71xx_add_device_mdio(DIR_615C1_MDIO_MASK); + -+ probe_type = rom_probe_types; -+ for (; info->mtd == NULL && *probe_type != NULL; probe_type++) -+ info->mtd = do_map_probe(*probe_type, &info->map); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.phy_mask = DIR_615C1_LAN_PHYMASK; + -+ if (info->mtd == NULL) { -+ dev_err(&pdev->dev, "map_probe failed\n"); -+ err = -ENXIO; -+ goto err_out; -+ } ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = DIR_615C1_WAN_PHYMASK; + -+ info->mtd->owner = THIS_MODULE; ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+#ifdef CONFIG_MTD_PARTITIONS -+ if (pdata->nr_parts) { -+ dev_info(&pdev->dev, "using static partition mapping\n"); -+ add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); -+ return 0; -+ } ++ ar71xx_add_device_m25p80(&dir_615c1_flash_data); + -+ err = parse_mtd_partitions(info->mtd, part_probe_types, -+ &info->parts, 0); -+ if (err > 0) { -+ add_mtd_partitions(info->mtd, info->parts, err); -+ return 0; -+ } -+#endif ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir_615c1_leds_gpio), ++ dir_615c1_leds_gpio); + -+ add_mtd_device(info->mtd); -+ return 0; ++ ar71xx_add_device_gpio_buttons(-1, DIR_615C1_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(dir_615c1_gpio_buttons), ++ dir_615c1_gpio_buttons); + -+ err_out: -+ ar91xx_flash_remove(pdev); -+ return err; ++ ar913x_add_device_wmac(eeprom, wlan_mac); +} + -+#ifdef CONFIG_PM -+static int ar91xx_flash_suspend(struct platform_device *dev, pm_message_t state) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(dev); -+ int ret = 0; ++MIPS_MACHINE(AR71XX_MACH_DIR_615_C1, "DIR-615-C1", "D-Link DIR-615 rev. C1", ++ dir_615c1_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-825-b1.c linux-2.6.36/arch/mips/ar71xx/mach-dir-825-b1.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-dir-825-b1.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-dir-825-b1.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,192 @@ ++/* ++ * D-Link DIR-825 rev. B1 board support ++ * ++ * Copyright (C) 2009 Lukas Kuna, Evkanet, s.r.o. ++ * ++ * based on mach-wndr3700.c ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ if (info->mtd->suspend) -+ ret = info->mtd->suspend(info->mtd); ++#include ++#include ++#include ++#include ++#include + -+ if (ret) -+ goto fail; ++#include + -+ return 0; ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap94-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+ fail: -+ if (info->mtd->suspend) { -+ BUG_ON(!info->mtd->resume); -+ info->mtd->resume(info->mtd); -+ } ++#define DIR825B1_GPIO_LED_BLUE_USB 0 ++#define DIR825B1_GPIO_LED_ORANGE_POWER 1 ++#define DIR825B1_GPIO_LED_BLUE_POWER 2 ++#define DIR825B1_GPIO_LED_BLUE_POWERSAVE 4 ++#define DIR825B1_GPIO_LED_ORANGE_PLANET 6 ++#define DIR825B1_GPIO_LED_BLUE_PLANET 11 + -+ return ret; -+} ++#define DIR825B1_GPIO_BTN_RESET 3 ++#define DIR825B1_GPIO_BTN_POWERSAVE 8 + -+static int ar91xx_flash_resume(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); ++#define DIR825B1_GPIO_RTL8366_SDA 5 ++#define DIR825B1_GPIO_RTL8366_SCK 7 + -+ if (info->mtd->resume) -+ info->mtd->resume(info->mtd); ++#define DIR825B1_BUTTONS_POLL_INTERVAL 20 + -+ return 0; -+} ++#define DIR825B1_CAL_LOCATION_0 0x1f661000 ++#define DIR825B1_CAL_LOCATION_1 0x1f665000 + -+static void ar91xx_flash_shutdown(struct platform_device *pdev) -+{ -+ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); ++#define DIR825B1_MAC_LOCATION_0 0x2ffa81b8 ++#define DIR825B1_MAC_LOCATION_1 0x2ffa8370 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition dir825b1_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "config", ++ .offset = 0x040000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x050000, ++ .size = 0x610000, ++ } , { ++ .name = "caldata", ++ .offset = 0x660000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "unknown", ++ .offset = 0x670000, ++ .size = 0x190000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+ if (info->mtd->suspend && info->mtd->resume) -+ if (info->mtd->suspend(info->mtd) == 0) -+ info->mtd->resume(info->mtd); -+} -+#else -+#define ar91xx_flash_suspend NULL -+#define ar91xx_flash_resume NULL -+#define ar91xx_flash_shutdown NULL ++static struct flash_platform_data dir825b1_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = dir825b1_partitions, ++ .nr_parts = ARRAY_SIZE(dir825b1_partitions), +#endif -+ -+static struct platform_driver ar91xx_flash_driver = { -+ .probe = ar91xx_flash_probe, -+ .remove = ar91xx_flash_remove, -+ .suspend = ar91xx_flash_suspend, -+ .resume = ar91xx_flash_resume, -+ .shutdown = ar91xx_flash_shutdown, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, +}; + -+static int __init ar91xx_flash_init(void) -+{ -+ return platform_driver_register(&ar91xx_flash_driver); -+} -+ -+static void __exit ar91xx_flash_exit(void) -+{ -+ platform_driver_unregister(&ar91xx_flash_driver); -+} ++static struct gpio_led dir825b1_leds_gpio[] __initdata = { ++ { ++ .name = "dir825b1:blue:usb", ++ .gpio = DIR825B1_GPIO_LED_BLUE_USB, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:orange:power", ++ .gpio = DIR825B1_GPIO_LED_ORANGE_POWER, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:blue:power", ++ .gpio = DIR825B1_GPIO_LED_BLUE_POWER, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:blue:powersave", ++ .gpio = DIR825B1_GPIO_LED_BLUE_POWERSAVE, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:orange:planet", ++ .gpio = DIR825B1_GPIO_LED_ORANGE_PLANET, ++ .active_low = 1, ++ }, { ++ .name = "dir825b1:blue:planet", ++ .gpio = DIR825B1_GPIO_LED_BLUE_PLANET, ++ .active_low = 1, ++ } ++}; + -+module_init(ar91xx_flash_init); -+module_exit(ar91xx_flash_exit); ++static struct gpio_button dir825b1_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = DIR825B1_GPIO_BTN_RESET, ++ .active_low = 1, ++ } , { ++ .desc = "powersave", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .threshold = 3, ++ .gpio = DIR825B1_GPIO_BTN_POWERSAVE, ++ .active_low = 1, ++ } ++}; + -+MODULE_LICENSE("GPL v2"); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_DESCRIPTION("Parallel flash driver for the Atheros AR91xx SoC"); -+MODULE_ALIAS("platform:" DRV_NAME); -diff -Nur linux-2.6.35.7.orig/drivers/mtd/maps/Kconfig linux-2.6.35.7/drivers/mtd/maps/Kconfig ---- linux-2.6.35.7.orig/drivers/mtd/maps/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/mtd/maps/Kconfig 2010-10-14 20:28:00.198101134 +0200 -@@ -251,6 +251,13 @@ - help - Support for flash chips on NETtel/SecureEdge/SnapGear boards. - -+config MTD_AR91XX_FLASH -+ tristate "Atheros AR91xx parallel flash support" -+ depends on ATHEROS_AR71XX -+ select MTD_COMPLEX_MAPPINGS -+ help -+ Parallel flash driver for the Atheros AR91xx based boards. ++static struct rtl8366s_platform_data dir825b1_rtl8366s_data = { ++ .gpio_sda = DIR825B1_GPIO_RTL8366_SDA, ++ .gpio_sck = DIR825B1_GPIO_RTL8366_SCK, ++}; + - config MTD_DILNETPC - tristate "CFI Flash device mapped on DIL/Net PC" - depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN -diff -Nur linux-2.6.35.7.orig/drivers/mtd/maps/Makefile linux-2.6.35.7/drivers/mtd/maps/Makefile ---- linux-2.6.35.7.orig/drivers/mtd/maps/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/mtd/maps/Makefile 2010-10-14 20:28:00.238101165 +0200 -@@ -7,6 +7,7 @@ - endif - - # Chip mappings -+obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o - obj-$(CONFIG_MTD_CDB89712) += cdb89712.o - obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o - obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o -diff -Nur linux-2.6.35.7.orig/drivers/mtd/nand/Kconfig linux-2.6.35.7/drivers/mtd/nand/Kconfig ---- linux-2.6.35.7.orig/drivers/mtd/nand/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/mtd/nand/Kconfig 2010-10-14 20:28:00.288101273 +0200 -@@ -526,4 +526,8 @@ - This enables the driver for the NAND Flash on evaluation board based - on w90p910 / NUC9xx. - -+config MTD_NAND_RB4XX -+ tristate "NAND flash driver for RouterBoard 4xx series" -+ depends on MTD_NAND && AR71XX_MACH_RB4XX ++static struct platform_device dir825b1_rtl8366s_device = { ++ .name = RTL8366S_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &dir825b1_rtl8366s_data, ++ } ++}; + - endif # MTD_NAND -diff -Nur linux-2.6.35.7.orig/drivers/mtd/nand/Kconfig.orig linux-2.6.35.7/drivers/mtd/nand/Kconfig.orig ---- linux-2.6.35.7.orig/drivers/mtd/nand/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/mtd/nand/Kconfig.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,529 @@ -+config MTD_NAND_ECC -+ tristate -+ -+config MTD_NAND_ECC_SMC -+ bool "NAND ECC Smart Media byte order" -+ depends on MTD_NAND_ECC -+ default n -+ help -+ Software ECC according to the Smart Media Specification. -+ The original Linux implementation had byte 0 and 1 swapped. ++static void __init dir825b1_setup(void) ++{ ++ u8 mac[6], i; + ++ memcpy(mac, (u8*)KSEG1ADDR(DIR825B1_MAC_LOCATION_1), 6); ++ for(i = 5; i >= 3; i--) ++ if(++mac[i] != 0x00) break; + -+menuconfig MTD_NAND -+ tristate "NAND Device Support" -+ depends on MTD -+ select MTD_NAND_IDS -+ select MTD_NAND_ECC -+ help -+ This enables support for accessing all type of NAND flash -+ devices. For further information see -+ . ++ ar71xx_set_mac_base(mac); + -+if MTD_NAND ++ ar71xx_add_device_mdio(0x0); + -+config MTD_NAND_VERIFY_WRITE -+ bool "Verify NAND page writes" -+ help -+ This adds an extra check when data is written to the flash. The -+ NAND flash device internally checks only bits transitioning -+ from 1 to 0. There is a rare possibility that even though the -+ device thinks the write was successful, a bit could have been -+ flipped accidentally due to device wear or something else. -+ -+config MTD_SM_COMMON -+ tristate -+ default n ++ ar71xx_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; + -+config MTD_NAND_MUSEUM_IDS -+ bool "Enable chip ids for obsolete ancient NAND devices" -+ depends on MTD_NAND -+ default n -+ help -+ Enable this option only when your board has first generation -+ NAND chips (page size 256 byte, erase size 4-8KiB). The IDs -+ of these chips were reused by later, larger chips. ++ ar71xx_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = 0x10; ++ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; + -+config MTD_NAND_AUTCPU12 -+ tristate "SmartMediaCard on autronix autcpu12 board" -+ depends on ARCH_AUTCPU12 -+ help -+ This enables the driver for the autronix autcpu12 board to -+ access the SmartMediaCard. -+ -+config MTD_NAND_DENALI -+ depends on PCI -+ tristate "Support Denali NAND controller on Intel Moorestown" -+ help -+ Enable the driver for NAND flash on Intel Moorestown, using the -+ Denali NAND controller core. -+ -+config MTD_NAND_DENALI_SCRATCH_REG_ADDR -+ hex "Denali NAND size scratch register address" -+ default "0xFF108018" -+ help -+ Some platforms place the NAND chip size in a scratch register -+ because (some versions of) the driver aren't able to automatically -+ determine the size of certain chips. Set the address of the -+ scratch register here to enable this feature. On Intel Moorestown -+ boards, the scratch register is at 0xFF108018. -+ -+config MTD_NAND_EDB7312 -+ tristate "Support for Cirrus Logic EBD7312 evaluation board" -+ depends on ARCH_EDB7312 -+ help -+ This enables the driver for the Cirrus Logic EBD7312 evaluation -+ board to access the onboard NAND Flash. ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+config MTD_NAND_H1900 -+ tristate "iPAQ H1900 flash" -+ depends on ARCH_PXA && MTD_PARTITIONS -+ help -+ This enables the driver for the iPAQ h1900 flash. ++ ar71xx_add_device_m25p80(&dir825b1_flash_data); + -+config MTD_NAND_GPIO -+ tristate "GPIO NAND Flash driver" -+ depends on GENERIC_GPIO && ARM -+ help -+ This enables a GPIO based NAND flash driver. ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio), ++ dir825b1_leds_gpio); + -+config MTD_NAND_SPIA -+ tristate "NAND Flash device on SPIA board" -+ depends on ARCH_P720T -+ help -+ If you had to ask, you don't have one. Say 'N'. ++ ar71xx_add_device_gpio_buttons(-1, DIR825B1_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(dir825b1_gpio_buttons), ++ dir825b1_gpio_buttons); + -+config MTD_NAND_AMS_DELTA -+ tristate "NAND Flash device on Amstrad E3" -+ depends on MACH_AMS_DELTA -+ help -+ Support for NAND flash on Amstrad E3 (Delta). ++ ar71xx_add_device_usb(); + -+config MTD_NAND_OMAP2 -+ tristate "NAND Flash device on OMAP2 and OMAP3" -+ depends on ARM && MTD_NAND && (ARCH_OMAP2 || ARCH_OMAP3) -+ help -+ Support for NAND flash on Texas Instruments OMAP2 and OMAP3 platforms. ++ platform_device_register(&dir825b1_rtl8366s_device); + -+config MTD_NAND_OMAP_PREFETCH -+ bool "GPMC prefetch support for NAND Flash device" -+ depends on MTD_NAND && MTD_NAND_OMAP2 -+ default y -+ help -+ The NAND device can be accessed for Read/Write using GPMC PREFETCH engine -+ to improve the performance. ++ ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), ++ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_0), ++ (u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), ++ (u8 *) KSEG1ADDR(DIR825B1_MAC_LOCATION_1)); ++} + -+config MTD_NAND_OMAP_PREFETCH_DMA -+ depends on MTD_NAND_OMAP_PREFETCH -+ bool "DMA mode" -+ default n -+ help -+ The GPMC PREFETCH engine can be configured eigther in MPU interrupt mode -+ or in DMA interrupt mode. -+ Say y for DMA mode or MPU mode will be used ++MIPS_MACHINE(AR71XX_MACH_DIR_825_B1, "DIR-825-B1", "D-Link DIR-825 rev. B1", ++ dir825b1_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-mzk-w04nu.c linux-2.6.36/arch/mips/ar71xx/mach-mzk-w04nu.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-mzk-w04nu.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-mzk-w04nu.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,165 @@ ++/* ++ * Planex MZK-W04NU board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+config MTD_NAND_IDS -+ tristate ++#include ++#include + -+config MTD_NAND_RICOH -+ tristate "Ricoh xD card reader" -+ default n -+ depends on PCI -+ select MTD_SM_COMMON -+ help -+ Enable support for Ricoh R5C852 xD card reader -+ You also need to enable ether -+ NAND SSFDC (SmartMedia) read only translation layer' or new -+ expermental, readwrite -+ 'SmartMedia/xD new translation layer' -+ -+config MTD_NAND_AU1550 -+ tristate "Au1550/1200 NAND support" -+ depends on SOC_AU1200 || SOC_AU1550 -+ help -+ This enables the driver for the NAND flash controller on the -+ AMD/Alchemy 1550 SOC. ++#include + -+config MTD_NAND_BF5XX -+ tristate "Blackfin on-chip NAND Flash Controller driver" -+ depends on (BF54x || BF52x) && MTD_NAND -+ help -+ This enables the Blackfin on-chip NAND flash controller ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-m25p80.h" ++#include "dev-usb.h" + -+ No board specific support is done by this driver, each board -+ must advertise a platform_device for the driver to attach. ++#define MZK_W04NU_GPIO_LED_USB 0 ++#define MZK_W04NU_GPIO_LED_STATUS 1 ++#define MZK_W04NU_GPIO_LED_WPS 3 ++#define MZK_W04NU_GPIO_LED_WLAN 6 ++#define MZK_W04NU_GPIO_LED_AP 15 ++#define MZK_W04NU_GPIO_LED_ROUTER 16 + -+ This driver can also be built as a module. If so, the module -+ will be called bf5xx-nand. ++#define MZK_W04NU_GPIO_BTN_APROUTER 5 ++#define MZK_W04NU_GPIO_BTN_WPS 12 ++#define MZK_W04NU_GPIO_BTN_RESET 21 + -+config MTD_NAND_BF5XX_HWECC -+ bool "BF5XX NAND Hardware ECC" -+ default y -+ depends on MTD_NAND_BF5XX -+ help -+ Enable the use of the BF5XX's internal ECC generator when -+ using NAND. ++#define MZK_W04NU_BUTTONS_POLL_INTERVAL 20 + -+config MTD_NAND_BF5XX_BOOTROM_ECC -+ bool "Use Blackfin BootROM ECC Layout" -+ default n -+ depends on MTD_NAND_BF5XX_HWECC -+ help -+ If you wish to modify NAND pages and allow the Blackfin on-chip -+ BootROM to boot from them, say Y here. This is only necessary -+ if you are booting U-Boot out of NAND and you wish to update -+ U-Boot from Linux' userspace. Otherwise, you should say N here. -+ -+ If unsure, say N. -+ -+config MTD_NAND_RTC_FROM4 -+ tristate "Renesas Flash ROM 4-slot interface board (FROM_BOARD4)" -+ depends on SH_SOLUTION_ENGINE -+ select REED_SOLOMON -+ select REED_SOLOMON_DEC8 -+ select BITREVERSE -+ help -+ This enables the driver for the Renesas Technology AG-AND -+ flash interface board (FROM_BOARD4) ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition mzk_w04nu_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ } , { ++ .name = "kernel", ++ .offset = 0x050000, ++ .size = 0x160000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x1b0000, ++ .size = 0x630000, ++ } , { ++ .name = "art", ++ .offset = 0x7e0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x050000, ++ .size = 0x790000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+config MTD_NAND_PPCHAMELEONEVB -+ tristate "NAND Flash device on PPChameleonEVB board" -+ depends on PPCHAMELEONEVB && BROKEN -+ help -+ This enables the NAND flash driver on the PPChameleon EVB Board. ++static struct flash_platform_data mzk_w04nu_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = mzk_w04nu_partitions, ++ .nr_parts = ARRAY_SIZE(mzk_w04nu_partitions), ++#endif ++}; + -+config MTD_NAND_S3C2410 -+ tristate "NAND Flash support for Samsung S3C SoCs" -+ depends on ARCH_S3C2410 || ARCH_S3C64XX -+ help -+ This enables the NAND flash controller on the S3C24xx and S3C64xx -+ SoCs ++static struct gpio_led mzk_w04nu_leds_gpio[] __initdata = { ++ { ++ .name = "mzk-w04nu:green:status", ++ .gpio = MZK_W04NU_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:blue:wps", ++ .gpio = MZK_W04NU_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:green:wlan", ++ .gpio = MZK_W04NU_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:green:usb", ++ .gpio = MZK_W04NU_GPIO_LED_USB, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:green:ap", ++ .gpio = MZK_W04NU_GPIO_LED_AP, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w04nu:green:router", ++ .gpio = MZK_W04NU_GPIO_LED_ROUTER, ++ .active_low = 1, ++ } ++}; + -+ No board specific support is done by this driver, each board -+ must advertise a platform_device for the driver to attach. ++static struct gpio_button mzk_w04nu_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = MZK_W04NU_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = MZK_W04NU_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, { ++ .desc = "aprouter", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .threshold = 3, ++ .gpio = MZK_W04NU_GPIO_BTN_APROUTER, ++ .active_low = 0, ++ } ++}; + -+config MTD_NAND_S3C2410_DEBUG -+ bool "Samsung S3C NAND driver debug" -+ depends on MTD_NAND_S3C2410 -+ help -+ Enable debugging of the S3C NAND driver ++#define MZK_W04NU_WAN_PHYMASK BIT(4) ++#define MZK_W04NU_MDIO_MASK (~MZK_W04NU_WAN_PHYMASK) + -+config MTD_NAND_S3C2410_HWECC -+ bool "Samsung S3C NAND Hardware ECC" -+ depends on MTD_NAND_S3C2410 -+ help -+ Enable the use of the controller's internal ECC generator when -+ using NAND. Early versions of the chips have had problems with -+ incorrect ECC generation, and if using these, the default of -+ software ECC is preferable. -+ -+config MTD_NAND_NDFC -+ tristate "NDFC NanD Flash Controller" -+ depends on 4xx -+ select MTD_NAND_ECC_SMC -+ help -+ NDFC Nand Flash Controllers are integrated in IBM/AMCC's 4xx SoCs ++static void __init mzk_w04nu_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+config MTD_NAND_S3C2410_CLKSTOP -+ bool "Samsung S3C NAND IDLE clock stop" -+ depends on MTD_NAND_S3C2410 -+ default n -+ help -+ Stop the clock to the NAND controller when there is no chip -+ selected to save power. This will mean there is a small delay -+ when the is NAND chip selected or released, but will save -+ approximately 5mA of power when there is nothing happening. -+ -+config MTD_NAND_BCM_UMI -+ tristate "NAND Flash support for BCM Reference Boards" -+ depends on ARCH_BCMRING && MTD_NAND -+ help -+ This enables the NAND flash controller on the BCM UMI block. ++ ar71xx_set_mac_base(eeprom); + -+ No board specfic support is done by this driver, each board -+ must advertise a platform_device for the driver to attach. ++ ar71xx_add_device_mdio(MZK_W04NU_MDIO_MASK); + -+config MTD_NAND_BCM_UMI_HWCS -+ bool "BCM UMI NAND Hardware CS" -+ depends on MTD_NAND_BCM_UMI -+ help -+ Enable the use of the BCM UMI block's internal CS using NAND. -+ This should only be used if you know the external NAND CS can toggle. -+ -+config MTD_NAND_DISKONCHIP -+ tristate "DiskOnChip 2000, Millennium and Millennium Plus (NAND reimplementation) (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ select REED_SOLOMON -+ select REED_SOLOMON_DEC16 -+ help -+ This is a reimplementation of M-Systems DiskOnChip 2000, -+ Millennium and Millennium Plus as a standard NAND device driver, -+ as opposed to the earlier self-contained MTD device drivers. -+ This should enable, among other things, proper JFFS2 operation on -+ these devices. -+ -+config MTD_NAND_DISKONCHIP_PROBE_ADVANCED -+ bool "Advanced detection options for DiskOnChip" -+ depends on MTD_NAND_DISKONCHIP -+ help -+ This option allows you to specify nonstandard address at which to -+ probe for a DiskOnChip, or to change the detection options. You -+ are unlikely to need any of this unless you are using LinuxBIOS. -+ Say 'N'. -+ -+config MTD_NAND_DISKONCHIP_PROBE_ADDRESS -+ hex "Physical address of DiskOnChip" if MTD_NAND_DISKONCHIP_PROBE_ADVANCED -+ depends on MTD_NAND_DISKONCHIP -+ default "0" -+ ---help--- -+ By default, the probe for DiskOnChip devices will look for a -+ DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000. -+ This option allows you to specify a single address at which to probe -+ for the device, which is useful if you have other devices in that -+ range which get upset when they are probed. -+ -+ (Note that on PowerPC, the normal probe will only check at -+ 0xE4000000.) -+ -+ Normally, you should leave this set to zero, to allow the probe at -+ the normal addresses. -+ -+config MTD_NAND_DISKONCHIP_PROBE_HIGH -+ bool "Probe high addresses" -+ depends on MTD_NAND_DISKONCHIP_PROBE_ADVANCED -+ help -+ By default, the probe for DiskOnChip devices will look for a -+ DiskOnChip at every multiple of 0x2000 between 0xC8000 and 0xEE000. -+ This option changes to make it probe between 0xFFFC8000 and -+ 0xFFFEE000. Unless you are using LinuxBIOS, this is unlikely to be -+ useful to you. Say 'N'. -+ -+config MTD_NAND_DISKONCHIP_BBTWRITE -+ bool "Allow BBT writes on DiskOnChip Millennium and 2000TSOP" -+ depends on MTD_NAND_DISKONCHIP -+ help -+ On DiskOnChip devices shipped with the INFTL filesystem (Millennium -+ and 2000 TSOP/Alon), Linux reserves some space at the end of the -+ device for the Bad Block Table (BBT). If you have existing INFTL -+ data on your device (created by non-Linux tools such as M-Systems' -+ DOS drivers), your data might overlap the area Linux wants to use for -+ the BBT. If this is a concern for you, leave this option disabled and -+ Linux will not write BBT data into this area. -+ The downside of leaving this option disabled is that if bad blocks -+ are detected by Linux, they will not be recorded in the BBT, which -+ could cause future problems. -+ Once you enable this option, new filesystems (INFTL or others, created -+ in Linux or other operating systems) will not use the reserved area. -+ The only reason not to enable this option is to prevent damage to -+ preexisting filesystems. -+ Even if you leave this disabled, you can enable BBT writes at module -+ load time (assuming you build diskonchip as a module) with the module -+ parameter "inftl_bbt_write=1". -+ -+config MTD_NAND_SHARPSL -+ tristate "Support for NAND Flash on Sharp SL Series (C7xx + others)" -+ depends on ARCH_PXA -+ -+config MTD_NAND_CAFE -+ tristate "NAND support for OLPC CAFÉ chip" -+ depends on PCI -+ select REED_SOLOMON -+ select REED_SOLOMON_DEC16 -+ help -+ Use NAND flash attached to the CAFÉ chip designed for the OLPC -+ laptop. ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; + -+config MTD_NAND_CS553X -+ tristate "NAND support for CS5535/CS5536 (AMD Geode companion chip)" -+ depends on X86_32 -+ help -+ The CS553x companion chips for the AMD Geode processor -+ include NAND flash controllers with built-in hardware ECC -+ capabilities; enabling this option will allow you to use -+ these. The driver will check the MSRs to verify that the -+ controller is enabled for NAND, and currently requires that -+ the controller be in MMIO mode. -+ -+ If you say "m", the module will be called cs553x_nand. -+ -+config MTD_NAND_ATMEL -+ tristate "Support for NAND Flash / SmartMedia on AT91 and AVR32" -+ depends on ARCH_AT91 || AVR32 -+ help -+ Enables support for NAND Flash / Smart Media Card interface -+ on Atmel AT91 and AVR32 processors. -+choice -+ prompt "ECC management for NAND Flash / SmartMedia on AT91 / AVR32" -+ depends on MTD_NAND_ATMEL -+ -+config MTD_NAND_ATMEL_ECC_HW -+ bool "Hardware ECC" -+ depends on ARCH_AT91SAM9263 || ARCH_AT91SAM9260 || AVR32 -+ help -+ Use hardware ECC instead of software ECC when the chip -+ supports it. ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = MZK_W04NU_WAN_PHYMASK; + -+ The hardware ECC controller is capable of single bit error -+ correction and 2-bit random detection per page. ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ NB : hardware and software ECC schemes are incompatible. -+ If you switch from one to another, you'll have to erase your -+ mtd partition. ++ ar71xx_add_device_m25p80(&mzk_w04nu_flash_data); + -+ If unsure, say Y ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w04nu_leds_gpio), ++ mzk_w04nu_leds_gpio); + -+config MTD_NAND_ATMEL_ECC_SOFT -+ bool "Software ECC" -+ help -+ Use software ECC. ++ ar71xx_add_device_gpio_buttons(-1, MZK_W04NU_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(mzk_w04nu_gpio_buttons), ++ mzk_w04nu_gpio_buttons); ++ ar71xx_add_device_usb(); + -+ NB : hardware and software ECC schemes are incompatible. -+ If you switch from one to another, you'll have to erase your -+ mtd partition. ++ ar913x_add_device_wmac(eeprom, NULL); ++} + -+config MTD_NAND_ATMEL_ECC_NONE -+ bool "No ECC (testing only, DANGEROUS)" -+ depends on DEBUG_KERNEL -+ help -+ No ECC will be used. -+ It's not a good idea and it should be reserved for testing -+ purpose only. ++MIPS_MACHINE(AR71XX_MACH_MZK_W04NU, "MZK-W04NU", "Planex MZK-W04NU", ++ mzk_w04nu_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-mzk-w300nh.c linux-2.6.36/arch/mips/ar71xx/mach-mzk-w300nh.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-mzk-w300nh.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-mzk-w300nh.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,158 @@ ++/* ++ * Planex MZK-W300NH board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ If unsure, say N ++#include ++#include + -+endchoice ++#include + -+config MTD_NAND_PXA3xx -+ tristate "Support for NAND flash devices on PXA3xx" -+ depends on MTD_NAND && (PXA3xx || ARCH_MMP) -+ help -+ This enables the driver for the NAND flash device found on -+ PXA3xx processors ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" + -+config MTD_NAND_PXA3xx_BUILTIN -+ bool "Use builtin definitions for some NAND chips (deprecated)" -+ depends on MTD_NAND_PXA3xx -+ help -+ This enables builtin definitions for some NAND chips. This -+ is deprecated in favor of platform specific data. ++#define MZK_W300NH_GPIO_LED_STATUS 1 ++#define MZK_W300NH_GPIO_LED_WPS 3 ++#define MZK_W300NH_GPIO_LED_WLAN 6 ++#define MZK_W300NH_GPIO_LED_AP 15 ++#define MZK_W300NH_GPIO_LED_ROUTER 16 + -+config MTD_NAND_CM_X270 -+ tristate "Support for NAND Flash on CM-X270 modules" -+ depends on MTD_NAND && MACH_ARMCORE ++#define MZK_W300NH_GPIO_BTN_APROUTER 5 ++#define MZK_W300NH_GPIO_BTN_WPS 12 ++#define MZK_W300NH_GPIO_BTN_RESET 21 + -+config MTD_NAND_PASEMI -+ tristate "NAND support for PA Semi PWRficient" -+ depends on MTD_NAND && PPC_PASEMI -+ help -+ Enables support for NAND Flash interface on PA Semi PWRficient -+ based boards ++#define MZK_W04NU_BUTTONS_POLL_INTERVAL 20 + -+config MTD_NAND_TMIO -+ tristate "NAND Flash device on Toshiba Mobile IO Controller" -+ depends on MTD_NAND && MFD_TMIO -+ help -+ Support for NAND flash connected to a Toshiba Mobile IO -+ Controller in some PDAs, including the Sharp SL6000x. ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition mzk_w300nh_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ } , { ++ .name = "kernel", ++ .offset = 0x050000, ++ .size = 0x160000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x1b0000, ++ .size = 0x630000, ++ } , { ++ .name = "art", ++ .offset = 0x7e0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x050000, ++ .size = 0x790000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+config MTD_NAND_NANDSIM -+ tristate "Support for NAND Flash Simulator" -+ depends on MTD_PARTITIONS -+ help -+ The simulator may simulate various NAND flash chips for the -+ MTD nand layer. ++static struct flash_platform_data mzk_w300nh_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = mzk_w300nh_partitions, ++ .nr_parts = ARRAY_SIZE(mzk_w300nh_partitions), ++#endif ++}; + -+config MTD_NAND_PLATFORM -+ tristate "Support for generic platform NAND driver" -+ depends on MTD_NAND -+ help -+ This implements a generic NAND driver for on-SOC platform -+ devices. You will need to provide platform-specific functions -+ via platform_data. ++static struct gpio_led mzk_w300nh_leds_gpio[] __initdata = { ++ { ++ .name = "mzk-w300nh:green:status", ++ .gpio = MZK_W300NH_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w300nh:blue:wps", ++ .gpio = MZK_W300NH_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w300nh:green:wlan", ++ .gpio = MZK_W300NH_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w300nh:green:ap", ++ .gpio = MZK_W300NH_GPIO_LED_AP, ++ .active_low = 1, ++ }, { ++ .name = "mzk-w300nh:green:router", ++ .gpio = MZK_W300NH_GPIO_LED_ROUTER, ++ .active_low = 1, ++ } ++}; + -+config MTD_ALAUDA -+ tristate "MTD driver for Olympus MAUSB-10 and Fujifilm DPC-R1" -+ depends on MTD_NAND && USB -+ help -+ These two (and possibly other) Alauda-based cardreaders for -+ SmartMedia and xD allow raw flash access. ++static struct gpio_button mzk_w300nh_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = MZK_W300NH_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = MZK_W300NH_GPIO_BTN_WPS, ++ .active_low = 1, ++ }, { ++ .desc = "aprouter", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .threshold = 3, ++ .gpio = MZK_W300NH_GPIO_BTN_APROUTER, ++ .active_low = 0, ++ } ++}; + -+config MTD_NAND_ORION -+ tristate "NAND Flash support for Marvell Orion SoC" -+ depends on PLAT_ORION && MTD_NAND -+ help -+ This enables the NAND flash controller on Orion machines. ++#define MZK_W300NH_WAN_PHYMASK BIT(4) ++#define MZK_W300NH_MDIO_MASK (~MZK_W300NH_WAN_PHYMASK) + -+ No board specific support is done by this driver, each board -+ must advertise a platform_device for the driver to attach. ++static void __init mzk_w300nh_setup(void) ++{ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+config MTD_NAND_FSL_ELBC -+ tristate "NAND support for Freescale eLBC controllers" -+ depends on MTD_NAND && PPC_OF -+ help -+ Various Freescale chips, including the 8313, include a NAND Flash -+ Controller Module with built-in hardware ECC capabilities. -+ Enabling this option will enable you to use this to control -+ external NAND devices. -+ -+config MTD_NAND_FSL_UPM -+ tristate "Support for NAND on Freescale UPM" -+ depends on MTD_NAND && (PPC_83xx || PPC_85xx) -+ select FSL_LBC -+ help -+ Enables support for NAND Flash chips wired onto Freescale PowerPC -+ processor localbus with User-Programmable Machine support. ++ ar71xx_set_mac_base(eeprom); + -+config MTD_NAND_MPC5121_NFC -+ tristate "MPC5121 built-in NAND Flash Controller support" -+ depends on PPC_MPC512x -+ help -+ This enables the driver for the NAND flash controller on the -+ MPC5121 SoC. ++ ar71xx_add_device_mdio(MZK_W300NH_MDIO_MASK); + -+config MTD_NAND_MXC -+ tristate "MXC NAND support" -+ depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 -+ help -+ This enables the driver for the NAND flash controller on the -+ MXC processors. ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; + -+config MTD_NAND_NOMADIK -+ tristate "ST Nomadik 8815 NAND support" -+ depends on ARCH_NOMADIK -+ help -+ Driver for the NAND flash controller on the Nomadik, with ECC. ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = MZK_W300NH_WAN_PHYMASK; + -+config MTD_NAND_SH_FLCTL -+ tristate "Support for NAND on Renesas SuperH FLCTL" -+ depends on MTD_NAND && (SUPERH || ARCH_SHMOBILE) -+ help -+ Several Renesas SuperH CPU has FLCTL. This option enables support -+ for NAND Flash using FLCTL. -+ -+config MTD_NAND_DAVINCI -+ tristate "Support NAND on DaVinci SoC" -+ depends on ARCH_DAVINCI -+ help -+ Enable the driver for NAND flash chips on Texas Instruments -+ DaVinci processors. -+ -+config MTD_NAND_TXX9NDFMC -+ tristate "NAND Flash support for TXx9 SoC" -+ depends on SOC_TX4938 || SOC_TX4939 -+ help -+ This enables the NAND flash controller on the TXx9 SoCs. ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+config MTD_NAND_SOCRATES -+ tristate "Support for NAND on Socrates board" -+ depends on MTD_NAND && SOCRATES -+ help -+ Enables support for NAND Flash chips wired onto Socrates board. ++ ar71xx_add_device_m25p80(&mzk_w300nh_flash_data); + -+config MTD_NAND_NUC900 -+ tristate "Support for NAND on Nuvoton NUC9xx/w90p910 evaluation boards." -+ depends on ARCH_W90X900 && MTD_PARTITIONS -+ help -+ This enables the driver for the NAND Flash on evaluation board based -+ on w90p910 / NUC9xx. ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(mzk_w300nh_leds_gpio), ++ mzk_w300nh_leds_gpio); + -+endif # MTD_NAND -diff -Nur linux-2.6.35.7.orig/drivers/mtd/nand/Makefile linux-2.6.35.7/drivers/mtd/nand/Makefile ---- linux-2.6.35.7.orig/drivers/mtd/nand/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/mtd/nand/Makefile 2010-10-14 20:28:00.318093945 +0200 -@@ -32,6 +32,7 @@ - obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o - obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o - obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o - obj-$(CONFIG_MTD_ALAUDA) += alauda.o - obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o - obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o -diff -Nur linux-2.6.35.7.orig/drivers/mtd/nand/Makefile.orig linux-2.6.35.7/drivers/mtd/nand/Makefile.orig ---- linux-2.6.35.7.orig/drivers/mtd/nand/Makefile.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/mtd/nand/Makefile.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,50 @@ -+# -+# linux/drivers/nand/Makefile -+# ++ ar71xx_add_device_gpio_buttons(-1, MZK_W04NU_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(mzk_w300nh_gpio_buttons), ++ mzk_w300nh_gpio_buttons); ++ ar913x_add_device_wmac(eeprom, NULL); ++} + -+obj-$(CONFIG_MTD_NAND) += nand.o -+obj-$(CONFIG_MTD_NAND_ECC) += nand_ecc.o -+obj-$(CONFIG_MTD_NAND_IDS) += nand_ids.o -+obj-$(CONFIG_MTD_SM_COMMON) += sm_common.o -+ -+obj-$(CONFIG_MTD_NAND_CAFE) += cafe_nand.o -+obj-$(CONFIG_MTD_NAND_SPIA) += spia.o -+obj-$(CONFIG_MTD_NAND_AMS_DELTA) += ams-delta.o -+obj-$(CONFIG_MTD_NAND_AUTCPU12) += autcpu12.o -+obj-$(CONFIG_MTD_NAND_DENALI) += denali.o -+obj-$(CONFIG_MTD_NAND_EDB7312) += edb7312.o -+obj-$(CONFIG_MTD_NAND_AU1550) += au1550nd.o -+obj-$(CONFIG_MTD_NAND_BF5XX) += bf5xx_nand.o -+obj-$(CONFIG_MTD_NAND_PPCHAMELEONEVB) += ppchameleonevb.o -+obj-$(CONFIG_MTD_NAND_S3C2410) += s3c2410.o -+obj-$(CONFIG_MTD_NAND_DAVINCI) += davinci_nand.o -+obj-$(CONFIG_MTD_NAND_DISKONCHIP) += diskonchip.o -+obj-$(CONFIG_MTD_NAND_H1900) += h1910.o -+obj-$(CONFIG_MTD_NAND_RTC_FROM4) += rtc_from4.o -+obj-$(CONFIG_MTD_NAND_SHARPSL) += sharpsl.o -+obj-$(CONFIG_MTD_NAND_NANDSIM) += nandsim.o -+obj-$(CONFIG_MTD_NAND_CS553X) += cs553x_nand.o -+obj-$(CONFIG_MTD_NAND_NDFC) += ndfc.o -+obj-$(CONFIG_MTD_NAND_ATMEL) += atmel_nand.o -+obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o -+obj-$(CONFIG_MTD_NAND_OMAP2) += omap2.o -+obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o -+obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o -+obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o -+obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o -+obj-$(CONFIG_MTD_ALAUDA) += alauda.o -+obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o -+obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o -+obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o -+obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o -+obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o -+obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o -+obj-$(CONFIG_MTD_NAND_SOCRATES) += socrates_nand.o -+obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o -+obj-$(CONFIG_MTD_NAND_NUC900) += nuc900_nand.o -+obj-$(CONFIG_MTD_NAND_NOMADIK) += nomadik_nand.o -+obj-$(CONFIG_MTD_NAND_BCM_UMI) += bcm_umi_nand.o nand_bcm_umi.o -+obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o -+obj-$(CONFIG_MTD_NAND_RICOH) += r852.o -+ -+nand-objs := nand_base.o nand_bbt.o -diff -Nur linux-2.6.35.7.orig/drivers/mtd/nand/rb4xx_nand.c linux-2.6.35.7/drivers/mtd/nand/rb4xx_nand.c ---- linux-2.6.35.7.orig/drivers/mtd/nand/rb4xx_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/mtd/nand/rb4xx_nand.c 2010-10-14 20:28:34.515600563 +0200 -@@ -0,0 +1,513 @@ ++MIPS_MACHINE(AR71XX_MACH_MZK_W300NH, "MZK-W300NH", "Planex MZK-W300NH", ++ mzk_w300nh_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-nbg460n.c linux-2.6.36/arch/mips/ar71xx/mach-nbg460n.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-nbg460n.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-nbg460n.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,222 @@ +/* -+ * NAND flash driver for the MikroTik RouterBoard 4xx series ++ * Zyxel NBG 460N/550N/550NH board support + * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz ++ * Copyright (C) 2010 Michael Kurz + * -+ * This file was based on the driver for Linux 2.6.22 published by -+ * MikroTik for their RouterBoard 4xx series devices. ++ * based on mach-tl-wr1043nd.c + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include -+#include ++#include +#include +#include -+#include +#include -+#include -+#include -+#include -+ -+#include -+ -+#define DRV_NAME "rb4xx-nand" -+#define DRV_VERSION "0.1.10" -+#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" -+ -+#define USE_FAST_READ 1 -+#define USE_FAST_WRITE 1 -+#undef RB4XX_NAND_DEBUG -+ -+#ifdef RB4XX_NAND_DEBUG -+#define DBG(fmt, arg...) printk(KERN_DEBUG DRV_NAME ": " fmt, ## arg) -+#else -+#define DBG(fmt, arg...) do {} while (0) -+#endif ++#include + -+#define RB4XX_NAND_GPIO_RDY 5 -+#define RB4XX_FLASH_HZ 33333334 -+#define RB4XX_NAND_HZ 33333334 ++#include ++#include ++#include + -+#define SPI_CTRL_FASTEST 0x40 -+#define SPI_CTRL_SAFE 0x43 /* 25 MHz for AHB 200 MHz */ -+#define SBIT_IOC_BASE SPI_IOC_CS1 -+#define SBIT_IOC_DO_SHIFT 0 -+#define SBIT_IOC_DO (1u << SBIT_IOC_DO_SHIFT) -+#define SBIT_IOC_DO2_SHIFT 18 -+#define SBIT_IOC_DO2 (1u << SBIT_IOC_DO2_SHIFT) ++#include + -+#define CPLD_CMD_WRITE_MULT 0x08 /* send cmd, n x send data, read data */ -+#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ -+#define CPLD_CMD_READ_MULT 0x0a /* send cmd, send idle, n x read data */ -+#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" + -+#define CFG_BIT_nCE 0x80 -+#define CFG_BIT_CLE 0x40 -+#define CFG_BIT_ALE 0x20 -+#define CFG_BIT_FAN 0x10 -+#define CFG_BIT_nLED4 0x08 -+#define CFG_BIT_nLED3 0x04 -+#define CFG_BIT_nLED2 0x02 -+#define CFG_BIT_nLED1 0x01 ++/* LEDs */ ++#define NBG460N_GPIO_LED_WPS 3 ++#define NBG460N_GPIO_LED_WAN 6 ++#define NBG460N_GPIO_LED_POWER 14 ++#define NBG460N_GPIO_LED_WLAN 15 + -+#define CFG_BIT_nLEDS \ -+ (CFG_BIT_nLED1 | CFG_BIT_nLED2 | CFG_BIT_nLED3 | CFG_BIT_nLED4) ++/* Buttons */ ++#define NBG460N_GPIO_BTN_WPS 12 ++#define NBG460N_GPIO_BTN_RESET 21 ++#define NBG460N_BUTTONS_POLL_INTERVAL 20 + -+struct rb4xx_nand_info { -+ struct nand_chip chip; -+ struct mtd_info mtd; -+}; ++/* RTC chip PCF8563 I2C interface */ ++#define NBG460N_GPIO_PCF8563_SDA 8 ++#define NBG460N_GPIO_PCF8563_SCK 7 + -+/* -+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader -+ * will not be able to find the kernel that we load. -+ */ -+static struct nand_ecclayout rb4xx_nand_ecclayout = { -+ .eccbytes = 6, -+ .eccpos = { 8, 9, 10, 13, 14, 15 }, -+ .oobavail = 9, -+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } -+}; ++/* Switch configuration I2C interface */ ++#define NBG460N_GPIO_RTL8366_SDA 16 ++#define NBG460N_GPIO_RTL8366_SCK 18 + -+static struct mtd_partition rb4xx_nand_partitions[] = { -+ { -+ .name = "booter", -+ .offset = 0, -+ .size = (256 * 1024), -+ .mask_flags = MTD_WRITEABLE, -+ }, -+ { -+ .name = "kernel", -+ .offset = (256 * 1024), -+ .size = (4 * 1024 * 1024) - (256 * 1024), -+ }, -+ { -+ .name = "rootfs", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = (1024*1024*64) - (1024*256) - (4 * 1024 * 1024) -+ }, ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition nbg460n_partitions[] = { + { -+ .name = "cfgfs", -+ .offset = (1024*1024*64) - (1024*256), -+ .size = (1024*256), -+ }, ++ .name = "Bootbase", ++ .offset = 0, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "U-Boot Config", ++ .offset = 0x010000, ++ .size = 0x030000, ++ } , { ++ .name = "U-Boot", ++ .offset = 0x040000, ++ .size = 0x030000, ++ } , { ++ .name = "linux", ++ .offset = 0x070000, ++ .size = 0x0e0000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x150000, ++ .size = 0x2a0000, ++ } , { ++ .name = "CalibData", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x070000, ++ .size = 0x380000, ++ } +}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+#if USE_FAST_READ -+#define SPI_NDATA_BASE 0x00800000 -+static unsigned spi_ctrl_fread = SPI_CTRL_SAFE; -+static unsigned spi_ctrl_flash = SPI_CTRL_SAFE; -+extern unsigned mips_hpt_frequency; ++static struct flash_platform_data nbg460n_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = nbg460n_partitions, ++ .nr_parts = ARRAY_SIZE(nbg460n_partitions), +#endif ++}; + -+static inline unsigned rb4xx_spi_rreg(unsigned r) -+{ -+ return __raw_readl((void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r)); -+} -+ -+static inline void rb4xx_spi_wreg(unsigned r, unsigned v) -+{ -+ __raw_writel(v, (void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r)); -+} -+ -+static inline void do_spi_clk(int bit) -+{ -+ unsigned bval = SBIT_IOC_BASE | (bit & 1); -+ -+ rb4xx_spi_wreg(SPI_REG_IOC, bval); -+ rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK); -+} -+ -+static void do_spi_byte(uint8_t byte) -+{ -+ do_spi_clk(byte >> 7); -+ do_spi_clk(byte >> 6); -+ do_spi_clk(byte >> 5); -+ do_spi_clk(byte >> 4); -+ do_spi_clk(byte >> 3); -+ do_spi_clk(byte >> 2); -+ do_spi_clk(byte >> 1); -+ do_spi_clk(byte); -+ -+ DBG("spi_byte sent 0x%02x got 0x%x\n", -+ byte, rb4xx_spi_rreg(SPI_REG_RDS)); -+} -+ -+#if USE_FAST_WRITE -+static inline void do_spi_clk_fast(int bit1, int bit2) -+{ -+ unsigned bval = (SBIT_IOC_BASE | -+ ((bit1 << SBIT_IOC_DO_SHIFT) & SBIT_IOC_DO) | -+ ((bit2 << SBIT_IOC_DO2_SHIFT) & SBIT_IOC_DO2)); -+ -+ rb4xx_spi_wreg(SPI_REG_IOC, bval); -+ rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK); -+} -+ -+static inline void do_spi_byte_fast(uint8_t byte) -+{ -+ do_spi_clk_fast(byte >> 7, byte >> 6); -+ do_spi_clk_fast(byte >> 5, byte >> 4); -+ do_spi_clk_fast(byte >> 3, byte >> 2); -+ do_spi_clk_fast(byte >> 1, byte >> 0); -+ -+ DBG("spi_byte_fast sent 0x%02x got 0x%x\n", -+ byte, rb4xx_spi_rreg(SPI_REG_RDS)); -+} -+#else -+static inline void do_spi_byte_fast(uint8_t byte) -+{ -+ do_spi_byte(byte); -+} -+#endif /* USE_FAST_WRITE */ -+ -+static int do_spi_cmd(unsigned cmd, unsigned sendCnt, const uint8_t *sendData, -+ unsigned recvCnt, uint8_t *recvData, -+ const uint8_t *verifyData, int fastWrite) -+{ -+ unsigned i; -+ -+ DBG("SPI cmd 0x%x send %u recv %u\n", cmd, sendCnt, recvCnt); -+ -+ rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO); -+ rb4xx_spi_wreg(SPI_REG_CTRL, SPI_CTRL_FASTEST); -+ -+ do_spi_byte(cmd); -+#if 0 -+ if (cmd == CPLD_CMD_READ_FAST) { -+ do_spi_byte(0x80); -+ do_spi_byte(0); -+ do_spi_byte(0); -+ } -+#endif -+ for (i = 0; i < sendCnt; ++i) { -+ if (fastWrite) -+ do_spi_byte_fast(sendData[i]); -+ else -+ do_spi_byte(sendData[i]); ++static struct gpio_led nbg460n_leds_gpio[] __initdata = { ++ { ++ .name = "nbg460n:green:power", ++ .gpio = NBG460N_GPIO_LED_POWER, ++ .active_low = 0, ++ .default_trigger = "default-on", ++ }, { ++ .name = "nbg460n:green:wps", ++ .gpio = NBG460N_GPIO_LED_WPS, ++ .active_low = 0, ++ }, { ++ .name = "nbg460n:green:wlan", ++ .gpio = NBG460N_GPIO_LED_WLAN, ++ .active_low = 0, ++ }, { ++ /* Not really for controlling the LED, ++ when set low the LED blinks uncontrollable */ ++ .name = "nbg460n:green:wan", ++ .gpio = NBG460N_GPIO_LED_WAN, ++ .active_low = 0, + } ++}; + -+ for (i = 0; i < recvCnt; ++i) { -+ if (fastWrite) -+ do_spi_byte_fast(0); -+ else -+ do_spi_byte(0); -+ -+ if (recvData) { -+ recvData[i] = rb4xx_spi_rreg(SPI_REG_RDS) & 0xff; -+ } else if (verifyData) { -+ if (verifyData[i] != (rb4xx_spi_rreg(SPI_REG_RDS) -+ & 0xff)) -+ break; -+ } ++static struct gpio_button nbg460n_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = NBG460N_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = NBG460N_GPIO_BTN_WPS, ++ .active_low = 1, + } ++}; + -+ rb4xx_spi_wreg(SPI_REG_IOC, SBIT_IOC_BASE | SPI_IOC_CS0); -+ rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_flash); -+ rb4xx_spi_wreg(SPI_REG_FS, 0); ++static struct i2c_gpio_platform_data nbg460n_i2c_device_platdata = { ++ .sda_pin = NBG460N_GPIO_PCF8563_SDA, ++ .scl_pin = NBG460N_GPIO_PCF8563_SCK, ++ .udelay = 10, ++}; + -+ return i == recvCnt; -+} ++static struct platform_device nbg460n_i2c_device = { ++ .name = "i2c-gpio", ++ .id = -1, ++ .num_resources = 0, ++ .resource = NULL, ++ .dev = { ++ .platform_data = &nbg460n_i2c_device_platdata, ++ }, ++}; + -+static int got_write = 1; ++static struct i2c_board_info nbg460n_i2c_devs[] __initdata = { ++ { ++ I2C_BOARD_INFO("pcf8563", 0x51), ++ }, ++}; + -+static void rb4xx_nand_write_data(const uint8_t *byte, unsigned cnt) ++static void __devinit nbg460n_i2c_init(void) +{ -+ do_spi_cmd(CPLD_CMD_WRITE_MULT, cnt, byte, 1, NULL, NULL, 1); -+ got_write = 1; ++ /* The gpio interface */ ++ platform_device_register(&nbg460n_i2c_device); ++ /* I2C devices */ ++ i2c_register_board_info(0, nbg460n_i2c_devs, ++ ARRAY_SIZE(nbg460n_i2c_devs)); +} + -+static void rb4xx_nand_write_byte(uint8_t byte) -+{ -+ rb4xx_nand_write_data(&byte, 1); -+} + -+#if USE_FAST_READ -+static uint8_t *rb4xx_nand_read_getaddr(unsigned cnt) ++static struct rtl8366s_platform_data nbg460n_rtl8366s_data = { ++ .gpio_sda = NBG460N_GPIO_RTL8366_SDA, ++ .gpio_sck = NBG460N_GPIO_RTL8366_SCK, ++}; ++ ++static struct platform_device nbg460n_rtl8366s_device = { ++ .name = RTL8366S_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &nbg460n_rtl8366s_data, ++ } ++}; ++ ++static void __init nbg460n_setup(void) +{ -+ static unsigned nboffset = 0x100000; -+ unsigned addr; ++ /* end of bootloader sector contains mac address*/ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fc0fff8); ++ /* last sector contains wlan calib data */ ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+ if (got_write) { -+ nboffset = (nboffset + 31) & ~31; -+ if (nboffset >= 0x100000) /* 1MB */ -+ nboffset = 0; ++ ar71xx_set_mac_base(mac); + -+ got_write = 0; -+ rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO); -+ rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_fread); -+ rb4xx_spi_wreg(SPI_REG_FS, 0); -+ } ++ /* LAN Port */ ++ ar71xx_eth0_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+ addr = KSEG1ADDR(AR71XX_SPI_BASE + SPI_NDATA_BASE) + nboffset; -+ DBG("rb4xx_nand_read_getaddr 0x%x cnt 0x%x\n", addr, cnt); ++ /* WAN Port */ ++ ar71xx_eth1_data.mii_bus_dev = &nbg460n_rtl8366s_device.dev; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = 0x10; + -+ nboffset += cnt; -+ return (uint8_t *)addr; -+} ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt) -+{ -+ unsigned size32 = cnt & ~31; -+ unsigned remain = cnt & 31; ++ /* register the switch phy */ ++ platform_device_register(&nbg460n_rtl8366s_device); + -+ if (size32) { -+ uint8_t *addr = rb4xx_nand_read_getaddr(size32); -+ memcpy(buf, (void *)addr, size32); -+ } ++ /* register flash */ ++ ar71xx_add_device_m25p80(&nbg460n_flash_data); + -+ if (remain) { -+ do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain, -+ buf + size32, NULL, 0); -+ } -+} ++ ar913x_add_device_wmac(eeprom, mac); + -+static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt) -+{ -+ unsigned size32 = cnt & ~31; -+ unsigned remain = cnt & 31; ++ /* register RTC chip */ ++ nbg460n_i2c_init(); + -+ if (size32) { -+ uint8_t *addr = rb4xx_nand_read_getaddr(size32); -+ if (memcmp(buf, (void *)addr, size32) != 0) -+ return 0; -+ } ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(nbg460n_leds_gpio), ++ nbg460n_leds_gpio); + -+ if (remain) { -+ return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain, -+ NULL, buf + size32, 0); -+ } -+ return 1; -+} -+#else /* USE_FAST_READ */ -+static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt) -+{ -+ do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, buf, NULL, 0); ++ ar71xx_add_device_gpio_buttons(-1, NBG460N_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(nbg460n_gpio_buttons), ++ nbg460n_gpio_buttons); +} + -+static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt) -+{ -+ return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, NULL, buf, 0); -+} -+#endif /* USE_FAST_READ */ ++MIPS_MACHINE(AR71XX_MACH_NBG460N, "NBG460N", "Zyxel NBG460N/550N/550NH", nbg460n_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-pb42.c linux-2.6.36/arch/mips/ar71xx/mach-pb42.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-pb42.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-pb42.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,71 @@ ++/* ++ * Atheros PB42 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static void rb4xx_nand_write_cfg(uint8_t byte) -+{ -+ do_spi_cmd(CPLD_CMD_WRITE_CFG, 1, &byte, 0, NULL, NULL, 0); -+ got_write = 1; -+} ++#include + -+static int rb4xx_nand_dev_ready(struct mtd_info *mtd) -+{ -+ return gpio_get_value(RB4XX_NAND_GPIO_RDY); -+} ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-usb.h" + -+static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ uint8_t cfg = CFG_BIT_nLEDS; ++#define PB42_BUTTONS_POLL_INTERVAL 20 + -+ cfg |= (ctrl & NAND_CLE) ? CFG_BIT_CLE : 0; -+ cfg |= (ctrl & NAND_ALE) ? CFG_BIT_ALE : 0; -+ cfg |= (ctrl & NAND_NCE) ? 0 : CFG_BIT_nCE; ++#define PB42_GPIO_BTN_SW4 8 ++#define PB42_GPIO_BTN_SW5 3 + -+ rb4xx_nand_write_cfg(cfg); ++static struct gpio_button pb42_gpio_buttons[] __initdata = { ++ { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .threshold = 3, ++ .gpio = PB42_GPIO_BTN_SW4, ++ .active_low = 1, ++ } , { ++ .desc = "sw5", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .threshold = 3, ++ .gpio = PB42_GPIO_BTN_SW5, ++ .active_low = 1, + } ++}; + -+ if (cmd != NAND_CMD_NONE) -+ rb4xx_nand_write_byte(cmd); -+} ++#define PB42_WAN_PHYMASK BIT(20) ++#define PB42_LAN_PHYMASK (BIT(16) | BIT(17) | BIT(18) | BIT(19)) ++#define PB42_MDIO_PHYMASK (PB42_LAN_PHYMASK | PB42_WAN_PHYMASK) + -+static uint8_t rb4xx_nand_read_byte(struct mtd_info *mtd) ++static void __init pb42_init(void) +{ -+ uint8_t byte = 0; ++ ar71xx_add_device_m25p80(NULL); + -+ rb4xx_nand_read_data(&byte, 1); -+ return byte; -+} ++ ar71xx_add_device_mdio(~PB42_MDIO_PHYMASK); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = PB42_WAN_PHYMASK; ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_100; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+static void rb4xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, -+ int len) -+{ -+ rb4xx_nand_write_data(buf, len); -+} ++ ar71xx_add_device_gpio_buttons(-1, PB42_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(pb42_gpio_buttons), ++ pb42_gpio_buttons); + -+static void rb4xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, -+ int len) -+{ -+ rb4xx_nand_read_data(buf, len); ++ pb42_pci_init(); +} + -+static int rb4xx_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, -+ int len) -+{ -+ if (!rb4xx_nand_verify_data(buf, len)) -+ return -EFAULT; ++MIPS_MACHINE(AR71XX_MACH_PB42, "PB42", "Atheros PB42", pb42_init); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-pb44.c linux-2.6.36/arch/mips/ar71xx/mach-pb44.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-pb44.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-pb44.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,207 @@ ++/* ++ * Atheros PB44 board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ return 0; -+} ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+static unsigned get_spi_ctrl(unsigned hz_max, const char *name) -+{ -+ unsigned div; ++#include + -+ div = (ar71xx_ahb_freq - 1) / (2 * hz_max); -+ /* -+ * CPU has a bug at (div == 0) - first bit read is random -+ */ -+ if (div == 0) -+ ++div; ++#include "machtype.h" ++#include "devices.h" ++#include "dev-pb42-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+ if (name) { -+ unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000; -+ unsigned div_real = 2 * (div + 1); -+ printk(KERN_INFO "%s SPI clock %u kHz (AHB %u kHz / %u)\n", -+ name, -+ ahb_khz / div_real, -+ ahb_khz, div_real); -+ } ++#define PB44_PCF8757_VSC7395_CS 0 ++#define PB44_PCF8757_STEREO_CS 1 ++#define PB44_PCF8757_SLIC_CS0 2 ++#define PB44_PCF8757_SLIC_TEST 3 ++#define PB44_PCF8757_SLIC_INT0 4 ++#define PB44_PCF8757_SLIC_INT1 5 ++#define PB44_PCF8757_SW_RESET 6 ++#define PB44_PCF8757_SW_JUMP 8 ++#define PB44_PCF8757_LED_JUMP1 9 ++#define PB44_PCF8757_LED_JUMP2 10 ++#define PB44_PCF8757_TP24 11 ++#define PB44_PCF8757_TP25 12 ++#define PB44_PCF8757_TP26 13 ++#define PB44_PCF8757_TP27 14 ++#define PB44_PCF8757_TP28 15 + -+ return SPI_CTRL_FASTEST + div; -+} ++#define PB44_GPIO_I2C_SCL 0 ++#define PB44_GPIO_I2C_SDA 1 + -+static int __init rb4xx_nand_probe(struct platform_device *pdev) -+{ -+ struct rb4xx_nand_info *info; -+ int ret; ++#define PB44_GPIO_EXP_BASE 16 ++#define PB44_GPIO_VSC7395_CS (PB44_GPIO_EXP_BASE + PB44_PCF8757_VSC7395_CS) ++#define PB44_GPIO_SW_RESET (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_RESET) ++#define PB44_GPIO_SW_JUMP (PB44_GPIO_EXP_BASE + PB44_PCF8757_SW_JUMP) ++#define PB44_GPIO_LED_JUMP1 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP1) ++#define PB44_GPIO_LED_JUMP2 (PB44_GPIO_EXP_BASE + PB44_PCF8757_LED_JUMP2) + -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); ++static struct i2c_gpio_platform_data pb44_i2c_gpio_data = { ++ .sda_pin = PB44_GPIO_I2C_SDA, ++ .scl_pin = PB44_GPIO_I2C_SCL, ++}; + -+ ret = gpio_request(RB4XX_NAND_GPIO_RDY, "NAND RDY"); -+ if (ret) { -+ printk(KERN_ERR "rb4xx-nand: gpio request failed\n"); -+ return ret; ++static struct platform_device pb44_i2c_gpio_device = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &pb44_i2c_gpio_data, + } ++}; + -+ ret = gpio_direction_input(RB4XX_NAND_GPIO_RDY); -+ if (ret) { -+ printk(KERN_ERR "rb4xx-nand: unable to set input mode " -+ "on gpio%d\n", RB4XX_NAND_GPIO_RDY); -+ goto err_free_gpio; -+ } ++static struct pcf857x_platform_data pb44_pcf857x_data = { ++ .gpio_base = PB44_GPIO_EXP_BASE, ++}; + -+ info = kzalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) { -+ printk(KERN_ERR "rb4xx-nand: no memory for private data\n"); -+ ret = -ENOMEM; -+ goto err_free_gpio; ++static struct i2c_board_info pb44_i2c_board_info[] __initdata = { ++ { ++ I2C_BOARD_INFO("pcf8575", 0x20), ++ .platform_data = &pb44_pcf857x_data, ++ }, ++}; ++ ++static struct gpio_led pb44_leds_gpio[] __initdata = { ++ { ++ .name = "pb44:amber:jump1", ++ .gpio = PB44_GPIO_LED_JUMP1, ++ .active_low = 1, ++ }, { ++ .name = "pb44:green:jump2", ++ .gpio = PB44_GPIO_LED_JUMP2, ++ .active_low = 1, ++ }, ++}; ++ ++static struct gpio_button pb44_gpio_buttons[] __initdata = { ++ { ++ .desc = "soft_reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = PB44_GPIO_SW_RESET, ++ .active_low = 1, ++ } , { ++ .desc = "jumpstart", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = PB44_GPIO_SW_JUMP, ++ .active_low = 1, + } ++}; + -+#if USE_FAST_READ -+ spi_ctrl_fread = get_spi_ctrl(RB4XX_NAND_HZ, "NAND"); -+#endif -+ spi_ctrl_flash = get_spi_ctrl(RB4XX_FLASH_HZ, "FLASH"); ++static void pb44_vsc7395_reset(void) ++{ ++ ar71xx_device_stop(RESET_MODULE_GE1_PHY); ++ udelay(10); ++ ar71xx_device_start(RESET_MODULE_GE1_PHY); ++ mdelay(50); ++} + -+ rb4xx_nand_write_cfg(CFG_BIT_nLEDS | CFG_BIT_nCE); ++static struct vsc7385_platform_data pb44_vsc7395_data = { ++ .reset = pb44_vsc7395_reset, ++ .ucode_name = "vsc7395_ucode_pb44.bin", ++ .mac_cfg = { ++ .tx_ipg = 6, ++ .bit2 = 1, ++ .clk_sel = 0, ++ }, ++}; + -+ info->chip.priv = &info; -+ info->mtd.priv = &info->chip; -+ info->mtd.owner = THIS_MODULE; ++static struct spi_board_info pb44_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ }, { ++ .bus_num = 0, ++ .chip_select = 1, ++ .max_speed_hz = 25000000, ++ .modalias = "spi-vsc7385", ++ .platform_data = &pb44_vsc7395_data, ++ .controller_data = (void *) PB44_GPIO_VSC7395_CS, ++ }, ++}; + -+ info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; -+ info->chip.dev_ready = rb4xx_nand_dev_ready; -+ info->chip.read_byte = rb4xx_nand_read_byte; -+ info->chip.write_buf = rb4xx_nand_write_buf; -+ info->chip.read_buf = rb4xx_nand_read_buf; -+ info->chip.verify_buf = rb4xx_nand_verify_buf; ++static struct resource pb44_spi_resources[] = { ++ [0] = { ++ .start = AR71XX_SPI_BASE, ++ .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; + -+ info->chip.chip_delay = 25; -+ info->chip.ecc.mode = NAND_ECC_SOFT; -+ info->chip.options |= NAND_NO_AUTOINCR; ++static struct ar71xx_spi_platform_data pb44_spi_data = { ++ .bus_num = 0, ++ .num_chipselect = 2, ++}; + -+ platform_set_drvdata(pdev, info); ++static struct platform_device pb44_spi_device = { ++ .name = "pb44-spi", ++ .id = -1, ++ .resource = pb44_spi_resources, ++ .num_resources = ARRAY_SIZE(pb44_spi_resources), ++ .dev = { ++ .platform_data = &pb44_spi_data, ++ }, ++}; + -+ ret = nand_scan_ident(&info->mtd, 1, NULL); -+ if (ret) { -+ ret = -ENXIO; -+ goto err_free_info; -+ } ++#define PB44_WAN_PHYMASK BIT(0) ++#define PB44_LAN_PHYMASK 0 ++#define PB44_MDIO_PHYMASK (PB44_LAN_PHYMASK | PB44_WAN_PHYMASK) + -+ if (info->mtd.writesize == 512) -+ info->chip.ecc.layout = &rb4xx_nand_ecclayout; ++static void __init pb44_init(void) ++{ ++ ar71xx_add_device_mdio(~PB44_MDIO_PHYMASK); + -+ ret = nand_scan_tail(&info->mtd); -+ if (ret) { -+ return -ENXIO; -+ goto err_set_drvdata; -+ } ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = PB44_WAN_PHYMASK; + -+#ifdef CONFIG_MTD_PARTITIONS -+ ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions, -+ ARRAY_SIZE(rb4xx_nand_partitions)); -+#else -+ ret = add_mtd_device(&info->mtd); -+#endif -+ if (ret) -+ goto err_release_nand; ++ ar71xx_add_device_eth(0); + -+ return 0; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ar71xx_eth1_pll_data.pll_1000 = 0x110000; + -+err_release_nand: -+ nand_release(&info->mtd); -+err_set_drvdata: -+ platform_set_drvdata(pdev, NULL); -+err_free_info: -+ kfree(info); -+err_free_gpio: -+ gpio_free(RB4XX_NAND_GPIO_RDY); -+ return ret; -+} ++ ar71xx_add_device_eth(1); + -+static int __devexit rb4xx_nand_remove(struct platform_device *pdev) -+{ -+ struct rb4xx_nand_info *info = platform_get_drvdata(pdev); ++ ar71xx_add_device_usb(); + -+ nand_release(&info->mtd); -+ platform_set_drvdata(pdev, NULL); -+ kfree(info); ++ pb42_pci_init(); + -+ return 0; -+} ++ i2c_register_board_info(0, pb44_i2c_board_info, ++ ARRAY_SIZE(pb44_i2c_board_info)); + -+static struct platform_driver rb4xx_nand_driver = { -+ .probe = rb4xx_nand_probe, -+ .remove = __devexit_p(rb4xx_nand_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; ++ platform_device_register(&pb44_i2c_gpio_device); + -+static int __init rb4xx_nand_init(void) -+{ -+ return platform_driver_register(&rb4xx_nand_driver); -+} ++ spi_register_board_info(pb44_spi_info, ARRAY_SIZE(pb44_spi_info)); ++ platform_device_register(&pb44_spi_device); + -+static void __exit rb4xx_nand_exit(void) -+{ -+ platform_driver_unregister(&rb4xx_nand_driver); -+} ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(pb44_leds_gpio), ++ pb44_leds_gpio); + -+module_init(rb4xx_nand_init); -+module_exit(rb4xx_nand_exit); ++ ar71xx_add_device_gpio_buttons(-1, 20, ARRAY_SIZE(pb44_gpio_buttons), ++ pb44_gpio_buttons); ++} + -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.35.7.orig/drivers/mtd/nand/rb750_nand.c linux-2.6.35.7/drivers/mtd/nand/rb750_nand.c ---- linux-2.6.35.7.orig/drivers/mtd/nand/rb750_nand.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/mtd/nand/rb750_nand.c 2010-10-14 20:28:00.398101127 +0200 -@@ -0,0 +1,360 @@ ++MIPS_MACHINE(AR71XX_MACH_PB44, "PB44", "Atheros PB44", pb44_init); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-pb92.c linux-2.6.36/arch/mips/ar71xx/mach-pb92.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-pb92.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-pb92.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,109 @@ +/* -+ * NAND flash driver for the MikroTik RouterBOARD 750 ++ * Atheros PB92 board support + * -+ * Copyright (C) 2010 Gabor Juhos ++ * Copyright (C) 2010 Felix Fietkau ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include -+#include +#include +#include -+#include -+#include -+ +#include -+#include -+ -+#define DRV_NAME "rb750-nand" -+#define DRV_VERSION "0.1.0" -+#define DRV_DESC "NAND flash driver for the RouterBOARD 750" -+ -+#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) -+#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) -+#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) -+#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) -+#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) -+#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) -+#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) -+ -+#define RB750_NAND_DATA_SHIFT 1 -+#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) -+#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) -+#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ -+ RB750_NAND_NRE | RB750_NAND_NWE | \ -+ RB750_NAND_NCE) -+ -+struct rb750_nand_info { -+ struct nand_chip chip; -+ struct mtd_info mtd; -+}; + -+/* -+ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader -+ * will not be able to find the kernel that we load. -+ */ -+static struct nand_ecclayout rb750_nand_ecclayout = { -+ .eccbytes = 6, -+ .eccpos = { 8, 9, 10, 13, 14, 15 }, -+ .oobavail = 9, -+ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } -+}; ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb9x-pci.h" ++#include "dev-usb.h" + -+static struct mtd_partition rb750_nand_partitions[] = { ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition pb92_partitions[] = { + { -+ .name = "booter", -+ .offset = 0, -+ .size = (256 * 1024), -+ .mask_flags = MTD_WRITEABLE, -+ }, { -+ .name = "kernel", -+ .offset = (256 * 1024), -+ .size = (4 * 1024 * 1024) - (256 * 1024), -+ }, { -+ .name = "rootfs", -+ .offset = MTDPART_OFS_NXTBLK, -+ .size = MTDPART_SIZ_FULL, -+ }, ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x2b0000, ++ } , { ++ .name = "uImage", ++ .offset = 0x300000, ++ .size = 0x0e0000, ++ } , { ++ .name = "ART", ++ .offset = 0x3e0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } +}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+static void rb750_nand_write(const u8 *buf, unsigned len) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 out; -+ unsigned i; ++static struct flash_platform_data pb92_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = pb92_partitions, ++ .nr_parts = ARRAY_SIZE(pb92_partitions), ++#endif ++}; + -+ /* set data lines to output mode */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_DATA_BITS, -+ base + GPIO_REG_OE); + -+ out = __raw_readl(base + GPIO_REG_OUT); -+ out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); -+ for (i = 0; i != len; i++) { -+ u32 data; ++#define PB92_BUTTONS_POLL_INTERVAL 20 + -+ data = buf[i]; -+ data <<= RB750_NAND_DATA_SHIFT; -+ data |= out; -+ __raw_writel(data, base + GPIO_REG_OUT); ++#define PB92_GPIO_BTN_SW4 8 ++#define PB92_GPIO_BTN_SW5 3 + -+ __raw_writel(data | RB750_NAND_NWE, base + GPIO_REG_OUT); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OUT); ++static struct gpio_button pb92_gpio_buttons[] __initdata = { ++ { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .threshold = 3, ++ .gpio = PB92_GPIO_BTN_SW4, ++ .active_low = 1, ++ } , { ++ .desc = "sw5", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .threshold = 3, ++ .gpio = PB92_GPIO_BTN_SW5, ++ .active_low = 1, + } ++}; + -+ /* set data lines to input mode */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~RB750_NAND_DATA_BITS, -+ base + GPIO_REG_OE); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OE); -+} -+ -+static int rb750_nand_read_verify(u8 *read_buf, unsigned len, -+ const u8 *verify_buf) ++static void __init pb92_init(void) +{ -+ void __iomem *base = ar71xx_gpio_base; -+ unsigned i; ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); + -+ for (i = 0; i < len; i++) { -+ u8 data; ++ ar71xx_set_mac_base(mac); ++ ar71xx_add_device_m25p80(&pb92_flash_data); + -+ /* activate RE line */ -+ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_CLEAR); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_CLEAR); ++ ar71xx_add_device_mdio(~0); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+ /* read input lines */ -+ data = __raw_readl(base + GPIO_REG_IN) >> RB750_NAND_DATA_SHIFT; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; + -+ /* deactivate RE line */ -+ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_SET); ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ if (read_buf) -+ read_buf[i] = data; -+ else if (verify_buf && verify_buf[i] != data) -+ return -EFAULT; -+ } ++ ar71xx_add_device_gpio_buttons(-1, PB92_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(pb92_gpio_buttons), ++ pb92_gpio_buttons); + -+ return 0; ++ pb9x_pci_init(); +} + -+static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) -+{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 func; -+ -+ func = __raw_readl(base + GPIO_REG_FUNC); -+ if (chip >= 0) { -+ /* disable latch */ -+ rb750_latch_change(RB750_LVC573_LE, 0); ++MIPS_MACHINE(AR71XX_MACH_PB92, "PB92", "Atheros PB92", pb92_init); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-rb4xx.c linux-2.6.36/arch/mips/ar71xx/mach-rb4xx.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-rb4xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-rb4xx.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,290 @@ ++/* ++ * MikroTik RouterBOARD 4xx series support ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ /* disable alternate functions */ -+ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, -+ AR724X_GPIO_FUNC_SPI_EN); ++#include ++#include ++#include ++#include ++#include ++#include + -+ /* set input mode for data lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & -+ ~RB750_NAND_INPUT_BITS, -+ base + GPIO_REG_OE); ++#include ++#include + -+ /* deactivate RE and WE lines */ -+ __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, -+ base + GPIO_REG_SET); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_SET); ++#include "machtype.h" ++#include "devices.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+ /* activate CE line */ -+ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_CLEAR); -+ } else { -+ /* deactivate CE line */ -+ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_SET); -+ /* flush write */ -+ (void) __raw_readl(base + GPIO_REG_SET); ++#define RB4XX_GPIO_USER_LED 4 ++#define RB4XX_GPIO_RESET_SWITCH 7 + -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | -+ RB750_NAND_IO0 | RB750_NAND_RDY, -+ base + GPIO_REG_OE); ++#define RB4XX_BUTTONS_POLL_INTERVAL 20 + -+ /* restore alternate functions */ -+ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, -+ AR724X_GPIO_FUNC_JTAG_DISABLE); ++static struct gpio_led rb4xx_leds_gpio[] __initdata = { ++ { ++ .name = "rb4xx:yellow:user", ++ .gpio = RB4XX_GPIO_USER_LED, ++ .active_low = 0, ++ }, ++}; + -+ /* enable latch */ -+ rb750_latch_change(0, RB750_LVC573_LE); ++static struct gpio_button rb4xx_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset_switch", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = RB4XX_GPIO_RESET_SWITCH, ++ .active_low = 1, + } -+} ++}; + -+static int rb750_nand_dev_ready(struct mtd_info *mtd) -+{ -+ void __iomem *base = ar71xx_gpio_base; ++static struct platform_device rb4xx_nand_device = { ++ .name = "rb4xx-nand", ++ .id = -1, ++}; + -+ return !!(__raw_readl(base + GPIO_REG_IN) & RB750_NAND_RDY); -+} ++static struct ar71xx_pci_irq rb4xx_pci_irqs[] __initdata = { ++ { ++ .slot = 0, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV2, ++ }, { ++ .slot = 1, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV0, ++ }, { ++ .slot = 1, ++ .pin = 2, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ }, { ++ .slot = 2, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV1, ++ }, { ++ .slot = 3, ++ .pin = 1, ++ .irq = AR71XX_PCI_IRQ_DEV2, ++ } ++}; + -+static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, -+ unsigned int ctrl) -+{ -+ if (ctrl & NAND_CTRL_CHANGE) { -+ void __iomem *base = ar71xx_gpio_base; -+ u32 t; ++#if 0 ++/* ++ * SPI device support is experimental ++ */ ++static struct flash_platform_data rb4xx_flash_data = { ++ .type = "pm25lv512", ++}; + -+ t = __raw_readl(base + GPIO_REG_OUT); ++static struct spi_board_info rb4xx_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ .platform_data = &rb4xx_flash_data, ++ } ++}; + -+ t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); -+ t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; -+ t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; ++static struct mmc_spi_platform_data rb433_mmc_data = { ++ .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, ++}; + -+ __raw_writel(t, base + GPIO_REG_OUT); -+ /* flush write */ -+ __raw_readl(base + GPIO_REG_OUT); ++static struct spi_board_info rb433_spi_info[] = { ++ { ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 25000000, ++ .modalias = "m25p80", ++ .platform_data = &rb433_flash_data, ++ }, { ++ .bus_num = 0, ++ .chip_select = 2, ++ .max_speed_hz = 25000000, ++ .modalias = "mmc_spi", ++ .platform_data = &rb433_mmc_data, + } ++}; + -+ if (cmd != NAND_CMD_NONE) { -+ u8 t = cmd; -+ rb750_nand_write(&t, 1); ++static u32 rb433_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) ++{ ++ u32 ret; ++ ++ if (is_on == AR71XX_SPI_CS_INACTIVE) { ++ ret = SPI_IOC_CS0 | SPI_IOC_CS1; ++ } else { ++ if (cs_high) { ++ ret = SPI_IOC_CS0 | SPI_IOC_CS1; ++ } else { ++ if ((chip_select ^ 2) == 0) ++ ret = SPI_IOC_CS1 ^ (SPI_IOC_CS0 | SPI_IOC_CS1); ++ else ++ ret = SPI_IOC_CS0 ^ (SPI_IOC_CS0 | SPI_IOC_CS1); ++ } + } -+} + -+static u8 rb750_nand_read_byte(struct mtd_info *mtd) -+{ -+ u8 data = 0; -+ rb750_nand_read_verify(&data, 1, NULL); -+ return data; ++ return ret; +} + -+static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) -+{ -+ rb750_nand_read_verify(buf, len, NULL); -+} ++struct ar71xx_spi_platform_data rb433_spi_data = { ++ .bus_num = 0, ++ .num_chipselect = 3, ++ .get_ioc_base = rb433_spi_get_ioc_base, ++}; + -+static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) ++static void rb4xx_add_device_spi(void) +{ -+ rb750_nand_write(buf, len); ++ ar71xx_add_device_spi(NULL, rb4xx_spi_info, ARRAY_SIZE(rb4xx_spi_info)); +} + -+static int rb750_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, int len) ++static void rb433_add_device_spi(void) +{ -+ return rb750_nand_read_verify(NULL, len, buf); ++ ar71xx_add_device_spi(&rb433_spi_data, rb433_spi_info, ++ ARRAY_SIZE(rb433_spi_info)); +} ++#else ++static inline void rb4xx_add_device_spi(void) {} ++static inline void rb433_add_device_spi(void) {} ++#endif + -+static void __init rb750_nand_gpio_init(void) ++static void __init rb4xx_generic_setup(void) +{ -+ void __iomem *base = ar71xx_gpio_base; -+ u32 out; -+ -+ out = __raw_readl(base + GPIO_REG_OUT); -+ -+ /* setup output levels */ -+ __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, -+ base + GPIO_REG_SET); -+ -+ __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, -+ base + GPIO_REG_CLEAR); ++ ar71xx_gpio_function_enable(AR71XX_GPIO_FUNC_SPI_CS1_EN | ++ AR71XX_GPIO_FUNC_SPI_CS2_EN); + -+ /* setup input lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(RB750_NAND_INPUT_BITS), -+ base + GPIO_REG_OE); ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(rb4xx_leds_gpio), ++ rb4xx_leds_gpio); + -+ /* setup output lines */ -+ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_OUTPUT_BITS, -+ base + GPIO_REG_OE); ++ ar71xx_add_device_gpio_buttons(-1, RB4XX_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(rb4xx_gpio_buttons), ++ rb4xx_gpio_buttons); + -+ rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); ++ platform_device_register(&rb4xx_nand_device); +} + -+static int __init rb750_nand_probe(struct platform_device *pdev) ++static void __init rb411_setup(void) +{ -+ struct rb750_nand_info *info; -+ int ret; ++ rb4xx_generic_setup(); ++ rb4xx_add_device_spi(); + -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); ++ ar71xx_add_device_mdio(0xfffffffc); + -+ rb750_nand_gpio_init(); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = 0x00000003; + -+ info = kzalloc(sizeof(*info), GFP_KERNEL); -+ if (!info) -+ return -ENOMEM; ++ ar71xx_add_device_eth(0); + -+ info->chip.priv = &info; -+ info->mtd.priv = &info->chip; -+ info->mtd.owner = THIS_MODULE; ++ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); ++} + -+ info->chip.select_chip = rb750_nand_select_chip; -+ info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; -+ info->chip.dev_ready = rb750_nand_dev_ready; -+ info->chip.read_byte = rb750_nand_read_byte; -+ info->chip.write_buf = rb750_nand_write_buf; -+ info->chip.read_buf = rb750_nand_read_buf; -+ info->chip.verify_buf = rb750_nand_verify_buf; ++MIPS_MACHINE(AR71XX_MACH_RB_411, "411", "MikroTik RouterBOARD 411/A/AH", ++ rb411_setup); ++ ++static void __init rb411u_setup(void) ++{ ++ rb411_setup(); ++ ar71xx_add_device_usb(); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_RB_411U, "411U", "MikroTik RouterBOARD 411U", ++ rb411u_setup); + -+ info->chip.chip_delay = 25; -+ info->chip.ecc.mode = NAND_ECC_SOFT; -+ info->chip.options |= NAND_NO_AUTOINCR; ++static void __init rb433_setup(void) ++{ ++ rb4xx_generic_setup(); ++ rb433_add_device_spi(); + -+ platform_set_drvdata(pdev, info); ++ ar71xx_add_device_mdio(0xffffffe9); + -+ ret = nand_scan_ident(&info->mtd, 1); -+ if (ret) { -+ ret = -ENXIO; -+ goto err_free_info; -+ } ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+ if (info->mtd.writesize == 512) -+ info->chip.ecc.layout = &rb750_nand_ecclayout; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x00000010; + -+ ret = nand_scan_tail(&info->mtd); -+ if (ret) { -+ return -ENXIO; -+ goto err_set_drvdata; -+ } ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); + -+#ifdef CONFIG_MTD_PARTITIONS -+ ret = add_mtd_partitions(&info->mtd, rb750_nand_partitions, -+ ARRAY_SIZE(rb750_nand_partitions)); -+#else -+ ret = add_mtd_device(&info->mtd); -+#endif -+ if (ret) -+ goto err_release_nand; ++ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); ++} + -+ return 0; ++MIPS_MACHINE(AR71XX_MACH_RB_433, "433", "MikroTik RouterBOARD 433/AH", ++ rb433_setup); + -+ err_release_nand: -+ nand_release(&info->mtd); -+ err_set_drvdata: -+ platform_set_drvdata(pdev, NULL); -+ err_free_info: -+ kfree(info); -+ return ret; ++static void __init rb433u_setup(void) ++{ ++ rb433_setup(); ++ ar71xx_add_device_usb(); +} + -+static int __devexit rb750_nand_remove(struct platform_device *pdev) ++MIPS_MACHINE(AR71XX_MACH_RB_433U, "433U", "MikroTik RouterBOARD 433UAH", ++ rb433u_setup); ++ ++static void __init rb450_generic_setup(int gige) +{ -+ struct rb750_nand_info *info = platform_get_drvdata(pdev); ++ rb4xx_generic_setup(); ++ rb4xx_add_device_spi(); + -+ nand_release(&info->mtd); -+ platform_set_drvdata(pdev, NULL); -+ kfree(info); ++ ar71xx_add_device_mdio(0xffffffe0); + -+ return 0; -+} ++ ar71xx_eth0_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = (gige) ? (1 << 0) : 0; ++ ar71xx_eth0_data.speed = (gige) ? SPEED_1000 : SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+static struct platform_driver rb750_nand_driver = { -+ .probe = rb750_nand_probe, -+ .remove = __devexit_p(rb750_nand_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; ++ ar71xx_eth1_data.phy_if_mode = (gige) ? PHY_INTERFACE_MODE_RGMII : PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x00000010; + -+static int __init rb750_nand_init(void) ++ ar71xx_add_device_eth(1); ++ ar71xx_add_device_eth(0); ++} ++ ++static void __init rb450_setup(void) +{ -+ return platform_driver_register(&rb750_nand_driver); ++ rb450_generic_setup(0); +} + -+static void __exit rb750_nand_exit(void) ++MIPS_MACHINE(AR71XX_MACH_RB_450, "450", "MikroTik RouterBOARD 450", ++ rb450_setup); ++ ++static void __init rb450g_setup(void) +{ -+ platform_driver_unregister(&rb750_nand_driver); ++ rb450_generic_setup(1); +} + -+module_init(rb750_nand_init); -+module_exit(rb750_nand_exit); ++MIPS_MACHINE(AR71XX_MACH_RB_450G, "450G", "MikroTik RouterBOARD 450G", ++ rb450g_setup); + -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.35.7.orig/drivers/mtd/wrt160nl_part.c linux-2.6.35.7/drivers/mtd/wrt160nl_part.c ---- linux-2.6.35.7.orig/drivers/mtd/wrt160nl_part.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/mtd/wrt160nl_part.c 2010-10-14 20:28:00.438101171 +0200 -@@ -0,0 +1,181 @@ -+/* -+ * Copyright (C) 2009 Christian Daniel -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -+ * -+ * TRX flash partition table. -+ * Based on ar7 map by Felix Fietkau -+ * -+ */ ++static void __init rb493_setup(void) ++{ ++ rb4xx_generic_setup(); ++ rb4xx_add_device_spi(); + -+#include -+#include -+#include ++ ar71xx_add_device_mdio(0x3fffff00); + -+#include -+#include ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+struct cybertan_header { -+ char magic[4]; -+ u8 res1[4]; -+ char fw_date[3]; -+ char fw_ver[3]; -+ char id[4]; -+ char hw_ver; -+ char unused; -+ u8 flags[2]; -+ u8 res2[10]; -+}; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x00000001; + -+#define TRX_PARTS 6 -+#define TRX_MAGIC 0x30524448 -+#define TRX_MAX_OFFSET 3 ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+struct trx_header { -+ uint32_t magic; /* "HDR0" */ -+ uint32_t len; /* Length of file including header */ -+ uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ -+ uint32_t flag_version; /* 0:15 flags, 16:31 version */ -+ uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ -+}; ++ ar71xx_pci_init(ARRAY_SIZE(rb4xx_pci_irqs), rb4xx_pci_irqs); ++} + -+#define IH_MAGIC 0x27051956 /* Image Magic Number */ -+#define IH_NMLEN 32 /* Image Name Length */ ++MIPS_MACHINE(AR71XX_MACH_RB_493, "493", "MikroTik RouterBOARD 493/AH", ++ rb493_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-rb750.c linux-2.6.36/arch/mips/ar71xx/mach-rb750.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-rb750.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-rb750.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,133 @@ ++/* ++ * MikroTik RouterBOARD 750 support ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+struct uimage_header { -+ uint32_t ih_magic; /* Image Header Magic Number */ -+ uint32_t ih_hcrc; /* Image Header CRC Checksum */ -+ uint32_t ih_time; /* Image Creation Timestamp */ -+ uint32_t ih_size; /* Image Data Size */ -+ uint32_t ih_load; /* Data» Load Address */ -+ uint32_t ih_ep; /* Entry Point Address */ -+ uint32_t ih_dcrc; /* Image Data CRC Checksum */ -+ uint8_t ih_os; /* Operating System */ -+ uint8_t ih_arch; /* CPU architecture */ -+ uint8_t ih_type; /* Image Type */ -+ uint8_t ih_comp; /* Compression Type */ -+ uint8_t ih_name[IH_NMLEN]; /* Image Name */ -+}; ++#include ++#include ++#include + -+struct wrt160nl_header { -+ struct cybertan_header cybertan; -+ struct trx_header trx; -+ struct uimage_header uimage; -+} __attribute__ ((packed)); ++#include "machtype.h" ++#include "dev-ap91-eth.h" + -+static struct mtd_partition trx_parts[TRX_PARTS]; ++static struct rb750_led_data rb750_leds[] = { ++ { ++ .name = "rb750:green:act", ++ .mask = RB750_LED_ACT, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port1", ++ .mask = RB750_LED_PORT5, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port2", ++ .mask = RB750_LED_PORT4, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port3", ++ .mask = RB750_LED_PORT3, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port4", ++ .mask = RB750_LED_PORT2, ++ .active_low = 1, ++ }, { ++ .name = "rb750:green:port5", ++ .mask = RB750_LED_PORT1, ++ .active_low = 1, ++ } ++}; + -+static int wrt160nl_parse_partitions(struct mtd_info *master, -+ struct mtd_partition **pparts, -+ unsigned long origin) -+{ -+ struct wrt160nl_header *header; -+ struct trx_header *theader; -+ struct uimage_header *uheader; -+ size_t retlen; -+ unsigned int kernel_len; -+ int ret; ++static struct rb750_led_platform_data rb750_leds_data = { ++ .num_leds = ARRAY_SIZE(rb750_leds), ++ .leds = rb750_leds, ++}; + -+ header = vmalloc(sizeof(*header)); -+ if (!header) { -+ return -ENOMEM; -+ goto out; ++static struct platform_device rb750_leds_device = { ++ .name = "leds-rb750", ++ .dev = { ++ .platform_data = &rb750_leds_data, + } ++}; + -+ ret = master->read(master, 4 * master->erasesize, sizeof(*header), -+ &retlen, (void *) header); -+ if (ret) -+ goto free_hdr; ++static const char *rb750_port_names[AP91_ETH_NUM_PORT_NAMES] __initdata = { ++ "port5", ++ "port4", ++ "port3", ++ "port2", ++}; + -+ if (retlen != sizeof(*header)) { -+ ret = -EIO; -+ goto free_hdr; -+ } ++static struct platform_device rb750_nand_device = { ++ .name = "rb750-nand", ++ .id = -1, ++}; + -+ if (strncmp(header->cybertan.magic, "NL16", 4) != 0) { -+ printk(KERN_NOTICE "%s: no WRT160NL signature found\n", -+ master->name); -+ goto free_hdr; -+ } ++int rb750_latch_change(u32 mask_clr, u32 mask_set) ++{ ++ static DEFINE_SPINLOCK(lock); ++ static u32 latch_set = RB750_LED_BITS | RB750_LVC573_LE; ++ static u32 latch_oe; ++ static u32 latch_clr; ++ unsigned long flags; ++ u32 t; ++ int ret = 0; + -+ theader = &header->trx; -+ if (le32_to_cpu(theader->magic) != TRX_MAGIC) { -+ printk(KERN_NOTICE "%s: no TRX header found\n", master->name); -+ goto free_hdr; -+ } ++ spin_lock_irqsave(&lock, flags); + -+ uheader = &header->uimage; -+ if (uheader->ih_magic != IH_MAGIC) { -+ printk(KERN_NOTICE "%s: no uImage found\n", master->name); -+ goto free_hdr; ++ if ((mask_clr & BIT(31)) != 0 && ++ (latch_set & RB750_LVC573_LE) == 0) { ++ goto unlock; + } + -+ kernel_len = le32_to_cpu(theader->offsets[1]) + sizeof(struct cybertan_header); -+ -+ trx_parts[0].name = "u-boot"; -+ trx_parts[0].offset = 0; -+ trx_parts[0].size = 4 * master->erasesize; -+ trx_parts[0].mask_flags = MTD_WRITEABLE; ++ latch_set = (latch_set | mask_set) & ~mask_clr; ++ latch_clr = (latch_clr | mask_clr) & ~mask_set; + -+ trx_parts[1].name = "kernel"; -+ trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; -+ trx_parts[1].size = kernel_len; -+ trx_parts[1].mask_flags = 0; ++ if (latch_oe == 0) ++ latch_oe = __raw_readl(ar71xx_gpio_base + GPIO_REG_OE); + -+ trx_parts[2].name = "rootfs"; -+ trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; -+ trx_parts[2].size = master->size - 6 * master->erasesize - trx_parts[1].size; -+ trx_parts[2].mask_flags = 0; ++ if (likely(latch_set & RB750_LVC573_LE)) { ++ void __iomem *base = ar71xx_gpio_base; + -+ trx_parts[3].name = "nvram"; -+ trx_parts[3].offset = master->size - 2 * master->erasesize; -+ trx_parts[3].size = master->erasesize; -+ trx_parts[3].mask_flags = MTD_WRITEABLE; ++ t = __raw_readl(base + GPIO_REG_OE); ++ t |= mask_clr | latch_oe | mask_set; + -+ trx_parts[4].name = "art"; -+ trx_parts[4].offset = master->size - master->erasesize; -+ trx_parts[4].size = master->erasesize; -+ trx_parts[4].mask_flags = MTD_WRITEABLE; ++ __raw_writel(t, base + GPIO_REG_OE); ++ __raw_writel(latch_clr, base + GPIO_REG_CLEAR); ++ __raw_writel(latch_set, base + GPIO_REG_SET); ++ } else if (mask_clr & RB750_LVC573_LE) { ++ void __iomem *base = ar71xx_gpio_base; + -+ trx_parts[5].name = "firmware"; -+ trx_parts[5].offset = 4 * master->erasesize; -+ trx_parts[5].size = master->size - 6 * master->erasesize; -+ trx_parts[5].mask_flags = 0; ++ latch_oe = __raw_readl(base + GPIO_REG_OE); ++ __raw_writel(RB750_LVC573_LE, base + GPIO_REG_CLEAR); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_CLEAR); ++ } + -+ *pparts = trx_parts; -+ ret = TRX_PARTS; ++ ret = 1; + -+ free_hdr: -+ vfree(header); -+ out: ++ unlock: ++ spin_unlock_irqrestore(&lock, flags); + return ret; +} ++EXPORT_SYMBOL_GPL(rb750_latch_change); + -+static struct mtd_part_parser wrt160nl_parser = { -+ .owner = THIS_MODULE, -+ .parse_fn = wrt160nl_parse_partitions, -+ .name = "wrt160nl", -+}; -+ -+static int __init wrt160nl_parser_init(void) ++static void __init rb750_setup(void) +{ -+ return register_mtd_parser(&wrt160nl_parser); -+} ++ ar71xx_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN | ++ AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN); + -+module_init(wrt160nl_parser_init); ++ ap91_eth_init(NULL, rb750_port_names); ++ platform_device_register(&rb750_leds_device); ++ platform_device_register(&rb750_nand_device); ++} + -+MODULE_LICENSE("GPL"); -+MODULE_AUTHOR("Christian Daniel "); -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_ar8216.c linux-2.6.35.7/drivers/net/ag71xx/ag71xx_ar8216.c ---- linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_ar8216.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/ag71xx_ar8216.c 2010-10-14 20:28:00.478101179 +0200 -@@ -0,0 +1,44 @@ ++MIPS_MACHINE(AR71XX_MACH_RB_750, "750i", "MikroTik RouterBOARD 750", ++ rb750_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tew-632brp.c linux-2.6.36/arch/mips/ar71xx/mach-tew-632brp.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-tew-632brp.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-tew-632brp.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,149 @@ +/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * Special support for the Atheros ar8216 switch chip -+ * -+ * Copyright (C) 2009-2010 Gabor Juhos ++ * TrendNET TEW-632BRP board support + * -+ * Based on Atheros' AG7100 driver ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include "ag71xx.h" ++#include ++#include + -+#define AR8216_PACKET_TYPE_MASK 0xf -+#define AR8216_PACKET_TYPE_NORMAL 0 ++#include + -+#define AR8216_HEADER_LEN 2 ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "nvram.h" + -+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) ++#define TEW_632BRP_GPIO_LED_STATUS 1 ++#define TEW_632BRP_GPIO_LED_WPS 3 ++#define TEW_632BRP_GPIO_LED_WLAN 6 ++#define TEW_632BRP_GPIO_BTN_WPS 12 ++#define TEW_632BRP_GPIO_BTN_RESET 21 ++ ++#define TEW_632BRP_BUTTONS_POLL_INTERVAL 20 ++ ++#define TEW_632BRP_CONFIG_ADDR 0x1f020000 ++#define TEW_632BRP_CONFIG_SIZE 0x10000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tew_632brp_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "config", ++ .offset = 0x020000, ++ .size = 0x010000, ++ } , { ++ .name = "kernel", ++ .offset = 0x030000, ++ .size = 0x0d0000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x100000, ++ .size = 0x2f0000, ++ } , { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x030000, ++ .size = 0x3c0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tew_632brp_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tew_632brp_partitions, ++ .nr_parts = ARRAY_SIZE(tew_632brp_partitions), ++#endif ++}; ++ ++static struct gpio_led tew_632brp_leds_gpio[] __initdata = { ++ { ++ .name = "tew-632brp:green:status", ++ .gpio = TEW_632BRP_GPIO_LED_STATUS, ++ .active_low = 1, ++ }, { ++ .name = "tew-632brp:blue:wps", ++ .gpio = TEW_632BRP_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "tew-632brp:green:wlan", ++ .gpio = TEW_632BRP_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_button tew_632brp_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = TEW_632BRP_GPIO_BTN_RESET, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = TEW_632BRP_GPIO_BTN_WPS, ++ } ++}; ++ ++#define TEW_632BRP_LAN_PHYMASK BIT(0) ++#define TEW_632BRP_WAN_PHYMASK BIT(4) ++#define TEW_632BRP_MDIO_MASK (~(TEW_632BRP_LAN_PHYMASK | \ ++ TEW_632BRP_WAN_PHYMASK)) ++ ++static void __init tew_632brp_setup(void) +{ -+ skb_push(skb, AR8216_HEADER_LEN); -+ skb->data[0] = 0x10; -+ skb->data[1] = 0x80; -+} ++ const char *config = (char *) KSEG1ADDR(TEW_632BRP_CONFIG_ADDR); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 mac[6]; ++ u8 *wlan_mac = NULL; ++ ++ if (nvram_parse_mac_addr(config, TEW_632BRP_CONFIG_SIZE, ++ "lan_mac=", mac) == 0) { ++ ar71xx_set_mac_base(mac); ++ wlan_mac = mac; ++ } ++ ++ ar71xx_add_device_mdio(TEW_632BRP_MDIO_MASK); ++ ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.phy_mask = TEW_632BRP_LAN_PHYMASK; ++ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = TEW_632BRP_WAN_PHYMASK; + -+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, -+ int pktlen) -+{ -+ u8 type; ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ type = skb->data[1] & AR8216_PACKET_TYPE_MASK; -+ switch (type) { -+ case AR8216_PACKET_TYPE_NORMAL: -+ break; ++ ar71xx_add_device_m25p80(&tew_632brp_flash_data); + -+ default: -+ return -EINVAL; -+ } ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tew_632brp_leds_gpio), ++ tew_632brp_leds_gpio); + -+ skb_pull(skb, AR8216_HEADER_LEN); -+ return 0; ++ ar71xx_add_device_gpio_buttons(-1, TEW_632BRP_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(tew_632brp_gpio_buttons), ++ tew_632brp_gpio_buttons); ++ ++ ar913x_add_device_wmac(eeprom, wlan_mac); +} -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_debugfs.c linux-2.6.35.7/drivers/net/ag71xx/ag71xx_debugfs.c ---- linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/ag71xx_debugfs.c 2010-10-14 20:28:00.514356373 +0200 -@@ -0,0 +1,197 @@ ++ ++MIPS_MACHINE(AR71XX_MACH_TEW_632BRP, "TEW-632BRP", "TRENDnet TEW-632BRP", ++ tew_632brp_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c linux-2.6.36/arch/mips/ar71xx/mach-tl-wr1043nd.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr1043nd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-tl-wr1043nd.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,156 @@ +/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz ++ * TP-LINK TL-WR1043ND board support + * -+ * Based on Atheros' AG7100 driver ++ * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include -+ -+#include "ag71xx.h" -+ -+static struct dentry *ag71xx_debugfs_root; ++#include ++#include ++#include ++#include ++#include + -+static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) -+{ -+ file->private_data = inode->i_private; -+ return 0; -+} ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) -+{ -+ if (status) -+ ag->debug.int_stats.total++; -+ if (status & AG71XX_INT_TX_PS) -+ ag->debug.int_stats.tx_ps++; -+ if (status & AG71XX_INT_TX_UR) -+ ag->debug.int_stats.tx_ur++; -+ if (status & AG71XX_INT_TX_BE) -+ ag->debug.int_stats.tx_be++; -+ if (status & AG71XX_INT_RX_PR) -+ ag->debug.int_stats.rx_pr++; -+ if (status & AG71XX_INT_RX_OF) -+ ag->debug.int_stats.rx_of++; -+ if (status & AG71XX_INT_RX_BE) -+ ag->debug.int_stats.rx_be++; -+} ++#define TL_WR1043ND_GPIO_LED_USB 1 ++#define TL_WR1043ND_GPIO_LED_SYSTEM 2 ++#define TL_WR1043ND_GPIO_LED_QSS 5 ++#define TL_WR1043ND_GPIO_LED_WLAN 9 + -+static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) -+{ -+#define PR_INT_STAT(_label, _field) \ -+ len += snprintf(buf + len, sizeof(buf) - len, \ -+ "%20s: %10lu\n", _label, ag->debug.int_stats._field); ++#define TL_WR1043ND_GPIO_BTN_RESET 3 ++#define TL_WR1043ND_GPIO_BTN_QSS 7 + -+ struct ag71xx *ag = file->private_data; -+ char buf[256]; -+ unsigned int len = 0; ++#define TL_WR1043ND_GPIO_RTL8366_SDA 18 ++#define TL_WR1043ND_GPIO_RTL8366_SCK 19 + -+ PR_INT_STAT("TX Packet Sent", tx_ps); -+ PR_INT_STAT("TX Underrun", tx_ur); -+ PR_INT_STAT("TX Bus Error", tx_be); -+ PR_INT_STAT("RX Packet Received", rx_pr); -+ PR_INT_STAT("RX Overflow", rx_of); -+ PR_INT_STAT("RX Bus Error", rx_be); -+ len += snprintf(buf + len, sizeof(buf) - len, "\n"); -+ PR_INT_STAT("Total", total); ++#define TL_WR1043ND_BUTTONS_POLL_INTERVAL 20 + -+ return simple_read_from_buffer(user_buf, count, ppos, buf, len); -+#undef PR_INT_STAT -+} ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wr1043nd_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x690000, ++ } , { ++ .name = "art", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x7d0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+static const struct file_operations ag71xx_fops_int_stats = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_int_stats, -+ .owner = THIS_MODULE ++static struct flash_platform_data tl_wr1043nd_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wr1043nd_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wr1043nd_partitions), ++#endif +}; + -+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) -+{ -+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; ++static struct gpio_led tl_wr1043nd_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wr1043nd:green:usb", ++ .gpio = TL_WR1043ND_GPIO_LED_USB, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr1043nd:green:system", ++ .gpio = TL_WR1043ND_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr1043nd:green:qss", ++ .gpio = TL_WR1043ND_GPIO_LED_QSS, ++ .active_low = 0, ++ }, { ++ .name = "tl-wr1043nd:green:wlan", ++ .gpio = TL_WR1043ND_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; + -+ if (rx) { -+ stats->rx_count++; -+ stats->rx_packets += rx; -+ if (rx <= AG71XX_NAPI_WEIGHT) -+ stats->rx[rx]++; -+ if (rx > stats->rx_packets_max) -+ stats->rx_packets_max = rx; ++static struct gpio_button tl_wr1043nd_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = TL_WR1043ND_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = TL_WR1043ND_GPIO_BTN_QSS, ++ .active_low = 1, + } ++}; + -+ if (tx) { -+ stats->tx_count++; -+ stats->tx_packets += tx; -+ if (tx <= AG71XX_NAPI_WEIGHT) -+ stats->tx[tx]++; -+ if (tx > stats->tx_packets_max) -+ stats->tx_packets_max = tx; ++static struct rtl8366rb_platform_data tl_wr1043nd_rtl8366rb_data = { ++ .gpio_sda = TL_WR1043ND_GPIO_RTL8366_SDA, ++ .gpio_sck = TL_WR1043ND_GPIO_RTL8366_SCK, ++}; ++ ++static struct platform_device tl_wr1043nd_rtl8366rb_device = { ++ .name = RTL8366RB_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &tl_wr1043nd_rtl8366rb_data, + } -+} ++}; + -+static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, -+ size_t count, loff_t *ppos) ++static void __init tl_wr1043nd_setup(void) +{ -+ struct ag71xx *ag = file->private_data; -+ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; -+ char buf[2048]; -+ unsigned int len = 0; -+ unsigned long rx_avg = 0; -+ unsigned long tx_avg = 0; -+ int i; ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+ if (stats->rx_count) -+ rx_avg = stats->rx_packets / stats->rx_count; ++ ar71xx_set_mac_base(mac); + -+ if (stats->tx_count) -+ tx_avg = stats->tx_packets / stats->tx_count; ++ ar71xx_eth0_data.mii_bus_dev = &tl_wr1043nd_rtl8366rb_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_pll_data.pll_1000 = 0x1a000000; + -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s %10s %10s\n", -+ "len", "rx", "tx"); ++ ar71xx_add_device_eth(0); + -+ for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) -+ len += snprintf(buf + len, sizeof(buf) - len, -+ "%3d: %10lu %10lu\n", -+ i, stats->rx[i], stats->tx[i]); ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_m25p80(&tl_wr1043nd_flash_data); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr1043nd_leds_gpio), ++ tl_wr1043nd_leds_gpio); ++ ++ platform_device_register(&tl_wr1043nd_rtl8366rb_device); ++ ++ ar71xx_add_device_gpio_buttons(-1, TL_WR1043ND_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wr1043nd_gpio_buttons), ++ tl_wr1043nd_gpio_buttons); ++ ++ ar913x_add_device_wmac(eeprom, mac); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_TL_WR1043ND, "TL-WR1043ND", "TP-LINK TL-WR1043ND", ++ tl_wr1043nd_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr741nd.c linux-2.6.36/arch/mips/ar71xx/mach-tl-wr741nd.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr741nd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-tl-wr741nd.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,115 @@ ++/* ++ * TP-LINK TL-WR741ND board support ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ len += snprintf(buf + len, sizeof(buf) - len, "\n"); ++#include ++#include + -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "sum", stats->rx_count, stats->tx_count); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "avg", rx_avg, tx_avg); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "max", stats->rx_packets_max, stats->tx_packets_max); -+ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", -+ "pkt", stats->rx_packets, stats->tx_packets); ++#include + -+ return simple_read_from_buffer(user_buf, count, ppos, buf, len); -+} ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-eth.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" + -+static const struct file_operations ag71xx_fops_napi_stats = { -+ .open = ag71xx_debugfs_generic_open, -+ .read = read_file_napi_stats, -+ .owner = THIS_MODULE -+}; ++#define TL_WR741ND_GPIO_LED_QSS 0 ++#define TL_WR741ND_GPIO_LED_SYSTEM 1 + -+void ag71xx_debugfs_exit(struct ag71xx *ag) -+{ -+ debugfs_remove(ag->debug.debugfs_napi_stats); -+ debugfs_remove(ag->debug.debugfs_int_stats); -+ debugfs_remove(ag->debug.debugfs_dir); -+} ++#define TL_WR741ND_GPIO_BTN_RESET 11 ++#define TL_WR741ND_GPIO_BTN_QSS 12 + -+int ag71xx_debugfs_init(struct ag71xx *ag) -+{ -+ ag->debug.debugfs_dir = debugfs_create_dir(ag->dev->name, -+ ag71xx_debugfs_root); -+ if (!ag->debug.debugfs_dir) -+ goto err; ++#define TL_WR741ND_BUTTONS_POLL_INTERVAL 20 + -+ ag->debug.debugfs_int_stats = -+ debugfs_create_file("int_stats", -+ S_IRUGO, -+ ag->debug.debugfs_dir, -+ ag, -+ &ag71xx_fops_int_stats); -+ if (!ag->debug.debugfs_int_stats) -+ goto err; ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wr741nd_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x290000, ++ } , { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3d0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+ ag->debug.debugfs_napi_stats = -+ debugfs_create_file("napi_stats", -+ S_IRUGO, -+ ag->debug.debugfs_dir, -+ ag, -+ &ag71xx_fops_napi_stats); -+ if (!ag->debug.debugfs_napi_stats) -+ goto err; ++static struct flash_platform_data tl_wr741nd_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wr741nd_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wr741nd_partitions), ++#endif ++}; + -+ return 0; ++static struct gpio_led tl_wr741nd_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wr741nd:green:system", ++ .gpio = TL_WR741ND_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr741nd:green:qss", ++ .gpio = TL_WR741ND_GPIO_LED_QSS, ++ .active_low = 1, ++ } ++}; + -+ err: -+ ag71xx_debugfs_exit(ag); -+ return -ENOMEM; -+} ++static struct gpio_button tl_wr741nd_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = TL_WR741ND_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = TL_WR741ND_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; + -+int ag71xx_debugfs_root_init(void) ++static void __init tl_wr741nd_setup(void) +{ -+ if (ag71xx_debugfs_root) -+ return -EBUSY; ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + -+ ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); -+ if (!ag71xx_debugfs_root) -+ return -ENOENT; ++ ar71xx_add_device_m25p80(&tl_wr741nd_flash_data); + -+ return 0; -+} ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr741nd_leds_gpio), ++ tl_wr741nd_leds_gpio); + -+void ag71xx_debugfs_root_exit(void) -+{ -+ debugfs_remove(ag71xx_debugfs_root); -+ ag71xx_debugfs_root = NULL; ++ ar71xx_add_device_gpio_buttons(-1, TL_WR741ND_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wr741nd_gpio_buttons), ++ tl_wr741nd_gpio_buttons); ++ ++ ap91_eth_init(mac, NULL); ++ ap91_pci_init(ee, mac); +} -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_ethtool.c linux-2.6.35.7/drivers/net/ag71xx/ag71xx_ethtool.c ---- linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_ethtool.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/ag71xx_ethtool.c 2010-10-14 20:28:00.558101160 +0200 -@@ -0,0 +1,71 @@ ++MIPS_MACHINE(AR71XX_MACH_TL_WR741ND, "TL-WR741ND", "TP-LINK TL-WR741ND", ++ tl_wr741nd_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr841n.c linux-2.6.36/arch/mips/ar71xx/mach-tl-wr841n.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr841n.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-tl-wr841n.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,143 @@ +/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz ++ * TP-LINK TL-WR841N board support + * -+ * Based on Atheros' AG7100 driver ++ * Copyright (C) 2009 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include "ag71xx.h" ++#include ++#include + -+static int ag71xx_ethtool_get_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; ++#include ++ ++#include "machtype.h" ++#include "devices.h" ++#include "dev-dsa.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-leds-gpio.h" ++ ++#define TL_WR841ND_V1_GPIO_LED_SYSTEM 2 ++#define TL_WR841ND_V1_GPIO_LED_QSS_GREEN 4 ++#define TL_WR841ND_V1_GPIO_LED_QSS_RED 5 ++ ++#define TL_WR841ND_V1_GPIO_BTN_RESET 3 ++#define TL_WR841ND_V1_GPIO_BTN_QSS 7 ++ ++#define TL_WR841ND_V1_BUTTONS_POLL_INTERVAL 20 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wr841n_v1_partitions[] = { ++ { ++ .name = "redboot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x280000, ++ } , { ++ .name = "config", ++ .offset = 0x3e0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3c0000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data tl_wr841n_v1_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wr841n_v1_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wr841n_v1_partitions), ++#endif ++}; ++ ++static struct gpio_led tl_wr841n_v1_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wr841n:green:system", ++ .gpio = TL_WR841ND_V1_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr841n:red:qss", ++ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_RED, ++ }, { ++ .name = "tl-wr841n:green:qss", ++ .gpio = TL_WR841ND_V1_GPIO_LED_QSS_GREEN, ++ } ++}; ++ ++static struct gpio_button tl_wr841n_v1_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = TL_WR841ND_V1_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = TL_WR841ND_V1_GPIO_BTN_QSS, ++ .active_low = 1, ++ } ++}; + -+ if (!phydev) -+ return -ENODEV; ++static struct dsa_chip_data tl_wr841n_v1_dsa_chip = { ++ .port_names[0] = "wan", ++ .port_names[1] = "lan1", ++ .port_names[2] = "lan2", ++ .port_names[3] = "lan3", ++ .port_names[4] = "lan4", ++ .port_names[5] = "cpu", ++}; + -+ return phy_ethtool_gset(phydev, cmd); -+} ++static struct dsa_platform_data tl_wr841n_v1_dsa_data = { ++ .nr_chips = 1, ++ .chip = &tl_wr841n_v1_dsa_chip, ++}; + -+static int ag71xx_ethtool_set_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) ++static void __init tl_wr841n_v1_setup(void) +{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); + -+ if (!phydev) -+ return -ENODEV; ++ ar71xx_set_mac_base(mac); + -+ return phy_ethtool_sset(phydev, cmd); -+} ++ ar71xx_add_device_mdio(0x0); + -+static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, -+ struct ethtool_drvinfo *info) -+{ -+ struct ag71xx *ag = netdev_priv(dev); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+ strcpy(info->driver, ag->pdev->dev.driver->name); -+ strcpy(info->version, AG71XX_DRV_VERSION); -+ strcpy(info->bus_info, dev_name(&ag->pdev->dev)); -+} ++ ar71xx_add_device_eth(0); + -+static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); ++ ar71xx_add_device_dsa(0, &tl_wr841n_v1_dsa_data); + -+ return ag->msg_enable; -+} ++ ar71xx_add_device_m25p80(&tl_wr841n_v1_flash_data); + -+static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) -+{ -+ struct ag71xx *ag = netdev_priv(dev); ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v1_leds_gpio), ++ tl_wr841n_v1_leds_gpio); + -+ ag->msg_enable = msg_level; ++ ar71xx_add_device_gpio_buttons(-1, TL_WR841ND_V1_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wr841n_v1_gpio_buttons), ++ tl_wr841n_v1_gpio_buttons); ++ ++ pb42_pci_init(); +} + -+struct ethtool_ops ag71xx_ethtool_ops = { -+ .set_settings = ag71xx_ethtool_set_settings, -+ .get_settings = ag71xx_ethtool_get_settings, -+ .get_drvinfo = ag71xx_ethtool_get_drvinfo, -+ .get_msglevel = ag71xx_ethtool_get_msglevel, -+ .set_msglevel = ag71xx_ethtool_set_msglevel, -+ .get_link = ethtool_op_get_link, -+}; -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx.h linux-2.6.35.7/drivers/net/ag71xx/ag71xx.h ---- linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/ag71xx.h 2010-10-14 20:28:00.594356402 +0200 -@@ -0,0 +1,500 @@ ++MIPS_MACHINE(AR71XX_MACH_TL_WR841N_V1, "TL-WR841N-v1.5", "TP-LINK TL-WR841N v1", ++ tl_wr841n_v1_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr941nd.c linux-2.6.36/arch/mips/ar71xx/mach-tl-wr941nd.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-tl-wr941nd.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-tl-wr941nd.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,142 @@ +/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz ++ * TP-LINK TL-WR941ND board support + * -+ * Based on Atheros' AG7100 driver ++ * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#ifndef __AG71XX_H -+#define __AG71XX_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include ++#include ++#include + +#include -+#include -+ -+#define ETH_FCS_LEN 4 -+ -+#define AG71XX_DRV_NAME "ag71xx" -+#define AG71XX_DRV_VERSION "0.5.35" -+ -+#define AG71XX_NAPI_WEIGHT 64 -+#define AG71XX_OOM_REFILL (1 + HZ/10) -+ -+#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) -+#define AG71XX_INT_TX (AG71XX_INT_TX_PS) -+#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) -+ -+#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) -+#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) -+ -+#define AG71XX_TX_FIFO_LEN 2048 -+#define AG71XX_TX_MTU_LEN 1536 -+#define AG71XX_RX_PKT_RESERVE 64 -+#define AG71XX_RX_PKT_SIZE \ -+ (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN) -+ -+#define AG71XX_TX_RING_SIZE 64 -+#define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4) -+#define AG71XX_TX_THRES_WAKEUP \ -+ (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4)) -+ -+#define AG71XX_RX_RING_SIZE 128 + -+#ifdef CONFIG_AG71XX_DEBUG -+#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) -+#else -+#define DBG(fmt, args...) do {} while (0) -+#endif ++#include "machtype.h" ++#include "devices.h" ++#include "dev-dsa.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" + -+#define ag71xx_assert(_cond) \ -+do { \ -+ if (_cond) \ -+ break; \ -+ printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ -+ BUG(); \ -+} while (0) ++#define TL_WR941ND_GPIO_LED_SYSTEM 2 ++#define TL_WR941ND_GPIO_LED_QSS_RED 4 ++#define TL_WR941ND_GPIO_LED_QSS_GREEN 5 + -+struct ag71xx_desc { -+ u32 data; -+ u32 ctrl; -+#define DESC_EMPTY BIT(31) -+#define DESC_MORE BIT(24) -+#define DESC_PKTLEN_M 0xfff -+ u32 next; -+ u32 pad; -+} __attribute__((aligned(4))); ++#define TL_WR941ND_GPIO_BTN_RESET 3 ++#define TL_WR941ND_GPIO_BTN_QSS 7 + -+struct ag71xx_buf { -+ struct sk_buff *skb; -+ struct ag71xx_desc *desc; -+ dma_addr_t dma_addr; -+ u32 pad; -+}; ++#define TL_WR941ND_BUTTONS_POLL_INTERVAL 20 + -+struct ag71xx_ring { -+ struct ag71xx_buf *buf; -+ u8 *descs_cpu; -+ dma_addr_t descs_dma; -+ unsigned int desc_size; -+ unsigned int curr; -+ unsigned int dirty; -+ unsigned int size; ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition tl_wr941nd_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "kernel", ++ .offset = 0x020000, ++ .size = 0x140000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x160000, ++ .size = 0x290000, ++ } , { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x020000, ++ .size = 0x3d0000, ++ } +}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+struct ag71xx_mdio { -+ struct mii_bus *mii_bus; -+ int mii_irq[PHY_MAX_ADDR]; -+ void __iomem *mdio_base; -+ struct ag71xx_mdio_platform_data *pdata; ++static struct flash_platform_data tl_wr941nd_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = tl_wr941nd_partitions, ++ .nr_parts = ARRAY_SIZE(tl_wr941nd_partitions), ++#endif +}; + -+struct ag71xx_int_stats { -+ unsigned long rx_pr; -+ unsigned long rx_be; -+ unsigned long rx_of; -+ unsigned long tx_ps; -+ unsigned long tx_be; -+ unsigned long tx_ur; -+ unsigned long total; ++static struct gpio_led tl_wr941nd_leds_gpio[] __initdata = { ++ { ++ .name = "tl-wr941nd:green:system", ++ .gpio = TL_WR941ND_GPIO_LED_SYSTEM, ++ .active_low = 1, ++ }, { ++ .name = "tl-wr941nd:red:qss", ++ .gpio = TL_WR941ND_GPIO_LED_QSS_RED, ++ }, { ++ .name = "tl-wr941nd:green:qss", ++ .gpio = TL_WR941ND_GPIO_LED_QSS_GREEN, ++ } +}; + -+struct ag71xx_napi_stats { -+ unsigned long napi_calls; -+ unsigned long rx_count; -+ unsigned long rx_packets; -+ unsigned long rx_packets_max; -+ unsigned long tx_count; -+ unsigned long tx_packets; -+ unsigned long tx_packets_max; -+ -+ unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; -+ unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; ++static struct gpio_button tl_wr941nd_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = TL_WR941ND_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "qss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = TL_WR941ND_GPIO_BTN_QSS, ++ .active_low = 1, ++ } +}; + -+struct ag71xx_debug { -+ struct dentry *debugfs_dir; -+ struct dentry *debugfs_int_stats; -+ struct dentry *debugfs_napi_stats; -+ -+ struct ag71xx_int_stats int_stats; -+ struct ag71xx_napi_stats napi_stats; ++static struct dsa_chip_data tl_wr941nd_dsa_chip = { ++ .port_names[0] = "wan", ++ .port_names[1] = "lan1", ++ .port_names[2] = "lan2", ++ .port_names[3] = "lan3", ++ .port_names[4] = "lan4", ++ .port_names[5] = "cpu", +}; + -+struct ag71xx { -+ void __iomem *mac_base; -+ void __iomem *mii_ctrl; -+ -+ spinlock_t lock; -+ struct platform_device *pdev; -+ struct net_device *dev; -+ struct napi_struct napi; -+ u32 msg_enable; -+ -+ struct ag71xx_ring rx_ring; -+ struct ag71xx_ring tx_ring; -+ -+ struct mii_bus *mii_bus; -+ struct phy_device *phy_dev; ++static struct dsa_platform_data tl_wr941nd_dsa_data = { ++ .nr_chips = 1, ++ .chip = &tl_wr941nd_dsa_chip, ++}; + -+ unsigned int link; -+ unsigned int speed; -+ int duplex; ++static void __init tl_wr941nd_setup(void) ++{ ++ u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+ struct work_struct restart_work; -+ struct timer_list oom_timer; ++ ar71xx_set_mac_base(mac); + -+#ifdef CONFIG_AG71XX_DEBUG_FS -+ struct ag71xx_debug debug; -+#endif -+}; ++ ar71xx_add_device_mdio(0x0); + -+extern struct ethtool_ops ag71xx_ethtool_ops; -+void ag71xx_link_adjust(struct ag71xx *ag); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+int ag71xx_mdio_driver_init(void) __init; -+void ag71xx_mdio_driver_exit(void); ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_dsa(0, &tl_wr941nd_dsa_data); + -+int ag71xx_phy_connect(struct ag71xx *ag); -+void ag71xx_phy_disconnect(struct ag71xx *ag); -+void ag71xx_phy_start(struct ag71xx *ag); -+void ag71xx_phy_stop(struct ag71xx *ag); ++ ar71xx_add_device_m25p80(&tl_wr941nd_flash_data); + -+static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) -+{ -+ return ag->pdev->dev.platform_data; -+} ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(tl_wr941nd_leds_gpio), ++ tl_wr941nd_leds_gpio); + -+static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) -+{ -+ return ((desc->ctrl & DESC_EMPTY) != 0); ++ ar71xx_add_device_gpio_buttons(-1, TL_WR941ND_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(tl_wr941nd_gpio_buttons), ++ tl_wr941nd_gpio_buttons); ++ ar913x_add_device_wmac(eeprom, mac); +} + -+static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) -+{ -+ return (desc->ctrl & DESC_PKTLEN_M); -+} ++MIPS_MACHINE(AR71XX_MACH_TL_WR941ND, "TL-WR941ND", "TP-LINK TL-WR941ND", ++ tl_wr941nd_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-ubnt.c linux-2.6.36/arch/mips/ar71xx/mach-ubnt.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-ubnt.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-ubnt.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,281 @@ ++/* ++ * Ubiquiti RouterStation support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * Copyright (C) 2008 Ubiquiti ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+/* Register offsets */ -+#define AG71XX_REG_MAC_CFG1 0x0000 -+#define AG71XX_REG_MAC_CFG2 0x0004 -+#define AG71XX_REG_MAC_IPG 0x0008 -+#define AG71XX_REG_MAC_HDX 0x000c -+#define AG71XX_REG_MAC_MFL 0x0010 -+#define AG71XX_REG_MII_CFG 0x0020 -+#define AG71XX_REG_MII_CMD 0x0024 -+#define AG71XX_REG_MII_ADDR 0x0028 -+#define AG71XX_REG_MII_CTRL 0x002c -+#define AG71XX_REG_MII_STATUS 0x0030 -+#define AG71XX_REG_MII_IND 0x0034 -+#define AG71XX_REG_MAC_IFCTL 0x0038 -+#define AG71XX_REG_MAC_ADDR1 0x0040 -+#define AG71XX_REG_MAC_ADDR2 0x0044 -+#define AG71XX_REG_FIFO_CFG0 0x0048 -+#define AG71XX_REG_FIFO_CFG1 0x004c -+#define AG71XX_REG_FIFO_CFG2 0x0050 -+#define AG71XX_REG_FIFO_CFG3 0x0054 -+#define AG71XX_REG_FIFO_CFG4 0x0058 -+#define AG71XX_REG_FIFO_CFG5 0x005c -+#define AG71XX_REG_FIFO_RAM0 0x0060 -+#define AG71XX_REG_FIFO_RAM1 0x0064 -+#define AG71XX_REG_FIFO_RAM2 0x0068 -+#define AG71XX_REG_FIFO_RAM3 0x006c -+#define AG71XX_REG_FIFO_RAM4 0x0070 -+#define AG71XX_REG_FIFO_RAM5 0x0074 -+#define AG71XX_REG_FIFO_RAM6 0x0078 -+#define AG71XX_REG_FIFO_RAM7 0x007c ++#include + -+#define AG71XX_REG_TX_CTRL 0x0180 -+#define AG71XX_REG_TX_DESC 0x0184 -+#define AG71XX_REG_TX_STATUS 0x0188 -+#define AG71XX_REG_RX_CTRL 0x018c -+#define AG71XX_REG_RX_DESC 0x0190 -+#define AG71XX_REG_RX_STATUS 0x0194 -+#define AG71XX_REG_INT_ENABLE 0x0198 -+#define AG71XX_REG_INT_STATUS 0x019c ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap91-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-pb42-pci.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ -+#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ -+#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ -+#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ -+#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ -+#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ -+#define MAC_CFG1_LB BIT(8) /* Loopback mode */ -+#define MAC_CFG1_SR BIT(31) /* Soft Reset */ ++#define UBNT_RS_GPIO_LED_RF 2 ++#define UBNT_RS_GPIO_SW4 8 + -+#define MAC_CFG2_FDX BIT(0) -+#define MAC_CFG2_CRC_EN BIT(1) -+#define MAC_CFG2_PAD_CRC_EN BIT(2) -+#define MAC_CFG2_LEN_CHECK BIT(4) -+#define MAC_CFG2_HUGE_FRAME_EN BIT(5) -+#define MAC_CFG2_IF_1000 BIT(9) -+#define MAC_CFG2_IF_10_100 BIT(8) ++#define UBNT_LS_SR71_GPIO_LED_D25 0 ++#define UBNT_LS_SR71_GPIO_LED_D26 1 ++#define UBNT_LS_SR71_GPIO_LED_D24 2 ++#define UBNT_LS_SR71_GPIO_LED_D23 4 ++#define UBNT_LS_SR71_GPIO_LED_D22 5 ++#define UBNT_LS_SR71_GPIO_LED_D27 6 ++#define UBNT_LS_SR71_GPIO_LED_D28 7 + -+#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ -+#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ -+#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ -+#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ -+#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ -+#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ -+ | FIFO_CFG0_TXS | FIFO_CFG0_TXF) ++#define UBNT_M_GPIO_LED_L1 0 ++#define UBNT_M_GPIO_LED_L2 1 ++#define UBNT_M_GPIO_LED_L3 11 ++#define UBNT_M_GPIO_LED_L4 7 ++#define UBNT_M_GPIO_BTN_RESET 12 + -+#define FIFO_CFG0_ENABLE_SHIFT 8 ++#define UBNT_BUTTONS_POLL_INTERVAL 20 + -+#define FIFO_CFG4_DE BIT(0) /* Drop Event */ -+#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ -+#define FIFO_CFG4_FC BIT(2) /* False Carrier */ -+#define FIFO_CFG4_CE BIT(3) /* Code Error */ -+#define FIFO_CFG4_CR BIT(4) /* CRC error */ -+#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ -+#define FIFO_CFG4_LO BIT(6) /* Length out of range */ -+#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ -+#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ -+#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ -+#define FIFO_CFG4_DR BIT(10) /* Dribble */ -+#define FIFO_CFG4_LE BIT(11) /* Long Event */ -+#define FIFO_CFG4_CF BIT(12) /* Control Frame */ -+#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ -+#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ -+#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ -+#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ -+#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ ++static struct gpio_led ubnt_rs_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:rf", ++ .gpio = UBNT_RS_GPIO_LED_RF, ++ .active_low = 0, ++ } ++}; + -+#define FIFO_CFG5_DE BIT(0) /* Drop Event */ -+#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ -+#define FIFO_CFG5_FC BIT(2) /* False Carrier */ -+#define FIFO_CFG5_CE BIT(3) /* Code Error */ -+#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ -+#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ -+#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ -+#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ -+#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ -+#define FIFO_CFG5_DR BIT(9) /* Dribble */ -+#define FIFO_CFG5_CF BIT(10) /* Control Frame */ -+#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ -+#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ -+#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ -+#define FIFO_CFG5_LE BIT(14) /* Long Event */ -+#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ -+#define FIFO_CFG5_16 BIT(16) /* unknown */ -+#define FIFO_CFG5_17 BIT(17) /* unknown */ -+#define FIFO_CFG5_SF BIT(18) /* Short Frame */ -+#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ ++static struct gpio_led ubnt_ls_sr71_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:green:d22", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D22, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:d23", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D23, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:d24", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D24, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:red:d25", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D25, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:red:d26", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D26, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:d27", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D27, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:d28", ++ .gpio = UBNT_LS_SR71_GPIO_LED_D28, ++ .active_low = 0, ++ } ++}; + -+#define AG71XX_INT_TX_PS BIT(0) -+#define AG71XX_INT_TX_UR BIT(1) -+#define AG71XX_INT_TX_BE BIT(3) -+#define AG71XX_INT_RX_PR BIT(4) -+#define AG71XX_INT_RX_OF BIT(6) -+#define AG71XX_INT_RX_BE BIT(7) ++static struct gpio_led ubnt_m_leds_gpio[] __initdata = { ++ { ++ .name = "ubnt:red:link1", ++ .gpio = UBNT_M_GPIO_LED_L1, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:orange:link2", ++ .gpio = UBNT_M_GPIO_LED_L2, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:link3", ++ .gpio = UBNT_M_GPIO_LED_L3, ++ .active_low = 0, ++ }, { ++ .name = "ubnt:green:link4", ++ .gpio = UBNT_M_GPIO_LED_L4, ++ .active_low = 0, ++ } ++}; + -+#define MAC_IFCTL_SPEED BIT(16) ++static struct gpio_button ubnt_gpio_buttons[] __initdata = { ++ { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = UBNT_RS_GPIO_SW4, ++ .active_low = 1, ++ } ++}; + -+#define MII_CFG_CLK_DIV_4 0 -+#define MII_CFG_CLK_DIV_6 2 -+#define MII_CFG_CLK_DIV_8 3 -+#define MII_CFG_CLK_DIV_10 4 -+#define MII_CFG_CLK_DIV_14 5 -+#define MII_CFG_CLK_DIV_20 6 -+#define MII_CFG_CLK_DIV_28 7 -+#define MII_CFG_RESET BIT(31) ++static struct gpio_button ubnt_m_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = UBNT_M_GPIO_BTN_RESET, ++ .active_low = 1, ++ } ++}; + -+#define MII_CMD_WRITE 0x0 -+#define MII_CMD_READ 0x1 -+#define MII_ADDR_SHIFT 8 -+#define MII_IND_BUSY BIT(0) -+#define MII_IND_INVALID BIT(2) ++static void __init ubnt_generic_setup(void) ++{ ++ ar71xx_add_device_m25p80(NULL); + -+#define TX_CTRL_TXE BIT(0) /* Tx Enable */ ++ ar71xx_add_device_gpio_buttons(-1, UBNT_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_gpio_buttons), ++ ubnt_gpio_buttons); + -+#define TX_STATUS_PS BIT(0) /* Packet Sent */ -+#define TX_STATUS_UR BIT(1) /* Tx Underrun */ -+#define TX_STATUS_BE BIT(3) /* Bus Error */ ++ pb42_pci_init(); ++} + -+#define RX_CTRL_RXE BIT(0) /* Rx Enable */ ++#define UBNT_RS_WAN_PHYMASK (1 << 20) ++#define UBNT_RS_LAN_PHYMASK ((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19)) + -+#define RX_STATUS_PR BIT(0) /* Packet Received */ -+#define RX_STATUS_OF BIT(2) /* Rx Overflow */ -+#define RX_STATUS_BE BIT(3) /* Bus Error */ ++static void __init ubnt_rs_setup(void) ++{ ++ ubnt_generic_setup(); + -+#define MII_CTRL_IF_MASK 3 -+#define MII_CTRL_SPEED_SHIFT 4 -+#define MII_CTRL_SPEED_MASK 3 -+#define MII_CTRL_SPEED_10 0 -+#define MII_CTRL_SPEED_100 1 -+#define MII_CTRL_SPEED_1000 2 ++ ar71xx_add_device_mdio(~(UBNT_RS_WAN_PHYMASK | UBNT_RS_LAN_PHYMASK)); + -+static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) -+{ -+ switch (reg) { -+ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: -+ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: -+ break; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = UBNT_RS_WAN_PHYMASK; + -+ default: -+ BUG(); -+ } -+} ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_100; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; + -+static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) -+{ -+ ag71xx_check_reg_offset(ag, reg); ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ __raw_writel(value, ag->mac_base + reg); -+ /* flush write */ -+ (void) __raw_readl(ag->mac_base + reg); ++ ar71xx_add_device_usb(); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), ++ ubnt_rs_leds_gpio); +} + -+static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) -+{ -+ ag71xx_check_reg_offset(ag, reg); ++MIPS_MACHINE(AR71XX_MACH_UBNT_RS, "UBNT-RS", "Ubiquiti RouterStation", ++ ubnt_rs_setup); + -+ return __raw_readl(ag->mac_base + reg); -+} ++MIPS_MACHINE(AR71XX_MACH_UBNT_AR71XX, "Ubiquiti AR71xx-based board", ++ "Ubiquiti RouterStation", ubnt_rs_setup); + -+static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) ++#define UBNT_RSPRO_WAN_PHYMASK (1 << 4) ++#define UBNT_RSPRO_LAN_PHYMASK ((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) ++ ++static void __init ubnt_rspro_setup(void) +{ -+ void __iomem *r; ++ ubnt_generic_setup(); + -+ ag71xx_check_reg_offset(ag, reg); ++ ar71xx_add_device_mdio(~(UBNT_RSPRO_WAN_PHYMASK | UBNT_RSPRO_LAN_PHYMASK)); + -+ r = ag->mac_base + reg; -+ __raw_writel(__raw_readl(r) | mask, r); -+ /* flush write */ -+ (void)__raw_readl(r); -+} ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.phy_mask = UBNT_RSPRO_WAN_PHYMASK; + -+static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) -+{ -+ void __iomem *r; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = UBNT_RSPRO_LAN_PHYMASK; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; + -+ ag71xx_check_reg_offset(ag, reg); ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ r = ag->mac_base + reg; -+ __raw_writel(__raw_readl(r) & ~mask, r); -+ /* flush write */ -+ (void) __raw_readl(r); -+} ++ ar71xx_add_device_usb(); + -+static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) -+{ -+ ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_rs_leds_gpio), ++ ubnt_rs_leds_gpio); +} + -+static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) ++MIPS_MACHINE(AR71XX_MACH_UBNT_RSPRO, "UBNT-RSPRO", "Ubiquiti RouterStation Pro", ++ ubnt_rspro_setup); ++ ++static void __init ubnt_lsx_setup(void) +{ -+ ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); ++ ubnt_generic_setup(); +} + -+static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value) ++MIPS_MACHINE(AR71XX_MACH_UBNT_LSX, "UBNT-LSX", "Ubiquiti LSX", ubnt_lsx_setup); ++ ++#define UBNT_LSSR71_PHY_MASK (1 << 1) ++ ++static void __init ubnt_lssr71_setup(void) +{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ ubnt_generic_setup(); + -+ if (pdata->is_ar724x) -+ return; ++ ar71xx_add_device_mdio(~UBNT_LSSR71_PHY_MASK); + -+ __raw_writel(value, ag->mii_ctrl); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = UBNT_LSSR71_PHY_MASK; + -+ /* flush write */ -+ __raw_readl(ag->mii_ctrl); ++ ar71xx_add_device_eth(0); ++ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_ls_sr71_leds_gpio), ++ ubnt_ls_sr71_leds_gpio); +} + -+static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag) ++MIPS_MACHINE(AR71XX_MACH_UBNT_LSSR71, "UBNT-LS-SR71", "Ubiquiti LS-SR71", ++ ubnt_lssr71_setup); ++ ++static void __init ubnt_m_setup(void) +{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ u8 *mac = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000); + -+ if (pdata->is_ar724x) -+ return 0xffffffff; ++ ar71xx_set_mac_base(mac); + -+ return __raw_readl(ag->mii_ctrl); -+} ++ ar71xx_add_device_m25p80(NULL); + -+static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag, -+ unsigned int mii_if) -+{ -+ u32 t; ++ ar71xx_add_device_mdio(~0); + -+ t = ag71xx_mii_ctrl_rr(ag); -+ t &= ~(MII_CTRL_IF_MASK); -+ t |= (mii_if & MII_CTRL_IF_MASK); -+ ag71xx_mii_ctrl_wr(ag, t); -+} ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.fifo_cfg1 = 0x0010ffff; ++ ar71xx_eth0_data.fifo_cfg2 = 0x015500aa; ++ ar71xx_eth0_data.fifo_cfg3 = 0x01f00140; + -+static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, -+ unsigned int speed) -+{ -+ u32 t; ++ ar71xx_add_device_eth(0); + -+ t = ag71xx_mii_ctrl_rr(ag); -+ t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); -+ t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; -+ ag71xx_mii_ctrl_wr(ag, t); -+} ++ ap91_pci_init(ee, NULL); + -+#ifdef CONFIG_AG71XX_AR8216_SUPPORT -+void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); -+int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, -+ int pktlen); -+static inline int ag71xx_has_ar8216(struct ag71xx *ag) -+{ -+ return ag71xx_get_pdata(ag)->has_ar8216; -+} -+#else -+static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, -+ struct sk_buff *skb) -+{ ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_m_leds_gpio), ++ ubnt_m_leds_gpio); ++ ++ ar71xx_add_device_gpio_buttons(-1, UBNT_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(ubnt_m_gpio_buttons), ++ ubnt_m_gpio_buttons); +} + -+static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, -+ struct sk_buff *skb, -+ int pktlen) ++static void __init ubnt_rocket_m_setup(void) +{ -+ return 0; ++ ubnt_m_setup(); ++ ar71xx_add_device_usb(); +} -+static inline int ag71xx_has_ar8216(struct ag71xx *ag) ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_BULLET_M, "UBNT-BM", "Ubiquiti Bullet M", ++ ubnt_m_setup); ++MIPS_MACHINE(AR71XX_MACH_UBNT_ROCKET_M, "UBNT-RM", "Ubiquiti Rocket M", ++ ubnt_rocket_m_setup); ++ ++/* TODO detect the second ethernet port and use one ++ init function for all Ubiquiti MIMO series products */ ++static void __init ubnt_nano_m_setup(void) +{ -+ return 0; -+} -+#endif ++ ubnt_m_setup(); + -+#ifdef CONFIG_AG71XX_DEBUG_FS -+int ag71xx_debugfs_root_init(void); -+void ag71xx_debugfs_root_exit(void); -+int ag71xx_debugfs_init(struct ag71xx *ag); -+void ag71xx_debugfs_exit(struct ag71xx *ag); -+void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); -+void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); -+#else -+static inline int ag71xx_debugfs_root_init(void) { return 0; } -+static inline void ag71xx_debugfs_root_exit(void) {} -+static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } -+static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} -+static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, -+ u32 status) {} -+static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, -+ int rx, int tx) {} -+#endif /* CONFIG_AG71XX_DEBUG_FS */ ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.speed = SPEED_1000; ++ ar71xx_eth1_data.duplex = DUPLEX_FULL; ++ ar71xx_eth1_data.fifo_cfg1 = 0x0010ffff; ++ ar71xx_eth1_data.fifo_cfg2 = 0x015500aa; ++ ar71xx_eth1_data.fifo_cfg3 = 0x01f00140; + -+#endif /* _AG71XX_H */ -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_main.c linux-2.6.35.7/drivers/net/ag71xx/ag71xx_main.c ---- linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_main.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/ag71xx_main.c 2010-10-14 20:28:00.638101269 +0200 -@@ -0,0 +1,1184 @@ ++ ar71xx_add_device_eth(1); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_UBNT_NANO_M, "UBNT-NM", "Ubiquiti Nanostation M", ++ ubnt_nano_m_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wndr3700.c linux-2.6.36/arch/mips/ar71xx/mach-wndr3700.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-wndr3700.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-wndr3700.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,209 @@ +/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz ++ * Netgear WNDR3700 board support + * -+ * Based on Atheros' AG7100 driver ++ * Copyright (C) 2009 Marco Porsch ++ * Copyright (C) 2009-2010 Gabor Juhos + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include "ag71xx.h" ++#include ++#include ++#include ++#include ++#include + -+#define AG71XX_DEFAULT_MSG_ENABLE \ -+ ( NETIF_MSG_DRV \ -+ | NETIF_MSG_PROBE \ -+ | NETIF_MSG_LINK \ -+ | NETIF_MSG_TIMER \ -+ | NETIF_MSG_IFDOWN \ -+ | NETIF_MSG_IFUP \ -+ | NETIF_MSG_RX_ERR \ -+ | NETIF_MSG_TX_ERR ) ++#include + -+static int ag71xx_msg_level = -1; ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ap94-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+module_param_named(msg_level, ag71xx_msg_level, int, 0); -+MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); ++#define WNDR3700_GPIO_LED_WPS_ORANGE 0 ++#define WNDR3700_GPIO_LED_POWER_ORANGE 1 ++#define WNDR3700_GPIO_LED_POWER_GREEN 2 ++#define WNDR3700_GPIO_LED_WPS_GREEN 4 ++#define WNDR3700_GPIO_LED_WAN_GREEN 6 + -+static void ag71xx_dump_dma_regs(struct ag71xx *ag) -+{ -+ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_TX_CTRL), -+ ag71xx_rr(ag, AG71XX_REG_TX_DESC), -+ ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); ++#define WNDR3700_GPIO_BTN_WPS 3 ++#define WNDR3700_GPIO_BTN_RESET 8 ++#define WNDR3700_GPIO_BTN_WIFI 11 + -+ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_RX_CTRL), -+ ag71xx_rr(ag, AG71XX_REG_RX_DESC), -+ ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); -+} ++#define WNDR3700_GPIO_RTL8366_SDA 5 ++#define WNDR3700_GPIO_RTL8366_SCK 7 + -+static void ag71xx_dump_regs(struct ag71xx *ag) -+{ -+ DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), -+ ag71xx_rr(ag, AG71XX_REG_MAC_IPG), -+ ag71xx_rr(ag, AG71XX_REG_MAC_HDX), -+ ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); -+ DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), -+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), -+ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); -+ DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); -+ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); -+} ++#define WNDR3700_BUTTONS_POLL_INTERVAL 20 + -+static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) -+{ -+ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", -+ ag->dev->name, label, intr, -+ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", -+ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", -+ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", -+ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", -+ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", -+ (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); -+} ++#define WNDR3700_WMAC0_MAC_OFFSET 0 ++#define WNDR3700_WMAC1_MAC_OFFSET 0xc ++#define WNDR3700_CALDATA0_OFFSET 0x1000 ++#define WNDR3700_CALDATA1_OFFSET 0x5000 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wndr3700_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0, ++ .size = 0x050000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "env", ++ .offset = 0x050000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "rootfs", ++ .offset = 0x070000, ++ .size = 0x720000, ++ } , { ++ .name = "config", ++ .offset = 0x790000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "config_bak", ++ .offset = 0x7a0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "pot", ++ .offset = 0x7b0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "traffic_meter", ++ .offset = 0x7c0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "language", ++ .offset = 0x7d0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "caldata", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ ++ ++static struct flash_platform_data wndr3700_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wndr3700_partitions, ++ .nr_parts = ARRAY_SIZE(wndr3700_partitions), ++#endif ++}; ++ ++static struct gpio_led wndr3700_leds_gpio[] __initdata = { ++ { ++ .name = "wndr3700:green:power", ++ .gpio = WNDR3700_GPIO_LED_POWER_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "wndr3700:orange:power", ++ .gpio = WNDR3700_GPIO_LED_POWER_ORANGE, ++ .active_low = 1, ++ }, { ++ .name = "wndr3700:green:wps", ++ .gpio = WNDR3700_GPIO_LED_WPS_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "wndr3700:orange:wps", ++ .gpio = WNDR3700_GPIO_LED_WPS_ORANGE, ++ .active_low = 1, ++ }, { ++ .name = "wndr3700:green:wan", ++ .gpio = WNDR3700_GPIO_LED_WAN_GREEN, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_button wndr3700_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = WNDR3700_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = WNDR3700_GPIO_BTN_WPS, ++ .active_low = 1, ++ } , { ++ .desc = "wifi", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .threshold = 3, ++ .gpio = WNDR3700_GPIO_BTN_WIFI, ++ .active_low = 1, ++ } ++}; ++ ++static struct rtl8366s_platform_data wndr3700_rtl8366s_data = { ++ .gpio_sda = WNDR3700_GPIO_RTL8366_SDA, ++ .gpio_sck = WNDR3700_GPIO_RTL8366_SCK, ++}; ++ ++static struct platform_device wndr3700_rtl8366s_device = { ++ .name = RTL8366S_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &wndr3700_rtl8366s_data, ++ } ++}; + -+static void ag71xx_ring_free(struct ag71xx_ring *ring) ++static void __init wndr3700_setup(void) +{ -+ kfree(ring->buf); ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); + -+ if (ring->descs_cpu) -+ dma_free_coherent(NULL, ring->size * ring->desc_size, -+ ring->descs_cpu, ring->descs_dma); -+} ++ ar71xx_set_mac_base(art); + -+static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size) -+{ -+ int err; -+ int i; ++ ar71xx_eth0_pll_data.pll_1000 = 0x11110000; ++ ar71xx_eth0_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+ ring->desc_size = sizeof(struct ag71xx_desc); -+ if (ring->desc_size % cache_line_size()) { -+ DBG("ag71xx: ring %p, desc size %u rounded to %u\n", -+ ring, ring->desc_size, -+ roundup(ring->desc_size, cache_line_size())); -+ ring->desc_size = roundup(ring->desc_size, cache_line_size()); -+ } ++ ar71xx_eth1_pll_data.pll_1000 = 0x11110000; ++ ar71xx_eth1_data.mii_bus_dev = &wndr3700_rtl8366s_device.dev; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = 0x10; + -+ ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size, -+ &ring->descs_dma, GFP_ATOMIC); -+ if (!ring->descs_cpu) { -+ err = -ENOMEM; -+ goto err; -+ } ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ ring->size = size; ++ ar71xx_add_device_usb(); + -+ ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL); -+ if (!ring->buf) { -+ err = -ENOMEM; -+ goto err; -+ } ++ ar71xx_add_device_m25p80(&wndr3700_flash_data); + -+ for (i = 0; i < size; i++) { -+ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size]; -+ DBG("ag71xx: ring %p, desc %d at %p\n", -+ ring, i, ring->buf[i].desc); -+ } ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wndr3700_leds_gpio), ++ wndr3700_leds_gpio); + -+ return 0; ++ ar71xx_add_device_gpio_buttons(-1, WNDR3700_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(wndr3700_gpio_buttons), ++ wndr3700_gpio_buttons); + -+ err: -+ return err; ++ platform_device_register(&wndr3700_rtl8366s_device); ++ platform_device_register_simple("wndr3700-led-usb", -1, NULL, 0); ++ ++ ap94_pci_enable_quirk_wndr3700(); ++ ap94_pci_init(art + WNDR3700_CALDATA0_OFFSET, ++ art + WNDR3700_WMAC0_MAC_OFFSET, ++ art + WNDR3700_CALDATA1_OFFSET, ++ art + WNDR3700_WMAC1_MAC_OFFSET); +} + -+static void ag71xx_ring_tx_clean(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct net_device *dev = ag->dev; ++MIPS_MACHINE(AR71XX_MACH_WNDR3700, "WNDR3700", "NETGEAR WNDR3700", ++ wndr3700_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wnr2000.c linux-2.6.36/arch/mips/ar71xx/mach-wnr2000.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-wnr2000.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-wnr2000.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,148 @@ ++/* ++ * NETGEAR WNR2000 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * Copyright (C) 2008-2009 Andy Boyett ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ while (ring->curr != ring->dirty) { -+ u32 i = ring->dirty % AG71XX_TX_RING_SIZE; ++#include ++#include + -+ if (!ag71xx_desc_empty(ring->buf[i].desc)) { -+ ring->buf[i].desc->ctrl = 0; -+ dev->stats.tx_errors++; -+ } ++#include + -+ if (ring->buf[i].skb) -+ dev_kfree_skb_any(ring->buf[i].skb); ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" + -+ ring->buf[i].skb = NULL; ++#define WNR2000_GPIO_LED_PWR_GREEN 14 ++#define WNR2000_GPIO_LED_PWR_AMBER 7 ++#define WNR2000_GPIO_LED_WPS 4 ++#define WNR2000_GPIO_LED_WLAN 6 ++#define WNR2000_GPIO_BTN_RESET 21 ++#define WNR2000_GPIO_BTN_WPS 8 + -+ ring->dirty++; ++#define WNR2000_BUTTONS_POLL_INTERVAL 20 ++ ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wnr2000_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "u-boot-env", ++ .offset = 0x040000, ++ .size = 0x010000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x050000, ++ .size = 0x240000, ++ } , { ++ .name = "user-config", ++ .offset = 0x290000, ++ .size = 0x010000, ++ } , { ++ .name = "uImage", ++ .offset = 0x2a0000, ++ .size = 0x120000, ++ } , { ++ .name = "language_table", ++ .offset = 0x3c0000, ++ .size = 0x020000, ++ } , { ++ .name = "rootfs_checksum", ++ .offset = 0x3e0000, ++ .size = 0x010000, ++ } , { ++ .name = "art", ++ .offset = 0x3f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, + } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+ /* flush descriptors */ -+ wmb(); ++static struct flash_platform_data wnr2000_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wnr2000_partitions, ++ .nr_parts = ARRAY_SIZE(wnr2000_partitions), ++#endif ++}; + -+} ++static struct gpio_led wnr2000_leds_gpio[] __initdata = { ++ { ++ .name = "wnr2000:green:power", ++ .gpio = WNR2000_GPIO_LED_PWR_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "wnr2000:amber:power", ++ .gpio = WNR2000_GPIO_LED_PWR_AMBER, ++ .active_low = 1, ++ }, { ++ .name = "wnr2000:green:wps", ++ .gpio = WNR2000_GPIO_LED_WPS, ++ .active_low = 1, ++ }, { ++ .name = "wnr2000:blue:wlan", ++ .gpio = WNR2000_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; + -+static void ag71xx_ring_tx_init(struct ag71xx *ag) ++static struct gpio_button wnr2000_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = WNR2000_GPIO_BTN_RESET, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = WNR2000_GPIO_BTN_WPS, ++ } ++}; ++ ++static void __init wnr2000_setup(void) +{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ int i; ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+ for (i = 0; i < AG71XX_TX_RING_SIZE; i++) { -+ ring->buf[i].desc->next = (u32) (ring->descs_dma + -+ ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE)); ++ ar71xx_set_mac_base(eeprom); ++ ar71xx_add_device_mdio(0x0); + -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ ring->buf[i].skb = NULL; -+ } ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; ++ ar71xx_eth0_data.has_ar8216 = 1; + -+ /* flush descriptors */ -+ wmb(); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x10; + -+ ring->curr = 0; -+ ring->dirty = 0; -+} ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+static void ag71xx_ring_rx_clean(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ int i; ++ ar71xx_add_device_m25p80(&wnr2000_flash_data); + -+ if (!ring->buf) -+ return; ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wnr2000_leds_gpio), ++ wnr2000_leds_gpio); + -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) -+ if (ring->buf[i].skb) { -+ dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, -+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); -+ kfree_skb(ring->buf[i].skb); -+ } -+} ++ ar71xx_add_device_gpio_buttons(-1, WNR2000_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(wnr2000_gpio_buttons), ++ wnr2000_gpio_buttons); + -+static int ag71xx_rx_reserve(struct ag71xx *ag) -+{ -+ int reserve = 0; + -+ if (ag71xx_get_pdata(ag)->is_ar724x) { -+ if (!ag71xx_has_ar8216(ag)) -+ reserve = 2; ++ ar913x_add_device_wmac(eeprom, NULL); ++} ++ ++MIPS_MACHINE(AR71XX_MACH_WNR2000, "WNR2000", "NETGEAR WNR2000", wnr2000_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wp543.c linux-2.6.36/arch/mips/ar71xx/mach-wp543.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-wp543.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-wp543.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,99 @@ ++/* ++ * Compex WP543/WPJ543 board support ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ if (ag->phy_dev) -+ reserve += 4 - (ag->phy_dev->pkt_align % 4); ++#include ++#include + -+ reserve %= 4; -+ } ++#include + -+ return reserve + AG71XX_RX_PKT_RESERVE; -+} ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-pb42-pci.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + ++#define WP543_GPIO_SW6 2 ++#define WP543_GPIO_LED_1 3 ++#define WP543_GPIO_LED_2 4 ++#define WP543_GPIO_LED_WLAN 5 ++#define WP543_GPIO_LED_CONN 6 ++#define WP543_GPIO_LED_DIAG 7 ++#define WP543_GPIO_SW4 8 + -+static int ag71xx_ring_rx_init(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ unsigned int reserve = ag71xx_rx_reserve(ag); -+ unsigned int i; -+ int ret; ++#define WP543_BUTTONS_POLL_INTERVAL 20 + -+ ret = 0; -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) { -+ ring->buf[i].desc->next = (u32) (ring->descs_dma + -+ ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE)); ++static struct gpio_led wp543_leds_gpio[] __initdata = { ++ { ++ .name = "wp543:green:led1", ++ .gpio = WP543_GPIO_LED_1, ++ .active_low = 1, ++ }, { ++ .name = "wp543:green:led2", ++ .gpio = WP543_GPIO_LED_2, ++ .active_low = 1, ++ }, { ++ .name = "wp543:green:wlan", ++ .gpio = WP543_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "wp543:green:conn", ++ .gpio = WP543_GPIO_LED_CONN, ++ .active_low = 1, ++ }, { ++ .name = "wp543:green:diag", ++ .gpio = WP543_GPIO_LED_DIAG, ++ .active_low = 1, ++ } ++}; + -+ DBG("ag71xx: RX desc at %p, next is %08x\n", -+ ring->buf[i].desc, -+ ring->buf[i].desc->next); ++static struct gpio_button wp543_gpio_buttons[] __initdata = { ++ { ++ .desc = "sw6", ++ .type = EV_KEY, ++ .code = BTN_0, ++ .threshold = 3, ++ .gpio = WP543_GPIO_SW6, ++ }, { ++ .desc = "sw4", ++ .type = EV_KEY, ++ .code = BTN_1, ++ .threshold = 3, ++ .gpio = WP543_GPIO_SW4, + } ++}; + -+ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) { -+ struct sk_buff *skb; -+ dma_addr_t dma_addr; ++static void __init wp543_setup(void) ++{ ++ ar71xx_add_device_m25p80(NULL); + -+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); -+ if (!skb) { -+ ret = -ENOMEM; -+ break; -+ } ++ ar71xx_add_device_mdio(0xfffffff7); + -+ skb->dev = ag->dev; -+ skb_reserve(skb, reserve); ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII; ++ ar71xx_eth0_data.phy_mask = 0x08; ++ ar71xx_eth0_data.reset_bit = RESET_MODULE_GE0_MAC | ++ RESET_MODULE_GE0_PHY; ++ ar71xx_add_device_eth(0); + -+ dma_addr = dma_map_single(&ag->dev->dev, skb->data, -+ AG71XX_RX_PKT_SIZE, -+ DMA_FROM_DEVICE); -+ ring->buf[i].skb = skb; -+ ring->buf[i].dma_addr = dma_addr; -+ ring->buf[i].desc->data = (u32) dma_addr; -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ } ++ ar71xx_add_device_usb(); + -+ /* flush descriptors */ -+ wmb(); ++ pb42_pci_init(); + -+ ring->curr = 0; -+ ring->dirty = 0; ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wp543_leds_gpio), ++ wp543_leds_gpio); + -+ return ret; ++ ar71xx_add_device_gpio_buttons(-1, WP543_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(wp543_gpio_buttons), ++ wp543_gpio_buttons); +} + -+static int ag71xx_ring_rx_refill(struct ag71xx *ag) -+{ -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ unsigned int reserve = ag71xx_rx_reserve(ag); -+ unsigned int count; ++MIPS_MACHINE(AR71XX_MACH_WP543, "WP543", "Compex WP543", wp543_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wrt160nl.c linux-2.6.36/arch/mips/ar71xx/mach-wrt160nl.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-wrt160nl.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-wrt160nl.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,158 @@ ++/* ++ * Linksys WRT160NL board support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ count = 0; -+ for (; ring->curr - ring->dirty > 0; ring->dirty++) { -+ unsigned int i; ++#include ++#include + -+ i = ring->dirty % AG71XX_RX_RING_SIZE; ++#include + -+ if (ring->buf[i].skb == NULL) { -+ dma_addr_t dma_addr; -+ struct sk_buff *skb; ++#include "machtype.h" ++#include "devices.h" ++#include "dev-m25p80.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" ++#include "nvram.h" + -+ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); -+ if (skb == NULL) -+ break; ++#define WRT160NL_GPIO_LED_POWER 14 ++#define WRT160NL_GPIO_LED_WPS_AMBER 9 ++#define WRT160NL_GPIO_LED_WPS_BLUE 8 ++#define WRT160NL_GPIO_LED_WLAN 6 + -+ skb_reserve(skb, reserve); -+ skb->dev = ag->dev; ++#define WRT160NL_GPIO_BTN_WPS 7 ++#define WRT160NL_GPIO_BTN_RESET 21 + -+ dma_addr = dma_map_single(&ag->dev->dev, skb->data, -+ AG71XX_RX_PKT_SIZE, -+ DMA_FROM_DEVICE); ++#define WRT160NL_BUTTONS_POLL_INTERVAL 20 + -+ ring->buf[i].skb = skb; -+ ring->buf[i].dma_addr = dma_addr; -+ ring->buf[i].desc->data = (u32) dma_addr; -+ } ++#define WRT160NL_NVRAM_ADDR 0x1f7e0000 ++#define WRT160NL_NVRAM_SIZE 0x10000 + -+ ring->buf[i].desc->ctrl = DESC_EMPTY; -+ count++; ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wrt160nl_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x040000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "kernel", ++ .offset = 0x040000, ++ .size = 0x0e0000, ++ } , { ++ .name = "filesytem", ++ .offset = 0x120000, ++ .size = 0x6c0000, ++ } , { ++ .name = "nvram", ++ .offset = 0x7e0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "ART", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x040000, ++ .size = 0x7a0000, + } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+ /* flush descriptors */ -+ wmb(); ++static struct flash_platform_data wrt160nl_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wrt160nl_partitions, ++ .nr_parts = ARRAY_SIZE(wrt160nl_partitions), ++#endif ++}; + -+ DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); ++static struct gpio_led wrt160nl_leds_gpio[] __initdata = { ++ { ++ .name = "wrt160nl:blue:power", ++ .gpio = WRT160NL_GPIO_LED_POWER, ++ .active_low = 1, ++ .default_trigger = "default-on", ++ }, { ++ .name = "wrt160nl:amber:wps", ++ .gpio = WRT160NL_GPIO_LED_WPS_AMBER, ++ .active_low = 1, ++ }, { ++ .name = "wrt160nl:blue:wps", ++ .gpio = WRT160NL_GPIO_LED_WPS_BLUE, ++ .active_low = 1, ++ }, { ++ .name = "wrt160nl:blue:wlan", ++ .gpio = WRT160NL_GPIO_LED_WLAN, ++ .active_low = 1, ++ } ++}; + -+ return count; -+} ++static struct gpio_button wrt160nl_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = WRT160NL_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "wps", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = WRT160NL_GPIO_BTN_WPS, ++ .active_low = 1, ++ } ++}; + -+static int ag71xx_rings_init(struct ag71xx *ag) ++static void __init wrt160nl_setup(void) +{ -+ int ret; ++ const char *nvram = (char *) KSEG1ADDR(WRT160NL_NVRAM_ADDR); ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); ++ u8 mac[6]; + -+ ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE); -+ if (ret) -+ return ret; ++ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, ++ "lan_hwaddr=", mac) == 0) ++ ar71xx_set_mac_base(mac); + -+ ag71xx_ring_tx_init(ag); ++ ar71xx_add_device_mdio(0x0); + -+ ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE); -+ if (ret) -+ return ret; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.phy_mask = 0x01; + -+ ret = ag71xx_ring_rx_init(ag); -+ return ret; -+} ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x10; + -+static void ag71xx_rings_cleanup(struct ag71xx *ag) -+{ -+ ag71xx_ring_rx_clean(ag); -+ ag71xx_ring_free(&ag->rx_ring); ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ ag71xx_ring_tx_clean(ag); -+ ag71xx_ring_free(&ag->tx_ring); -+} ++ ar71xx_add_device_m25p80(&wrt160nl_flash_data); + -+static unsigned char *ag71xx_speed_str(struct ag71xx *ag) -+{ -+ switch (ag->speed) { -+ case SPEED_1000: -+ return "1000"; -+ case SPEED_100: -+ return "100"; -+ case SPEED_10: -+ return "10"; -+ } ++ ar71xx_add_device_usb(); + -+ return "?"; -+} ++ if (nvram_parse_mac_addr(nvram, WRT160NL_NVRAM_SIZE, ++ "wl0_hwaddr=", mac) == 0) ++ ar913x_add_device_wmac(eeprom, mac); ++ else ++ ar913x_add_device_wmac(eeprom, NULL); + -+void ag71xx_link_adjust(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ u32 cfg2; -+ u32 ifctl; -+ u32 fifo5; -+ u32 mii_speed; ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt160nl_leds_gpio), ++ wrt160nl_leds_gpio); + -+ if (!ag->link) { -+ netif_carrier_off(ag->dev); -+ if (netif_msg_link(ag)) -+ printk(KERN_INFO "%s: link down\n", ag->dev->name); -+ return; -+ } ++ ar71xx_add_device_gpio_buttons(-1, WRT160NL_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(wrt160nl_gpio_buttons), ++ wrt160nl_gpio_buttons); + -+ cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); -+ cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); -+ cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; ++} + -+ ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); -+ ifctl &= ~(MAC_IFCTL_SPEED); ++MIPS_MACHINE(AR71XX_MACH_WRT160NL, "WRT160NL", "Linksys WRT160NL", ++ wrt160nl_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wrt400n.c linux-2.6.36/arch/mips/ar71xx/mach-wrt400n.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-wrt400n.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-wrt400n.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,168 @@ ++/* ++ * Linksys WRT400N board support ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * Copyright (C) 2009 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); -+ fifo5 &= ~FIFO_CFG5_BM; ++#include ++#include + -+ switch (ag->speed) { -+ case SPEED_1000: -+ mii_speed = MII_CTRL_SPEED_1000; -+ cfg2 |= MAC_CFG2_IF_1000; -+ fifo5 |= FIFO_CFG5_BM; -+ break; -+ case SPEED_100: -+ mii_speed = MII_CTRL_SPEED_100; -+ cfg2 |= MAC_CFG2_IF_10_100; -+ ifctl |= MAC_IFCTL_SPEED; -+ break; -+ case SPEED_10: -+ mii_speed = MII_CTRL_SPEED_10; -+ cfg2 |= MAC_CFG2_IF_10_100; -+ break; -+ default: -+ BUG(); -+ return; -+ } ++#include + -+ if (pdata->is_ar91xx) -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff); -+ else if (pdata->is_ar724x) -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3); -+ else -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ap94-pci.h" ++#include "dev-m25p80.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" + -+ if (pdata->set_pll) -+ pdata->set_pll(ag->speed); ++#define WRT400N_GPIO_LED_ORANGE 5 ++#define WRT400N_GPIO_LED_GREEN 4 ++#define WRT400N_GPIO_LED_POWER 1 ++#define WRT400N_GPIO_LED_WLAN 0 + -+ ag71xx_mii_ctrl_set_speed(ag, mii_speed); ++#define WRT400N_GPIO_BTN_RESET 8 ++#define WRT400N_GPIO_BTN_WLSEC 3 + -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); -+ ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); ++#define WRT400N_BUTTONS_POLL_INTERVAL 20 + -+ netif_carrier_on(ag->dev); -+ if (netif_msg_link(ag)) -+ printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n", -+ ag->dev->name, -+ ag71xx_speed_str(ag), -+ (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); ++#define WRT400N_MAC_ADDR_OFFSET 0x120c ++#define WRT400N_CALDATA0_OFFSET 0x1000 ++#define WRT400N_CALDATA1_OFFSET 0x5000 + -+ DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wrt400n_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0, ++ .size = 0x030000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "env", ++ .offset = 0x030000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "linux", ++ .offset = 0x040000, ++ .size = 0x140000, ++ } , { ++ .name = "rootfs", ++ .offset = 0x180000, ++ .size = 0x630000, ++ } , { ++ .name = "nvram", ++ .offset = 0x7b0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "factory", ++ .offset = 0x7c0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "language", ++ .offset = 0x7d0000, ++ .size = 0x020000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "caldata", ++ .offset = 0x7f0000, ++ .size = 0x010000, ++ .mask_flags = MTD_WRITEABLE, ++ } , { ++ .name = "firmware", ++ .offset = 0x040000, ++ .size = 0x770000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+ DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), -+ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); ++static struct flash_platform_data wrt400n_flash_data = { ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wrt400n_partitions, ++ .nr_parts = ARRAY_SIZE(wrt400n_partitions), ++#endif ++}; + -+ DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n", -+ ag->dev->name, -+ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), -+ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), -+ ag71xx_mii_ctrl_rr(ag)); -+} ++static struct gpio_led wrt400n_leds_gpio[] __initdata = { ++ { ++ .name = "wrt400n:green:status", ++ .gpio = WRT400N_GPIO_LED_GREEN, ++ .active_low = 1, ++ }, { ++ .name = "wrt400n:amber:aoss", ++ .gpio = WRT400N_GPIO_LED_ORANGE, ++ .active_low = 1, ++ }, { ++ .name = "wrt400n:green:wlan", ++ .gpio = WRT400N_GPIO_LED_WLAN, ++ .active_low = 1, ++ }, { ++ .name = "wrt400n:green:power", ++ .gpio = WRT400N_GPIO_LED_POWER, ++ .active_low = 1, ++ } ++}; + -+static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) ++static struct gpio_button wrt400n_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = WRT400N_GPIO_BTN_RESET, ++ .active_low = 1, ++ } , { ++ .desc = "wlsec", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = WRT400N_GPIO_BTN_WLSEC, ++ .active_low = 1, ++ } ++}; ++ ++static void __init wrt400n_setup(void) +{ -+ u32 t; ++ u8 *art = (u8 *) KSEG1ADDR(0x1fff0000); ++ u8 mac[6]; ++ int i; + -+ t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) -+ | (((u32) mac[3]) << 8) | ((u32) mac[2]); ++ memcpy(mac, art + WRT400N_MAC_ADDR_OFFSET, 6); ++ for (i = 5; i >= 3; i--) ++ if (++mac[i] != 0x00) break; + -+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); ++ ar71xx_set_mac_base(mac); + -+ t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); -+ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); -+} ++ ar71xx_add_device_mdio(0x0); + -+static void ag71xx_dma_reset(struct ag71xx *ag) -+{ -+ u32 val; -+ int i; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth0_data.speed = SPEED_100; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+ ag71xx_dump_dma_regs(ag); ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RMII; ++ ar71xx_eth1_data.phy_mask = 0x10; + -+ /* stop RX and TX */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ /* clear descriptor addresses */ -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0); -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0); ++ ar71xx_add_device_m25p80(&wrt400n_flash_data); + -+ /* clear pending RX/TX interrupts */ -+ for (i = 0; i < 256; i++) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); -+ } ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wrt400n_leds_gpio), ++ wrt400n_leds_gpio); + -+ /* clear pending errors */ -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); ++ ar71xx_add_device_gpio_buttons(-1, WRT400N_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(wrt400n_gpio_buttons), ++ wrt400n_gpio_buttons); + -+ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); -+ if (val) -+ printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n", -+ ag->dev->name, val); ++ ap94_pci_init(art + WRT400N_CALDATA0_OFFSET, NULL, ++ art + WRT400N_CALDATA1_OFFSET, NULL); ++} + -+ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); ++MIPS_MACHINE(AR71XX_MACH_WRT400N, "WRT400N", "Linksys WRT400N", wrt400n_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c linux-2.6.36/arch/mips/ar71xx/mach-wzr-hp-g300nh.c +--- linux-2.6.36.orig/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/mach-wzr-hp-g300nh.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,265 @@ ++/* ++ * Buffalo WZR-HP-G300NH board support ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ /* mask out reserved bits */ -+ val &= ~0xff000000; ++#include ++#include ++#include ++#include ++#include + -+ if (val) -+ printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n", -+ ag->dev->name, val); ++#include ++#include ++#include + -+ ag71xx_dump_dma_regs(ag); -+} ++#include "machtype.h" ++#include "devices.h" ++#include "dev-ar913x-wmac.h" ++#include "dev-gpio-buttons.h" ++#include "dev-leds-gpio.h" ++#include "dev-usb.h" + -+#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ -+ MAC_CFG1_SRX | MAC_CFG1_STX) ++#define WZRHPG300NH_GPIO_LED_USB 0 ++#define WZRHPG300NH_GPIO_LED_DIAG 1 ++#define WZRHPG300NH_GPIO_LED_WIRELESS 6 ++#define WZRHPG300NH_GPIO_LED_SECURITY 17 ++#define WZRHPG300NH_GPIO_LED_ROUTER 18 + -+#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) ++#define WZRHPG300NH_GPIO_RTL8366_SDA 19 ++#define WZRHPG300NH_GPIO_RTL8366_SCK 20 + -+#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ -+ FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ -+ FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ -+ FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ -+ FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ -+ FIFO_CFG4_VT) ++#define WZRHPG300NH_GPIO_74HC153_S0 9 ++#define WZRHPG300NH_GPIO_74HC153_S1 11 ++#define WZRHPG300NH_GPIO_74HC153_1Y 12 ++#define WZRHPG300NH_GPIO_74HC153_2Y 14 + -+#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ -+ FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ -+ FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ -+ FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ -+ FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ -+ FIFO_CFG5_17 | FIFO_CFG5_SF) ++#define WZRHPG300NH_GPIO_EXP_BASE 32 ++#define WZRHPG300NH_GPIO_BTN_AOSS (WZRHPG300NH_GPIO_EXP_BASE + 0) ++#define WZRHPG300NH_GPIO_BTN_RESET (WZRHPG300NH_GPIO_EXP_BASE + 1) ++#define WZRHPG300NH_GPIO_BTN_ROUTER_ON (WZRHPG300NH_GPIO_EXP_BASE + 2) ++#define WZRHPG300NH_GPIO_BTN_QOS_ON (WZRHPG300NH_GPIO_EXP_BASE + 3) ++#define WZRHPG300NH_GPIO_BTN_USB (WZRHPG300NH_GPIO_EXP_BASE + 5) ++#define WZRHPG300NH_GPIO_BTN_ROUTER_AUTO (WZRHPG300NH_GPIO_EXP_BASE + 6) ++#define WZRHPG300NH_GPIO_BTN_QOS_OFF (WZRHPG300NH_GPIO_EXP_BASE + 7) + -+static void ag71xx_hw_init(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++#define WZRHPG300NH_BUTTONS_POLL_INTERVAL 20 + -+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); -+ udelay(20); ++#define WZRHPG300NH_MAC_OFFSET 0x20c + -+ ar71xx_device_stop(pdata->reset_bit); -+ mdelay(100); -+ ar71xx_device_start(pdata->reset_bit); -+ mdelay(100); ++#ifdef CONFIG_MTD_PARTITIONS ++static struct mtd_partition wzrhpg300nh_flash_partitions[] = { ++ { ++ .name = "u-boot", ++ .offset = 0, ++ .size = 0x0040000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "u-boot-env", ++ .offset = 0x0040000, ++ .size = 0x0020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = 0x0060000, ++ .size = 0x0100000, ++ }, { ++ .name = "rootfs", ++ .offset = 0x0160000, ++ .size = 0x1e60000, ++ }, { ++ .name = "user_property", ++ .offset = 0x1fc0000, ++ .size = 0x0020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "art", ++ .offset = 0x1fe0000, ++ .size = 0x0020000, ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "firmware", ++ .offset = 0x0060000, ++ .size = 0x1f60000, ++ } ++}; ++#endif /* CONFIG_MTD_PARTITIONS */ + -+ /* setup MAC configuration registers */ -+ if (pdata->is_ar724x) -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, -+ MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC); -+ else -+ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); ++static struct ar91xx_flash_platform_data wzrhpg300nh_flash_data = { ++ .width = 2, ++#ifdef CONFIG_MTD_PARTITIONS ++ .parts = wzrhpg300nh_flash_partitions, ++ .nr_parts = ARRAY_SIZE(wzrhpg300nh_flash_partitions), ++#endif ++}; + -+ ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, -+ MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); ++#define WZRHPG300NH_FLASH_BASE 0x1e000000 ++#define WZRHPG300NH_FLASH_SIZE (32 * 1024 * 1024) + -+ /* setup max frame length */ -+ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); ++static struct resource wzrhpg300nh_flash_resources[] = { ++ [0] = { ++ .start = WZRHPG300NH_FLASH_BASE, ++ .end = WZRHPG300NH_FLASH_BASE + WZRHPG300NH_FLASH_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; + -+ /* setup MII interface type */ -+ ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); ++static struct platform_device wzrhpg300nh_flash_device = { ++ .name = "ar91xx-flash", ++ .id = -1, ++ .resource = wzrhpg300nh_flash_resources, ++ .num_resources = ARRAY_SIZE(wzrhpg300nh_flash_resources), ++ .dev = { ++ .platform_data = &wzrhpg300nh_flash_data, ++ } ++}; + -+ /* setup FIFO configuration registers */ -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); -+ if (pdata->is_ar724x) { -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); -+ } else { -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); ++static struct gpio_led wzrhpg300nh_leds_gpio[] __initdata = { ++ { ++ .name = "wzr-hp-g300nh:orange:security", ++ .gpio = WZRHPG300NH_GPIO_LED_SECURITY, ++ .active_low = 1, ++ }, { ++ .name = "wzr-hp-g300nh:green:wireless", ++ .gpio = WZRHPG300NH_GPIO_LED_WIRELESS, ++ .active_low = 1, ++ }, { ++ .name = "wzr-hp-g300nh:green:router", ++ .gpio = WZRHPG300NH_GPIO_LED_ROUTER, ++ .active_low = 1, ++ }, { ++ .name = "wzr-hp-g300nh:red:diag", ++ .gpio = WZRHPG300NH_GPIO_LED_DIAG, ++ .active_low = 1, ++ }, { ++ .name = "wzr-hp-g300nh:blue:usb", ++ .gpio = WZRHPG300NH_GPIO_LED_USB, ++ .active_low = 1, ++ } ++}; ++ ++static struct gpio_button wzrhpg300nh_gpio_buttons[] __initdata = { ++ { ++ .desc = "reset", ++ .type = EV_KEY, ++ .code = KEY_RESTART, ++ .threshold = 3, ++ .gpio = WZRHPG300NH_GPIO_BTN_RESET, ++ .active_low = 1, ++ }, { ++ .desc = "aoss", ++ .type = EV_KEY, ++ .code = KEY_WPS_BUTTON, ++ .threshold = 3, ++ .gpio = WZRHPG300NH_GPIO_BTN_AOSS, ++ .active_low = 1, ++ }, { ++ .desc = "usb", ++ .type = EV_KEY, ++ .code = BTN_2, ++ .threshold = 3, ++ .gpio = WZRHPG300NH_GPIO_BTN_USB, ++ .active_low = 1, ++ }, { ++ .desc = "qos_on", ++ .type = EV_KEY, ++ .code = BTN_3, ++ .threshold = 3, ++ .gpio = WZRHPG300NH_GPIO_BTN_QOS_ON, ++ .active_low = 0, ++ }, { ++ .desc = "qos_off", ++ .type = EV_KEY, ++ .code = BTN_4, ++ .threshold = 3, ++ .gpio = WZRHPG300NH_GPIO_BTN_QOS_OFF, ++ .active_low = 0, ++ }, { ++ .desc = "router_on", ++ .type = EV_KEY, ++ .code = BTN_5, ++ .threshold = 3, ++ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_ON, ++ .active_low = 0, ++ }, { ++ .desc = "router_auto", ++ .type = EV_KEY, ++ .code = BTN_6, ++ .threshold = 3, ++ .gpio = WZRHPG300NH_GPIO_BTN_ROUTER_AUTO, ++ .active_low = 0, + } -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); -+ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); -+ -+ ag71xx_dma_reset(ag); -+} ++}; + -+static void ag71xx_hw_start(struct ag71xx *ag) -+{ -+ /* start RX engine */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); ++static struct nxp_74hc153_platform_data wzrhpg300nh_74hc153_data = { ++ .gpio_base = WZRHPG300NH_GPIO_EXP_BASE, ++ .gpio_pin_s0 = WZRHPG300NH_GPIO_74HC153_S0, ++ .gpio_pin_s1 = WZRHPG300NH_GPIO_74HC153_S1, ++ .gpio_pin_1y = WZRHPG300NH_GPIO_74HC153_1Y, ++ .gpio_pin_2y = WZRHPG300NH_GPIO_74HC153_2Y, ++}; + -+ /* enable interrupts */ -+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); -+} ++static struct platform_device wzrhpg300nh_74hc153_device = { ++ .name = NXP_74HC153_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &wzrhpg300nh_74hc153_data, ++ } ++}; + -+static void ag71xx_hw_stop(struct ag71xx *ag) -+{ -+ /* disable all interrupts */ -+ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); ++static struct rtl8366s_platform_data wzrhpg300nh_rtl8366s_data = { ++ .gpio_sda = WZRHPG300NH_GPIO_RTL8366_SDA, ++ .gpio_sck = WZRHPG300NH_GPIO_RTL8366_SCK, ++}; + -+ ag71xx_dma_reset(ag); -+} ++static struct platform_device wzrhpg300nh_rtl8366s_device = { ++ .name = RTL8366S_DRIVER_NAME, ++ .id = -1, ++ .dev = { ++ .platform_data = &wzrhpg300nh_rtl8366s_data, ++ } ++}; + -+static int ag71xx_open(struct net_device *dev) ++static void __init wzrhpg300nh_setup(void) +{ -+ struct ag71xx *ag = netdev_priv(dev); -+ int ret; ++ u8 *eeprom = (u8 *) KSEG1ADDR(0x1fff1000); + -+ ret = ag71xx_rings_init(ag); -+ if (ret) -+ goto err; ++ ar71xx_set_mac_base(eeprom + WZRHPG300NH_MAC_OFFSET); + -+ napi_enable(&ag->napi); ++ ar71xx_eth0_pll_data.pll_1000 = 0x1e000100; ++ ar71xx_eth0_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; ++ ar71xx_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth0_data.speed = SPEED_1000; ++ ar71xx_eth0_data.duplex = DUPLEX_FULL; + -+ netif_carrier_off(dev); -+ ag71xx_phy_start(ag); ++ ar71xx_eth1_pll_data.pll_1000 = 0x1e000100; ++ ar71xx_eth1_data.mii_bus_dev = &wzrhpg300nh_rtl8366s_device.dev; ++ ar71xx_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII; ++ ar71xx_eth1_data.phy_mask = 0x10; + -+ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); -+ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); ++ ar71xx_add_device_eth(0); ++ ar71xx_add_device_eth(1); + -+ ag71xx_hw_set_macaddr(ag, dev->dev_addr); ++ ar71xx_add_device_usb(); ++ ar913x_add_device_wmac(eeprom, NULL); + -+ ag71xx_hw_start(ag); ++ platform_device_register(&wzrhpg300nh_74hc153_device); ++ platform_device_register(&wzrhpg300nh_flash_device); ++ platform_device_register(&wzrhpg300nh_rtl8366s_device); + -+ netif_start_queue(dev); ++ ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(wzrhpg300nh_leds_gpio), ++ wzrhpg300nh_leds_gpio); + -+ return 0; ++ ar71xx_add_device_gpio_buttons(-1, WZRHPG300NH_BUTTONS_POLL_INTERVAL, ++ ARRAY_SIZE(wzrhpg300nh_gpio_buttons), ++ wzrhpg300nh_gpio_buttons); + -+ err: -+ ag71xx_rings_cleanup(ag); -+ return ret; +} + -+static int ag71xx_stop(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ unsigned long flags; -+ -+ netif_carrier_off(dev); -+ ag71xx_phy_stop(ag); -+ -+ spin_lock_irqsave(&ag->lock, flags); ++MIPS_MACHINE(AR71XX_MACH_WZR_HP_G300NH, "WZR-HP-G300NH", ++ "Buffalo WZR-HP-G300NH", wzrhpg300nh_setup); +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/machtype.h linux-2.6.36/arch/mips/ar71xx/machtype.h +--- linux-2.6.36.orig/arch/mips/ar71xx/machtype.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/machtype.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,60 @@ ++/* ++ * Atheros AR71xx machine type definitions ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ netif_stop_queue(dev); ++#ifndef _AR71XX_MACHTYPE_H ++#define _AR71XX_MACHTYPE_H + -+ ag71xx_hw_stop(ag); ++#include + -+ napi_disable(&ag->napi); -+ del_timer_sync(&ag->oom_timer); ++enum ar71xx_mach_type { ++ AR71XX_MACH_GENERIC = 0, ++ AR71XX_MACH_AP81, /* Atheros AP81 */ ++ AR71XX_MACH_AP83, /* Atheros AP83 */ ++ AR71XX_MACH_AW_NR580, /* AzureWave AW-NR580 */ ++ AR71XX_MACH_DIR_600_A1, /* D-Link DIR-600 rev. A1 */ ++ AR71XX_MACH_DIR_615_C1, /* D-Link DIR-615 rev. C1 */ ++ AR71XX_MACH_DIR_825_B1, /* D-Link DIR-825 rev. B1 */ ++ AR71XX_MACH_RB_411, /* MikroTik RouterBOARD 411/411A/411AH */ ++ AR71XX_MACH_RB_411U, /* MikroTik RouterBOARD 411U */ ++ AR71XX_MACH_RB_433, /* MikroTik RouterBOARD 433/433AH */ ++ AR71XX_MACH_RB_433U, /* MikroTik RouterBOARD 433UAH */ ++ AR71XX_MACH_RB_450, /* MikroTik RouterBOARD 450 */ ++ AR71XX_MACH_RB_450G, /* MikroTik RouterBOARD 450G */ ++ AR71XX_MACH_RB_493, /* Mikrotik RouterBOARD 493/493AH */ ++ AR71XX_MACH_RB_750, /* MikroTik RouterBOARD 750 */ ++ AR71XX_MACH_PB42, /* Atheros PB42 */ ++ AR71XX_MACH_PB44, /* Atheros PB44 */ ++ AR71XX_MACH_PB92, /* Atheros PB92 */ ++ AR71XX_MACH_MZK_W04NU, /* Planex MZK-W04NU */ ++ AR71XX_MACH_MZK_W300NH, /* Planex MZK-W300NH */ ++ AR71XX_MACH_NBG460N, /* Zyxel NBG460N/550N/550NH */ ++ AR71XX_MACH_TEW_632BRP, /* TRENDnet TEW-632BRP */ ++ AR71XX_MACH_TL_WR741ND, /* TP-LINK TL-WR741ND */ ++ AR71XX_MACH_TL_WR841N_V1, /* TP-LINK TL-WR841N v1 */ ++ AR71XX_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */ ++ AR71XX_MACH_TL_WR1043ND, /* TP-LINK TL-WR1041ND */ ++ AR71XX_MACH_UBNT_LSSR71, /* Ubiquiti LS-SR71 */ ++ AR71XX_MACH_UBNT_LSX, /* Ubiquiti LSX */ ++ AR71XX_MACH_UBNT_RS, /* Ubiquiti RouterStation */ ++ AR71XX_MACH_UBNT_AR71XX, /* Ubiquiti AR71xx-based board */ ++ AR71XX_MACH_UBNT_RSPRO, /* Ubiquiti RouterStation Pro */ ++ AR71XX_MACH_UBNT_BULLET_M, /* Ubiquiti Bullet M */ ++ AR71XX_MACH_UBNT_ROCKET_M, /* Ubiquiti Rocket M */ ++ AR71XX_MACH_UBNT_NANO_M, /* Ubiquiti NanoStation M */ ++ AR71XX_MACH_WNDR3700, /* NETGEAR WNDR3700 */ ++ AR71XX_MACH_WNR2000, /* NETGEAR WNR2000 */ ++ AR71XX_MACH_WP543, /* Compex WP543 */ ++ AR71XX_MACH_WRT160NL, /* Linksys WRT160NL */ ++ AR71XX_MACH_WRT400N, /* Linksys WRT400N */ ++ AR71XX_MACH_WZR_HP_G300NH, /* Buffalo WZR-HP-G300NH */ ++}; + -+ spin_unlock_irqrestore(&ag->lock, flags); ++#endif /* _AR71XX_MACHTYPE_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/nvram.c linux-2.6.36/arch/mips/ar71xx/nvram.c +--- linux-2.6.36.orig/arch/mips/ar71xx/nvram.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/nvram.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,75 @@ ++/* ++ * Atheros AR71xx minimal nvram support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ ag71xx_rings_cleanup(ag); ++#include ++#include ++#include ++#include ++#include + -+ return 0; -+} ++#include "nvram.h" + -+static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, -+ struct net_device *dev) ++char *nvram_find_var(const char *name, const char *buf, unsigned buf_len) +{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ struct ag71xx_desc *desc; -+ dma_addr_t dma_addr; -+ int i; ++ unsigned len = strlen(name); ++ char *cur, *last; + -+ i = ring->curr % AG71XX_TX_RING_SIZE; -+ desc = ring->buf[i].desc; ++ if (buf_len == 0 || len == 0) ++ return NULL; + -+ if (!ag71xx_desc_empty(desc)) -+ goto err_drop; ++ if (buf_len < len) ++ return NULL; + -+ if (ag71xx_has_ar8216(ag)) -+ ag71xx_add_ar8216_header(ag, skb); ++ if (len == 1) ++ return memchr(buf, (int) *name, buf_len); + -+ if (skb->len <= 0) { -+ DBG("%s: packet len is too small\n", ag->dev->name); -+ goto err_drop; -+ } ++ last = (char *) buf + buf_len - len; ++ for (cur = (char *) buf; cur <= last; cur++) ++ if (cur[0] == name[0] && memcmp(cur, name, len) == 0) ++ return cur + len; + -+ dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, -+ DMA_TO_DEVICE); ++ return NULL; ++} + -+ ring->buf[i].skb = skb; ++int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, ++ const char *name, char *mac) ++{ ++ char *buf; ++ char *mac_str; ++ int ret; ++ int t; + -+ /* setup descriptor fields */ -+ desc->data = (u32) dma_addr; -+ desc->ctrl = (skb->len & DESC_PKTLEN_M); ++ buf = vmalloc(nvram_len); ++ if (!buf) ++ return -ENOMEM; + -+ /* flush descriptor */ -+ wmb(); ++ memcpy(buf, nvram, nvram_len); ++ buf[nvram_len - 1] = '\0'; + -+ ring->curr++; -+ if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) { -+ DBG("%s: tx queue full\n", ag->dev->name); -+ netif_stop_queue(dev); ++ mac_str = nvram_find_var(name, buf, nvram_len); ++ if (!mac_str) { ++ ret = -EINVAL; ++ goto free; + } + -+ DBG("%s: packet injected into TX queue\n", ag->dev->name); -+ -+ /* enable TX engine */ -+ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); ++ t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx", ++ &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]); + -+ return NETDEV_TX_OK; ++ if (t != 6) { ++ ret = -EINVAL; ++ goto free; ++ } + -+ err_drop: -+ dev->stats.tx_dropped++; ++ ret = 0; + -+ dev_kfree_skb(skb); -+ return NETDEV_TX_OK; ++ free: ++ vfree(buf); ++ return ret; +} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/nvram.h linux-2.6.36/arch/mips/ar71xx/nvram.h +--- linux-2.6.36.orig/arch/mips/ar71xx/nvram.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/nvram.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,19 @@ ++/* ++ * Atheros AR71xx minimal nvram support ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) -+{ -+ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; -+ struct ag71xx *ag = netdev_priv(dev); -+ int ret; ++#ifndef _AR71XX_NVRAM_H ++#define _AR71XX_NVRAM_H + -+ switch (cmd) { -+ case SIOCETHTOOL: -+ if (ag->phy_dev == NULL) -+ break; ++char *nvram_find_var(const char *name, const char *buf, ++ unsigned buf_len) __init; ++int nvram_parse_mac_addr(const char *nvram, unsigned nvram_len, ++ const char *name, char *mac) __init; + -+ spin_lock_irq(&ag->lock); -+ ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); -+ spin_unlock_irq(&ag->lock); -+ return ret; ++#endif /* _AR71XX_NVRAM_H */ +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/pci.c linux-2.6.36/arch/mips/ar71xx/pci.c +--- linux-2.6.36.orig/arch/mips/ar71xx/pci.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/pci.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,93 @@ ++/* ++ * Atheros AR71xx PCI setup code ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ case SIOCSIFHWADDR: -+ if (copy_from_user -+ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; ++#include + -+ case SIOCGIFHWADDR: -+ if (copy_to_user -+ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) -+ return -EFAULT; -+ return 0; ++#include + -+ case SIOCGMIIPHY: -+ case SIOCGMIIREG: -+ case SIOCSMIIREG: -+ if (ag->phy_dev == NULL) -+ break; ++#include ++#include + -+ return phy_mii_ioctl(ag->phy_dev, data, cmd); ++unsigned ar71xx_pci_nr_irqs __initdata; ++struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; + -+ default: -+ break; -+ } ++int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); + -+ return -EOPNOTSUPP; ++static int ar71xx_be_handler(struct pt_regs *regs, int is_fixup) ++{ ++ int err = 0; ++ ++ err = ar71xx_pci_be_handler(is_fixup); ++ ++ return (is_fixup && !err) ? MIPS_BE_FIXUP : MIPS_BE_FATAL; +} + -+static void ag71xx_oom_timer_handler(unsigned long data) ++int pcibios_plat_dev_init(struct pci_dev *dev) +{ -+ struct net_device *dev = (struct net_device *) data; -+ struct ag71xx *ag = netdev_priv(dev); ++ if (ar71xx_pci_plat_dev_init) ++ return ar71xx_pci_plat_dev_init(dev); + -+ napi_schedule(&ag->napi); ++ return 0; +} + -+static void ag71xx_tx_timeout(struct net_device *dev) ++int __init pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, uint8_t pin) +{ -+ struct ag71xx *ag = netdev_priv(dev); ++ int ret = 0; + -+ if (netif_msg_tx_err(ag)) -+ printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name); ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ret = ar71xx_pcibios_map_irq(dev, slot, pin); ++ break; + -+ schedule_work(&ag->restart_work); -+} ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ret = ar724x_pcibios_map_irq(dev, slot, pin); ++ break; + -+static void ag71xx_restart_work_func(struct work_struct *work) -+{ -+ struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); ++ default: ++ break; ++ } + -+ ag71xx_stop(ag->dev); -+ ag71xx_open(ag->dev); ++ return ret; +} + -+static int ag71xx_tx_packets(struct ag71xx *ag) ++int __init ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) +{ -+ struct ag71xx_ring *ring = &ag->tx_ring; -+ int sent; ++ int ret = 0; + -+ DBG("%s: processing TX ring\n", ag->dev->name); ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ board_be_handler = ar71xx_be_handler; ++ ret = ar71xx_pcibios_init(); ++ break; + -+ sent = 0; -+ while (ring->dirty != ring->curr) { -+ unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE; -+ struct ag71xx_desc *desc = ring->buf[i].desc; -+ struct sk_buff *skb = ring->buf[i].skb; ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ret = ar724x_pcibios_init(); ++ break; + -+ if (!ag71xx_desc_empty(desc)) -+ break; ++ default: ++ return 0; ++ } + -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); ++ ar71xx_pci_nr_irqs = nr_irqs; ++ ar71xx_pci_irq_map = map; + -+ ag->dev->stats.tx_bytes += skb->len; -+ ag->dev->stats.tx_packets++; ++ return ret; ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/prom.c linux-2.6.36/arch/mips/ar71xx/prom.c +--- linux-2.6.36.orig/arch/mips/ar71xx/prom.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/prom.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,105 @@ ++/* ++ * Atheros AR71xx SoC specific prom routines ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ dev_kfree_skb_any(skb); -+ ring->buf[i].skb = NULL; ++#include ++#include ++#include ++#include + -+ ring->dirty++; -+ sent++; -+ } ++#include ++#include + -+ DBG("%s: %d packets sent out\n", ag->dev->name, sent); ++#include + -+ if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP) -+ netif_wake_queue(ag->dev); ++static inline int is_valid_ram_addr(void *addr) ++{ ++ if (((u32) addr > KSEG0) && ++ ((u32) addr < (KSEG0 + AR71XX_MEM_SIZE_MAX))) ++ return 1; + -+ return sent; ++ if (((u32) addr > KSEG1) && ++ ((u32) addr < (KSEG1 + AR71XX_MEM_SIZE_MAX))) ++ return 1; ++ ++ return 0; +} + -+static int ag71xx_rx_packets(struct ag71xx *ag, int limit) ++static void __init ar71xx_prom_append_cmdline(const char *name, ++ const char *value) +{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_ring *ring = &ag->rx_ring; -+ int done = 0; ++ char buf[COMMAND_LINE_SIZE]; + -+ DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", -+ dev->name, limit, ring->curr, ring->dirty); ++ snprintf(buf, sizeof(buf), " %s=%s", name, value); ++ strlcat(arcs_cmdline, buf, sizeof(arcs_cmdline)); ++} + -+ while (done < limit) { -+ unsigned int i = ring->curr % AG71XX_RX_RING_SIZE; -+ struct ag71xx_desc *desc = ring->buf[i].desc; -+ struct sk_buff *skb; -+ int pktlen; -+ int err = 0; ++static void __init ar71xx_prom_find_env(char **envp, const char *name) ++{ ++ int len = strlen(name); ++ char **p; + -+ if (ag71xx_desc_empty(desc)) -+ break; ++ if (!is_valid_ram_addr(envp)) ++ return; + -+ if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) { -+ ag71xx_assert(0); ++ for (p = envp; is_valid_ram_addr(*p); p++) { ++ if (strncmp(name, *p, len) == 0 && (*p)[len] == '=') { ++ ar71xx_prom_append_cmdline(name, *p + len + 1); + break; + } + -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); ++ /* RedBoot env comes in pointer pairs - key, value */ ++ if (strncmp(name, *p, len) == 0 && (*p)[len] == 0) ++ if (is_valid_ram_addr(*(++p))) { ++ ar71xx_prom_append_cmdline(name, *p); ++ break; ++ } ++ } ++} + -+ skb = ring->buf[i].skb; -+ pktlen = ag71xx_desc_pktlen(desc); -+ pktlen -= ETH_FCS_LEN; ++static int inline ar71xx_use__image_cmdline(void) { return 0; } + -+ dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, -+ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); ++static __init void ar71xx_prom_init_cmdline(int argc, char **argv) ++{ ++ int i; + -+ dev->last_rx = jiffies; -+ dev->stats.rx_packets++; -+ dev->stats.rx_bytes += pktlen; ++ if (ar71xx_use__image_cmdline()) ++ return; + -+ skb_put(skb, pktlen); -+ if (ag71xx_has_ar8216(ag)) -+ err = ag71xx_remove_ar8216_header(ag, skb, pktlen); ++ if (!is_valid_ram_addr(argv)) ++ return; + -+ if (err) { -+ dev->stats.rx_dropped++; -+ kfree_skb(skb); -+ } else { -+ skb->dev = dev; -+ skb->ip_summed = CHECKSUM_NONE; -+ if (ag->phy_dev) { -+ ag->phy_dev->netif_receive_skb(skb); -+ } else { -+ skb->protocol = eth_type_trans(skb, dev); -+ netif_receive_skb(skb); -+ } ++ for (i = 0; i < argc; i++) ++ if (is_valid_ram_addr(argv[i])) { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, argv[i], sizeof(arcs_cmdline)); + } ++} + -+ ring->buf[i].skb = NULL; -+ done++; ++void __init prom_init(void) ++{ ++ char **envp; + -+ ring->curr++; -+ } ++ printk(KERN_DEBUG "prom: fw_arg0=%08x, fw_arg1=%08x, " ++ "fw_arg2=%08x, fw_arg3=%08x\n", ++ (unsigned int)fw_arg0, (unsigned int)fw_arg1, ++ (unsigned int)fw_arg2, (unsigned int)fw_arg3); + -+ ag71xx_ring_rx_refill(ag); + -+ DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", -+ dev->name, ring->curr, ring->dirty, done); ++ ar71xx_prom_init_cmdline(fw_arg0, (char **)fw_arg1); + -+ return done; ++ envp = (char **)fw_arg2; ++ ar71xx_prom_find_env(envp, "board"); +} + -+static int ag71xx_poll(struct napi_struct *napi, int limit) ++void __init prom_free_prom_memory(void) +{ -+ struct ag71xx *ag = container_of(napi, struct ag71xx, napi); -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct net_device *dev = ag->dev; -+ struct ag71xx_ring *rx_ring; -+ unsigned long flags; -+ u32 status; -+ int tx_done; -+ int rx_done; ++ /* We do not have to prom memory to free */ ++} +diff -Nur linux-2.6.36.orig/arch/mips/ar71xx/setup.c linux-2.6.36/arch/mips/ar71xx/setup.c +--- linux-2.6.36.orig/arch/mips/ar71xx/setup.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/ar71xx/setup.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,310 @@ ++/* ++ * Atheros AR71xx SoC specific setup ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ pdata->ddr_flush(); -+ tx_done = ag71xx_tx_packets(ag); ++#include ++#include ++#include + -+ DBG("%s: processing RX ring\n", dev->name); -+ rx_done = ag71xx_rx_packets(ag, limit); ++#include ++#include /* for mips_hpt_frequency */ ++#include /* for _machine_{restart,halt} */ ++#include + -+ ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); ++#include + -+ rx_ring = &ag->rx_ring; -+ if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL) -+ goto oom; ++#include "machtype.h" ++#include "devices.h" + -+ status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); -+ if (unlikely(status & RX_STATUS_OF)) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); -+ dev->stats.rx_fifo_errors++; ++#define AR71XX_SYS_TYPE_LEN 64 ++#define AR71XX_BASE_FREQ 40000000 ++#define AR91XX_BASE_FREQ 5000000 ++#define AR724X_BASE_FREQ 5000000 + -+ /* restart RX */ -+ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); -+ } ++u32 ar71xx_cpu_freq; ++EXPORT_SYMBOL_GPL(ar71xx_cpu_freq); + -+ if (rx_done < limit) { -+ if (status & RX_STATUS_PR) -+ goto more; ++u32 ar71xx_ahb_freq; ++EXPORT_SYMBOL_GPL(ar71xx_ahb_freq); + -+ status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); -+ if (status & TX_STATUS_PS) -+ goto more; ++u32 ar71xx_ddr_freq; ++EXPORT_SYMBOL_GPL(ar71xx_ddr_freq); + -+ DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", -+ dev->name, rx_done, tx_done, limit); ++enum ar71xx_soc_type ar71xx_soc; ++EXPORT_SYMBOL_GPL(ar71xx_soc); + -+ napi_complete(napi); ++static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN]; + -+ /* enable interrupts */ -+ spin_lock_irqsave(&ag->lock, flags); -+ ag71xx_int_enable(ag, AG71XX_INT_POLL); -+ spin_unlock_irqrestore(&ag->lock, flags); -+ return rx_done; -+ } ++static void ar71xx_restart(char *command) ++{ ++ ar71xx_device_stop(RESET_MODULE_FULL_CHIP); ++ for (;;) ++ if (cpu_wait) ++ cpu_wait(); ++} + -+ more: -+ DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", -+ dev->name, rx_done, tx_done, limit); -+ return rx_done; ++static void ar71xx_halt(void) ++{ ++ while (1) ++ cpu_wait(); ++} + -+ oom: -+ if (netif_msg_rx_err(ag)) -+ printk(KERN_DEBUG "%s: out of memory\n", dev->name); ++static void __init ar71xx_detect_mem_size(void) ++{ ++ unsigned long size; + -+ mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); -+ napi_complete(napi); -+ return 0; ++ for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX; ++ size <<= 1 ) { ++ if (!memcmp(ar71xx_detect_mem_size, ++ ar71xx_detect_mem_size + size, 1024)) ++ break; ++ } ++ ++ add_memory_region(0, size, BOOT_MEM_RAM); +} + -+static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) ++static void __init ar71xx_detect_sys_type(void) +{ -+ struct net_device *dev = dev_id; -+ struct ag71xx *ag = netdev_priv(dev); -+ u32 status; ++ char *chip = "????"; ++ u32 id; ++ u32 major; ++ u32 minor; ++ u32 rev = 0; + -+ status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); -+ ag71xx_dump_intr(ag, "raw", status); ++ id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID); ++ major = id & REV_ID_MAJOR_MASK; + -+ if (unlikely(!status)) -+ return IRQ_NONE; ++ switch (major) { ++ case REV_ID_MAJOR_AR71XX: ++ minor = id & AR71XX_REV_ID_MINOR_MASK; ++ rev = id >> AR71XX_REV_ID_REVISION_SHIFT; ++ rev &= AR71XX_REV_ID_REVISION_MASK; ++ switch (minor) { ++ case AR71XX_REV_ID_MINOR_AR7130: ++ ar71xx_soc = AR71XX_SOC_AR7130; ++ chip = "7130"; ++ break; + -+ if (unlikely(status & AG71XX_INT_ERR)) { -+ if (status & AG71XX_INT_TX_BE) { -+ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); -+ dev_err(&dev->dev, "TX BUS error\n"); ++ case AR71XX_REV_ID_MINOR_AR7141: ++ ar71xx_soc = AR71XX_SOC_AR7141; ++ chip = "7141"; ++ break; ++ ++ case AR71XX_REV_ID_MINOR_AR7161: ++ ar71xx_soc = AR71XX_SOC_AR7161; ++ chip = "7161"; ++ break; + } -+ if (status & AG71XX_INT_RX_BE) { -+ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); -+ dev_err(&dev->dev, "RX BUS error\n"); ++ break; ++ ++ case REV_ID_MAJOR_AR7240: ++ ar71xx_soc = AR71XX_SOC_AR7240; ++ chip = "7240"; ++ rev = (id & AR724X_REV_ID_REVISION_MASK); ++ break; ++ ++ case REV_ID_MAJOR_AR7241: ++ ar71xx_soc = AR71XX_SOC_AR7241; ++ chip = "7241"; ++ rev = (id & AR724X_REV_ID_REVISION_MASK); ++ break; ++ ++ case REV_ID_MAJOR_AR7242: ++ ar71xx_soc = AR71XX_SOC_AR7242; ++ chip = "7242"; ++ rev = (id & AR724X_REV_ID_REVISION_MASK); ++ break; ++ ++ case REV_ID_MAJOR_AR913X: ++ minor = id & AR91XX_REV_ID_MINOR_MASK; ++ rev = id >> AR91XX_REV_ID_REVISION_SHIFT; ++ rev &= AR91XX_REV_ID_REVISION_MASK; ++ switch (minor) { ++ case AR91XX_REV_ID_MINOR_AR9130: ++ ar71xx_soc = AR71XX_SOC_AR9130; ++ chip = "9130"; ++ break; ++ ++ case AR91XX_REV_ID_MINOR_AR9132: ++ ar71xx_soc = AR71XX_SOC_AR9132; ++ chip = "9132"; ++ break; + } -+ } ++ break; + -+ if (likely(status & AG71XX_INT_POLL)) { -+ ag71xx_int_disable(ag, AG71XX_INT_POLL); -+ DBG("%s: enable polling mode\n", dev->name); -+ napi_schedule(&ag->napi); ++ default: ++ panic("ar71xx: unknown chip id:0x%08x\n", id); + } + -+ ag71xx_debugfs_update_int_stats(ag, status); -+ -+ return IRQ_HANDLED; ++ sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev); +} + -+static void ag71xx_set_multicast_list(struct net_device *dev) ++static void __init ar91xx_detect_sys_frequency(void) +{ -+ /* TODO */ -+} ++ u32 pll; ++ u32 freq; ++ u32 div; + -+#ifdef CONFIG_NET_POLL_CONTROLLER -+/* -+ * Polling 'interrupt' - used by things like netconsole to send skbs -+ * without having to re-enable interrupts. It's not called while -+ * the interrupt routine is executing. -+ */ -+static void ag71xx_netpoll(struct net_device *dev) -+{ -+ disable_irq(dev->irq); -+ ag71xx_interrupt(dev->irq, dev); -+ enable_irq(dev->irq); -+} -+#endif ++ pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG); + -+static const struct net_device_ops ag71xx_netdev_ops = { -+ .ndo_open = ag71xx_open, -+ .ndo_stop = ag71xx_stop, -+ .ndo_start_xmit = ag71xx_hard_start_xmit, -+ .ndo_set_multicast_list = ag71xx_set_multicast_list, -+ .ndo_do_ioctl = ag71xx_do_ioctl, -+ .ndo_tx_timeout = ag71xx_tx_timeout, -+ .ndo_change_mtu = eth_change_mtu, -+ .ndo_set_mac_address = eth_mac_addr, -+ .ndo_validate_addr = eth_validate_addr, -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ .ndo_poll_controller = ag71xx_netpoll, -+#endif -+}; ++ div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); ++ freq = div * AR91XX_BASE_FREQ; + -+static int __init ag71xx_probe(struct platform_device *pdev) -+{ -+ struct net_device *dev; -+ struct resource *res; -+ struct ag71xx *ag; -+ struct ag71xx_platform_data *pdata; -+ int err; ++ ar71xx_cpu_freq = freq; + -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified\n"); -+ err = -ENXIO; -+ goto err_out; -+ } ++ div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; ++ ar71xx_ddr_freq = freq / div; + -+ if (pdata->mii_bus_dev == NULL) { -+ dev_err(&pdev->dev, "no MII bus device specified\n"); -+ err = -EINVAL; -+ goto err_out; -+ } ++ div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; ++ ar71xx_ahb_freq = ar71xx_cpu_freq / div; ++} + -+ dev = alloc_etherdev(sizeof(*ag)); -+ if (!dev) { -+ dev_err(&pdev->dev, "alloc_etherdev failed\n"); -+ err = -ENOMEM; -+ goto err_out; -+ } ++static void __init ar71xx_detect_sys_frequency(void) ++{ ++ u32 pll; ++ u32 freq; ++ u32 div; + -+ SET_NETDEV_DEV(dev, &pdev->dev); ++ pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG); + -+ ag = netdev_priv(dev); -+ ag->pdev = pdev; -+ ag->dev = dev; -+ ag->msg_enable = netif_msg_init(ag71xx_msg_level, -+ AG71XX_DEFAULT_MSG_ENABLE); -+ spin_lock_init(&ag->lock); ++ div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; ++ freq = div * AR71XX_BASE_FREQ; + -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); -+ if (!res) { -+ dev_err(&pdev->dev, "no mac_base resource found\n"); -+ err = -ENXIO; -+ goto err_out; -+ } ++ div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; ++ ar71xx_cpu_freq = freq / div; + -+ ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!ag->mac_base) { -+ dev_err(&pdev->dev, "unable to ioremap mac_base\n"); -+ err = -ENOMEM; -+ goto err_free_dev; -+ } ++ div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; ++ ar71xx_ddr_freq = freq / div; + -+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl"); -+ if (!res) { -+ dev_err(&pdev->dev, "no mii_ctrl resource found\n"); -+ err = -ENXIO; -+ goto err_unmap_base; -+ } ++ div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; ++ ar71xx_ahb_freq = ar71xx_cpu_freq / div; ++} + -+ ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!ag->mii_ctrl) { -+ dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n"); -+ err = -ENOMEM; -+ goto err_unmap_base; -+ } ++static void __init ar724x_detect_sys_frequency(void) ++{ ++ u32 pll; ++ u32 freq; ++ u32 div; + -+ dev->irq = platform_get_irq(pdev, 0); -+ err = request_irq(dev->irq, ag71xx_interrupt, -+ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, -+ dev->name, dev); -+ if (err) { -+ dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); -+ goto err_unmap_mii_ctrl; -+ } ++ pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG); + -+ dev->base_addr = (unsigned long)ag->mac_base; -+ dev->netdev_ops = &ag71xx_netdev_ops; -+ dev->ethtool_ops = &ag71xx_ethtool_ops; ++ div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); ++ freq = div * AR724X_BASE_FREQ; + -+ INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); ++ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); ++ freq *= div; + -+ init_timer(&ag->oom_timer); -+ ag->oom_timer.data = (unsigned long) dev; -+ ag->oom_timer.function = ag71xx_oom_timer_handler; ++ ar71xx_cpu_freq = freq; + -+ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); ++ div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; ++ ar71xx_ddr_freq = freq / div; + -+ netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); ++ div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; ++ ar71xx_ahb_freq = ar71xx_cpu_freq / div; ++} + -+ err = register_netdev(dev); -+ if (err) { -+ dev_err(&pdev->dev, "unable to register net device\n"); -+ goto err_free_irq; -+ } ++static void __init detect_sys_frequency(void) ++{ ++ switch (ar71xx_soc) { ++ case AR71XX_SOC_AR7130: ++ case AR71XX_SOC_AR7141: ++ case AR71XX_SOC_AR7161: ++ ar71xx_detect_sys_frequency(); ++ break; + -+ printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n", -+ dev->name, dev->base_addr, dev->irq); ++ case AR71XX_SOC_AR7240: ++ case AR71XX_SOC_AR7241: ++ case AR71XX_SOC_AR7242: ++ ar724x_detect_sys_frequency(); ++ break; + -+ ag71xx_dump_regs(ag); ++ case AR71XX_SOC_AR9130: ++ case AR71XX_SOC_AR9132: ++ ar91xx_detect_sys_frequency(); ++ break; + -+ ag71xx_hw_init(ag); ++ default: ++ BUG(); ++ } ++} + -+ ag71xx_dump_regs(ag); ++const char *get_system_type(void) ++{ ++ return ar71xx_sys_type; ++} + -+ err = ag71xx_phy_connect(ag); -+ if (err) -+ goto err_unregister_netdev; ++unsigned int __cpuinit get_c0_compare_irq(void) ++{ ++ return CP0_LEGACY_COMPARE_IRQ; ++} + -+ err = ag71xx_debugfs_init(ag); -+ if (err) -+ goto err_phy_disconnect; ++void __init plat_mem_setup(void) ++{ ++ set_io_port_base(KSEG1); + -+ platform_set_drvdata(pdev, dev); ++ ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE, ++ AR71XX_DDR_CTRL_SIZE); + -+ return 0; ++ ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE, ++ AR71XX_PLL_SIZE); + -+ err_phy_disconnect: -+ ag71xx_phy_disconnect(ag); -+ err_unregister_netdev: -+ unregister_netdev(dev); -+ err_free_irq: -+ free_irq(dev->irq, dev); -+ err_unmap_mii_ctrl: -+ iounmap(ag->mii_ctrl); -+ err_unmap_base: -+ iounmap(ag->mac_base); -+ err_free_dev: -+ kfree(dev); -+ err_out: -+ platform_set_drvdata(pdev, NULL); -+ return err; -+} ++ ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE, ++ AR71XX_RESET_SIZE); + -+static int __exit ag71xx_remove(struct platform_device *pdev) -+{ -+ struct net_device *dev = platform_get_drvdata(pdev); ++ ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); + -+ if (dev) { -+ struct ag71xx *ag = netdev_priv(dev); ++ ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE, ++ AR71XX_USB_CTRL_SIZE); + -+ ag71xx_debugfs_exit(ag); -+ ag71xx_phy_disconnect(ag); -+ unregister_netdev(dev); -+ free_irq(dev->irq, dev); -+ iounmap(ag->mii_ctrl); -+ iounmap(ag->mac_base); -+ kfree(dev); -+ platform_set_drvdata(pdev, NULL); -+ } ++ ar71xx_detect_mem_size(); ++ ar71xx_detect_sys_type(); ++ detect_sys_frequency(); + -+ return 0; -+} ++ printk(KERN_INFO ++ "%s, CPU:%u.%03u MHz, AHB:%u.%03u MHz, DDR:%u.%03u MHz\n", ++ ar71xx_sys_type, ++ ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000, ++ ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000, ++ ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000); + -+static struct platform_driver ag71xx_driver = { -+ .probe = ag71xx_probe, -+ .remove = __exit_p(ag71xx_remove), -+ .driver = { -+ .name = AG71XX_DRV_NAME, -+ } -+}; ++ _machine_restart = ar71xx_restart; ++ _machine_halt = ar71xx_halt; ++ pm_power_off = ar71xx_halt; ++} + -+static int __init ag71xx_module_init(void) ++void __init plat_time_init(void) +{ -+ int ret; ++ mips_hpt_frequency = ar71xx_cpu_freq / 2; ++} + -+ ret = ag71xx_debugfs_root_init(); -+ if (ret) -+ goto err_out; ++__setup("board=", mips_machtype_setup); + -+ ret = ag71xx_mdio_driver_init(); -+ if (ret) -+ goto err_debugfs_exit; ++static int __init ar71xx_machine_setup(void) ++{ ++ ar71xx_gpio_init(); + -+ ret = platform_driver_register(&ag71xx_driver); -+ if (ret) -+ goto err_mdio_exit; ++ ar71xx_add_device_uart(); ++ ar71xx_add_device_wdt(); + ++ mips_machine_setup(); + return 0; -+ -+ err_mdio_exit: -+ ag71xx_mdio_driver_exit(); -+ err_debugfs_exit: -+ ag71xx_debugfs_root_exit(); -+ err_out: -+ return ret; +} + -+static void __exit ag71xx_module_exit(void) ++arch_initcall(ar71xx_machine_setup); ++ ++static void __init ar71xx_generic_init(void) +{ -+ platform_driver_unregister(&ag71xx_driver); -+ ag71xx_mdio_driver_exit(); -+ ag71xx_debugfs_root_exit(); ++ /* Nothing to do */ +} + -+module_init(ag71xx_module_init); -+module_exit(ag71xx_module_exit); -+ -+MODULE_VERSION(AG71XX_DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -+MODULE_ALIAS("platform:" AG71XX_DRV_NAME); -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_mdio.c linux-2.6.35.7/drivers/net/ag71xx/ag71xx_mdio.c ---- linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_mdio.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/ag71xx_mdio.c 2010-10-14 20:28:00.678101104 +0200 -@@ -0,0 +1,243 @@ ++MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board", ++ ar71xx_generic_init); +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/ar71xx.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/ar71xx.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/ar71xx.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,514 @@ +/* -+ * Atheros AR71xx built-in ethernet mac driver ++ * Atheros AR71xx SoC specific definitions + * -+ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008-2009 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * -+ * Based on Atheros' AG7100 driver ++ * Parts of this file are based on Atheros' 2.6.15 BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include "ag71xx.h" ++#ifndef __ASM_MACH_AR71XX_H ++#define __ASM_MACH_AR71XX_H + -+#define AG71XX_MDIO_RETRY 1000 -+#define AG71XX_MDIO_DELAY 5 ++#include ++#include ++#include ++#include + -+static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, -+ u32 value) -+{ -+ void __iomem *r; ++#ifndef __ASSEMBLER__ + -+ r = am->mdio_base + reg; -+ __raw_writel(value, r); ++#define AR71XX_PCI_MEM_BASE 0x10000000 ++#define AR71XX_PCI_MEM_SIZE 0x08000000 ++#define AR71XX_APB_BASE 0x18000000 ++#define AR71XX_GE0_BASE 0x19000000 ++#define AR71XX_GE0_SIZE 0x01000000 ++#define AR71XX_GE1_BASE 0x1a000000 ++#define AR71XX_GE1_SIZE 0x01000000 ++#define AR71XX_EHCI_BASE 0x1b000000 ++#define AR71XX_EHCI_SIZE 0x01000000 ++#define AR71XX_OHCI_BASE 0x1c000000 ++#define AR71XX_OHCI_SIZE 0x01000000 ++#define AR7240_OHCI_BASE 0x1b000000 ++#define AR7240_OHCI_SIZE 0x01000000 ++#define AR71XX_SPI_BASE 0x1f000000 ++#define AR71XX_SPI_SIZE 0x01000000 + -+ /* flush write */ -+ (void) __raw_readl(r); -+} ++#define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000) ++#define AR71XX_DDR_CTRL_SIZE 0x10000 ++#define AR71XX_CPU_BASE (AR71XX_APB_BASE + 0x00010000) ++#define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000) ++#define AR71XX_UART_SIZE 0x10000 ++#define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000) ++#define AR71XX_USB_CTRL_SIZE 0x10000 ++#define AR71XX_GPIO_BASE (AR71XX_APB_BASE + 0x00040000) ++#define AR71XX_GPIO_SIZE 0x10000 ++#define AR71XX_PLL_BASE (AR71XX_APB_BASE + 0x00050000) ++#define AR71XX_PLL_SIZE 0x10000 ++#define AR71XX_RESET_BASE (AR71XX_APB_BASE + 0x00060000) ++#define AR71XX_RESET_SIZE 0x10000 ++#define AR71XX_MII_BASE (AR71XX_APB_BASE + 0x00070000) ++#define AR71XX_MII_SIZE 0x10000 ++#define AR71XX_SLIC_BASE (AR71XX_APB_BASE + 0x00090000) ++#define AR71XX_SLIC_SIZE 0x10000 ++#define AR71XX_DMA_BASE (AR71XX_APB_BASE + 0x000A0000) ++#define AR71XX_DMA_SIZE 0x10000 ++#define AR71XX_STEREO_BASE (AR71XX_APB_BASE + 0x000B0000) ++#define AR71XX_STEREO_SIZE 0x10000 + -+static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) -+{ -+ return __raw_readl(am->mdio_base + reg); -+} ++#define AR724X_PCI_CRP_BASE (AR71XX_APB_BASE + 0x000C0000) ++#define AR724X_PCI_CRP_SIZE 0x100 + -+static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) -+{ -+ DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", -+ am->mii_bus->name, -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); -+ DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", -+ am->mii_bus->name, -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), -+ ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); -+} ++#define AR724X_PCI_CTRL_BASE (AR71XX_APB_BASE + 0x000F0000) ++#define AR724X_PCI_CTRL_SIZE 0x100 + -+static int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) -+{ -+ int ret; -+ int i; ++#define AR91XX_WMAC_BASE (AR71XX_APB_BASE + 0x000C0000) ++#define AR91XX_WMAC_SIZE 0x30000 + -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, -+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); ++#define AR71XX_MEM_SIZE_MIN 0x0200000 ++#define AR71XX_MEM_SIZE_MAX 0x10000000 + -+ i = AG71XX_MDIO_RETRY; -+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { -+ if (i-- == 0) { -+ printk(KERN_ERR "%s: mii_read timed out\n", -+ am->mii_bus->name); -+ ret = 0xffff; -+ goto out; -+ } -+ udelay(AG71XX_MDIO_DELAY); -+ } ++#define AR71XX_CPU_IRQ_BASE 0 ++#define AR71XX_MISC_IRQ_BASE 8 ++#define AR71XX_MISC_IRQ_COUNT 8 ++#define AR71XX_GPIO_IRQ_BASE 16 ++#define AR71XX_GPIO_IRQ_COUNT 32 ++#define AR71XX_PCI_IRQ_BASE 48 ++#define AR71XX_PCI_IRQ_COUNT 8 + -+ ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); ++#define AR71XX_CPU_IRQ_IP2 (AR71XX_CPU_IRQ_BASE + 2) ++#define AR71XX_CPU_IRQ_USB (AR71XX_CPU_IRQ_BASE + 3) ++#define AR71XX_CPU_IRQ_GE0 (AR71XX_CPU_IRQ_BASE + 4) ++#define AR71XX_CPU_IRQ_GE1 (AR71XX_CPU_IRQ_BASE + 5) ++#define AR71XX_CPU_IRQ_MISC (AR71XX_CPU_IRQ_BASE + 6) ++#define AR71XX_CPU_IRQ_TIMER (AR71XX_CPU_IRQ_BASE + 7) + -+ DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); ++#define AR71XX_MISC_IRQ_TIMER (AR71XX_MISC_IRQ_BASE + 0) ++#define AR71XX_MISC_IRQ_ERROR (AR71XX_MISC_IRQ_BASE + 1) ++#define AR71XX_MISC_IRQ_GPIO (AR71XX_MISC_IRQ_BASE + 2) ++#define AR71XX_MISC_IRQ_UART (AR71XX_MISC_IRQ_BASE + 3) ++#define AR71XX_MISC_IRQ_WDOG (AR71XX_MISC_IRQ_BASE + 4) ++#define AR71XX_MISC_IRQ_PERFC (AR71XX_MISC_IRQ_BASE + 5) ++#define AR71XX_MISC_IRQ_OHCI (AR71XX_MISC_IRQ_BASE + 6) ++#define AR71XX_MISC_IRQ_DMA (AR71XX_MISC_IRQ_BASE + 7) + -+ out: -+ return ret; -+} ++#define AR71XX_GPIO_IRQ(_x) (AR71XX_GPIO_IRQ_BASE + (_x)) + -+static void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, -+ int addr, int reg, u16 val) -+{ -+ int i; ++#define AR71XX_PCI_IRQ_DEV0 (AR71XX_PCI_IRQ_BASE + 0) ++#define AR71XX_PCI_IRQ_DEV1 (AR71XX_PCI_IRQ_BASE + 1) ++#define AR71XX_PCI_IRQ_DEV2 (AR71XX_PCI_IRQ_BASE + 2) ++#define AR71XX_PCI_IRQ_CORE (AR71XX_PCI_IRQ_BASE + 4) + -+ DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); ++extern u32 ar71xx_ahb_freq; ++extern u32 ar71xx_cpu_freq; ++extern u32 ar71xx_ddr_freq; + -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, -+ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); ++enum ar71xx_soc_type { ++ AR71XX_SOC_UNKNOWN, ++ AR71XX_SOC_AR7130, ++ AR71XX_SOC_AR7141, ++ AR71XX_SOC_AR7161, ++ AR71XX_SOC_AR7240, ++ AR71XX_SOC_AR7241, ++ AR71XX_SOC_AR7242, ++ AR71XX_SOC_AR9130, ++ AR71XX_SOC_AR9132 ++}; + -+ i = AG71XX_MDIO_RETRY; -+ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { -+ if (i-- == 0) { -+ printk(KERN_ERR "%s: mii_write timed out\n", -+ am->mii_bus->name); -+ break; -+ } -+ udelay(AG71XX_MDIO_DELAY); -+ } -+} ++extern enum ar71xx_soc_type ar71xx_soc; + -+static int ag71xx_mdio_reset(struct mii_bus *bus) -+{ -+ struct ag71xx_mdio *am = bus->priv; -+ u32 t; ++/* ++ * PLL block ++ */ ++#define AR71XX_PLL_REG_CPU_CONFIG 0x00 ++#define AR71XX_PLL_REG_SEC_CONFIG 0x04 ++#define AR71XX_PLL_REG_ETH0_INT_CLOCK 0x10 ++#define AR71XX_PLL_REG_ETH1_INT_CLOCK 0x14 + -+ if (am->pdata->is_ar7240) -+ t = MII_CFG_CLK_DIV_6; -+ else -+ t = MII_CFG_CLK_DIV_28; ++#define AR71XX_PLL_DIV_SHIFT 3 ++#define AR71XX_PLL_DIV_MASK 0x1f ++#define AR71XX_CPU_DIV_SHIFT 16 ++#define AR71XX_CPU_DIV_MASK 0x3 ++#define AR71XX_DDR_DIV_SHIFT 18 ++#define AR71XX_DDR_DIV_MASK 0x3 ++#define AR71XX_AHB_DIV_SHIFT 20 ++#define AR71XX_AHB_DIV_MASK 0x7 + -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); -+ udelay(100); ++#define AR71XX_ETH0_PLL_SHIFT 17 ++#define AR71XX_ETH1_PLL_SHIFT 19 ++ ++#define AR724X_PLL_REG_CPU_CONFIG 0x00 ++#define AR724X_PLL_REG_PCIE_CONFIG 0x18 ++ ++#define AR724X_PLL_DIV_SHIFT 0 ++#define AR724X_PLL_DIV_MASK 0x3ff ++#define AR724X_PLL_REF_DIV_SHIFT 10 ++#define AR724X_PLL_REF_DIV_MASK 0xf ++#define AR724X_AHB_DIV_SHIFT 19 ++#define AR724X_AHB_DIV_MASK 0x1 ++#define AR724X_DDR_DIV_SHIFT 22 ++#define AR724X_DDR_DIV_MASK 0x3 + -+ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); -+ udelay(100); ++#define AR91XX_PLL_REG_CPU_CONFIG 0x00 ++#define AR91XX_PLL_REG_ETH_CONFIG 0x04 ++#define AR91XX_PLL_REG_ETH0_INT_CLOCK 0x14 ++#define AR91XX_PLL_REG_ETH1_INT_CLOCK 0x18 + -+ return 0; -+} ++#define AR91XX_PLL_DIV_SHIFT 0 ++#define AR91XX_PLL_DIV_MASK 0x3ff ++#define AR91XX_DDR_DIV_SHIFT 22 ++#define AR91XX_DDR_DIV_MASK 0x3 ++#define AR91XX_AHB_DIV_SHIFT 19 ++#define AR91XX_AHB_DIV_MASK 0x1 + -+static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) -+{ -+ struct ag71xx_mdio *am = bus->priv; ++#define AR91XX_ETH0_PLL_SHIFT 20 ++#define AR91XX_ETH1_PLL_SHIFT 22 + -+ return ag71xx_mdio_mii_read(am, addr, reg); -+} ++extern void __iomem *ar71xx_pll_base; + -+static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) ++static inline void ar71xx_pll_wr(unsigned reg, u32 val) +{ -+ struct ag71xx_mdio *am = bus->priv; -+ -+ ag71xx_mdio_mii_write(am, addr, reg, val); -+ return 0; ++ __raw_writel(val, ar71xx_pll_base + reg); +} + -+static int __init ag71xx_mdio_probe(struct platform_device *pdev) ++static inline u32 ar71xx_pll_rr(unsigned reg) +{ -+ struct ag71xx_mdio_platform_data *pdata; -+ struct ag71xx_mdio *am; -+ struct resource *res; -+ int i; -+ int err; -+ -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified\n"); -+ return -EINVAL; -+ } ++ return __raw_readl(ar71xx_pll_base + reg); ++} + -+ am = kzalloc(sizeof(*am), GFP_KERNEL); -+ if (!am) { -+ err = -ENOMEM; -+ goto err_out; -+ } ++/* ++ * USB_CONFIG block ++ */ ++#define USB_CTRL_REG_FLADJ 0x00 ++#define USB_CTRL_REG_CONFIG 0x04 + -+ am->pdata = pdata; ++extern void __iomem *ar71xx_usb_ctrl_base; + -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_err(&pdev->dev, "no iomem resource found\n"); -+ err = -ENXIO; -+ goto err_out; -+ } ++static inline void ar71xx_usb_ctrl_wr(unsigned reg, u32 val) ++{ ++ __raw_writel(val, ar71xx_usb_ctrl_base + reg); ++} + -+ am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); -+ if (!am->mdio_base) { -+ dev_err(&pdev->dev, "unable to ioremap registers\n"); -+ err = -ENOMEM; -+ goto err_free_mdio; -+ } ++static inline u32 ar71xx_usb_ctrl_rr(unsigned reg) ++{ ++ return __raw_readl(ar71xx_usb_ctrl_base + reg); ++} + -+ am->mii_bus = mdiobus_alloc(); -+ if (am->mii_bus == NULL) { -+ err = -ENOMEM; -+ goto err_iounmap; -+ } ++/* ++ * GPIO block ++ */ ++#define GPIO_REG_OE 0x00 ++#define GPIO_REG_IN 0x04 ++#define GPIO_REG_OUT 0x08 ++#define GPIO_REG_SET 0x0c ++#define GPIO_REG_CLEAR 0x10 ++#define GPIO_REG_INT_MODE 0x14 ++#define GPIO_REG_INT_TYPE 0x18 ++#define GPIO_REG_INT_POLARITY 0x1c ++#define GPIO_REG_INT_PENDING 0x20 ++#define GPIO_REG_INT_ENABLE 0x24 ++#define GPIO_REG_FUNC 0x28 + -+ am->mii_bus->name = "ag71xx_mdio"; -+ am->mii_bus->read = ag71xx_mdio_read; -+ am->mii_bus->write = ag71xx_mdio_write; -+ am->mii_bus->reset = ag71xx_mdio_reset; -+ am->mii_bus->irq = am->mii_irq; -+ am->mii_bus->priv = am; -+ am->mii_bus->parent = &pdev->dev; -+ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); -+ am->mii_bus->phy_mask = pdata->phy_mask; ++#define AR71XX_GPIO_FUNC_STEREO_EN BIT(17) ++#define AR71XX_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13) ++#define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12) ++#define AR71XX_GPIO_FUNC_UART_EN BIT(8) ++#define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4) ++#define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0) + -+ for (i = 0; i < PHY_MAX_ADDR; i++) -+ am->mii_irq[i] = PHY_POLL; ++#define AR71XX_GPIO_COUNT 16 + -+ ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); ++#define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19) ++#define AR724X_GPIO_FUNC_SPI_EN BIT(18) ++#define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14) ++#define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13) ++#define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12) ++#define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11) ++#define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10) ++#define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9) ++#define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4) ++#define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3) ++#define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2) ++#define AR724X_GPIO_FUNC_UART_EN BIT(1) ++#define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0) + -+ err = mdiobus_register(am->mii_bus); -+ if (err) -+ goto err_free_bus; ++#define AR724X_GPIO_COUNT 18 + -+ ag71xx_mdio_dump_regs(am); ++#define AR91XX_GPIO_FUNC_WMAC_LED_EN BIT(22) ++#define AR91XX_GPIO_FUNC_EXP_PORT_CS_EN BIT(21) ++#define AR91XX_GPIO_FUNC_I2S_REFCLKEN BIT(20) ++#define AR91XX_GPIO_FUNC_I2S_MCKEN BIT(19) ++#define AR91XX_GPIO_FUNC_I2S1_EN BIT(18) ++#define AR91XX_GPIO_FUNC_I2S0_EN BIT(17) ++#define AR91XX_GPIO_FUNC_SLIC_EN BIT(16) ++#define AR91XX_GPIO_FUNC_UART_RTSCTS_EN BIT(9) ++#define AR91XX_GPIO_FUNC_UART_EN BIT(8) ++#define AR91XX_GPIO_FUNC_USB_CLK_EN BIT(4) + -+ platform_set_drvdata(pdev, am); -+ return 0; ++#define AR91XX_GPIO_COUNT 22 + -+ err_free_bus: -+ mdiobus_free(am->mii_bus); -+ err_iounmap: -+ iounmap(am->mdio_base); -+ err_free_mdio: -+ kfree(am); -+ err_out: -+ return err; -+} ++extern void __iomem *ar71xx_gpio_base; + -+static int __exit ag71xx_mdio_remove(struct platform_device *pdev) ++static inline void ar71xx_gpio_wr(unsigned reg, u32 value) +{ -+ struct ag71xx_mdio *am = platform_get_drvdata(pdev); -+ -+ if (am) { -+ mdiobus_unregister(am->mii_bus); -+ mdiobus_free(am->mii_bus); -+ iounmap(am->mdio_base); -+ kfree(am); -+ platform_set_drvdata(pdev, NULL); -+ } -+ -+ return 0; ++ __raw_writel(value, ar71xx_gpio_base + reg); +} + -+static struct platform_driver ag71xx_mdio_driver = { -+ .probe = ag71xx_mdio_probe, -+ .remove = __exit_p(ag71xx_mdio_remove), -+ .driver = { -+ .name = "ag71xx-mdio", -+ } -+}; -+ -+int ag71xx_mdio_driver_init(void) ++static inline u32 ar71xx_gpio_rr(unsigned reg) +{ -+ return platform_driver_register(&ag71xx_mdio_driver); ++ return __raw_readl(ar71xx_gpio_base + reg); +} + -+void ag71xx_mdio_driver_exit(void) -+{ -+ platform_driver_unregister(&ag71xx_mdio_driver); -+} -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_phy.c linux-2.6.35.7/drivers/net/ag71xx/ag71xx_phy.c ---- linux-2.6.35.7.orig/drivers/net/ag71xx/ag71xx_phy.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/ag71xx_phy.c 2010-10-14 20:28:00.708092093 +0200 -@@ -0,0 +1,213 @@ ++void ar71xx_gpio_init(void) __init; ++void ar71xx_gpio_function_enable(u32 mask); ++void ar71xx_gpio_function_disable(u32 mask); ++void ar71xx_gpio_function_setup(u32 set, u32 clear); ++ +/* -+ * Atheros AR71xx built-in ethernet mac driver -+ * -+ * Copyright (C) 2008-2010 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Based on Atheros' AG7100 driver -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. ++ * DDR_CTRL block + */ ++#define AR71XX_DDR_REG_PCI_WIN0 0x7c ++#define AR71XX_DDR_REG_PCI_WIN1 0x80 ++#define AR71XX_DDR_REG_PCI_WIN2 0x84 ++#define AR71XX_DDR_REG_PCI_WIN3 0x88 ++#define AR71XX_DDR_REG_PCI_WIN4 0x8c ++#define AR71XX_DDR_REG_PCI_WIN5 0x90 ++#define AR71XX_DDR_REG_PCI_WIN6 0x94 ++#define AR71XX_DDR_REG_PCI_WIN7 0x98 ++#define AR71XX_DDR_REG_FLUSH_GE0 0x9c ++#define AR71XX_DDR_REG_FLUSH_GE1 0xa0 ++#define AR71XX_DDR_REG_FLUSH_USB 0xa4 ++#define AR71XX_DDR_REG_FLUSH_PCI 0xa8 + -+#include "ag71xx.h" -+ -+static void ag71xx_phy_link_adjust(struct net_device *dev) -+{ -+ struct ag71xx *ag = netdev_priv(dev); -+ struct phy_device *phydev = ag->phy_dev; -+ unsigned long flags; -+ int status_change = 0; -+ -+ spin_lock_irqsave(&ag->lock, flags); -+ -+ if (phydev->link) { -+ if (ag->duplex != phydev->duplex -+ || ag->speed != phydev->speed) { -+ status_change = 1; -+ } -+ } -+ -+ if (phydev->link != ag->link) -+ status_change = 1; ++#define AR724X_DDR_REG_FLUSH_GE0 0x7c ++#define AR724X_DDR_REG_FLUSH_GE1 0x80 ++#define AR724X_DDR_REG_FLUSH_USB 0x84 ++#define AR724X_DDR_REG_FLUSH_PCIE 0x88 + -+ ag->link = phydev->link; -+ ag->duplex = phydev->duplex; -+ ag->speed = phydev->speed; ++#define AR91XX_DDR_REG_FLUSH_GE0 0x7c ++#define AR91XX_DDR_REG_FLUSH_GE1 0x80 ++#define AR91XX_DDR_REG_FLUSH_USB 0x84 ++#define AR91XX_DDR_REG_FLUSH_WMAC 0x88 + -+ if (status_change) -+ ag71xx_link_adjust(ag); ++#define PCI_WIN0_OFFS 0x10000000 ++#define PCI_WIN1_OFFS 0x11000000 ++#define PCI_WIN2_OFFS 0x12000000 ++#define PCI_WIN3_OFFS 0x13000000 ++#define PCI_WIN4_OFFS 0x14000000 ++#define PCI_WIN5_OFFS 0x15000000 ++#define PCI_WIN6_OFFS 0x16000000 ++#define PCI_WIN7_OFFS 0x07000000 + -+ spin_unlock_irqrestore(&ag->lock, flags); -+} ++extern void __iomem *ar71xx_ddr_base; + -+void ag71xx_phy_start(struct ag71xx *ag) ++static inline void ar71xx_ddr_wr(unsigned reg, u32 val) +{ -+ if (ag->phy_dev) { -+ phy_start(ag->phy_dev); -+ } else { -+ ag->link = 1; -+ ag71xx_link_adjust(ag); -+ } ++ __raw_writel(val, ar71xx_ddr_base + reg); +} + -+void ag71xx_phy_stop(struct ag71xx *ag) ++static inline u32 ar71xx_ddr_rr(unsigned reg) +{ -+ if (ag->phy_dev) { -+ phy_stop(ag->phy_dev); -+ } else { -+ ag->link = 0; -+ ag71xx_link_adjust(ag); -+ } ++ return __raw_readl(ar71xx_ddr_base + reg); +} + -+static int ag71xx_phy_connect_fixed(struct ag71xx *ag) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ int ret = 0; ++void ar71xx_ddr_flush(u32 reg); + -+ /* use fixed settings */ -+ switch (pdata->speed) { -+ case SPEED_10: -+ case SPEED_100: -+ case SPEED_1000: -+ break; -+ default: -+ printk(KERN_ERR "%s: invalid speed specified\n", dev->name); -+ ret = -EINVAL; -+ break; -+ } ++/* ++ * PCI block ++ */ ++#define AR71XX_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + PCI_WIN7_OFFS + 0x10000) ++#define AR71XX_PCI_CFG_SIZE 0x100 + -+ printk(KERN_DEBUG "%s: using fixed link parameters\n", dev->name); ++#define PCI_REG_CRP_AD_CBE 0x00 ++#define PCI_REG_CRP_WRDATA 0x04 ++#define PCI_REG_CRP_RDDATA 0x08 ++#define PCI_REG_CFG_AD 0x0c ++#define PCI_REG_CFG_CBE 0x10 ++#define PCI_REG_CFG_WRDATA 0x14 ++#define PCI_REG_CFG_RDDATA 0x18 ++#define PCI_REG_PCI_ERR 0x1c ++#define PCI_REG_PCI_ERR_ADDR 0x20 ++#define PCI_REG_AHB_ERR 0x24 ++#define PCI_REG_AHB_ERR_ADDR 0x28 + -+ ag->duplex = pdata->duplex; -+ ag->speed = pdata->speed; ++#define PCI_CRP_CMD_WRITE 0x00010000 ++#define PCI_CRP_CMD_READ 0x00000000 ++#define PCI_CFG_CMD_READ 0x0000000a ++#define PCI_CFG_CMD_WRITE 0x0000000b + -+ return ret; -+} ++#define PCI_IDSEL_ADL_START 17 + -+static int ag71xx_phy_connect_multi(struct ag71xx *ag) -+{ -+ struct net_device *dev = ag->dev; -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); -+ struct phy_device *phydev = NULL; -+ int phy_addr; -+ int ret = 0; ++#define AR724X_PCI_CFG_BASE (AR71XX_PCI_MEM_BASE + 0x4000000) ++#define AR724X_PCI_CFG_SIZE 0x1000 + -+ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { -+ if (!(pdata->phy_mask & (1 << phy_addr))) -+ continue; ++#define AR724X_PCI_REG_APP 0x00 ++#define AR724X_PCI_REG_RESET 0x18 ++#define AR724X_PCI_REG_INT_STATUS 0x4c ++#define AR724X_PCI_REG_INT_MASK 0x50 + -+ if (ag->mii_bus->phy_map[phy_addr] == NULL) -+ continue; ++#define AR724X_PCI_APP_LTSSM_ENABLE BIT(0) ++#define AR724X_PCI_RESET_LINK_UP BIT(0) + -+ DBG("%s: PHY found at %s, uid=%08x\n", -+ dev->name, -+ dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), -+ ag->mii_bus->phy_map[phy_addr]->phy_id); ++#define AR724X_PCI_INT_DEV0 BIT(14) + -+ if (phydev == NULL) -+ phydev = ag->mii_bus->phy_map[phy_addr]; -+ } ++/* ++ * RESET block ++ */ ++#define AR71XX_RESET_REG_TIMER 0x00 ++#define AR71XX_RESET_REG_TIMER_RELOAD 0x04 ++#define AR71XX_RESET_REG_WDOG_CTRL 0x08 ++#define AR71XX_RESET_REG_WDOG 0x0c ++#define AR71XX_RESET_REG_MISC_INT_STATUS 0x10 ++#define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 ++#define AR71XX_RESET_REG_PCI_INT_STATUS 0x18 ++#define AR71XX_RESET_REG_PCI_INT_ENABLE 0x1c ++#define AR71XX_RESET_REG_GLOBAL_INT_STATUS 0x20 ++#define AR71XX_RESET_REG_RESET_MODULE 0x24 ++#define AR71XX_RESET_REG_PERFC_CTRL 0x2c ++#define AR71XX_RESET_REG_PERFC0 0x30 ++#define AR71XX_RESET_REG_PERFC1 0x34 ++#define AR71XX_RESET_REG_REV_ID 0x90 + -+ if (!phydev) { -+ printk(KERN_ERR "%s: no PHY found with phy_mask=%08x\n", -+ dev->name, pdata->phy_mask); -+ return -ENODEV; -+ } ++#define AR91XX_RESET_REG_GLOBAL_INT_STATUS 0x18 ++#define AR91XX_RESET_REG_RESET_MODULE 0x1c ++#define AR91XX_RESET_REG_PERF_CTRL 0x20 ++#define AR91XX_RESET_REG_PERFC0 0x24 ++#define AR91XX_RESET_REG_PERFC1 0x28 + -+ ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev), -+ &ag71xx_phy_link_adjust, 0, -+ pdata->phy_if_mode); ++#define AR724X_RESET_REG_RESET_MODULE 0x1c + -+ if (IS_ERR(ag->phy_dev)) { -+ printk(KERN_ERR "%s: could not connect to PHY at %s\n", -+ dev->name, dev_name(&phydev->dev)); -+ return PTR_ERR(ag->phy_dev); -+ } ++#define WDOG_CTRL_LAST_RESET BIT(31) ++#define WDOG_CTRL_ACTION_MASK 3 ++#define WDOG_CTRL_ACTION_NONE 0 /* no action */ ++#define WDOG_CTRL_ACTION_GPI 1 /* general purpose interrupt */ ++#define WDOG_CTRL_ACTION_NMI 2 /* NMI */ ++#define WDOG_CTRL_ACTION_FCR 3 /* full chip reset */ + -+ /* mask with MAC supported features */ -+ if (pdata->has_gbit) -+ phydev->supported &= PHY_GBIT_FEATURES; -+ else -+ phydev->supported &= PHY_BASIC_FEATURES; ++#define MISC_INT_DMA BIT(7) ++#define MISC_INT_OHCI BIT(6) ++#define MISC_INT_PERFC BIT(5) ++#define MISC_INT_WDOG BIT(4) ++#define MISC_INT_UART BIT(3) ++#define MISC_INT_GPIO BIT(2) ++#define MISC_INT_ERROR BIT(1) ++#define MISC_INT_TIMER BIT(0) + -+ phydev->advertising = phydev->supported; ++#define PCI_INT_CORE BIT(4) ++#define PCI_INT_DEV2 BIT(2) ++#define PCI_INT_DEV1 BIT(1) ++#define PCI_INT_DEV0 BIT(0) + -+ printk(KERN_DEBUG "%s: connected to PHY at %s [uid=%08x, driver=%s]\n", -+ dev->name, dev_name(&phydev->dev), -+ phydev->phy_id, phydev->drv->name); ++#define RESET_MODULE_EXTERNAL BIT(28) ++#define RESET_MODULE_FULL_CHIP BIT(24) ++#define RESET_MODULE_AMBA2WMAC BIT(22) ++#define RESET_MODULE_CPU_NMI BIT(21) ++#define RESET_MODULE_CPU_COLD BIT(20) ++#define RESET_MODULE_DMA BIT(19) ++#define RESET_MODULE_SLIC BIT(18) ++#define RESET_MODULE_STEREO BIT(17) ++#define RESET_MODULE_DDR BIT(16) ++#define RESET_MODULE_GE1_MAC BIT(13) ++#define RESET_MODULE_GE1_PHY BIT(12) ++#define RESET_MODULE_USBSUS_OVERRIDE BIT(10) ++#define RESET_MODULE_GE0_MAC BIT(9) ++#define RESET_MODULE_GE0_PHY BIT(8) ++#define RESET_MODULE_USB_OHCI_DLL BIT(6) ++#define RESET_MODULE_USB_HOST BIT(5) ++#define RESET_MODULE_USB_PHY BIT(4) ++#define RESET_MODULE_USB_OHCI_DLL_7240 BIT(3) ++#define RESET_MODULE_PCI_BUS BIT(1) ++#define RESET_MODULE_PCI_CORE BIT(0) + -+ ag->link = 0; -+ ag->speed = 0; -+ ag->duplex = -1; ++#define AR724X_RESET_GE1_MDIO BIT(23) ++#define AR724X_RESET_GE0_MDIO BIT(22) ++#define AR724X_RESET_PCIE_PHY_SERIAL BIT(10) ++#define AR724X_RESET_PCIE_PHY BIT(7) ++#define AR724X_RESET_PCIE BIT(6) + -+ return ret; -+} ++#define REV_ID_MAJOR_MASK 0xfff0 ++#define REV_ID_MAJOR_AR71XX 0x00a0 ++#define REV_ID_MAJOR_AR913X 0x00b0 ++#define REV_ID_MAJOR_AR7240 0x00c0 ++#define REV_ID_MAJOR_AR7241 0x0100 ++#define REV_ID_MAJOR_AR7242 0x1100 + -+static int dev_is_class(struct device *dev, void *class) -+{ -+ if (dev->class != NULL && !strcmp(dev->class->name, class)) -+ return 1; ++#define AR71XX_REV_ID_MINOR_MASK 0x3 ++#define AR71XX_REV_ID_MINOR_AR7130 0x0 ++#define AR71XX_REV_ID_MINOR_AR7141 0x1 ++#define AR71XX_REV_ID_MINOR_AR7161 0x2 ++#define AR71XX_REV_ID_REVISION_MASK 0x3 ++#define AR71XX_REV_ID_REVISION_SHIFT 2 + -+ return 0; -+} ++#define AR91XX_REV_ID_MINOR_MASK 0x3 ++#define AR91XX_REV_ID_MINOR_AR9130 0x0 ++#define AR91XX_REV_ID_MINOR_AR9132 0x1 ++#define AR91XX_REV_ID_REVISION_MASK 0x3 ++#define AR91XX_REV_ID_REVISION_SHIFT 2 + -+static struct device *dev_find_class(struct device *parent, char *class) -+{ -+ if (dev_is_class(parent, class)) { -+ get_device(parent); -+ return parent; -+ } ++#define AR724X_REV_ID_REVISION_MASK 0x3 + -+ return device_find_child(parent, class, dev_is_class); ++extern void __iomem *ar71xx_reset_base; ++ ++static inline void ar71xx_reset_wr(unsigned reg, u32 val) ++{ ++ __raw_writel(val, ar71xx_reset_base + reg); +} + -+static struct mii_bus *dev_to_mii_bus(struct device *dev) ++static inline u32 ar71xx_reset_rr(unsigned reg) +{ -+ struct device *d; ++ return __raw_readl(ar71xx_reset_base + reg); ++} + -+ d = dev_find_class(dev, "mdio_bus"); -+ if (d != NULL) { -+ struct mii_bus *bus; ++void ar71xx_device_stop(u32 mask); ++void ar71xx_device_start(u32 mask); ++int ar71xx_device_stopped(u32 mask); + -+ bus = to_mii_bus(d); -+ put_device(d); ++/* ++ * SPI block ++ */ ++#define SPI_REG_FS 0x00 /* Function Select */ ++#define SPI_REG_CTRL 0x04 /* SPI Control */ ++#define SPI_REG_IOC 0x08 /* SPI I/O Control */ ++#define SPI_REG_RDS 0x0c /* Read Data Shift */ + -+ return bus; -+ } ++#define SPI_FS_GPIO BIT(0) /* Enable GPIO mode */ + -+ return NULL; -+} ++#define SPI_CTRL_RD BIT(6) /* Remap Disable */ ++#define SPI_CTRL_DIV_MASK 0x3f + -+int ag71xx_phy_connect(struct ag71xx *ag) -+{ -+ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++#define SPI_IOC_DO BIT(0) /* Data Out pin */ ++#define SPI_IOC_CLK BIT(8) /* CLK pin */ ++#define SPI_IOC_CS(n) BIT(16 + (n)) ++#define SPI_IOC_CS0 SPI_IOC_CS(0) ++#define SPI_IOC_CS1 SPI_IOC_CS(1) ++#define SPI_IOC_CS2 SPI_IOC_CS(2) ++#define SPI_IOC_CS_ALL (SPI_IOC_CS0 | SPI_IOC_CS1 | SPI_IOC_CS2) + -+ ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); -+ if (ag->mii_bus == NULL) { -+ printk(KERN_ERR "%s: unable to find MII bus on device '%s'\n", -+ ag->dev->name, dev_name(pdata->mii_bus_dev)); -+ return -ENODEV; -+ } ++void ar71xx_flash_acquire(void); ++void ar71xx_flash_release(void); + -+ /* Reset the mdio bus explicitly */ -+ if (ag->mii_bus->reset) { -+ mutex_lock(&ag->mii_bus->mdio_lock); -+ ag->mii_bus->reset(ag->mii_bus); -+ mutex_unlock(&ag->mii_bus->mdio_lock); -+ } ++/* ++ * MII_CTRL block ++ */ ++#define MII_REG_MII0_CTRL 0x00 ++#define MII_REG_MII1_CTRL 0x04 + -+ if (pdata->phy_mask) -+ return ag71xx_phy_connect_multi(ag); ++#define MII0_CTRL_IF_GMII 0 ++#define MII0_CTRL_IF_MII 1 ++#define MII0_CTRL_IF_RGMII 2 ++#define MII0_CTRL_IF_RMII 3 + -+ return ag71xx_phy_connect_fixed(ag); -+} ++#define MII1_CTRL_IF_RGMII 0 ++#define MII1_CTRL_IF_RMII 1 + -+void ag71xx_phy_disconnect(struct ag71xx *ag) -+{ -+ if (ag->phy_dev) -+ phy_disconnect(ag->phy_dev); -+} -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/Kconfig linux-2.6.35.7/drivers/net/ag71xx/Kconfig ---- linux-2.6.35.7.orig/drivers/net/ag71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/Kconfig 2010-10-14 20:28:00.748098810 +0200 -@@ -0,0 +1,33 @@ -+config AG71XX -+ tristate "Atheros AR71xx built-in ethernet mac support" -+ depends on ATHEROS_AR71XX -+ select PHYLIB -+ help -+ If you wish to compile a kernel for AR71xx/91xx and enable -+ ethernet support, then you should always answer Y to this. ++#endif /* __ASSEMBLER__ */ + -+if AG71XX ++#endif /* __ASM_MACH_AR71XX_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/ar91xx_flash.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,26 @@ ++/* ++ * AR91xx parallel flash driver platform data definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+config AG71XX_DEBUG -+ bool "Atheros AR71xx built-in ethernet driver debugging" -+ default n -+ help -+ Atheros AR71xx built-in ethernet driver debugging messages. ++#ifndef __AR91XX_FLASH_H ++#define __AR91XX_FLASH_H + -+config AG71XX_DEBUG_FS -+ bool "Atheros AR71xx built-in ethernet driver debugfs support" -+ depends on DEBUG_FS -+ default n -+ help -+ Say Y, if you need access to various statistics provided by -+ the ag71xx driver. ++struct mtd_partition; + -+config AG71XX_AR8216_SUPPORT -+ bool "special support for the Atheros AR8216 switch" -+ default n -+ default y if AR71XX_MACH_WNR2000 || AR71XX_MACH_MZK_W04NU -+ help -+ Say 'y' here if you want to enable special support for the -+ Atheros AR8216 switch found on some boards. ++struct ar91xx_flash_platform_data { ++ unsigned int width; ++ u8 is_shared:1; ++#ifdef CONFIG_MTD_PARTITIONS ++ unsigned int nr_parts; ++ struct mtd_partition *parts; ++#endif ++}; + -+endif -diff -Nur linux-2.6.35.7.orig/drivers/net/ag71xx/Makefile linux-2.6.35.7/drivers/net/ag71xx/Makefile ---- linux-2.6.35.7.orig/drivers/net/ag71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/ag71xx/Makefile 2010-10-14 20:28:00.784356250 +0200 -@@ -0,0 +1,14 @@ -+# -+# Makefile for the Atheros AR71xx built-in ethernet macs -+# ++#endif /* __AR91XX_FLASH_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/cpu-feature-overrides.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,56 @@ ++/* ++ * Atheros AR71xx specific CPU feature overrides ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H + -+ag71xx-y += ag71xx_main.o -+ag71xx-y += ag71xx_ethtool.o -+ag71xx-y += ag71xx_phy.o -+ag71xx-y += ag71xx_mdio.o ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++#define cpu_has_watch 1 ++#define cpu_has_divec 1 + -+ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o -+ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o ++#define cpu_has_prefetch 1 ++#define cpu_has_ejtag 1 ++#define cpu_has_llsc 1 + -+obj-$(CONFIG_AG71XX) += ag71xx.o ++#define cpu_has_mips16 1 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 + -diff -Nur linux-2.6.35.7.orig/drivers/net/Kconfig linux-2.6.35.7/drivers/net/Kconfig ---- linux-2.6.35.7.orig/drivers/net/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/net/Kconfig 2010-10-14 20:28:00.828101196 +0200 -@@ -2032,6 +2032,8 @@ - - The safe and default value for this is N. - -+source drivers/net/ag71xx/Kconfig ++#define cpu_has_mips32r1 1 ++#define cpu_has_mips32r2 1 ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 + - config DL2K - tristate "DL2000/TC902x-based Gigabit Ethernet support" - depends on PCI -diff -Nur linux-2.6.35.7.orig/drivers/net/Kconfig.orig linux-2.6.35.7/drivers/net/Kconfig.orig ---- linux-2.6.35.7.orig/drivers/net/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/Kconfig.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,3314 @@ -+# -+# Network device configuration -+# ++#define cpu_has_dsp 0 ++#define cpu_has_mipsmt 0 + -+menuconfig NETDEVICES -+ default y if UML -+ depends on NET -+ bool "Network device support" -+ ---help--- -+ You can say N here if you don't intend to connect your Linux box to -+ any other computer at all. -+ -+ You'll have to say Y if your computer contains a network card that -+ you want to use under Linux. If you are going to run SLIP or PPP over -+ telephone line or null modem cable you need say Y here. Connecting -+ two machines with parallel ports using PLIP needs this, as well as -+ AX.25/KISS for sending Internet traffic over amateur radio links. -+ -+ See also "The Linux Network Administrator's Guide" by Olaf Kirch and -+ Terry Dawson. Available at . -+ -+ If unsure, say Y. -+ -+# All the following symbols are dependent on NETDEVICES - do not repeat -+# that for each of the symbols. -+if NETDEVICES -+ -+config IFB -+ tristate "Intermediate Functional Block support" -+ depends on NET_CLS_ACT -+ ---help--- -+ This is an intermediate driver that allows sharing of -+ resources. -+ To compile this driver as a module, choose M here: the module -+ will be called ifb. If you want to use more than one ifb -+ device at a time, you need to compile this driver as a module. -+ Instead of 'ifb', the devices will then be called 'ifb0', -+ 'ifb1' etc. -+ Look at the iproute2 documentation directory for usage etc -+ -+config DUMMY -+ tristate "Dummy net driver support" -+ ---help--- -+ This is essentially a bit-bucket device (i.e. traffic you send to -+ this device is consigned into oblivion) with a configurable IP -+ address. It is most commonly used in order to make your currently -+ inactive SLIP address seem like a real address for local programs. -+ If you use SLIP or PPP, you might want to say Y here. Since this -+ thing often comes in handy, the default is Y. It won't enlarge your -+ kernel either. What a deal. Read about it in the Network -+ Administrator's Guide, available from -+ . -+ -+ To compile this driver as a module, choose M here: the module -+ will be called dummy. If you want to use more than one dummy -+ device at a time, you need to compile this driver as a module. -+ Instead of 'dummy', the devices will then be called 'dummy0', -+ 'dummy1' etc. -+ -+config BONDING -+ tristate "Bonding driver support" -+ depends on INET -+ depends on IPV6 || IPV6=n -+ ---help--- -+ Say 'Y' or 'M' if you wish to be able to 'bond' multiple Ethernet -+ Channels together. This is called 'Etherchannel' by Cisco, -+ 'Trunking' by Sun, 802.3ad by the IEEE, and 'Bonding' in Linux. -+ -+ The driver supports multiple bonding modes to allow for both high -+ performance and high availability operation. -+ -+ Refer to for more -+ information. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called bonding. -+ -+config MACVLAN -+ tristate "MAC-VLAN support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ ---help--- -+ This allows one to create virtual interfaces that map packets to -+ or from specific MAC addresses to a particular interface. -+ -+ Macvlan devices can be added using the "ip" command from the -+ iproute2 package starting with the iproute2-2.6.23 release: -+ -+ "ip link add link [ address MAC ] [ NAME ] type macvlan" -+ -+ To compile this driver as a module, choose M here: the module -+ will be called macvlan. -+ -+config MACVTAP -+ tristate "MAC-VLAN based tap driver (EXPERIMENTAL)" -+ depends on MACVLAN -+ help -+ This adds a specialized tap character device driver that is based -+ on the MAC-VLAN network interface, called macvtap. A macvtap device -+ can be added in the same way as a macvlan device, using 'type -+ macvlan', and then be accessed through the tap user space interface. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called macvtap. -+ -+config EQUALIZER -+ tristate "EQL (serial line load balancing) support" -+ ---help--- -+ If you have two serial connections to some other computer (this -+ usually requires two modems and two telephone lines) and you use -+ SLIP (the protocol for sending Internet traffic over telephone -+ lines) or PPP (a better SLIP) on them, you can make them behave like -+ one double speed connection using this driver. Naturally, this has -+ to be supported at the other end as well, either with a similar EQL -+ Linux driver or with a Livingston Portmaster 2e. -+ -+ Say Y if you want this and read -+ . You may also want to read -+ section 6.2 of the NET-3-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here: the module -+ will be called eql. If unsure, say N. -+ -+config TUN -+ tristate "Universal TUN/TAP device driver support" -+ select CRC32 -+ ---help--- -+ TUN/TAP provides packet reception and transmission for user space -+ programs. It can be viewed as a simple Point-to-Point or Ethernet -+ device, which instead of receiving packets from a physical media, -+ receives them from user space program and instead of sending packets -+ via physical media writes them to the user space program. -+ -+ When a program opens /dev/net/tun, driver creates and registers -+ corresponding net device tunX or tapX. After a program closed above -+ devices, driver will automatically delete tunXX or tapXX device and -+ all routes corresponding to it. -+ -+ Please read for more -+ information. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called tun. -+ -+ If you don't know what to use this for, you don't need it. -+ -+config VETH -+ tristate "Virtual ethernet pair device" -+ ---help--- -+ This device is a local ethernet tunnel. Devices are created in pairs. -+ When one end receives the packet it appears on its pair and vice -+ versa. -+ -+config NET_SB1000 -+ tristate "General Instruments Surfboard 1000" -+ depends on PNP -+ ---help--- -+ This is a driver for the General Instrument (also known as -+ NextLevel) SURFboard 1000 internal -+ cable modem. This is an ISA card which is used by a number of cable -+ TV companies to provide cable modem access. It's a one-way -+ downstream-only cable modem, meaning that your upstream net link is -+ provided by your regular phone modem. -+ -+ At present this driver only compiles as a module, so say M here if -+ you have this card. The module will be called sb1000. Then read -+ for information on how -+ to use this module, as it needs special ppp scripts for establishing -+ a connection. Further documentation and the necessary scripts can be -+ found at: -+ -+ -+ -+ -+ -+ If you don't have this card, of course say N. -+ -+source "drivers/net/arcnet/Kconfig" -+ -+source "drivers/net/phy/Kconfig" ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 + -+# -+# Ethernet -+# ++#define cpu_dcache_line_size() 32 ++#define cpu_icache_line_size() 32 + -+menuconfig NET_ETHERNET -+ bool "Ethernet (10 or 100Mbit)" -+ depends on !UML -+ ---help--- -+ Ethernet (also called IEEE 802.3 or ISO 8802-2) is the most common -+ type of Local Area Network (LAN) in universities and companies. -+ -+ Common varieties of Ethernet are: 10BASE-2 or Thinnet (10 Mbps over -+ coaxial cable, linking computers in a chain), 10BASE-T or twisted -+ pair (10 Mbps over twisted pair cable, linking computers to central -+ hubs), 10BASE-F (10 Mbps over optical fiber links, using hubs), -+ 100BASE-TX (100 Mbps over two twisted pair cables, using hubs), -+ 100BASE-T4 (100 Mbps over 4 standard voice-grade twisted pair -+ cables, using hubs), 100BASE-FX (100 Mbps over optical fiber links) -+ [the 100BASE varieties are also known as Fast Ethernet], and Gigabit -+ Ethernet (1 Gbps over optical fiber or short copper links). -+ -+ If your Linux machine will be connected to an Ethernet and you have -+ an Ethernet network interface card (NIC) installed in your computer, -+ say Y here and read the Ethernet-HOWTO, available from -+ . You will then also have -+ to say Y to the driver for your particular NIC. -+ -+ Note that the answer to this question won't directly affect the -+ kernel: saying N will just cause the configurator to skip all -+ the questions about Ethernet network cards. If unsure, say N. -+ -+if NET_ETHERNET -+ -+config MII -+ tristate "Generic Media Independent Interface device support" -+ help -+ Most ethernet controllers have MII transceiver either as an external -+ or internal device. It is safe to say Y or M here even if your -+ ethernet card lack MII. ++#endif /* __ASM_MACH_AR71XX_CPU_FEATURE_OVERRIDES_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/gpio.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/gpio.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/gpio.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/gpio.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,53 @@ ++/* ++ * Atheros AR71xx GPIO API definitions ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ + -+config MACB -+ tristate "Atmel MACB support" -+ depends on AVR32 || ARCH_AT91SAM9260 || ARCH_AT91SAM9263 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45 || ARCH_AT91CAP9 -+ select PHYLIB -+ help -+ The Atmel MACB ethernet interface is found on many AT32 and AT91 -+ parts. Say Y to include support for the MACB chip. ++#ifndef __ASM_MACH_AR71XX_GPIO_H ++#define __ASM_MACH_AR71XX_GPIO_H + -+ To compile this driver as a module, choose M here: the module -+ will be called macb. ++#define ARCH_NR_GPIOS 64 ++#include + -+source "drivers/net/arm/Kconfig" ++#include + -+config AX88796 -+ tristate "ASIX AX88796 NE2000 clone support" -+ depends on ARM || MIPS || SUPERH -+ select CRC32 -+ select MII -+ help -+ AX88796 driver, using platform bus to provide -+ chip detection and resources ++extern unsigned long ar71xx_gpio_count; ++extern void __ar71xx_gpio_set_value(unsigned gpio, int value); ++extern int __ar71xx_gpio_get_value(unsigned gpio); + -+config AX88796_93CX6 -+ bool "ASIX AX88796 external 93CX6 eeprom support" -+ depends on AX88796 -+ select EEPROM_93CX6 -+ help -+ Select this if your platform comes with an external 93CX6 eeprom. ++static inline int gpio_to_irq(unsigned gpio) ++{ ++ return AR71XX_GPIO_IRQ(gpio); ++} + -+config MACE -+ tristate "MACE (Power Mac ethernet) support" -+ depends on PPC_PMAC && PPC32 -+ select CRC32 -+ help -+ Power Macintoshes and clones with Ethernet built-in on the -+ motherboard will usually use a MACE (Medium Access Control for -+ Ethernet) interface. Say Y to include support for the MACE chip. ++static inline int irq_to_gpio(unsigned irq) ++{ ++ return irq - AR71XX_GPIO_IRQ_BASE; ++} + -+ To compile this driver as a module, choose M here: the module -+ will be called mace. ++static inline int gpio_get_value(unsigned gpio) ++{ ++ if (gpio < ar71xx_gpio_count) ++ return __ar71xx_gpio_get_value(gpio); + -+config MACE_AAUI_PORT -+ bool "Use AAUI port instead of TP by default" -+ depends on MACE -+ help -+ Some Apple machines (notably the Apple Network Server) which use the -+ MACE ethernet chip have an Apple AUI port (small 15-pin connector), -+ instead of an 8-pin RJ45 connector for twisted-pair ethernet. Say -+ Y here if you have such a machine. If unsure, say N. -+ The driver will default to AAUI on ANS anyway, and if you use it as -+ a module, you can provide the port_aaui=0|1 to force the driver. -+ -+config BMAC -+ tristate "BMAC (G3 ethernet) support" -+ depends on PPC_PMAC && PPC32 -+ select CRC32 -+ help -+ Say Y for support of BMAC Ethernet interfaces. These are used on G3 -+ computers. ++ return __gpio_get_value(gpio); ++} + -+ To compile this driver as a module, choose M here: the module -+ will be called bmac. ++static inline void gpio_set_value(unsigned gpio, int value) ++{ ++ if (gpio < ar71xx_gpio_count) ++ __ar71xx_gpio_set_value(gpio, value); ++ else ++ __gpio_set_value(gpio, value); ++} + -+config ARIADNE -+ tristate "Ariadne support" -+ depends on ZORRO -+ help -+ If you have a Village Tronic Ariadne Ethernet adapter, say Y. -+ Otherwise, say N. ++#define gpio_cansleep __gpio_cansleep + -+ To compile this driver as a module, choose M here: the module -+ will be called ariadne. ++#endif /* __ASM_MACH_AR71XX_GPIO_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/irq.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/irq.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/irq.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/irq.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,17 @@ ++/* ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++#ifndef __ASM_MACH_AR71XX_IRQ_H ++#define __ASM_MACH_AR71XX_IRQ_H + -+config A2065 -+ tristate "A2065 support" -+ depends on ZORRO -+ select CRC32 -+ help -+ If you have a Commodore A2065 Ethernet adapter, say Y. Otherwise, -+ say N. ++#define MIPS_CPU_IRQ_BASE 0 ++#define NR_IRQS 56 + -+ To compile this driver as a module, choose M here: the module -+ will be called a2065. ++#include_next + -+config HYDRA -+ tristate "Hydra support" -+ depends on ZORRO -+ select CRC32 -+ help -+ If you have a Hydra Ethernet adapter, say Y. Otherwise, say N. ++#endif /* __ASM_MACH_AR71XX_IRQ_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/kernel-entry-init.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,32 @@ ++/* ++ * Atheros AR71xx specific kernel entry setup ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_AR71XX_KERNEL_ENTRY_H ++#define __ASM_MACH_AR71XX_KERNEL_ENTRY_H + -+ To compile this driver as a module, choose M here: the module -+ will be called hydra. ++ /* ++ * Some bootloaders set the 'Kseg0 coherency algorithm' to ++ * 'Cacheable, noncoherent, write-through, no write allocate' ++ * and this cause performance issues. Let's go and change it to ++ * 'Cacheable, noncoherent, write-back, write allocate' ++ */ ++ .macro kernel_entry_setup ++ mfc0 t0, CP0_CONFIG ++ li t1, ~CONF_CM_CMASK ++ and t0, t1 ++ ori t0, CONF_CM_CACHABLE_NONCOHERENT ++ mtc0 t0, CP0_CONFIG ++ nop ++ .endm + -+config ZORRO8390 -+ tristate "Zorro NS8390-based Ethernet support" -+ depends on ZORRO -+ select CRC32 -+ help -+ This driver is for Zorro Ethernet cards using an NS8390-compatible -+ chipset, like the Village Tronic Ariadne II and the Individual -+ Computers X-Surf Ethernet cards. If you have such a card, say Y. -+ Otherwise, say N. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called zorro8390. -+ -+config APNE -+ tristate "PCMCIA NE2000 support" -+ depends on AMIGA_PCMCIA -+ select CRC32 -+ help -+ If you have a PCMCIA NE2000 compatible adapter, say Y. Otherwise, -+ say N. ++ .macro smp_slave_setup ++ .endm + -+ To compile this driver as a module, choose M here: the module -+ will be called apne. ++#endif /* __ASM_MACH_AR71XX_KERNEL_ENTRY_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/mach-rb750.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/mach-rb750.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,66 @@ ++/* ++ * MikroTik RouterBOARD 750 definitions ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ ++#ifndef _MACH_RB750_H ++#define _MACH_RB750_H + -+config MAC8390 -+ bool "Macintosh NS 8390 based ethernet cards" -+ depends on MAC -+ select CRC32 -+ help -+ If you want to include a driver to support Nubus or LC-PDS -+ Ethernet cards using an NS8390 chipset or its equivalent, say Y -+ and read the Ethernet-HOWTO, available from -+ . -+ -+config MAC89x0 -+ tristate "Macintosh CS89x0 based ethernet cards" -+ depends on MAC -+ ---help--- -+ Support for CS89x0 chipset based Ethernet cards. If you have a -+ Nubus or LC-PDS network (Ethernet) card of this type, say Y and -+ read the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. This module will -+ be called mac89x0. -+ -+config MACSONIC -+ tristate "Macintosh SONIC based ethernet (onboard, NuBus, LC, CS)" -+ depends on MAC -+ ---help--- -+ Support for NatSemi SONIC based Ethernet devices. This includes -+ the onboard Ethernet in many Quadras as well as some LC-PDS, -+ a few Nubus and all known Comm Slot Ethernet cards. If you have -+ one of these say Y and read the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. This module will -+ be called macsonic. -+ -+config MACMACE -+ bool "Macintosh (AV) onboard MACE ethernet" -+ depends on MAC -+ select CRC32 -+ help -+ Support for the onboard AMD 79C940 MACE Ethernet controller used in -+ the 660AV and 840AV Macintosh. If you have one of these Macintoshes -+ say Y and read the Ethernet-HOWTO, available from -+ . -+ -+config MVME147_NET -+ tristate "MVME147 (Lance) Ethernet support" -+ depends on MVME147 -+ select CRC32 -+ help -+ Support for the on-board Ethernet interface on the Motorola MVME147 -+ single-board computer. Say Y here to include the -+ driver for this chip in your kernel. -+ To compile this driver as a module, choose M here. -+ -+config MVME16x_NET -+ tristate "MVME16x Ethernet support" -+ depends on MVME16x -+ help -+ This is the driver for the Ethernet interface on the Motorola -+ MVME162, 166, 167, 172 and 177 boards. Say Y here to include the -+ driver for this chip in your kernel. -+ To compile this driver as a module, choose M here. -+ -+config BVME6000_NET -+ tristate "BVME6000 Ethernet support" -+ depends on BVME6000 -+ help -+ This is the driver for the Ethernet interface on BVME4000 and -+ BVME6000 VME boards. Say Y here to include the driver for this chip -+ in your kernel. -+ To compile this driver as a module, choose M here. -+ -+config ATARILANCE -+ tristate "Atari Lance support" -+ depends on ATARI -+ help -+ Say Y to include support for several Atari Ethernet adapters based -+ on the AMD Lance chipset: RieblCard (with or without battery), or -+ PAMCard VME (also the version by Rhotron, with different addresses). ++#include + -+config SUN3LANCE -+ tristate "Sun3/Sun3x on-board LANCE support" -+ depends on SUN3 || SUN3X -+ help -+ Most Sun3 and Sun3x motherboards (including the 3/50, 3/60 and 3/80) -+ featured an AMD Lance 10Mbit Ethernet controller on board; say Y -+ here to compile in the Linux driver for this and enable Ethernet. -+ General Linux information on the Sun 3 and 3x series (now -+ discontinued) is at -+ . -+ -+ If you're not building a kernel for a Sun 3, say N. -+ -+config SUN3_82586 -+ bool "Sun3 on-board Intel 82586 support" -+ depends on SUN3 -+ help -+ This driver enables support for the on-board Intel 82586 based -+ Ethernet adapter found on Sun 3/1xx and 3/2xx motherboards. Note -+ that this driver does not support 82586-based adapters on additional -+ VME boards. -+ -+config HPLANCE -+ bool "HP on-board LANCE support" -+ depends on DIO -+ select CRC32 -+ help -+ If you want to use the builtin "LANCE" Ethernet controller on an -+ HP300 machine, say Y here. ++#define RB750_GPIO_LVC573_LE 0 /* Latch enable on LVC573 */ ++#define RB750_GPIO_NAND_IO0 1 /* NAND I/O 0 */ ++#define RB750_GPIO_NAND_IO1 2 /* NAND I/O 1 */ ++#define RB750_GPIO_NAND_IO2 3 /* NAND I/O 2 */ ++#define RB750_GPIO_NAND_IO3 4 /* NAND I/O 3 */ ++#define RB750_GPIO_NAND_IO4 5 /* NAND I/O 4 */ ++#define RB750_GPIO_NAND_IO5 6 /* NAND I/O 5 */ ++#define RB750_GPIO_NAND_IO6 7 /* NAND I/O 6 */ ++#define RB750_GPIO_NAND_IO7 8 /* NAND I/O 7 */ ++#define RB750_GPIO_NAND_NCE 11 /* NAND Chip Enable (active low) */ ++#define RB750_GPIO_NAND_RDY 12 /* NAND Ready */ ++#define RB750_GPIO_NAND_CLE 14 /* NAND Command Latch Enable */ ++#define RB750_GPIO_NAND_ALE 15 /* NAND Address Latch Enable */ ++#define RB750_GPIO_NAND_NRE 16 /* NAND Read Enable (active low) */ ++#define RB750_GPIO_NAND_NWE 17 /* NAND Write Enable (active low) */ + -+config LASI_82596 -+ tristate "Lasi ethernet" -+ depends on GSC -+ help -+ Say Y here to support the builtin Intel 82596 ethernet controller -+ found in Hewlett-Packard PA-RISC machines with 10Mbit ethernet. ++#define RB750_GPIO_BTN_RESET 1 ++#define RB750_GPIO_SPI_CS0 2 ++#define RB750_GPIO_LED_ACT 12 ++#define RB750_GPIO_LED_PORT1 13 ++#define RB750_GPIO_LED_PORT2 14 ++#define RB750_GPIO_LED_PORT3 15 ++#define RB750_GPIO_LED_PORT4 16 ++#define RB750_GPIO_LED_PORT5 17 + -+config SNI_82596 -+ tristate "SNI RM ethernet" -+ depends on NET_ETHERNET && SNI_RM -+ help -+ Say Y here to support the on-board Intel 82596 ethernet controller -+ built into SNI RM machines. ++#define RB750_LED_ACT BIT(RB750_GPIO_LED_ACT) ++#define RB750_LED_PORT1 BIT(RB750_GPIO_LED_PORT1) ++#define RB750_LED_PORT2 BIT(RB750_GPIO_LED_PORT2) ++#define RB750_LED_PORT3 BIT(RB750_GPIO_LED_PORT3) ++#define RB750_LED_PORT4 BIT(RB750_GPIO_LED_PORT4) ++#define RB750_LED_PORT5 BIT(RB750_GPIO_LED_PORT5) + -+config KORINA -+ tristate "Korina (IDT RC32434) Ethernet support" -+ depends on NET_ETHERNET && MIKROTIK_RB532 -+ help -+ If you have a Mikrotik RouterBoard 500 or IDT RC32434 -+ based system say Y. Otherwise say N. ++#define RB750_LVC573_LE BIT(RB750_GPIO_LVC573_LE) + -+config MIPS_JAZZ_SONIC -+ tristate "MIPS JAZZ onboard SONIC Ethernet support" -+ depends on MACH_JAZZ -+ help -+ This is the driver for the onboard card of MIPS Magnum 4000, -+ Acer PICA, Olivetti M700-10 and a few other identical OEM systems. ++#define RB750_LED_BITS (RB750_LED_PORT1 | RB750_LED_PORT2 | RB750_LED_PORT3 | \ ++ RB750_LED_PORT4 | RB750_LED_PORT5 | RB750_LED_ACT) + -+config XTENSA_XT2000_SONIC -+ tristate "Xtensa XT2000 onboard SONIC Ethernet support" -+ depends on XTENSA_PLATFORM_XT2000 -+ help -+ This is the driver for the onboard card of the Xtensa XT2000 board. ++struct rb750_led_data { ++ char *name; ++ char *default_trigger; ++ u32 mask; ++ int active_low; ++}; + -+config MIPS_AU1X00_ENET -+ tristate "MIPS AU1000 Ethernet support" -+ depends on SOC_AU1X00 -+ select PHYLIB -+ select CRC32 -+ help -+ If you have an Alchemy Semi AU1X00 based system -+ say Y. Otherwise, say N. -+ -+config SGI_IOC3_ETH -+ bool "SGI IOC3 Ethernet" -+ depends on PCI && SGI_IP27 -+ select CRC32 -+ select MII -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . ++struct rb750_led_platform_data { ++ int num_leds; ++ struct rb750_led_data *leds; ++}; + -+config MIPS_SIM_NET -+ tristate "MIPS simulator Network device" -+ depends on MIPS_SIM -+ help -+ The MIPSNET device is a simple Ethernet network device which is -+ emulated by the MIPS Simulator. -+ If you are not using a MIPSsim or are unsure, say N. -+ -+config SGI_O2MACE_ETH -+ tristate "SGI O2 MACE Fast Ethernet support" -+ depends on SGI_IP32=y -+ -+config STNIC -+ tristate "National DP83902AV support" -+ depends on SUPERH -+ select CRC32 -+ help -+ Support for cards based on the National Semiconductor DP83902AV -+ ST-NIC Serial Network Interface Controller for Twisted Pair. This -+ is a 10Mbit/sec Ethernet controller. Product overview and specs at -+ . -+ -+ If unsure, say N. -+ -+config SH_ETH -+ tristate "Renesas SuperH Ethernet support" -+ depends on SUPERH && \ -+ (CPU_SUBTYPE_SH7710 || CPU_SUBTYPE_SH7712 || \ -+ CPU_SUBTYPE_SH7763 || CPU_SUBTYPE_SH7619 || \ -+ CPU_SUBTYPE_SH7724) -+ select CRC32 -+ select MII -+ select MDIO_BITBANG -+ select PHYLIB -+ help -+ Renesas SuperH Ethernet device driver. -+ This driver support SH7710, SH7712, SH7763, SH7619, and SH7724. ++int rb750_latch_change(u32 mask_clr, u32 mask_set); + -+config SUNLANCE -+ tristate "Sun LANCE support" -+ depends on SBUS -+ select CRC32 -+ help -+ This driver supports the "le" interface present on all 32-bit Sparc -+ systems, on some older Ultra systems and as an Sbus option. These -+ cards are based on the AMD Lance chipset, which is better known -+ via the NE2100 cards. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called sunlance. -+ -+config HAPPYMEAL -+ tristate "Sun Happy Meal 10/100baseT support" -+ depends on SBUS || PCI -+ select CRC32 -+ help -+ This driver supports the "hme" interface present on most Ultra -+ systems and as an option on older Sbus systems. This driver supports -+ both PCI and Sbus devices. This driver also supports the "qfe" quad -+ 100baseT device available in both PCI and Sbus configurations. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called sunhme. -+ -+config SUNBMAC -+ tristate "Sun BigMAC 10/100baseT support (EXPERIMENTAL)" -+ depends on SBUS && EXPERIMENTAL -+ select CRC32 -+ help -+ This driver supports the "be" interface available as an Sbus option. -+ This is Sun's older 100baseT Ethernet device. ++#endif /* _MACH_RB750_H */ +\ No newline at end of file +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/mangle-port.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/mangle-port.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/mangle-port.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,45 @@ ++/* ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This file was derived from: inlude/asm-mips/mach-generic/mangle-port.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ To compile this driver as a module, choose M here: the module -+ will be called sunbmac. ++#ifndef __ASM_MACH_AR71XX_MANGLE_PORT_H ++#define __ASM_MACH_AR71XX_MANGLE_PORT_H + -+config SUNQE -+ tristate "Sun QuadEthernet support" -+ depends on SBUS -+ select CRC32 -+ help -+ This driver supports the "qe" 10baseT Ethernet device, available as -+ an Sbus option. Note that this is not the same as Quad FastEthernet -+ "qfe" which is supported by the Happy Meal driver instead. ++#define __swizzle_addr_b(port) ((port) ^ 3) ++#define __swizzle_addr_w(port) ((port) ^ 2) ++#define __swizzle_addr_l(port) (port) ++#define __swizzle_addr_q(port) (port) + -+ To compile this driver as a module, choose M here: the module -+ will be called sunqe. ++#if defined(CONFIG_SWAP_IO_SPACE) + -+config SUNGEM -+ tristate "Sun GEM support" -+ depends on PCI -+ select CRC32 -+ help -+ Support for the Sun GEM chip, aka Sun GigabitEthernet/P 2.0. See also -+ . ++# define ioswabb(a, x) (x) ++# define __mem_ioswabb(a, x) (x) ++# define ioswabw(a, x) le16_to_cpu(x) ++# define __mem_ioswabw(a, x) (x) ++# define ioswabl(a, x) le32_to_cpu(x) ++# define __mem_ioswabl(a, x) (x) ++# define ioswabq(a, x) le64_to_cpu(x) ++# define __mem_ioswabq(a, x) (x) + -+config CASSINI -+ tristate "Sun Cassini support" -+ depends on PCI -+ select CRC32 -+ help -+ Support for the Sun Cassini chip, aka Sun GigaSwift Ethernet. See also -+ ++#else + -+config SUNVNET -+ tristate "Sun Virtual Network support" -+ depends on SUN_LDOMS -+ help -+ Support for virtual network devices under Sun Logical Domains. ++# define ioswabb(a, x) (x) ++# define __mem_ioswabb(a, x) (x) ++# define ioswabw(a, x) (x) ++# define __mem_ioswabw(a, x) cpu_to_le16(x) ++# define ioswabl(a, x) (x) ++# define __mem_ioswabl(a, x) cpu_to_le32(x) ++# define ioswabq(a, x) (x) ++# define __mem_ioswabq(a, x) cpu_to_le64(x) + -+config NET_VENDOR_3COM -+ bool "3COM cards" -+ depends on ISA || EISA || MCA || PCI -+ help -+ If you have a network (Ethernet) card belonging to this class, say Y -+ and read the Ethernet-HOWTO, available from -+ . -+ -+ Note that the answer to this question doesn't directly affect the -+ kernel: saying N will just cause the configurator to skip all -+ the questions about 3COM cards. If you say Y, you will be asked for -+ your specific card in the following questions. -+ -+config EL1 -+ tristate "3c501 \"EtherLink\" support" -+ depends on NET_VENDOR_3COM && ISA -+ ---help--- -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . Also, consider buying a -+ new card, since the 3c501 is slow, broken, and obsolete: you will -+ have problems. Some people suggest to ping ("man ping") a nearby -+ machine every minute ("man cron") when using this card. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called 3c501. -+ -+config EL2 -+ tristate "3c503 \"EtherLink II\" support" -+ depends on NET_VENDOR_3COM && ISA -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called 3c503. -+ -+config ELPLUS -+ tristate "3c505 \"EtherLink Plus\" support" -+ depends on NET_VENDOR_3COM && ISA && ISA_DMA_API -+ ---help--- -+ Information about this network (Ethernet) card can be found in -+ . If you have a card of -+ this type, say Y and read the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called 3c505. -+ -+config EL16 -+ tristate "3c507 \"EtherLink 16\" support (EXPERIMENTAL)" -+ depends on NET_VENDOR_3COM && ISA && EXPERIMENTAL -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called 3c507. -+ -+config EL3 -+ tristate "3c509/3c529 (MCA)/3c579 \"EtherLink III\" support" -+ depends on NET_VENDOR_3COM && (ISA || EISA || MCA) -+ ---help--- -+ If you have a network (Ethernet) card belonging to the 3Com -+ EtherLinkIII series, say Y and read the Ethernet-HOWTO, available -+ from . -+ -+ If your card is not working you may need to use the DOS -+ setup disk to disable Plug & Play mode, and to select the default -+ media type. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called 3c509. -+ -+config 3C515 -+ tristate "3c515 ISA \"Fast EtherLink\"" -+ depends on NET_VENDOR_3COM && (ISA || EISA) && ISA_DMA_API -+ help -+ If you have a 3Com ISA EtherLink XL "Corkscrew" 3c515 Fast Ethernet -+ network card, say Y and read the Ethernet-HOWTO, available from -+ . ++#endif + -+ To compile this driver as a module, choose M here. The module -+ will be called 3c515. ++#endif /* __ASM_MACH_AR71XX_MANGLE_PORT_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/pci.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/pci.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/pci.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/pci.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,39 @@ ++/* ++ * Atheros AR71xx SoC specific PCI definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+config ELMC -+ tristate "3c523 \"EtherLink/MC\" support" -+ depends on NET_VENDOR_3COM && MCA_LEGACY -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . ++#ifndef __ASM_MACH_AR71XX_PCI_H ++#define __ASM_MACH_AR71XX_PCI_H + -+ To compile this driver as a module, choose M here. The module -+ will be called 3c523. ++struct pci_dev; + -+config ELMC_II -+ tristate "3c527 \"EtherLink/MC 32\" support (EXPERIMENTAL)" -+ depends on NET_VENDOR_3COM && MCA && MCA_LEGACY -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called 3c527. -+ -+config VORTEX -+ tristate "3c590/3c900 series (592/595/597) \"Vortex/Boomerang\" support" -+ depends on NET_VENDOR_3COM && (PCI || EISA) -+ select MII -+ ---help--- -+ This option enables driver support for a large number of 10Mbps and -+ 10/100Mbps EISA, PCI and PCMCIA 3Com network cards: -+ -+ "Vortex" (Fast EtherLink 3c590/3c592/3c595/3c597) EISA and PCI -+ "Boomerang" (EtherLink XL 3c900 or 3c905) PCI -+ "Cyclone" (3c540/3c900/3c905/3c980/3c575/3c656) PCI and Cardbus -+ "Tornado" (3c905) PCI -+ "Hurricane" (3c555/3cSOHO) PCI -+ -+ If you have such a card, say Y and read the Ethernet-HOWTO, -+ available from . More -+ specific information is in -+ and in the comments at -+ the beginning of . -+ -+ To compile this support as a module, choose M here. -+ -+config TYPHOON -+ tristate "3cr990 series \"Typhoon\" support" -+ depends on NET_VENDOR_3COM && PCI -+ select CRC32 -+ ---help--- -+ This option enables driver support for the 3cr990 series of cards: -+ -+ 3C990-TX, 3CR990-TX-95, 3CR990-TX-97, 3CR990-FX-95, 3CR990-FX-97, -+ 3CR990SVR, 3CR990SVR95, 3CR990SVR97, 3CR990-FX-95 Server, -+ 3CR990-FX-97 Server, 3C990B-TX-M, 3C990BSVR -+ -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called typhoon. -+ -+config LANCE -+ tristate "AMD LANCE and PCnet (AT1500 and NE2100) support" -+ depends on ISA && ISA_DMA_API -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . Some LinkSys cards are -+ of this type. ++struct ar71xx_pci_irq { ++ int irq; ++ u8 slot; ++ u8 pin; ++}; + -+ To compile this driver as a module, choose M here: the module -+ will be called lance. This is recommended. ++extern int (*ar71xx_pci_plat_dev_init)(struct pci_dev *dev); ++extern unsigned ar71xx_pci_nr_irqs __initdata; ++extern struct ar71xx_pci_irq *ar71xx_pci_irq_map __initdata; + -+config NET_VENDOR_SMC -+ bool "Western Digital/SMC cards" -+ depends on ISA || MCA || EISA || MAC -+ help -+ If you have a network (Ethernet) card belonging to this class, say Y -+ and read the Ethernet-HOWTO, available from -+ . -+ -+ Note that the answer to this question doesn't directly affect the -+ kernel: saying N will just cause the configurator to skip all -+ the questions about Western Digital cards. If you say Y, you will be -+ asked for your specific card in the following questions. -+ -+config WD80x3 -+ tristate "WD80*3 support" -+ depends on NET_VENDOR_SMC && ISA -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . ++int ar71xx_pcibios_map_irq(const struct pci_dev *dev, ++ uint8_t slot, uint8_t pin) __init; ++int ar71xx_pcibios_init(void) __init; + -+ To compile this driver as a module, choose M here. The module -+ will be called wd. ++int ar71xx_pci_be_handler(int is_fixup); + -+config ULTRAMCA -+ tristate "SMC Ultra MCA support" -+ depends on NET_VENDOR_SMC && MCA -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type and are running -+ an MCA based system (PS/2), say Y and read the Ethernet-HOWTO, -+ available from . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called smc-mca. -+ -+config ULTRA -+ tristate "SMC Ultra support" -+ depends on NET_VENDOR_SMC && ISA -+ select CRC32 -+ ---help--- -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ Important: There have been many reports that, with some motherboards -+ mixing an SMC Ultra and an Adaptec AHA154x SCSI card (or compatible, -+ such as some BusLogic models) causes corruption problems with many -+ operating systems. The Linux smc-ultra driver has a work-around for -+ this but keep it in mind if you have such a SCSI card and have -+ problems. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called smc-ultra. -+ -+config ULTRA32 -+ tristate "SMC Ultra32 EISA support" -+ depends on NET_VENDOR_SMC && EISA -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called smc-ultra32. -+ -+config BFIN_MAC -+ tristate "Blackfin on-chip MAC support" -+ depends on NET_ETHERNET && (BF516 || BF518 || BF526 || BF527 || BF536 || BF537) -+ select CRC32 -+ select MII -+ select PHYLIB -+ select BFIN_MAC_USE_L1 if DMA_UNCACHED_NONE -+ help -+ This is the driver for Blackfin on-chip mac device. Say Y if you want it -+ compiled into the kernel. This driver is also available as a module -+ ( = code which can be inserted in and removed from the running kernel -+ whenever you want). The module will be called bfin_mac. -+ -+config BFIN_MAC_USE_L1 -+ bool "Use L1 memory for rx/tx packets" -+ depends on BFIN_MAC && (BF527 || BF537) -+ default y -+ help -+ To get maximum network performance, you should use L1 memory as rx/tx buffers. -+ Say N here if you want to reserve L1 memory for other uses. -+ -+config BFIN_TX_DESC_NUM -+ int "Number of transmit buffer packets" -+ depends on BFIN_MAC -+ range 6 10 if BFIN_MAC_USE_L1 -+ range 10 100 -+ default "10" -+ help -+ Set the number of buffer packets used in driver. -+ -+config BFIN_RX_DESC_NUM -+ int "Number of receive buffer packets" -+ depends on BFIN_MAC -+ range 20 100 if BFIN_MAC_USE_L1 -+ range 20 800 -+ default "20" -+ help -+ Set the number of buffer packets used in driver. ++int ar724x_pcibios_map_irq(const struct pci_dev *dev, ++ uint8_t slot, uint8_t pin) __init; ++int ar724x_pcibios_init(void) __init; + -+config BFIN_MAC_RMII -+ bool "RMII PHY Interface" -+ depends on BFIN_MAC -+ default y if BFIN527_EZKIT -+ default n if BFIN537_STAMP -+ help -+ Use Reduced PHY MII Interface ++int ar71xx_pci_init(unsigned nr_irqs, struct ar71xx_pci_irq *map) __init; + -+config BFIN_MAC_USE_HWSTAMP -+ bool "Use IEEE 1588 hwstamp" -+ depends on BFIN_MAC && BF518 -+ default y -+ help -+ To support the IEEE 1588 Precision Time Protocol (PTP), select y here -+ -+config SMC9194 -+ tristate "SMC 9194 support" -+ depends on NET_VENDOR_SMC && (ISA || MAC && BROKEN) -+ select CRC32 -+ ---help--- -+ This is support for the SMC9xxx based Ethernet cards. Choose this -+ option if you have a DELL laptop with the docking station, or -+ another SMC9192/9194 based chipset. Say Y if you want it compiled -+ into the kernel, and read the file -+ and the Ethernet-HOWTO, -+ available from . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called smc9194. -+ -+config SMC91X -+ tristate "SMC 91C9x/91C1xxx support" -+ select CRC32 -+ select MII -+ depends on ARM || REDWOOD_5 || REDWOOD_6 || M32R || SUPERH || \ -+ MIPS || BLACKFIN || MN10300 || COLDFIRE -+ help -+ This is a driver for SMC's 91x series of Ethernet chipsets, -+ including the SMC91C94 and the SMC91C111. Say Y if you want it -+ compiled into the kernel, and read the file -+ and the Ethernet-HOWTO, -+ available from . -+ -+ This driver is also available as a module ( = code which can be -+ inserted in and removed from the running kernel whenever you want). -+ The module will be called smc91x. If you want to compile it as a -+ module, say M here and read . -+ -+config NET_NETX -+ tristate "NetX Ethernet support" -+ select MII -+ depends on ARCH_NETX -+ help -+ This is support for the Hilscher netX builtin Ethernet ports ++#endif /* __ASM_MACH_AR71XX_PCI_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/platform.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/platform.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/platform.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/platform.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,61 @@ ++/* ++ * Atheros AR71xx SoC specific platform data definitions ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ To compile this driver as a module, choose M here. The module -+ will be called netx-eth. ++#ifndef __ASM_MACH_AR71XX_PLATFORM_H ++#define __ASM_MACH_AR71XX_PLATFORM_H + -+config TI_DAVINCI_EMAC -+ tristate "TI DaVinci EMAC Support" -+ depends on ARM && ( ARCH_DAVINCI || ARCH_OMAP3 ) -+ select PHYLIB -+ help -+ This driver supports TI's DaVinci Ethernet . -+ -+ To compile this driver as a module, choose M here: the module -+ will be called davinci_emac_driver. This is recommended. -+ -+config DM9000 -+ tristate "DM9000 support" -+ depends on ARM || BLACKFIN || MIPS -+ select CRC32 -+ select MII -+ ---help--- -+ Support for DM9000 chipset. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called dm9000. -+ -+config DM9000_DEBUGLEVEL -+ int "DM9000 maximum debug level" -+ depends on DM9000 -+ default 4 -+ help -+ The maximum level of debugging code compiled into the DM9000 -+ driver. -+ -+config DM9000_FORCE_SIMPLE_PHY_POLL -+ bool "Force simple NSR based PHY polling" -+ depends on DM9000 -+ ---help--- -+ This configuration forces the DM9000 to use the NSR's LinkStatus -+ bit to determine if the link is up or down instead of the more -+ costly MII PHY reads. Note, this will not work if the chip is -+ operating with an external PHY. -+ -+config ENC28J60 -+ tristate "ENC28J60 support" -+ depends on EXPERIMENTAL && SPI && NET_ETHERNET -+ select CRC32 -+ ---help--- -+ Support for the Microchip EN28J60 ethernet chip. -+ -+ To compile this driver as a module, choose M here. The module will be -+ called enc28j60. -+ -+config ENC28J60_WRITEVERIFY -+ bool "Enable write verify" -+ depends on ENC28J60 -+ ---help--- -+ Enable the verify after the buffer write useful for debugging purpose. -+ If unsure, say N. -+ -+config ETHOC -+ tristate "OpenCores 10/100 Mbps Ethernet MAC support" -+ depends on NET_ETHERNET && HAS_IOMEM && HAS_DMA -+ select MII -+ select PHYLIB -+ select CRC32 -+ select BITREVERSE -+ help -+ Say Y here if you want to use the OpenCores 10/100 Mbps Ethernet MAC. ++#include ++#include ++#include ++#include + -+config GRETH -+ tristate "Aeroflex Gaisler GRETH Ethernet MAC support" -+ depends on SPARC -+ select PHYLIB -+ select CRC32 -+ help -+ Say Y here if you want to use the Aeroflex Gaisler GRETH Ethernet MAC. ++struct ag71xx_platform_data { ++ phy_interface_t phy_if_mode; ++ u32 phy_mask; ++ int speed; ++ int duplex; ++ u32 reset_bit; ++ u32 mii_if; ++ u8 mac_addr[ETH_ALEN]; ++ struct device *mii_bus_dev; + -+config SMC911X -+ tristate "SMSC LAN911[5678] support" -+ select CRC32 -+ select MII -+ depends on ARM || SUPERH -+ help -+ This is a driver for SMSC's LAN911x series of Ethernet chipsets -+ including the new LAN9115, LAN9116, LAN9117, and LAN9118. -+ Say Y if you want it compiled into the kernel, -+ and read the Ethernet-HOWTO, available from -+ . -+ -+ This driver is also available as a module. The module will be -+ called smc911x. If you want to compile it as a module, say M -+ here and read -+ -+config SMSC911X -+ tristate "SMSC LAN911x/LAN921x families embedded ethernet support" -+ depends on ARM || SUPERH || BLACKFIN || MIPS -+ select CRC32 -+ select MII -+ select PHYLIB -+ ---help--- -+ Say Y here if you want support for SMSC LAN911x and LAN921x families -+ of ethernet controllers. ++ u8 has_gbit:1; ++ u8 is_ar91xx:1; ++ u8 is_ar724x:1; ++ u8 has_ar8216:1; + -+ To compile this driver as a module, choose M here and read -+ . The module -+ will be called smsc911x. ++ void (* ddr_flush)(void); ++ void (* set_pll)(int speed); + -+config NET_VENDOR_RACAL -+ bool "Racal-Interlan (Micom) NI cards" -+ depends on ISA -+ help -+ If you have a network (Ethernet) card belonging to this class, such -+ as the NI5010, NI5210 or NI6210, say Y and read the Ethernet-HOWTO, -+ available from . -+ -+ Note that the answer to this question doesn't directly affect the -+ kernel: saying N will just cause the configurator to skip all -+ the questions about NI cards. If you say Y, you will be asked for -+ your specific card in the following questions. -+ -+config NI5010 -+ tristate "NI5010 support (EXPERIMENTAL)" -+ depends on NET_VENDOR_RACAL && ISA && EXPERIMENTAL && BROKEN_ON_SMP -+ ---help--- -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . Note that this is still -+ experimental code. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ni5010. -+ -+config NI52 -+ tristate "NI5210 support" -+ depends on NET_VENDOR_RACAL && ISA -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . ++ u32 fifo_cfg1; ++ u32 fifo_cfg2; ++ u32 fifo_cfg3; ++}; + -+ To compile this driver as a module, choose M here. The module -+ will be called ni52. ++struct ag71xx_mdio_platform_data { ++ u32 phy_mask; ++ int is_ar7240; ++}; + -+config NI65 -+ tristate "NI6510 support" -+ depends on NET_VENDOR_RACAL && ISA && ISA_DMA_API -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . ++struct ar71xx_ehci_platform_data { ++ u8 is_ar91xx; ++}; + -+ To compile this driver as a module, choose M here. The module -+ will be called ni65. ++struct ar71xx_spi_platform_data { ++ unsigned bus_num; ++ unsigned num_chipselect; ++ u32 (*get_ioc_base)(u8 chip_select, int cs_high, int is_on); ++}; + -+config DNET -+ tristate "Dave ethernet support (DNET)" -+ depends on NET_ETHERNET && HAS_IOMEM -+ select PHYLIB -+ help -+ The Dave ethernet interface (DNET) is found on Qong Board FPGA. -+ Say Y to include support for the DNET chip. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called dnet. -+ -+source "drivers/net/tulip/Kconfig" -+ -+config AT1700 -+ tristate "AT1700/1720 support (EXPERIMENTAL)" -+ depends on (ISA || MCA_LEGACY) && EXPERIMENTAL -+ select CRC32 -+ ---help--- -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called at1700. -+ -+config DEPCA -+ tristate "DEPCA, DE10x, DE200, DE201, DE202, DE422 support" -+ depends on ISA || EISA || MCA -+ select CRC32 -+ ---help--- -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ as well as -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called depca. -+ -+config HP100 -+ tristate "HP 10/100VG PCLAN (ISA, EISA, PCI) support" -+ depends on ISA || EISA || PCI -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called hp100. -+ -+config NET_ISA -+ bool "Other ISA cards" -+ depends on ISA -+ ---help--- -+ If your network (Ethernet) card hasn't been mentioned yet and its -+ bus system (that's the way the cards talks to the other components -+ of your computer) is ISA (as opposed to EISA, VLB or PCI), say Y. -+ Make sure you know the name of your card. Read the Ethernet-HOWTO, -+ available from . -+ -+ If unsure, say Y. -+ -+ Note that the answer to this question doesn't directly affect the -+ kernel: saying N will just cause the configurator to skip all -+ the remaining ISA network card questions. If you say Y, you will be -+ asked for your specific card in the following questions. -+ -+config E2100 -+ tristate "Cabletron E21xx support" -+ depends on NET_ISA -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called e2100. -+ -+config EWRK3 -+ tristate "EtherWORKS 3 (DE203, DE204, DE205) support" -+ depends on NET_ISA -+ select CRC32 -+ ---help--- -+ This driver supports the DE203, DE204 and DE205 network (Ethernet) -+ cards. If this is for you, say Y and read -+ in the kernel source as -+ well as the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ewrk3. -+ -+config EEXPRESS -+ tristate "EtherExpress 16 support" -+ depends on NET_ISA -+ ---help--- -+ If you have an EtherExpress16 network (Ethernet) card, say Y and -+ read the Ethernet-HOWTO, available from -+ . Note that the Intel -+ EtherExpress16 card used to be regarded as a very poor choice -+ because the driver was very unreliable. We now have a new driver -+ that should do better. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called eexpress. -+ -+config EEXPRESS_PRO -+ tristate "EtherExpressPro support/EtherExpress 10 (i82595) support" -+ depends on NET_ISA -+ ---help--- -+ If you have a network (Ethernet) card of this type, say Y. This -+ driver supports Intel i82595{FX,TX} based boards. Note however -+ that the EtherExpress PRO/100 Ethernet card has its own separate -+ driver. Please read the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called eepro. -+ -+config HPLAN_PLUS -+ tristate "HP PCLAN+ (27247B and 27252A) support" -+ depends on NET_ISA -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . ++#define AR71XX_SPI_CS_INACTIVE 0 ++#define AR71XX_SPI_CS_ACTIVE 1 + -+ To compile this driver as a module, choose M here. The module -+ will be called hp-plus. ++#endif /* __ASM_MACH_AR71XX_PLATFORM_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/war.h linux-2.6.36/arch/mips/include/asm/mach-ar71xx/war.h +--- linux-2.6.36.orig/arch/mips/include/asm/mach-ar71xx/war.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mach-ar71xx/war.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,25 @@ ++/* ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file "COPYING" in the main directory of this archive ++ * for more details. ++ * ++ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle ++ */ ++#ifndef __ASM_MACH_AR71XX_WAR_H ++#define __ASM_MACH_AR71XX_WAR_H + -+config HPLAN -+ tristate "HP PCLAN (27245 and other 27xxx series) support" -+ depends on NET_ISA -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . ++#define R4600_V1_INDEX_ICACHEOP_WAR 0 ++#define R4600_V1_HIT_CACHEOP_WAR 0 ++#define R4600_V2_HIT_CACHEOP_WAR 0 ++#define R5432_CP0_INTERRUPT_WAR 0 ++#define BCM1250_M3_WAR 0 ++#define SIBYTE_1956_WAR 0 ++#define MIPS4K_ICACHE_REFILL_WAR 0 ++#define MIPS_CACHE_SYNC_WAR 0 ++#define TX49XX_ICACHE_INDEX_INV_WAR 0 ++#define RM9000_CDEX_SMP_WAR 0 ++#define ICACHE_REFILLS_WORKAROUND_WAR 0 ++#define R10000_LLSC_WAR 0 ++#define MIPS34K_MISSED_ITLB_WAR 0 + -+ To compile this driver as a module, choose M here. The module -+ will be called hp. ++#endif /* __ASM_MACH_AR71XX_WAR_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/mips_machine.h linux-2.6.36/arch/mips/include/asm/mips_machine.h +--- linux-2.6.36.orig/arch/mips/include/asm/mips_machine.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/include/asm/mips_machine.h 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ + -+config LP486E -+ tristate "LP486E on board Ethernet" -+ depends on NET_ISA -+ help -+ Say Y here to support the 82596-based on-board Ethernet controller -+ for the Panther motherboard, which is one of the two shipped in the -+ Intel Professional Workstation. ++#ifndef __ASM_MIPS_MACHINE_H ++#define __ASM_MIPS_MACHINE_H + -+config ETH16I -+ tristate "ICL EtherTeam 16i/32 support" -+ depends on NET_ISA -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called eth16i. -+ -+config NE2000 -+ tristate "NE2000/NE1000 support" -+ depends on NET_ISA || (Q40 && m) || M32R || MACH_TX49XX -+ select CRC32 -+ ---help--- -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . Many Ethernet cards -+ without a specific driver are compatible with NE2000. -+ -+ If you have a PCI NE2000 card however, say N here and Y to "PCI -+ NE2000 and clone support" under "EISA, VLB, PCI and on board -+ controllers" below. If you have a NE2000 card and are running on -+ an MCA system (a bus system used on some IBM PS/2 computers and -+ laptops), say N here and Y to "NE/2 (ne2000 MCA version) support", -+ below. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ne. -+ -+config ZNET -+ tristate "Zenith Z-Note support (EXPERIMENTAL)" -+ depends on NET_ISA && EXPERIMENTAL && ISA_DMA_API -+ help -+ The Zenith Z-Note notebook computer has a built-in network -+ (Ethernet) card, and this is the Linux driver for it. Note that the -+ IBM Thinkpad 300 is compatible with the Z-Note and is also supported -+ by this driver. Read the Ethernet-HOWTO, available from -+ . -+ -+config SEEQ8005 -+ tristate "SEEQ8005 support (EXPERIMENTAL)" -+ depends on NET_ISA && EXPERIMENTAL -+ help -+ This is a driver for the SEEQ 8005 network (Ethernet) card. If this -+ is for you, read the Ethernet-HOWTO, available from -+ . ++#include ++#include + -+ To compile this driver as a module, choose M here. The module -+ will be called seeq8005. ++#include + -+config NE2_MCA -+ tristate "NE/2 (ne2000 MCA version) support" -+ depends on MCA_LEGACY -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ne2. -+ -+config IBMLANA -+ tristate "IBM LAN Adapter/A support" -+ depends on MCA -+ ---help--- -+ This is a Micro Channel Ethernet adapter. You need to set -+ CONFIG_MCA to use this driver. It is both available as an in-kernel -+ driver and as a module. -+ -+ To compile this driver as a module, choose M here. The only -+ currently supported card is the IBM LAN Adapter/A for Ethernet. It -+ will both support 16K and 32K memory windows, however a 32K window -+ gives a better security against packet losses. Usage of multiple -+ boards with this driver should be possible, but has not been tested -+ up to now due to lack of hardware. -+ -+config IBMVETH -+ tristate "IBM LAN Virtual Ethernet support" -+ depends on PPC_PSERIES -+ ---help--- -+ This driver supports virtual ethernet adapters on newer IBM iSeries -+ and pSeries systems. -+ -+ To compile this driver as a module, choose M here. The module will -+ be called ibmveth. -+ -+source "drivers/net/ibm_newemac/Kconfig" -+ -+config NET_PCI -+ bool "EISA, VLB, PCI and on board controllers" -+ depends on ISA || EISA || PCI -+ help -+ This is another class of network cards which attach directly to the -+ bus. If you have one of those, say Y and read the Ethernet-HOWTO, -+ available from . -+ -+ Note that the answer to this question doesn't directly affect the -+ kernel: saying N will just cause the configurator to skip all -+ the questions about this class of network cards. If you say Y, you -+ will be asked for your specific card in the following questions. If -+ you are unsure, say Y. -+ -+config PCNET32 -+ tristate "AMD PCnet32 PCI support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ help -+ If you have a PCnet32 or PCnetPCI based network (Ethernet) card, -+ answer Y here and read the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called pcnet32. -+ -+config AMD8111_ETH -+ tristate "AMD 8111 (new PCI lance) support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ help -+ If you have an AMD 8111-based PCI lance ethernet card, -+ answer Y here and read the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called amd8111e. -+ -+config ADAPTEC_STARFIRE -+ tristate "Adaptec Starfire/DuraLAN support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ help -+ Say Y here if you have an Adaptec Starfire (or DuraLAN) PCI network -+ adapter. The DuraLAN chip is used on the 64 bit PCI boards from -+ Adaptec e.g. the ANA-6922A. The older 32 bit boards use the tulip -+ driver. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called starfire. This is recommended. -+ -+config AC3200 -+ tristate "Ansel Communications EISA 3200 support (EXPERIMENTAL)" -+ depends on NET_PCI && (ISA || EISA) && EXPERIMENTAL -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ac3200. -+ -+config KSZ884X_PCI -+ tristate "Micrel KSZ8841/2 PCI" -+ depends on NET_PCI && PCI -+ select MII -+ select CRC32 -+ help -+ This PCI driver is for Micrel KSZ8841/KSZ8842 PCI Ethernet chip. ++struct mips_machine { ++ unsigned long mach_type; ++ char *mach_id; ++ char *mach_name; ++ void (*mach_setup)(void); ++ struct list_head list; ++}; + -+ To compile this driver as a module, choose M here. The module -+ will be called ksz884x. ++void mips_machine_register(struct mips_machine *) __init; ++void mips_machine_setup(void) __init; ++int mips_machtype_setup(char *id) __init; ++void mips_machine_set_name(char *name) __init; + -+config APRICOT -+ tristate "Apricot Xen-II on board Ethernet" -+ depends on NET_PCI && ISA -+ help -+ If you have a network (Ethernet) controller of this type, say Y and -+ read the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called apricot. -+ -+config B44 -+ tristate "Broadcom 440x/47xx ethernet support" -+ depends on SSB_POSSIBLE && HAS_DMA -+ select SSB -+ select MII -+ help -+ If you have a network (Ethernet) controller of this type, say Y -+ or M and read the Ethernet-HOWTO, available from -+ . ++extern char *mips_machine_name; + -+ To compile this driver as a module, choose M here. The module -+ will be called b44. ++#define MIPS_MACHINE(_type, _id, _name, _setup) \ ++static const char machine_name_##_type[] __initconst \ ++ __aligned(1) = _name; \ ++static const char machine_id_##_type[] __initconst \ ++ __aligned(1) = _id; \ ++static struct mips_machine machine_##_type __initdata = \ ++{ \ ++ .mach_type = _type, \ ++ .mach_id = (char *) machine_id_##_type, \ ++ .mach_name = (char *) machine_name_##_type, \ ++ .mach_setup = _setup, \ ++}; \ ++ \ ++static int __init register_machine_##_type(void) \ ++{ \ ++ mips_machine_register(&machine_##_type); \ ++ return 0; \ ++} \ ++ \ ++pure_initcall(register_machine_##_type) + -+# Auto-select SSB PCI-HOST support, if possible -+config B44_PCI_AUTOSELECT -+ bool -+ depends on B44 && SSB_PCIHOST_POSSIBLE -+ select SSB_PCIHOST -+ default y ++#endif /* __ASM_MIPS_MACHINE_H */ +diff -Nur linux-2.6.36.orig/arch/mips/include/asm/time.h linux-2.6.36/arch/mips/include/asm/time.h +--- linux-2.6.36.orig/arch/mips/include/asm/time.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/include/asm/time.h 2010-11-18 21:16:05.000000000 +0100 +@@ -52,6 +52,7 @@ + */ + #ifdef CONFIG_CEVT_R4K_LIB + extern unsigned int __weak get_c0_compare_int(void); ++extern unsigned int __weak get_c0_compare_irq(void); + extern int r4k_clockevent_init(void); + #endif + +diff -Nur linux-2.6.36.orig/arch/mips/kernel/Makefile linux-2.6.36/arch/mips/kernel/Makefile +--- linux-2.6.36.orig/arch/mips/kernel/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/kernel/Makefile 2010-11-18 21:16:05.000000000 +0100 +@@ -94,6 +94,7 @@ + + obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o ++obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o + obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o + + CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) +diff -Nur linux-2.6.36.orig/arch/mips/kernel/mips_machine.c linux-2.6.36/arch/mips/kernel/mips_machine.c +--- linux-2.6.36.orig/arch/mips/kernel/mips_machine.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/kernel/mips_machine.c 2010-11-18 21:16:05.000000000 +0100 +@@ -0,0 +1,121 @@ ++/* ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include + -+# Auto-select SSB PCICORE driver, if possible -+config B44_PCICORE_AUTOSELECT -+ bool -+ depends on B44 && SSB_DRIVER_PCICORE_POSSIBLE -+ select SSB_DRIVER_PCICORE -+ default y ++#include + -+config B44_PCI -+ bool -+ depends on B44_PCI_AUTOSELECT && B44_PCICORE_AUTOSELECT -+ default y ++static struct list_head mips_machines __initdata = ++ LIST_HEAD_INIT(mips_machines); ++static char *mips_machid __initdata; + -+config FORCEDETH -+ tristate "nForce Ethernet support" -+ depends on NET_PCI && PCI -+ help -+ If you have a network (Ethernet) controller of this type, say Y and -+ read the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called forcedeth. -+ -+config CS89x0 -+ tristate "CS89x0 support" -+ depends on NET_ETHERNET && (ISA || EISA || MACH_IXDP2351 \ -+ || ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS) -+ ---help--- -+ Support for CS89x0 chipset based Ethernet cards. If you have a -+ network (Ethernet) card of this type, say Y and read the -+ Ethernet-HOWTO, available from -+ as well as -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called cs89x0. -+ -+config CS89x0_NONISA_IRQ -+ def_bool y -+ depends on CS89x0 != n -+ depends on MACH_IXDP2351 || ARCH_IXDP2X01 || ARCH_PNX010X || MACH_MX31ADS -+ -+config TC35815 -+ tristate "TOSHIBA TC35815 Ethernet support" -+ depends on NET_PCI && PCI && MIPS -+ select PHYLIB ++char *mips_machine_name = "Unknown"; + -+config E100 -+ tristate "Intel(R) PRO/100+ support" -+ depends on NET_PCI && PCI -+ select MII -+ ---help--- -+ This driver supports Intel(R) PRO/100 family of adapters. -+ To verify that your adapter is supported, find the board ID number -+ on the adapter. Look for a label that has a barcode and a number -+ in the format 123456-001 (six digits hyphen three digits). ++static struct mips_machine * __init mips_machine_find(unsigned long machtype) ++{ ++ struct list_head *this; + -+ Use the above information and the Adapter & Driver ID Guide at: ++ list_for_each(this, &mips_machines) { ++ struct mips_machine *mach; + -+ ++ mach = list_entry(this, struct mips_machine, list); ++ if (mach->mach_type == machtype) ++ return mach; ++ } + -+ to identify the adapter. ++ return NULL; ++} + -+ For the latest Intel PRO/100 network driver for Linux, see: ++void __init mips_machine_register(struct mips_machine *mach) ++{ ++ list_add_tail(&mach->list, &mips_machines); ++} + -+ ++void __init mips_machine_set_name(char *name) ++{ ++ unsigned int len; ++ char *p; + -+ More specific information on configuring the driver is in -+ . ++ if (name == NULL) ++ return; + -+ To compile this driver as a module, choose M here. The module -+ will be called e100. ++ len = strlen(name); ++ p = kmalloc(len + 1, GFP_KERNEL); ++ if (p) { ++ strncpy(p, name, len); ++ p[len] = '\0'; ++ mips_machine_name = p; ++ } else { ++ printk(KERN_WARNING "MIPS: no memory for machine_name\n"); ++ } ++} + -+config LNE390 -+ tristate "Mylex EISA LNE390A/B support (EXPERIMENTAL)" -+ depends on NET_PCI && EISA && EXPERIMENTAL -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called lne390. -+ -+config FEALNX -+ tristate "Myson MTD-8xx PCI Ethernet support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ help -+ Say Y here to support the Mysom MTD-800 family of PCI-based Ethernet -+ cards. Specifications and data at -+ . -+ -+config NATSEMI -+ tristate "National Semiconductor DP8381x series PCI Ethernet support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ help -+ This driver is for the National Semiconductor DP83810 series, -+ which is used in cards from PureData, NetGear, Linksys -+ and others, including the 83815 chip. -+ More specific information and updates are available from -+ . -+ -+config NE2K_PCI -+ tristate "PCI NE2000 and clones support (see help)" -+ depends on NET_PCI && PCI -+ select CRC32 -+ ---help--- -+ This driver is for NE2000 compatible PCI cards. It will not work -+ with ISA NE2000 cards (they have their own driver, "NE2000/NE1000 -+ support" below). If you have a PCI NE2000 network (Ethernet) card, -+ say Y and read the Ethernet-HOWTO, available from -+ . -+ -+ This driver also works for the following NE2000 clone cards: -+ RealTek RTL-8029 Winbond 89C940 Compex RL2000 KTI ET32P2 -+ NetVin NV5000SC Via 86C926 SureCom NE34 Winbond -+ Holtek HT80232 Holtek HT80229 -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ne2k-pci. -+ -+config NE3210 -+ tristate "Novell/Eagle/Microdyne NE3210 EISA support (EXPERIMENTAL)" -+ depends on NET_PCI && EISA && EXPERIMENTAL -+ select CRC32 -+ ---help--- -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . Note that this driver -+ will NOT WORK for NE3200 cards as they are completely different. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ne3210. -+ -+config ES3210 -+ tristate "Racal-Interlan EISA ES3210 support (EXPERIMENTAL)" -+ depends on NET_PCI && EISA && EXPERIMENTAL -+ select CRC32 -+ help -+ If you have a network (Ethernet) card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called es3210. -+ -+config 8139CP -+ tristate "RealTek RTL-8139 C+ PCI Fast Ethernet Adapter support (EXPERIMENTAL)" -+ depends on NET_PCI && PCI && EXPERIMENTAL -+ select CRC32 -+ select MII -+ help -+ This is a driver for the Fast Ethernet PCI network cards based on -+ the RTL8139C+ chips. If you have one of those, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here: the module -+ will be called 8139cp. This is recommended. -+ -+config 8139TOO -+ tristate "RealTek RTL-8129/8130/8139 PCI Fast Ethernet Adapter support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ ---help--- -+ This is a driver for the Fast Ethernet PCI network cards based on -+ the RTL 8129/8130/8139 chips. If you have one of those, say Y and -+ read the Ethernet-HOWTO . -+ -+ To compile this driver as a module, choose M here: the module -+ will be called 8139too. This is recommended. -+ -+config 8139TOO_PIO -+ bool "Use PIO instead of MMIO" -+ default y -+ depends on 8139TOO -+ help -+ This instructs the driver to use programmed I/O ports (PIO) instead -+ of PCI shared memory (MMIO). This can possibly solve some problems -+ in case your mainboard has memory consistency issues. If unsure, -+ say N. -+ -+config 8139TOO_TUNE_TWISTER -+ bool "Support for uncommon RTL-8139 rev. K (automatic channel equalization)" -+ depends on 8139TOO -+ help -+ This implements a function which might come in handy in case you -+ are using low quality on long cabling. It is required for RealTek -+ RTL-8139 revision K boards, and totally unused otherwise. It tries -+ to match the transceiver to the cable characteristics. This is -+ experimental since hardly documented by the manufacturer. -+ If unsure, say Y. -+ -+config 8139TOO_8129 -+ bool "Support for older RTL-8129/8130 boards" -+ depends on 8139TOO -+ help -+ This enables support for the older and uncommon RTL-8129 and -+ RTL-8130 chips, which support MII via an external transceiver, -+ instead of an internal one. Disabling this option will save some -+ memory by making the code size smaller. If unsure, say Y. -+ -+config 8139_OLD_RX_RESET -+ bool "Use older RX-reset method" -+ depends on 8139TOO -+ help -+ The 8139too driver was recently updated to contain a more rapid -+ reset sequence, in the face of severe receive errors. This "new" -+ RX-reset method should be adequate for all boards. But if you -+ experience problems, you can enable this option to restore the -+ old RX-reset behavior. If unsure, say N. -+ -+config R6040 -+ tristate "RDC R6040 Fast Ethernet Adapter support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ help -+ This is a driver for the R6040 Fast Ethernet MACs found in the -+ the RDC R-321x System-on-chips. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called r6040. This is recommended. -+ -+config SIS900 -+ tristate "SiS 900/7016 PCI Fast Ethernet Adapter support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ ---help--- -+ This is a driver for the Fast Ethernet PCI network cards based on -+ the SiS 900 and SiS 7016 chips. The SiS 900 core is also embedded in -+ SiS 630 and SiS 540 chipsets. -+ -+ This driver also supports AMD 79C901 HomePNA so that you can use -+ your phone line as a network cable. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called sis900. This is recommended. -+ -+config EPIC100 -+ tristate "SMC EtherPower II" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ help -+ This driver is for the SMC EtherPower II 9432 PCI Ethernet NIC, -+ which is based on the SMC83c17x (EPIC/100). -+ More specific information and updates are available from -+ . -+ -+config SMSC9420 -+ tristate "SMSC LAN9420 PCI ethernet adapter support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select PHYLIB -+ select SMSC_PHY -+ help -+ This is a driver for SMSC's LAN9420 PCI ethernet adapter. -+ Say Y if you want it compiled into the kernel, -+ and read the Ethernet-HOWTO, available from -+ . -+ -+ This driver is also available as a module. The module will be -+ called smsc9420. If you want to compile it as a module, say M -+ here and read -+ -+config SUNDANCE -+ tristate "Sundance Alta support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ help -+ This driver is for the Sundance "Alta" chip. -+ More specific information and updates are available from -+ . ++void __init mips_machine_setup(void) ++{ ++ struct mips_machine *mach; + -+config SUNDANCE_MMIO -+ bool "Use MMIO instead of PIO" -+ depends on SUNDANCE -+ help -+ Enable memory-mapped I/O for interaction with Sundance NIC registers. -+ Do NOT enable this by default, PIO (enabled when MMIO is disabled) -+ is known to solve bugs on certain chips. ++ mach = mips_machine_find(mips_machtype); ++ if (!mach) { ++ printk(KERN_WARNING "MIPS: no machine registered for " ++ "machtype %lu\n", mips_machtype); ++ return; ++ } + -+ If unsure, say N. ++ mips_machine_set_name(mach->mach_name); ++ printk(KERN_NOTICE "MIPS: machine is %s\n", mips_machine_name); + -+config TLAN -+ tristate "TI ThunderLAN support" -+ depends on NET_PCI && (PCI || EISA) -+ ---help--- -+ If you have a PCI Ethernet network card based on the ThunderLAN chip -+ which is supported by this driver, say Y and read the -+ Ethernet-HOWTO, available from -+ . ++ if (mach->mach_setup) ++ mach->mach_setup(); ++} + -+ Devices currently supported by this driver are Compaq Netelligent, -+ Compaq NetFlex and Olicom cards. Please read the file -+ for more details. ++int __init mips_machtype_setup(char *id) ++{ ++ if (mips_machid == NULL) ++ mips_machid = id; + -+ To compile this driver as a module, choose M here. The module -+ will be called tlan. ++ return 1; ++} + -+ Please email feedback to . ++__setup("machtype=", mips_machtype_setup); + -+config KS8842 -+ tristate "Micrel KSZ8842" -+ depends on HAS_IOMEM -+ help -+ This platform driver is for Micrel KSZ8842 / KS8842 -+ 2-port ethernet switch chip (managed, VLAN, QoS). -+ -+config KS8851 -+ tristate "Micrel KS8851 SPI" -+ depends on SPI -+ select MII -+ select CRC32 -+ help -+ SPI driver for Micrel KS8851 SPI attached network chip. -+ -+config KS8851_MLL -+ tristate "Micrel KS8851 MLL" -+ depends on HAS_IOMEM -+ select MII -+ help -+ This platform driver is for Micrel KS8851 Address/data bus -+ multiplexed network chip. -+ -+config VIA_RHINE -+ tristate "VIA Rhine support" -+ depends on NET_PCI && PCI -+ select CRC32 -+ select MII -+ help -+ If you have a VIA "Rhine" based network card (Rhine-I (VT86C100A), -+ Rhine-II (VT6102), or Rhine-III (VT6105)), say Y here. Rhine-type -+ Ethernet functions can also be found integrated on South Bridges -+ (e.g. VT8235). ++static int __init mips_machtype_init(void) ++{ ++ struct list_head *this; ++ struct mips_machine *mach; + -+ To compile this driver as a module, choose M here. The module -+ will be called via-rhine. ++ if (mips_machid == NULL) ++ return 0; + -+config VIA_RHINE_MMIO -+ bool "Use MMIO instead of PIO" -+ depends on VIA_RHINE -+ help -+ This instructs the driver to use PCI shared memory (MMIO) instead of -+ programmed I/O ports (PIO). Enabling this gives an improvement in -+ processing time in parts of the driver. -+ -+ If unsure, say Y. -+ -+config SC92031 -+ tristate "Silan SC92031 PCI Fast Ethernet Adapter driver (EXPERIMENTAL)" -+ depends on NET_PCI && PCI && EXPERIMENTAL -+ select CRC32 -+ ---help--- -+ This is a driver for the Fast Ethernet PCI network cards based on -+ the Silan SC92031 chip (sometimes also called Rsltek 8139D). If you -+ have one of these, say Y here. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called sc92031. This is recommended. -+ -+config CPMAC -+ tristate "TI AR7 CPMAC Ethernet support (EXPERIMENTAL)" -+ depends on NET_ETHERNET && EXPERIMENTAL && AR7 -+ select PHYLIB -+ help -+ TI AR7 CPMAC Ethernet support -+ -+config NET_POCKET -+ bool "Pocket and portable adapters" -+ depends on PARPORT -+ ---help--- -+ Cute little network (Ethernet) devices which attach to the parallel -+ port ("pocket adapters"), commonly used with laptops. If you have -+ one of those, say Y and read the Ethernet-HOWTO, available from -+ . -+ -+ If you want to plug a network (or some other) card into the PCMCIA -+ (or PC-card) slot of your laptop instead (PCMCIA is the standard for -+ credit card size extension cards used by all modern laptops), you -+ need the pcmcia-cs package (location contained in the file -+ ) and you can say N here. -+ -+ Laptop users should read the Linux Laptop home page at -+ or -+ Tuxmobil - Linux on Mobile Computers at . -+ -+ Note that the answer to this question doesn't directly affect the -+ kernel: saying N will just cause the configurator to skip all -+ the questions about this class of network devices. If you say Y, you -+ will be asked for your specific device in the following questions. -+ -+config ATP -+ tristate "AT-LAN-TEC/RealTek pocket adapter support" -+ depends on NET_POCKET && PARPORT && X86 -+ select CRC32 -+ ---help--- -+ This is a network (Ethernet) device which attaches to your parallel -+ port. Read as well as the Ethernet-HOWTO, -+ available from , if you -+ want to use this. If you intend to use this driver, you should have -+ said N to the "Parallel printer support", because the two drivers -+ don't like each other. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called atp. -+ -+config DE600 -+ tristate "D-Link DE600 pocket adapter support" -+ depends on NET_POCKET && PARPORT -+ ---help--- -+ This is a network (Ethernet) device which attaches to your parallel -+ port. Read as well as the -+ Ethernet-HOWTO, available from -+ , if you want to use -+ this. It is possible to have several devices share a single parallel -+ port and it is safe to compile the corresponding drivers into the -+ kernel. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called de600. -+ -+config DE620 -+ tristate "D-Link DE620 pocket adapter support" -+ depends on NET_POCKET && PARPORT -+ ---help--- -+ This is a network (Ethernet) device which attaches to your parallel -+ port. Read as well as the -+ Ethernet-HOWTO, available from -+ , if you want to use -+ this. It is possible to have several devices share a single parallel -+ port and it is safe to compile the corresponding drivers into the -+ kernel. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called de620. -+ -+config SGISEEQ -+ tristate "SGI Seeq ethernet controller support" -+ depends on SGI_HAS_SEEQ -+ help -+ Say Y here if you have an Seeq based Ethernet network card. This is -+ used in many Silicon Graphics machines. ++ list_for_each(this, &mips_machines) { ++ mach = list_entry(this, struct mips_machine, list); ++ if (mach->mach_id == NULL) ++ continue; + -+config DECLANCE -+ tristate "DEC LANCE ethernet controller support" -+ depends on MACH_DECSTATION -+ select CRC32 -+ help -+ This driver is for the series of Ethernet controllers produced by -+ DEC (now Compaq) based on the AMD Lance chipset, including the -+ DEPCA series. (This chipset is better known via the NE2100 cards.) ++ if (strcmp(mach->mach_id, mips_machid) == 0) { ++ mips_machtype = mach->mach_type; ++ return 0; ++ } ++ } + -+config 68360_ENET -+ bool "Motorola 68360 ethernet controller" -+ depends on M68360 -+ help -+ Say Y here if you want to use the built-in ethernet controller of -+ the Motorola 68360 processor. ++ printk(KERN_WARNING ++ "MIPS: no machine found for id: '%s', registered machines:\n", ++ mips_machid); ++ printk(KERN_WARNING "%32s %s\n", "id", "name"); + -+config FEC -+ bool "FEC ethernet controller (of ColdFire and some i.MX CPUs)" -+ depends on M523x || M527x || M5272 || M528x || M520x || M532x || \ -+ MACH_MX27 || ARCH_MX35 || ARCH_MX25 || ARCH_MX5 -+ select PHYLIB -+ help -+ Say Y here if you want to use the built-in 10/100 Fast ethernet -+ controller on some Motorola ColdFire and Freescale i.MX processors. ++ list_for_each(this, &mips_machines) { ++ mach = list_entry(this, struct mips_machine, list); ++ printk(KERN_WARNING "%32s %s\n", ++ mach->mach_id ? mach->mach_id : "", mach->mach_name); ++ } + -+config FEC2 -+ bool "Second FEC ethernet controller (on some ColdFire CPUs)" -+ depends on FEC -+ help -+ Say Y here if you want to use the second built-in 10/100 Fast -+ ethernet controller on some Motorola ColdFire processors. ++ return 0; ++} + -+config FEC_MPC52xx -+ tristate "MPC52xx FEC driver" -+ depends on PPC_MPC52xx && PPC_BESTCOMM -+ select CRC32 -+ select PHYLIB -+ select PPC_BESTCOMM_FEC -+ ---help--- -+ This option enables support for the MPC5200's on-chip -+ Fast Ethernet Controller -+ If compiled as module, it will be called fec_mpc52xx. -+ -+config FEC_MPC52xx_MDIO -+ bool "MPC52xx FEC MDIO bus driver" -+ depends on FEC_MPC52xx -+ default y -+ ---help--- -+ The MPC5200's FEC can connect to the Ethernet either with -+ an external MII PHY chip or 10 Mbps 7-wire interface -+ (Motorola? industry standard). -+ If your board uses an external PHY connected to FEC, enable this. -+ If not sure, enable. -+ If compiled as module, it will be called fec_mpc52xx_phy. -+ -+config NE_H8300 -+ tristate "NE2000 compatible support for H8/300" -+ depends on H8300 -+ help -+ Say Y here if you want to use the NE2000 compatible -+ controller on the Renesas H8/300 processor. -+ -+config ATL2 -+ tristate "Atheros L2 Fast Ethernet support" -+ depends on PCI -+ select CRC32 -+ select MII -+ help -+ This driver supports the Atheros L2 fast ethernet adapter. ++core_initcall(mips_machtype_init); +diff -Nur linux-2.6.36.orig/arch/mips/kernel/proc.c linux-2.6.36/arch/mips/kernel/proc.c +--- linux-2.6.36.orig/arch/mips/kernel/proc.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/kernel/proc.c 2010-11-18 21:16:05.000000000 +0100 +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + + unsigned int vced_count, vcei_count; + +@@ -31,8 +32,12 @@ + /* + * For the first processor also print the system type + */ +- if (n == 0) ++ if (n == 0) { + seq_printf(m, "system type\t\t: %s\n", get_system_type()); ++#ifdef CONFIG_MIPS_MACHINE ++ seq_printf(m, "machine\t\t\t: %s\n", mips_machine_name); ++#endif ++ } + + seq_printf(m, "processor\t\t: %ld\n", n); + sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n", +diff -Nur linux-2.6.36.orig/arch/mips/kernel/traps.c linux-2.6.36/arch/mips/kernel/traps.c +--- linux-2.6.36.orig/arch/mips/kernel/traps.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/kernel/traps.c 2010-11-18 21:16:05.000000000 +0100 +@@ -52,6 +52,7 @@ + #include + #include + #include ++#include + #include + + extern void check_wait(void); +@@ -1539,6 +1540,8 @@ + if (cpu_has_mips_r2) { + cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; + cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; ++ if (get_c0_compare_irq) ++ cp0_compare_irq = get_c0_compare_irq(); + cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; + if (cp0_perfcount_irq == cp0_compare_irq) + cp0_perfcount_irq = -1; +diff -Nur linux-2.6.36.orig/arch/mips/pci/Makefile linux-2.6.36/arch/mips/pci/Makefile +--- linux-2.6.36.orig/arch/mips/pci/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/arch/mips/pci/Makefile 2010-11-18 21:16:07.000000000 +0100 +@@ -18,6 +18,7 @@ + obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o + obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o ++obj-$(CONFIG_ATHEROS_AR71XX) += pci-ar71xx.o pci-ar724x.o + + # + # These are still pretty much in the old state, watch, go blind. +diff -Nur linux-2.6.36.orig/arch/mips/pci/pci-ar71xx.c linux-2.6.36/arch/mips/pci/pci-ar71xx.c +--- linux-2.6.36.orig/arch/mips/pci/pci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/pci/pci-ar71xx.c 2010-11-18 21:16:07.000000000 +0100 +@@ -0,0 +1,409 @@ ++/* ++ * Atheros AR71xx PCI host controller driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ To compile this driver as a module, choose M here. The module -+ will be called atl2. ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+config XILINX_EMACLITE -+ tristate "Xilinx 10/100 Ethernet Lite support" -+ depends on PPC32 || MICROBLAZE -+ select PHYLIB -+ help -+ This driver supports the 10/100 Ethernet Lite from Xilinx. ++#include ++#include + -+config BCM63XX_ENET -+ tristate "Broadcom 63xx internal mac support" -+ depends on BCM63XX -+ select MII -+ select PHYLIB -+ help -+ This driver supports the ethernet MACs in the Broadcom 63xx -+ MIPS chipset family (BCM63XX). ++#undef DEBUG ++#ifdef DEBUG ++#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) ++#else ++#define DBG(fmt, args...) ++#endif + -+source "drivers/net/fs_enet/Kconfig" ++#define AR71XX_PCI_DELAY 100 /* msecs */ + -+source "drivers/net/octeon/Kconfig" ++#if 0 ++#define PCI_IDSEL_BASE PCI_IDSEL_ADL_START ++#else ++#define PCI_IDSEL_BASE 0 ++#endif + -+endif # NET_ETHERNET ++static void __iomem *ar71xx_pcicfg_base; ++static DEFINE_SPINLOCK(ar71xx_pci_lock); ++static int ar71xx_pci_fixup_enable; + -+# -+# Gigabit Ethernet -+# ++static inline void ar71xx_pci_delay(void) ++{ ++ mdelay(AR71XX_PCI_DELAY); ++} + -+menuconfig NETDEV_1000 -+ bool "Ethernet (1000 Mbit)" -+ depends on !UML -+ default y -+ ---help--- -+ Ethernet (also called IEEE 802.3 or ISO 8802-2) is the most common -+ type of Local Area Network (LAN) in universities and companies. -+ -+ Say Y here to get to see options for Gigabit Ethernet drivers. -+ This option alone does not add any kernel code. -+ Note that drivers supporting both 100 and 1000 MBit may be listed -+ under "Ethernet (10 or 100MBit)" instead. -+ -+ If you say N, all options in this submenu will be skipped and disabled. -+ -+if NETDEV_1000 -+ -+config ACENIC -+ tristate "Alteon AceNIC/3Com 3C985/NetGear GA620 Gigabit support" -+ depends on PCI -+ ---help--- -+ Say Y here if you have an Alteon AceNIC, 3Com 3C985(B), NetGear -+ GA620, SGI Gigabit or Farallon PN9000-SX PCI Gigabit Ethernet -+ adapter. The driver allows for using the Jumbo Frame option (9000 -+ bytes/frame) however it requires that your switches can handle this -+ as well. To enable Jumbo Frames, add `mtu 9000' to your ifconfig -+ line. ++/* Byte lane enable bits */ ++static u8 ble_table[4][4] = { ++ {0x0, 0xf, 0xf, 0xf}, ++ {0xe, 0xd, 0xb, 0x7}, ++ {0xc, 0xf, 0x3, 0xf}, ++ {0xf, 0xf, 0xf, 0xf}, ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called acenic. ++static inline u32 ar71xx_pci_get_ble(int where, int size, int local) ++{ ++ u32 t; + -+config ACENIC_OMIT_TIGON_I -+ bool "Omit support for old Tigon I based AceNICs" -+ depends on ACENIC -+ help -+ Say Y here if you only have Tigon II based AceNICs and want to leave -+ out support for the older Tigon I based cards which are no longer -+ being sold (ie. the original Alteon AceNIC and 3Com 3C985 (non B -+ version)). This will reduce the size of the driver object by -+ app. 100KB. If you are not sure whether your card is a Tigon I or a -+ Tigon II, say N here. -+ -+ The safe and default value for this is N. -+ -+config DL2K -+ tristate "DL2000/TC902x-based Gigabit Ethernet support" -+ depends on PCI -+ select CRC32 -+ help -+ This driver supports DL2000/TC902x-based Gigabit ethernet cards, -+ which includes -+ D-Link DGE-550T Gigabit Ethernet Adapter. -+ D-Link DL2000-based Gigabit Ethernet Adapter. -+ Sundance/Tamarack TC902x Gigabit Ethernet Adapter. ++ t = ble_table[size & 3][where & 3]; ++ BUG_ON(t == 0xf); ++ t <<= (local) ? 20 : 4; ++ return t; ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called dl2k. ++static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn, ++ int where) ++{ ++ u32 ret; + -+config E1000 -+ tristate "Intel(R) PRO/1000 Gigabit Ethernet support" -+ depends on PCI -+ ---help--- -+ This driver supports Intel(R) PRO/1000 gigabit ethernet family of -+ adapters. For more information on how to identify your adapter, go -+ to the Adapter & Driver ID Guide at: ++ if (!bus->number) { ++ /* type 0 */ ++ ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn))) ++ | (PCI_FUNC(devfn) << 8) | (where & ~3); ++ } else { ++ /* type 1 */ ++ ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11) ++ | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1; ++ } + -+ ++ return ret; ++} + -+ For general information and support, go to the Intel support -+ website at: ++int ar71xx_pci_be_handler(int is_fixup) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 pci_err; ++ u32 ahb_err; + -+ ++ pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3; ++ if (pci_err) { ++ if (!is_fixup) ++ printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n", ++ pci_err, ++ __raw_readl(base + PCI_REG_PCI_ERR_ADDR)); + -+ More specific information on configuring the driver is in -+ . ++ __raw_writel(pci_err, base + PCI_REG_PCI_ERR); ++ } + -+ To compile this driver as a module, choose M here. The module -+ will be called e1000. ++ ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1; ++ if (ahb_err) { ++ if (!is_fixup) ++ printk(KERN_ALERT "AHB error at AHB address 0x%x\n", ++ __raw_readl(base + PCI_REG_AHB_ERR_ADDR)); + -+config E1000E -+ tristate "Intel(R) PRO/1000 PCI-Express Gigabit Ethernet support" -+ depends on PCI && (!SPARC32 || BROKEN) -+ ---help--- -+ This driver supports the PCI-Express Intel(R) PRO/1000 gigabit -+ ethernet family of adapters. For PCI or PCI-X e1000 adapters, -+ use the regular e1000 driver For more information on how to -+ identify your adapter, go to the Adapter & Driver ID Guide at: ++ __raw_writel(ahb_err, base + PCI_REG_AHB_ERR); ++ } + -+ ++ return ((ahb_err | pci_err) ? 1 : 0); ++} + -+ For general information and support, go to the Intel support -+ website at: ++static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus, ++ unsigned int devfn, int where, int size, u32 cmd) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ u32 addr; + -+ ++ addr = ar71xx_pci_bus_addr(bus, devfn, where); + -+ To compile this driver as a module, choose M here. The module -+ will be called e1000e. ++ DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ++ where, size, addr); + -+config IP1000 -+ tristate "IP1000 Gigabit Ethernet support" -+ depends on PCI && EXPERIMENTAL -+ select MII -+ ---help--- -+ This driver supports IP1000 gigabit Ethernet cards. ++ __raw_writel(addr, base + PCI_REG_CFG_AD); ++ __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0), ++ base + PCI_REG_CFG_CBE); + -+ To compile this driver as a module, choose M here: the module -+ will be called ipg. This is recommended. ++ return ar71xx_pci_be_handler(1); ++} + -+config IGB -+ tristate "Intel(R) 82575/82576 PCI-Express Gigabit Ethernet support" -+ depends on PCI -+ ---help--- -+ This driver supports Intel(R) 82575/82576 gigabit ethernet family of -+ adapters. For more information on how to identify your adapter, go -+ to the Adapter & Driver ID Guide at: ++static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0}; ++ unsigned long flags; ++ u32 data; ++ int ret; + -+ ++ ret = PCIBIOS_SUCCESSFUL; + -+ For general information and support, go to the Intel support -+ website at: ++ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number, ++ PCI_SLOT(devfn), PCI_FUNC(devfn), where, size); + -+ ++ spin_lock_irqsave(&ar71xx_pci_lock, flags); + -+ More specific information on configuring the driver is in -+ . ++ if (bus->number == 0 && devfn == 0) { ++ u32 t; + -+ To compile this driver as a module, choose M here. The module -+ will be called igb. ++ t = PCI_CRP_CMD_READ | (where & ~3); + -+config IGB_DCA -+ bool "Direct Cache Access (DCA) Support" -+ default y -+ depends on IGB && DCA && !(IGB=y && DCA=m) -+ ---help--- -+ Say Y here if you want to use Direct Cache Access (DCA) in the -+ driver. DCA is a method for warming the CPU cache before data -+ is used, with the intent of lessening the impact of cache misses. ++ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); ++ data = __raw_readl(base + PCI_REG_CRP_RDDATA); + -+config IGBVF -+ tristate "Intel(R) 82576 Virtual Function Ethernet support" -+ depends on PCI -+ ---help--- -+ This driver supports Intel(R) 82576 virtual functions. For more -+ information on how to identify your adapter, go to the Adapter & -+ Driver ID Guide at: ++ DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data); + -+ ++ } else { ++ int err; + -+ For general information and support, go to the Intel support -+ website at: ++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, ++ PCI_CFG_CMD_READ); + -+ ++ if (err == 0) { ++ data = __raw_readl(base + PCI_REG_CFG_RDDATA); ++ } else { ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ data = ~0; ++ } ++ } + -+ More specific information on configuring the driver is in -+ . ++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); + -+ To compile this driver as a module, choose M here. The module -+ will be called igbvf. ++ DBG("PCI: read config: data=%08x raw=%08x\n", ++ (data >> (8 * (where & 3))) & mask[size & 7], data); + -+source "drivers/net/ixp2000/Kconfig" ++ *value = (data >> (8 * (where & 3))) & mask[size & 7]; + -+config MYRI_SBUS -+ tristate "MyriCOM Gigabit Ethernet support" -+ depends on SBUS -+ help -+ This driver supports MyriCOM Sbus gigabit Ethernet cards. ++ return ret; ++} + -+ To compile this driver as a module, choose M here: the module -+ will be called myri_sbus. This is recommended. ++static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ void __iomem *base = ar71xx_pcicfg_base; ++ unsigned long flags; ++ int ret; + -+config NS83820 -+ tristate "National Semiconductor DP83820 support" -+ depends on PCI -+ help -+ This is a driver for the National Semiconductor DP83820 series -+ of gigabit ethernet MACs. Cards using this chipset include -+ the D-Link DGE-500T, PureData's PDP8023Z-TG, SMC's SMC9462TX, -+ SOHO-GA2000T, SOHO-GA2500T. The driver supports the use of -+ zero copy. -+ -+config HAMACHI -+ tristate "Packet Engines Hamachi GNIC-II support" -+ depends on PCI -+ select MII -+ help -+ If you have a Gigabit Ethernet card of this type, say Y and read -+ the Ethernet-HOWTO, available from -+ . -+ -+ To compile this driver as a module, choose M here. The module will be -+ called hamachi. -+ -+config YELLOWFIN -+ tristate "Packet Engines Yellowfin Gigabit-NIC support (EXPERIMENTAL)" -+ depends on PCI && EXPERIMENTAL -+ select CRC32 -+ ---help--- -+ Say Y here if you have a Packet Engines G-NIC PCI Gigabit Ethernet -+ adapter or the SYM53C885 Ethernet controller. The Gigabit adapter is -+ used by the Beowulf Linux cluster project. See -+ for more -+ information about this driver in particular and Beowulf in general. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called yellowfin. This is recommended. -+ -+config R8169 -+ tristate "Realtek 8169 gigabit ethernet support" -+ depends on PCI -+ select CRC32 -+ select MII -+ ---help--- -+ Say Y here if you have a Realtek 8169 PCI Gigabit Ethernet adapter. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called r8169. This is recommended. -+ -+config R8169_VLAN -+ bool "VLAN support" -+ depends on R8169 && VLAN_8021Q -+ ---help--- -+ Say Y here for the r8169 driver to support the functions required -+ by the kernel 802.1Q code. -+ -+ If in doubt, say Y. -+ -+config SB1250_MAC -+ tristate "SB1250 Gigabit Ethernet support" -+ depends on SIBYTE_SB1xxx_SOC -+ select PHYLIB -+ ---help--- -+ This driver supports Gigabit Ethernet interfaces based on the -+ Broadcom SiByte family of System-On-a-Chip parts. They include -+ the BCM1120, BCM1125, BCM1125H, BCM1250, BCM1255, BCM1280, BCM1455 -+ and BCM1480 chips. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called sb1250-mac. -+ -+config SIS190 -+ tristate "SiS190/SiS191 gigabit ethernet support" -+ depends on PCI -+ select CRC32 -+ select MII -+ ---help--- -+ Say Y here if you have a SiS 190 PCI Fast Ethernet adapter or -+ a SiS 191 PCI Gigabit Ethernet adapter. Both are expected to -+ appear in lan on motherboard designs which are based on SiS 965 -+ and SiS 966 south bridge. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called sis190. This is recommended. -+ -+config SKGE -+ tristate "New SysKonnect GigaEthernet support" -+ depends on PCI -+ select CRC32 -+ ---help--- -+ This driver support the Marvell Yukon or SysKonnect SK-98xx/SK-95xx -+ and related Gigabit Ethernet adapters. It is a new smaller driver -+ with better performance and more complete ethtool support. -+ -+ It does not support the link failover and network management -+ features that "portable" vendor supplied sk98lin driver does. -+ -+ This driver supports adapters based on the original Yukon chipset: -+ Marvell 88E8001, Belkin F5D5005, CNet GigaCard, DLink DGE-530T, -+ Linksys EG1032/EG1064, 3Com 3C940/3C940B, SysKonnect SK-9871/9872. -+ -+ It does not support the newer Yukon2 chipset: a separate driver, -+ sky2, is provided for Yukon2-based adapters. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called skge. This is recommended. -+ -+config SKGE_DEBUG -+ bool "Debugging interface" -+ depends on SKGE && DEBUG_FS -+ help -+ This option adds the ability to dump driver state for debugging. -+ The file /sys/kernel/debug/skge/ethX displays the state of the internal -+ transmit and receive rings. -+ -+ If unsure, say N. -+ -+config SKY2 -+ tristate "SysKonnect Yukon2 support" -+ depends on PCI -+ select CRC32 -+ ---help--- -+ This driver supports Gigabit Ethernet adapters based on the -+ Marvell Yukon 2 chipset: -+ Marvell 88E8021/88E8022/88E8035/88E8036/88E8038/88E8050/88E8052/ -+ 88E8053/88E8055/88E8061/88E8062, SysKonnect SK-9E21D/SK-9S21 -+ -+ There is companion driver for the older Marvell Yukon and -+ Genesis based adapters: skge. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called sky2. This is recommended. -+ -+config SKY2_DEBUG -+ bool "Debugging interface" -+ depends on SKY2 && DEBUG_FS -+ help -+ This option adds the ability to dump driver state for debugging. -+ The file /sys/kernel/debug/sky2/ethX displays the state of the internal -+ transmit and receive rings. -+ -+ If unsure, say N. -+ -+config VIA_VELOCITY -+ tristate "VIA Velocity support" -+ depends on PCI -+ select CRC32 -+ select CRC_CCITT -+ select MII -+ help -+ If you have a VIA "Velocity" based network card say Y here. ++ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ++ where, size, value); + -+ To compile this driver as a module, choose M here. The module -+ will be called via-velocity. ++ value = value << (8 * (where & 3)); ++ ret = PCIBIOS_SUCCESSFUL; + -+config TIGON3 -+ tristate "Broadcom Tigon3 support" -+ depends on PCI -+ select PHYLIB -+ help -+ This driver supports Broadcom Tigon3 based gigabit Ethernet cards. ++ spin_lock_irqsave(&ar71xx_pci_lock, flags); ++ if (bus->number == 0 && devfn == 0) { ++ u32 t; + -+ To compile this driver as a module, choose M here: the module -+ will be called tg3. This is recommended. ++ t = PCI_CRP_CMD_WRITE | (where & ~3); ++ t |= ar71xx_pci_get_ble(where, size, 1); + -+config BNX2 -+ tristate "Broadcom NetXtremeII support" -+ depends on PCI -+ select CRC32 -+ select FW_LOADER -+ help -+ This driver supports Broadcom NetXtremeII gigabit Ethernet cards. ++ DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value); + -+ To compile this driver as a module, choose M here: the module -+ will be called bnx2. This is recommended. ++ __raw_writel(t, base + PCI_REG_CRP_AD_CBE); ++ __raw_writel(value, base + PCI_REG_CRP_WRDATA); ++ } else { ++ int err; + -+config CNIC -+ tristate "Broadcom CNIC support" -+ depends on PCI -+ select BNX2 -+ select UIO -+ help -+ This driver supports offload features of Broadcom NetXtremeII -+ gigabit Ethernet cards. ++ err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size, ++ PCI_CFG_CMD_WRITE); + -+ To compile this driver as a module, choose M here: the module -+ will be called cnic. This is recommended. ++ if (err == 0) ++ __raw_writel(value, base + PCI_REG_CFG_WRDATA); ++ else ++ ret = PCIBIOS_DEVICE_NOT_FOUND; ++ } ++ spin_unlock_irqrestore(&ar71xx_pci_lock, flags); + -+config SPIDER_NET -+ tristate "Spider Gigabit Ethernet driver" -+ depends on PCI && (PPC_IBM_CELL_BLADE || PPC_CELLEB) -+ select FW_LOADER -+ help -+ This driver supports the Gigabit Ethernet chips present on the -+ Cell Processor-Based Blades from IBM. -+ -+config TSI108_ETH -+ tristate "Tundra TSI108 gigabit Ethernet support" -+ depends on TSI108_BRIDGE -+ help -+ This driver supports Tundra TSI108 gigabit Ethernet ports. -+ To compile this driver as a module, choose M here: the module -+ will be called tsi108_eth. -+ -+config GELIC_NET -+ tristate "PS3 Gigabit Ethernet driver" -+ depends on PPC_PS3 -+ select PS3_SYS_MANAGER -+ help -+ This driver supports the network device on the PS3 game -+ console. This driver has built-in support for Ethernet. ++ return ret; ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called ps3_gelic. ++static void ar71xx_pci_fixup(struct pci_dev *dev) ++{ ++ u32 t; + -+config GELIC_WIRELESS -+ bool "PS3 Wireless support" -+ depends on WLAN -+ depends on GELIC_NET -+ select WIRELESS_EXT -+ help -+ This option adds the support for the wireless feature of PS3. -+ If you have the wireless-less model of PS3 or have no plan to -+ use wireless feature, disabling this option saves memory. As -+ the driver automatically distinguishes the models, you can -+ safely enable this option even if you have a wireless-less model. -+ -+config FSL_PQ_MDIO -+ tristate "Freescale PQ MDIO" -+ depends on FSL_SOC -+ select PHYLIB -+ help -+ This driver supports the MDIO bus used by the gianfar and UCC drivers. ++ if (!ar71xx_pci_fixup_enable) ++ return; + -+config GIANFAR -+ tristate "Gianfar Ethernet" -+ depends on FSL_SOC -+ select FSL_PQ_MDIO -+ select PHYLIB -+ select CRC32 -+ help -+ This driver supports the Gigabit TSEC on the MPC83xx, MPC85xx, -+ and MPC86xx family of chips, and the FEC on the 8540. ++ if (dev->bus->number != 0 || dev->devfn != 0) ++ return; + -+config UCC_GETH -+ tristate "Freescale QE Gigabit Ethernet" -+ depends on QUICC_ENGINE -+ select FSL_PQ_MDIO -+ select PHYLIB -+ help -+ This driver supports the Gigabit Ethernet mode of the QUICC Engine, -+ which is available on some Freescale SOCs. ++ DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev), ++ dev->vendor, dev->device); + -+config UGETH_TX_ON_DEMAND -+ bool "Transmit on Demand support" -+ depends on UCC_GETH ++ /* setup COMMAND register */ ++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE ++ | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK; + -+config MV643XX_ETH -+ tristate "Marvell Discovery (643XX) and Orion ethernet support" -+ depends on MV64X60 || PPC32 || PLAT_ORION -+ select INET_LRO -+ select PHYLIB -+ help -+ This driver supports the gigabit ethernet MACs in the -+ Marvell Discovery PPC/MIPS chipset family (MV643XX) and -+ in the Marvell Orion ARM SoC family. ++ pci_write_config_word(dev, PCI_COMMAND, t); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup); + -+ Some boards that use the Discovery chipset are the Momenco -+ Ocelot C and Jaguar ATX and Pegasos II. ++int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, ++ uint8_t pin) ++{ ++ int irq = -1; ++ int i; + -+config XILINX_LL_TEMAC -+ tristate "Xilinx LL TEMAC (LocalLink Tri-mode Ethernet MAC) driver" -+ depends on PPC || MICROBLAZE -+ select PHYLIB -+ help -+ This driver supports the Xilinx 10/100/1000 LocalLink TEMAC -+ core used in Xilinx Spartan and Virtex FPGAs ++ slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE; + -+config QLA3XXX -+ tristate "QLogic QLA3XXX Network Driver Support" -+ depends on PCI -+ help -+ This driver supports QLogic ISP3XXX gigabit Ethernet cards. ++ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { ++ struct ar71xx_pci_irq *entry; + -+ To compile this driver as a module, choose M here: the module -+ will be called qla3xxx. ++ entry = &ar71xx_pci_irq_map[i]; ++ if (entry->slot == slot && entry->pin == pin) { ++ irq = entry->irq; ++ break; ++ } ++ } + -+config ATL1 -+ tristate "Atheros/Attansic L1 Gigabit Ethernet support" -+ depends on PCI -+ select CRC32 -+ select MII -+ help -+ This driver supports the Atheros/Attansic L1 gigabit ethernet -+ adapter. ++ if (irq < 0) { ++ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", ++ pin, pci_name((struct pci_dev *)dev)); ++ } else { ++ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", ++ irq, pin, pci_name((struct pci_dev *)dev)); ++ } + -+ To compile this driver as a module, choose M here. The module -+ will be called atl1. ++ return irq; ++} + -+config ATL1E -+ tristate "Atheros L1E Gigabit Ethernet support (EXPERIMENTAL)" -+ depends on PCI && EXPERIMENTAL -+ select CRC32 -+ select MII -+ help -+ This driver supports the Atheros L1E gigabit ethernet adapter. ++static struct pci_ops ar71xx_pci_ops = { ++ .read = ar71xx_pci_read_config, ++ .write = ar71xx_pci_write_config, ++}; + -+ To compile this driver as a module, choose M here. The module -+ will be called atl1e. ++static struct resource ar71xx_pci_io_resource = { ++ .name = "PCI IO space", ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IO, ++}; + -+config ATL1C -+ tristate "Atheros L1C Gigabit Ethernet support (EXPERIMENTAL)" -+ depends on PCI && EXPERIMENTAL -+ select CRC32 -+ select MII -+ help -+ This driver supports the Atheros L1C gigabit ethernet adapter. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called atl1c. -+ -+config JME -+ tristate "JMicron(R) PCI-Express Gigabit Ethernet support" -+ depends on PCI -+ select CRC32 -+ select MII -+ ---help--- -+ This driver supports the PCI-Express gigabit ethernet adapters -+ based on JMicron JMC250 chipset. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called jme. -+ -+config S6GMAC -+ tristate "S6105 GMAC ethernet support" -+ depends on XTENSA_VARIANT_S6000 -+ select PHYLIB -+ help -+ This driver supports the on chip ethernet device on the -+ S6105 xtensa processor. ++static struct resource ar71xx_pci_mem_resource = { ++ .name = "PCI memory space", ++ .start = AR71XX_PCI_MEM_BASE, ++ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, ++ .flags = IORESOURCE_MEM ++}; ++ ++static struct pci_controller ar71xx_pci_controller = { ++ .pci_ops = &ar71xx_pci_ops, ++ .mem_resource = &ar71xx_pci_mem_resource, ++ .io_resource = &ar71xx_pci_io_resource, ++}; + -+ To compile this driver as a module, choose M here. The module -+ will be called s6gmac. ++static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ u32 pending; + -+source "drivers/net/stmmac/Kconfig" ++ pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & ++ __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); + -+endif # NETDEV_1000 ++ if (pending & PCI_INT_DEV0) ++ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); + -+# -+# 10 Gigabit Ethernet -+# ++ else if (pending & PCI_INT_DEV1) ++ generic_handle_irq(AR71XX_PCI_IRQ_DEV1); + -+menuconfig NETDEV_10000 -+ bool "Ethernet (10000 Mbit)" -+ depends on !UML -+ default y -+ ---help--- -+ Say Y here to get to see options for 10 Gigabit Ethernet drivers. -+ This option alone does not add any kernel code. ++ else if (pending & PCI_INT_DEV2) ++ generic_handle_irq(AR71XX_PCI_IRQ_DEV2); + -+ If you say N, all options in this submenu will be skipped and disabled. ++ else if (pending & PCI_INT_CORE) ++ generic_handle_irq(AR71XX_PCI_IRQ_CORE); + -+if NETDEV_10000 ++ else ++ spurious_interrupt(); ++} + -+config MDIO -+ tristate ++static void ar71xx_pci_irq_unmask(unsigned int irq) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; + -+config CHELSIO_T1 -+ tristate "Chelsio 10Gb Ethernet support" -+ depends on PCI -+ select CRC32 -+ select MDIO -+ help -+ This driver supports Chelsio gigabit and 10-gigabit -+ Ethernet cards. More information about adapter features and -+ performance tuning is in . ++ irq -= AR71XX_PCI_IRQ_BASE; + -+ For general information about Chelsio and our products, visit -+ our website at . ++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); + -+ For customer support, please visit our customer support page at -+ . ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++} + -+ Please send feedback to . ++static void ar71xx_pci_irq_mask(unsigned int irq) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ u32 t; + -+ To compile this driver as a module, choose M here: the module -+ will be called cxgb. ++ irq -= AR71XX_PCI_IRQ_BASE; + -+config CHELSIO_T1_1G -+ bool "Chelsio gigabit Ethernet support" -+ depends on CHELSIO_T1 -+ help -+ Enables support for Chelsio's gigabit Ethernet PCI cards. If you -+ are using only 10G cards say 'N' here. ++ t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE); + -+config CHELSIO_T3_DEPENDS -+ tristate -+ depends on PCI && INET -+ default y ++ /* flush write */ ++ (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++} + -+config CHELSIO_T3 -+ tristate "Chelsio Communications T3 10Gb Ethernet support" -+ depends on CHELSIO_T3_DEPENDS -+ select FW_LOADER -+ select MDIO -+ help -+ This driver supports Chelsio T3-based gigabit and 10Gb Ethernet -+ adapters. ++static struct irq_chip ar71xx_pci_irq_chip = { ++ .name = "AR71XX PCI ", ++ .mask = ar71xx_pci_irq_mask, ++ .unmask = ar71xx_pci_irq_unmask, ++ .mask_ack = ar71xx_pci_irq_mask, ++}; + -+ For general information about Chelsio and our products, visit -+ our website at . ++static void __init ar71xx_pci_irq_init(void) ++{ ++ void __iomem *base = ar71xx_reset_base; ++ int i; + -+ For customer support, please visit our customer support page at -+ . ++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE); ++ __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS); + -+ Please send feedback to . ++ for (i = AR71XX_PCI_IRQ_BASE; ++ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { ++ irq_desc[i].status = IRQ_DISABLED; ++ set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip, ++ handle_level_irq); ++ } + -+ To compile this driver as a module, choose M here: the module -+ will be called cxgb3. ++ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler); ++} + -+config CHELSIO_T4_DEPENDS -+ tristate -+ depends on PCI && INET -+ default y ++int __init ar71xx_pcibios_init(void) ++{ ++ void __iomem *ddr_base = ar71xx_ddr_base; + -+config CHELSIO_T4 -+ tristate "Chelsio Communications T4 Ethernet support" -+ depends on CHELSIO_T4_DEPENDS -+ select FW_LOADER -+ select MDIO -+ help -+ This driver supports Chelsio T4-based gigabit and 10Gb Ethernet -+ adapters. ++ ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); ++ ar71xx_pci_delay(); + -+ For general information about Chelsio and our products, visit -+ our website at . ++ ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE); ++ ar71xx_pci_delay(); + -+ For customer support, please visit our customer support page at -+ . ++ ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE, ++ AR71XX_PCI_CFG_SIZE); ++ if (ar71xx_pcicfg_base == NULL) ++ return -ENOMEM; + -+ Please send feedback to . ++ __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0); ++ __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1); ++ __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2); ++ __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3); ++ __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4); ++ __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5); ++ __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6); ++ __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7); + -+ To compile this driver as a module choose M here; the module -+ will be called cxgb4. ++ ar71xx_pci_delay(); + -+config EHEA -+ tristate "eHEA Ethernet support" -+ depends on IBMEBUS && INET && SPARSEMEM -+ select INET_LRO -+ ---help--- -+ This driver supports the IBM pSeries eHEA ethernet adapter. ++ /* clear bus errors */ ++ (void)ar71xx_pci_be_handler(1); + -+ To compile the driver as a module, choose M here. The module -+ will be called ehea. ++ ar71xx_pci_fixup_enable = 1; ++ ar71xx_pci_irq_init(); ++ register_pci_controller(&ar71xx_pci_controller); + -+config ENIC -+ tristate "Cisco VIC Ethernet NIC Support" -+ depends on PCI && INET -+ select INET_LRO -+ help -+ This enables the support for the Cisco VIC Ethernet card. ++ return 0; ++} +diff -Nur linux-2.6.36.orig/arch/mips/pci/pci-ar724x.c linux-2.6.36/arch/mips/pci/pci-ar724x.c +--- linux-2.6.36.orig/arch/mips/pci/pci-ar724x.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/arch/mips/pci/pci-ar724x.c 2010-11-18 21:16:07.000000000 +0100 +@@ -0,0 +1,395 @@ ++/* ++ * Atheros AR724x PCI host controller driver ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+config IXGBE -+ tristate "Intel(R) 10GbE PCI Express adapters support" -+ depends on PCI && INET -+ select MDIO -+ ---help--- -+ This driver supports Intel(R) 10GbE PCI Express family of -+ adapters. For more information on how to identify your adapter, go -+ to the Adapter & Driver ID Guide at: ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+ ++#include ++#include + -+ For general information and support, go to the Intel support -+ website at: ++#undef DEBUG ++#ifdef DEBUG ++#define DBG(fmt, args...) printk(KERN_INFO fmt, ## args) ++#else ++#define DBG(fmt, args...) ++#endif + -+ ++static void __iomem *ar724x_pci_localcfg_base; ++static void __iomem *ar724x_pci_devcfg_base; ++static void __iomem *ar724x_pci_ctrl_base; ++static int ar724x_pci_fixup_enable; + -+ To compile this driver as a module, choose M here. The module -+ will be called ixgbe. ++static DEFINE_SPINLOCK(ar724x_pci_lock); + -+config IXGBE_DCA -+ bool "Direct Cache Access (DCA) Support" -+ default y -+ depends on IXGBE && DCA && !(IXGBE=y && DCA=m) -+ ---help--- -+ Say Y here if you want to use Direct Cache Access (DCA) in the -+ driver. DCA is a method for warming the CPU cache before data -+ is used, with the intent of lessening the impact of cache misses. -+ -+config IXGBE_DCB -+ bool "Data Center Bridging (DCB) Support" -+ default n -+ depends on IXGBE && DCB -+ ---help--- -+ Say Y here if you want to use Data Center Bridging (DCB) in the -+ driver. -+ -+ If unsure, say N. -+ -+config IXGBEVF -+ tristate "Intel(R) 82599 Virtual Function Ethernet support" -+ depends on PCI_MSI -+ ---help--- -+ This driver supports Intel(R) 82599 virtual functions. For more -+ information on how to identify your adapter, go to the Adapter & -+ Driver ID Guide at: -+ -+ -+ -+ For general information and support, go to the Intel support -+ website at: -+ -+ -+ -+ More specific information on configuring the driver is in -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ixgbevf. MSI-X interrupt support is required -+ for this driver to work correctly. -+ -+config IXGB -+ tristate "Intel(R) PRO/10GbE support" -+ depends on PCI -+ ---help--- -+ This driver supports Intel(R) PRO/10GbE family of adapters for -+ PCI-X type cards. For PCI-E type cards, use the "ixgbe" driver -+ instead. For more information on how to identify your adapter, go -+ to the Adapter & Driver ID Guide at: -+ -+ -+ -+ For general information and support, go to the Intel support -+ website at: -+ -+ -+ -+ More specific information on configuring the driver is in -+ . -+ -+ To compile this driver as a module, choose M here. The module -+ will be called ixgb. -+ -+config S2IO -+ tristate "S2IO 10Gbe XFrame NIC" -+ depends on PCI -+ ---help--- -+ This driver supports the 10Gbe XFrame NIC of S2IO. -+ More specific information on configuring the driver is in -+ . -+ -+config VXGE -+ tristate "Neterion X3100 Series 10GbE PCIe Server Adapter" -+ depends on PCI && INET -+ ---help--- -+ This driver supports Neterion Inc's X3100 Series 10 GbE PCIe -+ I/O Virtualized Server Adapter. -+ More specific information on configuring the driver is in -+ . -+ -+config VXGE_DEBUG_TRACE_ALL -+ bool "Enabling All Debug trace statments in driver" -+ default n -+ depends on VXGE -+ ---help--- -+ Say Y here if you want to enabling all the debug trace statements in -+ driver. By default only few debug trace statements are enabled. -+ -+config MYRI10GE -+ tristate "Myricom Myri-10G Ethernet support" -+ depends on PCI && INET -+ select FW_LOADER -+ select CRC32 -+ select INET_LRO -+ ---help--- -+ This driver supports Myricom Myri-10G Dual Protocol interface in -+ Ethernet mode. If the eeprom on your board is not recent enough, -+ you will need a newer firmware image. -+ You may get this image or more information, at: -+ -+ -+ -+ To compile this driver as a module, choose M here. The module -+ will be called myri10ge. -+ -+config MYRI10GE_DCA -+ bool "Direct Cache Access (DCA) Support" -+ default y -+ depends on MYRI10GE && DCA && !(MYRI10GE=y && DCA=m) -+ ---help--- -+ Say Y here if you want to use Direct Cache Access (DCA) in the -+ driver. DCA is a method for warming the CPU cache before data -+ is used, with the intent of lessening the impact of cache misses. -+ -+config NETXEN_NIC -+ tristate "NetXen Multi port (1/10) Gigabit Ethernet NIC" -+ depends on PCI -+ select FW_LOADER -+ help -+ This enables the support for NetXen's Gigabit Ethernet card. ++static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value) ++{ ++ unsigned long flags; ++ u32 data; + -+config NIU -+ tristate "Sun Neptune 10Gbit Ethernet support" -+ depends on PCI -+ select CRC32 -+ help -+ This enables support for cards based upon Sun's -+ Neptune chipset. ++ spin_lock_irqsave(&ar724x_pci_lock, flags); ++ data = __raw_readl(base + (where & ~3)); + -+config PASEMI_MAC -+ tristate "PA Semi 1/10Gbit MAC" -+ depends on PPC_PASEMI && PCI -+ select PHYLIB -+ select INET_LRO -+ help -+ This driver supports the on-chip 1/10Gbit Ethernet controller on -+ PA Semi's PWRficient line of chips. -+ -+config MLX4_EN -+ tristate "Mellanox Technologies 10Gbit Ethernet support" -+ depends on PCI && INET -+ select MLX4_CORE -+ select INET_LRO -+ help -+ This driver supports Mellanox Technologies ConnectX Ethernet -+ devices. ++ switch (size) { ++ case 1: ++ if (where & 1) ++ data >>= 8; ++ if (where & 2) ++ data >>= 16; ++ data &= 0xFF; ++ break; ++ case 2: ++ if (where & 2) ++ data >>= 16; ++ data &= 0xFFFF; ++ break; ++ } + -+config MLX4_CORE -+ tristate -+ depends on PCI -+ default n ++ *value = data; ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++} + -+config MLX4_DEBUG -+ bool "Verbose debugging output" if (MLX4_CORE && EMBEDDED) -+ depends on MLX4_CORE -+ default y -+ ---help--- -+ This option causes debugging code to be compiled into the -+ mlx4_core driver. The output can be turned on via the -+ debug_level module parameter (which can also be set after -+ the driver is loaded through sysfs). -+ -+config TEHUTI -+ tristate "Tehuti Networks 10G Ethernet" -+ depends on PCI -+ help -+ Tehuti Networks 10G Ethernet NIC -+ -+config BNX2X -+ tristate "Broadcom NetXtremeII 10Gb support" -+ depends on PCI -+ select FW_LOADER -+ select ZLIB_INFLATE -+ select LIBCRC32C -+ select MDIO -+ help -+ This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards. -+ To compile this driver as a module, choose M here: the module -+ will be called bnx2x. This is recommended. -+ -+config QLCNIC -+ tristate "QLOGIC QLCNIC 1/10Gb Converged Ethernet NIC Support" -+ depends on PCI -+ select FW_LOADER -+ help -+ This driver supports QLogic QLE8240 and QLE8242 Converged Ethernet -+ devices. ++static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value) ++{ ++ unsigned long flags; ++ u32 data; ++ int s; + -+config QLGE -+ tristate "QLogic QLGE 10Gb Ethernet Driver Support" -+ depends on PCI -+ help -+ This driver supports QLogic ISP8XXX 10Gb Ethernet cards. ++ spin_lock_irqsave(&ar724x_pci_lock, flags); ++ data = __raw_readl(base + (where & ~3)); + -+ To compile this driver as a module, choose M here: the module -+ will be called qlge. ++ switch (size) { ++ case 1: ++ s = ((where & 3) << 3); ++ data &= ~(0xFF << s); ++ data |= ((value & 0xFF) << s); ++ break; ++ case 2: ++ s = ((where & 2) << 3); ++ data &= ~(0xFFFF << s); ++ data |= ((value & 0xFFFF) << s); ++ break; ++ case 4: ++ data = value; ++ break; ++ } + -+source "drivers/net/sfc/Kconfig" ++ __raw_writel(data, base + (where & ~3)); ++ /* flush write */ ++ (void)__raw_readl(base + (where & ~3)); ++ spin_unlock_irqrestore(&ar724x_pci_lock, flags); ++} + -+source "drivers/net/benet/Kconfig" ++static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 *value) ++{ + -+endif # NETDEV_10000 ++ if (bus->number != 0 || devfn != 0) ++ return PCIBIOS_DEVICE_NOT_FOUND; + -+source "drivers/net/tokenring/Kconfig" ++ ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value); + -+source "drivers/net/wireless/Kconfig" ++ DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ++ where, size, *value); + -+source "drivers/net/wimax/Kconfig" ++ /* ++ * WAR for BAR issue - We are unable to access the PCI device space ++ * if we set the BAR with proper base address ++ */ ++ if ((where == 0x10) && (size == 4)) { ++ if (ar71xx_soc == AR71XX_SOC_AR7240) ++ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff); ++ else ++ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0x1000ffff); ++ } + -+source "drivers/net/usb/Kconfig" ++ return PCIBIOS_SUCCESSFUL; ++} + -+source "drivers/net/pcmcia/Kconfig" ++static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn, ++ int where, int size, u32 value) ++{ ++ if (bus->number != 0 || devfn != 0) ++ return PCIBIOS_DEVICE_NOT_FOUND; + -+source "drivers/net/wan/Kconfig" ++ DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n", ++ bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), ++ where, size, value); + -+source "drivers/atm/Kconfig" ++ ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value); + -+source "drivers/ieee802154/Kconfig" ++ return PCIBIOS_SUCCESSFUL; ++} + -+source "drivers/s390/net/Kconfig" ++static void ar724x_pci_fixup(struct pci_dev *dev) ++{ ++ u16 cmd; + -+source "drivers/net/caif/Kconfig" ++ if (!ar724x_pci_fixup_enable) ++ return; + -+config XEN_NETDEV_FRONTEND -+ tristate "Xen network device frontend driver" -+ depends on XEN -+ default y -+ help -+ The network device frontend driver allows the kernel to -+ access network devices exported exported by a virtual -+ machine containing a physical network device driver. The -+ frontend driver is intended for unprivileged guest domains; -+ if you are compiling a kernel for a Xen guest, you almost -+ certainly want to enable this. -+ -+config ISERIES_VETH -+ tristate "iSeries Virtual Ethernet driver support" -+ depends on PPC_ISERIES -+ -+config RIONET -+ tristate "RapidIO Ethernet over messaging driver support" -+ depends on RAPIDIO -+ -+config RIONET_TX_SIZE -+ int "Number of outbound queue entries" -+ depends on RIONET -+ default "128" -+ -+config RIONET_RX_SIZE -+ int "Number of inbound queue entries" -+ depends on RIONET -+ default "128" -+ -+config FDDI -+ tristate "FDDI driver support" -+ depends on (PCI || EISA || TC) -+ help -+ Fiber Distributed Data Interface is a high speed local area network -+ design; essentially a replacement for high speed Ethernet. FDDI can -+ run over copper or fiber. If you are connected to such a network and -+ want a driver for the FDDI card in your computer, say Y here (and -+ then also Y to the driver for your FDDI card, below). Most people -+ will say N. -+ -+config DEFXX -+ tristate "Digital DEFTA/DEFEA/DEFPA adapter support" -+ depends on FDDI && (PCI || EISA || TC) -+ ---help--- -+ This is support for the DIGITAL series of TURBOchannel (DEFTA), -+ EISA (DEFEA) and PCI (DEFPA) controllers which can connect you -+ to a local FDDI network. -+ -+ To compile this driver as a module, choose M here: the module -+ will be called defxx. If unsure, say N. -+ -+config DEFXX_MMIO -+ bool -+ prompt "Use MMIO instead of PIO" if PCI || EISA -+ depends on DEFXX -+ default n if PCI || EISA -+ default y -+ ---help--- -+ This instructs the driver to use EISA or PCI memory-mapped I/O -+ (MMIO) as appropriate instead of programmed I/O ports (PIO). -+ Enabling this gives an improvement in processing time in parts -+ of the driver, but it may cause problems with EISA (DEFEA) -+ adapters. TURBOchannel does not have the concept of I/O ports, -+ so MMIO is always used for these (DEFTA) adapters. -+ -+ If unsure, say N. -+ -+config SKFP -+ tristate "SysKonnect FDDI PCI support" -+ depends on FDDI && PCI -+ select BITREVERSE -+ ---help--- -+ Say Y here if you have a SysKonnect FDDI PCI adapter. -+ The following adapters are supported by this driver: -+ - SK-5521 (SK-NET FDDI-UP) -+ - SK-5522 (SK-NET FDDI-UP DAS) -+ - SK-5541 (SK-NET FDDI-FP) -+ - SK-5543 (SK-NET FDDI-LP) -+ - SK-5544 (SK-NET FDDI-LP DAS) -+ - SK-5821 (SK-NET FDDI-UP64) -+ - SK-5822 (SK-NET FDDI-UP64 DAS) -+ - SK-5841 (SK-NET FDDI-FP64) -+ - SK-5843 (SK-NET FDDI-LP64) -+ - SK-5844 (SK-NET FDDI-LP64 DAS) -+ - Netelligent 100 FDDI DAS Fibre SC -+ - Netelligent 100 FDDI SAS Fibre SC -+ - Netelligent 100 FDDI DAS UTP -+ - Netelligent 100 FDDI SAS UTP -+ - Netelligent 100 FDDI SAS Fibre MIC -+ -+ Read for information about -+ the driver. -+ -+ Questions concerning this driver can be addressed to: -+ -+ -+ To compile this driver as a module, choose M here: the module -+ will be called skfp. This is recommended. -+ -+config HIPPI -+ bool "HIPPI driver support (EXPERIMENTAL)" -+ depends on EXPERIMENTAL && INET && PCI -+ help -+ HIgh Performance Parallel Interface (HIPPI) is a 800Mbit/sec and -+ 1600Mbit/sec dual-simplex switched or point-to-point network. HIPPI -+ can run over copper (25m) or fiber (300m on multi-mode or 10km on -+ single-mode). HIPPI networks are commonly used for clusters and to -+ connect to super computers. If you are connected to a HIPPI network -+ and have a HIPPI network card in your computer that you want to use -+ under Linux, say Y here (you must also remember to enable the driver -+ for your HIPPI card below). Most people will say N here. -+ -+config ROADRUNNER -+ tristate "Essential RoadRunner HIPPI PCI adapter support (EXPERIMENTAL)" -+ depends on HIPPI && PCI -+ help -+ Say Y here if this is your PCI HIPPI network card. ++ if (dev->bus->number != 0 || dev->devfn != 0) ++ return; + -+ To compile this driver as a module, choose M here: the module -+ will be called rrunner. If unsure, say N. ++ /* setup COMMAND register */ ++ pci_read_config_word(dev, PCI_COMMAND, &cmd); ++ cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | ++ PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | ++ PCI_COMMAND_FAST_BACK; + -+config ROADRUNNER_LARGE_RINGS -+ bool "Use large TX/RX rings (EXPERIMENTAL)" -+ depends on ROADRUNNER -+ help -+ If you say Y here, the RoadRunner driver will preallocate up to 2 MB -+ of additional memory to allow for fastest operation, both for -+ transmitting and receiving. This memory cannot be used by any other -+ kernel code or by user space programs. Say Y here only if you have -+ the memory. -+ -+config PLIP -+ tristate "PLIP (parallel port) support" -+ depends on PARPORT -+ ---help--- -+ PLIP (Parallel Line Internet Protocol) is used to create a -+ reasonably fast mini network consisting of two (or, rarely, more) -+ local machines. A PLIP link from a Linux box is a popular means to -+ install a Linux distribution on a machine which doesn't have a -+ CD-ROM drive (a minimal system has to be transferred with floppies -+ first). The kernels on both machines need to have this PLIP option -+ enabled for this to work. -+ -+ The PLIP driver has two modes, mode 0 and mode 1. The parallel -+ ports (the connectors at the computers with 25 holes) are connected -+ with "null printer" or "Turbo Laplink" cables which can transmit 4 -+ bits at a time (mode 0) or with special PLIP cables, to be used on -+ bidirectional parallel ports only, which can transmit 8 bits at a -+ time (mode 1); you can find the wiring of these cables in -+ . The cables can be up to -+ 15m long. Mode 0 works also if one of the machines runs DOS/Windows -+ and has some PLIP software installed, e.g. the Crynwr PLIP packet -+ driver () -+ and winsock or NCSA's telnet. -+ -+ If you want to use PLIP, say Y and read the PLIP mini-HOWTO as well -+ as the NET-3-HOWTO, both available from -+ . Note that the PLIP -+ protocol has been changed and this PLIP driver won't work together -+ with the PLIP support in Linux versions 1.0.x. This option enlarges -+ your kernel by about 8 KB. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called plip. If unsure, say Y or M, in case you buy -+ a laptop later. -+ -+config PPP -+ tristate "PPP (point-to-point protocol) support" -+ select SLHC -+ ---help--- -+ PPP (Point to Point Protocol) is a newer and better SLIP. It serves -+ the same purpose: sending Internet traffic over telephone (and other -+ serial) lines. Ask your access provider if they support it, because -+ otherwise you can't use it; most Internet access providers these -+ days support PPP rather than SLIP. -+ -+ To use PPP, you need an additional program called pppd as described -+ in the PPP-HOWTO, available at -+ . Make sure that you have -+ the version of pppd recommended in . -+ The PPP option enlarges your kernel by about 16 KB. -+ -+ There are actually two versions of PPP: the traditional PPP for -+ asynchronous lines, such as regular analog phone lines, and -+ synchronous PPP which can be used over digital ISDN lines for -+ example. If you want to use PPP over phone lines or other -+ asynchronous serial lines, you need to say Y (or M) here and also to -+ the next option, "PPP support for async serial ports". For PPP over -+ synchronous lines, you should say Y (or M) here and to "Support -+ synchronous PPP", below. -+ -+ If you said Y to "Version information on all symbols" above, then -+ you cannot compile the PPP driver into the kernel; you can then only -+ compile it as a module. To compile this driver as a module, choose M -+ here. The module will be called ppp_generic. -+ -+config PPP_MULTILINK -+ bool "PPP multilink support (EXPERIMENTAL)" -+ depends on PPP && EXPERIMENTAL -+ help -+ PPP multilink is a protocol (defined in RFC 1990) which allows you -+ to combine several (logical or physical) lines into one logical PPP -+ connection, so that you can utilize your full bandwidth. ++ pci_write_config_word(dev, PCI_COMMAND, cmd); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup); + -+ This has to be supported at the other end as well and you need a -+ version of the pppd daemon which understands the multilink protocol. ++int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot, ++ uint8_t pin) ++{ ++ int irq = -1; ++ int i; + -+ If unsure, say N. ++ for (i = 0; i < ar71xx_pci_nr_irqs; i++) { ++ struct ar71xx_pci_irq *entry; ++ entry = &ar71xx_pci_irq_map[i]; + -+config PPP_FILTER -+ bool "PPP filtering" -+ depends on PPP -+ help -+ Say Y here if you want to be able to filter the packets passing over -+ PPP interfaces. This allows you to control which packets count as -+ activity (i.e. which packets will reset the idle timer or bring up -+ a demand-dialed link) and which packets are to be dropped entirely. -+ You need to say Y here if you wish to use the pass-filter and -+ active-filter options to pppd. -+ -+ If unsure, say N. -+ -+config PPP_ASYNC -+ tristate "PPP support for async serial ports" -+ depends on PPP -+ select CRC_CCITT -+ ---help--- -+ Say Y (or M) here if you want to be able to use PPP over standard -+ asynchronous serial ports, such as COM1 or COM2 on a PC. If you use -+ a modem (not a synchronous or ISDN modem) to contact your ISP, you -+ need this option. -+ -+ To compile this driver as a module, choose M here. -+ -+ If unsure, say Y. -+ -+config PPP_SYNC_TTY -+ tristate "PPP support for sync tty ports" -+ depends on PPP -+ help -+ Say Y (or M) here if you want to be able to use PPP over synchronous -+ (HDLC) tty devices, such as the SyncLink adapter. These devices -+ are often used for high-speed leased lines like T1/E1. -+ -+ To compile this driver as a module, choose M here. -+ -+config PPP_DEFLATE -+ tristate "PPP Deflate compression" -+ depends on PPP -+ select ZLIB_INFLATE -+ select ZLIB_DEFLATE -+ ---help--- -+ Support for the Deflate compression method for PPP, which uses the -+ Deflate algorithm (the same algorithm that gzip uses) to compress -+ each PPP packet before it is sent over the wire. The machine at the -+ other end of the PPP link (usually your ISP) has to support the -+ Deflate compression method as well for this to be useful. Even if -+ they don't support it, it is safe to say Y here. -+ -+ To compile this driver as a module, choose M here. -+ -+config PPP_BSDCOMP -+ tristate "PPP BSD-Compress compression" -+ depends on PPP -+ ---help--- -+ Support for the BSD-Compress compression method for PPP, which uses -+ the LZW compression method to compress each PPP packet before it is -+ sent over the wire. The machine at the other end of the PPP link -+ (usually your ISP) has to support the BSD-Compress compression -+ method as well for this to be useful. Even if they don't support it, -+ it is safe to say Y here. -+ -+ The PPP Deflate compression method ("PPP Deflate compression", -+ above) is preferable to BSD-Compress, because it compresses better -+ and is patent-free. -+ -+ Note that the BSD compression code will always be compiled as a -+ module; it is called bsd_comp and will show up in the directory -+ modules once you have said "make modules". If unsure, say N. -+ -+config PPP_MPPE -+ tristate "PPP MPPE compression (encryption) (EXPERIMENTAL)" -+ depends on PPP && EXPERIMENTAL -+ select CRYPTO -+ select CRYPTO_SHA1 -+ select CRYPTO_ARC4 -+ select CRYPTO_ECB -+ ---help--- -+ Support for the MPPE Encryption protocol, as employed by the -+ Microsoft Point-to-Point Tunneling Protocol. -+ -+ See http://pptpclient.sourceforge.net/ for information on -+ configuring PPTP clients and servers to utilize this method. -+ -+config PPPOE -+ tristate "PPP over Ethernet (EXPERIMENTAL)" -+ depends on EXPERIMENTAL && PPP -+ help -+ Support for PPP over Ethernet. ++ if (entry->slot == slot && entry->pin == pin) { ++ irq = entry->irq; ++ break; ++ } ++ } + -+ This driver requires the latest version of pppd from the CVS -+ repository at cvs.samba.org. Alternatively, see the -+ RoaringPenguin package () -+ which contains instruction on how to use this driver (under -+ the heading "Kernel mode PPPoE"). ++ if (irq < 0) ++ printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n", ++ pin, pci_name((struct pci_dev *)dev)); ++ else ++ printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n", ++ irq, pin, pci_name((struct pci_dev *)dev)); + -+config PPPOATM -+ tristate "PPP over ATM" -+ depends on ATM && PPP -+ help -+ Support PPP (Point to Point Protocol) encapsulated in ATM frames. -+ This implementation does not yet comply with section 8 of RFC2364, -+ which can lead to bad results if the ATM peer loses state and -+ changes its encapsulation unilaterally. -+ -+config PPPOL2TP -+ tristate "PPP over L2TP (EXPERIMENTAL)" -+ depends on EXPERIMENTAL && L2TP && PPP -+ help -+ Support for PPP-over-L2TP socket family. L2TP is a protocol -+ used by ISPs and enterprises to tunnel PPP traffic over UDP -+ tunnels. L2TP is replacing PPTP for VPN uses. -+ -+config SLIP -+ tristate "SLIP (serial line) support" -+ ---help--- -+ Say Y if you intend to use SLIP or CSLIP (compressed SLIP) to -+ connect to your Internet service provider or to connect to some -+ other local Unix box or if you want to configure your Linux box as a -+ Slip/CSlip server for other people to dial in. SLIP (Serial Line -+ Internet Protocol) is a protocol used to send Internet traffic over -+ serial connections such as telephone lines or null modem cables; -+ nowadays, the protocol PPP is more commonly used for this same -+ purpose. -+ -+ Normally, your access provider has to support SLIP in order for you -+ to be able to use it, but there is now a SLIP emulator called SLiRP -+ around (available from -+ ) which -+ allows you to use SLIP over a regular dial up shell connection. If -+ you plan to use SLiRP, make sure to say Y to CSLIP, below. The -+ NET-3-HOWTO, available from -+ , explains how to -+ configure SLIP. Note that you don't need this option if you just -+ want to run term (term is a program which gives you almost full -+ Internet connectivity if you have a regular dial up shell account on -+ some Internet connected Unix computer. Read -+ ). SLIP -+ support will enlarge your kernel by about 4 KB. If unsure, say N. -+ -+ To compile this driver as a module, choose M here. The module -+ will be called slip. -+ -+config SLIP_COMPRESSED -+ bool "CSLIP compressed headers" -+ depends on SLIP -+ select SLHC -+ ---help--- -+ This protocol is faster than SLIP because it uses compression on the -+ TCP/IP headers (not on the data itself), but it has to be supported -+ on both ends. Ask your access provider if you are not sure and -+ answer Y, just in case. You will still be able to use plain SLIP. If -+ you plan to use SLiRP, the SLIP emulator (available from -+ ) which -+ allows you to use SLIP over a regular dial up shell connection, you -+ definitely want to say Y here. The NET-3-HOWTO, available from -+ , explains how to configure -+ CSLIP. This won't enlarge your kernel. -+ -+config SLHC -+ tristate -+ help -+ This option enables Van Jacobsen serial line header compression -+ routines. ++ return irq; ++} + -+config SLIP_SMART -+ bool "Keepalive and linefill" -+ depends on SLIP -+ help -+ Adds additional capabilities to the SLIP driver to support the -+ RELCOM line fill and keepalive monitoring. Ideal on poor quality -+ analogue lines. ++static struct pci_ops ar724x_pci_ops = { ++ .read = ar724x_pci_read_config, ++ .write = ar724x_pci_write_config, ++}; + -+config SLIP_MODE_SLIP6 -+ bool "Six bit SLIP encapsulation" -+ depends on SLIP -+ help -+ Just occasionally you may need to run IP over hostile serial -+ networks that don't pass all control characters or are only seven -+ bit. Saying Y here adds an extra mode you can use with SLIP: -+ "slip6". In this mode, SLIP will only send normal ASCII symbols over -+ the serial device. Naturally, this has to be supported at the other -+ end of the link as well. It's good enough, for example, to run IP -+ over the async ports of a Camtec JNT Pad. If unsure, say N. -+ -+config NET_FC -+ bool "Fibre Channel driver support" -+ depends on SCSI && PCI -+ help -+ Fibre Channel is a high speed serial protocol mainly used to connect -+ large storage devices to the computer; it is compatible with and -+ intended to replace SCSI. -+ -+ If you intend to use Fibre Channel, you need to have a Fibre channel -+ adaptor card in your computer; say Y here and to the driver for your -+ adaptor below. You also should have said Y to "SCSI support" and -+ "SCSI generic support". -+ -+config NETCONSOLE -+ tristate "Network console logging support" -+ ---help--- -+ If you want to log kernel messages over the network, enable this. -+ See for details. -+ -+config NETCONSOLE_DYNAMIC -+ bool "Dynamic reconfiguration of logging targets" -+ depends on NETCONSOLE && SYSFS -+ select CONFIGFS_FS -+ help -+ This option enables the ability to dynamically reconfigure target -+ parameters (interface, IP addresses, port numbers, MAC addresses) -+ at runtime through a userspace interface exported using configfs. -+ See for details. ++static struct resource ar724x_pci_io_resource = { ++ .name = "PCI IO space", ++ .start = 0, ++ .end = 0, ++ .flags = IORESOURCE_IO, ++}; + -+config NETPOLL -+ def_bool NETCONSOLE ++static struct resource ar724x_pci_mem_resource = { ++ .name = "PCI memory space", ++ .start = AR71XX_PCI_MEM_BASE, ++ .end = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1, ++ .flags = IORESOURCE_MEM ++}; + -+config NETPOLL_TRAP -+ bool "Netpoll traffic trapping" -+ default n -+ depends on NETPOLL -+ -+config NET_POLL_CONTROLLER -+ def_bool NETPOLL -+ -+config VIRTIO_NET -+ tristate "Virtio network driver (EXPERIMENTAL)" -+ depends on EXPERIMENTAL && VIRTIO -+ ---help--- -+ This is the virtual network driver for virtio. It can be used with -+ lguest or QEMU based VMMs (like KVM or Xen). Say Y or M. -+ -+config VMXNET3 -+ tristate "VMware VMXNET3 ethernet driver" -+ depends on PCI && INET -+ help -+ This driver supports VMware's vmxnet3 virtual ethernet NIC. -+ To compile this driver as a module, choose M here: the -+ module will be called vmxnet3. -+ -+endif # NETDEVICES -diff -Nur linux-2.6.35.7.orig/drivers/net/Makefile linux-2.6.35.7/drivers/net/Makefile ---- linux-2.6.35.7.orig/drivers/net/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/net/Makefile 2010-10-14 20:28:00.878101155 +0200 -@@ -109,6 +109,7 @@ - # end link order section - # - -+obj-$(CONFIG_AG71XX) += ag71xx/ - obj-$(CONFIG_SUNDANCE) += sundance.o - obj-$(CONFIG_HAMACHI) += hamachi.o - obj-$(CONFIG_NET) += Space.o loopback.o -diff -Nur linux-2.6.35.7.orig/drivers/net/phy/Kconfig linux-2.6.35.7/drivers/net/phy/Kconfig ---- linux-2.6.35.7.orig/drivers/net/phy/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/net/phy/Kconfig 2010-10-14 20:28:00.918101155 +0200 -@@ -93,6 +93,10 @@ - ---help--- - Supports the KSZ9021, VSC8201, KS8001 PHYs. - -+config IP175C_PHY -+ tristate "Driver for IC+ IP175C/IP178C switches" -+ select SWCONFIG ++static struct pci_controller ar724x_pci_controller = { ++ .pci_ops = &ar724x_pci_ops, ++ .mem_resource = &ar724x_pci_mem_resource, ++ .io_resource = &ar724x_pci_io_resource, ++}; + - config FIXED_PHY - bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" - depends on PHYLIB=y -diff -Nur linux-2.6.35.7.orig/drivers/net/phy/phy.c linux-2.6.35.7/drivers/net/phy/phy.c ---- linux-2.6.35.7.orig/drivers/net/phy/phy.c 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/net/phy/phy.c 2010-10-14 20:28:00.948101153 +0200 -@@ -298,6 +298,50 @@ - } - EXPORT_SYMBOL(phy_ethtool_gset); - -+int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) ++static void __init ar724x_pci_reset(void) +{ -+ u32 cmd; -+ int tmp; -+ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; -+ struct ethtool_value edata = { ETHTOOL_GLINK }; ++ ar71xx_device_stop(AR724X_RESET_PCIE); ++ ar71xx_device_stop(AR724X_RESET_PCIE_PHY); ++ ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL); ++ udelay(100); + -+ if (get_user(cmd, (u32 *) useraddr)) -+ return -EFAULT; ++ ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL); ++ udelay(100); ++ ar71xx_device_start(AR724X_RESET_PCIE_PHY); ++ ar71xx_device_start(AR724X_RESET_PCIE); ++} + -+ switch (cmd) { -+ case ETHTOOL_GSET: -+ phy_ethtool_gset(phydev, &ecmd); -+ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) -+ return -EFAULT; -+ return 0; ++static int __init ar724x_pci_setup(void) ++{ ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 t; + -+ case ETHTOOL_SSET: -+ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) -+ return -EFAULT; -+ return phy_ethtool_sset(phydev, &ecmd); ++ /* setup COMMAND register */ ++ t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE | ++ PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK; + -+ case ETHTOOL_NWAY_RST: -+ /* if autoneg is off, it's an error */ -+ tmp = phy_read(phydev, MII_BMCR); -+ if (tmp & BMCR_ANENABLE) { -+ tmp |= (BMCR_ANRESTART); -+ phy_write(phydev, MII_BMCR, tmp); -+ return 0; -+ } -+ return -EINVAL; ++ ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t); ++ ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000); ++ ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000); + -+ case ETHTOOL_GLINK: -+ edata.data = (phy_read(phydev, -+ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; -+ if (copy_to_user(useraddr, &edata, sizeof(edata))) -+ return -EFAULT; -+ return 0; ++ t = __raw_readl(base + AR724X_PCI_REG_RESET); ++ if (t != 0x7) { ++ udelay(100000); ++ __raw_writel(0, base + AR724X_PCI_REG_RESET); ++ udelay(100); ++ __raw_writel(4, base + AR724X_PCI_REG_RESET); ++ udelay(100000); + } + -+ return -EOPNOTSUPP; -+} -+EXPORT_SYMBOL(phy_ethtool_ioctl); ++ if (ar71xx_soc == AR71XX_SOC_AR7240) ++ t = AR724X_PCI_APP_LTSSM_ENABLE; ++ else ++ t = 0x1ffc1; ++ __raw_writel(t, base + AR724X_PCI_REG_APP); ++ /* flush write */ ++ (void) __raw_readl(base + AR724X_PCI_REG_APP); ++ udelay(1000); + - /** - * phy_mii_ioctl - generic PHY MII ioctl interface - * @phydev: the phy_device struct -@@ -351,7 +395,7 @@ - } - - phy_write(phydev, mii_data->reg_num, val); -- ++ t = __raw_readl(base + AR724X_PCI_REG_RESET); ++ if ((t & AR724X_PCI_RESET_LINK_UP) == 0x0) { ++ printk(KERN_WARNING "PCI: no PCIe module found\n"); ++ return -ENODEV; ++ } + - if (mii_data->reg_num == MII_BMCR && - val & BMCR_RESET && - phydev->drv->config_init) { -@@ -465,7 +509,7 @@ - int idx; - - idx = phy_find_setting(phydev->speed, phydev->duplex); -- ++ if (ar71xx_soc == AR71XX_SOC_AR7241 || ar71xx_soc == AR71XX_SOC_AR7242) { ++ t = __raw_readl(base + AR724X_PCI_REG_APP); ++ t |= BIT(16); ++ __raw_writel(t, base + AR724X_PCI_REG_APP); ++ } + - idx++; - - idx = phy_find_valid(idx, phydev->supported); -diff -Nur linux-2.6.35.7.orig/drivers/net/phy/phy_device.c linux-2.6.35.7/drivers/net/phy/phy_device.c ---- linux-2.6.35.7.orig/drivers/net/phy/phy_device.c 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/net/phy/phy_device.c 2010-10-14 20:28:01.005039092 +0200 -@@ -146,6 +146,18 @@ - } - EXPORT_SYMBOL(phy_scan_fixups); - -+static int generic_receive_skb(struct sk_buff *skb) -+{ -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ return netif_receive_skb(skb); ++ return 0; +} + -+static int generic_rx(struct sk_buff *skb) ++static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc) +{ -+ skb->protocol = eth_type_trans(skb, skb->dev); -+ return netif_rx(skb); -+} -+ - struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id) - { - struct phy_device *dev; -@@ -176,6 +188,8 @@ - dev_set_name(&dev->dev, PHY_ID_FMT, bus->id, addr); - - dev->state = PHY_DOWN; -+ dev->netif_receive_skb = &generic_receive_skb; -+ dev->netif_rx = &generic_rx; - - mutex_init(&dev->lock); - INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); -diff -Nur linux-2.6.35.7.orig/drivers/net/phy/phy_device.c.orig linux-2.6.35.7/drivers/net/phy/phy_device.c.orig ---- linux-2.6.35.7.orig/drivers/net/phy/phy_device.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/net/phy/phy_device.c.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,1041 @@ -+/* -+ * drivers/net/phy/phy_device.c -+ * -+ * Framework for finding and configuring PHYs. -+ * Also contains generic PHY driver -+ * -+ * Author: Andy Fleming -+ * -+ * Copyright (c) 2004 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 pending; + -+#include -+#include -+#include ++ pending = __raw_readl(base + AR724X_PCI_REG_INT_STATUS) & ++ __raw_readl(base + AR724X_PCI_REG_INT_MASK); + -+MODULE_DESCRIPTION("PHY library"); -+MODULE_AUTHOR("Andy Fleming"); -+MODULE_LICENSE("GPL"); ++ if (pending & AR724X_PCI_INT_DEV0) ++ generic_handle_irq(AR71XX_PCI_IRQ_DEV0); + -+void phy_device_free(struct phy_device *phydev) -+{ -+ kfree(phydev); ++ else ++ spurious_interrupt(); +} -+EXPORT_SYMBOL(phy_device_free); + -+static void phy_device_release(struct device *dev) ++static void ar724x_pci_irq_unmask(unsigned int irq) +{ -+ phy_device_free(to_phy_device(dev)); -+} ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 t; + -+static struct phy_driver genphy_driver; -+extern int mdio_bus_init(void); -+extern void mdio_bus_exit(void); ++ switch (irq) { ++ case AR71XX_PCI_IRQ_DEV0: ++ irq -= AR71XX_PCI_IRQ_BASE; + -+static LIST_HEAD(phy_fixup_list); -+static DEFINE_MUTEX(phy_fixup_lock); ++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(t | AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_MASK); ++ /* flush write */ ++ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ } ++} + -+/* -+ * Creates a new phy_fixup and adds it to the list -+ * @bus_id: A string which matches phydev->dev.bus_id (or PHY_ANY_ID) -+ * @phy_uid: Used to match against phydev->phy_id (the UID of the PHY) -+ * It can also be PHY_ANY_UID -+ * @phy_uid_mask: Applied to phydev->phy_id and fixup->phy_uid before -+ * comparison -+ * @run: The actual code to be run when a matching PHY is found -+ */ -+int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask, -+ int (*run)(struct phy_device *)) ++static void ar724x_pci_irq_mask(unsigned int irq) +{ -+ struct phy_fixup *fixup; ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 t; + -+ fixup = kzalloc(sizeof(struct phy_fixup), GFP_KERNEL); -+ if (!fixup) -+ return -ENOMEM; ++ switch (irq) { ++ case AR71XX_PCI_IRQ_DEV0: ++ irq -= AR71XX_PCI_IRQ_BASE; + -+ strlcpy(fixup->bus_id, bus_id, sizeof(fixup->bus_id)); -+ fixup->phy_uid = phy_uid; -+ fixup->phy_uid_mask = phy_uid_mask; -+ fixup->run = run; ++ t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(t & ~AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_MASK); + -+ mutex_lock(&phy_fixup_lock); -+ list_add_tail(&fixup->list, &phy_fixup_list); -+ mutex_unlock(&phy_fixup_lock); ++ /* flush write */ ++ (void) __raw_readl(base + AR724X_PCI_REG_INT_MASK); + -+ return 0; -+} -+EXPORT_SYMBOL(phy_register_fixup); ++ t = __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ++ __raw_writel(t | AR724X_PCI_INT_DEV0, ++ base + AR724X_PCI_REG_INT_STATUS); + -+/* Registers a fixup to be run on any PHY with the UID in phy_uid */ -+int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask, -+ int (*run)(struct phy_device *)) -+{ -+ return phy_register_fixup(PHY_ANY_ID, phy_uid, phy_uid_mask, run); ++ /* flush write */ ++ (void) __raw_readl(base + AR724X_PCI_REG_INT_STATUS); ++ } +} -+EXPORT_SYMBOL(phy_register_fixup_for_uid); + -+/* Registers a fixup to be run on the PHY with id string bus_id */ -+int phy_register_fixup_for_id(const char *bus_id, -+ int (*run)(struct phy_device *)) -+{ -+ return phy_register_fixup(bus_id, PHY_ANY_UID, 0xffffffff, run); -+} -+EXPORT_SYMBOL(phy_register_fixup_for_id); ++static struct irq_chip ar724x_pci_irq_chip = { ++ .name = "AR724X PCI ", ++ .mask = ar724x_pci_irq_mask, ++ .unmask = ar724x_pci_irq_unmask, ++ .mask_ack = ar724x_pci_irq_mask, ++}; + -+/* -+ * Returns 1 if fixup matches phydev in bus_id and phy_uid. -+ * Fixups can be set to match any in one or more fields. -+ */ -+static int phy_needs_fixup(struct phy_device *phydev, struct phy_fixup *fixup) ++static void __init ar724x_pci_irq_init(void) +{ -+ if (strcmp(fixup->bus_id, dev_name(&phydev->dev)) != 0) -+ if (strcmp(fixup->bus_id, PHY_ANY_ID) != 0) -+ return 0; ++ void __iomem *base = ar724x_pci_ctrl_base; ++ u32 t; ++ int i; + -+ if ((fixup->phy_uid & fixup->phy_uid_mask) != -+ (phydev->phy_id & fixup->phy_uid_mask)) -+ if (fixup->phy_uid != PHY_ANY_UID) -+ return 0; ++ t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE); ++ if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY | ++ AR724X_RESET_PCIE_PHY_SERIAL)) { ++ return; ++ } + -+ return 1; ++ __raw_writel(0, base + AR724X_PCI_REG_INT_MASK); ++ __raw_writel(0, base + AR724X_PCI_REG_INT_STATUS); ++ ++ for (i = AR71XX_PCI_IRQ_BASE; ++ i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) { ++ irq_desc[i].status = IRQ_DISABLED; ++ set_irq_chip_and_handler(i, &ar724x_pci_irq_chip, ++ handle_level_irq); ++ } ++ ++ set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler); +} + -+/* Runs any matching fixups for this phydev */ -+int phy_scan_fixups(struct phy_device *phydev) ++int __init ar724x_pcibios_init(void) +{ -+ struct phy_fixup *fixup; ++ int ret = -ENOMEM; + -+ mutex_lock(&phy_fixup_lock); -+ list_for_each_entry(fixup, &phy_fixup_list, list) { -+ if (phy_needs_fixup(phydev, fixup)) { -+ int err; ++ ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE, ++ AR724X_PCI_CRP_SIZE); ++ if (ar724x_pci_localcfg_base == NULL) ++ goto err; + -+ err = fixup->run(phydev); ++ ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE, ++ AR724X_PCI_CFG_SIZE); ++ if (ar724x_pci_devcfg_base == NULL) ++ goto err_unmap_localcfg; + -+ if (err < 0) { -+ mutex_unlock(&phy_fixup_lock); -+ return err; -+ } -+ } -+ } -+ mutex_unlock(&phy_fixup_lock); ++ ar724x_pci_ctrl_base = ioremap_nocache(AR724X_PCI_CTRL_BASE, ++ AR724X_PCI_CTRL_SIZE); ++ if (ar724x_pci_ctrl_base == NULL) ++ goto err_unmap_devcfg; ++ ++ ar724x_pci_reset(); ++ ret = ar724x_pci_setup(); ++ if (ret) ++ goto err_unmap_ctrl; ++ ++ ar724x_pci_fixup_enable = 1; ++ ar724x_pci_irq_init(); ++ register_pci_controller(&ar724x_pci_controller); + + return 0; ++ ++ err_unmap_ctrl: ++ iounmap(ar724x_pci_ctrl_base); ++ err_unmap_devcfg: ++ iounmap(ar724x_pci_devcfg_base); ++ err_unmap_localcfg: ++ iounmap(ar724x_pci_localcfg_base); ++ err: ++ return ret; +} -+EXPORT_SYMBOL(phy_scan_fixups); +diff -Nur linux-2.6.36.orig/drivers/char/Kconfig linux-2.6.36/drivers/char/Kconfig +--- linux-2.6.36.orig/drivers/char/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/char/Kconfig 2010-11-18 21:16:07.000000000 +0100 +@@ -1032,6 +1032,14 @@ + + If compiled as a module, it will be called cs5535_gpio. + ++config GPIO_DEVICE ++ tristate "GPIO device support" ++ depends on GENERIC_GPIO ++ help ++ Say Y to enable Linux GPIO device support. This allows control of ++ GPIO pins using a character device + -+struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id) -+{ -+ struct phy_device *dev; + -+ /* We allocate the device, and initialize the -+ * default values */ -+ dev = kzalloc(sizeof(*dev), GFP_KERNEL); + config RAW_DRIVER + tristate "RAW driver (/dev/raw/rawN)" + depends on BLOCK +diff -Nur linux-2.6.36.orig/drivers/char/Makefile linux-2.6.36/drivers/char/Makefile +--- linux-2.6.36.orig/drivers/char/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/char/Makefile 2010-11-18 21:16:07.000000000 +0100 +@@ -98,6 +98,7 @@ + obj-$(CONFIG_PC8736x_GPIO) += pc8736x_gpio.o + obj-$(CONFIG_NSC_GPIO) += nsc_gpio.o + obj-$(CONFIG_CS5535_GPIO) += cs5535_gpio.o ++obj-$(CONFIG_GPIO_DEVICE) += gpio_dev.o + obj-$(CONFIG_GPIO_TB0219) += tb0219.o + obj-$(CONFIG_TELCLOCK) += tlclk.o + +diff -Nur linux-2.6.36.orig/drivers/gpio/nxp_74hc153.c linux-2.6.36/drivers/gpio/nxp_74hc153.c +--- linux-2.6.36.orig/drivers/gpio/nxp_74hc153.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/gpio/nxp_74hc153.c 2010-11-18 21:16:11.000000000 +0100 +@@ -0,0 +1,246 @@ ++/* ++ * NXP 74HC153 - Dual 4-input multiplexer GPIO driver ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#define NXP_74HC153_NUM_GPIOS 8 ++#define NXP_74HC153_S0_MASK 0x1 ++#define NXP_74HC153_S1_MASK 0x2 ++#define NXP_74HC153_BANK_MASK 0x4 + -+ if (NULL == dev) -+ return (struct phy_device*) PTR_ERR((void*)-ENOMEM); ++struct nxp_74hc153_chip { ++ struct device *parent; ++ struct gpio_chip gpio_chip; ++ struct mutex lock; ++}; + -+ dev->dev.release = phy_device_release; ++static struct nxp_74hc153_chip *gpio_to_nxp(struct gpio_chip *gc) ++{ ++ return container_of(gc, struct nxp_74hc153_chip, gpio_chip); ++} + -+ dev->speed = 0; -+ dev->duplex = -1; -+ dev->pause = dev->asym_pause = 0; -+ dev->link = 1; -+ dev->interface = PHY_INTERFACE_MODE_GMII; ++static int nxp_74hc153_direction_input(struct gpio_chip *gc, unsigned offset) ++{ ++ return 0; ++} + -+ dev->autoneg = AUTONEG_ENABLE; ++static int nxp_74hc153_direction_output(struct gpio_chip *gc, ++ unsigned offset, int val) ++{ ++ return -EINVAL; ++} + -+ dev->addr = addr; -+ dev->phy_id = phy_id; -+ dev->bus = bus; -+ dev->dev.parent = bus->parent; -+ dev->dev.bus = &mdio_bus_type; -+ dev->irq = bus->irq != NULL ? bus->irq[addr] : PHY_POLL; -+ dev_set_name(&dev->dev, PHY_ID_FMT, bus->id, addr); ++static int nxp_74hc153_get_value(struct gpio_chip *gc, unsigned offset) ++{ ++ struct nxp_74hc153_chip *nxp; ++ struct nxp_74hc153_platform_data *pdata; ++ unsigned s0; ++ unsigned s1; ++ unsigned pin; ++ int ret; + -+ dev->state = PHY_DOWN; ++ nxp = gpio_to_nxp(gc); ++ pdata = nxp->parent->platform_data; + -+ mutex_init(&dev->lock); -+ INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); ++ s0 = !!(offset & NXP_74HC153_S0_MASK); ++ s1 = !!(offset & NXP_74HC153_S1_MASK); ++ pin = (offset & NXP_74HC153_BANK_MASK) ? pdata->gpio_pin_2y ++ : pdata->gpio_pin_1y; + -+ /* Request the appropriate module unconditionally; don't -+ bother trying to do so only if it isn't already loaded, -+ because that gets complicated. A hotplug event would have -+ done an unconditional modprobe anyway. -+ We don't do normal hotplug because it won't work for MDIO -+ -- because it relies on the device staying around for long -+ enough for the driver to get loaded. With MDIO, the NIC -+ driver will get bored and give up as soon as it finds that -+ there's no driver _already_ loaded. */ -+ request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT, MDIO_ID_ARGS(phy_id)); ++ mutex_lock(&nxp->lock); ++ gpio_set_value(pdata->gpio_pin_s0, s0); ++ gpio_set_value(pdata->gpio_pin_s1, s1); ++ ret = gpio_get_value(pin); ++ mutex_unlock(&nxp->lock); + -+ return dev; ++ return ret; +} -+EXPORT_SYMBOL(phy_device_create); + -+/** -+ * get_phy_id - reads the specified addr for its ID. -+ * @bus: the target MII bus -+ * @addr: PHY address on the MII bus -+ * @phy_id: where to store the ID retrieved. -+ * -+ * Description: Reads the ID registers of the PHY at @addr on the -+ * @bus, stores it in @phy_id and returns zero on success. -+ */ -+int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id) ++static void nxp_74hc153_set_value(struct gpio_chip *gc, ++ unsigned offset, int val) +{ -+ int phy_reg; ++ /* not supported */ ++} + -+ /* Grab the bits from PHYIR1, and put them -+ * in the upper half */ -+ phy_reg = bus->read(bus, addr, MII_PHYSID1); ++static int __devinit nxp_74hc153_probe(struct platform_device *pdev) ++{ ++ struct nxp_74hc153_platform_data *pdata; ++ struct nxp_74hc153_chip *nxp; ++ struct gpio_chip *gc; ++ int err; + -+ if (phy_reg < 0) -+ return -EIO; ++ pdata = pdev->dev.platform_data; ++ if (pdata == NULL) { ++ dev_dbg(&pdev->dev, "no platform data specified\n"); ++ return -EINVAL; ++ } + -+ *phy_id = (phy_reg & 0xffff) << 16; ++ nxp = kzalloc(sizeof(struct nxp_74hc153_chip), GFP_KERNEL); ++ if (nxp == NULL) { ++ dev_err(&pdev->dev, "no memory for private data\n"); ++ return -ENOMEM; ++ } + -+ /* Grab the bits from PHYIR2, and put them in the lower half */ -+ phy_reg = bus->read(bus, addr, MII_PHYSID2); ++ err = gpio_request(pdata->gpio_pin_s0, dev_name(&pdev->dev)); ++ if (err) { ++ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", ++ pdata->gpio_pin_s0, err); ++ goto err_free_nxp; ++ } + -+ if (phy_reg < 0) -+ return -EIO; ++ err = gpio_request(pdata->gpio_pin_s1, dev_name(&pdev->dev)); ++ if (err) { ++ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", ++ pdata->gpio_pin_s1, err); ++ goto err_free_s0; ++ } + -+ *phy_id |= (phy_reg & 0xffff); ++ err = gpio_request(pdata->gpio_pin_1y, dev_name(&pdev->dev)); ++ if (err) { ++ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", ++ pdata->gpio_pin_1y, err); ++ goto err_free_s1; ++ } + -+ return 0; -+} -+EXPORT_SYMBOL(get_phy_id); ++ err = gpio_request(pdata->gpio_pin_2y, dev_name(&pdev->dev)); ++ if (err) { ++ dev_err(&pdev->dev, "unable to claim gpio %u, err=%d\n", ++ pdata->gpio_pin_2y, err); ++ goto err_free_1y; ++ } + -+/** -+ * get_phy_device - reads the specified PHY device and returns its @phy_device struct -+ * @bus: the target MII bus -+ * @addr: PHY address on the MII bus -+ * -+ * Description: Reads the ID registers of the PHY at @addr on the -+ * @bus, then allocates and returns the phy_device to represent it. -+ */ -+struct phy_device * get_phy_device(struct mii_bus *bus, int addr) -+{ -+ struct phy_device *dev = NULL; -+ u32 phy_id; -+ int r; ++ err = gpio_direction_output(pdata->gpio_pin_s0, 0); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to set direction of gpio %u, err=%d\n", ++ pdata->gpio_pin_s0, err); ++ goto err_free_2y; ++ } + -+ r = get_phy_id(bus, addr, &phy_id); -+ if (r) -+ return ERR_PTR(r); ++ err = gpio_direction_output(pdata->gpio_pin_s1, 0); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to set direction of gpio %u, err=%d\n", ++ pdata->gpio_pin_s1, err); ++ goto err_free_2y; ++ } + -+ /* If the phy_id is mostly Fs, there is no device there */ -+ if ((phy_id & 0x1fffffff) == 0x1fffffff) -+ return NULL; ++ err = gpio_direction_input(pdata->gpio_pin_1y); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to set direction of gpio %u, err=%d\n", ++ pdata->gpio_pin_1y, err); ++ goto err_free_2y; ++ } + -+ dev = phy_device_create(bus, addr, phy_id); ++ err = gpio_direction_input(pdata->gpio_pin_2y); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to set direction of gpio %u, err=%d\n", ++ pdata->gpio_pin_2y, err); ++ goto err_free_2y; ++ } + -+ return dev; -+} -+EXPORT_SYMBOL(get_phy_device); ++ nxp->parent = &pdev->dev; ++ mutex_init(&nxp->lock); + -+/** -+ * phy_device_register - Register the phy device on the MDIO bus -+ * @phydev: phy_device structure to be added to the MDIO bus -+ */ -+int phy_device_register(struct phy_device *phydev) -+{ -+ int err; ++ gc = &nxp->gpio_chip; + -+ /* Don't register a phy if one is already registered at this -+ * address */ -+ if (phydev->bus->phy_map[phydev->addr]) -+ return -EINVAL; -+ phydev->bus->phy_map[phydev->addr] = phydev; ++ gc->direction_input = nxp_74hc153_direction_input; ++ gc->direction_output = nxp_74hc153_direction_output; ++ gc->get = nxp_74hc153_get_value; ++ gc->set = nxp_74hc153_set_value; ++ gc->can_sleep = 1; + -+ /* Run all of the fixups for this PHY */ -+ phy_scan_fixups(phydev); ++ gc->base = pdata->gpio_base; ++ gc->ngpio = NXP_74HC153_NUM_GPIOS; ++ gc->label = dev_name(nxp->parent); ++ gc->dev = nxp->parent; ++ gc->owner = THIS_MODULE; + -+ err = device_register(&phydev->dev); ++ err = gpiochip_add(&nxp->gpio_chip); + if (err) { -+ pr_err("phy %d failed to register\n", phydev->addr); -+ goto out; ++ dev_err(&pdev->dev, "unable to add gpio chip, err=%d\n", err); ++ goto err_free_2y; + } + ++ platform_set_drvdata(pdev, nxp); + return 0; + -+ out: -+ phydev->bus->phy_map[phydev->addr] = NULL; ++ err_free_2y: ++ gpio_free(pdata->gpio_pin_2y); ++ err_free_1y: ++ gpio_free(pdata->gpio_pin_1y); ++ err_free_s1: ++ gpio_free(pdata->gpio_pin_s1); ++ err_free_s0: ++ gpio_free(pdata->gpio_pin_s0); ++ err_free_nxp: ++ kfree(nxp); + return err; +} -+EXPORT_SYMBOL(phy_device_register); + -+/** -+ * phy_find_first - finds the first PHY device on the bus -+ * @bus: the target MII bus -+ */ -+struct phy_device *phy_find_first(struct mii_bus *bus) ++static int nxp_74hc153_remove(struct platform_device *pdev) +{ -+ int addr; -+ -+ for (addr = 0; addr < PHY_MAX_ADDR; addr++) { -+ if (bus->phy_map[addr]) -+ return bus->phy_map[addr]; -+ } -+ return NULL; -+} -+EXPORT_SYMBOL(phy_find_first); ++ struct nxp_74hc153_chip *nxp = platform_get_drvdata(pdev); ++ struct nxp_74hc153_platform_data *pdata = pdev->dev.platform_data; + -+/** -+ * phy_prepare_link - prepares the PHY layer to monitor link status -+ * @phydev: target phy_device struct -+ * @handler: callback function for link status change notifications -+ * -+ * Description: Tells the PHY infrastructure to handle the -+ * gory details on monitoring link status (whether through -+ * polling or an interrupt), and to call back to the -+ * connected device driver when the link status changes. -+ * If you want to monitor your own link state, don't call -+ * this function. -+ */ -+void phy_prepare_link(struct phy_device *phydev, -+ void (*handler)(struct net_device *)) -+{ -+ phydev->adjust_link = handler; -+} ++ if (nxp) { ++ int err; + -+/** -+ * phy_connect_direct - connect an ethernet device to a specific phy_device -+ * @dev: the network device to connect -+ * @phydev: the pointer to the phy device -+ * @handler: callback function for state change notifications -+ * @flags: PHY device's dev_flags -+ * @interface: PHY device's interface -+ */ -+int phy_connect_direct(struct net_device *dev, struct phy_device *phydev, -+ void (*handler)(struct net_device *), u32 flags, -+ phy_interface_t interface) -+{ -+ int rc; ++ err = gpiochip_remove(&nxp->gpio_chip); ++ if (err) { ++ dev_err(&pdev->dev, ++ "unable to remove gpio chip, err=%d\n", ++ err); ++ return err; ++ } + -+ rc = phy_attach_direct(dev, phydev, flags, interface); -+ if (rc) -+ return rc; ++ gpio_free(pdata->gpio_pin_2y); ++ gpio_free(pdata->gpio_pin_1y); ++ gpio_free(pdata->gpio_pin_s1); ++ gpio_free(pdata->gpio_pin_s0); + -+ phy_prepare_link(phydev, handler); -+ phy_start_machine(phydev, NULL); -+ if (phydev->irq > 0) -+ phy_start_interrupts(phydev); ++ kfree(nxp); ++ platform_set_drvdata(pdev, NULL); ++ } + + return 0; +} -+EXPORT_SYMBOL(phy_connect_direct); -+ -+/** -+ * phy_connect - connect an ethernet device to a PHY device -+ * @dev: the network device to connect -+ * @bus_id: the id string of the PHY device to connect -+ * @handler: callback function for state change notifications -+ * @flags: PHY device's dev_flags -+ * @interface: PHY device's interface -+ * -+ * Description: Convenience function for connecting ethernet -+ * devices to PHY devices. The default behavior is for -+ * the PHY infrastructure to handle everything, and only notify -+ * the connected driver when the link status changes. If you -+ * don't want, or can't use the provided functionality, you may -+ * choose to call only the subset of functions which provide -+ * the desired functionality. -+ */ -+struct phy_device * phy_connect(struct net_device *dev, const char *bus_id, -+ void (*handler)(struct net_device *), u32 flags, -+ phy_interface_t interface) -+{ -+ struct phy_device *phydev; -+ struct device *d; -+ int rc; -+ -+ /* Search the list of PHY devices on the mdio bus for the -+ * PHY with the requested name */ -+ d = bus_find_device_by_name(&mdio_bus_type, NULL, bus_id); -+ if (!d) { -+ pr_err("PHY %s not found\n", bus_id); -+ return ERR_PTR(-ENODEV); -+ } -+ phydev = to_phy_device(d); + -+ rc = phy_connect_direct(dev, phydev, handler, flags, interface); -+ if (rc) -+ return ERR_PTR(rc); -+ -+ return phydev; -+} -+EXPORT_SYMBOL(phy_connect); ++static struct platform_driver nxp_74hc153_driver = { ++ .probe = nxp_74hc153_probe, ++ .remove = __devexit_p(nxp_74hc153_remove), ++ .driver = { ++ .name = NXP_74HC153_DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; + -+/** -+ * phy_disconnect - disable interrupts, stop state machine, and detach a PHY device -+ * @phydev: target phy_device struct -+ */ -+void phy_disconnect(struct phy_device *phydev) ++static int __init nxp_74hc153_init(void) +{ -+ if (phydev->irq > 0) -+ phy_stop_interrupts(phydev); -+ -+ phy_stop_machine(phydev); -+ -+ phydev->adjust_link = NULL; -+ -+ phy_detach(phydev); ++ return platform_driver_register(&nxp_74hc153_driver); +} -+EXPORT_SYMBOL(phy_disconnect); ++subsys_initcall(nxp_74hc153_init); + -+int phy_init_hw(struct phy_device *phydev) ++static void __exit nxp_74hc153_exit(void) +{ -+ int ret; -+ -+ if (!phydev->drv || !phydev->drv->config_init) -+ return 0; -+ -+ ret = phy_scan_fixups(phydev); -+ if (ret < 0) -+ return ret; -+ -+ return phydev->drv->config_init(phydev); ++ platform_driver_unregister(&nxp_74hc153_driver); +} ++module_exit(nxp_74hc153_exit); + -+/** -+ * phy_attach_direct - attach a network device to a given PHY device pointer -+ * @dev: network device to attach -+ * @phydev: Pointer to phy_device to attach -+ * @flags: PHY device's dev_flags -+ * @interface: PHY device's interface -+ * -+ * Description: Called by drivers to attach to a particular PHY -+ * device. The phy_device is found, and properly hooked up -+ * to the phy_driver. If no driver is attached, then the -+ * genphy_driver is used. The phy_device is given a ptr to -+ * the attaching device, and given a callback for link status -+ * change. The phy_device is returned to the attaching driver. -+ */ -+int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, -+ u32 flags, phy_interface_t interface) -+{ -+ struct device *d = &phydev->dev; -+ -+ /* Assume that if there is no driver, that it doesn't -+ * exist, and we should use the genphy driver. */ -+ if (NULL == d->driver) { -+ int err; -+ d->driver = &genphy_driver.driver; -+ -+ err = d->driver->probe(d); -+ if (err >= 0) -+ err = device_bind_driver(d); -+ -+ if (err) -+ return err; -+ } -+ -+ if (phydev->attached_dev) { -+ dev_err(&dev->dev, "PHY already attached\n"); -+ return -EBUSY; -+ } -+ -+ phydev->attached_dev = dev; -+ -+ phydev->dev_flags = flags; ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_DESCRIPTION("GPIO expander driver for NXP 74HC153"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" NXP_74HC153_DRIVER_NAME); +diff -Nur linux-2.6.36.orig/drivers/input/misc/Kconfig linux-2.6.36/drivers/input/misc/Kconfig +--- linux-2.6.36.orig/drivers/input/misc/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/input/misc/Kconfig 2010-11-18 21:16:11.000000000 +0100 +@@ -438,4 +438,20 @@ + To compile this driver as a module, choose M here: the + module will be called adxl34x-spi. + ++config INPUT_GPIO_BUTTONS ++ tristate "Polled GPIO buttons interface" ++ depends on GENERIC_GPIO ++ select INPUT_POLLDEV ++ help ++ This driver implements support for buttons connected ++ to GPIO pins of various CPUs (and some other chips). + -+ phydev->interface = interface; ++ Say Y here if your device has buttons connected ++ directly to such GPIO pins. Your board-specific ++ setup logic must also provide a platform device, ++ with configuration data saying which GPIOs are used. + -+ /* Do initial configuration here, now that -+ * we have certain key parameters -+ * (dev_flags and interface) */ -+ return phy_init_hw(phydev); -+} -+EXPORT_SYMBOL(phy_attach_direct); ++ To compile this driver as a module, choose M here: the ++ module will be called gpio-buttons. + -+/** -+ * phy_attach - attach a network device to a particular PHY device -+ * @dev: network device to attach -+ * @bus_id: Bus ID of PHY device to attach -+ * @flags: PHY device's dev_flags -+ * @interface: PHY device's interface + endif +diff -Nur linux-2.6.36.orig/drivers/input/misc/Makefile linux-2.6.36/drivers/input/misc/Makefile +--- linux-2.6.36.orig/drivers/input/misc/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/input/misc/Makefile 2010-11-18 21:16:12.000000000 +0100 +@@ -41,4 +41,5 @@ + obj-$(CONFIG_INPUT_WISTRON_BTNS) += wistron_btns.o + obj-$(CONFIG_INPUT_WM831X_ON) += wm831x-on.o + obj-$(CONFIG_INPUT_YEALINK) += yealink.o ++obj-$(CONFIG_INPUT_GPIO_BUTTONS) += gpio_buttons.o + +diff -Nur linux-2.6.36.orig/drivers/input/misc/gpio_buttons.c linux-2.6.36/drivers/input/misc/gpio_buttons.c +--- linux-2.6.36.orig/drivers/input/misc/gpio_buttons.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/input/misc/gpio_buttons.c 2010-11-18 21:16:11.000000000 +0100 +@@ -0,0 +1,216 @@ ++/* ++ * Driver for buttons on GPIO lines not capable of generating interrupts ++ * ++ * Copyright (C) 2007-2010 Gabor Juhos ++ * Copyright (C) 2010 Nuno Goncalves ++ * ++ * This file was based on: /drivers/input/misc/cobalt_btns.c ++ * Copyright (C) 2007 Yoichi Yuasa ++ * ++ * also was based on: /drivers/input/keyboard/gpio_keys.c ++ * Copyright 2005 Phil Blundell ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. + * -+ * Description: Same as phy_attach_direct() except that a PHY bus_id -+ * string is passed instead of a pointer to a struct phy_device. + */ -+struct phy_device *phy_attach(struct net_device *dev, -+ const char *bus_id, u32 flags, phy_interface_t interface) -+{ -+ struct bus_type *bus = &mdio_bus_type; -+ struct phy_device *phydev; -+ struct device *d; -+ int rc; -+ -+ /* Search the list of PHY devices on the mdio bus for the -+ * PHY with the requested name */ -+ d = bus_find_device_by_name(bus, NULL, bus_id); -+ if (!d) { -+ pr_err("PHY %s not found\n", bus_id); -+ return ERR_PTR(-ENODEV); -+ } -+ phydev = to_phy_device(d); -+ -+ rc = phy_attach_direct(dev, phydev, flags, interface); -+ if (rc) -+ return ERR_PTR(rc); + -+ return phydev; -+} -+EXPORT_SYMBOL(phy_attach); ++#include ++#include ++#include ++#include + -+/** -+ * phy_detach - detach a PHY device from its network device -+ * @phydev: target phy_device struct -+ */ -+void phy_detach(struct phy_device *phydev) -+{ -+ phydev->attached_dev = NULL; ++#include ++#include ++#include ++#include + -+ /* If the device had no specific driver before (i.e. - it -+ * was using the generic driver), we unbind the device -+ * from the generic driver so that there's a chance a -+ * real driver could be loaded */ -+ if (phydev->dev.driver == &genphy_driver.driver) -+ device_release_driver(&phydev->dev); -+} -+EXPORT_SYMBOL(phy_detach); ++#include + ++#include + -+/* Generic PHY support and helper functions */ ++#define DRV_NAME "gpio-buttons" ++#define DRV_VERSION "0.1.2" ++#define PFX DRV_NAME ": " + -+/** -+ * genphy_config_advert - sanitize and advertise auto-negotation parameters -+ * @phydev: target phy_device struct -+ * -+ * Description: Writes MII_ADVERTISE with the appropriate values, -+ * after sanitizing the values to make sure we only advertise -+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement -+ * hasn't changed, and > 0 if it has changed. -+ */ -+int genphy_config_advert(struct phy_device *phydev) -+{ -+ u32 advertise; -+ int oldadv, adv; -+ int err, changed = 0; -+ -+ /* Only allow advertising what -+ * this PHY supports */ -+ phydev->advertising &= phydev->supported; -+ advertise = phydev->advertising; -+ -+ /* Setup standard advertisement */ -+ oldadv = adv = phy_read(phydev, MII_ADVERTISE); -+ -+ if (adv < 0) -+ return adv; -+ -+ adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | -+ ADVERTISE_PAUSE_ASYM); -+ if (advertise & ADVERTISED_10baseT_Half) -+ adv |= ADVERTISE_10HALF; -+ if (advertise & ADVERTISED_10baseT_Full) -+ adv |= ADVERTISE_10FULL; -+ if (advertise & ADVERTISED_100baseT_Half) -+ adv |= ADVERTISE_100HALF; -+ if (advertise & ADVERTISED_100baseT_Full) -+ adv |= ADVERTISE_100FULL; -+ if (advertise & ADVERTISED_Pause) -+ adv |= ADVERTISE_PAUSE_CAP; -+ if (advertise & ADVERTISED_Asym_Pause) -+ adv |= ADVERTISE_PAUSE_ASYM; -+ -+ if (adv != oldadv) { -+ err = phy_write(phydev, MII_ADVERTISE, adv); -+ -+ if (err < 0) -+ return err; -+ changed = 1; -+ } ++struct gpio_button_data { ++ int last_state; ++ int count; ++}; + -+ /* Configure gigabit if it's supported */ -+ if (phydev->supported & (SUPPORTED_1000baseT_Half | -+ SUPPORTED_1000baseT_Full)) { -+ oldadv = adv = phy_read(phydev, MII_CTRL1000); ++struct gpio_buttons_dev { ++ struct input_polled_dev *poll_dev; ++ struct gpio_buttons_platform_data *pdata; ++ struct gpio_button_data *data; ++}; + -+ if (adv < 0) -+ return adv; ++static void gpio_buttons_poll(struct input_polled_dev *dev) ++{ ++ struct gpio_buttons_dev *bdev = dev->private; ++ struct gpio_buttons_platform_data *pdata = bdev->pdata; ++ struct input_dev *input = dev->input; ++ int i; + -+ adv &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); -+ if (advertise & SUPPORTED_1000baseT_Half) -+ adv |= ADVERTISE_1000HALF; -+ if (advertise & SUPPORTED_1000baseT_Full) -+ adv |= ADVERTISE_1000FULL; ++ for (i = 0; i < bdev->pdata->nbuttons; i++) { ++ struct gpio_button *button = &pdata->buttons[i]; ++ unsigned int type = button->type ?: EV_KEY; ++ int state; + -+ if (adv != oldadv) { -+ err = phy_write(phydev, MII_CTRL1000, adv); ++ if (bdev->data[i].count < button->threshold) { ++ bdev->data[i].count++; ++ continue; ++ } + -+ if (err < 0) -+ return err; -+ changed = 1; ++ state = gpio_get_value(button->gpio) ? 1 : 0; ++ if (state != bdev->data[i].last_state) { ++ input_event(input, type, button->code, ++ !!(state ^ button->active_low)); ++ input_sync(input); ++ bdev->data[i].count = 0; ++ bdev->data[i].last_state = state; + } + } -+ -+ return changed; -+} -+EXPORT_SYMBOL(genphy_config_advert); -+ -+/** -+ * genphy_setup_forced - configures/forces speed/duplex from @phydev -+ * @phydev: target phy_device struct -+ * -+ * Description: Configures MII_BMCR to force speed/duplex -+ * to the values in phydev. Assumes that the values are valid. -+ * Please see phy_sanitize_settings(). -+ */ -+int genphy_setup_forced(struct phy_device *phydev) -+{ -+ int err; -+ int ctl = 0; -+ -+ phydev->pause = phydev->asym_pause = 0; -+ -+ if (SPEED_1000 == phydev->speed) -+ ctl |= BMCR_SPEED1000; -+ else if (SPEED_100 == phydev->speed) -+ ctl |= BMCR_SPEED100; -+ -+ if (DUPLEX_FULL == phydev->duplex) -+ ctl |= BMCR_FULLDPLX; -+ -+ err = phy_write(phydev, MII_BMCR, ctl); -+ -+ return err; +} + -+ -+/** -+ * genphy_restart_aneg - Enable and Restart Autonegotiation -+ * @phydev: target phy_device struct -+ */ -+int genphy_restart_aneg(struct phy_device *phydev) ++static int __devinit gpio_buttons_probe(struct platform_device *pdev) +{ -+ int ctl; -+ -+ ctl = phy_read(phydev, MII_BMCR); -+ -+ if (ctl < 0) -+ return ctl; ++ struct gpio_buttons_platform_data *pdata = pdev->dev.platform_data; ++ struct gpio_buttons_dev *bdev; ++ struct input_polled_dev *poll_dev; ++ struct input_dev *input; ++ int error, i; + -+ ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); ++ if (!pdata) ++ return -ENXIO; + -+ /* Don't isolate the PHY if we're negotiating */ -+ ctl &= ~(BMCR_ISOLATE); ++ bdev = kzalloc(sizeof(struct gpio_buttons_dev) + ++ sizeof(struct gpio_button_data) * pdata->nbuttons, ++ GFP_KERNEL); ++ if (!bdev) { ++ printk(KERN_ERR DRV_NAME "no memory for device\n"); ++ return -ENOMEM; ++ } + -+ ctl = phy_write(phydev, MII_BMCR, ctl); ++ bdev->data = (struct gpio_button_data *) &bdev[1]; + -+ return ctl; -+} -+EXPORT_SYMBOL(genphy_restart_aneg); ++ poll_dev = input_allocate_polled_device(); ++ if (!poll_dev) { ++ printk(KERN_ERR DRV_NAME "no memory for polled device\n"); ++ error = -ENOMEM; ++ goto err_free_bdev; ++ } + ++ poll_dev->private = bdev; ++ poll_dev->poll = gpio_buttons_poll; ++ poll_dev->poll_interval = pdata->poll_interval; + -+/** -+ * genphy_config_aneg - restart auto-negotiation or write BMCR -+ * @phydev: target phy_device struct -+ * -+ * Description: If auto-negotiation is enabled, we configure the -+ * advertising, and then restart auto-negotiation. If it is not -+ * enabled, then we write the BMCR. -+ */ -+int genphy_config_aneg(struct phy_device *phydev) -+{ -+ int result; ++ input = poll_dev->input; + -+ if (AUTONEG_ENABLE != phydev->autoneg) -+ return genphy_setup_forced(phydev); ++ input->evbit[0] = BIT(EV_KEY); ++ input->name = pdev->name; ++ input->phys = "gpio-buttons/input0"; ++ input->dev.parent = &pdev->dev; + -+ result = genphy_config_advert(phydev); ++ input->id.bustype = BUS_HOST; ++ input->id.vendor = 0x0001; ++ input->id.product = 0x0001; ++ input->id.version = 0x0100; + -+ if (result < 0) /* error */ -+ return result; ++ for (i = 0; i < pdata->nbuttons; i++) { ++ struct gpio_button *button = &pdata->buttons[i]; ++ unsigned int gpio = button->gpio; ++ unsigned int type = button->type ?: EV_KEY; + -+ if (result == 0) { -+ /* Advertisment hasn't changed, but maybe aneg was never on to -+ * begin with? Or maybe phy was isolated? */ -+ int ctl = phy_read(phydev, MII_BMCR); ++ error = gpio_request(gpio, button->desc ? ++ button->desc : DRV_NAME); ++ if (error) { ++ printk(KERN_ERR PFX "unable to claim gpio %u, " ++ "error %d\n", gpio, error); ++ goto err_free_gpio; ++ } + -+ if (ctl < 0) -+ return ctl; ++ error = gpio_direction_input(gpio); ++ if (error) { ++ printk(KERN_ERR PFX "unable to set direction on " ++ "gpio %u, error %d\n", gpio, error); ++ goto err_free_gpio; ++ } + -+ if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE)) -+ result = 1; /* do restart aneg */ ++ input_set_capability(input, type, button->code); ++ bdev->data[i].last_state = gpio_get_value(button->gpio) ? 1 : 0; + } + -+ /* Only restart aneg if we are advertising something different -+ * than we were before. */ -+ if (result > 0) -+ result = genphy_restart_aneg(phydev); -+ -+ return result; -+} -+EXPORT_SYMBOL(genphy_config_aneg); -+ -+/** -+ * genphy_update_link - update link status in @phydev -+ * @phydev: target phy_device struct -+ * -+ * Description: Update the value in phydev->link to reflect the -+ * current link value. In order to do this, we need to read -+ * the status register twice, keeping the second value. -+ */ -+int genphy_update_link(struct phy_device *phydev) -+{ -+ int status; ++ bdev->poll_dev = poll_dev; ++ bdev->pdata = pdata; ++ platform_set_drvdata(pdev, bdev); + -+ /* Do a fake read */ -+ status = phy_read(phydev, MII_BMSR); ++ error = input_register_polled_device(poll_dev); ++ if (error) { ++ printk(KERN_ERR PFX "unable to register polled device, " ++ "error %d\n", error); ++ goto err_free_gpio; ++ } + -+ if (status < 0) -+ return status; ++ return 0; + -+ /* Read link and autonegotiation status */ -+ status = phy_read(phydev, MII_BMSR); ++err_free_gpio: ++ for (i = i - 1; i >= 0; i--) ++ gpio_free(pdata->buttons[i].gpio); + -+ if (status < 0) -+ return status; ++ input_free_polled_device(poll_dev); + -+ if ((status & BMSR_LSTATUS) == 0) -+ phydev->link = 0; -+ else -+ phydev->link = 1; ++err_free_bdev: ++ kfree(bdev); + -+ return 0; ++ platform_set_drvdata(pdev, NULL); ++ return error; +} -+EXPORT_SYMBOL(genphy_update_link); + -+/** -+ * genphy_read_status - check the link status and update current link state -+ * @phydev: target phy_device struct -+ * -+ * Description: Check the link, then figure out the current state -+ * by comparing what we advertise with what the link partner -+ * advertises. Start by checking the gigabit possibilities, -+ * then move on to 10/100. -+ */ -+int genphy_read_status(struct phy_device *phydev) ++static int __devexit gpio_buttons_remove(struct platform_device *pdev) +{ -+ int adv; -+ int err; -+ int lpa; -+ int lpagb = 0; ++ struct gpio_buttons_dev *bdev = platform_get_drvdata(pdev); ++ struct gpio_buttons_platform_data *pdata = bdev->pdata; ++ int i; + -+ /* Update the link, but return if there -+ * was an error */ -+ err = genphy_update_link(phydev); -+ if (err) -+ return err; ++ input_unregister_polled_device(bdev->poll_dev); + -+ if (AUTONEG_ENABLE == phydev->autoneg) { -+ if (phydev->supported & (SUPPORTED_1000baseT_Half -+ | SUPPORTED_1000baseT_Full)) { -+ lpagb = phy_read(phydev, MII_STAT1000); ++ for (i = 0; i < pdata->nbuttons; i++) ++ gpio_free(pdata->buttons[i].gpio); + -+ if (lpagb < 0) -+ return lpagb; ++ input_free_polled_device(bdev->poll_dev); + -+ adv = phy_read(phydev, MII_CTRL1000); ++ kfree(bdev); ++ platform_set_drvdata(pdev, NULL); + -+ if (adv < 0) -+ return adv; ++ return 0; ++} + -+ lpagb &= adv << 2; -+ } ++static struct platform_driver gpio_buttons_driver = { ++ .probe = gpio_buttons_probe, ++ .remove = __devexit_p(gpio_buttons_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; + -+ lpa = phy_read(phydev, MII_LPA); ++static int __init gpio_buttons_init(void) ++{ ++ printk(KERN_INFO DRV_NAME " driver version " DRV_VERSION "\n"); ++ return platform_driver_register(&gpio_buttons_driver); ++} + -+ if (lpa < 0) -+ return lpa; ++static void __exit gpio_buttons_exit(void) ++{ ++ platform_driver_unregister(&gpio_buttons_driver); ++} + -+ adv = phy_read(phydev, MII_ADVERTISE); ++module_init(gpio_buttons_init); ++module_exit(gpio_buttons_exit); + -+ if (adv < 0) -+ return adv; ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_VERSION(DRV_VERSION); ++MODULE_DESCRIPTION("Polled buttons driver for CPU GPIOs"); + -+ lpa &= adv; +diff -Nur linux-2.6.36.orig/drivers/leds/leds-rb750.c linux-2.6.36/drivers/leds/leds-rb750.c +--- linux-2.6.36.orig/drivers/leds/leds-rb750.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/leds/leds-rb750.c 2010-11-18 21:16:13.000000000 +0100 +@@ -0,0 +1,140 @@ ++/* ++ * LED driver for the RouterBOARD 750 ++ * ++ * Copyright (C) 2010 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++#include ++#include ++#include ++#include + -+ phydev->speed = SPEED_10; -+ phydev->duplex = DUPLEX_HALF; -+ phydev->pause = phydev->asym_pause = 0; ++#include + -+ if (lpagb & (LPA_1000FULL | LPA_1000HALF)) { -+ phydev->speed = SPEED_1000; ++#define DRV_NAME "leds-rb750" + -+ if (lpagb & LPA_1000FULL) -+ phydev->duplex = DUPLEX_FULL; -+ } else if (lpa & (LPA_100FULL | LPA_100HALF)) { -+ phydev->speed = SPEED_100; -+ -+ if (lpa & LPA_100FULL) -+ phydev->duplex = DUPLEX_FULL; -+ } else -+ if (lpa & LPA_10FULL) -+ phydev->duplex = DUPLEX_FULL; ++struct rb750_led_dev { ++ struct led_classdev cdev; ++ u32 mask; ++ int active_low; ++}; + -+ if (phydev->duplex == DUPLEX_FULL){ -+ phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; -+ phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; -+ } -+ } else { -+ int bmcr = phy_read(phydev, MII_BMCR); -+ if (bmcr < 0) -+ return bmcr; ++struct rb750_led_drvdata { ++ struct rb750_led_dev *led_devs; ++ int num_leds; ++}; + -+ if (bmcr & BMCR_FULLDPLX) -+ phydev->duplex = DUPLEX_FULL; -+ else -+ phydev->duplex = DUPLEX_HALF; ++static inline struct rb750_led_dev *to_rbled(struct led_classdev *led_cdev) ++{ ++ return (struct rb750_led_dev *)container_of(led_cdev, ++ struct rb750_led_dev, cdev); ++} + -+ if (bmcr & BMCR_SPEED1000) -+ phydev->speed = SPEED_1000; -+ else if (bmcr & BMCR_SPEED100) -+ phydev->speed = SPEED_100; -+ else -+ phydev->speed = SPEED_10; ++static void rb750_led_brightness_set(struct led_classdev *led_cdev, ++ enum led_brightness value) ++{ ++ struct rb750_led_dev *rbled = to_rbled(led_cdev); ++ int level; + -+ phydev->pause = phydev->asym_pause = 0; -+ } ++ level = (value == LED_OFF) ? 0 : 1; ++ level ^= rbled->active_low; + -+ return 0; ++ if (level) ++ rb750_latch_change(0, rbled->mask); ++ else ++ rb750_latch_change(rbled->mask, 0); +} -+EXPORT_SYMBOL(genphy_read_status); + -+static int genphy_config_init(struct phy_device *phydev) ++static int __devinit rb750_led_probe(struct platform_device *pdev) +{ -+ int val; -+ u32 features; -+ -+ /* For now, I'll claim that the generic driver supports -+ * all possible port types */ -+ features = (SUPPORTED_TP | SUPPORTED_MII -+ | SUPPORTED_AUI | SUPPORTED_FIBRE | -+ SUPPORTED_BNC); ++ struct rb750_led_platform_data *pdata; ++ struct rb750_led_drvdata *drvdata; ++ int ret = 0; ++ int i; + -+ /* Do we support autonegotiation? */ -+ val = phy_read(phydev, MII_BMSR); ++ pdata = pdev->dev.platform_data; ++ if (!pdata) ++ return -EINVAL; + -+ if (val < 0) -+ return val; ++ drvdata = kzalloc(sizeof(struct rb750_led_drvdata) + ++ sizeof(struct rb750_led_dev) * pdata->num_leds, ++ GFP_KERNEL); ++ if (!drvdata) ++ return -ENOMEM; + -+ if (val & BMSR_ANEGCAPABLE) -+ features |= SUPPORTED_Autoneg; ++ drvdata->num_leds = pdata->num_leds; ++ drvdata->led_devs = (struct rb750_led_dev *) &drvdata[1]; + -+ if (val & BMSR_100FULL) -+ features |= SUPPORTED_100baseT_Full; -+ if (val & BMSR_100HALF) -+ features |= SUPPORTED_100baseT_Half; -+ if (val & BMSR_10FULL) -+ features |= SUPPORTED_10baseT_Full; -+ if (val & BMSR_10HALF) -+ features |= SUPPORTED_10baseT_Half; ++ for (i = 0; i < drvdata->num_leds; i++) { ++ struct rb750_led_dev *rbled = &drvdata->led_devs[i]; ++ struct rb750_led_data *led_data = &pdata->leds[i]; + -+ if (val & BMSR_ESTATEN) { -+ val = phy_read(phydev, MII_ESTATUS); ++ rbled->cdev.name = led_data->name; ++ rbled->cdev.default_trigger = led_data->default_trigger; ++ rbled->cdev.brightness_set = rb750_led_brightness_set; ++ rbled->cdev.brightness = LED_OFF; + -+ if (val < 0) -+ return val; ++ rbled->mask = led_data->mask; ++ rbled->active_low = !!led_data->active_low; + -+ if (val & ESTATUS_1000_TFULL) -+ features |= SUPPORTED_1000baseT_Full; -+ if (val & ESTATUS_1000_THALF) -+ features |= SUPPORTED_1000baseT_Half; ++ ret = led_classdev_register(&pdev->dev, &rbled->cdev); ++ if (ret) ++ goto err; + } + -+ phydev->supported = features; -+ phydev->advertising = features; -+ ++ platform_set_drvdata(pdev, drvdata); + return 0; -+} -+int genphy_suspend(struct phy_device *phydev) -+{ -+ int value; + -+ mutex_lock(&phydev->lock); -+ -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, (value | BMCR_PDOWN)); -+ -+ mutex_unlock(&phydev->lock); ++ err: ++ for (i = i - 1; i >= 0; i--) ++ led_classdev_unregister(&drvdata->led_devs[i].cdev); + -+ return 0; ++ kfree(drvdata); ++ return ret; +} -+EXPORT_SYMBOL(genphy_suspend); + -+int genphy_resume(struct phy_device *phydev) ++static int __devexit rb750_led_remove(struct platform_device *pdev) +{ -+ int value; -+ -+ mutex_lock(&phydev->lock); -+ -+ value = phy_read(phydev, MII_BMCR); -+ phy_write(phydev, MII_BMCR, (value & ~BMCR_PDOWN)); ++ struct rb750_led_drvdata *drvdata; ++ int i; + -+ mutex_unlock(&phydev->lock); ++ drvdata = platform_get_drvdata(pdev); ++ for (i = 0; i < drvdata->num_leds; i++) ++ led_classdev_unregister(&drvdata->led_devs[i].cdev); + ++ kfree(drvdata); + return 0; +} -+EXPORT_SYMBOL(genphy_resume); -+ -+/** -+ * phy_probe - probe and init a PHY device -+ * @dev: device to probe and init -+ * -+ * Description: Take care of setting up the phy_device structure, -+ * set the state to READY (the driver's init function should -+ * set it to STARTING if needed). -+ */ -+static int phy_probe(struct device *dev) -+{ -+ struct phy_device *phydev; -+ struct phy_driver *phydrv; -+ struct device_driver *drv; -+ int err = 0; + -+ phydev = to_phy_device(dev); -+ -+ /* Make sure the driver is held. -+ * XXX -- Is this correct? */ -+ drv = get_driver(phydev->dev.driver); -+ phydrv = to_phy_driver(drv); -+ phydev->drv = phydrv; ++static struct platform_driver rb750_led_driver = { ++ .probe = rb750_led_probe, ++ .remove = __devexit_p(rb750_led_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; + -+ /* Disable the interrupt if the PHY doesn't support it */ -+ if (!(phydrv->flags & PHY_HAS_INTERRUPT)) -+ phydev->irq = PHY_POLL; ++MODULE_ALIAS("platform:leds-rb750"); + -+ mutex_lock(&phydev->lock); ++static int __init rb750_led_init(void) ++{ ++ return platform_driver_register(&rb750_led_driver); ++} + -+ /* Start out supporting everything. Eventually, -+ * a controller will attach, and may modify one -+ * or both of these values */ -+ phydev->supported = phydrv->features; -+ phydev->advertising = phydrv->features; ++static void __exit rb750_led_exit(void) ++{ ++ platform_driver_unregister(&rb750_led_driver); ++} + -+ /* Set the state to READY by default */ -+ phydev->state = PHY_READY; ++module_init(rb750_led_init); ++module_exit(rb750_led_exit); + -+ if (phydev->drv->probe) -+ err = phydev->drv->probe(phydev); ++MODULE_DESCRIPTION(DRV_NAME); ++MODULE_DESCRIPTION("LED driver for the RouterBOARD 750"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.36.orig/drivers/leds/leds-wndr3700-usb.c linux-2.6.36/drivers/leds/leds-wndr3700-usb.c +--- linux-2.6.36.orig/drivers/leds/leds-wndr3700-usb.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/leds/leds-wndr3700-usb.c 2010-11-18 21:16:13.000000000 +0100 +@@ -0,0 +1,75 @@ ++/* ++ * USB LED driver for the NETGEAR WNDR3700 ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ mutex_unlock(&phydev->lock); ++#include ++#include ++#include + -+ return err; ++#include + -+} ++#define DRIVER_NAME "wndr3700-led-usb" + -+static int phy_remove(struct device *dev) ++static void wndr3700_usb_led_set(struct led_classdev *cdev, ++ enum led_brightness brightness) +{ -+ struct phy_device *phydev; -+ -+ phydev = to_phy_device(dev); -+ -+ mutex_lock(&phydev->lock); -+ phydev->state = PHY_DOWN; -+ mutex_unlock(&phydev->lock); -+ -+ if (phydev->drv->remove) -+ phydev->drv->remove(phydev); -+ -+ put_driver(dev->driver); -+ phydev->drv = NULL; -+ -+ return 0; ++ if (brightness) ++ ar71xx_device_start(RESET_MODULE_GE1_PHY); ++ else ++ ar71xx_device_stop(RESET_MODULE_GE1_PHY); +} + -+/** -+ * phy_driver_register - register a phy_driver with the PHY layer -+ * @new_driver: new phy_driver to register -+ */ -+int phy_driver_register(struct phy_driver *new_driver) ++static enum led_brightness wndr3700_usb_led_get(struct led_classdev *cdev) +{ -+ int retval; -+ -+ new_driver->driver.name = new_driver->name; -+ new_driver->driver.bus = &mdio_bus_type; -+ new_driver->driver.probe = phy_probe; -+ new_driver->driver.remove = phy_remove; -+ -+ retval = driver_register(&new_driver->driver); -+ -+ if (retval) { -+ printk(KERN_ERR "%s: Error %d in registering driver\n", -+ new_driver->name, retval); -+ -+ return retval; -+ } ++ return ar71xx_device_stopped(RESET_MODULE_GE1_PHY) ? LED_OFF : LED_FULL; ++} + -+ pr_debug("%s: Registered new driver\n", new_driver->name); ++static struct led_classdev wndr3700_usb_led = { ++ .name = "wndr3700:green:usb", ++ .brightness_set = wndr3700_usb_led_set, ++ .brightness_get = wndr3700_usb_led_get, ++}; + -+ return 0; ++static int __devinit wndr3700_usb_led_probe(struct platform_device *pdev) ++{ ++ return led_classdev_register(&pdev->dev, &wndr3700_usb_led); +} -+EXPORT_SYMBOL(phy_driver_register); + -+void phy_driver_unregister(struct phy_driver *drv) ++static int __devexit wndr3700_usb_led_remove(struct platform_device *pdev) +{ -+ driver_unregister(&drv->driver); ++ led_classdev_unregister(&wndr3700_usb_led); ++ return 0; +} -+EXPORT_SYMBOL(phy_driver_unregister); + -+static struct phy_driver genphy_driver = { -+ .phy_id = 0xffffffff, -+ .phy_id_mask = 0xffffffff, -+ .name = "Generic PHY", -+ .config_init = genphy_config_init, -+ .features = 0, -+ .config_aneg = genphy_config_aneg, -+ .read_status = genphy_read_status, -+ .suspend = genphy_suspend, -+ .resume = genphy_resume, -+ .driver = {.owner= THIS_MODULE, }, ++static struct platform_driver wndr3700_usb_led_driver = { ++ .probe = wndr3700_usb_led_probe, ++ .remove = __devexit_p(wndr3700_usb_led_remove), ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, +}; + -+static int __init phy_init(void) ++static int __init wndr3700_usb_led_init(void) +{ -+ int rc; -+ -+ rc = mdio_bus_init(); -+ if (rc) -+ return rc; -+ -+ rc = phy_driver_register(&genphy_driver); -+ if (rc) -+ mdio_bus_exit(); -+ -+ return rc; ++ return platform_driver_register(&wndr3700_usb_led_driver); +} + -+static void __exit phy_exit(void) ++static void __exit wndr3700_usb_led_exit(void) +{ -+ phy_driver_unregister(&genphy_driver); -+ mdio_bus_exit(); ++ platform_driver_unregister(&wndr3700_usb_led_driver); +} + -+subsys_initcall(phy_init); -+module_exit(phy_exit); -diff -Nur linux-2.6.35.7.orig/drivers/spi/ap83_spi.c linux-2.6.35.7/drivers/spi/ap83_spi.c ---- linux-2.6.35.7.orig/drivers/spi/ap83_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/spi/ap83_spi.c 2010-10-14 20:28:01.048101088 +0200 -@@ -0,0 +1,282 @@ ++module_init(wndr3700_usb_led_init); ++module_exit(wndr3700_usb_led_exit); ++ ++MODULE_DESCRIPTION("USB LED driver for the NETGEAR WNDR3700"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRIVER_NAME); +diff -Nur linux-2.6.36.orig/drivers/mtd/maps/Kconfig linux-2.6.36/drivers/mtd/maps/Kconfig +--- linux-2.6.36.orig/drivers/mtd/maps/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/mtd/maps/Kconfig 2010-11-18 21:16:13.000000000 +0100 +@@ -251,6 +251,13 @@ + help + Support for flash chips on NETtel/SecureEdge/SnapGear boards. + ++config MTD_AR91XX_FLASH ++ tristate "Atheros AR91xx parallel flash support" ++ depends on ATHEROS_AR71XX ++ select MTD_COMPLEX_MAPPINGS ++ help ++ Parallel flash driver for the Atheros AR91xx based boards. ++ + config MTD_DILNETPC + tristate "CFI Flash device mapped on DIL/Net PC" + depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT && BROKEN +diff -Nur linux-2.6.36.orig/drivers/mtd/maps/Makefile linux-2.6.36/drivers/mtd/maps/Makefile +--- linux-2.6.36.orig/drivers/mtd/maps/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/mtd/maps/Makefile 2010-11-18 21:16:13.000000000 +0100 +@@ -7,6 +7,7 @@ + endif + + # Chip mappings ++obj-$(CONFIG_MTD_AR91XX_FLASH) += ar91xx_flash.o + obj-$(CONFIG_MTD_CDB89712) += cdb89712.o + obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o + obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o +diff -Nur linux-2.6.36.orig/drivers/mtd/maps/ar91xx_flash.c linux-2.6.36/drivers/mtd/maps/ar91xx_flash.c +--- linux-2.6.36.orig/drivers/mtd/maps/ar91xx_flash.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/mtd/maps/ar91xx_flash.c 2010-11-18 21:16:13.000000000 +0100 +@@ -0,0 +1,310 @@ +/* -+ * Atheros AP83 board specific SPI Controller driver ++ * Parallel flash driver for the Atheros AR91xx SoC + * + * Copyright (C) 2009 Gabor Juhos + * @@ -23433,9018 +10942,6479 @@ diff -Nur linux-2.6.35.7.orig/drivers/spi/ap83_spi.c linux-2.6.35.7/drivers/spi/ + * + */ + ++#include ++#include +#include +#include -+#include -+#include -+#include ++#include ++#include +#include ++#include ++#include ++#include +#include -+#include -+#include -+#include -+#include + +#include -+#include -+ -+#define DRV_DESC "Atheros AP83 board SPI Controller driver" -+#define DRV_VERSION "0.1.0" -+#define DRV_NAME "ap83-spi" -+ -+#define AP83_SPI_CLK_HIGH (1 << 23) -+#define AP83_SPI_CLK_LOW 0 -+#define AP83_SPI_MOSI_HIGH (1 << 22) -+#define AP83_SPI_MOSI_LOW 0 -+ -+#define AP83_SPI_GPIO_CS 1 -+#define AP83_SPI_GPIO_MISO 3 ++#include + -+struct ap83_spi { -+ struct spi_bitbang bitbang; -+ void __iomem *base; -+ u32 addr; ++#define DRV_NAME "ar91xx-flash" + -+ struct platform_device *pdev; ++struct ar91xx_flash_info { ++ struct mtd_info *mtd; ++ struct map_info map; ++#ifdef CONFIG_MTD_PARTITIONS ++ int nr_parts; ++ struct mtd_partition *parts; ++#endif +}; + -+static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) -+{ -+ return __raw_readl(sp->base + reg); -+} -+ -+static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) -+{ -+ return spi_master_get_devdata(spi->master); -+} -+ -+static inline void setsck(struct spi_device *spi, int val) ++static map_word ar91xx_flash_read(struct map_info *map, unsigned long ofs) +{ -+ struct ap83_spi *sp = spidev_to_sp(spi); ++ map_word val; + -+ if (val) -+ sp->addr |= AP83_SPI_CLK_HIGH; ++ if (map_bankwidth_is_1(map)) ++ val.x[0] = __raw_readb(map->virt + (ofs ^ 3)); ++ else if (map_bankwidth_is_2(map)) ++ val.x[0] = __raw_readw(map->virt + (ofs ^ 2)); + else -+ sp->addr &= ~AP83_SPI_CLK_HIGH; -+ -+ dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", -+ sp->addr, (val) ? "HIGH" : "LOW"); ++ val = map_word_ff(map); + -+ ap83_spi_rr(sp, sp->addr); ++ return val; +} + -+static inline void setmosi(struct spi_device *spi, int val) ++static void ar91xx_flash_write(struct map_info *map, map_word d, ++ unsigned long ofs) +{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ if (val) -+ sp->addr |= AP83_SPI_MOSI_HIGH; -+ else -+ sp->addr &= ~AP83_SPI_MOSI_HIGH; -+ -+ dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", -+ sp->addr, (val) ? "HIGH" : "LOW"); ++ if (map_bankwidth_is_1(map)) ++ __raw_writeb(d.x[0], map->virt + (ofs ^ 3)); ++ else if (map_bankwidth_is_2(map)) ++ __raw_writew(d.x[0], map->virt + (ofs ^ 2)); + -+ ap83_spi_rr(sp, sp->addr); ++ mb(); +} + -+static inline u32 getmiso(struct spi_device *spi) ++static map_word ar91xx_flash_read_lock(struct map_info *map, unsigned long ofs) +{ -+ u32 ret; ++ map_word ret; + -+ ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; -+ dev_dbg(&spi->dev, "get MISO: %d\n", ret); ++ ar71xx_flash_acquire(); ++ ret = ar91xx_flash_read(map, ofs); ++ ar71xx_flash_release(); + + return ret; +} + -+static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) -+{ -+ ndelay(nsecs); -+} -+ -+static void ap83_spi_chipselect(struct spi_device *spi, int on) -+{ -+ struct ap83_spi *sp = spidev_to_sp(spi); -+ -+ dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); -+ -+ if (on) { -+ ar71xx_flash_acquire(); -+ -+ sp->addr = 0; -+ ap83_spi_rr(sp, sp->addr); -+ -+ gpio_set_value(AP83_SPI_GPIO_CS, 0); -+ } else { -+ gpio_set_value(AP83_SPI_GPIO_CS, 1); -+ ar71xx_flash_release(); -+ } -+} -+ -+#define spidelay(nsecs) \ -+ do { \ -+ /* Steal the spi_device pointer from our caller. \ -+ * The bitbang-API should probably get fixed here... */ \ -+ do_spidelay(spi, nsecs); \ -+ } while (0) -+ -+#define EXPAND_BITBANG_TXRX -+#include -+ -+static u32 ap83_spi_txrx_mode0(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) -+{ -+ dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits); -+} -+ -+static u32 ap83_spi_txrx_mode1(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) ++static void ar91xx_flash_write_lock(struct map_info *map, map_word d, ++ unsigned long ofs) +{ -+ dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits); ++ ar71xx_flash_acquire(); ++ ar91xx_flash_write(map, d, ofs); ++ ar71xx_flash_release(); +} + -+static u32 ap83_spi_txrx_mode2(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) ++static void ar91xx_flash_copy_from_lock(struct map_info *map, void *to, ++ unsigned long from, ssize_t len) +{ -+ dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, bits); ++ ar71xx_flash_acquire(); ++ inline_map_copy_from(map, to, from, len); ++ ar71xx_flash_release(); +} + -+static u32 ap83_spi_txrx_mode3(struct spi_device *spi, -+ unsigned nsecs, u32 word, u8 bits) ++static void ar91xx_flash_copy_to_lock(struct map_info *map, unsigned long to, ++ const void *from, ssize_t len) +{ -+ dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); -+ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, bits); ++ ar71xx_flash_acquire(); ++ inline_map_copy_to(map, to, from, len); ++ ar71xx_flash_release(); +} + -+static int ap83_spi_probe(struct platform_device *pdev) ++static int ar91xx_flash_remove(struct platform_device *pdev) +{ -+ struct spi_master *master; -+ struct ap83_spi *sp; -+ struct ap83_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; ++ struct ar91xx_flash_platform_data *pdata; ++ struct ar91xx_flash_info *info; + -+ ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); -+ if (ret) { -+ dev_err(&pdev->dev, "gpio request failed for MISO\n"); -+ return ret; -+ } ++ info = platform_get_drvdata(pdev); ++ if (info == NULL) ++ return 0; + -+ ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); -+ if (ret) { -+ dev_err(&pdev->dev, "gpio request failed for CS\n"); -+ goto err_free_miso; -+ } ++ platform_set_drvdata(pdev, NULL); + -+ ret = gpio_direction_input(AP83_SPI_GPIO_MISO); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set direction of MISO\n"); -+ goto err_free_cs; -+ } ++ if (info->mtd == NULL) ++ return 0; + -+ ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); -+ if (ret) { -+ dev_err(&pdev->dev, "unable to set direction of CS\n"); -+ goto err_free_cs; ++ pdata = pdev->dev.platform_data; ++#ifdef CONFIG_MTD_PARTITIONS ++ if (info->nr_parts) { ++ del_mtd_partitions(info->mtd); ++ kfree(info->parts); ++ } else if (pdata->nr_parts) { ++ del_mtd_partitions(info->mtd); ++ } else { ++ del_mtd_device(info->mtd); + } ++#else ++ del_mtd_device(info->mtd); ++#endif ++ map_destroy(info->mtd); + -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } ++ return 0; ++} + -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); ++static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; ++#ifdef CONFIG_MTD_PARTITIONS ++static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL }; ++#endif ++ ++static int ar91xx_flash_probe(struct platform_device *pdev) ++{ ++ struct ar91xx_flash_platform_data *pdata; ++ struct ar91xx_flash_info *info; ++ struct resource *res; ++ struct resource *region; ++ const char **probe_type; ++ int err = 0; + + pdata = pdev->dev.platform_data; ++ if (pdata == NULL) ++ return -EINVAL; + -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = ap83_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; -+ sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; -+ sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; -+ sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; ++ info = devm_kzalloc(&pdev->dev, sizeof(struct ar91xx_flash_info), ++ GFP_KERNEL); ++ if (info == NULL) { ++ err = -ENOMEM; ++ goto err_out; ++ } + -+ sp->bitbang.master->bus_num = pdev->id; -+ sp->bitbang.master->num_chipselect = 1; ++ platform_set_drvdata(pdev, info); + -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err_spi_put; ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ err = -ENOENT; ++ goto err_out; + } + -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err_spi_put; ++ dev_info(&pdev->dev, "%.8llx at %.8llx\n", ++ (unsigned long long)(res->end - res->start + 1), ++ (unsigned long long)res->start); ++ ++ region = devm_request_mem_region(&pdev->dev, ++ res->start, res->end - res->start + 1, ++ dev_name(&pdev->dev)); ++ if (region == NULL) { ++ dev_err(&pdev->dev, "could not reserve memory region\n"); ++ err = -ENOMEM; ++ goto err_out; + } + -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ goto err_unmap; ++ info->map.name = dev_name(&pdev->dev); ++ info->map.phys = res->start; ++ info->map.size = res->end - res->start + 1; ++ info->map.bankwidth = pdata->width; + -+ dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); ++ info->map.virt = devm_ioremap(&pdev->dev, info->map.phys, ++ info->map.size); ++ if (info->map.virt == NULL) { ++ dev_err(&pdev->dev, "failed to ioremap flash region\n"); ++ err = -EIO; ++ goto err_out; ++ } + -+ return 0; ++ simple_map_init(&info->map); ++ if (pdata->is_shared) { ++ info->map.read = ar91xx_flash_read_lock; ++ info->map.write = ar91xx_flash_write_lock; ++ info->map.copy_from = ar91xx_flash_copy_from_lock; ++ info->map.copy_to = ar91xx_flash_copy_to_lock; ++ } else { ++ info->map.read = ar91xx_flash_read; ++ info->map.write = ar91xx_flash_write; ++ } + -+ err_unmap: -+ iounmap(sp->base); -+ err_spi_put: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); ++ probe_type = rom_probe_types; ++ for (; info->mtd == NULL && *probe_type != NULL; probe_type++) ++ info->mtd = do_map_probe(*probe_type, &info->map); + -+ err_free_cs: -+ gpio_free(AP83_SPI_GPIO_CS); -+ err_free_miso: -+ gpio_free(AP83_SPI_GPIO_MISO); -+ return ret; -+} ++ if (info->mtd == NULL) { ++ dev_err(&pdev->dev, "map_probe failed\n"); ++ err = -ENXIO; ++ goto err_out; ++ } + -+static int ap83_spi_remove(struct platform_device *pdev) -+{ -+ struct ap83_spi *sp = platform_get_drvdata(pdev); ++ info->mtd->owner = THIS_MODULE; + -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); ++#ifdef CONFIG_MTD_PARTITIONS ++ if (pdata->nr_parts) { ++ dev_info(&pdev->dev, "using static partition mapping\n"); ++ add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); ++ return 0; ++ } + -+ return 0; -+} ++ err = parse_mtd_partitions(info->mtd, part_probe_types, ++ &info->parts, 0); ++ if (err > 0) { ++ add_mtd_partitions(info->mtd, info->parts, err); ++ return 0; ++ } ++#endif + -+static struct platform_driver ap83_spi_drv = { -+ .probe = ap83_spi_probe, -+ .remove = ap83_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; ++ add_mtd_device(info->mtd); ++ return 0; + -+static int __init ap83_spi_init(void) -+{ -+ return platform_driver_register(&ap83_spi_drv); ++ err_out: ++ ar91xx_flash_remove(pdev); ++ return err; +} -+module_init(ap83_spi_init); + -+static void __exit ap83_spi_exit(void) ++#ifdef CONFIG_PM ++static int ar91xx_flash_suspend(struct platform_device *dev, pm_message_t state) +{ -+ platform_driver_unregister(&ap83_spi_drv); -+} -+module_exit(ap83_spi_exit); -+ -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.35.7.orig/drivers/spi/ar71xx_spi.c linux-2.6.35.7/drivers/spi/ar71xx_spi.c ---- linux-2.6.35.7.orig/drivers/spi/ar71xx_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/spi/ar71xx_spi.c 2010-10-14 20:28:01.088050552 +0200 -@@ -0,0 +1,283 @@ -+/* -+ * Atheros AR71xx SPI Controller driver -+ * -+ * Copyright (C) 2008-2009 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include ++ struct ar91xx_flash_info *info = platform_get_drvdata(dev); ++ int ret = 0; + -+#define DRV_DESC "Atheros AR71xx SPI Controller driver" -+#define DRV_VERSION "0.2.4" -+#define DRV_NAME "ar71xx-spi" ++ if (info->mtd->suspend) ++ ret = info->mtd->suspend(info->mtd); + -+#undef PER_BIT_READ ++ if (ret) ++ goto fail; + -+struct ar71xx_spi { -+ struct spi_bitbang bitbang; -+ u32 ioc_base; -+ u32 reg_ctrl; ++ return 0; + -+ void __iomem *base; ++ fail: ++ if (info->mtd->suspend) { ++ BUG_ON(!info->mtd->resume); ++ info->mtd->resume(info->mtd); ++ } + -+ struct platform_device *pdev; -+ u32 (*get_ioc_base)(u8 chip_select, int cs_high, -+ int is_on); -+}; ++ return ret; ++} + -+static inline u32 ar71xx_spi_rr(struct ar71xx_spi *sp, unsigned reg) ++static int ar91xx_flash_resume(struct platform_device *pdev) +{ -+ return __raw_readl(sp->base + reg); ++ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); ++ ++ if (info->mtd->resume) ++ info->mtd->resume(info->mtd); ++ ++ return 0; +} + -+static inline void ar71xx_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) ++static void ar91xx_flash_shutdown(struct platform_device *pdev) +{ -+ __raw_writel(val, sp->base + reg); ++ struct ar91xx_flash_info *info = platform_get_drvdata(pdev); ++ ++ if (info->mtd->suspend && info->mtd->resume) ++ if (info->mtd->suspend(info->mtd) == 0) ++ info->mtd->resume(info->mtd); +} ++#else ++#define ar91xx_flash_suspend NULL ++#define ar91xx_flash_resume NULL ++#define ar91xx_flash_shutdown NULL ++#endif + -+static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) ++static struct platform_driver ar91xx_flash_driver = { ++ .probe = ar91xx_flash_probe, ++ .remove = ar91xx_flash_remove, ++ .suspend = ar91xx_flash_suspend, ++ .resume = ar91xx_flash_resume, ++ .shutdown = ar91xx_flash_shutdown, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init ar91xx_flash_init(void) +{ -+ return spi_master_get_devdata(spi->master); ++ return platform_driver_register(&ar91xx_flash_driver); +} + -+static u32 ar71xx_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) ++static void __exit ar91xx_flash_exit(void) +{ -+ u32 ret; ++ platform_driver_unregister(&ar91xx_flash_driver); ++} + -+ if (is_on == AR71XX_SPI_CS_INACTIVE) -+ ret = SPI_IOC_CS_ALL; -+ else -+ ret = SPI_IOC_CS_ALL & ~SPI_IOC_CS(chip_select); ++module_init(ar91xx_flash_init); ++module_exit(ar91xx_flash_exit); + -+ return ret; -+} ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_DESCRIPTION("Parallel flash driver for the Atheros AR91xx SoC"); ++MODULE_ALIAS("platform:" DRV_NAME); +diff -Nur linux-2.6.36.orig/drivers/mtd/nand/Kconfig linux-2.6.36/drivers/mtd/nand/Kconfig +--- linux-2.6.36.orig/drivers/mtd/nand/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/mtd/nand/Kconfig 2010-11-18 21:16:13.000000000 +0100 +@@ -531,4 +531,8 @@ + help + Enables support for NAND Flash on JZ4740 SoC based boards. + ++config MTD_NAND_RB4XX ++ tristate "NAND flash driver for RouterBoard 4xx series" ++ depends on MTD_NAND && AR71XX_MACH_RB4XX + -+static void ar71xx_spi_chipselect(struct spi_device *spi, int value) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ void __iomem *base = sp->base; -+ u32 ioc_base; + endif # MTD_NAND +diff -Nur linux-2.6.36.orig/drivers/mtd/nand/Makefile linux-2.6.36/drivers/mtd/nand/Makefile +--- linux-2.6.36.orig/drivers/mtd/nand/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/mtd/nand/Makefile 2010-11-18 21:16:14.000000000 +0100 +@@ -32,6 +32,7 @@ + obj-$(CONFIG_MTD_NAND_PXA3xx) += pxa3xx_nand.o + obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o + obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o ++obj-$(CONFIG_MTD_NAND_RB4XX) += rb4xx_nand.o + obj-$(CONFIG_MTD_ALAUDA) += alauda.o + obj-$(CONFIG_MTD_NAND_PASEMI) += pasemi_nand.o + obj-$(CONFIG_MTD_NAND_ORION) += orion_nand.o +diff -Nur linux-2.6.36.orig/drivers/mtd/nand/rb4xx_nand.c linux-2.6.36/drivers/mtd/nand/rb4xx_nand.c +--- linux-2.6.36.orig/drivers/mtd/nand/rb4xx_nand.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/mtd/nand/rb4xx_nand.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,513 @@ ++/* ++ * NAND flash driver for the MikroTik RouterBoard 4xx series ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This file was based on the driver for Linux 2.6.22 published by ++ * MikroTik for their RouterBoard 4xx series devices. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ switch (value) { -+ case BITBANG_CS_INACTIVE: -+ ioc_base = sp->get_ioc_base(spi->chip_select, -+ (spi->mode & SPI_CS_HIGH) != 0, -+ AR71XX_SPI_CS_INACTIVE); -+ __raw_writel(ioc_base, base + SPI_REG_IOC); -+ break; ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+ case BITBANG_CS_ACTIVE: -+ ioc_base = sp->get_ioc_base(spi->chip_select, -+ (spi->mode & SPI_CS_HIGH) != 0, -+ AR71XX_SPI_CS_ACTIVE); ++#include + -+ __raw_writel(ioc_base, base + SPI_REG_IOC); -+ sp->ioc_base = ioc_base; -+ break; -+ } -+} ++#define DRV_NAME "rb4xx-nand" ++#define DRV_VERSION "0.1.10" ++#define DRV_DESC "NAND flash driver for RouterBoard 4xx series" + -+static void ar71xx_spi_setup_regs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); ++#define USE_FAST_READ 1 ++#define USE_FAST_WRITE 1 ++#undef RB4XX_NAND_DEBUG + -+ /* enable GPIO mode */ -+ ar71xx_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); ++#ifdef RB4XX_NAND_DEBUG ++#define DBG(fmt, arg...) printk(KERN_DEBUG DRV_NAME ": " fmt, ## arg) ++#else ++#define DBG(fmt, arg...) do {} while (0) ++#endif + -+ /* save CTRL register */ -+ sp->reg_ctrl = ar71xx_spi_rr(sp, SPI_REG_CTRL); ++#define RB4XX_NAND_GPIO_RDY 5 ++#define RB4XX_FLASH_HZ 33333334 ++#define RB4XX_NAND_HZ 33333334 + -+ /* TODO: setup speed? */ -+ ar71xx_spi_wr(sp, SPI_REG_CTRL, 0x43); -+} ++#define SPI_CTRL_FASTEST 0x40 ++#define SPI_CTRL_SAFE 0x43 /* 25 MHz for AHB 200 MHz */ ++#define SBIT_IOC_BASE SPI_IOC_CS1 ++#define SBIT_IOC_DO_SHIFT 0 ++#define SBIT_IOC_DO (1u << SBIT_IOC_DO_SHIFT) ++#define SBIT_IOC_DO2_SHIFT 18 ++#define SBIT_IOC_DO2 (1u << SBIT_IOC_DO2_SHIFT) + -+static void ar71xx_spi_restore_regs(struct spi_device *spi) -+{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); ++#define CPLD_CMD_WRITE_MULT 0x08 /* send cmd, n x send data, read data */ ++#define CPLD_CMD_WRITE_CFG 0x09 /* send cmd, n x send cfg */ ++#define CPLD_CMD_READ_MULT 0x0a /* send cmd, send idle, n x read data */ ++#define CPLD_CMD_READ_FAST 0x0b /* send cmd, 4 x idle, n x read data */ + -+ /* restore CTRL register */ -+ ar71xx_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ ar71xx_spi_wr(sp, SPI_REG_FS, 0); -+} ++#define CFG_BIT_nCE 0x80 ++#define CFG_BIT_CLE 0x40 ++#define CFG_BIT_ALE 0x20 ++#define CFG_BIT_FAN 0x10 ++#define CFG_BIT_nLED4 0x08 ++#define CFG_BIT_nLED3 0x04 ++#define CFG_BIT_nLED2 0x02 ++#define CFG_BIT_nLED1 0x01 + -+static int ar71xx_spi_setup(struct spi_device *spi) -+{ -+ int status; ++#define CFG_BIT_nLEDS \ ++ (CFG_BIT_nLED1 | CFG_BIT_nLED2 | CFG_BIT_nLED3 | CFG_BIT_nLED4) + -+ if (spi->bits_per_word > 32) -+ return -EINVAL; ++struct rb4xx_nand_info { ++ struct nand_chip chip; ++ struct mtd_info mtd; ++}; + -+ if (!spi->controller_state) -+ ar71xx_spi_setup_regs(spi); ++/* ++ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader ++ * will not be able to find the kernel that we load. ++ */ ++static struct nand_ecclayout rb4xx_nand_ecclayout = { ++ .eccbytes = 6, ++ .eccpos = { 8, 9, 10, 13, 14, 15 }, ++ .oobavail = 9, ++ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } ++}; + -+ status = spi_bitbang_setup(spi); -+ if (status && !spi->controller_state) -+ ar71xx_spi_restore_regs(spi); ++static struct mtd_partition rb4xx_nand_partitions[] = { ++ { ++ .name = "booter", ++ .offset = 0, ++ .size = (256 * 1024), ++ .mask_flags = MTD_WRITEABLE, ++ }, ++ { ++ .name = "kernel", ++ .offset = (256 * 1024), ++ .size = (4 * 1024 * 1024) - (256 * 1024), ++ }, ++ { ++ .name = "rootfs", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = (1024*1024*64) - (1024*256) - (4 * 1024 * 1024) ++ }, ++ { ++ .name = "cfgfs", ++ .offset = (1024*1024*64) - (1024*256), ++ .size = (1024*256), ++ }, ++}; + -+ return status; -+} ++#if USE_FAST_READ ++#define SPI_NDATA_BASE 0x00800000 ++static unsigned spi_ctrl_fread = SPI_CTRL_SAFE; ++static unsigned spi_ctrl_flash = SPI_CTRL_SAFE; ++extern unsigned mips_hpt_frequency; ++#endif + -+static void ar71xx_spi_cleanup(struct spi_device *spi) ++static inline unsigned rb4xx_spi_rreg(unsigned r) +{ -+ ar71xx_spi_restore_regs(spi); -+ spi_bitbang_cleanup(spi); ++ return __raw_readl((void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r)); +} + -+static u32 ar71xx_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, -+ u32 word, u8 bits) ++static inline void rb4xx_spi_wreg(unsigned r, unsigned v) +{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ void __iomem *base = sp->base; -+ u32 ioc = sp->ioc_base; -+ u32 ret; -+ -+ /* clock starts at inactive polarity */ -+ for (word <<= (32 - bits); likely(bits); bits--) { -+ u32 out; -+ -+ if (word & (1 << 31)) -+ out = ioc | SPI_IOC_DO; -+ else -+ out = ioc & ~SPI_IOC_DO; ++ __raw_writel(v, (void * __iomem)(KSEG1ADDR(AR71XX_SPI_BASE) + r)); ++} + -+ /* setup MSB (to slave) on trailing edge */ -+ __raw_writel(out, base + SPI_REG_IOC); ++static inline void do_spi_clk(int bit) ++{ ++ unsigned bval = SBIT_IOC_BASE | (bit & 1); + -+ __raw_writel(out | SPI_IOC_CLK, base + SPI_REG_IOC); ++ rb4xx_spi_wreg(SPI_REG_IOC, bval); ++ rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK); ++} + -+ word <<= 1; ++static void do_spi_byte(uint8_t byte) ++{ ++ do_spi_clk(byte >> 7); ++ do_spi_clk(byte >> 6); ++ do_spi_clk(byte >> 5); ++ do_spi_clk(byte >> 4); ++ do_spi_clk(byte >> 3); ++ do_spi_clk(byte >> 2); ++ do_spi_clk(byte >> 1); ++ do_spi_clk(byte); + -+#ifdef PER_BIT_READ -+ /* sample MSB (from slave) on leading edge */ -+ ret = __raw_readl(base + SPI_REG_RDS); -+ __raw_writel(out, base + SPI_REG_IOC); -+#endif ++ DBG("spi_byte sent 0x%02x got 0x%x\n", ++ byte, rb4xx_spi_rreg(SPI_REG_RDS)); ++} + -+ } ++#if USE_FAST_WRITE ++static inline void do_spi_clk_fast(int bit1, int bit2) ++{ ++ unsigned bval = (SBIT_IOC_BASE | ++ ((bit1 << SBIT_IOC_DO_SHIFT) & SBIT_IOC_DO) | ++ ((bit2 << SBIT_IOC_DO2_SHIFT) & SBIT_IOC_DO2)); + -+#ifndef PER_BIT_READ -+ ret = __raw_readl(base + SPI_REG_RDS); -+#endif -+ return ret; ++ rb4xx_spi_wreg(SPI_REG_IOC, bval); ++ rb4xx_spi_wreg(SPI_REG_IOC, bval | SPI_IOC_CLK); +} + -+static int ar71xx_spi_probe(struct platform_device *pdev) ++static inline void do_spi_byte_fast(uint8_t byte) +{ -+ struct spi_master *master; -+ struct ar71xx_spi *sp; -+ struct ar71xx_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; -+ -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } ++ do_spi_clk_fast(byte >> 7, byte >> 6); ++ do_spi_clk_fast(byte >> 5, byte >> 4); ++ do_spi_clk_fast(byte >> 3, byte >> 2); ++ do_spi_clk_fast(byte >> 1, byte >> 0); + -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); ++ DBG("spi_byte_fast sent 0x%02x got 0x%x\n", ++ byte, rb4xx_spi_rreg(SPI_REG_RDS)); ++} ++#else ++static inline void do_spi_byte_fast(uint8_t byte) ++{ ++ do_spi_byte(byte); ++} ++#endif /* USE_FAST_WRITE */ + -+ pdata = pdev->dev.platform_data; ++static int do_spi_cmd(unsigned cmd, unsigned sendCnt, const uint8_t *sendData, ++ unsigned recvCnt, uint8_t *recvData, ++ const uint8_t *verifyData, int fastWrite) ++{ ++ unsigned i; + -+ master->setup = ar71xx_spi_setup; -+ master->cleanup = ar71xx_spi_cleanup; ++ DBG("SPI cmd 0x%x send %u recv %u\n", cmd, sendCnt, recvCnt); + -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = ar71xx_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = ar71xx_spi_txrx_mode0; -+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; ++ rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO); ++ rb4xx_spi_wreg(SPI_REG_CTRL, SPI_CTRL_FASTEST); + -+ sp->get_ioc_base = ar71xx_spi_get_ioc_base; -+ if (pdata) { -+ sp->bitbang.master->bus_num = pdata->bus_num; -+ sp->bitbang.master->num_chipselect = pdata->num_chipselect; -+ if (pdata->get_ioc_base) -+ sp->get_ioc_base = pdata->get_ioc_base; -+ } else { -+ sp->bitbang.master->bus_num = 0; -+ sp->bitbang.master->num_chipselect = 3; ++ do_spi_byte(cmd); ++#if 0 ++ if (cmd == CPLD_CMD_READ_FAST) { ++ do_spi_byte(0x80); ++ do_spi_byte(0); ++ do_spi_byte(0); + } -+ -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err1; ++#endif ++ for (i = 0; i < sendCnt; ++i) { ++ if (fastWrite) ++ do_spi_byte_fast(sendData[i]); ++ else ++ do_spi_byte(sendData[i]); + } + -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err1; -+ } ++ for (i = 0; i < recvCnt; ++i) { ++ if (fastWrite) ++ do_spi_byte_fast(0); ++ else ++ do_spi_byte(0); + -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ return 0; ++ if (recvData) { ++ recvData[i] = rb4xx_spi_rreg(SPI_REG_RDS) & 0xff; ++ } else if (verifyData) { ++ if (verifyData[i] != (rb4xx_spi_rreg(SPI_REG_RDS) ++ & 0xff)) ++ break; ++ } ++ } + -+ iounmap(sp->base); -+ err1: -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); ++ rb4xx_spi_wreg(SPI_REG_IOC, SBIT_IOC_BASE | SPI_IOC_CS0); ++ rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_flash); ++ rb4xx_spi_wreg(SPI_REG_FS, 0); + -+ return ret; ++ return i == recvCnt; +} + -+static int ar71xx_spi_remove(struct platform_device *pdev) -+{ -+ struct ar71xx_spi *sp = platform_get_drvdata(pdev); -+ -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); -+ platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); ++static int got_write = 1; + -+ return 0; ++static void rb4xx_nand_write_data(const uint8_t *byte, unsigned cnt) ++{ ++ do_spi_cmd(CPLD_CMD_WRITE_MULT, cnt, byte, 1, NULL, NULL, 1); ++ got_write = 1; +} + -+static struct platform_driver ar71xx_spi_drv = { -+ .probe = ar71xx_spi_probe, -+ .remove = ar71xx_spi_remove, -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar71xx_spi_init(void) ++static void rb4xx_nand_write_byte(uint8_t byte) +{ -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); -+ return platform_driver_register(&ar71xx_spi_drv); ++ rb4xx_nand_write_data(&byte, 1); +} -+module_init(ar71xx_spi_init); + -+static void __exit ar71xx_spi_exit(void) ++#if USE_FAST_READ ++static uint8_t *rb4xx_nand_read_getaddr(unsigned cnt) +{ -+ platform_driver_unregister(&ar71xx_spi_drv); -+} -+module_exit(ar71xx_spi_exit); ++ static unsigned nboffset = 0x100000; ++ unsigned addr; + -+MODULE_ALIAS("platform:" DRV_NAME); -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_AUTHOR("Imre Kaloz "); -+MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.35.7.orig/drivers/spi/Kconfig linux-2.6.35.7/drivers/spi/Kconfig ---- linux-2.6.35.7.orig/drivers/spi/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/spi/Kconfig 2010-10-14 20:28:01.128101086 +0200 -@@ -53,6 +53,13 @@ - - comment "SPI Master Controller Drivers" - -+config SPI_AR71XX -+ tristate "Atheros AR71xx SPI Controller" -+ depends on SPI_MASTER && ATHEROS_AR71XX -+ select SPI_BITBANG -+ help -+ This is the SPI contoller driver for Atheros AR71xx. ++ if (got_write) { ++ nboffset = (nboffset + 31) & ~31; ++ if (nboffset >= 0x100000) /* 1MB */ ++ nboffset = 0; + - config SPI_ATMEL - tristate "Atmel SPI Controller" - depends on (ARCH_AT91 || AVR32) -diff -Nur linux-2.6.35.7.orig/drivers/spi/Makefile linux-2.6.35.7/drivers/spi/Makefile ---- linux-2.6.35.7.orig/drivers/spi/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/spi/Makefile 2010-10-14 20:28:01.168101108 +0200 -@@ -11,6 +11,7 @@ - obj-$(CONFIG_SPI_MASTER) += spi.o - - # SPI master controller drivers (bus) -+obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o - obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o - obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o - obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o -diff -Nur linux-2.6.35.7.orig/drivers/spi/pb44_spi.c linux-2.6.35.7/drivers/spi/pb44_spi.c ---- linux-2.6.35.7.orig/drivers/spi/pb44_spi.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/spi/pb44_spi.c 2010-10-14 20:28:01.205601089 +0200 -@@ -0,0 +1,299 @@ -+/* -+ * Atheros PB44 board SPI controller driver -+ * -+ * Copyright (C) 2009 Gabor Juhos -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. -+ * -+ */ ++ got_write = 0; ++ rb4xx_spi_wreg(SPI_REG_FS, SPI_FS_GPIO); ++ rb4xx_spi_wreg(SPI_REG_CTRL, spi_ctrl_fread); ++ rb4xx_spi_wreg(SPI_REG_FS, 0); ++ } + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include ++ addr = KSEG1ADDR(AR71XX_SPI_BASE + SPI_NDATA_BASE) + nboffset; ++ DBG("rb4xx_nand_read_getaddr 0x%x cnt 0x%x\n", addr, cnt); + -+#include -+#include ++ nboffset += cnt; ++ return (uint8_t *)addr; ++} + -+#define DRV_DESC "Atheros PB44 SPI Controller driver" -+#define DRV_VERSION "0.1.0" -+#define DRV_NAME "pb44-spi" ++static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt) ++{ ++ unsigned size32 = cnt & ~31; ++ unsigned remain = cnt & 31; + -+#undef PER_BIT_READ ++ if (size32) { ++ uint8_t *addr = rb4xx_nand_read_getaddr(size32); ++ memcpy(buf, (void *)addr, size32); ++ } + -+struct ar71xx_spi { -+ struct spi_bitbang bitbang; -+ u32 ioc_base; -+ u32 reg_ctrl; ++ if (remain) { ++ do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain, ++ buf + size32, NULL, 0); ++ } ++} + -+ void __iomem *base; ++static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt) ++{ ++ unsigned size32 = cnt & ~31; ++ unsigned remain = cnt & 31; + -+ struct platform_device *pdev; -+}; ++ if (size32) { ++ uint8_t *addr = rb4xx_nand_read_getaddr(size32); ++ if (memcmp(buf, (void *)addr, size32) != 0) ++ return 0; ++ } + -+static inline u32 pb44_spi_rr(struct ar71xx_spi *sp, unsigned reg) ++ if (remain) { ++ return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, remain, ++ NULL, buf + size32, 0); ++ } ++ return 1; ++} ++#else /* USE_FAST_READ */ ++static void rb4xx_nand_read_data(uint8_t *buf, unsigned cnt) +{ -+ return __raw_readl(sp->base + reg); ++ do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, buf, NULL, 0); +} + -+static inline void pb44_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) ++static int rb4xx_nand_verify_data(const uint8_t *buf, unsigned cnt) +{ -+ __raw_writel(val, sp->base + reg); ++ return do_spi_cmd(CPLD_CMD_READ_MULT, 1, buf, cnt, NULL, buf, 0); +} ++#endif /* USE_FAST_READ */ + -+static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) ++static void rb4xx_nand_write_cfg(uint8_t byte) +{ -+ return spi_master_get_devdata(spi->master); ++ do_spi_cmd(CPLD_CMD_WRITE_CFG, 1, &byte, 0, NULL, NULL, 0); ++ got_write = 1; +} + -+static void pb44_spi_chipselect(struct spi_device *spi, int is_active) ++static int rb4xx_nand_dev_ready(struct mtd_info *mtd) +{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; -+ -+ if (is_active) { -+ /* set initial clock polarity */ -+ if (spi->mode & SPI_CPOL) -+ sp->ioc_base |= SPI_IOC_CLK; -+ else -+ sp->ioc_base &= ~SPI_IOC_CLK; -+ -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } ++ return gpio_get_value(RB4XX_NAND_GPIO_RDY); ++} + -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; ++static void rb4xx_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, ++ unsigned int ctrl) ++{ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ uint8_t cfg = CFG_BIT_nLEDS; + -+ /* SPI is normally active-low */ -+ gpio_set_value(gpio, cs_high); -+ } else { -+ if (cs_high) -+ sp->ioc_base |= SPI_IOC_CS0; -+ else -+ sp->ioc_base &= ~SPI_IOC_CS0; ++ cfg |= (ctrl & NAND_CLE) ? CFG_BIT_CLE : 0; ++ cfg |= (ctrl & NAND_ALE) ? CFG_BIT_ALE : 0; ++ cfg |= (ctrl & NAND_NCE) ? 0 : CFG_BIT_nCE; + -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); ++ rb4xx_nand_write_cfg(cfg); + } + ++ if (cmd != NAND_CMD_NONE) ++ rb4xx_nand_write_byte(cmd); +} + -+static int pb44_spi_setup_cs(struct spi_device *spi) ++static uint8_t rb4xx_nand_read_byte(struct mtd_info *mtd) +{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ -+ /* enable GPIO mode */ -+ pb44_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); -+ -+ /* save CTRL register */ -+ sp->reg_ctrl = pb44_spi_rr(sp, SPI_REG_CTRL); -+ sp->ioc_base = pb44_spi_rr(sp, SPI_REG_IOC); -+ -+ /* TODO: setup speed? */ -+ pb44_spi_wr(sp, SPI_REG_CTRL, 0x43); -+ -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ int status = 0; -+ -+ status = gpio_request(gpio, dev_name(&spi->dev)); -+ if (status) -+ return status; ++ uint8_t byte = 0; + -+ status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); -+ if (status) { -+ gpio_free(gpio); -+ return status; -+ } -+ } else { -+ if (spi->mode & SPI_CS_HIGH) -+ sp->ioc_base |= SPI_IOC_CS0; -+ else -+ sp->ioc_base &= ~SPI_IOC_CS0; -+ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); -+ } ++ rb4xx_nand_read_data(&byte, 1); ++ return byte; ++} + -+ return 0; ++static void rb4xx_nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, ++ int len) ++{ ++ rb4xx_nand_write_data(buf, len); +} + -+static void pb44_spi_cleanup_cs(struct spi_device *spi) ++static void rb4xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, ++ int len) +{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ rb4xx_nand_read_data(buf, len); ++} + -+ if (spi->chip_select) { -+ unsigned long gpio = (unsigned long) spi->controller_data; -+ gpio_free(gpio); -+ } ++static int rb4xx_nand_verify_buf(struct mtd_info *mtd, const uint8_t *buf, ++ int len) ++{ ++ if (!rb4xx_nand_verify_data(buf, len)) ++ return -EFAULT; + -+ /* restore CTRL register */ -+ pb44_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); -+ /* disable GPIO mode */ -+ pb44_spi_wr(sp, SPI_REG_FS, 0); ++ return 0; +} + -+static int pb44_spi_setup(struct spi_device *spi) ++static unsigned get_spi_ctrl(unsigned hz_max, const char *name) +{ -+ int status = 0; ++ unsigned div; + -+ if (spi->bits_per_word > 32) -+ return -EINVAL; ++ div = (ar71xx_ahb_freq - 1) / (2 * hz_max); ++ /* ++ * CPU has a bug at (div == 0) - first bit read is random ++ */ ++ if (div == 0) ++ ++div; + -+ if (!spi->controller_state) { -+ status = pb44_spi_setup_cs(spi); -+ if (status) -+ return status; ++ if (name) { ++ unsigned ahb_khz = (ar71xx_ahb_freq + 500) / 1000; ++ unsigned div_real = 2 * (div + 1); ++ printk(KERN_INFO "%s SPI clock %u kHz (AHB %u kHz / %u)\n", ++ name, ++ ahb_khz / div_real, ++ ahb_khz, div_real); + } + -+ status = spi_bitbang_setup(spi); -+ if (status && !spi->controller_state) -+ pb44_spi_cleanup_cs(spi); -+ -+ return status; -+} -+ -+static void pb44_spi_cleanup(struct spi_device *spi) -+{ -+ pb44_spi_cleanup_cs(spi); -+ spi_bitbang_cleanup(spi); ++ return SPI_CTRL_FASTEST + div; +} + -+static u32 pb44_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, -+ u32 word, u8 bits) ++static int __init rb4xx_nand_probe(struct platform_device *pdev) +{ -+ struct ar71xx_spi *sp = spidev_to_sp(spi); -+ u32 ioc = sp->ioc_base; -+ u32 ret; -+ -+ /* clock starts at inactive polarity */ -+ for (word <<= (32 - bits); likely(bits); bits--) { -+ u32 out; ++ struct rb4xx_nand_info *info; ++ int ret; + -+ if (word & (1 << 31)) -+ out = ioc | SPI_IOC_DO; -+ else -+ out = ioc & ~SPI_IOC_DO; ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + -+ /* setup MSB (to slave) on trailing edge */ -+ pb44_spi_wr(sp, SPI_REG_IOC, out); -+ pb44_spi_wr(sp, SPI_REG_IOC, out | SPI_IOC_CLK); ++ ret = gpio_request(RB4XX_NAND_GPIO_RDY, "NAND RDY"); ++ if (ret) { ++ printk(KERN_ERR "rb4xx-nand: gpio request failed\n"); ++ return ret; ++ } + -+ word <<= 1; ++ ret = gpio_direction_input(RB4XX_NAND_GPIO_RDY); ++ if (ret) { ++ printk(KERN_ERR "rb4xx-nand: unable to set input mode " ++ "on gpio%d\n", RB4XX_NAND_GPIO_RDY); ++ goto err_free_gpio; ++ } + -+#ifdef PER_BIT_READ -+ /* sample MSB (from slave) on leading edge */ -+ ret = pb44_spi_rr(sp, SPI_REG_RDS); -+ pb44_spi_wr(sp, SPI_REG_IOC, out); -+#endif ++ info = kzalloc(sizeof(*info), GFP_KERNEL); ++ if (!info) { ++ printk(KERN_ERR "rb4xx-nand: no memory for private data\n"); ++ ret = -ENOMEM; ++ goto err_free_gpio; + } + -+#ifndef PER_BIT_READ -+ ret = pb44_spi_rr(sp, SPI_REG_RDS); ++#if USE_FAST_READ ++ spi_ctrl_fread = get_spi_ctrl(RB4XX_NAND_HZ, "NAND"); +#endif -+ return ret; -+} ++ spi_ctrl_flash = get_spi_ctrl(RB4XX_FLASH_HZ, "FLASH"); + -+static int pb44_spi_probe(struct platform_device *pdev) -+{ -+ struct spi_master *master; -+ struct ar71xx_spi *sp; -+ struct ar71xx_spi_platform_data *pdata; -+ struct resource *r; -+ int ret; ++ rb4xx_nand_write_cfg(CFG_BIT_nLEDS | CFG_BIT_nCE); + -+ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); -+ if (master == NULL) { -+ dev_err(&pdev->dev, "failed to allocate spi master\n"); -+ return -ENOMEM; -+ } ++ info->chip.priv = &info; ++ info->mtd.priv = &info->chip; ++ info->mtd.owner = THIS_MODULE; + -+ sp = spi_master_get_devdata(master); -+ platform_set_drvdata(pdev, sp); ++ info->chip.cmd_ctrl = rb4xx_nand_cmd_ctrl; ++ info->chip.dev_ready = rb4xx_nand_dev_ready; ++ info->chip.read_byte = rb4xx_nand_read_byte; ++ info->chip.write_buf = rb4xx_nand_write_buf; ++ info->chip.read_buf = rb4xx_nand_read_buf; ++ info->chip.verify_buf = rb4xx_nand_verify_buf; + -+ pdata = pdev->dev.platform_data; ++ info->chip.chip_delay = 25; ++ info->chip.ecc.mode = NAND_ECC_SOFT; ++ info->chip.options |= NAND_NO_AUTOINCR; + -+ master->setup = pb44_spi_setup; -+ master->cleanup = pb44_spi_cleanup; -+ if (pdata) { -+ master->bus_num = pdata->bus_num; -+ master->num_chipselect = pdata->num_chipselect; -+ } else { -+ master->bus_num = 0; -+ master->num_chipselect = 1; ++ platform_set_drvdata(pdev, info); ++ ++ ret = nand_scan_ident(&info->mtd, 1, NULL); ++ if (ret) { ++ ret = -ENXIO; ++ goto err_free_info; + } + -+ sp->bitbang.master = spi_master_get(master); -+ sp->bitbang.chipselect = pb44_spi_chipselect; -+ sp->bitbang.txrx_word[SPI_MODE_0] = pb44_spi_txrx_mode0; -+ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; -+ sp->bitbang.flags = SPI_CS_HIGH; ++ if (info->mtd.writesize == 512) ++ info->chip.ecc.layout = &rb4xx_nand_ecclayout; + -+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (r == NULL) { -+ ret = -ENOENT; -+ goto err1; ++ ret = nand_scan_tail(&info->mtd); ++ if (ret) { ++ return -ENXIO; ++ goto err_set_drvdata; + } + -+ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); -+ if (!sp->base) { -+ ret = -ENXIO; -+ goto err1; -+ } ++#ifdef CONFIG_MTD_PARTITIONS ++ ret = add_mtd_partitions(&info->mtd, rb4xx_nand_partitions, ++ ARRAY_SIZE(rb4xx_nand_partitions)); ++#else ++ ret = add_mtd_device(&info->mtd); ++#endif ++ if (ret) ++ goto err_release_nand; + -+ ret = spi_bitbang_start(&sp->bitbang); -+ if (!ret) -+ return 0; ++ return 0; + -+ iounmap(sp->base); -+ err1: ++err_release_nand: ++ nand_release(&info->mtd); ++err_set_drvdata: + platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); -+ ++err_free_info: ++ kfree(info); ++err_free_gpio: ++ gpio_free(RB4XX_NAND_GPIO_RDY); + return ret; +} + -+static int pb44_spi_remove(struct platform_device *pdev) ++static int __devexit rb4xx_nand_remove(struct platform_device *pdev) +{ -+ struct ar71xx_spi *sp = platform_get_drvdata(pdev); ++ struct rb4xx_nand_info *info = platform_get_drvdata(pdev); + -+ spi_bitbang_stop(&sp->bitbang); -+ iounmap(sp->base); ++ nand_release(&info->mtd); + platform_set_drvdata(pdev, NULL); -+ spi_master_put(sp->bitbang.master); ++ kfree(info); + + return 0; +} + -+static struct platform_driver pb44_spi_drv = { -+ .probe = pb44_spi_probe, -+ .remove = pb44_spi_remove, -+ .driver = { ++static struct platform_driver rb4xx_nand_driver = { ++ .probe = rb4xx_nand_probe, ++ .remove = __devexit_p(rb4xx_nand_remove), ++ .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + -+static int __init pb44_spi_init(void) ++static int __init rb4xx_nand_init(void) +{ -+ return platform_driver_register(&pb44_spi_drv); ++ return platform_driver_register(&rb4xx_nand_driver); +} -+module_init(pb44_spi_init); + -+static void __exit pb44_spi_exit(void) ++static void __exit rb4xx_nand_exit(void) +{ -+ platform_driver_unregister(&pb44_spi_drv); ++ platform_driver_unregister(&rb4xx_nand_driver); +} -+module_exit(pb44_spi_exit); + -+MODULE_ALIAS("platform:" DRV_NAME); ++module_init(rb4xx_nand_init); ++module_exit(rb4xx_nand_exit); ++ +MODULE_DESCRIPTION(DRV_DESC); +MODULE_VERSION(DRV_VERSION); +MODULE_AUTHOR("Gabor Juhos "); ++MODULE_AUTHOR("Imre Kaloz "); +MODULE_LICENSE("GPL v2"); -diff -Nur linux-2.6.35.7.orig/drivers/spi/spi_vsc7385.c linux-2.6.35.7/drivers/spi/spi_vsc7385.c ---- linux-2.6.35.7.orig/drivers/spi/spi_vsc7385.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/spi/spi_vsc7385.c 2010-10-14 20:28:01.238101190 +0200 -@@ -0,0 +1,620 @@ +diff -Nur linux-2.6.36.orig/drivers/mtd/nand/rb750_nand.c linux-2.6.36/drivers/mtd/nand/rb750_nand.c +--- linux-2.6.36.orig/drivers/mtd/nand/rb750_nand.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/mtd/nand/rb750_nand.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,360 @@ +/* -+ * SPI driver for the Vitesse VSC7385 ethernet switch -+ * -+ * Copyright (C) 2009 Gabor Juhos ++ * NAND flash driver for the MikroTik RouterBOARD 750 + * -+ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Copyright (C) 2010 Gabor Juhos + * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ + -+#include -+#include +#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define DRV_NAME "spi-vsc7385" -+#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" -+#define DRV_VERSION "0.1.0" -+ -+#define VSC73XX_BLOCK_MAC 0x1 -+#define VSC73XX_BLOCK_2 0x2 -+#define VSC73XX_BLOCK_MII 0x3 -+#define VSC73XX_BLOCK_4 0x4 -+#define VSC73XX_BLOCK_5 0x5 -+#define VSC73XX_BLOCK_SYSTEM 0x7 -+ -+#define VSC73XX_SUBBLOCK_PORT_0 0 -+#define VSC73XX_SUBBLOCK_PORT_1 1 -+#define VSC73XX_SUBBLOCK_PORT_2 2 -+#define VSC73XX_SUBBLOCK_PORT_3 3 -+#define VSC73XX_SUBBLOCK_PORT_4 4 -+#define VSC73XX_SUBBLOCK_PORT_MAC 6 -+ -+/* MAC Block registers */ -+#define VSC73XX_MAC_CFG 0x0 -+#define VSC73XX_ADVPORTM 0x19 -+#define VSC73XX_RXOCT 0x50 -+#define VSC73XX_TXOCT 0x51 -+#define VSC73XX_C_RX0 0x52 -+#define VSC73XX_C_RX1 0x53 -+#define VSC73XX_C_RX2 0x54 -+#define VSC73XX_C_TX0 0x55 -+#define VSC73XX_C_TX1 0x56 -+#define VSC73XX_C_TX2 0x57 -+#define VSC73XX_C_CFG 0x58 -+ -+/* MAC_CFG register bits */ -+#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) -+#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) -+#define VSC73XX_MAC_CFG_TX_EN (1 << 28) -+#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) -+#define VSC73XX_MAC_CFG_FDX (1 << 18) -+#define VSC73XX_MAC_CFG_GIGE (1 << 17) -+#define VSC73XX_MAC_CFG_RX_EN (1 << 16) -+#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) -+#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) -+#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) -+#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) -+#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) -+#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) -+#define VSC73XX_MAC_CFG_BIT2 (1 << 2) -+#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) -+ -+/* ADVPORTM register bits */ -+#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) -+#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) -+#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) -+#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) -+#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) -+#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) -+#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) -+#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) -+ -+/* MII Block registers */ -+#define VSC73XX_MII_STAT 0x0 -+#define VSC73XX_MII_CMD 0x1 -+#define VSC73XX_MII_DATA 0x2 -+ -+/* System Block registers */ -+#define VSC73XX_ICPU_SIPAD 0x01 -+#define VSC73XX_ICPU_CLOCK_DELAY 0x05 -+#define VSC73XX_ICPU_CTRL 0x10 -+#define VSC73XX_ICPU_ADDR 0x11 -+#define VSC73XX_ICPU_SRAM 0x12 -+#define VSC73XX_ICPU_MBOX_VAL 0x15 -+#define VSC73XX_ICPU_MBOX_SET 0x16 -+#define VSC73XX_ICPU_MBOX_CLR 0x17 -+#define VSC73XX_ICPU_CHIPID 0x18 -+#define VSC73XX_ICPU_GPIO 0x34 -+ -+#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) -+#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) -+#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) -+#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) -+#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) -+#define VSC73XX_ICPU_CTRL_SRST (1 << 0) -+ -+#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 -+#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff -+#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 -+#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf -+#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 -+#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 -+ -+#define VSC73XX_CMD_MODE_READ 0 -+#define VSC73XX_CMD_MODE_WRITE 1 -+#define VSC73XX_CMD_MODE_SHIFT 4 -+#define VSC73XX_CMD_BLOCK_SHIFT 5 -+#define VSC73XX_CMD_BLOCK_MASK 0x7 -+#define VSC73XX_CMD_SUBBLOCK_MASK 0xf -+ -+#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) -+#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) -+ -+#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ -+ VSC73XX_ICPU_CTRL_BOOT_EN | \ -+ VSC73XX_ICPU_CTRL_EXT_ACC_EN) ++#include ++#include ++#include ++#include ++#include + -+#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ -+ VSC73XX_ICPU_CTRL_BOOT_EN | \ -+ VSC73XX_ICPU_CTRL_CLK_EN | \ -+ VSC73XX_ICPU_CTRL_SRST) ++#include ++#include + -+#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ -+ VSC73XX_ADVPORTM_EXC_COL_CONT | \ -+ VSC73XX_ADVPORTM_EXT_PORT | \ -+ VSC73XX_ADVPORTM_INV_GTX | \ -+ VSC73XX_ADVPORTM_ENA_GTX | \ -+ VSC73XX_ADVPORTM_DDR_MODE | \ -+ VSC73XX_ADVPORTM_IO_LOOPBACK | \ -+ VSC73XX_ADVPORTM_HOST_LOOPBACK) ++#define DRV_NAME "rb750-nand" ++#define DRV_VERSION "0.1.0" ++#define DRV_DESC "NAND flash driver for the RouterBOARD 750" + -+#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ -+ VSC73XX_ADVPORTM_ENA_GTX | \ -+ VSC73XX_ADVPORTM_DDR_MODE) ++#define RB750_NAND_IO0 BIT(RB750_GPIO_NAND_IO0) ++#define RB750_NAND_ALE BIT(RB750_GPIO_NAND_ALE) ++#define RB750_NAND_CLE BIT(RB750_GPIO_NAND_CLE) ++#define RB750_NAND_NRE BIT(RB750_GPIO_NAND_NRE) ++#define RB750_NAND_NWE BIT(RB750_GPIO_NAND_NWE) ++#define RB750_NAND_RDY BIT(RB750_GPIO_NAND_RDY) ++#define RB750_NAND_NCE BIT(RB750_GPIO_NAND_NCE) + -+#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ -+ VSC73XX_MAC_CFG_MAC_RX_RST | \ -+ VSC73XX_MAC_CFG_MAC_TX_RST) ++#define RB750_NAND_DATA_SHIFT 1 ++#define RB750_NAND_DATA_BITS (0xff << RB750_NAND_DATA_SHIFT) ++#define RB750_NAND_INPUT_BITS (RB750_NAND_DATA_BITS | RB750_NAND_RDY) ++#define RB750_NAND_OUTPUT_BITS (RB750_NAND_ALE | RB750_NAND_CLE | \ ++ RB750_NAND_NRE | RB750_NAND_NWE | \ ++ RB750_NAND_NCE) + -+#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ -+ VSC73XX_MAC_CFG_FDX | \ -+ VSC73XX_MAC_CFG_GIGE | \ -+ VSC73XX_MAC_CFG_RX_EN) ++struct rb750_nand_info { ++ struct nand_chip chip; ++ struct mtd_info mtd; ++}; + -+#define VSC73XX_RESET_DELAY 100 ++/* ++ * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader ++ * will not be able to find the kernel that we load. ++ */ ++static struct nand_ecclayout rb750_nand_ecclayout = { ++ .eccbytes = 6, ++ .eccpos = { 8, 9, 10, 13, 14, 15 }, ++ .oobavail = 9, ++ .oobfree = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } } ++}; + -+struct vsc7385 { -+ struct spi_device *spi; -+ struct mutex lock; -+ struct vsc7385_platform_data *pdata; ++static struct mtd_partition rb750_nand_partitions[] = { ++ { ++ .name = "booter", ++ .offset = 0, ++ .size = (256 * 1024), ++ .mask_flags = MTD_WRITEABLE, ++ }, { ++ .name = "kernel", ++ .offset = (256 * 1024), ++ .size = (4 * 1024 * 1024) - (256 * 1024), ++ }, { ++ .name = "rootfs", ++ .offset = MTDPART_OFS_NXTBLK, ++ .size = MTDPART_SIZ_FULL, ++ }, +}; + -+static int vsc7385_is_addr_valid(u8 block, u8 subblock) ++static void rb750_nand_write(const u8 *buf, unsigned len) +{ -+ switch (block) { -+ case VSC73XX_BLOCK_MAC: -+ switch (subblock) { -+ case 0 ... 4: -+ case 6: -+ return 1; -+ } -+ break; -+ -+ case VSC73XX_BLOCK_2: -+ case VSC73XX_BLOCK_SYSTEM: -+ switch (subblock) { -+ case 0: -+ return 1; -+ } -+ break; ++ void __iomem *base = ar71xx_gpio_base; ++ u32 out; ++ unsigned i; + -+ case VSC73XX_BLOCK_MII: -+ case VSC73XX_BLOCK_4: -+ case VSC73XX_BLOCK_5: -+ switch (subblock) { -+ case 0 ... 1: -+ return 1; -+ } -+ break; -+ } ++ /* set data lines to output mode */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_DATA_BITS, ++ base + GPIO_REG_OE); + -+ return 0; -+} ++ out = __raw_readl(base + GPIO_REG_OUT); ++ out &= ~(RB750_NAND_DATA_BITS | RB750_NAND_NWE); ++ for (i = 0; i != len; i++) { ++ u32 data; + -+static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) -+{ -+ u8 ret; ++ data = buf[i]; ++ data <<= RB750_NAND_DATA_SHIFT; ++ data |= out; ++ __raw_writel(data, base + GPIO_REG_OUT); + -+ ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; -+ ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; -+ ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; ++ __raw_writel(data | RB750_NAND_NWE, base + GPIO_REG_OUT); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_OUT); ++ } + -+ return ret; ++ /* set data lines to input mode */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~RB750_NAND_DATA_BITS, ++ base + GPIO_REG_OE); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_OE); +} + -+static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, -+ u32 *value) ++static int rb750_nand_read_verify(u8 *read_buf, unsigned len, ++ const u8 *verify_buf) +{ -+ u8 cmd[4]; -+ u8 buf[4]; -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ int err; -+ -+ if (!vsc7385_is_addr_valid(block, subblock)) -+ return -EINVAL; -+ -+ spi_message_init(&m); -+ -+ memset(&t, 0, sizeof(t)); -+ -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); ++ void __iomem *base = ar71xx_gpio_base; ++ unsigned i; + -+ t[1].rx_buf = buf; -+ t[1].len = sizeof(buf); -+ spi_message_add_tail(&t[1], &m); ++ for (i = 0; i < len; i++) { ++ u8 data; + -+ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); -+ cmd[1] = reg; -+ cmd[2] = 0; -+ cmd[3] = 0; ++ /* activate RE line */ ++ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_CLEAR); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_CLEAR); + -+ mutex_lock(&vsc->lock); -+ err = spi_sync(vsc->spi, &m); -+ mutex_unlock(&vsc->lock); ++ /* read input lines */ ++ data = __raw_readl(base + GPIO_REG_IN) >> RB750_NAND_DATA_SHIFT; + -+ if (err) -+ return err; ++ /* deactivate RE line */ ++ __raw_writel(RB750_NAND_NRE, base + GPIO_REG_SET); + -+ *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | -+ (((u32) buf[2]) << 8) | ((u32) buf[3]); ++ if (read_buf) ++ read_buf[i] = data; ++ else if (verify_buf && verify_buf[i] != data) ++ return -EFAULT; ++ } + + return 0; +} + -+ -+static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, -+ u32 value) ++static void rb750_nand_select_chip(struct mtd_info *mtd, int chip) +{ -+ u8 cmd[2]; -+ u8 buf[4]; -+ struct spi_transfer t[2]; -+ struct spi_message m; -+ int err; ++ void __iomem *base = ar71xx_gpio_base; ++ u32 func; + -+ if (!vsc7385_is_addr_valid(block, subblock)) -+ return -EINVAL; ++ func = __raw_readl(base + GPIO_REG_FUNC); ++ if (chip >= 0) { ++ /* disable latch */ ++ rb750_latch_change(RB750_LVC573_LE, 0); + -+ spi_message_init(&m); ++ /* disable alternate functions */ ++ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_JTAG_DISABLE, ++ AR724X_GPIO_FUNC_SPI_EN); + -+ memset(&t, 0, sizeof(t)); ++ /* set input mode for data lines */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ++ ~RB750_NAND_INPUT_BITS, ++ base + GPIO_REG_OE); + -+ t[0].tx_buf = cmd; -+ t[0].len = sizeof(cmd); -+ spi_message_add_tail(&t[0], &m); ++ /* deactivate RE and WE lines */ ++ __raw_writel(RB750_NAND_NRE | RB750_NAND_NWE, ++ base + GPIO_REG_SET); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_SET); + -+ t[1].tx_buf = buf; -+ t[1].len = sizeof(buf); -+ spi_message_add_tail(&t[1], &m); ++ /* activate CE line */ ++ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_CLEAR); ++ } else { ++ /* deactivate CE line */ ++ __raw_writel(RB750_NAND_NCE, base + GPIO_REG_SET); ++ /* flush write */ ++ (void) __raw_readl(base + GPIO_REG_SET); + -+ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); -+ cmd[1] = reg; ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | ++ RB750_NAND_IO0 | RB750_NAND_RDY, ++ base + GPIO_REG_OE); + -+ buf[0] = (value >> 24) & 0xff; -+ buf[1] = (value >> 16) & 0xff; -+ buf[2] = (value >> 8) & 0xff; -+ buf[3] = value & 0xff; ++ /* restore alternate functions */ ++ ar71xx_gpio_function_setup(AR724X_GPIO_FUNC_SPI_EN, ++ AR724X_GPIO_FUNC_JTAG_DISABLE); + -+ mutex_lock(&vsc->lock); -+ err = spi_sync(vsc->spi, &m); -+ mutex_unlock(&vsc->lock); ++ /* enable latch */ ++ rb750_latch_change(0, RB750_LVC573_LE); ++ } ++} + -+ return err; ++static int rb750_nand_dev_ready(struct mtd_info *mtd) ++{ ++ void __iomem *base = ar71xx_gpio_base; ++ ++ return !!(__raw_readl(base + GPIO_REG_IN) & RB750_NAND_RDY); +} + -+static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, -+ u8 subblock, u8 reg, u32 value, -+ u32 read_mask, u32 read_val) ++static void rb750_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, ++ unsigned int ctrl) +{ -+ struct spi_device *spi = vsc->spi; -+ u32 t; -+ int err; ++ if (ctrl & NAND_CTRL_CHANGE) { ++ void __iomem *base = ar71xx_gpio_base; ++ u32 t; + -+ err = vsc7385_write(vsc, block, subblock, reg, value); -+ if (err) -+ return err; ++ t = __raw_readl(base + GPIO_REG_OUT); + -+ err = vsc7385_read(vsc, block, subblock, reg, &t); -+ if (err) -+ return err; ++ t &= ~(RB750_NAND_CLE | RB750_NAND_ALE); ++ t |= (ctrl & NAND_CLE) ? RB750_NAND_CLE : 0; ++ t |= (ctrl & NAND_ALE) ? RB750_NAND_ALE : 0; + -+ if ((t & read_mask) != read_val) { -+ dev_err(&spi->dev, "register write error\n"); -+ return -EIO; ++ __raw_writel(t, base + GPIO_REG_OUT); ++ /* flush write */ ++ __raw_readl(base + GPIO_REG_OUT); + } + -+ return 0; ++ if (cmd != NAND_CMD_NONE) { ++ u8 t = cmd; ++ rb750_nand_write(&t, 1); ++ } +} + -+static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) ++static u8 rb750_nand_read_byte(struct mtd_info *mtd) +{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, val); ++ u8 data = 0; ++ rb750_nand_read_verify(&data, 1, NULL); ++ return data; +} + -+static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) ++static void rb750_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ -+ return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, val); ++ rb750_nand_read_verify(buf, len, NULL); +} + -+static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) -+{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, -+ VSC73XX_ICPU_CTRL_STOP); ++static void rb750_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len) ++{ ++ rb750_nand_write(buf, len); +} + -+static inline int vsc7385_icpu_start(struct vsc7385 *vsc) ++static int rb750_nand_verify_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ -+ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, -+ VSC73XX_ICPU_CTRL_START); ++ return rb750_nand_read_verify(NULL, len, buf); +} + -+static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) ++static void __init rb750_nand_gpio_init(void) +{ -+ int rc; ++ void __iomem *base = ar71xx_gpio_base; ++ u32 out; + -+ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, -+ 0x0000); -+ if (rc) -+ dev_err(&vsc->spi->dev, -+ "could not reset microcode, err=%d\n", rc); ++ out = __raw_readl(base + GPIO_REG_OUT); + -+ return rc; ++ /* setup output levels */ ++ __raw_writel(RB750_NAND_NCE | RB750_NAND_NRE | RB750_NAND_NWE, ++ base + GPIO_REG_SET); ++ ++ __raw_writel(RB750_NAND_ALE | RB750_NAND_CLE, ++ base + GPIO_REG_CLEAR); ++ ++ /* setup input lines */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) & ~(RB750_NAND_INPUT_BITS), ++ base + GPIO_REG_OE); ++ ++ /* setup output lines */ ++ __raw_writel(__raw_readl(base + GPIO_REG_OE) | RB750_NAND_OUTPUT_BITS, ++ base + GPIO_REG_OE); ++ ++ rb750_latch_change(~out & RB750_NAND_IO0, out & RB750_NAND_IO0); +} + -+static int vsc7385_upload_ucode(struct vsc7385 *vsc) ++static int __init rb750_nand_probe(struct platform_device *pdev) +{ -+ struct spi_device *spi = vsc->spi; -+ const struct firmware *firmware; -+ char *ucode_name; -+ unsigned char *dp; -+ unsigned int curVal; -+ int i; -+ int diffs; -+ int rc; ++ struct rb750_nand_info *info; ++ int ret; + -+ ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name -+ : "vsc7385_ucode.bin"; -+ rc = request_firmware(&firmware, ucode_name, &spi->dev); -+ if (rc) { -+ dev_err(&spi->dev, "request_firmware failed, err=%d\n", -+ rc); -+ return rc; -+ } ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + -+ rc = vsc7385_icpu_stop(vsc); -+ if (rc) -+ goto out; ++ rb750_nand_gpio_init(); + -+ rc = vsc7385_icpu_reset(vsc); -+ if (rc) -+ goto out; ++ info = kzalloc(sizeof(*info), GFP_KERNEL); ++ if (!info) ++ return -ENOMEM; + -+ dev_info(&spi->dev, "uploading microcode...\n"); ++ info->chip.priv = &info; ++ info->mtd.priv = &info->chip; ++ info->mtd.owner = THIS_MODULE; + -+ dp = (unsigned char *) firmware->data; -+ for (i = 0; i < firmware->size; i++) { -+ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_SRAM, *dp++); -+ if (rc) { -+ dev_err(&spi->dev, "could not load microcode, err=%d\n", -+ rc); -+ goto out; -+ } ++ info->chip.select_chip = rb750_nand_select_chip; ++ info->chip.cmd_ctrl = rb750_nand_cmd_ctrl; ++ info->chip.dev_ready = rb750_nand_dev_ready; ++ info->chip.read_byte = rb750_nand_read_byte; ++ info->chip.write_buf = rb750_nand_write_buf; ++ info->chip.read_buf = rb750_nand_read_buf; ++ info->chip.verify_buf = rb750_nand_verify_buf; ++ ++ info->chip.chip_delay = 25; ++ info->chip.ecc.mode = NAND_ECC_SOFT; ++ info->chip.options |= NAND_NO_AUTOINCR; ++ ++ platform_set_drvdata(pdev, info); ++ ++ ret = nand_scan_ident(&info->mtd, 1); ++ if (ret) { ++ ret = -ENXIO; ++ goto err_free_info; + } + -+ rc = vsc7385_icpu_reset(vsc); -+ if (rc) -+ goto out; ++ if (info->mtd.writesize == 512) ++ info->chip.ecc.layout = &rb750_nand_ecclayout; + -+ dev_info(&spi->dev, "verifying microcode...\n"); ++ ret = nand_scan_tail(&info->mtd); ++ if (ret) { ++ return -ENXIO; ++ goto err_set_drvdata; ++ } + -+ dp = (unsigned char *) firmware->data; -+ diffs = 0; -+ for (i = 0; i < firmware->size; i++) { -+ rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_SRAM, &curVal); -+ if (rc) { -+ dev_err(&spi->dev, "could not read microcode %d\n",rc); -+ goto out; -+ } ++#ifdef CONFIG_MTD_PARTITIONS ++ ret = add_mtd_partitions(&info->mtd, rb750_nand_partitions, ++ ARRAY_SIZE(rb750_nand_partitions)); ++#else ++ ret = add_mtd_device(&info->mtd); ++#endif ++ if (ret) ++ goto err_release_nand; + -+ if (curVal > 0xff) { -+ dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", -+ i, *dp, curVal); -+ rc = -EIO; -+ goto out; -+ } ++ return 0; + -+ if ((curVal & 0xff) != *dp) { -+ diffs++; -+ dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", -+ i, *dp, curVal); ++ err_release_nand: ++ nand_release(&info->mtd); ++ err_set_drvdata: ++ platform_set_drvdata(pdev, NULL); ++ err_free_info: ++ kfree(info); ++ return ret; ++} + -+ if (diffs > 4) -+ break; -+ } -+ dp++; -+ } ++static int __devexit rb750_nand_remove(struct platform_device *pdev) ++{ ++ struct rb750_nand_info *info = platform_get_drvdata(pdev); + -+ if (diffs) { -+ dev_err(&spi->dev, "microcode verification failed\n"); -+ rc = -EIO; -+ goto out; -+ } ++ nand_release(&info->mtd); ++ platform_set_drvdata(pdev, NULL); ++ kfree(info); + -+ dev_info(&spi->dev, "microcode uploaded\n"); ++ return 0; ++} + -+ rc = vsc7385_icpu_start(vsc); ++static struct platform_driver rb750_nand_driver = { ++ .probe = rb750_nand_probe, ++ .remove = __devexit_p(rb750_nand_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; + -+ out: -+ release_firmware(firmware); -+ return rc; ++static int __init rb750_nand_init(void) ++{ ++ return platform_driver_register(&rb750_nand_driver); +} + -+static int vsc7385_setup(struct vsc7385 *vsc) ++static void __exit rb750_nand_exit(void) +{ -+ struct vsc7385_platform_data *pdata = vsc->pdata; -+ u32 t; -+ int err; ++ platform_driver_unregister(&rb750_nand_driver); ++} + -+ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CLOCK_DELAY, -+ VSC7385_CLOCK_DELAY, -+ VSC7385_CLOCK_DELAY_MASK, -+ VSC7385_CLOCK_DELAY); -+ if (err) -+ goto err; ++module_init(rb750_nand_init); ++module_exit(rb750_nand_exit); + -+ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, -+ VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, -+ VSC7385_ADVPORTM_INIT, -+ VSC7385_ADVPORTM_MASK, -+ VSC7385_ADVPORTM_INIT); -+ if (err) -+ goto err; ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.36.orig/drivers/mtd/wrt160nl_part.c linux-2.6.36/drivers/mtd/wrt160nl_part.c +--- linux-2.6.36.orig/drivers/mtd/wrt160nl_part.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/mtd/wrt160nl_part.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,181 @@ ++/* ++ * Copyright (C) 2009 Christian Daniel ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ++ * ++ * TRX flash partition table. ++ * Based on ar7 map by Felix Fietkau ++ * ++ */ + -+ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, -+ VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); -+ if (err) -+ goto err; ++#include ++#include ++#include ++ ++#include ++#include ++ ++struct cybertan_header { ++ char magic[4]; ++ u8 res1[4]; ++ char fw_date[3]; ++ char fw_ver[3]; ++ char id[4]; ++ char hw_ver; ++ char unused; ++ u8 flags[2]; ++ u8 res2[10]; ++}; ++ ++#define TRX_PARTS 6 ++#define TRX_MAGIC 0x30524448 ++#define TRX_MAX_OFFSET 3 ++ ++struct trx_header { ++ uint32_t magic; /* "HDR0" */ ++ uint32_t len; /* Length of file including header */ ++ uint32_t crc32; /* 32-bit CRC from flag_version to end of file */ ++ uint32_t flag_version; /* 0:15 flags, 16:31 version */ ++ uint32_t offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */ ++}; + -+ t = VSC73XX_MAC_CFG_INIT; -+ t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); -+ t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); -+ if (pdata->mac_cfg.bit2) -+ t |= VSC73XX_MAC_CFG_BIT2; ++#define IH_MAGIC 0x27051956 /* Image Magic Number */ ++#define IH_NMLEN 32 /* Image Name Length */ + -+ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, -+ VSC73XX_MAC_CFG, t); -+ if (err) -+ goto err; ++struct uimage_header { ++ uint32_t ih_magic; /* Image Header Magic Number */ ++ uint32_t ih_hcrc; /* Image Header CRC Checksum */ ++ uint32_t ih_time; /* Image Creation Timestamp */ ++ uint32_t ih_size; /* Image Data Size */ ++ uint32_t ih_load; /* Data» Load Address */ ++ uint32_t ih_ep; /* Entry Point Address */ ++ uint32_t ih_dcrc; /* Image Data CRC Checksum */ ++ uint8_t ih_os; /* Operating System */ ++ uint8_t ih_arch; /* CPU architecture */ ++ uint8_t ih_type; /* Image Type */ ++ uint8_t ih_comp; /* Compression Type */ ++ uint8_t ih_name[IH_NMLEN]; /* Image Name */ ++}; + -+ return 0; ++struct wrt160nl_header { ++ struct cybertan_header cybertan; ++ struct trx_header trx; ++ struct uimage_header uimage; ++} __attribute__ ((packed)); + -+ err: -+ return err; -+} ++static struct mtd_partition trx_parts[TRX_PARTS]; + -+static int vsc7385_detect(struct vsc7385 *vsc) ++static int wrt160nl_parse_partitions(struct mtd_info *master, ++ struct mtd_partition **pparts, ++ unsigned long origin) +{ -+ struct spi_device *spi = vsc->spi; -+ u32 t; -+ u32 id; -+ u32 rev; -+ int err; ++ struct wrt160nl_header *header; ++ struct trx_header *theader; ++ struct uimage_header *uheader; ++ size_t retlen; ++ unsigned int kernel_len; ++ int ret; + -+ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_MBOX_VAL, &t); -+ if (err) { -+ dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); -+ return err; ++ header = vmalloc(sizeof(*header)); ++ if (!header) { ++ return -ENOMEM; ++ goto out; + } + -+ if (t == 0xffffffff) { -+ dev_dbg(&spi->dev, "assert chip reset\n"); -+ if (vsc->pdata->reset) -+ vsc->pdata->reset(); ++ ret = master->read(master, 4 * master->erasesize, sizeof(*header), ++ &retlen, (void *) header); ++ if (ret) ++ goto free_hdr; + ++ if (retlen != sizeof(*header)) { ++ ret = -EIO; ++ goto free_hdr; + } + -+ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, -+ VSC73XX_ICPU_CHIPID, &t); -+ if (err) { -+ dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); -+ return err; ++ if (strncmp(header->cybertan.magic, "NL16", 4) != 0) { ++ printk(KERN_NOTICE "%s: no WRT160NL signature found\n", ++ master->name); ++ goto free_hdr; + } + -+ id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; -+ switch (id) { -+ case VSC73XX_ICPU_CHIPID_ID_7385: -+ case VSC73XX_ICPU_CHIPID_ID_7395: -+ break; -+ default: -+ dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); -+ return -ENODEV; ++ theader = &header->trx; ++ if (le32_to_cpu(theader->magic) != TRX_MAGIC) { ++ printk(KERN_NOTICE "%s: no TRX header found\n", master->name); ++ goto free_hdr; + } + -+ rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & -+ VSC73XX_ICPU_CHIPID_REV_MASK; -+ dev_info(&spi->dev, "VSC%04X (rev. %d) switch found \n", id, rev); -+ -+ return 0; -+} ++ uheader = &header->uimage; ++ if (uheader->ih_magic != IH_MAGIC) { ++ printk(KERN_NOTICE "%s: no uImage found\n", master->name); ++ goto free_hdr; ++ } + -+static int __devinit vsc7385_probe(struct spi_device *spi) -+{ -+ struct vsc7385 *vsc; -+ struct vsc7385_platform_data *pdata; -+ int err; ++ kernel_len = le32_to_cpu(theader->offsets[1]) + sizeof(struct cybertan_header); + -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); ++ trx_parts[0].name = "u-boot"; ++ trx_parts[0].offset = 0; ++ trx_parts[0].size = 4 * master->erasesize; ++ trx_parts[0].mask_flags = MTD_WRITEABLE; + -+ pdata = spi->dev.platform_data; -+ if (!pdata) { -+ dev_err(&spi->dev, "no platform data specified\n"); -+ return-ENODEV; -+ } ++ trx_parts[1].name = "kernel"; ++ trx_parts[1].offset = trx_parts[0].offset + trx_parts[0].size; ++ trx_parts[1].size = kernel_len; ++ trx_parts[1].mask_flags = 0; + -+ vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); -+ if (!vsc) { -+ dev_err(&spi->dev, "no memory for private data\n"); -+ return-ENOMEM; -+ } ++ trx_parts[2].name = "rootfs"; ++ trx_parts[2].offset = trx_parts[1].offset + trx_parts[1].size; ++ trx_parts[2].size = master->size - 6 * master->erasesize - trx_parts[1].size; ++ trx_parts[2].mask_flags = 0; + -+ mutex_init(&vsc->lock); -+ vsc->pdata = pdata; -+ vsc->spi = spi_dev_get(spi); -+ dev_set_drvdata(&spi->dev, vsc); ++ trx_parts[3].name = "nvram"; ++ trx_parts[3].offset = master->size - 2 * master->erasesize; ++ trx_parts[3].size = master->erasesize; ++ trx_parts[3].mask_flags = MTD_WRITEABLE; + -+ spi->mode = SPI_MODE_0; -+ spi->bits_per_word = 8; -+ err = spi_setup(spi); -+ if (err) { -+ dev_err(&spi->dev, "spi_setup failed, err=%d \n", err); -+ goto err_drvdata; -+ } ++ trx_parts[4].name = "art"; ++ trx_parts[4].offset = master->size - master->erasesize; ++ trx_parts[4].size = master->erasesize; ++ trx_parts[4].mask_flags = MTD_WRITEABLE; + -+ err = vsc7385_detect(vsc); -+ if (err) { -+ dev_err(&spi->dev, "no chip found, err=%d \n", err); -+ goto err_drvdata; -+ } ++ trx_parts[5].name = "firmware"; ++ trx_parts[5].offset = 4 * master->erasesize; ++ trx_parts[5].size = master->size - 6 * master->erasesize; ++ trx_parts[5].mask_flags = 0; + -+ err = vsc7385_upload_ucode(vsc); -+ if (err) -+ goto err_drvdata; ++ *pparts = trx_parts; ++ ret = TRX_PARTS; + -+ err = vsc7385_setup(vsc); -+ if (err) -+ goto err_drvdata; ++ free_hdr: ++ vfree(header); ++ out: ++ return ret; ++} + -+ return 0; ++static struct mtd_part_parser wrt160nl_parser = { ++ .owner = THIS_MODULE, ++ .parse_fn = wrt160nl_parse_partitions, ++ .name = "wrt160nl", ++}; + -+ err_drvdata: -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(vsc); -+ return err; ++static int __init wrt160nl_parser_init(void) ++{ ++ return register_mtd_parser(&wrt160nl_parser); +} + -+static int __devexit vsc7385_remove(struct spi_device *spi) -+{ -+ struct vsc7385_data *vsc; ++module_init(wrt160nl_parser_init); + -+ vsc = dev_get_drvdata(&spi->dev); -+ dev_set_drvdata(&spi->dev, NULL); -+ kfree(vsc); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Christian Daniel "); +diff -Nur linux-2.6.36.orig/drivers/net/Kconfig linux-2.6.36/drivers/net/Kconfig +--- linux-2.6.36.orig/drivers/net/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/net/Kconfig 2010-11-18 21:16:14.000000000 +0100 +@@ -2045,6 +2045,8 @@ + + The safe and default value for this is N. + ++source drivers/net/ag71xx/Kconfig + -+ return 0; -+} + config DL2K + tristate "DL2000/TC902x-based Gigabit Ethernet support" + depends on PCI +diff -Nur linux-2.6.36.orig/drivers/net/Makefile linux-2.6.36/drivers/net/Makefile +--- linux-2.6.36.orig/drivers/net/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/net/Makefile 2010-11-18 21:16:15.000000000 +0100 +@@ -109,6 +109,7 @@ + # end link order section + # + ++obj-$(CONFIG_AG71XX) += ag71xx/ + obj-$(CONFIG_SUNDANCE) += sundance.o + obj-$(CONFIG_HAMACHI) += hamachi.o + obj-$(CONFIG_NET) += Space.o loopback.o +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/Kconfig linux-2.6.36/drivers/net/ag71xx/Kconfig +--- linux-2.6.36.orig/drivers/net/ag71xx/Kconfig 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/Kconfig 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,33 @@ ++config AG71XX ++ tristate "Atheros AR71xx built-in ethernet mac support" ++ depends on ATHEROS_AR71XX ++ select PHYLIB ++ help ++ If you wish to compile a kernel for AR71xx/91xx and enable ++ ethernet support, then you should always answer Y to this. + -+static struct spi_driver vsc7385_driver = { -+ .driver = { -+ .name = DRV_NAME, -+ .bus = &spi_bus_type, -+ .owner = THIS_MODULE, -+ }, -+ .probe = vsc7385_probe, -+ .remove = __devexit_p(vsc7385_remove), -+}; ++if AG71XX ++ ++config AG71XX_DEBUG ++ bool "Atheros AR71xx built-in ethernet driver debugging" ++ default n ++ help ++ Atheros AR71xx built-in ethernet driver debugging messages. ++ ++config AG71XX_DEBUG_FS ++ bool "Atheros AR71xx built-in ethernet driver debugfs support" ++ depends on DEBUG_FS ++ default n ++ help ++ Say Y, if you need access to various statistics provided by ++ the ag71xx driver. ++ ++config AG71XX_AR8216_SUPPORT ++ bool "special support for the Atheros AR8216 switch" ++ default n ++ default y if AR71XX_MACH_WNR2000 || AR71XX_MACH_MZK_W04NU ++ help ++ Say 'y' here if you want to enable special support for the ++ Atheros AR8216 switch found on some boards. + -+static int __init vsc7385_init(void) -+{ -+ return spi_register_driver(&vsc7385_driver); -+} -+module_init(vsc7385_init); ++endif +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/Makefile linux-2.6.36/drivers/net/ag71xx/Makefile +--- linux-2.6.36.orig/drivers/net/ag71xx/Makefile 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/Makefile 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,14 @@ ++# ++# Makefile for the Atheros AR71xx built-in ethernet macs ++# + -+static void __exit vsc7385_exit(void) -+{ -+ spi_unregister_driver(&vsc7385_driver); -+} -+module_exit(vsc7385_exit); ++ag71xx-y += ag71xx_main.o ++ag71xx-y += ag71xx_ethtool.o ++ag71xx-y += ag71xx_phy.o ++ag71xx-y += ag71xx_mdio.o + -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos "); -+MODULE_LICENSE("GPL v2"); ++ag71xx-$(CONFIG_AG71XX_DEBUG_FS) += ag71xx_debugfs.o ++ag71xx-$(CONFIG_AG71XX_AR8216_SUPPORT) += ag71xx_ar8216.o + -diff -Nur linux-2.6.35.7.orig/drivers/usb/host/ehci-ar71xx.c linux-2.6.35.7/drivers/usb/host/ehci-ar71xx.c ---- linux-2.6.35.7.orig/drivers/usb/host/ehci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/usb/host/ehci-ar71xx.c 2010-10-14 20:28:01.285601150 +0200 -@@ -0,0 +1,242 @@ ++obj-$(CONFIG_AG71XX) += ag71xx.o ++ +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx.h linux-2.6.36/drivers/net/ag71xx/ag71xx.h +--- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/ag71xx.h 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,500 @@ +/* -+ * Bus Glue for Atheros AR71xx built-in EHCI controller. ++ * Atheros AR71xx built-in ethernet mac driver + * + * Copyright (C) 2008-2010 Gabor Juhos + * Copyright (C) 2008 Imre Kaloz + * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Copyright (C) 2007 Atheros Communications, Inc. ++ * Based on Atheros' AG7100 driver + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + -+#include -+#include -+ -+#include -+ -+extern int usb_disabled(void); -+ -+static int ehci_ar71xx_init(struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ int ret; -+ -+ ehci->caps = hcd->regs; -+ ehci->regs = hcd->regs + -+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); -+ -+ ehci->sbrn = 0x20; -+ ehci->has_synopsys_hc_bug = 1; -+ -+ ehci_reset(ehci); -+ -+ ret = ehci_init(hcd); -+ if (ret) -+ return ret; -+ -+ ehci_port_power(ehci, 0); -+ -+ return 0; -+} -+ -+static int ehci_ar91xx_init(struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ int ret; -+ -+ ehci->caps = hcd->regs + 0x100; -+ ehci->regs = hcd->regs + 0x100 + -+ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); -+ -+ hcd->has_tt = 1; -+ ehci->sbrn = 0x20; -+ -+ ehci_reset(ehci); ++#ifndef __AG71XX_H ++#define __AG71XX_H + -+ ret = ehci_init(hcd); -+ if (ret) -+ return ret; ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+ ehci_port_power(ehci, 0); ++#include + -+ return 0; -+} ++#include ++#include + -+static int ehci_ar71xx_probe(const struct hc_driver *driver, -+ struct usb_hcd **hcd_out, -+ struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd; -+ struct resource *res; -+ int irq; -+ int ret; ++#define ETH_FCS_LEN 4 + -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } -+ irq = res->start; ++#define AG71XX_DRV_NAME "ag71xx" ++#define AG71XX_DRV_VERSION "0.5.35" + -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no base address specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } ++#define AG71XX_NAPI_WEIGHT 64 ++#define AG71XX_OOM_REFILL (1 + HZ/10) + -+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); -+ if (!hcd) -+ return -ENOMEM; ++#define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE) ++#define AG71XX_INT_TX (AG71XX_INT_TX_PS) ++#define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF) + -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = res->end - res->start + 1; ++#define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX) ++#define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL) + -+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { -+ dev_dbg(&pdev->dev, "controller already in use\n"); -+ ret = -EBUSY; -+ goto err_put_hcd; -+ } ++#define AG71XX_TX_FIFO_LEN 2048 ++#define AG71XX_TX_MTU_LEN 1536 ++#define AG71XX_RX_PKT_RESERVE 64 ++#define AG71XX_RX_PKT_SIZE \ ++ (AG71XX_RX_PKT_RESERVE + ETH_HLEN + ETH_FRAME_LEN + ETH_FCS_LEN) + -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_dbg(&pdev->dev, "error mapping memory\n"); -+ ret = -EFAULT; -+ goto err_release_region; -+ } ++#define AG71XX_TX_RING_SIZE 64 ++#define AG71XX_TX_THRES_STOP (AG71XX_TX_RING_SIZE - 4) ++#define AG71XX_TX_THRES_WAKEUP \ ++ (AG71XX_TX_RING_SIZE - (AG71XX_TX_RING_SIZE / 4)) + -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); -+ if (ret) -+ goto err_iounmap; ++#define AG71XX_RX_RING_SIZE 128 + -+ return 0; ++#ifdef CONFIG_AG71XX_DEBUG ++#define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args) ++#else ++#define DBG(fmt, args...) do {} while (0) ++#endif + -+ err_iounmap: -+ iounmap(hcd->regs); ++#define ag71xx_assert(_cond) \ ++do { \ ++ if (_cond) \ ++ break; \ ++ printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \ ++ BUG(); \ ++} while (0) + -+ err_release_region: -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ err_put_hcd: -+ usb_put_hcd(hcd); -+ return ret; -+} ++struct ag71xx_desc { ++ u32 data; ++ u32 ctrl; ++#define DESC_EMPTY BIT(31) ++#define DESC_MORE BIT(24) ++#define DESC_PKTLEN_M 0xfff ++ u32 next; ++ u32 pad; ++} __attribute__((aligned(4))); + -+static void ehci_ar71xx_remove(struct usb_hcd *hcd, -+ struct platform_device *pdev) -+{ -+ usb_remove_hcd(hcd); -+ iounmap(hcd->regs); -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ usb_put_hcd(hcd); -+} ++struct ag71xx_buf { ++ struct sk_buff *skb; ++ struct ag71xx_desc *desc; ++ dma_addr_t dma_addr; ++ u32 pad; ++}; + -+static const struct hc_driver ehci_ar71xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR71xx built-in EHCI controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), ++struct ag71xx_ring { ++ struct ag71xx_buf *buf; ++ u8 *descs_cpu; ++ dma_addr_t descs_dma; ++ unsigned int desc_size; ++ unsigned int curr; ++ unsigned int dirty; ++ unsigned int size; ++}; + -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, ++struct ag71xx_mdio { ++ struct mii_bus *mii_bus; ++ int mii_irq[PHY_MAX_ADDR]; ++ void __iomem *mdio_base; ++ struct ag71xx_mdio_platform_data *pdata; ++}; + -+ .reset = ehci_ar71xx_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, ++struct ag71xx_int_stats { ++ unsigned long rx_pr; ++ unsigned long rx_be; ++ unsigned long rx_of; ++ unsigned long tx_ps; ++ unsigned long tx_be; ++ unsigned long tx_ur; ++ unsigned long total; ++}; + -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, ++struct ag71xx_napi_stats { ++ unsigned long napi_calls; ++ unsigned long rx_count; ++ unsigned long rx_packets; ++ unsigned long rx_packets_max; ++ unsigned long tx_count; ++ unsigned long tx_packets; ++ unsigned long tx_packets_max; + -+ .get_frame_number = ehci_get_frame, ++ unsigned long rx[AG71XX_NAPI_WEIGHT + 1]; ++ unsigned long tx[AG71XX_NAPI_WEIGHT + 1]; ++}; + -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+#ifdef CONFIG_PM -+ .hub_suspend = ehci_hub_suspend, -+ .hub_resume = ehci_hub_resume, -+#endif -+ .relinquish_port = ehci_relinquish_port, -+ .port_handed_over = ehci_port_handed_over, ++struct ag71xx_debug { ++ struct dentry *debugfs_dir; ++ struct dentry *debugfs_int_stats; ++ struct dentry *debugfs_napi_stats; + -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, ++ struct ag71xx_int_stats int_stats; ++ struct ag71xx_napi_stats napi_stats; +}; + -+static const struct hc_driver ehci_ar91xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR91xx built-in EHCI controller", -+ .hcd_priv_size = sizeof(struct ehci_hcd), -+ .irq = ehci_irq, -+ .flags = HCD_MEMORY | HCD_USB2, ++struct ag71xx { ++ void __iomem *mac_base; ++ void __iomem *mii_ctrl; + -+ .reset = ehci_ar91xx_init, -+ .start = ehci_run, -+ .stop = ehci_stop, -+ .shutdown = ehci_shutdown, ++ spinlock_t lock; ++ struct platform_device *pdev; ++ struct net_device *dev; ++ struct napi_struct napi; ++ u32 msg_enable; + -+ .urb_enqueue = ehci_urb_enqueue, -+ .urb_dequeue = ehci_urb_dequeue, -+ .endpoint_disable = ehci_endpoint_disable, -+ .endpoint_reset = ehci_endpoint_reset, ++ struct ag71xx_ring rx_ring; ++ struct ag71xx_ring tx_ring; + -+ .get_frame_number = ehci_get_frame, ++ struct mii_bus *mii_bus; ++ struct phy_device *phy_dev; + -+ .hub_status_data = ehci_hub_status_data, -+ .hub_control = ehci_hub_control, -+#ifdef CONFIG_PM -+ .hub_suspend = ehci_hub_suspend, -+ .hub_resume = ehci_hub_resume, -+#endif -+ .relinquish_port = ehci_relinquish_port, -+ .port_handed_over = ehci_port_handed_over, ++ unsigned int link; ++ unsigned int speed; ++ int duplex; + -+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, -+}; ++ struct work_struct restart_work; ++ struct timer_list oom_timer; + -+static int ehci_ar71xx_driver_probe(struct platform_device *pdev) -+{ -+ struct ar71xx_ehci_platform_data *pdata; -+ struct usb_hcd *hcd = NULL; -+ int ret; ++#ifdef CONFIG_AG71XX_DEBUG_FS ++ struct ag71xx_debug debug; ++#endif ++}; + -+ if (usb_disabled()) -+ return -ENODEV; ++extern struct ethtool_ops ag71xx_ethtool_ops; ++void ag71xx_link_adjust(struct ag71xx *ag); + -+ pdata = pdev->dev.platform_data; -+ if (!pdata) { -+ dev_err(&pdev->dev, "no platform data specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; -+ } ++int ag71xx_mdio_driver_init(void) __init; ++void ag71xx_mdio_driver_exit(void); + -+ if (pdata->is_ar91xx) -+ ret = ehci_ar71xx_probe(&ehci_ar91xx_hc_driver, &hcd, pdev); -+ else -+ ret = ehci_ar71xx_probe(&ehci_ar71xx_hc_driver, &hcd, pdev); ++int ag71xx_phy_connect(struct ag71xx *ag); ++void ag71xx_phy_disconnect(struct ag71xx *ag); ++void ag71xx_phy_start(struct ag71xx *ag); ++void ag71xx_phy_stop(struct ag71xx *ag); + -+ return ret; ++static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag) ++{ ++ return ag->pdev->dev.platform_data; +} + -+static int ehci_ar71xx_driver_remove(struct platform_device *pdev) ++static inline int ag71xx_desc_empty(struct ag71xx_desc *desc) +{ -+ struct usb_hcd *hcd = platform_get_drvdata(pdev); -+ -+ ehci_ar71xx_remove(hcd, pdev); -+ return 0; ++ return ((desc->ctrl & DESC_EMPTY) != 0); +} + -+MODULE_ALIAS("platform:ar71xx-ehci"); -+ -+static struct platform_driver ehci_ar71xx_driver = { -+ .probe = ehci_ar71xx_driver_probe, -+ .remove = ehci_ar71xx_driver_remove, -+ .driver = { -+ .name = "ar71xx-ehci", -+ } -+}; -diff -Nur linux-2.6.35.7.orig/drivers/usb/host/ehci-hcd.c linux-2.6.35.7/drivers/usb/host/ehci-hcd.c ---- linux-2.6.35.7.orig/drivers/usb/host/ehci-hcd.c 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/usb/host/ehci-hcd.c 2010-10-14 20:28:01.328100455 +0200 -@@ -1158,6 +1158,11 @@ - #define PLATFORM_DRIVER ehci_atmel_driver - #endif - -+#ifdef CONFIG_USB_EHCI_AR71XX -+#include "ehci-ar71xx.c" -+#define PLATFORM_DRIVER ehci_ar71xx_driver -+#endif -+ - #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ - !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ - !defined(XILINX_OF_PLATFORM_DRIVER) -diff -Nur linux-2.6.35.7.orig/drivers/usb/host/ehci-hcd.c.orig linux-2.6.35.7/drivers/usb/host/ehci-hcd.c.orig ---- linux-2.6.35.7.orig/drivers/usb/host/ehci-hcd.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/usb/host/ehci-hcd.c.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,1278 @@ -+/* -+ * Copyright (c) 2000-2004 by David Brownell -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, but -+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software Foundation, -+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include ++static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc) ++{ ++ return (desc->ctrl & DESC_PKTLEN_M); ++} + -+#include -+#include -+#include -+#include -+#include ++/* Register offsets */ ++#define AG71XX_REG_MAC_CFG1 0x0000 ++#define AG71XX_REG_MAC_CFG2 0x0004 ++#define AG71XX_REG_MAC_IPG 0x0008 ++#define AG71XX_REG_MAC_HDX 0x000c ++#define AG71XX_REG_MAC_MFL 0x0010 ++#define AG71XX_REG_MII_CFG 0x0020 ++#define AG71XX_REG_MII_CMD 0x0024 ++#define AG71XX_REG_MII_ADDR 0x0028 ++#define AG71XX_REG_MII_CTRL 0x002c ++#define AG71XX_REG_MII_STATUS 0x0030 ++#define AG71XX_REG_MII_IND 0x0034 ++#define AG71XX_REG_MAC_IFCTL 0x0038 ++#define AG71XX_REG_MAC_ADDR1 0x0040 ++#define AG71XX_REG_MAC_ADDR2 0x0044 ++#define AG71XX_REG_FIFO_CFG0 0x0048 ++#define AG71XX_REG_FIFO_CFG1 0x004c ++#define AG71XX_REG_FIFO_CFG2 0x0050 ++#define AG71XX_REG_FIFO_CFG3 0x0054 ++#define AG71XX_REG_FIFO_CFG4 0x0058 ++#define AG71XX_REG_FIFO_CFG5 0x005c ++#define AG71XX_REG_FIFO_RAM0 0x0060 ++#define AG71XX_REG_FIFO_RAM1 0x0064 ++#define AG71XX_REG_FIFO_RAM2 0x0068 ++#define AG71XX_REG_FIFO_RAM3 0x006c ++#define AG71XX_REG_FIFO_RAM4 0x0070 ++#define AG71XX_REG_FIFO_RAM5 0x0074 ++#define AG71XX_REG_FIFO_RAM6 0x0078 ++#define AG71XX_REG_FIFO_RAM7 0x007c + -+/*-------------------------------------------------------------------------*/ ++#define AG71XX_REG_TX_CTRL 0x0180 ++#define AG71XX_REG_TX_DESC 0x0184 ++#define AG71XX_REG_TX_STATUS 0x0188 ++#define AG71XX_REG_RX_CTRL 0x018c ++#define AG71XX_REG_RX_DESC 0x0190 ++#define AG71XX_REG_RX_STATUS 0x0194 ++#define AG71XX_REG_INT_ENABLE 0x0198 ++#define AG71XX_REG_INT_STATUS 0x019c + -+/* -+ * EHCI hc_driver implementation ... experimental, incomplete. -+ * Based on the final 1.0 register interface specification. -+ * -+ * USB 2.0 shows up in upcoming www.pcmcia.org technology. -+ * First was PCMCIA, like ISA; then CardBus, which is PCI. -+ * Next comes "CardBay", using USB 2.0 signals. -+ * -+ * Contains additional contributions by Brad Hards, Rory Bolt, and others. -+ * Special thanks to Intel and VIA for providing host controllers to -+ * test this driver on, and Cypress (including In-System Design) for -+ * providing early devices for those host controllers to talk to! -+ */ ++#define MAC_CFG1_TXE BIT(0) /* Tx Enable */ ++#define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */ ++#define MAC_CFG1_RXE BIT(2) /* Rx Enable */ ++#define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */ ++#define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */ ++#define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */ ++#define MAC_CFG1_LB BIT(8) /* Loopback mode */ ++#define MAC_CFG1_SR BIT(31) /* Soft Reset */ + -+#define DRIVER_AUTHOR "David Brownell" -+#define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver" ++#define MAC_CFG2_FDX BIT(0) ++#define MAC_CFG2_CRC_EN BIT(1) ++#define MAC_CFG2_PAD_CRC_EN BIT(2) ++#define MAC_CFG2_LEN_CHECK BIT(4) ++#define MAC_CFG2_HUGE_FRAME_EN BIT(5) ++#define MAC_CFG2_IF_1000 BIT(9) ++#define MAC_CFG2_IF_10_100 BIT(8) + -+static const char hcd_name [] = "ehci_hcd"; ++#define FIFO_CFG0_WTM BIT(0) /* Watermark Module */ ++#define FIFO_CFG0_RXS BIT(1) /* Rx System Module */ ++#define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */ ++#define FIFO_CFG0_TXS BIT(3) /* Tx System Module */ ++#define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */ ++#define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \ ++ | FIFO_CFG0_TXS | FIFO_CFG0_TXF) + ++#define FIFO_CFG0_ENABLE_SHIFT 8 + -+#undef VERBOSE_DEBUG -+#undef EHCI_URB_TRACE ++#define FIFO_CFG4_DE BIT(0) /* Drop Event */ ++#define FIFO_CFG4_DV BIT(1) /* RX_DV Event */ ++#define FIFO_CFG4_FC BIT(2) /* False Carrier */ ++#define FIFO_CFG4_CE BIT(3) /* Code Error */ ++#define FIFO_CFG4_CR BIT(4) /* CRC error */ ++#define FIFO_CFG4_LM BIT(5) /* Length Mismatch */ ++#define FIFO_CFG4_LO BIT(6) /* Length out of range */ ++#define FIFO_CFG4_OK BIT(7) /* Packet is OK */ ++#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */ ++#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */ ++#define FIFO_CFG4_DR BIT(10) /* Dribble */ ++#define FIFO_CFG4_LE BIT(11) /* Long Event */ ++#define FIFO_CFG4_CF BIT(12) /* Control Frame */ ++#define FIFO_CFG4_PF BIT(13) /* Pause Frame */ ++#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */ ++#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */ ++#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */ ++#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */ + -+#ifdef DEBUG -+#define EHCI_STATS -+#endif ++#define FIFO_CFG5_DE BIT(0) /* Drop Event */ ++#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */ ++#define FIFO_CFG5_FC BIT(2) /* False Carrier */ ++#define FIFO_CFG5_CE BIT(3) /* Code Error */ ++#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */ ++#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */ ++#define FIFO_CFG5_OK BIT(6) /* Packet is OK */ ++#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */ ++#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */ ++#define FIFO_CFG5_DR BIT(9) /* Dribble */ ++#define FIFO_CFG5_CF BIT(10) /* Control Frame */ ++#define FIFO_CFG5_PF BIT(11) /* Pause Frame */ ++#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */ ++#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */ ++#define FIFO_CFG5_LE BIT(14) /* Long Event */ ++#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */ ++#define FIFO_CFG5_16 BIT(16) /* unknown */ ++#define FIFO_CFG5_17 BIT(17) /* unknown */ ++#define FIFO_CFG5_SF BIT(18) /* Short Frame */ ++#define FIFO_CFG5_BM BIT(19) /* Byte Mode */ + -+/* magic numbers that can affect system performance */ -+#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ -+#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ -+#define EHCI_TUNE_RL_TT 0 -+#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ -+#define EHCI_TUNE_MULT_TT 1 -+#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */ ++#define AG71XX_INT_TX_PS BIT(0) ++#define AG71XX_INT_TX_UR BIT(1) ++#define AG71XX_INT_TX_BE BIT(3) ++#define AG71XX_INT_RX_PR BIT(4) ++#define AG71XX_INT_RX_OF BIT(6) ++#define AG71XX_INT_RX_BE BIT(7) + -+#define EHCI_IAA_MSECS 10 /* arbitrary */ -+#define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */ -+#define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */ -+#define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */ ++#define MAC_IFCTL_SPEED BIT(16) + -+/* Initial IRQ latency: faster than hw default */ -+static int log2_irq_thresh = 0; // 0 to 6 -+module_param (log2_irq_thresh, int, S_IRUGO); -+MODULE_PARM_DESC (log2_irq_thresh, "log2 IRQ latency, 1-64 microframes"); ++#define MII_CFG_CLK_DIV_4 0 ++#define MII_CFG_CLK_DIV_6 2 ++#define MII_CFG_CLK_DIV_8 3 ++#define MII_CFG_CLK_DIV_10 4 ++#define MII_CFG_CLK_DIV_14 5 ++#define MII_CFG_CLK_DIV_20 6 ++#define MII_CFG_CLK_DIV_28 7 ++#define MII_CFG_RESET BIT(31) + -+/* initial park setting: slower than hw default */ -+static unsigned park = 0; -+module_param (park, uint, S_IRUGO); -+MODULE_PARM_DESC (park, "park setting; 1-3 back-to-back async packets"); ++#define MII_CMD_WRITE 0x0 ++#define MII_CMD_READ 0x1 ++#define MII_ADDR_SHIFT 8 ++#define MII_IND_BUSY BIT(0) ++#define MII_IND_INVALID BIT(2) + -+/* for flakey hardware, ignore overcurrent indicators */ -+static int ignore_oc = 0; -+module_param (ignore_oc, bool, S_IRUGO); -+MODULE_PARM_DESC (ignore_oc, "ignore bogus hardware overcurrent indications"); ++#define TX_CTRL_TXE BIT(0) /* Tx Enable */ + -+#define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT) ++#define TX_STATUS_PS BIT(0) /* Packet Sent */ ++#define TX_STATUS_UR BIT(1) /* Tx Underrun */ ++#define TX_STATUS_BE BIT(3) /* Bus Error */ + -+/*-------------------------------------------------------------------------*/ ++#define RX_CTRL_RXE BIT(0) /* Rx Enable */ + -+#include "ehci.h" -+#include "ehci-dbg.c" ++#define RX_STATUS_PR BIT(0) /* Packet Received */ ++#define RX_STATUS_OF BIT(2) /* Rx Overflow */ ++#define RX_STATUS_BE BIT(3) /* Bus Error */ + -+/*-------------------------------------------------------------------------*/ ++#define MII_CTRL_IF_MASK 3 ++#define MII_CTRL_SPEED_SHIFT 4 ++#define MII_CTRL_SPEED_MASK 3 ++#define MII_CTRL_SPEED_10 0 ++#define MII_CTRL_SPEED_100 1 ++#define MII_CTRL_SPEED_1000 2 + -+static void -+timer_action(struct ehci_hcd *ehci, enum ehci_timer_action action) ++static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg) +{ -+ /* Don't override timeouts which shrink or (later) disable -+ * the async ring; just the I/O watchdog. Note that if a -+ * SHRINK were pending, OFF would never be requested. -+ */ -+ if (timer_pending(&ehci->watchdog) -+ && ((BIT(TIMER_ASYNC_SHRINK) | BIT(TIMER_ASYNC_OFF)) -+ & ehci->actions)) -+ return; -+ -+ if (!test_and_set_bit(action, &ehci->actions)) { -+ unsigned long t; ++ switch (reg) { ++ case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL: ++ case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS: ++ break; + -+ switch (action) { -+ case TIMER_IO_WATCHDOG: -+ if (!ehci->need_io_watchdog) -+ return; -+ t = EHCI_IO_JIFFIES; -+ break; -+ case TIMER_ASYNC_OFF: -+ t = EHCI_ASYNC_JIFFIES; -+ break; -+ /* case TIMER_ASYNC_SHRINK: */ -+ default: -+ /* add a jiffie since we synch against the -+ * 8 KHz uframe counter. -+ */ -+ t = DIV_ROUND_UP(EHCI_SHRINK_FRAMES * HZ, 1000) + 1; -+ break; -+ } -+ mod_timer(&ehci->watchdog, t + jiffies); ++ default: ++ BUG(); + } +} + -+/*-------------------------------------------------------------------------*/ -+ -+/* -+ * handshake - spin reading hc until handshake completes or fails -+ * @ptr: address of hc register to be read -+ * @mask: bits to look at in result of read -+ * @done: value of those bits when handshake succeeds -+ * @usec: timeout in microseconds -+ * -+ * Returns negative errno, or zero on success -+ * -+ * Success happens when the "mask" bits have the specified value (hardware -+ * handshake done). There are two failure modes: "usec" have passed (major -+ * hardware flakeout), or the register reads as all-ones (hardware removed). -+ * -+ * That last failure should_only happen in cases like physical cardbus eject -+ * before driver shutdown. But it also seems to be caused by bugs in cardbus -+ * bridge shutdown: shutting down the bridge before the devices using it. -+ */ -+static int handshake (struct ehci_hcd *ehci, void __iomem *ptr, -+ u32 mask, u32 done, int usec) ++static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value) +{ -+ u32 result; ++ ag71xx_check_reg_offset(ag, reg); + -+ do { -+ result = ehci_readl(ehci, ptr); -+ if (result == ~(u32)0) /* card removed */ -+ return -ENODEV; -+ result &= mask; -+ if (result == done) -+ return 0; -+ udelay (1); -+ usec--; -+ } while (usec > 0); -+ return -ETIMEDOUT; ++ __raw_writel(value, ag->mac_base + reg); ++ /* flush write */ ++ (void) __raw_readl(ag->mac_base + reg); +} + -+/* force HC to halt state from unknown (EHCI spec section 2.3) */ -+static int ehci_halt (struct ehci_hcd *ehci) ++static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg) +{ -+ u32 temp = ehci_readl(ehci, &ehci->regs->status); -+ -+ /* disable any irqs left enabled by previous code */ -+ ehci_writel(ehci, 0, &ehci->regs->intr_enable); -+ -+ if ((temp & STS_HALT) != 0) -+ return 0; ++ ag71xx_check_reg_offset(ag, reg); + -+ temp = ehci_readl(ehci, &ehci->regs->command); -+ temp &= ~CMD_RUN; -+ ehci_writel(ehci, temp, &ehci->regs->command); -+ return handshake (ehci, &ehci->regs->status, -+ STS_HALT, STS_HALT, 16 * 125); ++ return __raw_readl(ag->mac_base + reg); +} + -+static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr, -+ u32 mask, u32 done, int usec) ++static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask) +{ -+ int error; ++ void __iomem *r; + -+ error = handshake(ehci, ptr, mask, done, usec); -+ if (error) { -+ ehci_halt(ehci); -+ ehci_to_hcd(ehci)->state = HC_STATE_HALT; -+ ehci_err(ehci, "force halt; handshake %p %08x %08x -> %d\n", -+ ptr, mask, done, error); -+ } ++ ag71xx_check_reg_offset(ag, reg); + -+ return error; ++ r = ag->mac_base + reg; ++ __raw_writel(__raw_readl(r) | mask, r); ++ /* flush write */ ++ (void)__raw_readl(r); +} + -+/* put TDI/ARC silicon into EHCI mode */ -+static void tdi_reset (struct ehci_hcd *ehci) ++static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask) +{ -+ u32 __iomem *reg_ptr; -+ u32 tmp; ++ void __iomem *r; + -+ reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); -+ tmp = ehci_readl(ehci, reg_ptr); -+ tmp |= USBMODE_CM_HC; -+ /* The default byte access to MMR space is LE after -+ * controller reset. Set the required endian mode -+ * for transfer buffers to match the host microprocessor -+ */ -+ if (ehci_big_endian_mmio(ehci)) -+ tmp |= USBMODE_BE; -+ ehci_writel(ehci, tmp, reg_ptr); ++ ag71xx_check_reg_offset(ag, reg); ++ ++ r = ag->mac_base + reg; ++ __raw_writel(__raw_readl(r) & ~mask, r); ++ /* flush write */ ++ (void) __raw_readl(r); +} + -+/* reset a non-running (STS_HALT == 1) controller */ -+static int ehci_reset (struct ehci_hcd *ehci) ++static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints) +{ -+ int retval; -+ u32 command = ehci_readl(ehci, &ehci->regs->command); -+ -+ /* If the EHCI debug controller is active, special care must be -+ * taken before and after a host controller reset */ -+ if (ehci->debug && !dbgp_reset_prep()) -+ ehci->debug = NULL; -+ -+ command |= CMD_RESET; -+ dbg_cmd (ehci, "reset", command); -+ ehci_writel(ehci, command, &ehci->regs->command); -+ ehci_to_hcd(ehci)->state = HC_STATE_HALT; -+ ehci->next_statechange = jiffies; -+ retval = handshake (ehci, &ehci->regs->command, -+ CMD_RESET, 0, 250 * 1000); -+ -+ if (ehci->has_hostpc) { -+ ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, -+ (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); -+ ehci_writel(ehci, TXFIFO_DEFAULT, -+ (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING)); -+ } -+ if (retval) -+ return retval; -+ -+ if (ehci_is_TDI(ehci)) -+ tdi_reset (ehci); -+ -+ if (ehci->debug) -+ dbgp_external_startup(); -+ -+ return retval; ++ ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints); +} + -+/* idle the controller (from running) */ -+static void ehci_quiesce (struct ehci_hcd *ehci) ++static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints) +{ -+ u32 temp; ++ ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints); ++} + -+#ifdef DEBUG -+ if (!HC_IS_RUNNING (ehci_to_hcd(ehci)->state)) -+ BUG (); -+#endif ++static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + -+ /* wait for any schedule enables/disables to take effect */ -+ temp = ehci_readl(ehci, &ehci->regs->command) << 10; -+ temp &= STS_ASS | STS_PSS; -+ if (handshake_on_error_set_halt(ehci, &ehci->regs->status, -+ STS_ASS | STS_PSS, temp, 16 * 125)) ++ if (pdata->is_ar724x) + return; + -+ /* then disable anything that's still active */ -+ temp = ehci_readl(ehci, &ehci->regs->command); -+ temp &= ~(CMD_ASE | CMD_IAAD | CMD_PSE); -+ ehci_writel(ehci, temp, &ehci->regs->command); ++ __raw_writel(value, ag->mii_ctrl); + -+ /* hardware can take 16 microframes to turn off ... */ -+ handshake_on_error_set_halt(ehci, &ehci->regs->status, -+ STS_ASS | STS_PSS, 0, 16 * 125); ++ /* flush write */ ++ __raw_readl(ag->mii_ctrl); +} + -+/*-------------------------------------------------------------------------*/ -+ -+static void end_unlink_async(struct ehci_hcd *ehci); -+static void ehci_work(struct ehci_hcd *ehci); -+ -+#include "ehci-hub.c" -+#include "ehci-mem.c" -+#include "ehci-q.c" -+#include "ehci-sched.c" -+ -+/*-------------------------------------------------------------------------*/ -+ -+static void ehci_iaa_watchdog(unsigned long param) ++static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag) +{ -+ struct ehci_hcd *ehci = (struct ehci_hcd *) param; -+ unsigned long flags; -+ -+ spin_lock_irqsave (&ehci->lock, flags); -+ -+ /* Lost IAA irqs wedge things badly; seen first with a vt8235. -+ * So we need this watchdog, but must protect it against both -+ * (a) SMP races against real IAA firing and retriggering, and -+ * (b) clean HC shutdown, when IAA watchdog was pending. -+ */ -+ if (ehci->reclaim -+ && !timer_pending(&ehci->iaa_watchdog) -+ && HC_IS_RUNNING(ehci_to_hcd(ehci)->state)) { -+ u32 cmd, status; -+ -+ /* If we get here, IAA is *REALLY* late. It's barely -+ * conceivable that the system is so busy that CMD_IAAD -+ * is still legitimately set, so let's be sure it's -+ * clear before we read STS_IAA. (The HC should clear -+ * CMD_IAAD when it sets STS_IAA.) -+ */ -+ cmd = ehci_readl(ehci, &ehci->regs->command); -+ if (cmd & CMD_IAAD) -+ ehci_writel(ehci, cmd & ~CMD_IAAD, -+ &ehci->regs->command); -+ -+ /* If IAA is set here it either legitimately triggered -+ * before we cleared IAAD above (but _way_ late, so we'll -+ * still count it as lost) ... or a silicon erratum: -+ * - VIA seems to set IAA without triggering the IRQ; -+ * - IAAD potentially cleared without setting IAA. -+ */ -+ status = ehci_readl(ehci, &ehci->regs->status); -+ if ((status & STS_IAA) || !(cmd & CMD_IAAD)) { -+ COUNT (ehci->stats.lost_iaa); -+ ehci_writel(ehci, STS_IAA, &ehci->regs->status); -+ } ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + -+ ehci_vdbg(ehci, "IAA watchdog: status %x cmd %x\n", -+ status, cmd); -+ end_unlink_async(ehci); -+ } ++ if (pdata->is_ar724x) ++ return 0xffffffff; + -+ spin_unlock_irqrestore(&ehci->lock, flags); ++ return __raw_readl(ag->mii_ctrl); +} + -+static void ehci_watchdog(unsigned long param) ++static void inline ag71xx_mii_ctrl_set_if(struct ag71xx *ag, ++ unsigned int mii_if) +{ -+ struct ehci_hcd *ehci = (struct ehci_hcd *) param; -+ unsigned long flags; -+ -+ spin_lock_irqsave(&ehci->lock, flags); -+ -+ /* stop async processing after it's idled a bit */ -+ if (test_bit (TIMER_ASYNC_OFF, &ehci->actions)) -+ start_unlink_async (ehci, ehci->async); -+ -+ /* ehci could run by timer, without IRQs ... */ -+ ehci_work (ehci); ++ u32 t; + -+ spin_unlock_irqrestore (&ehci->lock, flags); ++ t = ag71xx_mii_ctrl_rr(ag); ++ t &= ~(MII_CTRL_IF_MASK); ++ t |= (mii_if & MII_CTRL_IF_MASK); ++ ag71xx_mii_ctrl_wr(ag, t); +} + -+/* On some systems, leaving remote wakeup enabled prevents system shutdown. -+ * The firmware seems to think that powering off is a wakeup event! -+ * This routine turns off remote wakeup and everything else, on all ports. -+ */ -+static void ehci_turn_off_all_ports(struct ehci_hcd *ehci) ++static void inline ag71xx_mii_ctrl_set_speed(struct ag71xx *ag, ++ unsigned int speed) +{ -+ int port = HCS_N_PORTS(ehci->hcs_params); ++ u32 t; + -+ while (port--) -+ ehci_writel(ehci, PORT_RWC_BITS, -+ &ehci->regs->port_status[port]); ++ t = ag71xx_mii_ctrl_rr(ag); ++ t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT); ++ t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT; ++ ag71xx_mii_ctrl_wr(ag, t); +} + -+/* -+ * Halt HC, turn off all ports, and let the BIOS use the companion controllers. -+ * Should be called with ehci->lock held. -+ */ -+static void ehci_silence_controller(struct ehci_hcd *ehci) ++#ifdef CONFIG_AG71XX_AR8216_SUPPORT ++void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb); ++int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, ++ int pktlen); ++static inline int ag71xx_has_ar8216(struct ag71xx *ag) +{ -+ ehci_halt(ehci); -+ ehci_turn_off_all_ports(ehci); -+ -+ /* make BIOS/etc use companion controller during reboot */ -+ ehci_writel(ehci, 0, &ehci->regs->configured_flag); -+ -+ /* unblock posted writes */ -+ ehci_readl(ehci, &ehci->regs->configured_flag); ++ return ag71xx_get_pdata(ag)->has_ar8216; +} -+ -+/* ehci_shutdown kick in for silicon on any bus (not just pci, etc). -+ * This forcibly disables dma and IRQs, helping kexec and other cases -+ * where the next system software may expect clean state. -+ */ -+static void ehci_shutdown(struct usb_hcd *hcd) ++#else ++static inline void ag71xx_add_ar8216_header(struct ag71xx *ag, ++ struct sk_buff *skb) +{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ -+ del_timer_sync(&ehci->watchdog); -+ del_timer_sync(&ehci->iaa_watchdog); -+ -+ spin_lock_irq(&ehci->lock); -+ ehci_silence_controller(ehci); -+ spin_unlock_irq(&ehci->lock); +} + -+static void ehci_port_power (struct ehci_hcd *ehci, int is_on) ++static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag, ++ struct sk_buff *skb, ++ int pktlen) +{ -+ unsigned port; -+ -+ if (!HCS_PPC (ehci->hcs_params)) -+ return; -+ -+ ehci_dbg (ehci, "...power%s ports...\n", is_on ? "up" : "down"); -+ for (port = HCS_N_PORTS (ehci->hcs_params); port > 0; ) -+ (void) ehci_hub_control(ehci_to_hcd(ehci), -+ is_on ? SetPortFeature : ClearPortFeature, -+ USB_PORT_FEAT_POWER, -+ port--, NULL, 0); -+ /* Flush those writes */ -+ ehci_readl(ehci, &ehci->regs->command); -+ msleep(20); ++ return 0; ++} ++static inline int ag71xx_has_ar8216(struct ag71xx *ag) ++{ ++ return 0; +} ++#endif + -+/*-------------------------------------------------------------------------*/ ++#ifdef CONFIG_AG71XX_DEBUG_FS ++int ag71xx_debugfs_root_init(void); ++void ag71xx_debugfs_root_exit(void); ++int ag71xx_debugfs_init(struct ag71xx *ag); ++void ag71xx_debugfs_exit(struct ag71xx *ag); ++void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status); ++void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx); ++#else ++static inline int ag71xx_debugfs_root_init(void) { return 0; } ++static inline void ag71xx_debugfs_root_exit(void) {} ++static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; } ++static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {} ++static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, ++ u32 status) {} ++static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, ++ int rx, int tx) {} ++#endif /* CONFIG_AG71XX_DEBUG_FS */ + ++#endif /* _AG71XX_H */ +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_ar8216.c linux-2.6.36/drivers/net/ag71xx/ag71xx_ar8216.c +--- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_ar8216.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/ag71xx_ar8216.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,44 @@ +/* -+ * ehci_work is called from some interrupts, timers, and so on. -+ * it calls driver completion functions, after dropping ehci->lock. ++ * Atheros AR71xx built-in ethernet mac driver ++ * Special support for the Atheros ar8216 switch chip ++ * ++ * Copyright (C) 2009-2010 Gabor Juhos ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ -+static void ehci_work (struct ehci_hcd *ehci) -+{ -+ timer_action_done (ehci, TIMER_IO_WATCHDOG); + -+ /* another CPU may drop ehci->lock during a schedule scan while -+ * it reports urb completions. this flag guards against bogus -+ * attempts at re-entrant schedule scanning. -+ */ -+ if (ehci->scanning) -+ return; -+ ehci->scanning = 1; -+ scan_async (ehci); -+ if (ehci->next_uframe != -1) -+ scan_periodic (ehci); -+ ehci->scanning = 0; -+ -+ /* the IO watchdog guards against hardware or driver bugs that -+ * misplace IRQs, and should let us run completely without IRQs. -+ * such lossage has been observed on both VT6202 and VT8235. -+ */ -+ if (HC_IS_RUNNING (ehci_to_hcd(ehci)->state) && -+ (ehci->async->qh_next.ptr != NULL || -+ ehci->periodic_sched != 0)) -+ timer_action (ehci, TIMER_IO_WATCHDOG); ++#include "ag71xx.h" ++ ++#define AR8216_PACKET_TYPE_MASK 0xf ++#define AR8216_PACKET_TYPE_NORMAL 0 ++ ++#define AR8216_HEADER_LEN 2 ++ ++void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb) ++{ ++ skb_push(skb, AR8216_HEADER_LEN); ++ skb->data[0] = 0x10; ++ skb->data[1] = 0x80; +} + -+/* -+ * Called when the ehci_hcd module is removed. -+ */ -+static void ehci_stop (struct usb_hcd *hcd) ++int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb, ++ int pktlen) +{ -+ struct ehci_hcd *ehci = hcd_to_ehci (hcd); ++ u8 type; + -+ ehci_dbg (ehci, "stop\n"); ++ type = skb->data[1] & AR8216_PACKET_TYPE_MASK; ++ switch (type) { ++ case AR8216_PACKET_TYPE_NORMAL: ++ break; + -+ /* no more interrupts ... */ -+ del_timer_sync (&ehci->watchdog); -+ del_timer_sync(&ehci->iaa_watchdog); ++ default: ++ return -EINVAL; ++ } + -+ spin_lock_irq(&ehci->lock); -+ if (HC_IS_RUNNING (hcd->state)) -+ ehci_quiesce (ehci); ++ skb_pull(skb, AR8216_HEADER_LEN); ++ return 0; ++} +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_debugfs.c linux-2.6.36/drivers/net/ag71xx/ag71xx_debugfs.c +--- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_debugfs.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/ag71xx_debugfs.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,197 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ ehci_silence_controller(ehci); -+ ehci_reset (ehci); -+ spin_unlock_irq(&ehci->lock); ++#include + -+ remove_companion_file(ehci); -+ remove_debug_files (ehci); ++#include "ag71xx.h" + -+ /* root hub is shut down separately (first, when possible) */ -+ spin_lock_irq (&ehci->lock); -+ if (ehci->async) -+ ehci_work (ehci); -+ spin_unlock_irq (&ehci->lock); -+ ehci_mem_cleanup (ehci); ++static struct dentry *ag71xx_debugfs_root; + -+#ifdef EHCI_STATS -+ ehci_dbg (ehci, "irq normal %ld err %ld reclaim %ld (lost %ld)\n", -+ ehci->stats.normal, ehci->stats.error, ehci->stats.reclaim, -+ ehci->stats.lost_iaa); -+ ehci_dbg (ehci, "complete %ld unlink %ld\n", -+ ehci->stats.complete, ehci->stats.unlink); -+#endif ++static int ag71xx_debugfs_generic_open(struct inode *inode, struct file *file) ++{ ++ file->private_data = inode->i_private; ++ return 0; ++} + -+ dbg_status (ehci, "ehci_stop completed", -+ ehci_readl(ehci, &ehci->regs->status)); ++void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status) ++{ ++ if (status) ++ ag->debug.int_stats.total++; ++ if (status & AG71XX_INT_TX_PS) ++ ag->debug.int_stats.tx_ps++; ++ if (status & AG71XX_INT_TX_UR) ++ ag->debug.int_stats.tx_ur++; ++ if (status & AG71XX_INT_TX_BE) ++ ag->debug.int_stats.tx_be++; ++ if (status & AG71XX_INT_RX_PR) ++ ag->debug.int_stats.rx_pr++; ++ if (status & AG71XX_INT_RX_OF) ++ ag->debug.int_stats.rx_of++; ++ if (status & AG71XX_INT_RX_BE) ++ ag->debug.int_stats.rx_be++; +} + -+/* one-time init, only for memory state */ -+static int ehci_init(struct usb_hcd *hcd) ++static ssize_t read_file_int_stats(struct file *file, char __user *user_buf, ++ size_t count, loff_t *ppos) +{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ u32 temp; -+ int retval; -+ u32 hcc_params; -+ struct ehci_qh_hw *hw; -+ -+ spin_lock_init(&ehci->lock); -+ -+ /* -+ * keep io watchdog by default, those good HCDs could turn off it later -+ */ -+ ehci->need_io_watchdog = 1; -+ init_timer(&ehci->watchdog); -+ ehci->watchdog.function = ehci_watchdog; -+ ehci->watchdog.data = (unsigned long) ehci; -+ -+ init_timer(&ehci->iaa_watchdog); -+ ehci->iaa_watchdog.function = ehci_iaa_watchdog; -+ ehci->iaa_watchdog.data = (unsigned long) ehci; ++#define PR_INT_STAT(_label, _field) \ ++ len += snprintf(buf + len, sizeof(buf) - len, \ ++ "%20s: %10lu\n", _label, ag->debug.int_stats._field); + -+ /* -+ * hw default: 1K periodic list heads, one per frame. -+ * periodic_size can shrink by USBCMD update if hcc_params allows. -+ */ -+ ehci->periodic_size = DEFAULT_I_TDPS; -+ INIT_LIST_HEAD(&ehci->cached_itd_list); -+ INIT_LIST_HEAD(&ehci->cached_sitd_list); -+ if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0) -+ return retval; -+ -+ /* controllers may cache some of the periodic schedule ... */ -+ hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); -+ if (HCC_ISOC_CACHE(hcc_params)) // full frame cache -+ ehci->i_thresh = 2 + 8; -+ else // N microframes cached -+ ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params); -+ -+ ehci->reclaim = NULL; -+ ehci->next_uframe = -1; -+ ehci->clock_frame = -1; ++ struct ag71xx *ag = file->private_data; ++ char buf[256]; ++ unsigned int len = 0; + -+ /* -+ * dedicate a qh for the async ring head, since we couldn't unlink -+ * a 'real' qh without stopping the async schedule [4.8]. use it -+ * as the 'reclamation list head' too. -+ * its dummy is used in hw_alt_next of many tds, to prevent the qh -+ * from automatically advancing to the next td after short reads. -+ */ -+ ehci->async->qh_next.qh = NULL; -+ hw = ehci->async->hw; -+ hw->hw_next = QH_NEXT(ehci, ehci->async->qh_dma); -+ hw->hw_info1 = cpu_to_hc32(ehci, QH_HEAD); -+ hw->hw_token = cpu_to_hc32(ehci, QTD_STS_HALT); -+ hw->hw_qtd_next = EHCI_LIST_END(ehci); -+ ehci->async->qh_state = QH_STATE_LINKED; -+ hw->hw_alt_next = QTD_NEXT(ehci, ehci->async->dummy->qtd_dma); -+ -+ /* clear interrupt enables, set irq latency */ -+ if (log2_irq_thresh < 0 || log2_irq_thresh > 6) -+ log2_irq_thresh = 0; -+ temp = 1 << (16 + log2_irq_thresh); -+ if (HCC_CANPARK(hcc_params)) { -+ /* HW default park == 3, on hardware that supports it (like -+ * NVidia and ALI silicon), maximizes throughput on the async -+ * schedule by avoiding QH fetches between transfers. -+ * -+ * With fast usb storage devices and NForce2, "park" seems to -+ * make problems: throughput reduction (!), data errors... -+ */ -+ if (park) { -+ park = min(park, (unsigned) 3); -+ temp |= CMD_PARK; -+ temp |= park << 8; -+ } -+ ehci_dbg(ehci, "park %d\n", park); -+ } -+ if (HCC_PGM_FRAMELISTLEN(hcc_params)) { -+ /* periodic schedule size can be smaller than default */ -+ temp &= ~(3 << 2); -+ temp |= (EHCI_TUNE_FLS << 2); -+ switch (EHCI_TUNE_FLS) { -+ case 0: ehci->periodic_size = 1024; break; -+ case 1: ehci->periodic_size = 512; break; -+ case 2: ehci->periodic_size = 256; break; -+ default: BUG(); -+ } -+ } -+ ehci->command = temp; ++ PR_INT_STAT("TX Packet Sent", tx_ps); ++ PR_INT_STAT("TX Underrun", tx_ur); ++ PR_INT_STAT("TX Bus Error", tx_be); ++ PR_INT_STAT("RX Packet Received", rx_pr); ++ PR_INT_STAT("RX Overflow", rx_of); ++ PR_INT_STAT("RX Bus Error", rx_be); ++ len += snprintf(buf + len, sizeof(buf) - len, "\n"); ++ PR_INT_STAT("Total", total); + -+ /* Accept arbitrarily long scatter-gather lists */ -+ hcd->self.sg_tablesize = ~0; -+ return 0; ++ return simple_read_from_buffer(user_buf, count, ppos, buf, len); ++#undef PR_INT_STAT +} + -+/* start HC running; it's halted, ehci_init() has been run (once) */ -+static int ehci_run (struct usb_hcd *hcd) -+{ -+ struct ehci_hcd *ehci = hcd_to_ehci (hcd); -+ int retval; -+ u32 temp; -+ u32 hcc_params; ++static const struct file_operations ag71xx_fops_int_stats = { ++ .open = ag71xx_debugfs_generic_open, ++ .read = read_file_int_stats, ++ .owner = THIS_MODULE ++}; + -+ hcd->uses_new_polling = 1; -+ hcd->poll_rh = 0; ++void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx) ++{ ++ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; + -+ /* EHCI spec section 4.1 */ -+ if ((retval = ehci_reset(ehci)) != 0) { -+ ehci_mem_cleanup(ehci); -+ return retval; ++ if (rx) { ++ stats->rx_count++; ++ stats->rx_packets += rx; ++ if (rx <= AG71XX_NAPI_WEIGHT) ++ stats->rx[rx]++; ++ if (rx > stats->rx_packets_max) ++ stats->rx_packets_max = rx; + } -+ ehci_writel(ehci, ehci->periodic_dma, &ehci->regs->frame_list); -+ ehci_writel(ehci, (u32)ehci->async->qh_dma, &ehci->regs->async_next); + -+ /* -+ * hcc_params controls whether ehci->regs->segment must (!!!) -+ * be used; it constrains QH/ITD/SITD and QTD locations. -+ * pci_pool consistent memory always uses segment zero. -+ * streaming mappings for I/O buffers, like pci_map_single(), -+ * can return segments above 4GB, if the device allows. -+ * -+ * NOTE: the dma mask is visible through dma_supported(), so -+ * drivers can pass this info along ... like NETIF_F_HIGHDMA, -+ * Scsi_Host.highmem_io, and so forth. It's readonly to all -+ * host side drivers though. -+ */ -+ hcc_params = ehci_readl(ehci, &ehci->caps->hcc_params); -+ if (HCC_64BIT_ADDR(hcc_params)) { -+ ehci_writel(ehci, 0, &ehci->regs->segment); -+#if 0 -+// this is deeply broken on almost all architectures -+ if (!dma_set_mask(hcd->self.controller, DMA_BIT_MASK(64))) -+ ehci_info(ehci, "enabled 64bit DMA\n"); -+#endif ++ if (tx) { ++ stats->tx_count++; ++ stats->tx_packets += tx; ++ if (tx <= AG71XX_NAPI_WEIGHT) ++ stats->tx[tx]++; ++ if (tx > stats->tx_packets_max) ++ stats->tx_packets_max = tx; + } -+ -+ -+ // Philips, Intel, and maybe others need CMD_RUN before the -+ // root hub will detect new devices (why?); NEC doesn't -+ ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET); -+ ehci->command |= CMD_RUN; -+ ehci_writel(ehci, ehci->command, &ehci->regs->command); -+ dbg_cmd (ehci, "init", ehci->command); -+ -+ /* -+ * Start, enabling full USB 2.0 functionality ... usb 1.1 devices -+ * are explicitly handed to companion controller(s), so no TT is -+ * involved with the root hub. (Except where one is integrated, -+ * and there's no companion controller unless maybe for USB OTG.) -+ * -+ * Turning on the CF flag will transfer ownership of all ports -+ * from the companions to the EHCI controller. If any of the -+ * companions are in the middle of a port reset at the time, it -+ * could cause trouble. Write-locking ehci_cf_port_reset_rwsem -+ * guarantees that no resets are in progress. After we set CF, -+ * a short delay lets the hardware catch up; new resets shouldn't -+ * be started before the port switching actions could complete. -+ */ -+ down_write(&ehci_cf_port_reset_rwsem); -+ hcd->state = HC_STATE_RUNNING; -+ ehci_writel(ehci, FLAG_CF, &ehci->regs->configured_flag); -+ ehci_readl(ehci, &ehci->regs->command); /* unblock posted writes */ -+ msleep(5); -+ up_write(&ehci_cf_port_reset_rwsem); -+ ehci->last_periodic_enable = ktime_get_real(); -+ -+ temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase)); -+ ehci_info (ehci, -+ "USB %x.%x started, EHCI %x.%02x%s\n", -+ ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), -+ temp >> 8, temp & 0xff, -+ ignore_oc ? ", overcurrent ignored" : ""); -+ -+ ehci_writel(ehci, INTR_MASK, -+ &ehci->regs->intr_enable); /* Turn On Interrupts */ -+ -+ /* GRR this is run-once init(), being done every time the HC starts. -+ * So long as they're part of class devices, we can't do it init() -+ * since the class device isn't created that early. -+ */ -+ create_debug_files(ehci); -+ create_companion_file(ehci); -+ -+ return 0; +} + -+/*-------------------------------------------------------------------------*/ -+ -+static irqreturn_t ehci_irq (struct usb_hcd *hcd) ++static ssize_t read_file_napi_stats(struct file *file, char __user *user_buf, ++ size_t count, loff_t *ppos) +{ -+ struct ehci_hcd *ehci = hcd_to_ehci (hcd); -+ u32 status, masked_status, pcd_status = 0, cmd; -+ int bh; ++ struct ag71xx *ag = file->private_data; ++ struct ag71xx_napi_stats *stats = &ag->debug.napi_stats; ++ char buf[2048]; ++ unsigned int len = 0; ++ unsigned long rx_avg = 0; ++ unsigned long tx_avg = 0; ++ int i; + -+ spin_lock (&ehci->lock); ++ if (stats->rx_count) ++ rx_avg = stats->rx_packets / stats->rx_count; + -+ status = ehci_readl(ehci, &ehci->regs->status); ++ if (stats->tx_count) ++ tx_avg = stats->tx_packets / stats->tx_count; + -+ /* e.g. cardbus physical eject */ -+ if (status == ~(u32) 0) { -+ ehci_dbg (ehci, "device removed\n"); -+ goto dead; -+ } ++ len += snprintf(buf + len, sizeof(buf) - len, "%3s %10s %10s\n", ++ "len", "rx", "tx"); + -+ masked_status = status & INTR_MASK; -+ if (!masked_status) { /* irq sharing? */ -+ spin_unlock(&ehci->lock); -+ return IRQ_NONE; -+ } ++ for (i = 1; i <= AG71XX_NAPI_WEIGHT; i++) ++ len += snprintf(buf + len, sizeof(buf) - len, ++ "%3d: %10lu %10lu\n", ++ i, stats->rx[i], stats->tx[i]); + -+ /* clear (just) interrupts */ -+ ehci_writel(ehci, masked_status, &ehci->regs->status); -+ cmd = ehci_readl(ehci, &ehci->regs->command); -+ bh = 0; ++ len += snprintf(buf + len, sizeof(buf) - len, "\n"); + -+#ifdef VERBOSE_DEBUG -+ /* unrequested/ignored: Frame List Rollover */ -+ dbg_status (ehci, "irq", status); -+#endif ++ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", ++ "sum", stats->rx_count, stats->tx_count); ++ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", ++ "avg", rx_avg, tx_avg); ++ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", ++ "max", stats->rx_packets_max, stats->tx_packets_max); ++ len += snprintf(buf + len, sizeof(buf) - len, "%3s: %10lu %10lu\n", ++ "pkt", stats->rx_packets, stats->tx_packets); + -+ /* INT, ERR, and IAA interrupt rates can be throttled */ ++ return simple_read_from_buffer(user_buf, count, ppos, buf, len); ++} + -+ /* normal [4.15.1.2] or error [4.15.1.1] completion */ -+ if (likely ((status & (STS_INT|STS_ERR)) != 0)) { -+ if (likely ((status & STS_ERR) == 0)) -+ COUNT (ehci->stats.normal); -+ else -+ COUNT (ehci->stats.error); -+ bh = 1; -+ } ++static const struct file_operations ag71xx_fops_napi_stats = { ++ .open = ag71xx_debugfs_generic_open, ++ .read = read_file_napi_stats, ++ .owner = THIS_MODULE ++}; + -+ /* complete the unlinking of some qh [4.15.2.3] */ -+ if (status & STS_IAA) { -+ /* guard against (alleged) silicon errata */ -+ if (cmd & CMD_IAAD) { -+ ehci_writel(ehci, cmd & ~CMD_IAAD, -+ &ehci->regs->command); -+ ehci_dbg(ehci, "IAA with IAAD still set?\n"); -+ } -+ if (ehci->reclaim) { -+ COUNT(ehci->stats.reclaim); -+ end_unlink_async(ehci); -+ } else -+ ehci_dbg(ehci, "IAA with nothing to reclaim?\n"); -+ } ++void ag71xx_debugfs_exit(struct ag71xx *ag) ++{ ++ debugfs_remove(ag->debug.debugfs_napi_stats); ++ debugfs_remove(ag->debug.debugfs_int_stats); ++ debugfs_remove(ag->debug.debugfs_dir); ++} + -+ /* remote wakeup [4.3.1] */ -+ if (status & STS_PCD) { -+ unsigned i = HCS_N_PORTS (ehci->hcs_params); ++int ag71xx_debugfs_init(struct ag71xx *ag) ++{ ++ ag->debug.debugfs_dir = debugfs_create_dir(ag->dev->name, ++ ag71xx_debugfs_root); ++ if (!ag->debug.debugfs_dir) ++ goto err; + -+ /* kick root hub later */ -+ pcd_status = status; ++ ag->debug.debugfs_int_stats = ++ debugfs_create_file("int_stats", ++ S_IRUGO, ++ ag->debug.debugfs_dir, ++ ag, ++ &ag71xx_fops_int_stats); ++ if (!ag->debug.debugfs_int_stats) ++ goto err; + -+ /* resume root hub? */ -+ if (!(cmd & CMD_RUN)) -+ usb_hcd_resume_root_hub(hcd); ++ ag->debug.debugfs_napi_stats = ++ debugfs_create_file("napi_stats", ++ S_IRUGO, ++ ag->debug.debugfs_dir, ++ ag, ++ &ag71xx_fops_napi_stats); ++ if (!ag->debug.debugfs_napi_stats) ++ goto err; + -+ while (i--) { -+ int pstatus = ehci_readl(ehci, -+ &ehci->regs->port_status [i]); ++ return 0; + -+ if (pstatus & PORT_OWNER) -+ continue; -+ if (!(test_bit(i, &ehci->suspended_ports) && -+ ((pstatus & PORT_RESUME) || -+ !(pstatus & PORT_SUSPEND)) && -+ (pstatus & PORT_PE) && -+ ehci->reset_done[i] == 0)) -+ continue; ++ err: ++ ag71xx_debugfs_exit(ag); ++ return -ENOMEM; ++} + -+ /* start 20 msec resume signaling from this port, -+ * and make khubd collect PORT_STAT_C_SUSPEND to -+ * stop that signaling. Use 5 ms extra for safety, -+ * like usb_port_resume() does. -+ */ -+ ehci->reset_done[i] = jiffies + msecs_to_jiffies(25); -+ ehci_dbg (ehci, "port %d remote wakeup\n", i + 1); -+ mod_timer(&hcd->rh_timer, ehci->reset_done[i]); -+ } -+ } ++int ag71xx_debugfs_root_init(void) ++{ ++ if (ag71xx_debugfs_root) ++ return -EBUSY; + -+ /* PCI errors [4.15.2.4] */ -+ if (unlikely ((status & STS_FATAL) != 0)) { -+ ehci_err(ehci, "fatal error\n"); -+ dbg_cmd(ehci, "fatal", cmd); -+ dbg_status(ehci, "fatal", status); -+ ehci_halt(ehci); -+dead: -+ ehci_reset(ehci); -+ ehci_writel(ehci, 0, &ehci->regs->configured_flag); -+ /* generic layer kills/unlinks all urbs, then -+ * uses ehci_stop to clean up the rest -+ */ -+ bh = 1; -+ } ++ ag71xx_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL); ++ if (!ag71xx_debugfs_root) ++ return -ENOENT; + -+ if (bh) -+ ehci_work (ehci); -+ spin_unlock (&ehci->lock); -+ if (pcd_status) -+ usb_hcd_poll_rh_status(hcd); -+ return IRQ_HANDLED; ++ return 0; +} + -+/*-------------------------------------------------------------------------*/ -+ ++void ag71xx_debugfs_root_exit(void) ++{ ++ debugfs_remove(ag71xx_debugfs_root); ++ ag71xx_debugfs_root = NULL; ++} +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_ethtool.c linux-2.6.36/drivers/net/ag71xx/ag71xx_ethtool.c +--- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_ethtool.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/ag71xx_ethtool.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,71 @@ +/* -+ * non-error returns are a promise to giveback() the urb later -+ * we drop ownership so next owner (or urb unlink) can get it ++ * Atheros AR71xx built-in ethernet mac driver + * -+ * urb + dev is in hcd.self.controller.urb_list -+ * we're queueing TDs onto software and hardware lists ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz + * -+ * hcd-specific init for hcpriv hasn't been done yet ++ * Based on Atheros' AG7100 driver + * -+ * NOTE: control, bulk, and interrupt share the same code to append TDs -+ * to a (possibly active) QH, and the same QH scanning code. ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ -+static int ehci_urb_enqueue ( -+ struct usb_hcd *hcd, -+ struct urb *urb, -+ gfp_t mem_flags -+) { -+ struct ehci_hcd *ehci = hcd_to_ehci (hcd); -+ struct list_head qtd_list; -+ -+ INIT_LIST_HEAD (&qtd_list); -+ -+ switch (usb_pipetype (urb->pipe)) { -+ case PIPE_CONTROL: -+ /* qh_completions() code doesn't handle all the fault cases -+ * in multi-TD control transfers. Even 1KB is rare anyway. -+ */ -+ if (urb->transfer_buffer_length > (16 * 1024)) -+ return -EMSGSIZE; -+ /* FALLTHROUGH */ -+ /* case PIPE_BULK: */ -+ default: -+ if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) -+ return -ENOMEM; -+ return submit_async(ehci, urb, &qtd_list, mem_flags); -+ -+ case PIPE_INTERRUPT: -+ if (!qh_urb_transaction (ehci, urb, &qtd_list, mem_flags)) -+ return -ENOMEM; -+ return intr_submit(ehci, urb, &qtd_list, mem_flags); -+ -+ case PIPE_ISOCHRONOUS: -+ if (urb->dev->speed == USB_SPEED_HIGH) -+ return itd_submit (ehci, urb, mem_flags); -+ else -+ return sitd_submit (ehci, urb, mem_flags); -+ } -+} + -+static void unlink_async (struct ehci_hcd *ehci, struct ehci_qh *qh) ++#include "ag71xx.h" ++ ++static int ag71xx_ethtool_get_settings(struct net_device *dev, ++ struct ethtool_cmd *cmd) +{ -+ /* failfast */ -+ if (!HC_IS_RUNNING(ehci_to_hcd(ehci)->state) && ehci->reclaim) -+ end_unlink_async(ehci); ++ struct ag71xx *ag = netdev_priv(dev); ++ struct phy_device *phydev = ag->phy_dev; + -+ /* If the QH isn't linked then there's nothing we can do -+ * unless we were called during a giveback, in which case -+ * qh_completions() has to deal with it. -+ */ -+ if (qh->qh_state != QH_STATE_LINKED) { -+ if (qh->qh_state == QH_STATE_COMPLETING) -+ qh->needs_rescan = 1; -+ return; -+ } ++ if (!phydev) ++ return -ENODEV; ++ ++ return phy_ethtool_gset(phydev, cmd); ++} + -+ /* defer till later if busy */ -+ if (ehci->reclaim) { -+ struct ehci_qh *last; ++static int ag71xx_ethtool_set_settings(struct net_device *dev, ++ struct ethtool_cmd *cmd) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ struct phy_device *phydev = ag->phy_dev; + -+ for (last = ehci->reclaim; -+ last->reclaim; -+ last = last->reclaim) -+ continue; -+ qh->qh_state = QH_STATE_UNLINK_WAIT; -+ last->reclaim = qh; ++ if (!phydev) ++ return -ENODEV; + -+ /* start IAA cycle */ -+ } else -+ start_unlink_async (ehci, qh); ++ return phy_ethtool_sset(phydev, cmd); +} + -+/* remove from hardware lists -+ * completions normally happen asynchronously -+ */ ++static void ag71xx_ethtool_get_drvinfo(struct net_device *dev, ++ struct ethtool_drvinfo *info) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ ++ strcpy(info->driver, ag->pdev->dev.driver->name); ++ strcpy(info->version, AG71XX_DRV_VERSION); ++ strcpy(info->bus_info, dev_name(&ag->pdev->dev)); ++} + -+static int ehci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) ++static u32 ag71xx_ethtool_get_msglevel(struct net_device *dev) +{ -+ struct ehci_hcd *ehci = hcd_to_ehci (hcd); -+ struct ehci_qh *qh; -+ unsigned long flags; -+ int rc; ++ struct ag71xx *ag = netdev_priv(dev); + -+ spin_lock_irqsave (&ehci->lock, flags); -+ rc = usb_hcd_check_unlink_urb(hcd, urb, status); -+ if (rc) -+ goto done; ++ return ag->msg_enable; ++} + -+ switch (usb_pipetype (urb->pipe)) { -+ // case PIPE_CONTROL: -+ // case PIPE_BULK: -+ default: -+ qh = (struct ehci_qh *) urb->hcpriv; -+ if (!qh) -+ break; -+ switch (qh->qh_state) { -+ case QH_STATE_LINKED: -+ case QH_STATE_COMPLETING: -+ unlink_async(ehci, qh); -+ break; -+ case QH_STATE_UNLINK: -+ case QH_STATE_UNLINK_WAIT: -+ /* already started */ -+ break; -+ case QH_STATE_IDLE: -+ /* QH might be waiting for a Clear-TT-Buffer */ -+ qh_completions(ehci, qh); -+ break; -+ } -+ break; ++static void ag71xx_ethtool_set_msglevel(struct net_device *dev, u32 msg_level) ++{ ++ struct ag71xx *ag = netdev_priv(dev); + -+ case PIPE_INTERRUPT: -+ qh = (struct ehci_qh *) urb->hcpriv; -+ if (!qh) -+ break; -+ switch (qh->qh_state) { -+ case QH_STATE_LINKED: -+ case QH_STATE_COMPLETING: -+ intr_deschedule (ehci, qh); -+ break; -+ case QH_STATE_IDLE: -+ qh_completions (ehci, qh); -+ break; -+ default: -+ ehci_dbg (ehci, "bogus qh %p state %d\n", -+ qh, qh->qh_state); -+ goto done; -+ } -+ break; ++ ag->msg_enable = msg_level; ++} ++ ++struct ethtool_ops ag71xx_ethtool_ops = { ++ .set_settings = ag71xx_ethtool_set_settings, ++ .get_settings = ag71xx_ethtool_get_settings, ++ .get_drvinfo = ag71xx_ethtool_get_drvinfo, ++ .get_msglevel = ag71xx_ethtool_get_msglevel, ++ .set_msglevel = ag71xx_ethtool_set_msglevel, ++ .get_link = ethtool_op_get_link, ++}; +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_main.c linux-2.6.36/drivers/net/ag71xx/ag71xx_main.c +--- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_main.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/ag71xx_main.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,1184 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ case PIPE_ISOCHRONOUS: -+ // itd or sitd ... ++#include "ag71xx.h" + -+ // wait till next completion, do it then. -+ // completion irqs can wait up to 1024 msec, -+ break; -+ } -+done: -+ spin_unlock_irqrestore (&ehci->lock, flags); -+ return rc; -+} ++#define AG71XX_DEFAULT_MSG_ENABLE \ ++ ( NETIF_MSG_DRV \ ++ | NETIF_MSG_PROBE \ ++ | NETIF_MSG_LINK \ ++ | NETIF_MSG_TIMER \ ++ | NETIF_MSG_IFDOWN \ ++ | NETIF_MSG_IFUP \ ++ | NETIF_MSG_RX_ERR \ ++ | NETIF_MSG_TX_ERR ) + -+/*-------------------------------------------------------------------------*/ ++static int ag71xx_msg_level = -1; + -+// bulk qh holds the data toggle ++module_param_named(msg_level, ag71xx_msg_level, int, 0); ++MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)"); + -+static void -+ehci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++static void ag71xx_dump_dma_regs(struct ag71xx *ag) +{ -+ struct ehci_hcd *ehci = hcd_to_ehci (hcd); -+ unsigned long flags; -+ struct ehci_qh *qh, *tmp; -+ -+ /* ASSERT: any requests/urbs are being unlinked */ -+ /* ASSERT: nobody can be submitting urbs for this any more */ -+ -+rescan: -+ spin_lock_irqsave (&ehci->lock, flags); -+ qh = ep->hcpriv; -+ if (!qh) -+ goto done; ++ DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_TX_CTRL), ++ ag71xx_rr(ag, AG71XX_REG_TX_DESC), ++ ag71xx_rr(ag, AG71XX_REG_TX_STATUS)); + -+ /* endpoints can be iso streams. for now, we don't -+ * accelerate iso completions ... so spin a while. -+ */ -+ if (qh->hw == NULL) { -+ ehci_vdbg (ehci, "iso delay\n"); -+ goto idle_timeout; -+ } -+ -+ if (!HC_IS_RUNNING (hcd->state)) -+ qh->qh_state = QH_STATE_IDLE; -+ switch (qh->qh_state) { -+ case QH_STATE_LINKED: -+ case QH_STATE_COMPLETING: -+ for (tmp = ehci->async->qh_next.qh; -+ tmp && tmp != qh; -+ tmp = tmp->qh_next.qh) -+ continue; -+ /* periodic qh self-unlinks on empty */ -+ if (!tmp) -+ goto nogood; -+ unlink_async (ehci, qh); -+ /* FALL THROUGH */ -+ case QH_STATE_UNLINK: /* wait for hw to finish? */ -+ case QH_STATE_UNLINK_WAIT: -+idle_timeout: -+ spin_unlock_irqrestore (&ehci->lock, flags); -+ schedule_timeout_uninterruptible(1); -+ goto rescan; -+ case QH_STATE_IDLE: /* fully unlinked */ -+ if (qh->clearing_tt) -+ goto idle_timeout; -+ if (list_empty (&qh->qtd_list)) { -+ qh_put (qh); -+ break; -+ } -+ /* else FALL THROUGH */ -+ default: -+nogood: -+ /* caller was supposed to have unlinked any requests; -+ * that's not our job. just leak this memory. -+ */ -+ ehci_err (ehci, "qh %p (#%02x) state %d%s\n", -+ qh, ep->desc.bEndpointAddress, qh->qh_state, -+ list_empty (&qh->qtd_list) ? "" : "(has tds)"); -+ break; -+ } -+ ep->hcpriv = NULL; -+done: -+ spin_unlock_irqrestore (&ehci->lock, flags); -+ return; ++ DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_RX_CTRL), ++ ag71xx_rr(ag, AG71XX_REG_RX_DESC), ++ ag71xx_rr(ag, AG71XX_REG_RX_STATUS)); +} + -+static void -+ehci_endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++static void ag71xx_dump_regs(struct ag71xx *ag) +{ -+ struct ehci_hcd *ehci = hcd_to_ehci(hcd); -+ struct ehci_qh *qh; -+ int eptype = usb_endpoint_type(&ep->desc); -+ int epnum = usb_endpoint_num(&ep->desc); -+ int is_out = usb_endpoint_dir_out(&ep->desc); -+ unsigned long flags; -+ -+ if (eptype != USB_ENDPOINT_XFER_BULK && eptype != USB_ENDPOINT_XFER_INT) -+ return; -+ -+ spin_lock_irqsave(&ehci->lock, flags); -+ qh = ep->hcpriv; -+ -+ /* For Bulk and Interrupt endpoints we maintain the toggle state -+ * in the hardware; the toggle bits in udev aren't used at all. -+ * When an endpoint is reset by usb_clear_halt() we must reset -+ * the toggle bit in the QH. -+ */ -+ if (qh) { -+ usb_settoggle(qh->dev, epnum, is_out, 0); -+ if (!list_empty(&qh->qtd_list)) { -+ WARN_ONCE(1, "clear_halt for a busy endpoint\n"); -+ } else if (qh->qh_state == QH_STATE_LINKED || -+ qh->qh_state == QH_STATE_COMPLETING) { -+ -+ /* The toggle value in the QH can't be updated -+ * while the QH is active. Unlink it now; -+ * re-linking will call qh_refresh(). -+ */ -+ if (eptype == USB_ENDPOINT_XFER_BULK) -+ unlink_async(ehci, qh); -+ else -+ intr_deschedule(ehci, qh); -+ } -+ } -+ spin_unlock_irqrestore(&ehci->lock, flags); ++ DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_MAC_CFG1), ++ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), ++ ag71xx_rr(ag, AG71XX_REG_MAC_IPG), ++ ag71xx_rr(ag, AG71XX_REG_MAC_HDX), ++ ag71xx_rr(ag, AG71XX_REG_MAC_MFL)); ++ DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), ++ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1), ++ ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2)); ++ DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); ++ DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); +} + -+static int ehci_get_frame (struct usb_hcd *hcd) ++static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr) +{ -+ struct ehci_hcd *ehci = hcd_to_ehci (hcd); -+ return (ehci_readl(ehci, &ehci->regs->frame_index) >> 3) % -+ ehci->periodic_size; ++ DBG("%s: %s intr=%08x %s%s%s%s%s%s\n", ++ ag->dev->name, label, intr, ++ (intr & AG71XX_INT_TX_PS) ? "TXPS " : "", ++ (intr & AG71XX_INT_TX_UR) ? "TXUR " : "", ++ (intr & AG71XX_INT_TX_BE) ? "TXBE " : "", ++ (intr & AG71XX_INT_RX_PR) ? "RXPR " : "", ++ (intr & AG71XX_INT_RX_OF) ? "RXOF " : "", ++ (intr & AG71XX_INT_RX_BE) ? "RXBE " : ""); +} + -+/*-------------------------------------------------------------------------*/ -+ -+MODULE_DESCRIPTION(DRIVER_DESC); -+MODULE_AUTHOR (DRIVER_AUTHOR); -+MODULE_LICENSE ("GPL"); -+ -+#ifdef CONFIG_PCI -+#include "ehci-pci.c" -+#define PCI_DRIVER ehci_pci_driver -+#endif -+ -+#ifdef CONFIG_USB_EHCI_FSL -+#include "ehci-fsl.c" -+#define PLATFORM_DRIVER ehci_fsl_driver -+#endif -+ -+#ifdef CONFIG_USB_EHCI_MXC -+#include "ehci-mxc.c" -+#define PLATFORM_DRIVER ehci_mxc_driver -+#endif -+ -+#ifdef CONFIG_SOC_AU1200 -+#include "ehci-au1xxx.c" -+#define PLATFORM_DRIVER ehci_hcd_au1xxx_driver -+#endif ++static void ag71xx_ring_free(struct ag71xx_ring *ring) ++{ ++ kfree(ring->buf); + -+#ifdef CONFIG_ARCH_OMAP3 -+#include "ehci-omap.c" -+#define PLATFORM_DRIVER ehci_hcd_omap_driver -+#endif ++ if (ring->descs_cpu) ++ dma_free_coherent(NULL, ring->size * ring->desc_size, ++ ring->descs_cpu, ring->descs_dma); ++} + -+#ifdef CONFIG_PPC_PS3 -+#include "ehci-ps3.c" -+#define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver -+#endif ++static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size) ++{ ++ int err; ++ int i; + -+#ifdef CONFIG_USB_EHCI_HCD_PPC_OF -+#include "ehci-ppc-of.c" -+#define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver -+#endif ++ ring->desc_size = sizeof(struct ag71xx_desc); ++ if (ring->desc_size % cache_line_size()) { ++ DBG("ag71xx: ring %p, desc size %u rounded to %u\n", ++ ring, ring->desc_size, ++ roundup(ring->desc_size, cache_line_size())); ++ ring->desc_size = roundup(ring->desc_size, cache_line_size()); ++ } + -+#ifdef CONFIG_XPS_USB_HCD_XILINX -+#include "ehci-xilinx-of.c" -+#define XILINX_OF_PLATFORM_DRIVER ehci_hcd_xilinx_of_driver -+#endif ++ ring->descs_cpu = dma_alloc_coherent(NULL, size * ring->desc_size, ++ &ring->descs_dma, GFP_ATOMIC); ++ if (!ring->descs_cpu) { ++ err = -ENOMEM; ++ goto err; ++ } + -+#ifdef CONFIG_PLAT_ORION -+#include "ehci-orion.c" -+#define PLATFORM_DRIVER ehci_orion_driver -+#endif ++ ring->size = size; + -+#ifdef CONFIG_ARCH_IXP4XX -+#include "ehci-ixp4xx.c" -+#define PLATFORM_DRIVER ixp4xx_ehci_driver -+#endif ++ ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL); ++ if (!ring->buf) { ++ err = -ENOMEM; ++ goto err; ++ } + -+#ifdef CONFIG_USB_W90X900_EHCI -+#include "ehci-w90x900.c" -+#define PLATFORM_DRIVER ehci_hcd_w90x900_driver -+#endif ++ for (i = 0; i < size; i++) { ++ ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[i * ring->desc_size]; ++ DBG("ag71xx: ring %p, desc %d at %p\n", ++ ring, i, ring->buf[i].desc); ++ } + -+#ifdef CONFIG_ARCH_AT91 -+#include "ehci-atmel.c" -+#define PLATFORM_DRIVER ehci_atmel_driver -+#endif ++ return 0; + -+#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ -+ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ -+ !defined(XILINX_OF_PLATFORM_DRIVER) -+#error "missing bus glue for ehci-hcd" -+#endif ++ err: ++ return err; ++} + -+static int __init ehci_hcd_init(void) ++static void ag71xx_ring_tx_clean(struct ag71xx *ag) +{ -+ int retval = 0; -+ -+ if (usb_disabled()) -+ return -ENODEV; -+ -+ printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); -+ set_bit(USB_EHCI_LOADED, &usb_hcds_loaded); -+ if (test_bit(USB_UHCI_LOADED, &usb_hcds_loaded) || -+ test_bit(USB_OHCI_LOADED, &usb_hcds_loaded)) -+ printk(KERN_WARNING "Warning! ehci_hcd should always be loaded" -+ " before uhci_hcd and ohci_hcd, not after\n"); -+ -+ pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n", -+ hcd_name, -+ sizeof(struct ehci_qh), sizeof(struct ehci_qtd), -+ sizeof(struct ehci_itd), sizeof(struct ehci_sitd)); ++ struct ag71xx_ring *ring = &ag->tx_ring; ++ struct net_device *dev = ag->dev; + -+#ifdef DEBUG -+ ehci_debug_root = debugfs_create_dir("ehci", usb_debug_root); -+ if (!ehci_debug_root) { -+ retval = -ENOENT; -+ goto err_debug; -+ } -+#endif ++ while (ring->curr != ring->dirty) { ++ u32 i = ring->dirty % AG71XX_TX_RING_SIZE; + -+#ifdef PLATFORM_DRIVER -+ retval = platform_driver_register(&PLATFORM_DRIVER); -+ if (retval < 0) -+ goto clean0; -+#endif ++ if (!ag71xx_desc_empty(ring->buf[i].desc)) { ++ ring->buf[i].desc->ctrl = 0; ++ dev->stats.tx_errors++; ++ } + -+#ifdef PCI_DRIVER -+ retval = pci_register_driver(&PCI_DRIVER); -+ if (retval < 0) -+ goto clean1; -+#endif ++ if (ring->buf[i].skb) ++ dev_kfree_skb_any(ring->buf[i].skb); + -+#ifdef PS3_SYSTEM_BUS_DRIVER -+ retval = ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER); -+ if (retval < 0) -+ goto clean2; -+#endif ++ ring->buf[i].skb = NULL; + -+#ifdef OF_PLATFORM_DRIVER -+ retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); -+ if (retval < 0) -+ goto clean3; -+#endif ++ ring->dirty++; ++ } + -+#ifdef XILINX_OF_PLATFORM_DRIVER -+ retval = of_register_platform_driver(&XILINX_OF_PLATFORM_DRIVER); -+ if (retval < 0) -+ goto clean4; -+#endif -+ return retval; ++ /* flush descriptors */ ++ wmb(); + -+#ifdef XILINX_OF_PLATFORM_DRIVER -+ /* of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); */ -+clean4: -+#endif -+#ifdef OF_PLATFORM_DRIVER -+ of_unregister_platform_driver(&OF_PLATFORM_DRIVER); -+clean3: -+#endif -+#ifdef PS3_SYSTEM_BUS_DRIVER -+ ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); -+clean2: -+#endif -+#ifdef PCI_DRIVER -+ pci_unregister_driver(&PCI_DRIVER); -+clean1: -+#endif -+#ifdef PLATFORM_DRIVER -+ platform_driver_unregister(&PLATFORM_DRIVER); -+clean0: -+#endif -+#ifdef DEBUG -+ debugfs_remove(ehci_debug_root); -+ ehci_debug_root = NULL; -+err_debug: -+#endif -+ clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); -+ return retval; +} -+module_init(ehci_hcd_init); + -+static void __exit ehci_hcd_cleanup(void) ++static void ag71xx_ring_tx_init(struct ag71xx *ag) +{ -+#ifdef XILINX_OF_PLATFORM_DRIVER -+ of_unregister_platform_driver(&XILINX_OF_PLATFORM_DRIVER); -+#endif -+#ifdef OF_PLATFORM_DRIVER -+ of_unregister_platform_driver(&OF_PLATFORM_DRIVER); -+#endif -+#ifdef PLATFORM_DRIVER -+ platform_driver_unregister(&PLATFORM_DRIVER); -+#endif -+#ifdef PCI_DRIVER -+ pci_unregister_driver(&PCI_DRIVER); -+#endif -+#ifdef PS3_SYSTEM_BUS_DRIVER -+ ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); -+#endif -+#ifdef DEBUG -+ debugfs_remove(ehci_debug_root); -+#endif -+ clear_bit(USB_EHCI_LOADED, &usb_hcds_loaded); -+} -+module_exit(ehci_hcd_cleanup); -+ -diff -Nur linux-2.6.35.7.orig/drivers/usb/host/Kconfig linux-2.6.35.7/drivers/usb/host/Kconfig ---- linux-2.6.35.7.orig/drivers/usb/host/Kconfig 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/usb/host/Kconfig 2010-10-14 20:28:01.385601136 +0200 -@@ -109,6 +109,13 @@ - support both high speed and full speed devices, or high speed - devices only. - -+config USB_EHCI_AR71XX -+ bool "USB EHCI support for AR71xx" -+ depends on USB_EHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in EHCI controller -+ - config USB_EHCI_FSL - bool "Support for Freescale on-chip EHCI USB controller" - depends on USB_EHCI_HCD && FSL_SOC -@@ -222,6 +229,13 @@ - Enables support for the on-chip OHCI controller on - OMAP3 and later chips. - -+config USB_OHCI_AR71XX -+ bool "USB OHCI support for Atheros AR71xx" -+ depends on USB_OHCI_HCD && ATHEROS_AR71XX -+ default y -+ help -+ Support for Atheros AR71xx built-in OHCI controller ++ struct ag71xx_ring *ring = &ag->tx_ring; ++ int i; + - config USB_OHCI_HCD_PPC_SOC - bool "OHCI support for on-chip PPC USB controller" - depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) -diff -Nur linux-2.6.35.7.orig/drivers/usb/host/Kconfig.orig linux-2.6.35.7/drivers/usb/host/Kconfig.orig ---- linux-2.6.35.7.orig/drivers/usb/host/Kconfig.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/usb/host/Kconfig.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,427 @@ -+# -+# USB Host Controller Drivers -+# -+comment "USB Host Controller Drivers" -+ depends on USB ++ for (i = 0; i < AG71XX_TX_RING_SIZE; i++) { ++ ring->buf[i].desc->next = (u32) (ring->descs_dma + ++ ring->desc_size * ((i + 1) % AG71XX_TX_RING_SIZE)); + -+config USB_C67X00_HCD -+ tristate "Cypress C67x00 HCD support" -+ depends on USB -+ help -+ The Cypress C67x00 (EZ-Host/EZ-OTG) chips are dual-role -+ host/peripheral/OTG USB controllers. ++ ring->buf[i].desc->ctrl = DESC_EMPTY; ++ ring->buf[i].skb = NULL; ++ } + -+ Enable this option to support this chip in host controller mode. -+ If unsure, say N. ++ /* flush descriptors */ ++ wmb(); + -+ To compile this driver as a module, choose M here: the -+ module will be called c67x00. ++ ring->curr = 0; ++ ring->dirty = 0; ++} + -+config USB_XHCI_HCD -+ tristate "xHCI HCD (USB 3.0) support (EXPERIMENTAL)" -+ depends on USB && PCI && EXPERIMENTAL -+ ---help--- -+ The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 -+ "SuperSpeed" host controller hardware. ++static void ag71xx_ring_rx_clean(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->rx_ring; ++ int i; + -+ To compile this driver as a module, choose M here: the -+ module will be called xhci-hcd. -+ -+config USB_XHCI_HCD_DEBUGGING -+ bool "Debugging for the xHCI host controller" -+ depends on USB_XHCI_HCD -+ ---help--- -+ Say 'Y' to turn on debugging for the xHCI host controller driver. -+ This will spew debugging output, even in interrupt context. -+ This should only be used for debugging xHCI driver bugs. -+ -+ If unsure, say N. -+ -+config USB_EHCI_HCD -+ tristate "EHCI HCD (USB 2.0) support" -+ depends on USB && USB_ARCH_HAS_EHCI -+ ---help--- -+ The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 -+ "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. -+ If your USB host controller supports USB 2.0, you will likely want to -+ configure this Host Controller Driver. -+ -+ EHCI controllers are packaged with "companion" host controllers (OHCI -+ or UHCI) to handle USB 1.1 devices connected to root hub ports. Ports -+ will connect to EHCI if the device is high speed, otherwise they -+ connect to a companion controller. If you configure EHCI, you should -+ probably configure the OHCI (for NEC and some other vendors) USB Host -+ Controller Driver or UHCI (for Via motherboards) Host Controller -+ Driver too. -+ -+ You may want to read . ++ if (!ring->buf) ++ return; + -+ To compile this driver as a module, choose M here: the -+ module will be called ehci-hcd. -+ -+config USB_EHCI_ROOT_HUB_TT -+ bool "Root Hub Transaction Translators" -+ depends on USB_EHCI_HCD -+ ---help--- -+ Some EHCI chips have vendor-specific extensions to integrate -+ transaction translators, so that no OHCI or UHCI companion -+ controller is needed. It's safe to say "y" even if your -+ controller doesn't support this feature. -+ -+ This supports the EHCI implementation that's originally -+ from ARC, and has since changed hands a few times. -+ -+config USB_EHCI_TT_NEWSCHED -+ bool "Improved Transaction Translator scheduling (EXPERIMENTAL)" -+ depends on USB_EHCI_HCD && EXPERIMENTAL -+ ---help--- -+ This changes the periodic scheduling code to fill more of the low -+ and full speed bandwidth available from the Transaction Translator -+ (TT) in USB 2.0 hubs. Without this, only one transfer will be -+ issued in each microframe, significantly reducing the number of -+ periodic low/fullspeed transfers possible. -+ -+ If you have multiple periodic low/fullspeed devices connected to a -+ highspeed USB hub which is connected to a highspeed USB Host -+ Controller, and some of those devices will not work correctly -+ (possibly due to "ENOSPC" or "-28" errors), say Y. -+ -+ If unsure, say N. -+ -+config USB_EHCI_BIG_ENDIAN_MMIO -+ bool -+ depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX) -+ default y ++ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) ++ if (ring->buf[i].skb) { ++ dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr, ++ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); ++ kfree_skb(ring->buf[i].skb); ++ } ++} + -+config USB_EHCI_BIG_ENDIAN_DESC -+ bool -+ depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX) -+ default y ++static int ag71xx_rx_reserve(struct ag71xx *ag) ++{ ++ int reserve = 0; + -+config XPS_USB_HCD_XILINX -+ bool "Use Xilinx usb host EHCI controller core" -+ depends on USB_EHCI_HCD && (PPC32 || MICROBLAZE) -+ select USB_EHCI_BIG_ENDIAN_DESC -+ select USB_EHCI_BIG_ENDIAN_MMIO -+ ---help--- -+ Xilinx xps USB host controller core is EHCI compilant and has -+ transaction translator built-in. It can be configured to either -+ support both high speed and full speed devices, or high speed -+ devices only. -+ -+config USB_EHCI_FSL -+ bool "Support for Freescale on-chip EHCI USB controller" -+ depends on USB_EHCI_HCD && FSL_SOC -+ select USB_EHCI_ROOT_HUB_TT -+ ---help--- -+ Variation of ARC USB block used in some Freescale chips. -+ -+config USB_EHCI_MXC -+ bool "Support for Freescale on-chip EHCI USB controller" -+ depends on USB_EHCI_HCD && ARCH_MXC -+ select USB_EHCI_ROOT_HUB_TT -+ ---help--- -+ Variation of ARC USB block used in some Freescale chips. -+ -+config USB_EHCI_HCD_PPC_OF -+ bool "EHCI support for PPC USB controller on OF platform bus" -+ depends on USB_EHCI_HCD && PPC_OF -+ default y -+ ---help--- -+ Enables support for the USB controller present on the PowerPC -+ OpenFirmware platform bus. -+ -+config USB_W90X900_EHCI -+ bool "W90X900(W90P910) EHCI support" -+ depends on USB_EHCI_HCD && ARCH_W90X900 -+ ---help--- -+ Enables support for the W90X900 USB controller -+ -+config USB_OXU210HP_HCD -+ tristate "OXU210HP HCD support" -+ depends on USB -+ ---help--- -+ The OXU210HP is an USB host/OTG/device controller. Enable this -+ option if your board has this chip. If unsure, say N. -+ -+ This driver does not support isochronous transfers and doesn't -+ implement OTG nor USB device controllers. ++ if (ag71xx_get_pdata(ag)->is_ar724x) { ++ if (!ag71xx_has_ar8216(ag)) ++ reserve = 2; + -+ To compile this driver as a module, choose M here: the -+ module will be called oxu210hp-hcd. ++ if (ag->phy_dev) ++ reserve += 4 - (ag->phy_dev->pkt_align % 4); + -+config USB_ISP116X_HCD -+ tristate "ISP116X HCD support" -+ depends on USB -+ ---help--- -+ The ISP1160 and ISP1161 chips are USB host controllers. Enable this -+ option if your board has this chip. If unsure, say N. ++ reserve %= 4; ++ } + -+ This driver does not support isochronous transfers. ++ return reserve + AG71XX_RX_PKT_RESERVE; ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called isp116x-hcd. + -+config USB_ISP1760_HCD -+ tristate "ISP 1760 HCD support" -+ depends on USB && EXPERIMENTAL -+ ---help--- -+ The ISP1760 chip is a USB 2.0 host controller. ++static int ag71xx_ring_rx_init(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->rx_ring; ++ unsigned int reserve = ag71xx_rx_reserve(ag); ++ unsigned int i; ++ int ret; + -+ This driver does not support isochronous transfers or OTG. -+ This USB controller is usually attached to a non-DMA-Master -+ capable bus. NXP's eval kit brings this chip on PCI card -+ where the chip itself is behind a PLB to simulate such -+ a bus. ++ ret = 0; ++ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) { ++ ring->buf[i].desc->next = (u32) (ring->descs_dma + ++ ring->desc_size * ((i + 1) % AG71XX_RX_RING_SIZE)); + -+ To compile this driver as a module, choose M here: the -+ module will be called isp1760. ++ DBG("ag71xx: RX desc at %p, next is %08x\n", ++ ring->buf[i].desc, ++ ring->buf[i].desc->next); ++ } + -+config USB_ISP1362_HCD -+ tristate "ISP1362 HCD support" -+ depends on USB -+ default N -+ ---help--- -+ Supports the Philips ISP1362 chip as a host controller ++ for (i = 0; i < AG71XX_RX_RING_SIZE; i++) { ++ struct sk_buff *skb; ++ dma_addr_t dma_addr; + -+ This driver does not support isochronous transfers. ++ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); ++ if (!skb) { ++ ret = -ENOMEM; ++ break; ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called isp1362-hcd. -+ -+config USB_OHCI_HCD -+ tristate "OHCI HCD support" -+ depends on USB && USB_ARCH_HAS_OHCI -+ select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 -+ select USB_OTG_UTILS if ARCH_OMAP -+ ---help--- -+ The Open Host Controller Interface (OHCI) is a standard for accessing -+ USB 1.1 host controller hardware. It does more in hardware than Intel's -+ UHCI specification. If your USB host controller follows the OHCI spec, -+ say Y. On most non-x86 systems, and on x86 hardware that's not using a -+ USB controller from Intel or VIA, this is appropriate. If your host -+ controller doesn't use PCI, this is probably appropriate. For a PCI -+ based system where you're not sure, the "lspci -v" entry will list the -+ right "prog-if" for your USB controller(s): EHCI, OHCI, or UHCI. ++ skb->dev = ag->dev; ++ skb_reserve(skb, reserve); + -+ To compile this driver as a module, choose M here: the -+ module will be called ohci-hcd. ++ dma_addr = dma_map_single(&ag->dev->dev, skb->data, ++ AG71XX_RX_PKT_SIZE, ++ DMA_FROM_DEVICE); ++ ring->buf[i].skb = skb; ++ ring->buf[i].dma_addr = dma_addr; ++ ring->buf[i].desc->data = (u32) dma_addr; ++ ring->buf[i].desc->ctrl = DESC_EMPTY; ++ } + -+config USB_OHCI_HCD_OMAP1 -+ bool "OHCI support for OMAP1/2 chips" -+ depends on USB_OHCI_HCD && (ARCH_OMAP1 || ARCH_OMAP2) -+ default y -+ ---help--- -+ Enables support for the OHCI controller on OMAP1/2 chips. ++ /* flush descriptors */ ++ wmb(); + -+config USB_OHCI_HCD_OMAP3 -+ bool "OHCI support for OMAP3 and later chips" -+ depends on USB_OHCI_HCD && (ARCH_OMAP3 || ARCH_OMAP4) -+ default y -+ ---help--- -+ Enables support for the on-chip OHCI controller on -+ OMAP3 and later chips. ++ ring->curr = 0; ++ ring->dirty = 0; + -+config USB_OHCI_HCD_PPC_SOC -+ bool "OHCI support for on-chip PPC USB controller" -+ depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) -+ default y -+ select USB_OHCI_BIG_ENDIAN_DESC -+ select USB_OHCI_BIG_ENDIAN_MMIO -+ ---help--- -+ Enables support for the USB controller on the MPC52xx or -+ STB03xxx processor chip. If unsure, say Y. -+ -+config USB_OHCI_HCD_PPC_OF_BE -+ bool "OHCI support for OF platform bus (big endian)" -+ depends on USB_OHCI_HCD && PPC_OF -+ select USB_OHCI_BIG_ENDIAN_DESC -+ select USB_OHCI_BIG_ENDIAN_MMIO -+ ---help--- -+ Enables support for big-endian USB controllers present on the -+ OpenFirmware platform bus. -+ -+config USB_OHCI_HCD_PPC_OF_LE -+ bool "OHCI support for OF platform bus (little endian)" -+ depends on USB_OHCI_HCD && PPC_OF -+ select USB_OHCI_LITTLE_ENDIAN -+ ---help--- -+ Enables support for little-endian USB controllers present on the -+ OpenFirmware platform bus. -+ -+config USB_OHCI_HCD_PPC_OF -+ bool -+ depends on USB_OHCI_HCD && PPC_OF -+ default USB_OHCI_HCD_PPC_OF_BE || USB_OHCI_HCD_PPC_OF_LE ++ return ret; ++} + -+config USB_OHCI_HCD_PCI -+ bool "OHCI support for PCI-bus USB controllers" -+ depends on USB_OHCI_HCD && PCI && (STB03xxx || PPC_MPC52xx || USB_OHCI_HCD_PPC_OF) -+ default y -+ select USB_OHCI_LITTLE_ENDIAN -+ ---help--- -+ Enables support for PCI-bus plug-in USB controller cards. -+ If unsure, say Y. -+ -+config USB_OHCI_HCD_SSB -+ bool "OHCI support for Broadcom SSB OHCI core" -+ depends on USB_OHCI_HCD && (SSB = y || SSB = USB_OHCI_HCD) && EXPERIMENTAL -+ default n -+ ---help--- -+ Support for the Sonics Silicon Backplane (SSB) attached -+ Broadcom USB OHCI core. ++static int ag71xx_ring_rx_refill(struct ag71xx *ag) ++{ ++ struct ag71xx_ring *ring = &ag->rx_ring; ++ unsigned int reserve = ag71xx_rx_reserve(ag); ++ unsigned int count; + -+ This device is present in some embedded devices with -+ Broadcom based SSB bus. ++ count = 0; ++ for (; ring->curr - ring->dirty > 0; ring->dirty++) { ++ unsigned int i; + -+ If unsure, say N. ++ i = ring->dirty % AG71XX_RX_RING_SIZE; + -+config USB_OHCI_BIG_ENDIAN_DESC -+ bool -+ depends on USB_OHCI_HCD -+ default n ++ if (ring->buf[i].skb == NULL) { ++ dma_addr_t dma_addr; ++ struct sk_buff *skb; + -+config USB_OHCI_BIG_ENDIAN_MMIO -+ bool -+ depends on USB_OHCI_HCD -+ default n ++ skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE + reserve); ++ if (skb == NULL) ++ break; + -+config USB_OHCI_LITTLE_ENDIAN -+ bool -+ depends on USB_OHCI_HCD -+ default n if STB03xxx || PPC_MPC52xx -+ default y ++ skb_reserve(skb, reserve); ++ skb->dev = ag->dev; + -+config USB_UHCI_HCD -+ tristate "UHCI HCD (most Intel and VIA) support" -+ depends on USB && PCI -+ ---help--- -+ The Universal Host Controller Interface is a standard by Intel for -+ accessing the USB hardware in the PC (which is also called the USB -+ host controller). If your USB host controller conforms to this -+ standard, you may want to say Y, but see below. All recent boards -+ with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX, -+ i810, i820) conform to this standard. Also all VIA PCI chipsets -+ (like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro -+ 133). If unsure, say Y. ++ dma_addr = dma_map_single(&ag->dev->dev, skb->data, ++ AG71XX_RX_PKT_SIZE, ++ DMA_FROM_DEVICE); + -+ To compile this driver as a module, choose M here: the -+ module will be called uhci-hcd. ++ ring->buf[i].skb = skb; ++ ring->buf[i].dma_addr = dma_addr; ++ ring->buf[i].desc->data = (u32) dma_addr; ++ } + -+config USB_FHCI_HCD -+ tristate "Freescale QE USB Host Controller support" -+ depends on USB && OF_GPIO && QE_GPIO && QUICC_ENGINE -+ select FSL_GTM -+ select QE_USB -+ help -+ This driver enables support for Freescale QE USB Host Controller -+ (as found on MPC8360 and MPC8323 processors), the driver supports -+ Full and Low Speed USB. ++ ring->buf[i].desc->ctrl = DESC_EMPTY; ++ count++; ++ } + -+config FHCI_DEBUG -+ bool "Freescale QE USB Host Controller debug support" -+ depends on USB_FHCI_HCD && DEBUG_FS -+ help -+ Say "y" to see some FHCI debug information and statistics -+ throught debugfs. ++ /* flush descriptors */ ++ wmb(); + -+config USB_U132_HCD -+ tristate "Elan U132 Adapter Host Controller" -+ depends on USB && USB_FTDI_ELAN -+ default M -+ help -+ The U132 adapter is a USB to CardBus adapter specifically designed -+ for PC cards that contain an OHCI host controller. Typical PC cards -+ are the Orange Mobile 3G Option GlobeTrotter Fusion card. The U132 -+ adapter will *NOT* work with PC cards that do not contain an OHCI -+ controller. ++ DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count); + -+ For those PC cards that contain multiple OHCI controllers only the -+ first one is used. ++ return count; ++} + -+ The driver consists of two modules, the "ftdi-elan" module is a -+ USB client driver that interfaces to the FTDI chip within ELAN's -+ USB-to-PCMCIA adapter, and this "u132-hcd" module is a USB host -+ controller driver that talks to the OHCI controller within the -+ CardBus cards that are inserted in the U132 adapter. ++static int ag71xx_rings_init(struct ag71xx *ag) ++{ ++ int ret; + -+ This driver has been tested with a CardBus OHCI USB adapter, and -+ worked with a USB PEN Drive inserted into the first USB port of -+ the PCCARD. A rather pointless thing to do, but useful for testing. ++ ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE); ++ if (ret) ++ return ret; + -+ It is safe to say M here. ++ ag71xx_ring_tx_init(ag); + -+ See also ++ ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE); ++ if (ret) ++ return ret; + -+config USB_SL811_HCD -+ tristate "SL811HS HCD support" -+ depends on USB -+ help -+ The SL811HS is a single-port USB controller that supports either -+ host side or peripheral side roles. Enable this option if your -+ board has this chip, and you want to use it as a host controller. -+ If unsure, say N. ++ ret = ag71xx_ring_rx_init(ag); ++ return ret; ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called sl811-hcd. ++static void ag71xx_rings_cleanup(struct ag71xx *ag) ++{ ++ ag71xx_ring_rx_clean(ag); ++ ag71xx_ring_free(&ag->rx_ring); + -+config USB_SL811_CS -+ tristate "CF/PCMCIA support for SL811HS HCD" -+ depends on USB_SL811_HCD && PCMCIA -+ help -+ Wraps a PCMCIA driver around the SL811HS HCD, supporting the RATOC -+ REX-CFU1U CF card (often used with PDAs). If unsure, say N. ++ ag71xx_ring_tx_clean(ag); ++ ag71xx_ring_free(&ag->tx_ring); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called "sl811_cs". ++static unsigned char *ag71xx_speed_str(struct ag71xx *ag) ++{ ++ switch (ag->speed) { ++ case SPEED_1000: ++ return "1000"; ++ case SPEED_100: ++ return "100"; ++ case SPEED_10: ++ return "10"; ++ } + -+config USB_R8A66597_HCD -+ tristate "R8A66597 HCD support" -+ depends on USB -+ help -+ The R8A66597 is a USB 2.0 host and peripheral controller. ++ return "?"; ++} + -+ Enable this option if your board has this chip, and you want -+ to use it as a host controller. If unsure, say N. ++void ag71xx_link_adjust(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ u32 cfg2; ++ u32 ifctl; ++ u32 fifo5; ++ u32 mii_speed; + -+ To compile this driver as a module, choose M here: the -+ module will be called r8a66597-hcd. -+ -+config USB_WHCI_HCD -+ tristate "Wireless USB Host Controller Interface (WHCI) driver (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ depends on PCI && USB -+ select USB_WUSB -+ select UWB_WHCI -+ help -+ A driver for PCI-based Wireless USB Host Controllers that are -+ compliant with the WHCI specification. -+ -+ To compile this driver a module, choose M here: the module -+ will be called "whci-hcd". -+ -+config USB_HWA_HCD -+ tristate "Host Wire Adapter (HWA) driver (EXPERIMENTAL)" -+ depends on EXPERIMENTAL -+ depends on USB -+ select USB_WUSB -+ select UWB_HWA -+ help -+ This driver enables you to connect Wireless USB devices to -+ your system using a Host Wire Adaptor USB dongle. This is an -+ UWB Radio Controller and WUSB Host Controller connected to -+ your machine via USB (specified in WUSB1.0). -+ -+ To compile this driver a module, choose M here: the module -+ will be called "hwa-hc". -+ -+config USB_IMX21_HCD -+ tristate "iMX21 HCD support" -+ depends on USB && ARM && MACH_MX21 -+ help -+ This driver enables support for the on-chip USB host in the -+ iMX21 processor. -+ -+ To compile this driver as a module, choose M here: the -+ module will be called "imx21-hcd". -+ -diff -Nur linux-2.6.35.7.orig/drivers/usb/host/ohci-ar71xx.c linux-2.6.35.7/drivers/usb/host/ohci-ar71xx.c ---- linux-2.6.35.7.orig/drivers/usb/host/ohci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/usb/host/ohci-ar71xx.c 2010-10-14 20:28:01.428101246 +0200 -@@ -0,0 +1,165 @@ -+/* -+ * OHCI HCD (Host Controller Driver) for USB. -+ * -+ * Bus Glue for Atheros AR71xx built-in OHCI controller. -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * Parts of this file are based on Atheros' 2.6.15 BSP -+ * Copyright (C) 2007 Atheros Communications, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ */ ++ if (!ag->link) { ++ netif_carrier_off(ag->dev); ++ if (netif_msg_link(ag)) ++ printk(KERN_INFO "%s: link down\n", ag->dev->name); ++ return; ++ } + -+#include -+#include ++ cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2); ++ cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX); ++ cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0; + -+extern int usb_disabled(void); ++ ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL); ++ ifctl &= ~(MAC_IFCTL_SPEED); + -+static int usb_hcd_ar71xx_probe(const struct hc_driver *driver, -+ struct platform_device *pdev) -+{ -+ struct usb_hcd *hcd; -+ struct resource *res; -+ int irq; -+ int ret; ++ fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5); ++ fifo5 &= ~FIFO_CFG5_BM; + -+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", -+ dev_name(&pdev->dev)); -+ return -ENODEV; ++ switch (ag->speed) { ++ case SPEED_1000: ++ mii_speed = MII_CTRL_SPEED_1000; ++ cfg2 |= MAC_CFG2_IF_1000; ++ fifo5 |= FIFO_CFG5_BM; ++ break; ++ case SPEED_100: ++ mii_speed = MII_CTRL_SPEED_100; ++ cfg2 |= MAC_CFG2_IF_10_100; ++ ifctl |= MAC_IFCTL_SPEED; ++ break; ++ case SPEED_10: ++ mii_speed = MII_CTRL_SPEED_10; ++ cfg2 |= MAC_CFG2_IF_10_100; ++ break; ++ default: ++ BUG(); ++ return; + } -+ irq = res->start; + -+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); -+ if (!hcd) -+ return -ENOMEM; ++ if (pdata->is_ar91xx) ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff); ++ else if (pdata->is_ar724x) ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3); ++ else ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff); + -+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); -+ if (!res) { -+ dev_dbg(&pdev->dev, "no base address specified for %s\n", -+ dev_name(&pdev->dev)); -+ ret = -ENODEV; -+ goto err_put_hcd; -+ } -+ hcd->rsrc_start = res->start; -+ hcd->rsrc_len = res->end - res->start + 1; ++ if (pdata->set_pll) ++ pdata->set_pll(ag->speed); + -+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { -+ dev_dbg(&pdev->dev, "controller already in use\n"); -+ ret = -EBUSY; -+ goto err_put_hcd; -+ } ++ ag71xx_mii_ctrl_set_speed(ag, mii_speed); + -+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); -+ if (!hcd->regs) { -+ dev_dbg(&pdev->dev, "error mapping memory\n"); -+ ret = -EFAULT; -+ goto err_release_region; -+ } ++ ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2); ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5); ++ ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl); + -+ ohci_hcd_init(hcd_to_ohci(hcd)); ++ netif_carrier_on(ag->dev); ++ if (netif_msg_link(ag)) ++ printk(KERN_INFO "%s: link up (%sMbps/%s duplex)\n", ++ ag->dev->name, ++ ag71xx_speed_str(ag), ++ (DUPLEX_FULL == ag->duplex) ? "Full" : "Half"); + -+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); -+ if (ret) -+ goto err_stop_hcd; ++ DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2)); + -+ return 0; ++ DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4), ++ ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5)); + -+ err_stop_hcd: -+ iounmap(hcd->regs); -+ err_release_region: -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ err_put_hcd: -+ usb_put_hcd(hcd); -+ return ret; ++ DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x, mii_ctrl=%#x\n", ++ ag->dev->name, ++ ag71xx_rr(ag, AG71XX_REG_MAC_CFG2), ++ ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL), ++ ag71xx_mii_ctrl_rr(ag)); +} + -+void usb_hcd_ar71xx_remove(struct usb_hcd *hcd, struct platform_device *pdev) ++static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac) +{ -+ usb_remove_hcd(hcd); -+ iounmap(hcd->regs); -+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); -+ usb_put_hcd(hcd); ++ u32 t; ++ ++ t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16) ++ | (((u32) mac[3]) << 8) | ((u32) mac[2]); ++ ++ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t); ++ ++ t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16); ++ ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t); +} + -+static int __devinit ohci_ar71xx_start(struct usb_hcd *hcd) ++static void ag71xx_dma_reset(struct ag71xx *ag) +{ -+ struct ohci_hcd *ohci = hcd_to_ohci(hcd); -+ int ret; ++ u32 val; ++ int i; + -+ ret = ohci_init(ohci); -+ if (ret < 0) -+ return ret; ++ ag71xx_dump_dma_regs(ag); + -+ ret = ohci_run(ohci); -+ if (ret < 0) -+ goto err; ++ /* stop RX and TX */ ++ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0); ++ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0); + -+ return 0; ++ /* clear descriptor addresses */ ++ ag71xx_wr(ag, AG71XX_REG_TX_DESC, 0); ++ ag71xx_wr(ag, AG71XX_REG_RX_DESC, 0); + -+ err: -+ ohci_stop(hcd); -+ return ret; -+} ++ /* clear pending RX/TX interrupts */ ++ for (i = 0; i < 256; i++) { ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); ++ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); ++ } + -+static const struct hc_driver ohci_ar71xx_hc_driver = { -+ .description = hcd_name, -+ .product_desc = "Atheros AR71xx built-in OHCI controller", -+ .hcd_priv_size = sizeof(struct ohci_hcd), ++ /* clear pending errors */ ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF); ++ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR); + -+ .irq = ohci_irq, -+ .flags = HCD_USB11 | HCD_MEMORY, ++ val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); ++ if (val) ++ printk(KERN_ALERT "%s: unable to clear DMA Rx status: %08x\n", ++ ag->dev->name, val); + -+ .start = ohci_ar71xx_start, -+ .stop = ohci_stop, -+ .shutdown = ohci_shutdown, ++ val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); + -+ .urb_enqueue = ohci_urb_enqueue, -+ .urb_dequeue = ohci_urb_dequeue, -+ .endpoint_disable = ohci_endpoint_disable, ++ /* mask out reserved bits */ ++ val &= ~0xff000000; + -+ /* -+ * scheduling support -+ */ -+ .get_frame_number = ohci_get_frame, ++ if (val) ++ printk(KERN_ALERT "%s: unable to clear DMA Tx status: %08x\n", ++ ag->dev->name, val); + -+ /* -+ * root hub support -+ */ -+ .hub_status_data = ohci_hub_status_data, -+ .hub_control = ohci_hub_control, -+ .start_port_reset = ohci_start_port_reset, -+}; ++ ag71xx_dump_dma_regs(ag); ++} + -+static int ohci_hcd_ar71xx_drv_probe(struct platform_device *pdev) -+{ -+ if (usb_disabled()) -+ return -ENODEV; ++#define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \ ++ MAC_CFG1_SRX | MAC_CFG1_STX) + -+ return usb_hcd_ar71xx_probe(&ohci_ar71xx_hc_driver, pdev); -+} ++#define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT) + -+static int ohci_hcd_ar71xx_drv_remove(struct platform_device *pdev) ++#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \ ++ FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \ ++ FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \ ++ FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \ ++ FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \ ++ FIFO_CFG4_VT) ++ ++#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \ ++ FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \ ++ FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \ ++ FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \ ++ FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \ ++ FIFO_CFG5_17 | FIFO_CFG5_SF) ++ ++static void ag71xx_hw_init(struct ag71xx *ag) +{ -+ struct usb_hcd *hcd = platform_get_drvdata(pdev); ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + -+ usb_hcd_ar71xx_remove(hcd, pdev); -+ return 0; -+} ++ ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR); ++ udelay(20); + -+MODULE_ALIAS("platform:ar71xx-ohci"); ++ ar71xx_device_stop(pdata->reset_bit); ++ mdelay(100); ++ ar71xx_device_start(pdata->reset_bit); ++ mdelay(100); + -+static struct platform_driver ohci_hcd_ar71xx_driver = { -+ .probe = ohci_hcd_ar71xx_drv_probe, -+ .remove = ohci_hcd_ar71xx_drv_remove, -+ .shutdown = usb_hcd_platform_shutdown, -+ .driver = { -+ .name = "ar71xx-ohci", -+ .owner = THIS_MODULE, -+ }, -+}; -diff -Nur linux-2.6.35.7.orig/drivers/usb/host/ohci-hcd.c linux-2.6.35.7/drivers/usb/host/ohci-hcd.c ---- linux-2.6.35.7.orig/drivers/usb/host/ohci-hcd.c 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/usb/host/ohci-hcd.c 2010-10-14 20:28:01.468101083 +0200 -@@ -1095,6 +1095,11 @@ - #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver - #endif - -+#ifdef CONFIG_USB_OHCI_AR71XX -+#include "ohci-ar71xx.c" -+#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver -+#endif ++ /* setup MAC configuration registers */ ++ if (pdata->is_ar724x) ++ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, ++ MAC_CFG1_INIT | MAC_CFG1_TFC | MAC_CFG1_RFC); ++ else ++ ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT); + - #if !defined(PCI_DRIVER) && \ - !defined(PLATFORM_DRIVER) && \ - !defined(OMAP1_PLATFORM_DRIVER) && \ -diff -Nur linux-2.6.35.7.orig/drivers/usb/host/ohci-hcd.c.orig linux-2.6.35.7/drivers/usb/host/ohci-hcd.c.orig ---- linux-2.6.35.7.orig/drivers/usb/host/ohci-hcd.c.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/usb/host/ohci-hcd.c.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,1277 @@ -+/* -+ * OHCI HCD (Host Controller Driver) for USB. -+ * -+ * (C) Copyright 1999 Roman Weissgaerber -+ * (C) Copyright 2000-2004 David Brownell -+ * -+ * [ Initialisation is based on Linus' ] -+ * [ uhci code and gregs ohci fragments ] -+ * [ (C) Copyright 1999 Linus Torvalds ] -+ * [ (C) Copyright 1999 Gregory P. Smith] -+ * -+ * -+ * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller -+ * interfaces (though some non-x86 Intel chips use it). It supports -+ * smarter hardware than UHCI. A download link for the spec available -+ * through the http://www.usb.org website. -+ * -+ * This file is licenced under the GPL. -+ */ ++ ag71xx_sb(ag, AG71XX_REG_MAC_CFG2, ++ MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK); + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include ++ /* setup max frame length */ ++ ag71xx_wr(ag, AG71XX_REG_MAC_MFL, AG71XX_TX_MTU_LEN); ++ ++ /* setup MII interface type */ ++ ag71xx_mii_ctrl_set_if(ag, pdata->mii_if); + -+#include -+#include -+#include -+#include -+#include ++ /* setup FIFO configuration registers */ ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT); ++ if (pdata->is_ar724x) { ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1); ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2); ++ } else { ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000); ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff); ++ } ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT); ++ ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT); + ++ ag71xx_dma_reset(ag); ++} + -+#define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell" -+#define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver" ++static void ag71xx_hw_start(struct ag71xx *ag) ++{ ++ /* start RX engine */ ++ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); + -+/*-------------------------------------------------------------------------*/ ++ /* enable interrupts */ ++ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT); ++} + -+#undef OHCI_VERBOSE_DEBUG /* not always helpful */ ++static void ag71xx_hw_stop(struct ag71xx *ag) ++{ ++ /* disable all interrupts */ ++ ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0); + -+/* For initializing controller (mask in an HCFS mode too) */ -+#define OHCI_CONTROL_INIT OHCI_CTRL_CBSR -+#define OHCI_INTR_INIT \ -+ (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \ -+ | OHCI_INTR_RD | OHCI_INTR_WDH) ++ ag71xx_dma_reset(ag); ++} + -+#ifdef __hppa__ -+/* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */ -+#define IR_DISABLE -+#endif ++static int ag71xx_open(struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ int ret; + -+#ifdef CONFIG_ARCH_OMAP -+/* OMAP doesn't support IR (no SMM; not needed) */ -+#define IR_DISABLE -+#endif ++ ret = ag71xx_rings_init(ag); ++ if (ret) ++ goto err; + -+/*-------------------------------------------------------------------------*/ ++ napi_enable(&ag->napi); + -+static const char hcd_name [] = "ohci_hcd"; ++ netif_carrier_off(dev); ++ ag71xx_phy_start(ag); + -+#define STATECHANGE_DELAY msecs_to_jiffies(300) ++ ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma); ++ ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma); + -+#include "ohci.h" ++ ag71xx_hw_set_macaddr(ag, dev->dev_addr); + -+static void ohci_dump (struct ohci_hcd *ohci, int verbose); -+static int ohci_init (struct ohci_hcd *ohci); -+static void ohci_stop (struct usb_hcd *hcd); ++ ag71xx_hw_start(ag); + -+#if defined(CONFIG_PM) || defined(CONFIG_PCI) -+static int ohci_restart (struct ohci_hcd *ohci); -+#endif ++ netif_start_queue(dev); + -+#ifdef CONFIG_PCI -+static void quirk_amd_pll(int state); -+static void amd_iso_dev_put(void); -+static void sb800_prefetch(struct ohci_hcd *ohci, int on); -+#else -+static inline void quirk_amd_pll(int state) -+{ -+ return; -+} -+static inline void amd_iso_dev_put(void) -+{ -+ return; ++ return 0; ++ ++ err: ++ ag71xx_rings_cleanup(ag); ++ return ret; +} -+static inline void sb800_prefetch(struct ohci_hcd *ohci, int on) ++ ++static int ag71xx_stop(struct net_device *dev) +{ -+ return; -+} -+#endif ++ struct ag71xx *ag = netdev_priv(dev); ++ unsigned long flags; + ++ netif_carrier_off(dev); ++ ag71xx_phy_stop(ag); + -+#include "ohci-hub.c" -+#include "ohci-dbg.c" -+#include "ohci-mem.c" -+#include "ohci-q.c" ++ spin_lock_irqsave(&ag->lock, flags); + ++ netif_stop_queue(dev); + -+/* -+ * On architectures with edge-triggered interrupts we must never return -+ * IRQ_NONE. -+ */ -+#if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */ -+#define IRQ_NOTMINE IRQ_HANDLED -+#else -+#define IRQ_NOTMINE IRQ_NONE -+#endif ++ ag71xx_hw_stop(ag); + ++ napi_disable(&ag->napi); ++ del_timer_sync(&ag->oom_timer); + -+/* Some boards misreport power switching/overcurrent */ -+static int distrust_firmware = 1; -+module_param (distrust_firmware, bool, 0); -+MODULE_PARM_DESC (distrust_firmware, -+ "true to distrust firmware power/overcurrent setup"); ++ spin_unlock_irqrestore(&ag->lock, flags); + -+/* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */ -+static int no_handshake = 0; -+module_param (no_handshake, bool, 0); -+MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake"); ++ ag71xx_rings_cleanup(ag); + -+/*-------------------------------------------------------------------------*/ ++ return 0; ++} + -+/* -+ * queue up an urb for anything except the root hub -+ */ -+static int ohci_urb_enqueue ( -+ struct usb_hcd *hcd, -+ struct urb *urb, -+ gfp_t mem_flags -+) { -+ struct ohci_hcd *ohci = hcd_to_ohci (hcd); -+ struct ed *ed; -+ urb_priv_t *urb_priv; -+ unsigned int pipe = urb->pipe; -+ int i, size = 0; -+ unsigned long flags; -+ int retval = 0; -+ -+#ifdef OHCI_VERBOSE_DEBUG -+ urb_print(urb, "SUB", usb_pipein(pipe), -EINPROGRESS); -+#endif ++static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb, ++ struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ struct ag71xx_ring *ring = &ag->tx_ring; ++ struct ag71xx_desc *desc; ++ dma_addr_t dma_addr; ++ int i; + -+ /* every endpoint has a ed, locate and maybe (re)initialize it */ -+ if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval))) -+ return -ENOMEM; ++ i = ring->curr % AG71XX_TX_RING_SIZE; ++ desc = ring->buf[i].desc; + -+ /* for the private part of the URB we need the number of TDs (size) */ -+ switch (ed->type) { -+ case PIPE_CONTROL: -+ /* td_submit_urb() doesn't yet handle these */ -+ if (urb->transfer_buffer_length > 4096) -+ return -EMSGSIZE; -+ -+ /* 1 TD for setup, 1 for ACK, plus ... */ -+ size = 2; -+ /* FALLTHROUGH */ -+ // case PIPE_INTERRUPT: -+ // case PIPE_BULK: -+ default: -+ /* one TD for every 4096 Bytes (can be upto 8K) */ -+ size += urb->transfer_buffer_length / 4096; -+ /* ... and for any remaining bytes ... */ -+ if ((urb->transfer_buffer_length % 4096) != 0) -+ size++; -+ /* ... and maybe a zero length packet to wrap it up */ -+ if (size == 0) -+ size++; -+ else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0 -+ && (urb->transfer_buffer_length -+ % usb_maxpacket (urb->dev, pipe, -+ usb_pipeout (pipe))) == 0) -+ size++; -+ break; -+ case PIPE_ISOCHRONOUS: /* number of packets from URB */ -+ size = urb->number_of_packets; -+ break; -+ } ++ if (!ag71xx_desc_empty(desc)) ++ goto err_drop; + -+ /* allocate the private part of the URB */ -+ urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *), -+ mem_flags); -+ if (!urb_priv) -+ return -ENOMEM; -+ INIT_LIST_HEAD (&urb_priv->pending); -+ urb_priv->length = size; -+ urb_priv->ed = ed; ++ if (ag71xx_has_ar8216(ag)) ++ ag71xx_add_ar8216_header(ag, skb); + -+ /* allocate the TDs (deferring hash chain updates) */ -+ for (i = 0; i < size; i++) { -+ urb_priv->td [i] = td_alloc (ohci, mem_flags); -+ if (!urb_priv->td [i]) { -+ urb_priv->length = i; -+ urb_free_priv (ohci, urb_priv); -+ return -ENOMEM; -+ } ++ if (skb->len <= 0) { ++ DBG("%s: packet len is too small\n", ag->dev->name); ++ goto err_drop; + } + -+ spin_lock_irqsave (&ohci->lock, flags); ++ dma_addr = dma_map_single(&dev->dev, skb->data, skb->len, ++ DMA_TO_DEVICE); + -+ /* don't submit to a dead HC */ -+ if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) { -+ retval = -ENODEV; -+ goto fail; -+ } -+ if (!HC_IS_RUNNING(hcd->state)) { -+ retval = -ENODEV; -+ goto fail; -+ } -+ retval = usb_hcd_link_urb_to_ep(hcd, urb); -+ if (retval) -+ goto fail; ++ ring->buf[i].skb = skb; + -+ /* schedule the ed if needed */ -+ if (ed->state == ED_IDLE) { -+ retval = ed_schedule (ohci, ed); -+ if (retval < 0) { -+ usb_hcd_unlink_urb_from_ep(hcd, urb); -+ goto fail; -+ } -+ if (ed->type == PIPE_ISOCHRONOUS) { -+ u16 frame = ohci_frame_no(ohci); -+ -+ /* delay a few frames before the first TD */ -+ frame += max_t (u16, 8, ed->interval); -+ frame &= ~(ed->interval - 1); -+ frame |= ed->branch; -+ urb->start_frame = frame; -+ -+ /* yes, only URB_ISO_ASAP is supported, and -+ * urb->start_frame is never used as input. -+ */ -+ } -+ } else if (ed->type == PIPE_ISOCHRONOUS) -+ urb->start_frame = ed->last_iso + ed->interval; ++ /* setup descriptor fields */ ++ desc->data = (u32) dma_addr; ++ desc->ctrl = (skb->len & DESC_PKTLEN_M); + -+ /* fill the TDs and link them to the ed; and -+ * enable that part of the schedule, if needed -+ * and update count of queued periodic urbs -+ */ -+ urb->hcpriv = urb_priv; -+ td_submit_urb (ohci, urb); ++ /* flush descriptor */ ++ wmb(); + -+fail: -+ if (retval) -+ urb_free_priv (ohci, urb_priv); -+ spin_unlock_irqrestore (&ohci->lock, flags); -+ return retval; -+} ++ ring->curr++; ++ if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) { ++ DBG("%s: tx queue full\n", ag->dev->name); ++ netif_stop_queue(dev); ++ } + -+/* -+ * decouple the URB from the HC queues (TDs, urb_priv). -+ * reporting is always done -+ * asynchronously, and we might be dealing with an urb that's -+ * partially transferred, or an ED with other urbs being unlinked. -+ */ -+static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) -+{ -+ struct ohci_hcd *ohci = hcd_to_ohci (hcd); -+ unsigned long flags; -+ int rc; ++ DBG("%s: packet injected into TX queue\n", ag->dev->name); + -+#ifdef OHCI_VERBOSE_DEBUG -+ urb_print(urb, "UNLINK", 1, status); -+#endif ++ /* enable TX engine */ ++ ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE); + -+ spin_lock_irqsave (&ohci->lock, flags); -+ rc = usb_hcd_check_unlink_urb(hcd, urb, status); -+ if (rc) { -+ ; /* Do nothing */ -+ } else if (HC_IS_RUNNING(hcd->state)) { -+ urb_priv_t *urb_priv; ++ return NETDEV_TX_OK; + -+ /* Unless an IRQ completed the unlink while it was being -+ * handed to us, flag it for unlink and giveback, and force -+ * some upcoming INTR_SF to call finish_unlinks() -+ */ -+ urb_priv = urb->hcpriv; -+ if (urb_priv) { -+ if (urb_priv->ed->state == ED_OPER) -+ start_ed_unlink (ohci, urb_priv->ed); -+ } -+ } else { -+ /* -+ * with HC dead, we won't respect hc queue pointers -+ * any more ... just clean up every urb's memory. -+ */ -+ if (urb->hcpriv) -+ finish_urb(ohci, urb, status); -+ } -+ spin_unlock_irqrestore (&ohci->lock, flags); -+ return rc; ++ err_drop: ++ dev->stats.tx_dropped++; ++ ++ dev_kfree_skb(skb); ++ return NETDEV_TX_OK; +} + -+/*-------------------------------------------------------------------------*/ ++static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data; ++ struct ag71xx *ag = netdev_priv(dev); ++ int ret; + -+/* frees config/altsetting state for endpoints, -+ * including ED memory, dummy TD, and bulk/intr data toggle -+ */ ++ switch (cmd) { ++ case SIOCETHTOOL: ++ if (ag->phy_dev == NULL) ++ break; + -+static void -+ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep) -+{ -+ struct ohci_hcd *ohci = hcd_to_ohci (hcd); -+ unsigned long flags; -+ struct ed *ed = ep->hcpriv; -+ unsigned limit = 1000; ++ spin_lock_irq(&ag->lock); ++ ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data); ++ spin_unlock_irq(&ag->lock); ++ return ret; + -+ /* ASSERT: any requests/urbs are being unlinked */ -+ /* ASSERT: nobody can be submitting urbs for this any more */ ++ case SIOCSIFHWADDR: ++ if (copy_from_user ++ (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; + -+ if (!ed) -+ return; ++ case SIOCGIFHWADDR: ++ if (copy_to_user ++ (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr))) ++ return -EFAULT; ++ return 0; + -+rescan: -+ spin_lock_irqsave (&ohci->lock, flags); -+ -+ if (!HC_IS_RUNNING (hcd->state)) { -+sanitize: -+ ed->state = ED_IDLE; -+ if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT) -+ ohci->eds_scheduled--; -+ finish_unlinks (ohci, 0); -+ } -+ -+ switch (ed->state) { -+ case ED_UNLINK: /* wait for hw to finish? */ -+ /* major IRQ delivery trouble loses INTR_SF too... */ -+ if (limit-- == 0) { -+ ohci_warn(ohci, "ED unlink timeout\n"); -+ if (quirk_zfmicro(ohci)) { -+ ohci_warn(ohci, "Attempting ZF TD recovery\n"); -+ ohci->ed_to_check = ed; -+ ohci->zf_delay = 2; -+ } -+ goto sanitize; -+ } -+ spin_unlock_irqrestore (&ohci->lock, flags); -+ schedule_timeout_uninterruptible(1); -+ goto rescan; -+ case ED_IDLE: /* fully unlinked */ -+ if (list_empty (&ed->td_list)) { -+ td_free (ohci, ed->dummy); -+ ed_free (ohci, ed); ++ case SIOCGMIIPHY: ++ case SIOCGMIIREG: ++ case SIOCSMIIREG: ++ if (ag->phy_dev == NULL) + break; -+ } -+ /* else FALL THROUGH */ ++ ++ return phy_mii_ioctl(ag->phy_dev, data, cmd); ++ + default: -+ /* caller was supposed to have unlinked any requests; -+ * that's not our job. can't recover; must leak ed. -+ */ -+ ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n", -+ ed, ep->desc.bEndpointAddress, ed->state, -+ list_empty (&ed->td_list) ? "" : " (has tds)"); -+ td_free (ohci, ed->dummy); + break; + } -+ ep->hcpriv = NULL; -+ spin_unlock_irqrestore (&ohci->lock, flags); -+ return; ++ ++ return -EOPNOTSUPP; +} + -+static int ohci_get_frame (struct usb_hcd *hcd) ++static void ag71xx_oom_timer_handler(unsigned long data) +{ -+ struct ohci_hcd *ohci = hcd_to_ohci (hcd); ++ struct net_device *dev = (struct net_device *) data; ++ struct ag71xx *ag = netdev_priv(dev); + -+ return ohci_frame_no(ohci); ++ napi_schedule(&ag->napi); +} + -+static void ohci_usb_reset (struct ohci_hcd *ohci) ++static void ag71xx_tx_timeout(struct net_device *dev) +{ -+ ohci->hc_control = ohci_readl (ohci, &ohci->regs->control); -+ ohci->hc_control &= OHCI_CTRL_RWC; -+ ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); -+} ++ struct ag71xx *ag = netdev_priv(dev); + -+/* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and -+ * other cases where the next software may expect clean state from the -+ * "firmware". this is bus-neutral, unlike shutdown() methods. -+ */ -+static void -+ohci_shutdown (struct usb_hcd *hcd) -+{ -+ struct ohci_hcd *ohci; ++ if (netif_msg_tx_err(ag)) ++ printk(KERN_DEBUG "%s: tx timeout\n", ag->dev->name); + -+ ohci = hcd_to_ohci (hcd); -+ ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); -+ ohci_usb_reset (ohci); -+ /* flush the writes */ -+ (void) ohci_readl (ohci, &ohci->regs->control); ++ schedule_work(&ag->restart_work); +} + -+static int check_ed(struct ohci_hcd *ohci, struct ed *ed) ++static void ag71xx_restart_work_func(struct work_struct *work) +{ -+ return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0 -+ && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK) -+ == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK) -+ && !list_empty(&ed->td_list); ++ struct ag71xx *ag = container_of(work, struct ag71xx, restart_work); ++ ++ ag71xx_stop(ag->dev); ++ ag71xx_open(ag->dev); +} + -+/* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes -+ * an interrupt TD but neglects to add it to the donelist. On systems with -+ * this chipset, we need to periodically check the state of the queues to look -+ * for such "lost" TDs. -+ */ -+static void unlink_watchdog_func(unsigned long _ohci) ++static int ag71xx_tx_packets(struct ag71xx *ag) +{ -+ unsigned long flags; -+ unsigned max; -+ unsigned seen_count = 0; -+ unsigned i; -+ struct ed **seen = NULL; -+ struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci; -+ -+ spin_lock_irqsave(&ohci->lock, flags); -+ max = ohci->eds_scheduled; -+ if (!max) -+ goto done; ++ struct ag71xx_ring *ring = &ag->tx_ring; ++ int sent; + -+ if (ohci->ed_to_check) -+ goto out; ++ DBG("%s: processing TX ring\n", ag->dev->name); + -+ seen = kcalloc(max, sizeof *seen, GFP_ATOMIC); -+ if (!seen) -+ goto out; ++ sent = 0; ++ while (ring->dirty != ring->curr) { ++ unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE; ++ struct ag71xx_desc *desc = ring->buf[i].desc; ++ struct sk_buff *skb = ring->buf[i].skb; + -+ for (i = 0; i < NUM_INTS; i++) { -+ struct ed *ed = ohci->periodic[i]; ++ if (!ag71xx_desc_empty(desc)) ++ break; + -+ while (ed) { -+ unsigned temp; ++ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS); + -+ /* scan this branch of the periodic schedule tree */ -+ for (temp = 0; temp < seen_count; temp++) { -+ if (seen[temp] == ed) { -+ /* we've checked it and what's after */ -+ ed = NULL; -+ break; -+ } -+ } -+ if (!ed) -+ break; -+ seen[seen_count++] = ed; -+ if (!check_ed(ohci, ed)) { -+ ed = ed->ed_next; -+ continue; -+ } ++ ag->dev->stats.tx_bytes += skb->len; ++ ag->dev->stats.tx_packets++; + -+ /* HC's TD list is empty, but HCD sees at least one -+ * TD that's not been sent through the donelist. -+ */ -+ ohci->ed_to_check = ed; -+ ohci->zf_delay = 2; -+ -+ /* The HC may wait until the next frame to report the -+ * TD as done through the donelist and INTR_WDH. (We -+ * just *assume* it's not a multi-TD interrupt URB; -+ * those could defer the IRQ more than one frame, using -+ * DI...) Check again after the next INTR_SF. -+ */ -+ ohci_writel(ohci, OHCI_INTR_SF, -+ &ohci->regs->intrstatus); -+ ohci_writel(ohci, OHCI_INTR_SF, -+ &ohci->regs->intrenable); -+ -+ /* flush those writes */ -+ (void) ohci_readl(ohci, &ohci->regs->control); ++ dev_kfree_skb_any(skb); ++ ring->buf[i].skb = NULL; + -+ goto out; -+ } ++ ring->dirty++; ++ sent++; + } -+out: -+ kfree(seen); -+ if (ohci->eds_scheduled) -+ mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ)); -+done: -+ spin_unlock_irqrestore(&ohci->lock, flags); -+} + -+/*-------------------------------------------------------------------------* -+ * HC functions -+ *-------------------------------------------------------------------------*/ ++ DBG("%s: %d packets sent out\n", ag->dev->name, sent); ++ ++ if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP) ++ netif_wake_queue(ag->dev); + -+/* init memory, and kick BIOS/SMM off */ ++ return sent; ++} + -+static int ohci_init (struct ohci_hcd *ohci) ++static int ag71xx_rx_packets(struct ag71xx *ag, int limit) +{ -+ int ret; -+ struct usb_hcd *hcd = ohci_to_hcd(ohci); ++ struct net_device *dev = ag->dev; ++ struct ag71xx_ring *ring = &ag->rx_ring; ++ int done = 0; + -+ if (distrust_firmware) -+ ohci->flags |= OHCI_QUIRK_HUB_POWER; ++ DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n", ++ dev->name, limit, ring->curr, ring->dirty); + -+ disable (ohci); -+ ohci->regs = hcd->regs; ++ while (done < limit) { ++ unsigned int i = ring->curr % AG71XX_RX_RING_SIZE; ++ struct ag71xx_desc *desc = ring->buf[i].desc; ++ struct sk_buff *skb; ++ int pktlen; ++ int err = 0; + -+ /* REVISIT this BIOS handshake is now moved into PCI "quirks", and -+ * was never needed for most non-PCI systems ... remove the code? -+ */ ++ if (ag71xx_desc_empty(desc)) ++ break; + -+#ifndef IR_DISABLE -+ /* SMM owns the HC? not for long! */ -+ if (!no_handshake && ohci_readl (ohci, -+ &ohci->regs->control) & OHCI_CTRL_IR) { -+ u32 temp; ++ if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) { ++ ag71xx_assert(0); ++ break; ++ } + -+ ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n"); ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR); + -+ /* this timeout is arbitrary. we make it long, so systems -+ * depending on usb keyboards may be usable even if the -+ * BIOS/SMM code seems pretty broken. -+ */ -+ temp = 500; /* arbitrary: five seconds */ -+ -+ ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable); -+ ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus); -+ while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) { -+ msleep (10); -+ if (--temp == 0) { -+ ohci_err (ohci, "USB HC takeover failed!" -+ " (BIOS/SMM bug)\n"); -+ return -EBUSY; ++ skb = ring->buf[i].skb; ++ pktlen = ag71xx_desc_pktlen(desc); ++ pktlen -= ETH_FCS_LEN; ++ ++ dma_unmap_single(&dev->dev, ring->buf[i].dma_addr, ++ AG71XX_RX_PKT_SIZE, DMA_FROM_DEVICE); ++ ++ dev->last_rx = jiffies; ++ dev->stats.rx_packets++; ++ dev->stats.rx_bytes += pktlen; ++ ++ skb_put(skb, pktlen); ++ if (ag71xx_has_ar8216(ag)) ++ err = ag71xx_remove_ar8216_header(ag, skb, pktlen); ++ ++ if (err) { ++ dev->stats.rx_dropped++; ++ kfree_skb(skb); ++ } else { ++ skb->dev = dev; ++ skb->ip_summed = CHECKSUM_NONE; ++ if (ag->phy_dev) { ++ ag->phy_dev->netif_receive_skb(skb); ++ } else { ++ skb->protocol = eth_type_trans(skb, dev); ++ netif_receive_skb(skb); + } + } -+ ohci_usb_reset (ohci); ++ ++ ring->buf[i].skb = NULL; ++ done++; ++ ++ ring->curr++; + } -+#endif + -+ /* Disable HC interrupts */ -+ ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); ++ ag71xx_ring_rx_refill(ag); + -+ /* flush the writes, and save key bits like RWC */ -+ if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC) -+ ohci->hc_control |= OHCI_CTRL_RWC; ++ DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n", ++ dev->name, ring->curr, ring->dirty, done); + -+ /* Read the number of ports unless overridden */ -+ if (ohci->num_ports == 0) -+ ohci->num_ports = roothub_a(ohci) & RH_A_NDP; ++ return done; ++} + -+ if (ohci->hcca) -+ return 0; ++static int ag71xx_poll(struct napi_struct *napi, int limit) ++{ ++ struct ag71xx *ag = container_of(napi, struct ag71xx, napi); ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ struct net_device *dev = ag->dev; ++ struct ag71xx_ring *rx_ring; ++ unsigned long flags; ++ u32 status; ++ int tx_done; ++ int rx_done; ++ ++ pdata->ddr_flush(); ++ tx_done = ag71xx_tx_packets(ag); ++ ++ DBG("%s: processing RX ring\n", dev->name); ++ rx_done = ag71xx_rx_packets(ag, limit); ++ ++ ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done); ++ ++ rx_ring = &ag->rx_ring; ++ if (rx_ring->buf[rx_ring->dirty % AG71XX_RX_RING_SIZE].skb == NULL) ++ goto oom; + -+ ohci->hcca = dma_alloc_coherent (hcd->self.controller, -+ sizeof *ohci->hcca, &ohci->hcca_dma, 0); -+ if (!ohci->hcca) -+ return -ENOMEM; ++ status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS); ++ if (unlikely(status & RX_STATUS_OF)) { ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF); ++ dev->stats.rx_fifo_errors++; + -+ if ((ret = ohci_mem_init (ohci)) < 0) -+ ohci_stop (hcd); -+ else { -+ create_debug_files (ohci); ++ /* restart RX */ ++ ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE); + } + -+ return ret; -+} -+ -+/*-------------------------------------------------------------------------*/ ++ if (rx_done < limit) { ++ if (status & RX_STATUS_PR) ++ goto more; + -+/* Start an OHCI controller, set the BUS operational -+ * resets USB and controller -+ * enable interrupts -+ */ -+static int ohci_run (struct ohci_hcd *ohci) -+{ -+ u32 mask, val; -+ int first = ohci->fminterval == 0; -+ struct usb_hcd *hcd = ohci_to_hcd(ohci); ++ status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS); ++ if (status & TX_STATUS_PS) ++ goto more; + -+ disable (ohci); ++ DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n", ++ dev->name, rx_done, tx_done, limit); + -+ /* boot firmware should have set this up (5.1.1.3.1) */ -+ if (first) { ++ napi_complete(napi); + -+ val = ohci_readl (ohci, &ohci->regs->fminterval); -+ ohci->fminterval = val & 0x3fff; -+ if (ohci->fminterval != FI) -+ ohci_dbg (ohci, "fminterval delta %d\n", -+ ohci->fminterval - FI); -+ ohci->fminterval |= FSMP (ohci->fminterval) << 16; -+ /* also: power/overcurrent flags in roothub.a */ ++ /* enable interrupts */ ++ spin_lock_irqsave(&ag->lock, flags); ++ ag71xx_int_enable(ag, AG71XX_INT_POLL); ++ spin_unlock_irqrestore(&ag->lock, flags); ++ return rx_done; + } + -+ /* Reset USB nearly "by the book". RemoteWakeupConnected has -+ * to be checked in case boot firmware (BIOS/SMM/...) has set up -+ * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM). -+ * If the bus glue detected wakeup capability then it should -+ * already be enabled; if so we'll just enable it again. -+ */ -+ if ((ohci->hc_control & OHCI_CTRL_RWC) != 0) -+ device_set_wakeup_capable(hcd->self.controller, 1); ++ more: ++ DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n", ++ dev->name, rx_done, tx_done, limit); ++ return rx_done; + -+ switch (ohci->hc_control & OHCI_CTRL_HCFS) { -+ case OHCI_USB_OPER: -+ val = 0; -+ break; -+ case OHCI_USB_SUSPEND: -+ case OHCI_USB_RESUME: -+ ohci->hc_control &= OHCI_CTRL_RWC; -+ ohci->hc_control |= OHCI_USB_RESUME; -+ val = 10 /* msec wait */; -+ break; -+ // case OHCI_USB_RESET: -+ default: -+ ohci->hc_control &= OHCI_CTRL_RWC; -+ ohci->hc_control |= OHCI_USB_RESET; -+ val = 50 /* msec wait */; -+ break; -+ } -+ ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); -+ // flush the writes -+ (void) ohci_readl (ohci, &ohci->regs->control); -+ msleep(val); -+ -+ memset (ohci->hcca, 0, sizeof (struct ohci_hcca)); -+ -+ /* 2msec timelimit here means no irqs/preempt */ -+ spin_lock_irq (&ohci->lock); -+ -+retry: -+ /* HC Reset requires max 10 us delay */ -+ ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus); -+ val = 30; /* ... allow extra time */ -+ while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) { -+ if (--val == 0) { -+ spin_unlock_irq (&ohci->lock); -+ ohci_err (ohci, "USB HC reset timed out!\n"); -+ return -1; -+ } -+ udelay (1); -+ } ++ oom: ++ if (netif_msg_rx_err(ag)) ++ printk(KERN_DEBUG "%s: out of memory\n", dev->name); + -+ /* now we're in the SUSPEND state ... must go OPERATIONAL -+ * within 2msec else HC enters RESUME -+ * -+ * ... but some hardware won't init fmInterval "by the book" -+ * (SiS, OPTi ...), so reset again instead. SiS doesn't need -+ * this if we write fmInterval after we're OPERATIONAL. -+ * Unclear about ALi, ServerWorks, and others ... this could -+ * easily be a longstanding bug in chip init on Linux. -+ */ -+ if (ohci->flags & OHCI_QUIRK_INITRESET) { -+ ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); -+ // flush those writes -+ (void) ohci_readl (ohci, &ohci->regs->control); -+ } ++ mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL); ++ napi_complete(napi); ++ return 0; ++} + -+ /* Tell the controller where the control and bulk lists are -+ * The lists are empty now. */ -+ ohci_writel (ohci, 0, &ohci->regs->ed_controlhead); -+ ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead); ++static irqreturn_t ag71xx_interrupt(int irq, void *dev_id) ++{ ++ struct net_device *dev = dev_id; ++ struct ag71xx *ag = netdev_priv(dev); ++ u32 status; + -+ /* a reset clears this */ -+ ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca); ++ status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS); ++ ag71xx_dump_intr(ag, "raw", status); + -+ periodic_reinit (ohci); ++ if (unlikely(!status)) ++ return IRQ_NONE; + -+ /* some OHCI implementations are finicky about how they init. -+ * bogus values here mean not even enumeration could work. -+ */ -+ if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0 -+ || !ohci_readl (ohci, &ohci->regs->periodicstart)) { -+ if (!(ohci->flags & OHCI_QUIRK_INITRESET)) { -+ ohci->flags |= OHCI_QUIRK_INITRESET; -+ ohci_dbg (ohci, "enabling initreset quirk\n"); -+ goto retry; ++ if (unlikely(status & AG71XX_INT_ERR)) { ++ if (status & AG71XX_INT_TX_BE) { ++ ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE); ++ dev_err(&dev->dev, "TX BUS error\n"); ++ } ++ if (status & AG71XX_INT_RX_BE) { ++ ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE); ++ dev_err(&dev->dev, "RX BUS error\n"); + } -+ spin_unlock_irq (&ohci->lock); -+ ohci_err (ohci, "init err (%08x %04x)\n", -+ ohci_readl (ohci, &ohci->regs->fminterval), -+ ohci_readl (ohci, &ohci->regs->periodicstart)); -+ return -EOVERFLOW; -+ } -+ -+ /* use rhsc irqs after khubd is fully initialized */ -+ hcd->poll_rh = 1; -+ hcd->uses_new_polling = 1; -+ -+ /* start controller operations */ -+ ohci->hc_control &= OHCI_CTRL_RWC; -+ ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER; -+ ohci_writel (ohci, ohci->hc_control, &ohci->regs->control); -+ hcd->state = HC_STATE_RUNNING; -+ -+ /* wake on ConnectStatusChange, matching external hubs */ -+ ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status); -+ -+ /* Choose the interrupts we care about now, others later on demand */ -+ mask = OHCI_INTR_INIT; -+ ohci_writel (ohci, ~0, &ohci->regs->intrstatus); -+ ohci_writel (ohci, mask, &ohci->regs->intrenable); -+ -+ /* handle root hub init quirks ... */ -+ val = roothub_a (ohci); -+ val &= ~(RH_A_PSM | RH_A_OCPM); -+ if (ohci->flags & OHCI_QUIRK_SUPERIO) { -+ /* NSC 87560 and maybe others */ -+ val |= RH_A_NOCP; -+ val &= ~(RH_A_POTPGT | RH_A_NPS); -+ ohci_writel (ohci, val, &ohci->regs->roothub.a); -+ } else if ((ohci->flags & OHCI_QUIRK_AMD756) || -+ (ohci->flags & OHCI_QUIRK_HUB_POWER)) { -+ /* hub power always on; required for AMD-756 and some -+ * Mac platforms. ganged overcurrent reporting, if any. -+ */ -+ val |= RH_A_NPS; -+ ohci_writel (ohci, val, &ohci->regs->roothub.a); + } -+ ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status); -+ ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM, -+ &ohci->regs->roothub.b); -+ // flush those writes -+ (void) ohci_readl (ohci, &ohci->regs->control); + -+ ohci->next_statechange = jiffies + STATECHANGE_DELAY; -+ spin_unlock_irq (&ohci->lock); -+ -+ // POTPGT delay is bits 24-31, in 2 ms units. -+ mdelay ((val >> 23) & 0x1fe); -+ hcd->state = HC_STATE_RUNNING; -+ -+ if (quirk_zfmicro(ohci)) { -+ /* Create timer to watch for bad queue state on ZF Micro */ -+ setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func, -+ (unsigned long) ohci); -+ -+ ohci->eds_scheduled = 0; -+ ohci->ed_to_check = NULL; ++ if (likely(status & AG71XX_INT_POLL)) { ++ ag71xx_int_disable(ag, AG71XX_INT_POLL); ++ DBG("%s: enable polling mode\n", dev->name); ++ napi_schedule(&ag->napi); + } + -+ ohci_dump (ohci, 1); ++ ag71xx_debugfs_update_int_stats(ag, status); + -+ return 0; ++ return IRQ_HANDLED; +} + -+/*-------------------------------------------------------------------------*/ -+ -+/* an interrupt happens */ ++static void ag71xx_set_multicast_list(struct net_device *dev) ++{ ++ /* TODO */ ++} + -+static irqreturn_t ohci_irq (struct usb_hcd *hcd) ++#ifdef CONFIG_NET_POLL_CONTROLLER ++/* ++ * Polling 'interrupt' - used by things like netconsole to send skbs ++ * without having to re-enable interrupts. It's not called while ++ * the interrupt routine is executing. ++ */ ++static void ag71xx_netpoll(struct net_device *dev) +{ -+ struct ohci_hcd *ohci = hcd_to_ohci (hcd); -+ struct ohci_regs __iomem *regs = ohci->regs; -+ int ints; ++ disable_irq(dev->irq); ++ ag71xx_interrupt(dev->irq, dev); ++ enable_irq(dev->irq); ++} ++#endif + -+ /* Read interrupt status (and flush pending writes). We ignore the -+ * optimization of checking the LSB of hcca->done_head; it doesn't -+ * work on all systems (edge triggering for OHCI can be a factor). -+ */ -+ ints = ohci_readl(ohci, ®s->intrstatus); ++static const struct net_device_ops ag71xx_netdev_ops = { ++ .ndo_open = ag71xx_open, ++ .ndo_stop = ag71xx_stop, ++ .ndo_start_xmit = ag71xx_hard_start_xmit, ++ .ndo_set_multicast_list = ag71xx_set_multicast_list, ++ .ndo_do_ioctl = ag71xx_do_ioctl, ++ .ndo_tx_timeout = ag71xx_tx_timeout, ++ .ndo_change_mtu = eth_change_mtu, ++ .ndo_set_mac_address = eth_mac_addr, ++ .ndo_validate_addr = eth_validate_addr, ++#ifdef CONFIG_NET_POLL_CONTROLLER ++ .ndo_poll_controller = ag71xx_netpoll, ++#endif ++}; + -+ /* Check for an all 1's result which is a typical consequence -+ * of dead, unclocked, or unplugged (CardBus...) devices -+ */ -+ if (ints == ~(u32)0) { -+ disable (ohci); -+ ohci_dbg (ohci, "device removed!\n"); -+ return IRQ_HANDLED; -+ } ++static int __init ag71xx_probe(struct platform_device *pdev) ++{ ++ struct net_device *dev; ++ struct resource *res; ++ struct ag71xx *ag; ++ struct ag71xx_platform_data *pdata; ++ int err; + -+ /* We only care about interrupts that are enabled */ -+ ints &= ohci_readl(ohci, ®s->intrenable); ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "no platform data specified\n"); ++ err = -ENXIO; ++ goto err_out; ++ } + -+ /* interrupt for some other device? */ -+ if (ints == 0) -+ return IRQ_NOTMINE; ++ if (pdata->mii_bus_dev == NULL) { ++ dev_err(&pdev->dev, "no MII bus device specified\n"); ++ err = -EINVAL; ++ goto err_out; ++ } + -+ if (ints & OHCI_INTR_UE) { -+ // e.g. due to PCI Master/Target Abort -+ if (quirk_nec(ohci)) { -+ /* Workaround for a silicon bug in some NEC chips used -+ * in Apple's PowerBooks. Adapted from Darwin code. -+ */ -+ ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n"); ++ dev = alloc_etherdev(sizeof(*ag)); ++ if (!dev) { ++ dev_err(&pdev->dev, "alloc_etherdev failed\n"); ++ err = -ENOMEM; ++ goto err_out; ++ } + -+ ohci_writel (ohci, OHCI_INTR_UE, ®s->intrdisable); ++ SET_NETDEV_DEV(dev, &pdev->dev); + -+ schedule_work (&ohci->nec_work); -+ } else { -+ disable (ohci); -+ ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n"); -+ } ++ ag = netdev_priv(dev); ++ ag->pdev = pdev; ++ ag->dev = dev; ++ ag->msg_enable = netif_msg_init(ag71xx_msg_level, ++ AG71XX_DEFAULT_MSG_ENABLE); ++ spin_lock_init(&ag->lock); + -+ ohci_dump (ohci, 1); -+ ohci_usb_reset (ohci); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base"); ++ if (!res) { ++ dev_err(&pdev->dev, "no mac_base resource found\n"); ++ err = -ENXIO; ++ goto err_out; + } + -+ if (ints & OHCI_INTR_RHSC) { -+ ohci_vdbg(ohci, "rhsc\n"); -+ ohci->next_statechange = jiffies + STATECHANGE_DELAY; -+ ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC, -+ ®s->intrstatus); -+ -+ /* NOTE: Vendors didn't always make the same implementation -+ * choices for RHSC. Many followed the spec; RHSC triggers -+ * on an edge, like setting and maybe clearing a port status -+ * change bit. With others it's level-triggered, active -+ * until khubd clears all the port status change bits. We'll -+ * always disable it here and rely on polling until khubd -+ * re-enables it. -+ */ -+ ohci_writel(ohci, OHCI_INTR_RHSC, ®s->intrdisable); -+ usb_hcd_poll_rh_status(hcd); ++ ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1); ++ if (!ag->mac_base) { ++ dev_err(&pdev->dev, "unable to ioremap mac_base\n"); ++ err = -ENOMEM; ++ goto err_free_dev; + } + -+ /* For connect and disconnect events, we expect the controller -+ * to turn on RHSC along with RD. But for remote wakeup events -+ * this might not happen. -+ */ -+ else if (ints & OHCI_INTR_RD) { -+ ohci_vdbg(ohci, "resume detect\n"); -+ ohci_writel(ohci, OHCI_INTR_RD, ®s->intrstatus); -+ hcd->poll_rh = 1; -+ if (ohci->autostop) { -+ spin_lock (&ohci->lock); -+ ohci_rh_resume (ohci); -+ spin_unlock (&ohci->lock); -+ } else -+ usb_hcd_resume_root_hub(hcd); -+ } -+ -+ if (ints & OHCI_INTR_WDH) { -+ spin_lock (&ohci->lock); -+ dl_done_list (ohci); -+ spin_unlock (&ohci->lock); -+ } -+ -+ if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) { -+ spin_lock(&ohci->lock); -+ if (ohci->ed_to_check) { -+ struct ed *ed = ohci->ed_to_check; -+ -+ if (check_ed(ohci, ed)) { -+ /* HC thinks the TD list is empty; HCD knows -+ * at least one TD is outstanding -+ */ -+ if (--ohci->zf_delay == 0) { -+ struct td *td = list_entry( -+ ed->td_list.next, -+ struct td, td_list); -+ ohci_warn(ohci, -+ "Reclaiming orphan TD %p\n", -+ td); -+ takeback_td(ohci, td); -+ ohci->ed_to_check = NULL; -+ } -+ } else -+ ohci->ed_to_check = NULL; -+ } -+ spin_unlock(&ohci->lock); ++ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl"); ++ if (!res) { ++ dev_err(&pdev->dev, "no mii_ctrl resource found\n"); ++ err = -ENXIO; ++ goto err_unmap_base; + } + -+ /* could track INTR_SO to reduce available PCI/... bandwidth */ -+ -+ /* handle any pending URB/ED unlinks, leaving INTR_SF enabled -+ * when there's still unlinking to be done (next frame). -+ */ -+ spin_lock (&ohci->lock); -+ if (ohci->ed_rm_list) -+ finish_unlinks (ohci, ohci_frame_no(ohci)); -+ if ((ints & OHCI_INTR_SF) != 0 -+ && !ohci->ed_rm_list -+ && !ohci->ed_to_check -+ && HC_IS_RUNNING(hcd->state)) -+ ohci_writel (ohci, OHCI_INTR_SF, ®s->intrdisable); -+ spin_unlock (&ohci->lock); -+ -+ if (HC_IS_RUNNING(hcd->state)) { -+ ohci_writel (ohci, ints, ®s->intrstatus); -+ ohci_writel (ohci, OHCI_INTR_MIE, ®s->intrenable); -+ // flush those writes -+ (void) ohci_readl (ohci, &ohci->regs->control); ++ ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1); ++ if (!ag->mii_ctrl) { ++ dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n"); ++ err = -ENOMEM; ++ goto err_unmap_base; + } + -+ return IRQ_HANDLED; -+} -+ -+/*-------------------------------------------------------------------------*/ ++ dev->irq = platform_get_irq(pdev, 0); ++ err = request_irq(dev->irq, ag71xx_interrupt, ++ IRQF_DISABLED | IRQF_SAMPLE_RANDOM, ++ dev->name, dev); ++ if (err) { ++ dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq); ++ goto err_unmap_mii_ctrl; ++ } + -+static void ohci_stop (struct usb_hcd *hcd) -+{ -+ struct ohci_hcd *ohci = hcd_to_ohci (hcd); ++ dev->base_addr = (unsigned long)ag->mac_base; ++ dev->netdev_ops = &ag71xx_netdev_ops; ++ dev->ethtool_ops = &ag71xx_ethtool_ops; + -+ ohci_dump (ohci, 1); ++ INIT_WORK(&ag->restart_work, ag71xx_restart_work_func); + -+ flush_scheduled_work(); ++ init_timer(&ag->oom_timer); ++ ag->oom_timer.data = (unsigned long) dev; ++ ag->oom_timer.function = ag71xx_oom_timer_handler; + -+ ohci_usb_reset (ohci); -+ ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable); -+ free_irq(hcd->irq, hcd); -+ hcd->irq = -1; ++ memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN); + -+ if (quirk_zfmicro(ohci)) -+ del_timer(&ohci->unlink_watchdog); -+ if (quirk_amdiso(ohci)) -+ amd_iso_dev_put(); ++ netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT); + -+ remove_debug_files (ohci); -+ ohci_mem_cleanup (ohci); -+ if (ohci->hcca) { -+ dma_free_coherent (hcd->self.controller, -+ sizeof *ohci->hcca, -+ ohci->hcca, ohci->hcca_dma); -+ ohci->hcca = NULL; -+ ohci->hcca_dma = 0; ++ err = register_netdev(dev); ++ if (err) { ++ dev_err(&pdev->dev, "unable to register net device\n"); ++ goto err_free_irq; + } -+} -+ -+/*-------------------------------------------------------------------------*/ + -+#if defined(CONFIG_PM) || defined(CONFIG_PCI) ++ printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n", ++ dev->name, dev->base_addr, dev->irq); + -+/* must not be called from interrupt context */ -+static int ohci_restart (struct ohci_hcd *ohci) -+{ -+ int temp; -+ int i; -+ struct urb_priv *priv; -+ -+ spin_lock_irq(&ohci->lock); -+ disable (ohci); -+ -+ /* Recycle any "live" eds/tds (and urbs). */ -+ if (!list_empty (&ohci->pending)) -+ ohci_dbg(ohci, "abort schedule...\n"); -+ list_for_each_entry (priv, &ohci->pending, pending) { -+ struct urb *urb = priv->td[0]->urb; -+ struct ed *ed = priv->ed; -+ -+ switch (ed->state) { -+ case ED_OPER: -+ ed->state = ED_UNLINK; -+ ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE); -+ ed_deschedule (ohci, ed); -+ -+ ed->ed_next = ohci->ed_rm_list; -+ ed->ed_prev = NULL; -+ ohci->ed_rm_list = ed; -+ /* FALLTHROUGH */ -+ case ED_UNLINK: -+ break; -+ default: -+ ohci_dbg(ohci, "bogus ed %p state %d\n", -+ ed, ed->state); -+ } ++ ag71xx_dump_regs(ag); + -+ if (!urb->unlinked) -+ urb->unlinked = -ESHUTDOWN; -+ } -+ finish_unlinks (ohci, 0); -+ spin_unlock_irq(&ohci->lock); ++ ag71xx_hw_init(ag); + -+ /* paranoia, in case that didn't work: */ ++ ag71xx_dump_regs(ag); + -+ /* empty the interrupt branches */ -+ for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0; -+ for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0; ++ err = ag71xx_phy_connect(ag); ++ if (err) ++ goto err_unregister_netdev; + -+ /* no EDs to remove */ -+ ohci->ed_rm_list = NULL; ++ err = ag71xx_debugfs_init(ag); ++ if (err) ++ goto err_phy_disconnect; + -+ /* empty control and bulk lists */ -+ ohci->ed_controltail = NULL; -+ ohci->ed_bulktail = NULL; ++ platform_set_drvdata(pdev, dev); + -+ if ((temp = ohci_run (ohci)) < 0) { -+ ohci_err (ohci, "can't restart, %d\n", temp); -+ return temp; -+ } -+ ohci_dbg(ohci, "restart complete\n"); + return 0; -+} -+ -+#endif -+ -+/*-------------------------------------------------------------------------*/ -+ -+MODULE_AUTHOR (DRIVER_AUTHOR); -+MODULE_DESCRIPTION(DRIVER_DESC); -+MODULE_LICENSE ("GPL"); -+ -+#ifdef CONFIG_PCI -+#include "ohci-pci.c" -+#define PCI_DRIVER ohci_pci_driver -+#endif + -+#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111) -+#include "ohci-sa1111.c" -+#define SA1111_DRIVER ohci_hcd_sa1111_driver -+#endif ++ err_phy_disconnect: ++ ag71xx_phy_disconnect(ag); ++ err_unregister_netdev: ++ unregister_netdev(dev); ++ err_free_irq: ++ free_irq(dev->irq, dev); ++ err_unmap_mii_ctrl: ++ iounmap(ag->mii_ctrl); ++ err_unmap_base: ++ iounmap(ag->mac_base); ++ err_free_dev: ++ kfree(dev); ++ err_out: ++ platform_set_drvdata(pdev, NULL); ++ return err; ++} + -+#if defined(CONFIG_ARCH_S3C2410) || defined(CONFIG_ARCH_S3C64XX) -+#include "ohci-s3c2410.c" -+#define PLATFORM_DRIVER ohci_hcd_s3c2410_driver -+#endif ++static int __exit ag71xx_remove(struct platform_device *pdev) ++{ ++ struct net_device *dev = platform_get_drvdata(pdev); + -+#ifdef CONFIG_USB_OHCI_HCD_OMAP1 -+#include "ohci-omap.c" -+#define OMAP1_PLATFORM_DRIVER ohci_hcd_omap_driver -+#endif ++ if (dev) { ++ struct ag71xx *ag = netdev_priv(dev); + -+#ifdef CONFIG_USB_OHCI_HCD_OMAP3 -+#include "ohci-omap3.c" -+#define OMAP3_PLATFORM_DRIVER ohci_hcd_omap3_driver -+#endif ++ ag71xx_debugfs_exit(ag); ++ ag71xx_phy_disconnect(ag); ++ unregister_netdev(dev); ++ free_irq(dev->irq, dev); ++ iounmap(ag->mii_ctrl); ++ iounmap(ag->mac_base); ++ kfree(dev); ++ platform_set_drvdata(pdev, NULL); ++ } + -+#ifdef CONFIG_ARCH_LH7A404 -+#include "ohci-lh7a404.c" -+#define PLATFORM_DRIVER ohci_hcd_lh7a404_driver -+#endif ++ return 0; ++} + -+#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) -+#include "ohci-pxa27x.c" -+#define PLATFORM_DRIVER ohci_hcd_pxa27x_driver -+#endif ++static struct platform_driver ag71xx_driver = { ++ .probe = ag71xx_probe, ++ .remove = __exit_p(ag71xx_remove), ++ .driver = { ++ .name = AG71XX_DRV_NAME, ++ } ++}; + -+#ifdef CONFIG_ARCH_EP93XX -+#include "ohci-ep93xx.c" -+#define PLATFORM_DRIVER ohci_hcd_ep93xx_driver -+#endif ++static int __init ag71xx_module_init(void) ++{ ++ int ret; + -+#ifdef CONFIG_SOC_AU1X00 -+#include "ohci-au1xxx.c" -+#define PLATFORM_DRIVER ohci_hcd_au1xxx_driver -+#endif ++ ret = ag71xx_debugfs_root_init(); ++ if (ret) ++ goto err_out; + -+#ifdef CONFIG_PNX8550 -+#include "ohci-pnx8550.c" -+#define PLATFORM_DRIVER ohci_hcd_pnx8550_driver -+#endif ++ ret = ag71xx_mdio_driver_init(); ++ if (ret) ++ goto err_debugfs_exit; + -+#ifdef CONFIG_USB_OHCI_HCD_PPC_SOC -+#include "ohci-ppc-soc.c" -+#define PLATFORM_DRIVER ohci_hcd_ppc_soc_driver -+#endif ++ ret = platform_driver_register(&ag71xx_driver); ++ if (ret) ++ goto err_mdio_exit; + -+#ifdef CONFIG_ARCH_AT91 -+#include "ohci-at91.c" -+#define PLATFORM_DRIVER ohci_hcd_at91_driver -+#endif ++ return 0; + -+#ifdef CONFIG_ARCH_PNX4008 -+#include "ohci-pnx4008.c" -+#define PLATFORM_DRIVER usb_hcd_pnx4008_driver -+#endif ++ err_mdio_exit: ++ ag71xx_mdio_driver_exit(); ++ err_debugfs_exit: ++ ag71xx_debugfs_root_exit(); ++ err_out: ++ return ret; ++} + -+#ifdef CONFIG_ARCH_DAVINCI_DA8XX -+#include "ohci-da8xx.c" -+#define PLATFORM_DRIVER ohci_hcd_da8xx_driver -+#endif ++static void __exit ag71xx_module_exit(void) ++{ ++ platform_driver_unregister(&ag71xx_driver); ++ ag71xx_mdio_driver_exit(); ++ ag71xx_debugfs_root_exit(); ++} + -+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ -+ defined(CONFIG_CPU_SUBTYPE_SH7721) || \ -+ defined(CONFIG_CPU_SUBTYPE_SH7763) || \ -+ defined(CONFIG_CPU_SUBTYPE_SH7786) -+#include "ohci-sh.c" -+#define PLATFORM_DRIVER ohci_hcd_sh_driver -+#endif ++module_init(ag71xx_module_init); ++module_exit(ag71xx_module_exit); + ++MODULE_VERSION(AG71XX_DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_AUTHOR("Imre Kaloz "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" AG71XX_DRV_NAME); +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_mdio.c linux-2.6.36/drivers/net/ag71xx/ag71xx_mdio.c +--- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_mdio.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/ag71xx_mdio.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,243 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+#ifdef CONFIG_USB_OHCI_HCD_PPC_OF -+#include "ohci-ppc-of.c" -+#define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver -+#endif ++#include "ag71xx.h" + -+#ifdef CONFIG_PPC_PS3 -+#include "ohci-ps3.c" -+#define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver -+#endif ++#define AG71XX_MDIO_RETRY 1000 ++#define AG71XX_MDIO_DELAY 5 + -+#ifdef CONFIG_USB_OHCI_HCD_SSB -+#include "ohci-ssb.c" -+#define SSB_OHCI_DRIVER ssb_ohci_driver -+#endif ++static inline void ag71xx_mdio_wr(struct ag71xx_mdio *am, unsigned reg, ++ u32 value) ++{ ++ void __iomem *r; + -+#ifdef CONFIG_MFD_SM501 -+#include "ohci-sm501.c" -+#define SM501_OHCI_DRIVER ohci_hcd_sm501_driver -+#endif ++ r = am->mdio_base + reg; ++ __raw_writel(value, r); + -+#ifdef CONFIG_MFD_TC6393XB -+#include "ohci-tmio.c" -+#define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver -+#endif ++ /* flush write */ ++ (void) __raw_readl(r); ++} + -+#if !defined(PCI_DRIVER) && \ -+ !defined(PLATFORM_DRIVER) && \ -+ !defined(OMAP1_PLATFORM_DRIVER) && \ -+ !defined(OMAP3_PLATFORM_DRIVER) && \ -+ !defined(OF_PLATFORM_DRIVER) && \ -+ !defined(SA1111_DRIVER) && \ -+ !defined(PS3_SYSTEM_BUS_DRIVER) && \ -+ !defined(SM501_OHCI_DRIVER) && \ -+ !defined(TMIO_OHCI_DRIVER) && \ -+ !defined(SSB_OHCI_DRIVER) -+#error "missing bus glue for ohci-hcd" -+#endif ++static inline u32 ag71xx_mdio_rr(struct ag71xx_mdio *am, unsigned reg) ++{ ++ return __raw_readl(am->mdio_base + reg); ++} + -+static int __init ohci_hcd_mod_init(void) ++static void ag71xx_mdio_dump_regs(struct ag71xx_mdio *am) +{ -+ int retval = 0; ++ DBG("%s: mii_cfg=%08x, mii_cmd=%08x, mii_addr=%08x\n", ++ am->mii_bus->name, ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_CFG), ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_CMD), ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_ADDR)); ++ DBG("%s: mii_ctrl=%08x, mii_status=%08x, mii_ind=%08x\n", ++ am->mii_bus->name, ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_CTRL), ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS), ++ ag71xx_mdio_rr(am, AG71XX_REG_MII_IND)); ++} + -+ if (usb_disabled()) -+ return -ENODEV; ++static int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg) ++{ ++ int ret; ++ int i; + -+ printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name); -+ pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name, -+ sizeof (struct ed), sizeof (struct td)); -+ set_bit(USB_OHCI_LOADED, &usb_hcds_loaded); ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, ++ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_READ); + -+#ifdef DEBUG -+ ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root); -+ if (!ohci_debug_root) { -+ retval = -ENOENT; -+ goto error_debug; ++ i = AG71XX_MDIO_RETRY; ++ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { ++ if (i-- == 0) { ++ printk(KERN_ERR "%s: mii_read timed out\n", ++ am->mii_bus->name); ++ ret = 0xffff; ++ goto out; ++ } ++ udelay(AG71XX_MDIO_DELAY); + } -+#endif + -+#ifdef PS3_SYSTEM_BUS_DRIVER -+ retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER); -+ if (retval < 0) -+ goto error_ps3; -+#endif ++ ret = ag71xx_mdio_rr(am, AG71XX_REG_MII_STATUS) & 0xffff; ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CMD, MII_CMD_WRITE); + -+#ifdef PLATFORM_DRIVER -+ retval = platform_driver_register(&PLATFORM_DRIVER); -+ if (retval < 0) -+ goto error_platform; -+#endif ++ DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret); + -+#ifdef OMAP1_PLATFORM_DRIVER -+ retval = platform_driver_register(&OMAP1_PLATFORM_DRIVER); -+ if (retval < 0) -+ goto error_omap1_platform; -+#endif ++ out: ++ return ret; ++} + -+#ifdef OMAP3_PLATFORM_DRIVER -+ retval = platform_driver_register(&OMAP3_PLATFORM_DRIVER); -+ if (retval < 0) -+ goto error_omap3_platform; -+#endif ++static void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, ++ int addr, int reg, u16 val) ++{ ++ int i; + -+#ifdef OF_PLATFORM_DRIVER -+ retval = of_register_platform_driver(&OF_PLATFORM_DRIVER); -+ if (retval < 0) -+ goto error_of_platform; -+#endif ++ DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val); + -+#ifdef SA1111_DRIVER -+ retval = sa1111_driver_register(&SA1111_DRIVER); -+ if (retval < 0) -+ goto error_sa1111; -+#endif ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_ADDR, ++ ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff)); ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CTRL, val); + -+#ifdef PCI_DRIVER -+ retval = pci_register_driver(&PCI_DRIVER); -+ if (retval < 0) -+ goto error_pci; -+#endif ++ i = AG71XX_MDIO_RETRY; ++ while (ag71xx_mdio_rr(am, AG71XX_REG_MII_IND) & MII_IND_BUSY) { ++ if (i-- == 0) { ++ printk(KERN_ERR "%s: mii_write timed out\n", ++ am->mii_bus->name); ++ break; ++ } ++ udelay(AG71XX_MDIO_DELAY); ++ } ++} + -+#ifdef SSB_OHCI_DRIVER -+ retval = ssb_driver_register(&SSB_OHCI_DRIVER); -+ if (retval) -+ goto error_ssb; -+#endif ++static int ag71xx_mdio_reset(struct mii_bus *bus) ++{ ++ struct ag71xx_mdio *am = bus->priv; ++ u32 t; + -+#ifdef SM501_OHCI_DRIVER -+ retval = platform_driver_register(&SM501_OHCI_DRIVER); -+ if (retval < 0) -+ goto error_sm501; -+#endif ++ if (am->pdata->is_ar7240) ++ t = MII_CFG_CLK_DIV_6; ++ else ++ t = MII_CFG_CLK_DIV_28; + -+#ifdef TMIO_OHCI_DRIVER -+ retval = platform_driver_register(&TMIO_OHCI_DRIVER); -+ if (retval < 0) -+ goto error_tmio; -+#endif ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t | MII_CFG_RESET); ++ udelay(100); + -+ return retval; ++ ag71xx_mdio_wr(am, AG71XX_REG_MII_CFG, t); ++ udelay(100); + -+ /* Error path */ -+#ifdef TMIO_OHCI_DRIVER -+ platform_driver_unregister(&TMIO_OHCI_DRIVER); -+ error_tmio: -+#endif -+#ifdef SM501_OHCI_DRIVER -+ platform_driver_unregister(&SM501_OHCI_DRIVER); -+ error_sm501: -+#endif -+#ifdef SSB_OHCI_DRIVER -+ ssb_driver_unregister(&SSB_OHCI_DRIVER); -+ error_ssb: -+#endif -+#ifdef PCI_DRIVER -+ pci_unregister_driver(&PCI_DRIVER); -+ error_pci: -+#endif -+#ifdef SA1111_DRIVER -+ sa1111_driver_unregister(&SA1111_DRIVER); -+ error_sa1111: -+#endif -+#ifdef OF_PLATFORM_DRIVER -+ of_unregister_platform_driver(&OF_PLATFORM_DRIVER); -+ error_of_platform: -+#endif -+#ifdef PLATFORM_DRIVER -+ platform_driver_unregister(&PLATFORM_DRIVER); -+ error_platform: -+#endif -+#ifdef OMAP1_PLATFORM_DRIVER -+ platform_driver_unregister(&OMAP1_PLATFORM_DRIVER); -+ error_omap1_platform: -+#endif -+#ifdef OMAP3_PLATFORM_DRIVER -+ platform_driver_unregister(&OMAP3_PLATFORM_DRIVER); -+ error_omap3_platform: -+#endif -+#ifdef PS3_SYSTEM_BUS_DRIVER -+ ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); -+ error_ps3: -+#endif -+#ifdef DEBUG -+ debugfs_remove(ohci_debug_root); -+ ohci_debug_root = NULL; -+ error_debug: -+#endif ++ return 0; ++} ++ ++static int ag71xx_mdio_read(struct mii_bus *bus, int addr, int reg) ++{ ++ struct ag71xx_mdio *am = bus->priv; + -+ clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); -+ return retval; ++ return ag71xx_mdio_mii_read(am, addr, reg); +} -+module_init(ohci_hcd_mod_init); + -+static void __exit ohci_hcd_mod_exit(void) ++static int ag71xx_mdio_write(struct mii_bus *bus, int addr, int reg, u16 val) +{ -+#ifdef TMIO_OHCI_DRIVER -+ platform_driver_unregister(&TMIO_OHCI_DRIVER); -+#endif -+#ifdef SM501_OHCI_DRIVER -+ platform_driver_unregister(&SM501_OHCI_DRIVER); -+#endif -+#ifdef SSB_OHCI_DRIVER -+ ssb_driver_unregister(&SSB_OHCI_DRIVER); -+#endif -+#ifdef PCI_DRIVER -+ pci_unregister_driver(&PCI_DRIVER); -+#endif -+#ifdef SA1111_DRIVER -+ sa1111_driver_unregister(&SA1111_DRIVER); -+#endif -+#ifdef OF_PLATFORM_DRIVER -+ of_unregister_platform_driver(&OF_PLATFORM_DRIVER); -+#endif -+#ifdef PLATFORM_DRIVER -+ platform_driver_unregister(&PLATFORM_DRIVER); -+#endif -+#ifdef PS3_SYSTEM_BUS_DRIVER -+ ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER); -+#endif -+#ifdef DEBUG -+ debugfs_remove(ohci_debug_root); -+#endif -+ clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded); ++ struct ag71xx_mdio *am = bus->priv; ++ ++ ag71xx_mdio_mii_write(am, addr, reg, val); ++ return 0; +} -+module_exit(ohci_hcd_mod_exit); + -diff -Nur linux-2.6.35.7.orig/drivers/watchdog/ar71xx_wdt.c linux-2.6.35.7/drivers/watchdog/ar71xx_wdt.c ---- linux-2.6.35.7.orig/drivers/watchdog/ar71xx_wdt.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/watchdog/ar71xx_wdt.c 2010-10-14 20:28:01.508101380 +0200 -@@ -0,0 +1,270 @@ -+/* -+ * Driver for the Atheros AR71xx SoC's built-in hardware watchdog timer. -+ * -+ * Copyright (C) 2008 Gabor Juhos -+ * Copyright (C) 2008 Imre Kaloz -+ * -+ * This driver was based on: drivers/watchdog/ixp4xx_wdt.c -+ * Author: Deepak Saxena -+ * Copyright 2004 (c) MontaVista, Software, Inc. -+ * -+ * which again was based on sa1100 driver, -+ * Copyright (C) 2000 Oleg Drokin -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ ++static int __init ag71xx_mdio_probe(struct platform_device *pdev) ++{ ++ struct ag71xx_mdio_platform_data *pdata; ++ struct ag71xx_mdio *am; ++ struct resource *res; ++ int i; ++ int err; + -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "no platform data specified\n"); ++ return -EINVAL; ++ } ++ ++ am = kzalloc(sizeof(*am), GFP_KERNEL); ++ if (!am) { ++ err = -ENOMEM; ++ goto err_out; ++ } ++ ++ am->pdata = pdata; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_err(&pdev->dev, "no iomem resource found\n"); ++ err = -ENXIO; ++ goto err_out; ++ } + -+#include ++ am->mdio_base = ioremap_nocache(res->start, res->end - res->start + 1); ++ if (!am->mdio_base) { ++ dev_err(&pdev->dev, "unable to ioremap registers\n"); ++ err = -ENOMEM; ++ goto err_free_mdio; ++ } + -+#define DRV_NAME "ar71xx-wdt" -+#define DRV_DESC "Atheros AR71xx hardware watchdog driver" -+#define DRV_VERSION "0.1.0" ++ am->mii_bus = mdiobus_alloc(); ++ if (am->mii_bus == NULL) { ++ err = -ENOMEM; ++ goto err_iounmap; ++ } + -+#define WDT_TIMEOUT 15 /* seconds */ ++ am->mii_bus->name = "ag71xx_mdio"; ++ am->mii_bus->read = ag71xx_mdio_read; ++ am->mii_bus->write = ag71xx_mdio_write; ++ am->mii_bus->reset = ag71xx_mdio_reset; ++ am->mii_bus->irq = am->mii_irq; ++ am->mii_bus->priv = am; ++ am->mii_bus->parent = &pdev->dev; ++ snprintf(am->mii_bus->id, MII_BUS_ID_SIZE, "%s", dev_name(&pdev->dev)); ++ am->mii_bus->phy_mask = pdata->phy_mask; + -+static int nowayout = WATCHDOG_NOWAYOUT; ++ for (i = 0; i < PHY_MAX_ADDR; i++) ++ am->mii_irq[i] = PHY_POLL; + -+#ifdef CONFIG_WATCHDOG_NOWAYOUT -+module_param(nowayout, int, 0); -+MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " -+ "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); -+#endif ++ ag71xx_mdio_wr(am, AG71XX_REG_MAC_CFG1, 0); + -+static unsigned long wdt_flags; ++ err = mdiobus_register(am->mii_bus); ++ if (err) ++ goto err_free_bus; + -+#define WDT_FLAGS_BUSY 0 -+#define WDT_FLAGS_EXPECT_CLOSE 1 ++ ag71xx_mdio_dump_regs(am); + -+static int wdt_timeout = WDT_TIMEOUT; -+static int boot_status; -+static int max_timeout; ++ platform_set_drvdata(pdev, am); ++ return 0; + -+static void inline ar71xx_wdt_keepalive(void) -+{ -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, ar71xx_ahb_freq * wdt_timeout); ++ err_free_bus: ++ mdiobus_free(am->mii_bus); ++ err_iounmap: ++ iounmap(am->mdio_base); ++ err_free_mdio: ++ kfree(am); ++ err_out: ++ return err; +} + -+static void inline ar71xx_wdt_enable(void) ++static int __exit ag71xx_mdio_remove(struct platform_device *pdev) +{ -+ printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n"); -+ ar71xx_wdt_keepalive(); -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); ++ struct ag71xx_mdio *am = platform_get_drvdata(pdev); ++ ++ if (am) { ++ mdiobus_unregister(am->mii_bus); ++ mdiobus_free(am->mii_bus); ++ iounmap(am->mdio_base); ++ kfree(am); ++ platform_set_drvdata(pdev, NULL); ++ } ++ ++ return 0; +} + -+static void inline ar71xx_wdt_disable(void) ++static struct platform_driver ag71xx_mdio_driver = { ++ .probe = ag71xx_mdio_probe, ++ .remove = __exit_p(ag71xx_mdio_remove), ++ .driver = { ++ .name = "ag71xx-mdio", ++ } ++}; ++ ++int ag71xx_mdio_driver_init(void) +{ -+ printk(KERN_DEBUG DRV_NAME ": disabling watchdog timer\n"); -+ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); ++ return platform_driver_register(&ag71xx_mdio_driver); +} + -+static int ar71xx_wdt_set_timeout(int val) ++void ag71xx_mdio_driver_exit(void) +{ -+ if (val < 1 || val > max_timeout) -+ return -EINVAL; ++ platform_driver_unregister(&ag71xx_mdio_driver); ++} +diff -Nur linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_phy.c linux-2.6.36/drivers/net/ag71xx/ag71xx_phy.c +--- linux-2.6.36.orig/drivers/net/ag71xx/ag71xx_phy.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/net/ag71xx/ag71xx_phy.c 2010-11-18 21:16:14.000000000 +0100 +@@ -0,0 +1,213 @@ ++/* ++ * Atheros AR71xx built-in ethernet mac driver ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Based on Atheros' AG7100 driver ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+ wdt_timeout = val; -+ ar71xx_wdt_keepalive(); ++#include "ag71xx.h" + -+ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs\n", wdt_timeout); ++static void ag71xx_phy_link_adjust(struct net_device *dev) ++{ ++ struct ag71xx *ag = netdev_priv(dev); ++ struct phy_device *phydev = ag->phy_dev; ++ unsigned long flags; ++ int status_change = 0; + -+ return 0; -+} ++ spin_lock_irqsave(&ag->lock, flags); + -+static int ar71xx_wdt_open(struct inode *inode, struct file *file) -+{ -+ if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags)) -+ return -EBUSY; ++ if (phydev->link) { ++ if (ag->duplex != phydev->duplex ++ || ag->speed != phydev->speed) { ++ status_change = 1; ++ } ++ } + -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); ++ if (phydev->link != ag->link) ++ status_change = 1; + -+ ar71xx_wdt_enable(); ++ ag->link = phydev->link; ++ ag->duplex = phydev->duplex; ++ ag->speed = phydev->speed; + -+ return nonseekable_open(inode, file); ++ if (status_change) ++ ag71xx_link_adjust(ag); ++ ++ spin_unlock_irqrestore(&ag->lock, flags); +} + -+static int ar71xx_wdt_release(struct inode *inode, struct file *file) ++void ag71xx_phy_start(struct ag71xx *ag) +{ -+ if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags)) { -+ ar71xx_wdt_disable(); ++ if (ag->phy_dev) { ++ phy_start(ag->phy_dev); + } else { -+ printk(KERN_CRIT DRV_NAME ": device closed unexpectedly, " -+ "watchdog timer will not stop!\n"); ++ ag->link = 1; ++ ag71xx_link_adjust(ag); + } -+ -+ clear_bit(WDT_FLAGS_BUSY, &wdt_flags); -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ return 0; +} + -+static ssize_t ar71xx_wdt_write(struct file *file, const char *data, -+ size_t len, loff_t *ppos) ++void ag71xx_phy_stop(struct ag71xx *ag) +{ -+ if (len) { -+ if (!nowayout) { -+ size_t i; -+ -+ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); -+ -+ for (i = 0; i != len; i++) { -+ char c; -+ -+ if (get_user(c, data + i)) -+ return -EFAULT; -+ -+ if (c == 'V') -+ set_bit(WDT_FLAGS_EXPECT_CLOSE, -+ &wdt_flags); -+ } -+ } -+ -+ ar71xx_wdt_keepalive(); ++ if (ag->phy_dev) { ++ phy_stop(ag->phy_dev); ++ } else { ++ ag->link = 0; ++ ag71xx_link_adjust(ag); + } -+ -+ return len; +} + -+static struct watchdog_info ar71xx_wdt_info = { -+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | -+ WDIOF_MAGICCLOSE | WDIOF_CARDRESET, -+ .firmware_version = 0, -+ .identity = "AR71XX watchdog", -+}; -+ -+static int ar71xx_wdt_ioctl(struct inode *inode, struct file *file, -+ unsigned int cmd, unsigned long arg) ++static int ag71xx_phy_connect_fixed(struct ag71xx *ag) +{ -+ int t; -+ int ret; -+ -+ switch (cmd) { -+ case WDIOC_GETSUPPORT: -+ ret = copy_to_user((struct watchdog_info *)arg, -+ &ar71xx_wdt_info, -+ sizeof(&ar71xx_wdt_info)) ? -EFAULT : 0; -+ break; ++ struct net_device *dev = ag->dev; ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ int ret = 0; + -+ case WDIOC_GETSTATUS: -+ ret = put_user(0, (int *)arg) ? -EFAULT : 0; ++ /* use fixed settings */ ++ switch (pdata->speed) { ++ case SPEED_10: ++ case SPEED_100: ++ case SPEED_1000: + break; -+ -+ case WDIOC_GETBOOTSTATUS: -+ ret = put_user(boot_status, (int *)arg) ? -EFAULT : 0; ++ default: ++ printk(KERN_ERR "%s: invalid speed specified\n", dev->name); ++ ret = -EINVAL; + break; ++ } + -+ case WDIOC_KEEPALIVE: -+ ar71xx_wdt_keepalive(); -+ ret = 0; -+ break; ++ printk(KERN_DEBUG "%s: using fixed link parameters\n", dev->name); + -+ case WDIOC_SETTIMEOUT: -+ ret = get_user(t, (int *)arg) ? -EFAULT : 0; -+ if (ret) -+ break; ++ ag->duplex = pdata->duplex; ++ ag->speed = pdata->speed; + -+ ret = ar71xx_wdt_set_timeout(t); -+ if (ret) -+ break; ++ return ret; ++} + -+ /* fallthrough */ -+ case WDIOC_GETTIMEOUT: -+ ret = put_user(wdt_timeout, (int *)arg) ? -EFAULT : 0; -+ break; ++static int ag71xx_phy_connect_multi(struct ag71xx *ag) ++{ ++ struct net_device *dev = ag->dev; ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); ++ struct phy_device *phydev = NULL; ++ int phy_addr; ++ int ret = 0; + -+ default: -+ ret = -ENOTTY; -+ break; -+ } ++ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { ++ if (!(pdata->phy_mask & (1 << phy_addr))) ++ continue; + -+ return ret; -+} ++ if (ag->mii_bus->phy_map[phy_addr] == NULL) ++ continue; + -+static const struct file_operations ar71xx_wdt_fops = { -+ .owner = THIS_MODULE, -+ .write = ar71xx_wdt_write, -+ .ioctl = ar71xx_wdt_ioctl, -+ .open = ar71xx_wdt_open, -+ .release = ar71xx_wdt_release, -+}; ++ DBG("%s: PHY found at %s, uid=%08x\n", ++ dev->name, ++ dev_name(&ag->mii_bus->phy_map[phy_addr]->dev), ++ ag->mii_bus->phy_map[phy_addr]->phy_id); + -+static struct miscdevice ar71xx_wdt_miscdev = { -+ .minor = WATCHDOG_MINOR, -+ .name = "watchdog", -+ .fops = &ar71xx_wdt_fops, -+}; ++ if (phydev == NULL) ++ phydev = ag->mii_bus->phy_map[phy_addr]; ++ } + -+static int __devinit ar71xx_wdt_probe(struct platform_device *pdev) -+{ -+ int ret; ++ if (!phydev) { ++ printk(KERN_ERR "%s: no PHY found with phy_mask=%08x\n", ++ dev->name, pdata->phy_mask); ++ return -ENODEV; ++ } + -+ max_timeout = (0xfffffffful / ar71xx_ahb_freq); -+ wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; ++ ag->phy_dev = phy_connect(dev, dev_name(&phydev->dev), ++ &ag71xx_phy_link_adjust, 0, ++ pdata->phy_if_mode); + -+ boot_status = -+ (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) ? -+ WDIOF_CARDRESET : 0; ++ if (IS_ERR(ag->phy_dev)) { ++ printk(KERN_ERR "%s: could not connect to PHY at %s\n", ++ dev->name, dev_name(&phydev->dev)); ++ return PTR_ERR(ag->phy_dev); ++ } + -+ ret = misc_register(&ar71xx_wdt_miscdev); -+ if (ret) -+ goto err_out; ++ /* mask with MAC supported features */ ++ if (pdata->has_gbit) ++ phydev->supported &= PHY_GBIT_FEATURES; ++ else ++ phydev->supported &= PHY_BASIC_FEATURES; + -+ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); ++ phydev->advertising = phydev->supported; + -+ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs (max=%d)\n", -+ wdt_timeout, max_timeout); ++ printk(KERN_DEBUG "%s: connected to PHY at %s [uid=%08x, driver=%s]\n", ++ dev->name, dev_name(&phydev->dev), ++ phydev->phy_id, phydev->drv->name); + -+ return 0; ++ ag->link = 0; ++ ag->speed = 0; ++ ag->duplex = -1; + -+err_out: + return ret; +} + -+static int __devexit ar71xx_wdt_remove(struct platform_device *pdev) ++static int dev_is_class(struct device *dev, void *class) +{ -+ misc_deregister(&ar71xx_wdt_miscdev); ++ if (dev->class != NULL && !strcmp(dev->class->name, class)) ++ return 1; ++ + return 0; +} + -+static struct platform_driver ar71xx_wdt_driver = { -+ .probe = ar71xx_wdt_probe, -+ .remove = __devexit_p(ar71xx_wdt_remove), -+ .driver = { -+ .name = DRV_NAME, -+ .owner = THIS_MODULE, -+ }, -+}; -+ -+static int __init ar71xx_wdt_init(void) ++static struct device *dev_find_class(struct device *parent, char *class) +{ -+ return platform_driver_register(&ar71xx_wdt_driver); ++ if (dev_is_class(parent, class)) { ++ get_device(parent); ++ return parent; ++ } ++ ++ return device_find_child(parent, class, dev_is_class); +} -+module_init(ar71xx_wdt_init); + -+static void __exit ar71xx_wdt_exit(void) ++static struct mii_bus *dev_to_mii_bus(struct device *dev) +{ -+ platform_driver_unregister(&ar71xx_wdt_driver); -+} -+module_exit(ar71xx_wdt_exit); ++ struct device *d; + -+MODULE_DESCRIPTION(DRV_DESC); -+MODULE_VERSION(DRV_VERSION); -+MODULE_AUTHOR("Gabor Juhos in the kernel source. -+ -+ The watchdog is usually used together with the watchdog daemon -+ which is available from -+ . This daemon can -+ also monitor NFS connections and can reboot the machine when the process -+ table is full. -+ -+ If unsure, say N. -+ -+if WATCHDOG -+ -+config WATCHDOG_NOWAYOUT -+ bool "Disable watchdog shutdown on close" -+ help -+ The default watchdog behaviour (which you get if you say N here) is -+ to stop the timer if the process managing it closes the file -+ /dev/watchdog. It's always remotely possible that this process might -+ get killed. If you say Y here, the watchdog cannot be stopped once -+ it has been started. ++ return bus; ++ } + -+# -+# General Watchdog drivers -+# ++ return NULL; ++} + -+comment "Watchdog Device Drivers" ++int ag71xx_phy_connect(struct ag71xx *ag) ++{ ++ struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag); + -+# Architecture Independent ++ ag->mii_bus = dev_to_mii_bus(pdata->mii_bus_dev); ++ if (ag->mii_bus == NULL) { ++ printk(KERN_ERR "%s: unable to find MII bus on device '%s'\n", ++ ag->dev->name, dev_name(pdata->mii_bus_dev)); ++ return -ENODEV; ++ } + -+config SOFT_WATCHDOG -+ tristate "Software watchdog" -+ help -+ A software monitoring watchdog. This will fail to reboot your system -+ from some situations that the hardware watchdog will recover -+ from. Equally it's a lot cheaper to install. ++ /* Reset the mdio bus explicitly */ ++ if (ag->mii_bus->reset) { ++ mutex_lock(&ag->mii_bus->mdio_lock); ++ ag->mii_bus->reset(ag->mii_bus); ++ mutex_unlock(&ag->mii_bus->mdio_lock); ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called softdog. ++ if (pdata->phy_mask) ++ return ag71xx_phy_connect_multi(ag); + -+config WM831X_WATCHDOG -+ tristate "WM831x watchdog" -+ depends on MFD_WM831X -+ help -+ Support for the watchdog in the WM831x AudioPlus PMICs. When -+ the watchdog triggers the system will be reset. ++ return ag71xx_phy_connect_fixed(ag); ++} + -+config WM8350_WATCHDOG -+ tristate "WM8350 watchdog" -+ depends on MFD_WM8350 -+ help -+ Support for the watchdog in the WM8350 AudioPlus PMIC. When -+ the watchdog triggers the system will be reset. ++void ag71xx_phy_disconnect(struct ag71xx *ag) ++{ ++ if (ag->phy_dev) ++ phy_disconnect(ag->phy_dev); ++} +diff -Nur linux-2.6.36.orig/drivers/net/phy/Kconfig linux-2.6.36/drivers/net/phy/Kconfig +--- linux-2.6.36.orig/drivers/net/phy/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/net/phy/Kconfig 2010-11-18 21:16:15.000000000 +0100 +@@ -93,6 +93,10 @@ + ---help--- + Supports the KSZ9021, VSC8201, KS8001 PHYs. + ++config IP175C_PHY ++ tristate "Driver for IC+ IP175C/IP178C switches" ++ select SWCONFIG + -+# ALPHA Architecture + config FIXED_PHY + bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs" + depends on PHYLIB=y +diff -Nur linux-2.6.36.orig/drivers/net/phy/phy.c linux-2.6.36/drivers/net/phy/phy.c +--- linux-2.6.36.orig/drivers/net/phy/phy.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/net/phy/phy.c 2010-11-18 21:16:15.000000000 +0100 +@@ -298,6 +298,50 @@ + } + EXPORT_SYMBOL(phy_ethtool_gset); + ++int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr) ++{ ++ u32 cmd; ++ int tmp; ++ struct ethtool_cmd ecmd = { ETHTOOL_GSET }; ++ struct ethtool_value edata = { ETHTOOL_GLINK }; + -+# ARM Architecture ++ if (get_user(cmd, (u32 *) useraddr)) ++ return -EFAULT; + -+config AT91RM9200_WATCHDOG -+ tristate "AT91RM9200 watchdog" -+ depends on ARCH_AT91RM9200 -+ help -+ Watchdog timer embedded into AT91RM9200 chips. This will reboot your -+ system when the timeout is reached. ++ switch (cmd) { ++ case ETHTOOL_GSET: ++ phy_ethtool_gset(phydev, &ecmd); ++ if (copy_to_user(useraddr, &ecmd, sizeof(ecmd))) ++ return -EFAULT; ++ return 0; + -+config AT91SAM9X_WATCHDOG -+ tristate "AT91SAM9X / AT91CAP9 watchdog" -+ depends on ARCH_AT91 && !ARCH_AT91RM9200 -+ help -+ Watchdog timer embedded into AT91SAM9X and AT91CAP9 chips. This will -+ reboot your system when the timeout is reached. ++ case ETHTOOL_SSET: ++ if (copy_from_user(&ecmd, useraddr, sizeof(ecmd))) ++ return -EFAULT; ++ return phy_ethtool_sset(phydev, &ecmd); + -+config 21285_WATCHDOG -+ tristate "DC21285 watchdog" -+ depends on FOOTBRIDGE -+ help -+ The Intel Footbridge chip contains a built-in watchdog circuit. Say Y -+ here if you wish to use this. Alternatively say M to compile the -+ driver as a module, which will be called wdt285. ++ case ETHTOOL_NWAY_RST: ++ /* if autoneg is off, it's an error */ ++ tmp = phy_read(phydev, MII_BMCR); ++ if (tmp & BMCR_ANENABLE) { ++ tmp |= (BMCR_ANRESTART); ++ phy_write(phydev, MII_BMCR, tmp); ++ return 0; ++ } ++ return -EINVAL; + -+ This driver does not work on all machines. In particular, early CATS -+ boards have hardware problems that will cause the machine to simply -+ lock up if the watchdog fires. ++ case ETHTOOL_GLINK: ++ edata.data = (phy_read(phydev, ++ MII_BMSR) & BMSR_LSTATUS) ? 1 : 0; ++ if (copy_to_user(useraddr, &edata, sizeof(edata))) ++ return -EFAULT; ++ return 0; ++ } + -+ "If in doubt, leave it out" - say N. ++ return -EOPNOTSUPP; ++} ++EXPORT_SYMBOL(phy_ethtool_ioctl); + -+config 977_WATCHDOG -+ tristate "NetWinder WB83C977 watchdog" -+ depends on FOOTBRIDGE && ARCH_NETWINDER -+ help -+ Say Y here to include support for the WB977 watchdog included in -+ NetWinder machines. Alternatively say M to compile the driver as -+ a module, which will be called wdt977. + /** + * phy_mii_ioctl - generic PHY MII ioctl interface + * @phydev: the phy_device struct +@@ -352,7 +396,7 @@ + } + + phy_write(phydev, mii_data->reg_num, val); +- + -+ Not sure? It's safe to say N. + if (mii_data->reg_num == MII_BMCR && + val & BMCR_RESET && + phydev->drv->config_init) { +@@ -471,7 +515,7 @@ + int idx; + + idx = phy_find_setting(phydev->speed, phydev->duplex); +- + -+config IXP2000_WATCHDOG -+ tristate "IXP2000 Watchdog" -+ depends on ARCH_IXP2000 -+ help -+ Say Y here if to include support for the watchdog timer -+ in the Intel IXP2000(2400, 2800, 2850) network processors. -+ This driver can be built as a module by choosing M. The module -+ will be called ixp2000_wdt. + idx++; + + idx = phy_find_valid(idx, phydev->supported); +diff -Nur linux-2.6.36.orig/drivers/net/phy/phy_device.c linux-2.6.36/drivers/net/phy/phy_device.c +--- linux-2.6.36.orig/drivers/net/phy/phy_device.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/net/phy/phy_device.c 2010-11-18 21:16:15.000000000 +0100 +@@ -146,6 +146,18 @@ + } + EXPORT_SYMBOL(phy_scan_fixups); + ++static int generic_receive_skb(struct sk_buff *skb) ++{ ++ skb->protocol = eth_type_trans(skb, skb->dev); ++ return netif_receive_skb(skb); ++} + -+ Say N if you are unsure. ++static int generic_rx(struct sk_buff *skb) ++{ ++ skb->protocol = eth_type_trans(skb, skb->dev); ++ return netif_rx(skb); ++} + -+config IXP4XX_WATCHDOG -+ tristate "IXP4xx Watchdog" -+ depends on ARCH_IXP4XX + struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id) + { + struct phy_device *dev; +@@ -176,6 +188,8 @@ + dev_set_name(&dev->dev, PHY_ID_FMT, bus->id, addr); + + dev->state = PHY_DOWN; ++ dev->netif_receive_skb = &generic_receive_skb; ++ dev->netif_rx = &generic_rx; + + mutex_init(&dev->lock); + INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine); +diff -Nur linux-2.6.36.orig/drivers/spi/Kconfig linux-2.6.36/drivers/spi/Kconfig +--- linux-2.6.36.orig/drivers/spi/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/spi/Kconfig 2010-11-18 21:16:15.000000000 +0100 +@@ -53,6 +53,13 @@ + + comment "SPI Master Controller Drivers" + ++config SPI_AR71XX ++ tristate "Atheros AR71xx SPI Controller" ++ depends on SPI_MASTER && ATHEROS_AR71XX ++ select SPI_BITBANG + help -+ Say Y here if to include support for the watchdog timer -+ in the Intel IXP4xx network processors. This driver can -+ be built as a module by choosing M. The module will -+ be called ixp4xx_wdt. -+ -+ Note: The internal IXP4xx watchdog does a soft CPU reset -+ which doesn't reset any peripherals. There are circumstances -+ where the watchdog will fail to reset the board correctly -+ (e.g., if the boot ROM is in an unreadable state). -+ -+ Say N if you are unsure. ++ This is the SPI contoller driver for Atheros AR71xx. + -+config KS8695_WATCHDOG -+ tristate "KS8695 watchdog" -+ depends on ARCH_KS8695 -+ help -+ Watchdog timer embedded into KS8695 processor. This will reboot your -+ system when the timeout is reached. + config SPI_ATMEL + tristate "Atmel SPI Controller" + depends on (ARCH_AT91 || AVR32) +diff -Nur linux-2.6.36.orig/drivers/spi/Makefile linux-2.6.36/drivers/spi/Makefile +--- linux-2.6.36.orig/drivers/spi/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/spi/Makefile 2010-11-18 21:16:15.000000000 +0100 +@@ -11,6 +11,7 @@ + obj-$(CONFIG_SPI_MASTER) += spi.o + + # SPI master controller drivers (bus) ++obj-$(CONFIG_SPI_AR71XX) += ar71xx_spi.o + obj-$(CONFIG_SPI_ATMEL) += atmel_spi.o + obj-$(CONFIG_SPI_BFIN) += spi_bfin5xx.o + obj-$(CONFIG_SPI_BITBANG) += spi_bitbang.o +diff -Nur linux-2.6.36.orig/drivers/spi/ap83_spi.c linux-2.6.36/drivers/spi/ap83_spi.c +--- linux-2.6.36.orig/drivers/spi/ap83_spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/spi/ap83_spi.c 2010-11-18 21:16:15.000000000 +0100 +@@ -0,0 +1,282 @@ ++/* ++ * Atheros AP83 board specific SPI Controller driver ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ + -+config HAVE_S3C2410_WATCHDOG -+ bool -+ help -+ This will include watchdog timer support for Samsung SoCs. If -+ you want to include watchdog support for any machine, kindly -+ select this in the respective mach-XXXX/Kconfig file. ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+config S3C2410_WATCHDOG -+ tristate "S3C2410 Watchdog" -+ depends on ARCH_S3C2410 || HAVE_S3C2410_WATCHDOG -+ help -+ Watchdog timer block in the Samsung SoCs. This will reboot -+ the system when the timer expires with the watchdog enabled. ++#include ++#include + -+ The driver is limited by the speed of the system's PCLK -+ signal, so with reasonably fast systems (PCLK around 50-66MHz) -+ then watchdog intervals of over approximately 20seconds are -+ unavailable. ++#define DRV_DESC "Atheros AP83 board SPI Controller driver" ++#define DRV_VERSION "0.1.0" ++#define DRV_NAME "ap83-spi" + -+ The driver can be built as a module by choosing M, and will -+ be called s3c2410_wdt ++#define AP83_SPI_CLK_HIGH (1 << 23) ++#define AP83_SPI_CLK_LOW 0 ++#define AP83_SPI_MOSI_HIGH (1 << 22) ++#define AP83_SPI_MOSI_LOW 0 + -+config SA1100_WATCHDOG -+ tristate "SA1100/PXA2xx watchdog" -+ depends on ARCH_SA1100 || ARCH_PXA -+ help -+ Watchdog timer embedded into SA11x0 and PXA2xx chips. This will -+ reboot your system when timeout is reached. ++#define AP83_SPI_GPIO_CS 1 ++#define AP83_SPI_GPIO_MISO 3 + -+ NOTE: once enabled, this timer cannot be disabled. ++struct ap83_spi { ++ struct spi_bitbang bitbang; ++ void __iomem *base; ++ u32 addr; + -+ To compile this driver as a module, choose M here: the -+ module will be called sa1100_wdt. ++ struct platform_device *pdev; ++}; + -+config MPCORE_WATCHDOG -+ tristate "MPcore watchdog" -+ depends on HAVE_ARM_TWD -+ help -+ Watchdog timer embedded into the MPcore system. ++static inline u32 ap83_spi_rr(struct ap83_spi *sp, u32 reg) ++{ ++ return __raw_readl(sp->base + reg); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called mpcore_wdt. ++static inline struct ap83_spi *spidev_to_sp(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} + -+config EP93XX_WATCHDOG -+ tristate "EP93xx Watchdog" -+ depends on ARCH_EP93XX -+ help -+ Say Y here if to include support for the watchdog timer -+ embedded in the Cirrus Logic EP93xx family of devices. ++static inline void setsck(struct spi_device *spi, int val) ++{ ++ struct ap83_spi *sp = spidev_to_sp(spi); + -+ To compile this driver as a module, choose M here: the -+ module will be called ep93xx_wdt. ++ if (val) ++ sp->addr |= AP83_SPI_CLK_HIGH; ++ else ++ sp->addr &= ~AP83_SPI_CLK_HIGH; + -+config OMAP_WATCHDOG -+ tristate "OMAP Watchdog" -+ depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS -+ help -+ Support for TI OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog. Say 'Y' -+ here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer. ++ dev_dbg(&spi->dev, "addr=%08x, SCK set to %s\n", ++ sp->addr, (val) ? "HIGH" : "LOW"); + -+config PNX4008_WATCHDOG -+ tristate "PNX4008 Watchdog" -+ depends on ARCH_PNX4008 -+ help -+ Say Y here if to include support for the watchdog timer -+ in the PNX4008 processor. -+ This driver can be built as a module by choosing M. The module -+ will be called pnx4008_wdt. ++ ap83_spi_rr(sp, sp->addr); ++} + -+ Say N if you are unsure. ++static inline void setmosi(struct spi_device *spi, int val) ++{ ++ struct ap83_spi *sp = spidev_to_sp(spi); + -+config IOP_WATCHDOG -+ tristate "IOP Watchdog" -+ depends on PLAT_IOP -+ select WATCHDOG_NOWAYOUT if (ARCH_IOP32X || ARCH_IOP33X) -+ help -+ Say Y here if to include support for the watchdog timer -+ in the Intel IOP3XX & IOP13XX I/O Processors. This driver can -+ be built as a module by choosing M. The module will -+ be called iop_wdt. -+ -+ Note: The IOP13XX watchdog does an Internal Bus Reset which will -+ affect both cores and the peripherals of the IOP. The ATU-X -+ and/or ATUe configuration registers will remain intact, but if -+ operating as an Root Complex and/or Central Resource, the PCI-X -+ and/or PCIe busses will also be reset. THIS IS A VERY BIG HAMMER. -+ -+config DAVINCI_WATCHDOG -+ tristate "DaVinci watchdog" -+ depends on ARCH_DAVINCI -+ help -+ Say Y here if to include support for the watchdog timer -+ in the DaVinci DM644x/DM646x processors. -+ To compile this driver as a module, choose M here: the -+ module will be called davinci_wdt. ++ if (val) ++ sp->addr |= AP83_SPI_MOSI_HIGH; ++ else ++ sp->addr &= ~AP83_SPI_MOSI_HIGH; + -+ NOTE: once enabled, this timer cannot be disabled. -+ Say N if you are unsure. ++ dev_dbg(&spi->dev, "addr=%08x, MOSI set to %s\n", ++ sp->addr, (val) ? "HIGH" : "LOW"); + -+config ORION_WATCHDOG -+ tristate "Orion watchdog" -+ depends on ARCH_ORION5X || ARCH_KIRKWOOD -+ help -+ Say Y here if to include support for the watchdog timer -+ in the Marvell Orion5x and Kirkwood ARM SoCs. -+ To compile this driver as a module, choose M here: the -+ module will be called orion_wdt. ++ ap83_spi_rr(sp, sp->addr); ++} + -+config COH901327_WATCHDOG -+ bool "ST-Ericsson COH 901 327 watchdog" -+ depends on ARCH_U300 -+ default y if MACH_U300 -+ help -+ Say Y here to include Watchdog timer support for the -+ watchdog embedded into the ST-Ericsson U300 series platforms. -+ This watchdog is used to reset the system and thus cannot be -+ compiled as a module. -+ -+config TWL4030_WATCHDOG -+ tristate "TWL4030 Watchdog" -+ depends on TWL4030_CORE -+ help -+ Support for TI TWL4030 watchdog. Say 'Y' here to enable the -+ watchdog timer support for TWL4030 chips. ++static inline u32 getmiso(struct spi_device *spi) ++{ ++ u32 ret; + -+config STMP3XXX_WATCHDOG -+ tristate "Freescale STMP3XXX watchdog" -+ depends on ARCH_STMP3XXX -+ help -+ Say Y here if to include support for the watchdog timer -+ for the Sigmatel STMP37XX/378X SoC. -+ To compile this driver as a module, choose M here: the -+ module will be called stmp3xxx_wdt. ++ ret = gpio_get_value(AP83_SPI_GPIO_MISO) ? 1 : 0; ++ dev_dbg(&spi->dev, "get MISO: %d\n", ret); + -+config NUC900_WATCHDOG -+ tristate "Nuvoton NUC900 watchdog" -+ depends on ARCH_W90X900 -+ help -+ Say Y here if to include support for the watchdog timer -+ for the Nuvoton NUC900 series SoCs. -+ To compile this driver as a module, choose M here: the -+ module will be called nuc900_wdt. ++ return ret; ++} + -+config ADX_WATCHDOG -+ tristate "Avionic Design Xanthos watchdog" -+ depends on ARCH_PXA_ADX -+ help -+ Say Y here if you want support for the watchdog timer on Avionic -+ Design Xanthos boards. ++static inline void do_spidelay(struct spi_device *spi, unsigned nsecs) ++{ ++ ndelay(nsecs); ++} + -+config TS72XX_WATCHDOG -+ tristate "TS-72XX SBC Watchdog" -+ depends on MACH_TS72XX -+ help -+ Technologic Systems TS-7200, TS-7250 and TS-7260 boards have -+ watchdog timer implemented in a external CPLD chip. Say Y here -+ if you want to support for the watchdog timer on TS-72XX boards. ++static void ap83_spi_chipselect(struct spi_device *spi, int on) ++{ ++ struct ap83_spi *sp = spidev_to_sp(spi); + -+ To compile this driver as a module, choose M here: the -+ module will be called ts72xx_wdt. ++ dev_dbg(&spi->dev, "set CS to %d\n", (on) ? 0 : 1); + -+config MAX63XX_WATCHDOG -+ tristate "Max63xx watchdog" -+ depends on ARM && HAS_IOMEM -+ help -+ Support for memory mapped max63{69,70,71,72,73,74} watchdog timer. ++ if (on) { ++ ar71xx_flash_acquire(); + -+config IMX2_WDT -+ tristate "IMX2+ Watchdog" -+ depends on ARCH_MX2 || ARCH_MX25 || ARCH_MX3 || ARCH_MX5 -+ help -+ This is the driver for the hardware watchdog -+ on the Freescale IMX2 and later processors. -+ If you have one of these processors and wish to have -+ watchdog support enabled, say Y, otherwise say N. ++ sp->addr = 0; ++ ap83_spi_rr(sp, sp->addr); + -+ To compile this driver as a module, choose M here: the -+ module will be called imx2_wdt. ++ gpio_set_value(AP83_SPI_GPIO_CS, 0); ++ } else { ++ gpio_set_value(AP83_SPI_GPIO_CS, 1); ++ ar71xx_flash_release(); ++ } ++} + -+# AVR32 Architecture ++#define spidelay(nsecs) \ ++ do { \ ++ /* Steal the spi_device pointer from our caller. \ ++ * The bitbang-API should probably get fixed here... */ \ ++ do_spidelay(spi, nsecs); \ ++ } while (0) + -+config AT32AP700X_WDT -+ tristate "AT32AP700x watchdog" -+ depends on CPU_AT32AP700X -+ help -+ Watchdog timer embedded into AT32AP700x devices. This will reboot -+ your system when the timeout is reached. ++#define EXPAND_BITBANG_TXRX ++#include + -+# BLACKFIN Architecture ++static u32 ap83_spi_txrx_mode0(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ dev_dbg(&spi->dev, "TXRX0 word=%08x, bits=%u\n", word, bits); ++ return bitbang_txrx_be_cpha0(spi, nsecs, 0, word, bits); ++} + -+config BFIN_WDT -+ tristate "Blackfin On-Chip Watchdog Timer" -+ depends on BLACKFIN -+ ---help--- -+ If you say yes here you will get support for the Blackfin On-Chip -+ Watchdog Timer. If you have one of these processors and wish to -+ have watchdog support enabled, say Y, otherwise say N. ++static u32 ap83_spi_txrx_mode1(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ dev_dbg(&spi->dev, "TXRX1 word=%08x, bits=%u\n", word, bits); ++ return bitbang_txrx_be_cpha1(spi, nsecs, 0, word, bits); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called bfin_wdt. ++static u32 ap83_spi_txrx_mode2(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ dev_dbg(&spi->dev, "TXRX2 word=%08x, bits=%u\n", word, bits); ++ return bitbang_txrx_be_cpha0(spi, nsecs, 1, word, bits); ++} + -+# CRIS Architecture ++static u32 ap83_spi_txrx_mode3(struct spi_device *spi, ++ unsigned nsecs, u32 word, u8 bits) ++{ ++ dev_dbg(&spi->dev, "TXRX3 word=%08x, bits=%u\n", word, bits); ++ return bitbang_txrx_be_cpha1(spi, nsecs, 1, word, bits); ++} + -+# FRV Architecture ++static int ap83_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct ap83_spi *sp; ++ struct ap83_spi_platform_data *pdata; ++ struct resource *r; ++ int ret; + -+# H8300 Architecture ++ ret = gpio_request(AP83_SPI_GPIO_MISO, "spi-miso"); ++ if (ret) { ++ dev_err(&pdev->dev, "gpio request failed for MISO\n"); ++ return ret; ++ } + -+# X86 (i386 + ia64 + x86_64) Architecture ++ ret = gpio_request(AP83_SPI_GPIO_CS, "spi-cs"); ++ if (ret) { ++ dev_err(&pdev->dev, "gpio request failed for CS\n"); ++ goto err_free_miso; ++ } + -+config ACQUIRE_WDT -+ tristate "Acquire SBC Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog on Single Board -+ Computers produced by Acquire Inc (and others). This watchdog -+ simply watches your kernel to make sure it doesn't freeze, and if -+ it does, it reboots your computer after a certain amount of time. ++ ret = gpio_direction_input(AP83_SPI_GPIO_MISO); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to set direction of MISO\n"); ++ goto err_free_cs; ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called acquirewdt. ++ ret = gpio_direction_output(AP83_SPI_GPIO_CS, 0); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to set direction of CS\n"); ++ goto err_free_cs; ++ } + -+ Most people will say N. ++ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); ++ if (master == NULL) { ++ dev_err(&pdev->dev, "failed to allocate spi master\n"); ++ return -ENOMEM; ++ } + -+config ADVANTECH_WDT -+ tristate "Advantech SBC Watchdog Timer" -+ depends on X86 -+ help -+ If you are configuring a Linux kernel for the Advantech single-board -+ computer, say `Y' here to support its built-in watchdog timer -+ feature. More information can be found at -+ ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); + -+config ALIM1535_WDT -+ tristate "ALi M1535 PMU Watchdog Timer" -+ depends on X86 && PCI -+ ---help--- -+ This is the driver for the hardware watchdog on the ALi M1535 PMU. ++ pdata = pdev->dev.platform_data; + -+ To compile this driver as a module, choose M here: the -+ module will be called alim1535_wdt. ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.chipselect = ap83_spi_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = ap83_spi_txrx_mode0; ++ sp->bitbang.txrx_word[SPI_MODE_1] = ap83_spi_txrx_mode1; ++ sp->bitbang.txrx_word[SPI_MODE_2] = ap83_spi_txrx_mode2; ++ sp->bitbang.txrx_word[SPI_MODE_3] = ap83_spi_txrx_mode3; + -+ Most people will say N. ++ sp->bitbang.master->bus_num = pdev->id; ++ sp->bitbang.master->num_chipselect = 1; + -+config ALIM7101_WDT -+ tristate "ALi M7101 PMU Computer Watchdog" -+ depends on PCI -+ help -+ This is the driver for the hardware watchdog on the ALi M7101 PMU -+ as used in the x86 Cobalt servers and also found in some -+ SPARC Netra servers too. ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ ret = -ENOENT; ++ goto err_spi_put; ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called alim7101_wdt. ++ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); ++ if (!sp->base) { ++ ret = -ENXIO; ++ goto err_spi_put; ++ } + -+ Most people will say N. ++ ret = spi_bitbang_start(&sp->bitbang); ++ if (!ret) ++ goto err_unmap; + -+config GEODE_WDT -+ tristate "AMD Geode CS5535/CS5536 Watchdog" -+ depends on CS5535_MFGPT -+ help -+ This driver enables a watchdog capability built into the -+ CS5535/CS5536 companion chips for the AMD Geode GX and LX -+ processors. This watchdog watches your kernel to make sure -+ it doesn't freeze, and if it does, it reboots your computer after -+ a certain amount of time. -+ -+ You can compile this driver directly into the kernel, or use -+ it as a module. The module will be called geodewdt. -+ -+config SC520_WDT -+ tristate "AMD Elan SC520 processor Watchdog" -+ depends on X86 -+ help -+ This is the driver for the hardware watchdog built in to the -+ AMD "Elan" SC520 microcomputer commonly used in embedded systems. -+ This watchdog simply watches your kernel to make sure it doesn't -+ freeze, and if it does, it reboots your computer after a certain -+ amount of time. ++ dev_info(&pdev->dev, "AP83 SPI adapter at %08x\n", r->start); + -+ You can compile this driver directly into the kernel, or use -+ it as a module. The module will be called sc520_wdt. ++ return 0; + -+config SBC_FITPC2_WATCHDOG -+ tristate "Compulab SBC-FITPC2 watchdog" -+ depends on X86 -+ ---help--- -+ This is the driver for the built-in watchdog timer on the fit-PC2, -+ fit-PC2i, CM-iAM single-board computers made by Compulab. ++ err_unmap: ++ iounmap(sp->base); ++ err_spi_put: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); + -+ It`s possible to enable watchdog timer either from BIOS (F2) or from booted Linux. -+ When "Watchdog Timer Value" enabled one can set 31-255 s operational range. ++ err_free_cs: ++ gpio_free(AP83_SPI_GPIO_CS); ++ err_free_miso: ++ gpio_free(AP83_SPI_GPIO_MISO); ++ return ret; ++} + -+ Entering BIOS setup temporary disables watchdog operation regardless to current state, -+ so system will not be restarted while user in BIOS setup. ++static int ap83_spi_remove(struct platform_device *pdev) ++{ ++ struct ap83_spi *sp = platform_get_drvdata(pdev); + -+ Once watchdog was enabled the system will be restarted every -+ "Watchdog Timer Value" period, so to prevent it user can restart or -+ disable the watchdog. ++ spi_bitbang_stop(&sp->bitbang); ++ iounmap(sp->base); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); + -+ To compile this driver as a module, choose M here: the -+ module will be called sbc_fitpc2_wdt. ++ return 0; ++} + -+ Most people will say N. ++static struct platform_driver ap83_spi_drv = { ++ .probe = ap83_spi_probe, ++ .remove = ap83_spi_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; + -+config EUROTECH_WDT -+ tristate "Eurotech CPU-1220/1410 Watchdog Timer" -+ depends on X86 -+ help -+ Enable support for the watchdog timer on the Eurotech CPU-1220 and -+ CPU-1410 cards. These are PC/104 SBCs. Spec sheets and product -+ information are at . ++static int __init ap83_spi_init(void) ++{ ++ return platform_driver_register(&ap83_spi_drv); ++} ++module_init(ap83_spi_init); + -+config IB700_WDT -+ tristate "IB700 SBC Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog on the IB700 Single -+ Board Computer produced by TMC Technology (www.tmc-uk.com). This watchdog -+ simply watches your kernel to make sure it doesn't freeze, and if -+ it does, it reboots your computer after a certain amount of time. ++static void __exit ap83_spi_exit(void) ++{ ++ platform_driver_unregister(&ap83_spi_drv); ++} ++module_exit(ap83_spi_exit); + -+ This driver is like the WDT501 driver but for slightly different hardware. ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.36.orig/drivers/spi/ar71xx_spi.c linux-2.6.36/drivers/spi/ar71xx_spi.c +--- linux-2.6.36.orig/drivers/spi/ar71xx_spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/spi/ar71xx_spi.c 2010-11-18 21:16:15.000000000 +0100 +@@ -0,0 +1,283 @@ ++/* ++ * Atheros AR71xx SPI Controller driver ++ * ++ * Copyright (C) 2008-2009 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ + -+ To compile this driver as a module, choose M here: the -+ module will be called ib700wdt. ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+ Most people will say N. ++#include ++#include + -+config IBMASR -+ tristate "IBM Automatic Server Restart" -+ depends on X86 -+ help -+ This is the driver for the IBM Automatic Server Restart watchdog -+ timer built-in into some eServer xSeries machines. ++#define DRV_DESC "Atheros AR71xx SPI Controller driver" ++#define DRV_VERSION "0.2.4" ++#define DRV_NAME "ar71xx-spi" + -+ To compile this driver as a module, choose M here: the -+ module will be called ibmasr. ++#undef PER_BIT_READ + -+config WAFER_WDT -+ tristate "ICP Single Board Computer Watchdog Timer" -+ depends on X86 -+ help -+ This is a driver for the hardware watchdog on the ICP Single -+ Board Computer. This driver is working on (at least) the following -+ IPC SBC's: Wafer 5823, Rocky 4783, Rocky 3703 and Rocky 3782. ++struct ar71xx_spi { ++ struct spi_bitbang bitbang; ++ u32 ioc_base; ++ u32 reg_ctrl; + -+ To compile this driver as a module, choose M here: the -+ module will be called wafer5823wdt. ++ void __iomem *base; + -+config I6300ESB_WDT -+ tristate "Intel 6300ESB Timer/Watchdog" -+ depends on X86 && PCI -+ ---help--- -+ Hardware driver for the watchdog timer built into the Intel -+ 6300ESB controller hub. ++ struct platform_device *pdev; ++ u32 (*get_ioc_base)(u8 chip_select, int cs_high, ++ int is_on); ++}; + -+ To compile this driver as a module, choose M here: the -+ module will be called i6300esb. -+ -+config ITCO_WDT -+ tristate "Intel TCO Timer/Watchdog" -+ depends on (X86 || IA64) && PCI -+ ---help--- -+ Hardware driver for the intel TCO timer based watchdog devices. -+ These drivers are included in the Intel 82801 I/O Controller -+ Hub family (from ICH0 up to ICH10) and in the Intel 63xxESB -+ controller hub. -+ -+ The TCO (Total Cost of Ownership) timer is a watchdog timer -+ that will reboot the machine after its second expiration. The -+ expiration time can be configured with the "heartbeat" parameter. -+ -+ On some motherboards the driver may fail to reset the chipset's -+ NO_REBOOT flag which prevents the watchdog from rebooting the -+ machine. If this is the case you will get a kernel message like -+ "failed to reset NO_REBOOT flag, reboot disabled by hardware". ++static inline u32 ar71xx_spi_rr(struct ar71xx_spi *sp, unsigned reg) ++{ ++ return __raw_readl(sp->base + reg); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called iTCO_wdt. -+ -+config ITCO_VENDOR_SUPPORT -+ bool "Intel TCO Timer/Watchdog Specific Vendor Support" -+ depends on ITCO_WDT -+ ---help--- -+ Add vendor specific support to the intel TCO timer based watchdog -+ devices. At this moment we only have additional support for some -+ SuperMicro Inc. motherboards. -+ -+config IT8712F_WDT -+ tristate "IT8712F (Smart Guardian) Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the built-in watchdog timer on the IT8712F -+ Super I/0 chipset used on many motherboards. ++static inline void ar71xx_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) ++{ ++ __raw_writel(val, sp->base + reg); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called it8712f_wdt. -+ -+config IT87_WDT -+ tristate "IT87 Watchdog Timer" -+ depends on X86 && EXPERIMENTAL -+ ---help--- -+ This is the driver for the hardware watchdog on the ITE IT8716, -+ IT8718, IT8726, IT8712(Version J,K) Super I/O chips. This watchdog -+ simply watches your kernel to make sure it doesn't freeze, and if -+ it does, it reboots your computer after a certain amount of time. -+ -+ To compile this driver as a module, choose M here: the module will -+ be called it87_wdt. -+ -+config HP_WATCHDOG -+ tristate "HP Proliant iLO 2 Hardware Watchdog Timer" -+ depends on X86 -+ help -+ A software monitoring watchdog and NMI sourcing driver. This driver -+ will detect lockups and provide stack trace. Also, when an NMI -+ occurs this driver will make the necessary BIOS calls to log -+ the cause of the NMI. This is a driver that will only load on a -+ HP ProLiant system with a minimum of iLO2 support. -+ To compile this driver as a module, choose M here: the -+ module will be called hpwdt. ++static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} + -+config SC1200_WDT -+ tristate "National Semiconductor PC87307/PC97307 (ala SC1200) Watchdog" -+ depends on X86 -+ help -+ This is a driver for National Semiconductor PC87307/PC97307 hardware -+ watchdog cards as found on the SC1200. This watchdog is mainly used -+ for power management purposes and can be used to power down the device -+ during inactivity periods (includes interrupt activity monitoring). ++static u32 ar71xx_spi_get_ioc_base(u8 chip_select, int cs_high, int is_on) ++{ ++ u32 ret; + -+ To compile this driver as a module, choose M here: the -+ module will be called sc1200wdt. ++ if (is_on == AR71XX_SPI_CS_INACTIVE) ++ ret = SPI_IOC_CS_ALL; ++ else ++ ret = SPI_IOC_CS_ALL & ~SPI_IOC_CS(chip_select); + -+ Most people will say N. ++ return ret; ++} + -+config SCx200_WDT -+ tristate "National Semiconductor SCx200 Watchdog" -+ depends on SCx200 && PCI -+ help -+ Enable the built-in watchdog timer support on the National -+ Semiconductor SCx200 processors. ++static void ar71xx_spi_chipselect(struct spi_device *spi, int value) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ void __iomem *base = sp->base; ++ u32 ioc_base; + -+ If compiled as a module, it will be called scx200_wdt. ++ switch (value) { ++ case BITBANG_CS_INACTIVE: ++ ioc_base = sp->get_ioc_base(spi->chip_select, ++ (spi->mode & SPI_CS_HIGH) != 0, ++ AR71XX_SPI_CS_INACTIVE); ++ __raw_writel(ioc_base, base + SPI_REG_IOC); ++ break; + -+config PC87413_WDT -+ tristate "NS PC87413 watchdog" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog on the PC87413 chipset -+ This watchdog simply watches your kernel to make sure it doesn't -+ freeze, and if it does, it reboots your computer after a certain -+ amount of time. ++ case BITBANG_CS_ACTIVE: ++ ioc_base = sp->get_ioc_base(spi->chip_select, ++ (spi->mode & SPI_CS_HIGH) != 0, ++ AR71XX_SPI_CS_ACTIVE); + -+ To compile this driver as a module, choose M here: the -+ module will be called pc87413_wdt. ++ __raw_writel(ioc_base, base + SPI_REG_IOC); ++ sp->ioc_base = ioc_base; ++ break; ++ } ++} + -+ Most people will say N. ++static void ar71xx_spi_setup_regs(struct spi_device *spi) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); + -+config RDC321X_WDT -+ tristate "RDC R-321x SoC watchdog" -+ depends on X86_RDC321X -+ help -+ This is the driver for the built in hardware watchdog -+ in the RDC R-321x SoC. ++ /* enable GPIO mode */ ++ ar71xx_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); + -+ To compile this driver as a module, choose M here: the -+ module will be called rdc321x_wdt. ++ /* save CTRL register */ ++ sp->reg_ctrl = ar71xx_spi_rr(sp, SPI_REG_CTRL); + -+config 60XX_WDT -+ tristate "SBC-60XX Watchdog Timer" -+ depends on X86 -+ help -+ This driver can be used with the watchdog timer found on some -+ single board computers, namely the 6010 PII based computer. -+ It may well work with other cards. It reads port 0x443 to enable -+ and re-set the watchdog timer, and reads port 0x45 to disable -+ the watchdog. If you have a card that behave in similar ways, -+ you can probably make this driver work with your card as well. ++ /* TODO: setup speed? */ ++ ar71xx_spi_wr(sp, SPI_REG_CTRL, 0x43); ++} + -+ You can compile this driver directly into the kernel, or use -+ it as a module. The module will be called sbc60xxwdt. ++static void ar71xx_spi_restore_regs(struct spi_device *spi) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); + -+config SBC8360_WDT -+ tristate "SBC8360 Watchdog Timer" -+ depends on X86 -+ ---help--- ++ /* restore CTRL register */ ++ ar71xx_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); ++ /* disable GPIO mode */ ++ ar71xx_spi_wr(sp, SPI_REG_FS, 0); ++} + -+ This is the driver for the hardware watchdog on the SBC8360 Single -+ Board Computer produced by Axiomtek Co., Ltd. (www.axiomtek.com). ++static int ar71xx_spi_setup(struct spi_device *spi) ++{ ++ int status; + -+ To compile this driver as a module, choose M here: the -+ module will be called sbc8360. ++ if (spi->bits_per_word > 32) ++ return -EINVAL; + -+ Most people will say N. ++ if (!spi->controller_state) ++ ar71xx_spi_setup_regs(spi); + -+config SBC7240_WDT -+ tristate "SBC Nano 7240 Watchdog Timer" -+ depends on X86_32 -+ ---help--- -+ This is the driver for the hardware watchdog found on the IEI -+ single board computers EPIC Nano 7240 (and likely others). This -+ watchdog simply watches your kernel to make sure it doesn't freeze, -+ and if it does, it reboots your computer after a certain amount of -+ time. ++ status = spi_bitbang_setup(spi); ++ if (status && !spi->controller_state) ++ ar71xx_spi_restore_regs(spi); + -+ To compile this driver as a module, choose M here: the -+ module will be called sbc7240_wdt. ++ return status; ++} + -+config CPU5_WDT -+ tristate "SMA CPU5 Watchdog" -+ depends on X86 -+ ---help--- -+ TBD. -+ To compile this driver as a module, choose M here: the -+ module will be called cpu5wdt. ++static void ar71xx_spi_cleanup(struct spi_device *spi) ++{ ++ ar71xx_spi_restore_regs(spi); ++ spi_bitbang_cleanup(spi); ++} + -+config SMSC_SCH311X_WDT -+ tristate "SMSC SCH311X Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog timer on the -+ SMSC SCH3112, SCH3114 and SCH3116 Super IO chipset -+ (LPC IO with 8042 KBC, Reset Generation, HWM and multiple -+ serial ports). ++static u32 ar71xx_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, ++ u32 word, u8 bits) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ void __iomem *base = sp->base; ++ u32 ioc = sp->ioc_base; ++ u32 ret; + -+ To compile this driver as a module, choose M here: the -+ module will be called sch311x_wdt. ++ /* clock starts at inactive polarity */ ++ for (word <<= (32 - bits); likely(bits); bits--) { ++ u32 out; + -+config SMSC37B787_WDT -+ tristate "Winbond SMsC37B787 Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog component on the -+ Winbond SMsC37B787 chipset as used on the NetRunner Mainboard -+ from Vision Systems and maybe others. ++ if (word & (1 << 31)) ++ out = ioc | SPI_IOC_DO; ++ else ++ out = ioc & ~SPI_IOC_DO; + -+ This watchdog simply watches your kernel to make sure it doesn't -+ freeze, and if it does, it reboots your computer after a certain -+ amount of time. ++ /* setup MSB (to slave) on trailing edge */ ++ __raw_writel(out, base + SPI_REG_IOC); + -+ Usually a userspace daemon will notify the kernel WDT driver that -+ userspace is still alive, at regular intervals. ++ __raw_writel(out | SPI_IOC_CLK, base + SPI_REG_IOC); + -+ To compile this driver as a module, choose M here: the -+ module will be called smsc37b787_wdt. ++ word <<= 1; + -+ Most people will say N. ++#ifdef PER_BIT_READ ++ /* sample MSB (from slave) on leading edge */ ++ ret = __raw_readl(base + SPI_REG_RDS); ++ __raw_writel(out, base + SPI_REG_IOC); ++#endif + -+config W83627HF_WDT -+ tristate "W83627HF Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog on the W83627HF chipset -+ as used in Advantech PC-9578 and Tyan S2721-533 motherboards -+ (and likely others). This watchdog simply watches your kernel to -+ make sure it doesn't freeze, and if it does, it reboots your computer -+ after a certain amount of time. ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called w83627hf_wdt. ++#ifndef PER_BIT_READ ++ ret = __raw_readl(base + SPI_REG_RDS); ++#endif ++ return ret; ++} + -+ Most people will say N. ++static int ar71xx_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct ar71xx_spi *sp; ++ struct ar71xx_spi_platform_data *pdata; ++ struct resource *r; ++ int ret; + -+config W83697HF_WDT -+ tristate "W83697HF/W83697HG Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog on the W83697HF/HG -+ chipset as used in Dedibox/VIA motherboards (and likely others). -+ This watchdog simply watches your kernel to make sure it doesn't -+ freeze, and if it does, it reboots your computer after a certain -+ amount of time. ++ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); ++ if (master == NULL) { ++ dev_err(&pdev->dev, "failed to allocate spi master\n"); ++ return -ENOMEM; ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called w83697hf_wdt. ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); + -+ Most people will say N. ++ pdata = pdev->dev.platform_data; + -+config W83697UG_WDT -+ tristate "W83697UG/W83697UF Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog on the W83697UG/UF -+ chipset as used in MSI Fuzzy CX700 VIA motherboards (and likely others). -+ This watchdog simply watches your kernel to make sure it doesn't -+ freeze, and if it does, it reboots your computer after a certain -+ amount of time. ++ master->setup = ar71xx_spi_setup; ++ master->cleanup = ar71xx_spi_cleanup; + -+ To compile this driver as a module, choose M here: the -+ module will be called w83697ug_wdt. ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.chipselect = ar71xx_spi_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = ar71xx_spi_txrx_mode0; ++ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; + -+ Most people will say N. ++ sp->get_ioc_base = ar71xx_spi_get_ioc_base; ++ if (pdata) { ++ sp->bitbang.master->bus_num = pdata->bus_num; ++ sp->bitbang.master->num_chipselect = pdata->num_chipselect; ++ if (pdata->get_ioc_base) ++ sp->get_ioc_base = pdata->get_ioc_base; ++ } else { ++ sp->bitbang.master->bus_num = 0; ++ sp->bitbang.master->num_chipselect = 3; ++ } + -+config W83877F_WDT -+ tristate "W83877F (EMACS) Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog on the W83877F chipset -+ as used in EMACS PC-104 motherboards (and likely others). This -+ watchdog simply watches your kernel to make sure it doesn't freeze, -+ and if it does, it reboots your computer after a certain amount of -+ time. ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ ret = -ENOENT; ++ goto err1; ++ } + -+ To compile this driver as a module, choose M here: the -+ module will be called w83877f_wdt. ++ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); ++ if (!sp->base) { ++ ret = -ENXIO; ++ goto err1; ++ } + -+ Most people will say N. ++ ret = spi_bitbang_start(&sp->bitbang); ++ if (!ret) ++ return 0; + -+config W83977F_WDT -+ tristate "W83977F (PCM-5335) Watchdog Timer" -+ depends on X86 -+ ---help--- -+ This is the driver for the hardware watchdog on the W83977F I/O chip -+ as used in AAEON's PCM-5335 SBC (and likely others). This -+ watchdog simply watches your kernel to make sure it doesn't freeze, -+ and if it does, it reboots your computer after a certain amount of -+ time. ++ iounmap(sp->base); ++ err1: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); + -+ To compile this driver as a module, choose M here: the -+ module will be called w83977f_wdt. -+ -+config MACHZ_WDT -+ tristate "ZF MachZ Watchdog" -+ depends on X86 -+ ---help--- -+ If you are using a ZF Micro MachZ processor, say Y here, otherwise -+ N. This is the driver for the watchdog timer built-in on that -+ processor using ZF-Logic interface. This watchdog simply watches -+ your kernel to make sure it doesn't freeze, and if it does, it -+ reboots your computer after a certain amount of time. ++ return ret; ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called machzwd. -+ -+config SBC_EPX_C3_WATCHDOG -+ tristate "Winsystems SBC EPX-C3 watchdog" -+ depends on X86 -+ ---help--- -+ This is the driver for the built-in watchdog timer on the EPX-C3 -+ Single-board computer made by Winsystems, Inc. -+ -+ *Note*: This hardware watchdog is not probeable and thus there -+ is no way to know if writing to its IO address will corrupt -+ your system or have any real effect. The only way to be sure -+ that this driver does what you want is to make sure you -+ are running it on an EPX-C3 from Winsystems with the watchdog -+ timer at IO address 0x1ee and 0x1ef. It will write to both those -+ IO ports. Basically, the assumption is made that if you compile -+ this driver into your kernel and/or load it as a module, that you -+ know what you are doing and that you are in fact running on an -+ EPX-C3 board! ++static int ar71xx_spi_remove(struct platform_device *pdev) ++{ ++ struct ar71xx_spi *sp = platform_get_drvdata(pdev); + -+ To compile this driver as a module, choose M here: the -+ module will be called sbc_epx_c3. ++ spi_bitbang_stop(&sp->bitbang); ++ iounmap(sp->base); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); + -+# M32R Architecture ++ return 0; ++} + -+# M68K Architecture ++static struct platform_driver ar71xx_spi_drv = { ++ .probe = ar71xx_spi_probe, ++ .remove = ar71xx_spi_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; + -+# M68KNOMMU Architecture ++static int __init ar71xx_spi_init(void) ++{ ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); ++ return platform_driver_register(&ar71xx_spi_drv); ++} ++module_init(ar71xx_spi_init); + -+# MIPS Architecture ++static void __exit ar71xx_spi_exit(void) ++{ ++ platform_driver_unregister(&ar71xx_spi_drv); ++} ++module_exit(ar71xx_spi_exit); + -+config BCM47XX_WDT -+ tristate "Broadcom BCM47xx Watchdog Timer" -+ depends on BCM47XX -+ help -+ Hardware driver for the Broadcom BCM47xx Watchog Timer. ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_AUTHOR("Imre Kaloz "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.36.orig/drivers/spi/pb44_spi.c linux-2.6.36/drivers/spi/pb44_spi.c +--- linux-2.6.36.orig/drivers/spi/pb44_spi.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/spi/pb44_spi.c 2010-11-18 21:16:15.000000000 +0100 +@@ -0,0 +1,299 @@ ++/* ++ * Atheros PB44 board SPI controller driver ++ * ++ * Copyright (C) 2009 Gabor Juhos ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ + -+config RC32434_WDT -+ tristate "IDT RC32434 SoC Watchdog Timer" -+ depends on MIKROTIK_RB532 -+ help -+ Hardware driver for the IDT RC32434 SoC built-in -+ watchdog timer. ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+ To compile this driver as a module, choose M here: the -+ module will be called rc32434_wdt. ++#include ++#include + -+config INDYDOG -+ tristate "Indy/I2 Hardware Watchdog" -+ depends on SGI_HAS_INDYDOG -+ help -+ Hardware driver for the Indy's/I2's watchdog. This is a -+ watchdog timer that will reboot the machine after a 60 second -+ timer expired and no process has written to /dev/watchdog during -+ that time. -+ -+config WDT_MTX1 -+ tristate "MTX-1 Hardware Watchdog" -+ depends on MIPS_MTX1 -+ help -+ Hardware driver for the MTX-1 boards. This is a watchdog timer that -+ will reboot the machine after a 100 seconds timer expired. ++#define DRV_DESC "Atheros PB44 SPI Controller driver" ++#define DRV_VERSION "0.1.0" ++#define DRV_NAME "pb44-spi" + -+config PNX833X_WDT -+ tristate "PNX833x Hardware Watchdog" -+ depends on SOC_PNX8335 -+ help -+ Hardware driver for the PNX833x's watchdog. This is a -+ watchdog timer that will reboot the machine after a programable -+ timer has expired and no process has written to /dev/watchdog during -+ that time. -+ -+config SIBYTE_WDOG -+ tristate "Sibyte SoC hardware watchdog" -+ depends on CPU_SB1 -+ help -+ Watchdog driver for the built in watchdog hardware in Sibyte -+ SoC processors. There are apparently two watchdog timers -+ on such processors; this driver supports only the first one, -+ because currently Linux only supports exporting one watchdog -+ to userspace. -+ -+ To compile this driver as a loadable module, choose M here. -+ The module will be called sb_wdog. -+ -+config AR7_WDT -+ tristate "TI AR7 Watchdog Timer" -+ depends on AR7 -+ help -+ Hardware driver for the TI AR7 Watchdog Timer. ++#undef PER_BIT_READ + -+config TXX9_WDT -+ tristate "Toshiba TXx9 Watchdog Timer" -+ depends on CPU_TX39XX || CPU_TX49XX -+ help -+ Hardware driver for the built-in watchdog timer on TXx9 MIPS SoCs. ++struct ar71xx_spi { ++ struct spi_bitbang bitbang; ++ u32 ioc_base; ++ u32 reg_ctrl; + -+# PARISC Architecture ++ void __iomem *base; + -+# POWERPC Architecture ++ struct platform_device *pdev; ++}; + -+config GEF_WDT -+ tristate "GE Watchdog Timer" -+ depends on GEF_SBC610 || GEF_SBC310 || GEF_PPC9A -+ ---help--- -+ Watchdog timer found in a number of GE single board computers. ++static inline u32 pb44_spi_rr(struct ar71xx_spi *sp, unsigned reg) ++{ ++ return __raw_readl(sp->base + reg); ++} + -+config MPC5200_WDT -+ bool "MPC52xx Watchdog Timer" -+ depends on PPC_MPC52xx -+ help -+ Use General Purpose Timer (GPT) 0 on the MPC5200 as Watchdog. ++static inline void pb44_spi_wr(struct ar71xx_spi *sp, unsigned reg, u32 val) ++{ ++ __raw_writel(val, sp->base + reg); ++} + -+config 8xxx_WDT -+ tristate "MPC8xxx Platform Watchdog Timer" -+ depends on PPC_8xx || PPC_83xx || PPC_86xx -+ help -+ This driver is for a SoC level watchdog that exists on some -+ Freescale PowerPC processors. So far this driver supports: -+ - MPC8xx watchdogs -+ - MPC83xx watchdogs -+ - MPC86xx watchdogs ++static inline struct ar71xx_spi *spidev_to_sp(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} + -+ For BookE processors (MPC85xx) use the BOOKE_WDT driver instead. ++static void pb44_spi_chipselect(struct spi_device *spi, int is_active) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active; + -+config MV64X60_WDT -+ tristate "MV64X60 (Marvell Discovery) Watchdog Timer" -+ depends on MV64X60 ++ if (is_active) { ++ /* set initial clock polarity */ ++ if (spi->mode & SPI_CPOL) ++ sp->ioc_base |= SPI_IOC_CLK; ++ else ++ sp->ioc_base &= ~SPI_IOC_CLK; + -+config PIKA_WDT -+ tristate "PIKA FPGA Watchdog" -+ depends on WARP -+ default y -+ help -+ This enables the watchdog in the PIKA FPGA. Currently used on -+ the Warp platform. ++ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); ++ } + -+config BOOKE_WDT -+ bool "PowerPC Book-E Watchdog Timer" -+ depends on BOOKE || 4xx -+ ---help--- -+ Please see Documentation/watchdog/watchdog-api.txt for -+ more information. ++ if (spi->chip_select) { ++ unsigned long gpio = (unsigned long) spi->controller_data; + -+# PPC64 Architecture ++ /* SPI is normally active-low */ ++ gpio_set_value(gpio, cs_high); ++ } else { ++ if (cs_high) ++ sp->ioc_base |= SPI_IOC_CS0; ++ else ++ sp->ioc_base &= ~SPI_IOC_CS0; + -+config WATCHDOG_RTAS -+ tristate "RTAS watchdog" -+ depends on PPC_RTAS -+ help -+ This driver adds watchdog support for the RTAS watchdog. ++ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); ++ } + -+ To compile this driver as a module, choose M here. The module -+ will be called wdrtas. ++} + -+# S390 Architecture ++static int pb44_spi_setup_cs(struct spi_device *spi) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); + -+config ZVM_WATCHDOG -+ tristate "z/VM Watchdog Timer" -+ depends on S390 -+ help -+ IBM s/390 and zSeries machines running under z/VM 5.1 or later -+ provide a virtual watchdog timer to their guest that cause a -+ user define Control Program command to be executed after a -+ timeout. ++ /* enable GPIO mode */ ++ pb44_spi_wr(sp, SPI_REG_FS, SPI_FS_GPIO); + -+ To compile this driver as a module, choose M here. The module -+ will be called vmwatchdog. ++ /* save CTRL register */ ++ sp->reg_ctrl = pb44_spi_rr(sp, SPI_REG_CTRL); ++ sp->ioc_base = pb44_spi_rr(sp, SPI_REG_IOC); + -+# SUPERH (sh + sh64) Architecture ++ /* TODO: setup speed? */ ++ pb44_spi_wr(sp, SPI_REG_CTRL, 0x43); + -+config SH_WDT -+ tristate "SuperH Watchdog" -+ depends on SUPERH && (CPU_SH3 || CPU_SH4) -+ help -+ This driver adds watchdog support for the integrated watchdog in the -+ SuperH processors. If you have one of these processors and wish -+ to have watchdog support enabled, say Y, otherwise say N. ++ if (spi->chip_select) { ++ unsigned long gpio = (unsigned long) spi->controller_data; ++ int status = 0; + -+ As a side note, saying Y here will automatically boost HZ to 1000 -+ so that the timer has a chance to clear the overflow counter. On -+ slower systems (such as the SH-2 and SH-3) this will likely yield -+ some performance issues. As such, the WDT should be avoided here -+ unless it is absolutely necessary. ++ status = gpio_request(gpio, dev_name(&spi->dev)); ++ if (status) ++ return status; + -+ To compile this driver as a module, choose M here: the -+ module will be called shwdt. ++ status = gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH); ++ if (status) { ++ gpio_free(gpio); ++ return status; ++ } ++ } else { ++ if (spi->mode & SPI_CS_HIGH) ++ sp->ioc_base |= SPI_IOC_CS0; ++ else ++ sp->ioc_base &= ~SPI_IOC_CS0; ++ pb44_spi_wr(sp, SPI_REG_IOC, sp->ioc_base); ++ } + -+config SH_WDT_MMAP -+ bool "Allow mmap of SH WDT" -+ default n -+ depends on SH_WDT -+ help -+ If you say Y here, user applications will be able to mmap the -+ WDT/CPG registers. ++ return 0; ++} + -+# SPARC Architecture ++static void pb44_spi_cleanup_cs(struct spi_device *spi) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); + -+# SPARC64 Architecture ++ if (spi->chip_select) { ++ unsigned long gpio = (unsigned long) spi->controller_data; ++ gpio_free(gpio); ++ } + -+config WATCHDOG_CP1XXX -+ tristate "CP1XXX Hardware Watchdog support" -+ depends on SPARC64 && PCI -+ ---help--- -+ This is the driver for the hardware watchdog timers present on -+ Sun Microsystems CompactPCI models CP1400 and CP1500. ++ /* restore CTRL register */ ++ pb44_spi_wr(sp, SPI_REG_CTRL, sp->reg_ctrl); ++ /* disable GPIO mode */ ++ pb44_spi_wr(sp, SPI_REG_FS, 0); ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called cpwatchdog. ++static int pb44_spi_setup(struct spi_device *spi) ++{ ++ int status = 0; + -+ If you do not have a CompactPCI model CP1400 or CP1500, or -+ another UltraSPARC-IIi-cEngine boardset with hardware watchdog, -+ you should say N to this option. ++ if (spi->bits_per_word > 32) ++ return -EINVAL; + -+config WATCHDOG_RIO -+ tristate "RIO Hardware Watchdog support" -+ depends on SPARC64 && PCI -+ help -+ Say Y here to support the hardware watchdog capability on Sun RIO -+ machines. The watchdog timeout period is normally one minute but -+ can be changed with a boot-time parameter. ++ if (!spi->controller_state) { ++ status = pb44_spi_setup_cs(spi); ++ if (status) ++ return status; ++ } + -+# XTENSA Architecture ++ status = spi_bitbang_setup(spi); ++ if (status && !spi->controller_state) ++ pb44_spi_cleanup_cs(spi); + -+# -+# ISA-based Watchdog Cards -+# ++ return status; ++} + -+comment "ISA-based Watchdog Cards" -+ depends on ISA ++static void pb44_spi_cleanup(struct spi_device *spi) ++{ ++ pb44_spi_cleanup_cs(spi); ++ spi_bitbang_cleanup(spi); ++} + -+config PCWATCHDOG -+ tristate "Berkshire Products ISA-PC Watchdog" -+ depends on ISA -+ ---help--- -+ This is the driver for the Berkshire Products ISA-PC Watchdog card. -+ This card simply watches your kernel to make sure it doesn't freeze, -+ and if it does, it reboots your computer after a certain amount of -+ time. This driver is like the WDT501 driver but for different -+ hardware. Please read . The PC -+ watchdog cards can be ordered from . ++static u32 pb44_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs, ++ u32 word, u8 bits) ++{ ++ struct ar71xx_spi *sp = spidev_to_sp(spi); ++ u32 ioc = sp->ioc_base; ++ u32 ret; + -+ To compile this driver as a module, choose M here: the -+ module will be called pcwd. ++ /* clock starts at inactive polarity */ ++ for (word <<= (32 - bits); likely(bits); bits--) { ++ u32 out; + -+ Most people will say N. ++ if (word & (1 << 31)) ++ out = ioc | SPI_IOC_DO; ++ else ++ out = ioc & ~SPI_IOC_DO; + -+config MIXCOMWD -+ tristate "Mixcom Watchdog" -+ depends on ISA -+ ---help--- -+ This is a driver for the Mixcom hardware watchdog cards. This -+ watchdog simply watches your kernel to make sure it doesn't freeze, -+ and if it does, it reboots your computer after a certain amount of -+ time. ++ /* setup MSB (to slave) on trailing edge */ ++ pb44_spi_wr(sp, SPI_REG_IOC, out); ++ pb44_spi_wr(sp, SPI_REG_IOC, out | SPI_IOC_CLK); + -+ To compile this driver as a module, choose M here: the -+ module will be called mixcomwd. ++ word <<= 1; + -+ Most people will say N. ++#ifdef PER_BIT_READ ++ /* sample MSB (from slave) on leading edge */ ++ ret = pb44_spi_rr(sp, SPI_REG_RDS); ++ pb44_spi_wr(sp, SPI_REG_IOC, out); ++#endif ++ } + -+config WDT -+ tristate "WDT Watchdog timer" -+ depends on ISA -+ ---help--- -+ If you have a WDT500P or WDT501P watchdog board, say Y here, -+ otherwise N. It is not possible to probe for this board, which means -+ that you have to inform the kernel about the IO port and IRQ that -+ is needed (you can do this via the io and irq parameters) ++#ifndef PER_BIT_READ ++ ret = pb44_spi_rr(sp, SPI_REG_RDS); ++#endif ++ return ret; ++} + -+ To compile this driver as a module, choose M here: the -+ module will be called wdt. ++static int pb44_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct ar71xx_spi *sp; ++ struct ar71xx_spi_platform_data *pdata; ++ struct resource *r; ++ int ret; + -+# -+# PCI-based Watchdog Cards -+# ++ master = spi_alloc_master(&pdev->dev, sizeof(*sp)); ++ if (master == NULL) { ++ dev_err(&pdev->dev, "failed to allocate spi master\n"); ++ return -ENOMEM; ++ } + -+comment "PCI-based Watchdog Cards" -+ depends on PCI ++ sp = spi_master_get_devdata(master); ++ platform_set_drvdata(pdev, sp); + -+config PCIPCWATCHDOG -+ tristate "Berkshire Products PCI-PC Watchdog" -+ depends on PCI -+ ---help--- -+ This is the driver for the Berkshire Products PCI-PC Watchdog card. -+ This card simply watches your kernel to make sure it doesn't freeze, -+ and if it does, it reboots your computer after a certain amount of -+ time. The card can also monitor the internal temperature of the PC. -+ More info is available at . ++ pdata = pdev->dev.platform_data; + -+ To compile this driver as a module, choose M here: the -+ module will be called pcwd_pci. ++ master->setup = pb44_spi_setup; ++ master->cleanup = pb44_spi_cleanup; ++ if (pdata) { ++ master->bus_num = pdata->bus_num; ++ master->num_chipselect = pdata->num_chipselect; ++ } else { ++ master->bus_num = 0; ++ master->num_chipselect = 1; ++ } + -+ Most people will say N. ++ sp->bitbang.master = spi_master_get(master); ++ sp->bitbang.chipselect = pb44_spi_chipselect; ++ sp->bitbang.txrx_word[SPI_MODE_0] = pb44_spi_txrx_mode0; ++ sp->bitbang.setup_transfer = spi_bitbang_setup_transfer; ++ sp->bitbang.flags = SPI_CS_HIGH; + -+config WDTPCI -+ tristate "PCI-WDT500/501 Watchdog timer" -+ depends on PCI -+ ---help--- -+ If you have a PCI-WDT500/501 watchdog board, say Y here, otherwise N. ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ ret = -ENOENT; ++ goto err1; ++ } + -+ If you have a PCI-WDT501 watchdog board then you can enable the -+ temperature sensor by setting the type parameter to 501. ++ sp->base = ioremap_nocache(r->start, r->end - r->start + 1); ++ if (!sp->base) { ++ ret = -ENXIO; ++ goto err1; ++ } + -+ If you want to enable the Fan Tachometer on the PCI-WDT501, then you -+ can do this via the tachometer parameter. Only do this if you have a -+ fan tachometer actually set up. ++ ret = spi_bitbang_start(&sp->bitbang); ++ if (!ret) ++ return 0; + -+ To compile this driver as a module, choose M here: the -+ module will be called wdt_pci. ++ iounmap(sp->base); ++ err1: ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); + -+# -+# USB-based Watchdog Cards -+# ++ return ret; ++} + -+comment "USB-based Watchdog Cards" -+ depends on USB ++static int pb44_spi_remove(struct platform_device *pdev) ++{ ++ struct ar71xx_spi *sp = platform_get_drvdata(pdev); + -+config USBPCWATCHDOG -+ tristate "Berkshire Products USB-PC Watchdog" -+ depends on USB -+ ---help--- -+ This is the driver for the Berkshire Products USB-PC Watchdog card. -+ This card simply watches your kernel to make sure it doesn't freeze, -+ and if it does, it reboots your computer after a certain amount of -+ time. The card can also monitor the internal temperature of the PC. -+ More info is available at . ++ spi_bitbang_stop(&sp->bitbang); ++ iounmap(sp->base); ++ platform_set_drvdata(pdev, NULL); ++ spi_master_put(sp->bitbang.master); + -+ To compile this driver as a module, choose M here: the -+ module will be called pcwd_usb. ++ return 0; ++} + -+ Most people will say N. ++static struct platform_driver pb44_spi_drv = { ++ .probe = pb44_spi_probe, ++ .remove = pb44_spi_remove, ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; + -+endif # WATCHDOG -diff -Nur linux-2.6.35.7.orig/drivers/watchdog/Makefile linux-2.6.35.7/drivers/watchdog/Makefile ---- linux-2.6.35.7.orig/drivers/watchdog/Makefile 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/drivers/watchdog/Makefile 2010-10-14 20:28:01.588091787 +0200 -@@ -114,6 +114,7 @@ - obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o - obj-$(CONFIG_AR7_WDT) += ar7_wdt.o - obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o - - # PARISC Architecture - -diff -Nur linux-2.6.35.7.orig/drivers/watchdog/Makefile.orig linux-2.6.35.7/drivers/watchdog/Makefile.orig ---- linux-2.6.35.7.orig/drivers/watchdog/Makefile.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/drivers/watchdog/Makefile.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,148 @@ -+# -+# Makefile for the WatchDog device drivers. -+# ++static int __init pb44_spi_init(void) ++{ ++ return platform_driver_register(&pb44_spi_drv); ++} ++module_init(pb44_spi_init); + -+# Only one watchdog can succeed. We probe the ISA/PCI/USB based -+# watchdog-cards first, then the architecture specific watchdog -+# drivers and then the architecture independant "softdog" driver. -+# This means that if your ISA/PCI/USB card isn't detected that -+# you can fall back to an architecture specific driver and if -+# that also fails then you can fall back to the software watchdog -+# to give you some cover. -+ -+# ISA-based Watchdog Cards -+obj-$(CONFIG_PCWATCHDOG) += pcwd.o -+obj-$(CONFIG_MIXCOMWD) += mixcomwd.o -+obj-$(CONFIG_WDT) += wdt.o -+ -+# PCI-based Watchdog Cards -+obj-$(CONFIG_PCIPCWATCHDOG) += pcwd_pci.o -+obj-$(CONFIG_WDTPCI) += wdt_pci.o -+ -+# USB-based Watchdog Cards -+obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o -+ -+# ALPHA Architecture -+ -+# ARM Architecture -+obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o -+obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o -+obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o -+obj-$(CONFIG_TWL4030_WATCHDOG) += twl4030_wdt.o -+obj-$(CONFIG_21285_WATCHDOG) += wdt285.o -+obj-$(CONFIG_977_WATCHDOG) += wdt977.o -+obj-$(CONFIG_IXP2000_WATCHDOG) += ixp2000_wdt.o -+obj-$(CONFIG_IXP4XX_WATCHDOG) += ixp4xx_wdt.o -+obj-$(CONFIG_KS8695_WATCHDOG) += ks8695_wdt.o -+obj-$(CONFIG_S3C2410_WATCHDOG) += s3c2410_wdt.o -+obj-$(CONFIG_SA1100_WATCHDOG) += sa1100_wdt.o -+obj-$(CONFIG_MPCORE_WATCHDOG) += mpcore_wdt.o -+obj-$(CONFIG_EP93XX_WATCHDOG) += ep93xx_wdt.o -+obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o -+obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o -+obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o -+obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o -+obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o -+obj-$(CONFIG_STMP3XXX_WATCHDOG) += stmp3xxx_wdt.o -+obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o -+obj-$(CONFIG_ADX_WATCHDOG) += adx_wdt.o -+obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o -+obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o -+ -+# AVR32 Architecture -+obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o -+ -+# BLACKFIN Architecture -+obj-$(CONFIG_BFIN_WDT) += bfin_wdt.o -+ -+# CRIS Architecture -+ -+# FRV Architecture -+ -+# H8300 Architecture -+ -+# X86 (i386 + ia64 + x86_64) Architecture -+obj-$(CONFIG_ACQUIRE_WDT) += acquirewdt.o -+obj-$(CONFIG_ADVANTECH_WDT) += advantechwdt.o -+obj-$(CONFIG_ALIM1535_WDT) += alim1535_wdt.o -+obj-$(CONFIG_ALIM7101_WDT) += alim7101_wdt.o -+obj-$(CONFIG_GEODE_WDT) += geodewdt.o -+obj-$(CONFIG_SC520_WDT) += sc520_wdt.o -+obj-$(CONFIG_SBC_FITPC2_WATCHDOG) += sbc_fitpc2_wdt.o -+obj-$(CONFIG_EUROTECH_WDT) += eurotechwdt.o -+obj-$(CONFIG_IB700_WDT) += ib700wdt.o -+obj-$(CONFIG_IBMASR) += ibmasr.o -+obj-$(CONFIG_WAFER_WDT) += wafer5823wdt.o -+obj-$(CONFIG_I6300ESB_WDT) += i6300esb.o -+obj-$(CONFIG_ITCO_WDT) += iTCO_wdt.o -+ifeq ($(CONFIG_ITCO_VENDOR_SUPPORT),y) -+obj-$(CONFIG_ITCO_WDT) += iTCO_vendor_support.o -+endif -+obj-$(CONFIG_IT8712F_WDT) += it8712f_wdt.o -+obj-$(CONFIG_IT87_WDT) += it87_wdt.o -+obj-$(CONFIG_HP_WATCHDOG) += hpwdt.o -+obj-$(CONFIG_SC1200_WDT) += sc1200wdt.o -+obj-$(CONFIG_SCx200_WDT) += scx200_wdt.o -+obj-$(CONFIG_PC87413_WDT) += pc87413_wdt.o -+obj-$(CONFIG_RDC321X_WDT) += rdc321x_wdt.o -+obj-$(CONFIG_60XX_WDT) += sbc60xxwdt.o -+obj-$(CONFIG_SBC8360_WDT) += sbc8360.o -+obj-$(CONFIG_SBC7240_WDT) += sbc7240_wdt.o -+obj-$(CONFIG_CPU5_WDT) += cpu5wdt.o -+obj-$(CONFIG_SMSC_SCH311X_WDT) += sch311x_wdt.o -+obj-$(CONFIG_SMSC37B787_WDT) += smsc37b787_wdt.o -+obj-$(CONFIG_W83627HF_WDT) += w83627hf_wdt.o -+obj-$(CONFIG_W83697HF_WDT) += w83697hf_wdt.o -+obj-$(CONFIG_W83697UG_WDT) += w83697ug_wdt.o -+obj-$(CONFIG_W83877F_WDT) += w83877f_wdt.o -+obj-$(CONFIG_W83977F_WDT) += w83977f_wdt.o -+obj-$(CONFIG_MACHZ_WDT) += machzwd.o -+obj-$(CONFIG_SBC_EPX_C3_WATCHDOG) += sbc_epx_c3.o -+ -+# M32R Architecture -+ -+# M68K Architecture -+ -+# M68KNOMMU Architecture -+ -+# MIPS Architecture -+obj-$(CONFIG_BCM47XX_WDT) += bcm47xx_wdt.o -+obj-$(CONFIG_RC32434_WDT) += rc32434_wdt.o -+obj-$(CONFIG_INDYDOG) += indydog.o -+obj-$(CONFIG_WDT_MTX1) += mtx-1_wdt.o -+obj-$(CONFIG_PNX833X_WDT) += pnx833x_wdt.o -+obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o -+obj-$(CONFIG_AR7_WDT) += ar7_wdt.o -+obj-$(CONFIG_TXX9_WDT) += txx9wdt.o -+ -+# PARISC Architecture -+ -+# POWERPC Architecture -+obj-$(CONFIG_GEF_WDT) += gef_wdt.o -+obj-$(CONFIG_8xxx_WDT) += mpc8xxx_wdt.o -+obj-$(CONFIG_MV64X60_WDT) += mv64x60_wdt.o -+obj-$(CONFIG_PIKA_WDT) += pika_wdt.o -+obj-$(CONFIG_BOOKE_WDT) += booke_wdt.o -+ -+# PPC64 Architecture -+obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o -+ -+# S390 Architecture -+ -+# SUPERH (sh + sh64) Architecture -+obj-$(CONFIG_SH_WDT) += shwdt.o -+ -+# SPARC Architecture -+ -+# SPARC64 Architecture -+ -+obj-$(CONFIG_WATCHDOG_RIO) += riowd.o -+obj-$(CONFIG_WATCHDOG_CP1XXX) += cpwd.o -+ -+# XTENSA Architecture -+ -+# Architecture Independant -+obj-$(CONFIG_WM831X_WATCHDOG) += wm831x_wdt.o -+obj-$(CONFIG_WM8350_WATCHDOG) += wm8350_wdt.o -+obj-$(CONFIG_MAX63XX_WATCHDOG) += max63xx_wdt.o -+obj-$(CONFIG_SOFT_WATCHDOG) += softdog.o -diff -Nur linux-2.6.35.7.orig/include/linux/ath9k_platform.h linux-2.6.35.7/include/linux/ath9k_platform.h ---- linux-2.6.35.7.orig/include/linux/ath9k_platform.h 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/include/linux/ath9k_platform.h 2010-10-14 20:28:01.618101105 +0200 -@@ -1,19 +1,11 @@ - /* -- * Copyright (c) 2008 Atheros Communications Inc. -- * Copyright (c) 2009 Gabor Juhos -- * Copyright (c) 2009 Imre Kaloz -+ * ath9k platform data defines - * -- * Permission to use, copy, modify, and/or distribute this software for any -- * purpose with or without fee is hereby granted, provided that the above -- * copyright notice and this permission notice appear in all copies. -+ * Copyright (C) 2008 Gabor Juhos - * -- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. - */ - - #ifndef _LINUX_ATH9K_PLATFORM_H -@@ -23,6 +15,9 @@ - - struct ath9k_platform_data { - u16 eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS]; -+ u8 *macaddr; ++static void __exit pb44_spi_exit(void) ++{ ++ platform_driver_unregister(&pb44_spi_drv); ++} ++module_exit(pb44_spi_exit); + -+ unsigned long quirk_wndr3700:1; - }; - - #endif /* _LINUX_ATH9K_PLATFORM_H */ -diff -Nur linux-2.6.35.7.orig/include/linux/gpio_buttons.h linux-2.6.35.7/include/linux/gpio_buttons.h ---- linux-2.6.35.7.orig/include/linux/gpio_buttons.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/include/linux/gpio_buttons.h 2010-10-14 20:28:01.679342332 +0200 -@@ -0,0 +1,33 @@ ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); +diff -Nur linux-2.6.36.orig/drivers/spi/spi_vsc7385.c linux-2.6.36/drivers/spi/spi_vsc7385.c +--- linux-2.6.36.orig/drivers/spi/spi_vsc7385.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/spi/spi_vsc7385.c 2010-11-18 21:16:15.000000000 +0100 +@@ -0,0 +1,620 @@ +/* -+ * Definitions for the GPIO buttons interface driver -+ * -+ * Copyright (C) 2007-2010 Gabor Juhos ++ * SPI driver for the Vitesse VSC7385 ethernet switch + * -+ * This file was based on: /include/linux/gpio_keys.h -+ * The original gpio_keys.h seems not to have a license. ++ * Copyright (C) 2009 Gabor Juhos + * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License version 2 as -+ * published by the Free Software Foundation. ++ * Parts of this file are based on Atheros' 2.6.15 BSP + * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ + -+#ifndef _GPIO_BUTTONS_H_ -+#define _GPIO_BUTTONS_H_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+struct gpio_button { -+ int gpio; /* GPIO line number */ -+ int active_low; -+ char *desc; /* button description */ -+ int type; /* input event type (EV_KEY, EV_SW) */ -+ int code; /* input event code (KEY_*, SW_*) */ -+ int threshold; /* count threshold */ -+}; ++#define DRV_NAME "spi-vsc7385" ++#define DRV_DESC "Vitesse VSC7385 Gbit ethernet switch driver" ++#define DRV_VERSION "0.1.0" + -+struct gpio_buttons_platform_data { -+ struct gpio_button *buttons; -+ int nbuttons; /* number of buttons */ -+ int poll_interval; /* polling interval */ -+}; ++#define VSC73XX_BLOCK_MAC 0x1 ++#define VSC73XX_BLOCK_2 0x2 ++#define VSC73XX_BLOCK_MII 0x3 ++#define VSC73XX_BLOCK_4 0x4 ++#define VSC73XX_BLOCK_5 0x5 ++#define VSC73XX_BLOCK_SYSTEM 0x7 + -+#endif /* _GPIO_BUTTONS_H_ */ -diff -Nur linux-2.6.35.7.orig/include/linux/gpio_dev.h linux-2.6.35.7/include/linux/gpio_dev.h ---- linux-2.6.35.7.orig/include/linux/gpio_dev.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/include/linux/gpio_dev.h 2010-10-14 20:28:01.715601023 +0200 -@@ -0,0 +1,11 @@ -+#ifndef _GPIODEV_H__ -+#define _GPIODEV_H__ ++#define VSC73XX_SUBBLOCK_PORT_0 0 ++#define VSC73XX_SUBBLOCK_PORT_1 1 ++#define VSC73XX_SUBBLOCK_PORT_2 2 ++#define VSC73XX_SUBBLOCK_PORT_3 3 ++#define VSC73XX_SUBBLOCK_PORT_4 4 ++#define VSC73XX_SUBBLOCK_PORT_MAC 6 + -+#define IOC_GPIODEV_MAGIC 'B' -+#define GPIO_GET _IO(IOC_GPIODEV_MAGIC, 10) -+#define GPIO_SET _IO(IOC_GPIODEV_MAGIC, 11) -+#define GPIO_CLEAR _IO(IOC_GPIODEV_MAGIC, 12) -+#define GPIO_DIR_IN _IO(IOC_GPIODEV_MAGIC, 13) -+#define GPIO_DIR_OUT _IO(IOC_GPIODEV_MAGIC, 14) ++/* MAC Block registers */ ++#define VSC73XX_MAC_CFG 0x0 ++#define VSC73XX_ADVPORTM 0x19 ++#define VSC73XX_RXOCT 0x50 ++#define VSC73XX_TXOCT 0x51 ++#define VSC73XX_C_RX0 0x52 ++#define VSC73XX_C_RX1 0x53 ++#define VSC73XX_C_RX2 0x54 ++#define VSC73XX_C_TX0 0x55 ++#define VSC73XX_C_TX1 0x56 ++#define VSC73XX_C_TX2 0x57 ++#define VSC73XX_C_CFG 0x58 + -+#endif -diff -Nur linux-2.6.35.7.orig/include/linux/netdevice.h linux-2.6.35.7/include/linux/netdevice.h ---- linux-2.6.35.7.orig/include/linux/netdevice.h 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/include/linux/netdevice.h 2010-10-14 20:28:01.758101230 +0200 -@@ -932,6 +932,7 @@ - void *ax25_ptr; /* AX.25 specific data */ - struct wireless_dev *ieee80211_ptr; /* IEEE 802.11 specific data, - assign before registering */ -+ void *phy_ptr; /* PHY device specific data */ - - /* - * Cache line mostly used on receive path (including eth_type_trans()) -diff -Nur linux-2.6.35.7.orig/include/linux/netdevice.h.orig linux-2.6.35.7/include/linux/netdevice.h.orig ---- linux-2.6.35.7.orig/include/linux/netdevice.h.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/include/linux/netdevice.h.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,2349 @@ -+/* -+ * INET An implementation of the TCP/IP protocol suite for the LINUX -+ * operating system. INET is implemented using the BSD Socket -+ * interface as the means of communication with the user level. -+ * -+ * Definitions for the Interfaces handler. -+ * -+ * Version: @(#)dev.h 1.0.10 08/12/93 -+ * -+ * Authors: Ross Biro -+ * Fred N. van Kempen, -+ * Corey Minyard -+ * Donald J. Becker, -+ * Alan Cox, -+ * Bjorn Ekwall. -+ * Pekka Riikonen -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License -+ * as published by the Free Software Foundation; either version -+ * 2 of the License, or (at your option) any later version. -+ * -+ * Moved to /usr/include/linux for NET3 -+ */ -+#ifndef _LINUX_NETDEVICE_H -+#define _LINUX_NETDEVICE_H ++/* MAC_CFG register bits */ ++#define VSC73XX_MAC_CFG_WEXC_DIS (1 << 31) ++#define VSC73XX_MAC_CFG_PORT_RST (1 << 29) ++#define VSC73XX_MAC_CFG_TX_EN (1 << 28) ++#define VSC73XX_MAC_CFG_SEED_LOAD (1 << 27) ++#define VSC73XX_MAC_CFG_FDX (1 << 18) ++#define VSC73XX_MAC_CFG_GIGE (1 << 17) ++#define VSC73XX_MAC_CFG_RX_EN (1 << 16) ++#define VSC73XX_MAC_CFG_VLAN_DBLAWR (1 << 15) ++#define VSC73XX_MAC_CFG_VLAN_AWR (1 << 14) ++#define VSC73XX_MAC_CFG_100_BASE_T (1 << 13) ++#define VSC73XX_MAC_CFG_TX_IPG(x) (((x) & 0x1f) << 6) ++#define VSC73XX_MAC_CFG_MAC_RX_RST (1 << 5) ++#define VSC73XX_MAC_CFG_MAC_TX_RST (1 << 4) ++#define VSC73XX_MAC_CFG_BIT2 (1 << 2) ++#define VSC73XX_MAC_CFG_CLK_SEL(x) ((x) & 0x3) + -+#include -+#include -+#include -+#include ++/* ADVPORTM register bits */ ++#define VSC73XX_ADVPORTM_IFG_PPM (1 << 7) ++#define VSC73XX_ADVPORTM_EXC_COL_CONT (1 << 6) ++#define VSC73XX_ADVPORTM_EXT_PORT (1 << 5) ++#define VSC73XX_ADVPORTM_INV_GTX (1 << 4) ++#define VSC73XX_ADVPORTM_ENA_GTX (1 << 3) ++#define VSC73XX_ADVPORTM_DDR_MODE (1 << 2) ++#define VSC73XX_ADVPORTM_IO_LOOPBACK (1 << 1) ++#define VSC73XX_ADVPORTM_HOST_LOOPBACK (1 << 0) + -+#ifdef __KERNEL__ -+#include -+#include -+#include -+#include -+#include -+#include -+#include ++/* MII Block registers */ ++#define VSC73XX_MII_STAT 0x0 ++#define VSC73XX_MII_CMD 0x1 ++#define VSC73XX_MII_DATA 0x2 + -+#include -+#include -+#include -+#include -+#include ++/* System Block registers */ ++#define VSC73XX_ICPU_SIPAD 0x01 ++#define VSC73XX_ICPU_CLOCK_DELAY 0x05 ++#define VSC73XX_ICPU_CTRL 0x10 ++#define VSC73XX_ICPU_ADDR 0x11 ++#define VSC73XX_ICPU_SRAM 0x12 ++#define VSC73XX_ICPU_MBOX_VAL 0x15 ++#define VSC73XX_ICPU_MBOX_SET 0x16 ++#define VSC73XX_ICPU_MBOX_CLR 0x17 ++#define VSC73XX_ICPU_CHIPID 0x18 ++#define VSC73XX_ICPU_GPIO 0x34 + -+#include -+#include -+#include -+#ifdef CONFIG_DCB -+#include -+#endif ++#define VSC73XX_ICPU_CTRL_CLK_DIV (1 << 8) ++#define VSC73XX_ICPU_CTRL_SRST_HOLD (1 << 7) ++#define VSC73XX_ICPU_CTRL_BOOT_EN (1 << 3) ++#define VSC73XX_ICPU_CTRL_EXT_ACC_EN (1 << 2) ++#define VSC73XX_ICPU_CTRL_CLK_EN (1 << 1) ++#define VSC73XX_ICPU_CTRL_SRST (1 << 0) ++ ++#define VSC73XX_ICPU_CHIPID_ID_SHIFT 12 ++#define VSC73XX_ICPU_CHIPID_ID_MASK 0xffff ++#define VSC73XX_ICPU_CHIPID_REV_SHIFT 28 ++#define VSC73XX_ICPU_CHIPID_REV_MASK 0xf ++#define VSC73XX_ICPU_CHIPID_ID_7385 0x7385 ++#define VSC73XX_ICPU_CHIPID_ID_7395 0x7395 ++ ++#define VSC73XX_CMD_MODE_READ 0 ++#define VSC73XX_CMD_MODE_WRITE 1 ++#define VSC73XX_CMD_MODE_SHIFT 4 ++#define VSC73XX_CMD_BLOCK_SHIFT 5 ++#define VSC73XX_CMD_BLOCK_MASK 0x7 ++#define VSC73XX_CMD_SUBBLOCK_MASK 0xf + -+struct vlan_group; -+struct netpoll_info; -+/* 802.11 specific */ -+struct wireless_dev; -+ /* source back-compat hooks */ -+#define SET_ETHTOOL_OPS(netdev,ops) \ -+ ( (netdev)->ethtool_ops = (ops) ) ++#define VSC7385_CLOCK_DELAY ((3 << 4) | 3) ++#define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3) + -+#define HAVE_ALLOC_NETDEV /* feature macro: alloc_xxxdev -+ functions are available. */ -+#define HAVE_FREE_NETDEV /* free_netdev() */ -+#define HAVE_NETDEV_PRIV /* netdev_priv() */ ++#define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \ ++ VSC73XX_ICPU_CTRL_BOOT_EN | \ ++ VSC73XX_ICPU_CTRL_EXT_ACC_EN) + -+/* Backlog congestion levels */ -+#define NET_RX_SUCCESS 0 /* keep 'em coming, baby */ -+#define NET_RX_DROP 1 /* packet dropped */ ++#define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \ ++ VSC73XX_ICPU_CTRL_BOOT_EN | \ ++ VSC73XX_ICPU_CTRL_CLK_EN | \ ++ VSC73XX_ICPU_CTRL_SRST) + -+/* -+ * Transmit return codes: transmit return codes originate from three different -+ * namespaces: -+ * -+ * - qdisc return codes -+ * - driver transmit return codes -+ * - errno values -+ * -+ * Drivers are allowed to return any one of those in their hard_start_xmit() -+ * function. Real network devices commonly used with qdiscs should only return -+ * the driver transmit return codes though - when qdiscs are used, the actual -+ * transmission happens asynchronously, so the value is not propagated to -+ * higher layers. Virtual network devices transmit synchronously, in this case -+ * the driver transmit return codes are consumed by dev_queue_xmit(), all -+ * others are propagated to higher layers. -+ */ ++#define VSC7385_ADVPORTM_MASK (VSC73XX_ADVPORTM_IFG_PPM | \ ++ VSC73XX_ADVPORTM_EXC_COL_CONT | \ ++ VSC73XX_ADVPORTM_EXT_PORT | \ ++ VSC73XX_ADVPORTM_INV_GTX | \ ++ VSC73XX_ADVPORTM_ENA_GTX | \ ++ VSC73XX_ADVPORTM_DDR_MODE | \ ++ VSC73XX_ADVPORTM_IO_LOOPBACK | \ ++ VSC73XX_ADVPORTM_HOST_LOOPBACK) ++ ++#define VSC7385_ADVPORTM_INIT (VSC73XX_ADVPORTM_EXT_PORT | \ ++ VSC73XX_ADVPORTM_ENA_GTX | \ ++ VSC73XX_ADVPORTM_DDR_MODE) + -+/* qdisc ->enqueue() return codes. */ -+#define NET_XMIT_SUCCESS 0x00 -+#define NET_XMIT_DROP 0x01 /* skb dropped */ -+#define NET_XMIT_CN 0x02 /* congestion notification */ -+#define NET_XMIT_POLICED 0x03 /* skb is shot by police */ -+#define NET_XMIT_MASK 0x0f /* qdisc flags in net/sch_generic.h */ ++#define VSC7385_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \ ++ VSC73XX_MAC_CFG_MAC_RX_RST | \ ++ VSC73XX_MAC_CFG_MAC_TX_RST) + -+/* NET_XMIT_CN is special. It does not guarantee that this packet is lost. It -+ * indicates that the device will soon be dropping packets, or already drops -+ * some packets of the same priority; prompting us to send less aggressively. */ -+#define net_xmit_eval(e) ((e) == NET_XMIT_CN ? 0 : (e)) -+#define net_xmit_errno(e) ((e) != NET_XMIT_CN ? -ENOBUFS : 0) ++#define VSC73XX_MAC_CFG_INIT (VSC73XX_MAC_CFG_TX_EN | \ ++ VSC73XX_MAC_CFG_FDX | \ ++ VSC73XX_MAC_CFG_GIGE | \ ++ VSC73XX_MAC_CFG_RX_EN) + -+/* Driver transmit return codes */ -+#define NETDEV_TX_MASK 0xf0 ++#define VSC73XX_RESET_DELAY 100 + -+enum netdev_tx { -+ __NETDEV_TX_MIN = INT_MIN, /* make sure enum is signed */ -+ NETDEV_TX_OK = 0x00, /* driver took care of packet */ -+ NETDEV_TX_BUSY = 0x10, /* driver tx path was busy*/ -+ NETDEV_TX_LOCKED = 0x20, /* driver tx lock was already taken */ ++struct vsc7385 { ++ struct spi_device *spi; ++ struct mutex lock; ++ struct vsc7385_platform_data *pdata; +}; -+typedef enum netdev_tx netdev_tx_t; + -+/* -+ * Current order: NETDEV_TX_MASK > NET_XMIT_MASK >= 0 is significant; -+ * hard_start_xmit() return < NET_XMIT_MASK means skb was consumed. -+ */ -+static inline bool dev_xmit_complete(int rc) ++static int vsc7385_is_addr_valid(u8 block, u8 subblock) +{ -+ /* -+ * Positive cases with an skb consumed by a driver: -+ * - successful transmission (rc == NETDEV_TX_OK) -+ * - error while transmitting (rc < 0) -+ * - error while queueing to a different device (rc & NET_XMIT_MASK) -+ */ -+ if (likely(rc < NET_XMIT_MASK)) -+ return true; ++ switch (block) { ++ case VSC73XX_BLOCK_MAC: ++ switch (subblock) { ++ case 0 ... 4: ++ case 6: ++ return 1; ++ } ++ break; ++ ++ case VSC73XX_BLOCK_2: ++ case VSC73XX_BLOCK_SYSTEM: ++ switch (subblock) { ++ case 0: ++ return 1; ++ } ++ break; ++ ++ case VSC73XX_BLOCK_MII: ++ case VSC73XX_BLOCK_4: ++ case VSC73XX_BLOCK_5: ++ switch (subblock) { ++ case 0 ... 1: ++ return 1; ++ } ++ break; ++ } + -+ return false; ++ return 0; +} + -+#endif ++static inline u8 vsc7385_make_addr(u8 mode, u8 block, u8 subblock) ++{ ++ u8 ret; + -+#define MAX_ADDR_LEN 32 /* Largest hardware address length */ ++ ret = (block & VSC73XX_CMD_BLOCK_MASK) << VSC73XX_CMD_BLOCK_SHIFT; ++ ret |= (mode & 1) << VSC73XX_CMD_MODE_SHIFT; ++ ret |= subblock & VSC73XX_CMD_SUBBLOCK_MASK; + -+#ifdef __KERNEL__ -+/* -+ * Compute the worst case header length according to the protocols -+ * used. -+ */ ++ return ret; ++} + -+#if defined(CONFIG_WLAN) || defined(CONFIG_AX25) || defined(CONFIG_AX25_MODULE) -+# if defined(CONFIG_MAC80211_MESH) -+# define LL_MAX_HEADER 128 -+# else -+# define LL_MAX_HEADER 96 -+# endif -+#elif defined(CONFIG_TR) || defined(CONFIG_TR_MODULE) -+# define LL_MAX_HEADER 48 -+#else -+# define LL_MAX_HEADER 32 -+#endif ++static int vsc7385_read(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, ++ u32 *value) ++{ ++ u8 cmd[4]; ++ u8 buf[4]; ++ struct spi_transfer t[2]; ++ struct spi_message m; ++ int err; + -+#if !defined(CONFIG_NET_IPIP) && !defined(CONFIG_NET_IPIP_MODULE) && \ -+ !defined(CONFIG_NET_IPGRE) && !defined(CONFIG_NET_IPGRE_MODULE) && \ -+ !defined(CONFIG_IPV6_SIT) && !defined(CONFIG_IPV6_SIT_MODULE) && \ -+ !defined(CONFIG_IPV6_TUNNEL) && !defined(CONFIG_IPV6_TUNNEL_MODULE) -+#define MAX_HEADER LL_MAX_HEADER -+#else -+#define MAX_HEADER (LL_MAX_HEADER + 48) -+#endif ++ if (!vsc7385_is_addr_valid(block, subblock)) ++ return -EINVAL; + -+#endif /* __KERNEL__ */ ++ spi_message_init(&m); + -+/* -+ * Network device statistics. Akin to the 2.0 ether stats but -+ * with byte counters. -+ */ ++ memset(&t, 0, sizeof(t)); + -+struct net_device_stats { -+ unsigned long rx_packets; /* total packets received */ -+ unsigned long tx_packets; /* total packets transmitted */ -+ unsigned long rx_bytes; /* total bytes received */ -+ unsigned long tx_bytes; /* total bytes transmitted */ -+ unsigned long rx_errors; /* bad packets received */ -+ unsigned long tx_errors; /* packet transmit problems */ -+ unsigned long rx_dropped; /* no space in linux buffers */ -+ unsigned long tx_dropped; /* no space available in linux */ -+ unsigned long multicast; /* multicast packets received */ -+ unsigned long collisions; -+ -+ /* detailed rx_errors: */ -+ unsigned long rx_length_errors; -+ unsigned long rx_over_errors; /* receiver ring buff overflow */ -+ unsigned long rx_crc_errors; /* recved pkt with crc error */ -+ unsigned long rx_frame_errors; /* recv'd frame alignment error */ -+ unsigned long rx_fifo_errors; /* recv'r fifo overrun */ -+ unsigned long rx_missed_errors; /* receiver missed packet */ -+ -+ /* detailed tx_errors */ -+ unsigned long tx_aborted_errors; -+ unsigned long tx_carrier_errors; -+ unsigned long tx_fifo_errors; -+ unsigned long tx_heartbeat_errors; -+ unsigned long tx_window_errors; -+ -+ /* for cslip etc */ -+ unsigned long rx_compressed; -+ unsigned long tx_compressed; -+}; ++ t[0].tx_buf = cmd; ++ t[0].len = sizeof(cmd); ++ spi_message_add_tail(&t[0], &m); ++ ++ t[1].rx_buf = buf; ++ t[1].len = sizeof(buf); ++ spi_message_add_tail(&t[1], &m); + ++ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_READ, block, subblock); ++ cmd[1] = reg; ++ cmd[2] = 0; ++ cmd[3] = 0; + -+/* Media selection options. */ -+enum { -+ IF_PORT_UNKNOWN = 0, -+ IF_PORT_10BASE2, -+ IF_PORT_10BASET, -+ IF_PORT_AUI, -+ IF_PORT_100BASET, -+ IF_PORT_100BASETX, -+ IF_PORT_100BASEFX -+}; ++ mutex_lock(&vsc->lock); ++ err = spi_sync(vsc->spi, &m); ++ mutex_unlock(&vsc->lock); + -+#ifdef __KERNEL__ ++ if (err) ++ return err; + -+#include -+#include ++ *value = (((u32) buf[0]) << 24) | (((u32) buf[1]) << 16) | ++ (((u32) buf[2]) << 8) | ((u32) buf[3]); + -+struct neighbour; -+struct neigh_parms; -+struct sk_buff; ++ return 0; ++} + -+struct netdev_hw_addr { -+ struct list_head list; -+ unsigned char addr[MAX_ADDR_LEN]; -+ unsigned char type; -+#define NETDEV_HW_ADDR_T_LAN 1 -+#define NETDEV_HW_ADDR_T_SAN 2 -+#define NETDEV_HW_ADDR_T_SLAVE 3 -+#define NETDEV_HW_ADDR_T_UNICAST 4 -+#define NETDEV_HW_ADDR_T_MULTICAST 5 -+ int refcount; -+ bool synced; -+ bool global_use; -+ struct rcu_head rcu_head; -+}; -+ -+struct netdev_hw_addr_list { -+ struct list_head list; -+ int count; -+}; + -+#define netdev_hw_addr_list_count(l) ((l)->count) -+#define netdev_hw_addr_list_empty(l) (netdev_hw_addr_list_count(l) == 0) -+#define netdev_hw_addr_list_for_each(ha, l) \ -+ list_for_each_entry(ha, &(l)->list, list) ++static int vsc7385_write(struct vsc7385 *vsc, u8 block, u8 subblock, u8 reg, ++ u32 value) ++{ ++ u8 cmd[2]; ++ u8 buf[4]; ++ struct spi_transfer t[2]; ++ struct spi_message m; ++ int err; + -+#define netdev_uc_count(dev) netdev_hw_addr_list_count(&(dev)->uc) -+#define netdev_uc_empty(dev) netdev_hw_addr_list_empty(&(dev)->uc) -+#define netdev_for_each_uc_addr(ha, dev) \ -+ netdev_hw_addr_list_for_each(ha, &(dev)->uc) ++ if (!vsc7385_is_addr_valid(block, subblock)) ++ return -EINVAL; + -+#define netdev_mc_count(dev) netdev_hw_addr_list_count(&(dev)->mc) -+#define netdev_mc_empty(dev) netdev_hw_addr_list_empty(&(dev)->mc) -+#define netdev_for_each_mc_addr(ha, dev) \ -+ netdev_hw_addr_list_for_each(ha, &(dev)->mc) ++ spi_message_init(&m); + -+struct hh_cache { -+ struct hh_cache *hh_next; /* Next entry */ -+ atomic_t hh_refcnt; /* number of users */ -+/* -+ * We want hh_output, hh_len, hh_lock and hh_data be a in a separate -+ * cache line on SMP. -+ * They are mostly read, but hh_refcnt may be changed quite frequently, -+ * incurring cache line ping pongs. -+ */ -+ __be16 hh_type ____cacheline_aligned_in_smp; -+ /* protocol identifier, f.e ETH_P_IP -+ * NOTE: For VLANs, this will be the -+ * encapuslated type. --BLG -+ */ -+ u16 hh_len; /* length of header */ -+ int (*hh_output)(struct sk_buff *skb); -+ seqlock_t hh_lock; -+ -+ /* cached hardware header; allow for machine alignment needs. */ -+#define HH_DATA_MOD 16 -+#define HH_DATA_OFF(__len) \ -+ (HH_DATA_MOD - (((__len - 1) & (HH_DATA_MOD - 1)) + 1)) -+#define HH_DATA_ALIGN(__len) \ -+ (((__len)+(HH_DATA_MOD-1))&~(HH_DATA_MOD - 1)) -+ unsigned long hh_data[HH_DATA_ALIGN(LL_MAX_HEADER) / sizeof(long)]; -+}; -+ -+/* Reserve HH_DATA_MOD byte aligned hard_header_len, but at least that much. -+ * Alternative is: -+ * dev->hard_header_len ? (dev->hard_header_len + -+ * (HH_DATA_MOD - 1)) & ~(HH_DATA_MOD - 1) : 0 -+ * -+ * We could use other alignment values, but we must maintain the -+ * relationship HH alignment <= LL alignment. -+ * -+ * LL_ALLOCATED_SPACE also takes into account the tailroom the device -+ * may need. -+ */ -+#define LL_RESERVED_SPACE(dev) \ -+ ((((dev)->hard_header_len+(dev)->needed_headroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) -+#define LL_RESERVED_SPACE_EXTRA(dev,extra) \ -+ ((((dev)->hard_header_len+(dev)->needed_headroom+(extra))&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) -+#define LL_ALLOCATED_SPACE(dev) \ -+ ((((dev)->hard_header_len+(dev)->needed_headroom+(dev)->needed_tailroom)&~(HH_DATA_MOD - 1)) + HH_DATA_MOD) -+ -+struct header_ops { -+ int (*create) (struct sk_buff *skb, struct net_device *dev, -+ unsigned short type, const void *daddr, -+ const void *saddr, unsigned len); -+ int (*parse)(const struct sk_buff *skb, unsigned char *haddr); -+ int (*rebuild)(struct sk_buff *skb); -+#define HAVE_HEADER_CACHE -+ int (*cache)(const struct neighbour *neigh, struct hh_cache *hh); -+ void (*cache_update)(struct hh_cache *hh, -+ const struct net_device *dev, -+ const unsigned char *haddr); -+}; -+ -+/* These flag bits are private to the generic network queueing -+ * layer, they may not be explicitly referenced by any other -+ * code. -+ */ ++ memset(&t, 0, sizeof(t)); + -+enum netdev_state_t { -+ __LINK_STATE_START, -+ __LINK_STATE_PRESENT, -+ __LINK_STATE_NOCARRIER, -+ __LINK_STATE_LINKWATCH_PENDING, -+ __LINK_STATE_DORMANT, -+}; ++ t[0].tx_buf = cmd; ++ t[0].len = sizeof(cmd); ++ spi_message_add_tail(&t[0], &m); + ++ t[1].tx_buf = buf; ++ t[1].len = sizeof(buf); ++ spi_message_add_tail(&t[1], &m); + -+/* -+ * This structure holds at boot time configured netdevice settings. They -+ * are then used in the device probing. -+ */ -+struct netdev_boot_setup { -+ char name[IFNAMSIZ]; -+ struct ifmap map; -+}; -+#define NETDEV_BOOT_SETUP_MAX 8 ++ cmd[0] = vsc7385_make_addr(VSC73XX_CMD_MODE_WRITE, block, subblock); ++ cmd[1] = reg; + -+extern int __init netdev_boot_setup(char *str); ++ buf[0] = (value >> 24) & 0xff; ++ buf[1] = (value >> 16) & 0xff; ++ buf[2] = (value >> 8) & 0xff; ++ buf[3] = value & 0xff; + -+/* -+ * Structure for NAPI scheduling similar to tasklet but with weighting -+ */ -+struct napi_struct { -+ /* The poll_list must only be managed by the entity which -+ * changes the state of the NAPI_STATE_SCHED bit. This means -+ * whoever atomically sets that bit can add this napi_struct -+ * to the per-cpu poll_list, and whoever clears that bit -+ * can remove from the list right before clearing the bit. -+ */ -+ struct list_head poll_list; -+ -+ unsigned long state; -+ int weight; -+ int (*poll)(struct napi_struct *, int); -+#ifdef CONFIG_NETPOLL -+ spinlock_t poll_lock; -+ int poll_owner; -+#endif ++ mutex_lock(&vsc->lock); ++ err = spi_sync(vsc->spi, &m); ++ mutex_unlock(&vsc->lock); + -+ unsigned int gro_count; ++ return err; ++} + -+ struct net_device *dev; -+ struct list_head dev_list; -+ struct sk_buff *gro_list; -+ struct sk_buff *skb; -+}; ++static inline int vsc7385_write_verify(struct vsc7385 *vsc, u8 block, ++ u8 subblock, u8 reg, u32 value, ++ u32 read_mask, u32 read_val) ++{ ++ struct spi_device *spi = vsc->spi; ++ u32 t; ++ int err; + -+enum { -+ NAPI_STATE_SCHED, /* Poll is scheduled */ -+ NAPI_STATE_DISABLE, /* Disable pending */ -+ NAPI_STATE_NPSVC, /* Netpoll - don't dequeue from poll_list */ -+}; ++ err = vsc7385_write(vsc, block, subblock, reg, value); ++ if (err) ++ return err; + -+enum gro_result { -+ GRO_MERGED, -+ GRO_MERGED_FREE, -+ GRO_HELD, -+ GRO_NORMAL, -+ GRO_DROP, -+}; -+typedef enum gro_result gro_result_t; ++ err = vsc7385_read(vsc, block, subblock, reg, &t); ++ if (err) ++ return err; + -+extern void __napi_schedule(struct napi_struct *n); ++ if ((t & read_mask) != read_val) { ++ dev_err(&spi->dev, "register write error\n"); ++ return -EIO; ++ } + -+static inline int napi_disable_pending(struct napi_struct *n) -+{ -+ return test_bit(NAPI_STATE_DISABLE, &n->state); ++ return 0; +} + -+/** -+ * napi_schedule_prep - check if napi can be scheduled -+ * @n: napi context -+ * -+ * Test if NAPI routine is already running, and if not mark -+ * it as running. This is used as a condition variable -+ * insure only one NAPI poll instance runs. We also make -+ * sure there is no pending NAPI disable. -+ */ -+static inline int napi_schedule_prep(struct napi_struct *n) ++static inline int vsc7385_set_clock_delay(struct vsc7385 *vsc, u32 val) +{ -+ return !napi_disable_pending(n) && -+ !test_and_set_bit(NAPI_STATE_SCHED, &n->state); ++ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_CLOCK_DELAY, val); +} + -+/** -+ * napi_schedule - schedule NAPI poll -+ * @n: napi context -+ * -+ * Schedule NAPI poll routine to be called if it is not already -+ * running. -+ */ -+static inline void napi_schedule(struct napi_struct *n) ++static inline int vsc7385_get_clock_delay(struct vsc7385 *vsc, u32 *val) +{ -+ if (napi_schedule_prep(n)) -+ __napi_schedule(n); ++ return vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_CLOCK_DELAY, val); +} + -+/* Try to reschedule poll. Called by dev->poll() after napi_complete(). */ -+static inline int napi_reschedule(struct napi_struct *napi) ++static inline int vsc7385_icpu_stop(struct vsc7385 *vsc) +{ -+ if (napi_schedule_prep(napi)) { -+ __napi_schedule(napi); -+ return 1; -+ } -+ return 0; ++ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, ++ VSC73XX_ICPU_CTRL_STOP); +} + -+/** -+ * napi_complete - NAPI processing complete -+ * @n: napi context -+ * -+ * Mark NAPI processing as complete. -+ */ -+extern void __napi_complete(struct napi_struct *n); -+extern void napi_complete(struct napi_struct *n); -+ -+/** -+ * napi_disable - prevent NAPI from scheduling -+ * @n: napi context -+ * -+ * Stop NAPI from being scheduled on this context. -+ * Waits till any outstanding processing completes. -+ */ -+static inline void napi_disable(struct napi_struct *n) ++static inline int vsc7385_icpu_start(struct vsc7385 *vsc) +{ -+ set_bit(NAPI_STATE_DISABLE, &n->state); -+ while (test_and_set_bit(NAPI_STATE_SCHED, &n->state)) -+ msleep(1); -+ clear_bit(NAPI_STATE_DISABLE, &n->state); ++ return vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_CTRL, ++ VSC73XX_ICPU_CTRL_START); +} + -+/** -+ * napi_enable - enable NAPI scheduling -+ * @n: napi context -+ * -+ * Resume NAPI from being scheduled on this context. -+ * Must be paired with napi_disable. -+ */ -+static inline void napi_enable(struct napi_struct *n) ++static inline int vsc7385_icpu_reset(struct vsc7385 *vsc) +{ -+ BUG_ON(!test_bit(NAPI_STATE_SCHED, &n->state)); -+ smp_mb__before_clear_bit(); -+ clear_bit(NAPI_STATE_SCHED, &n->state); ++ int rc; ++ ++ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_ICPU_ADDR, ++ 0x0000); ++ if (rc) ++ dev_err(&vsc->spi->dev, ++ "could not reset microcode, err=%d\n", rc); ++ ++ return rc; +} + -+#ifdef CONFIG_SMP -+/** -+ * napi_synchronize - wait until NAPI is not running -+ * @n: napi context -+ * -+ * Wait until NAPI is done being scheduled on this context. -+ * Waits till any outstanding processing completes but -+ * does not disable future activations. -+ */ -+static inline void napi_synchronize(const struct napi_struct *n) ++static int vsc7385_upload_ucode(struct vsc7385 *vsc) +{ -+ while (test_bit(NAPI_STATE_SCHED, &n->state)) -+ msleep(1); -+} -+#else -+# define napi_synchronize(n) barrier() -+#endif ++ struct spi_device *spi = vsc->spi; ++ const struct firmware *firmware; ++ char *ucode_name; ++ unsigned char *dp; ++ unsigned int curVal; ++ int i; ++ int diffs; ++ int rc; ++ ++ ucode_name = (vsc->pdata->ucode_name) ? vsc->pdata->ucode_name ++ : "vsc7385_ucode.bin"; ++ rc = request_firmware(&firmware, ucode_name, &spi->dev); ++ if (rc) { ++ dev_err(&spi->dev, "request_firmware failed, err=%d\n", ++ rc); ++ return rc; ++ } ++ ++ rc = vsc7385_icpu_stop(vsc); ++ if (rc) ++ goto out; + -+enum netdev_queue_state_t { -+ __QUEUE_STATE_XOFF, -+ __QUEUE_STATE_FROZEN, -+}; ++ rc = vsc7385_icpu_reset(vsc); ++ if (rc) ++ goto out; + -+struct netdev_queue { -+/* -+ * read mostly part -+ */ -+ struct net_device *dev; -+ struct Qdisc *qdisc; -+ unsigned long state; -+ struct Qdisc *qdisc_sleeping; -+/* -+ * write mostly part -+ */ -+ spinlock_t _xmit_lock ____cacheline_aligned_in_smp; -+ int xmit_lock_owner; -+ /* -+ * please use this field instead of dev->trans_start -+ */ -+ unsigned long trans_start; -+ unsigned long tx_bytes; -+ unsigned long tx_packets; -+ unsigned long tx_dropped; -+} ____cacheline_aligned_in_smp; ++ dev_info(&spi->dev, "uploading microcode...\n"); + -+#ifdef CONFIG_RPS -+/* -+ * This structure holds an RPS map which can be of variable length. The -+ * map is an array of CPUs. -+ */ -+struct rps_map { -+ unsigned int len; -+ struct rcu_head rcu; -+ u16 cpus[0]; -+}; -+#define RPS_MAP_SIZE(_num) (sizeof(struct rps_map) + (_num * sizeof(u16))) ++ dp = (unsigned char *) firmware->data; ++ for (i = 0; i < firmware->size; i++) { ++ rc = vsc7385_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_SRAM, *dp++); ++ if (rc) { ++ dev_err(&spi->dev, "could not load microcode, err=%d\n", ++ rc); ++ goto out; ++ } ++ } + -+/* -+ * The rps_dev_flow structure contains the mapping of a flow to a CPU and the -+ * tail pointer for that CPU's input queue at the time of last enqueue. -+ */ -+struct rps_dev_flow { -+ u16 cpu; -+ u16 fill; -+ unsigned int last_qtail; -+}; ++ rc = vsc7385_icpu_reset(vsc); ++ if (rc) ++ goto out; + -+/* -+ * The rps_dev_flow_table structure contains a table of flow mappings. -+ */ -+struct rps_dev_flow_table { -+ unsigned int mask; -+ struct rcu_head rcu; -+ struct work_struct free_work; -+ struct rps_dev_flow flows[0]; -+}; -+#define RPS_DEV_FLOW_TABLE_SIZE(_num) (sizeof(struct rps_dev_flow_table) + \ -+ (_num * sizeof(struct rps_dev_flow))) ++ dev_info(&spi->dev, "verifying microcode...\n"); + -+/* -+ * The rps_sock_flow_table contains mappings of flows to the last CPU -+ * on which they were processed by the application (set in recvmsg). -+ */ -+struct rps_sock_flow_table { -+ unsigned int mask; -+ u16 ents[0]; -+}; -+#define RPS_SOCK_FLOW_TABLE_SIZE(_num) (sizeof(struct rps_sock_flow_table) + \ -+ (_num * sizeof(u16))) ++ dp = (unsigned char *) firmware->data; ++ diffs = 0; ++ for (i = 0; i < firmware->size; i++) { ++ rc = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_SRAM, &curVal); ++ if (rc) { ++ dev_err(&spi->dev, "could not read microcode %d\n",rc); ++ goto out; ++ } + -+#define RPS_NO_CPU 0xffff ++ if (curVal > 0xff) { ++ dev_err(&spi->dev, "bad val read: %04x : %02x %02x\n", ++ i, *dp, curVal); ++ rc = -EIO; ++ goto out; ++ } + -+static inline void rps_record_sock_flow(struct rps_sock_flow_table *table, -+ u32 hash) -+{ -+ if (table && hash) { -+ unsigned int cpu, index = hash & table->mask; ++ if ((curVal & 0xff) != *dp) { ++ diffs++; ++ dev_err(&spi->dev, "verify error: %04x : %02x %02x\n", ++ i, *dp, curVal); + -+ /* We only give a hint, preemption can change cpu under us */ -+ cpu = raw_smp_processor_id(); ++ if (diffs > 4) ++ break; ++ } ++ dp++; ++ } + -+ if (table->ents[index] != cpu) -+ table->ents[index] = cpu; ++ if (diffs) { ++ dev_err(&spi->dev, "microcode verification failed\n"); ++ rc = -EIO; ++ goto out; + } ++ ++ dev_info(&spi->dev, "microcode uploaded\n"); ++ ++ rc = vsc7385_icpu_start(vsc); ++ ++ out: ++ release_firmware(firmware); ++ return rc; +} + -+static inline void rps_reset_sock_flow(struct rps_sock_flow_table *table, -+ u32 hash) ++static int vsc7385_setup(struct vsc7385 *vsc) +{ -+ if (table && hash) -+ table->ents[hash & table->mask] = RPS_NO_CPU; -+} ++ struct vsc7385_platform_data *pdata = vsc->pdata; ++ u32 t; ++ int err; + -+extern struct rps_sock_flow_table *rps_sock_flow_table; ++ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_CLOCK_DELAY, ++ VSC7385_CLOCK_DELAY, ++ VSC7385_CLOCK_DELAY_MASK, ++ VSC7385_CLOCK_DELAY); ++ if (err) ++ goto err; + -+/* This structure contains an instance of an RX queue. */ -+struct netdev_rx_queue { -+ struct rps_map *rps_map; -+ struct rps_dev_flow_table *rps_flow_table; -+ struct kobject kobj; -+ struct netdev_rx_queue *first; -+ atomic_t count; -+} ____cacheline_aligned_in_smp; -+#endif /* CONFIG_RPS */ ++ err = vsc7385_write_verify(vsc, VSC73XX_BLOCK_MAC, ++ VSC73XX_SUBBLOCK_PORT_MAC, VSC73XX_ADVPORTM, ++ VSC7385_ADVPORTM_INIT, ++ VSC7385_ADVPORTM_MASK, ++ VSC7385_ADVPORTM_INIT); ++ if (err) ++ goto err; + -+/* -+ * This structure defines the management hooks for network devices. -+ * The following hooks can be defined; unless noted otherwise, they are -+ * optional and can be filled with a null pointer. -+ * -+ * int (*ndo_init)(struct net_device *dev); -+ * This function is called once when network device is registered. -+ * The network device can use this to any late stage initializaton -+ * or semantic validattion. It can fail with an error code which will -+ * be propogated back to register_netdev -+ * -+ * void (*ndo_uninit)(struct net_device *dev); -+ * This function is called when device is unregistered or when registration -+ * fails. It is not called if init fails. -+ * -+ * int (*ndo_open)(struct net_device *dev); -+ * This function is called when network device transistions to the up -+ * state. -+ * -+ * int (*ndo_stop)(struct net_device *dev); -+ * This function is called when network device transistions to the down -+ * state. -+ * -+ * netdev_tx_t (*ndo_start_xmit)(struct sk_buff *skb, -+ * struct net_device *dev); -+ * Called when a packet needs to be transmitted. -+ * Must return NETDEV_TX_OK , NETDEV_TX_BUSY. -+ * (can also return NETDEV_TX_LOCKED iff NETIF_F_LLTX) -+ * Required can not be NULL. -+ * -+ * u16 (*ndo_select_queue)(struct net_device *dev, struct sk_buff *skb); -+ * Called to decide which queue to when device supports multiple -+ * transmit queues. -+ * -+ * void (*ndo_change_rx_flags)(struct net_device *dev, int flags); -+ * This function is called to allow device receiver to make -+ * changes to configuration when multicast or promiscious is enabled. -+ * -+ * void (*ndo_set_rx_mode)(struct net_device *dev); -+ * This function is called device changes address list filtering. -+ * -+ * void (*ndo_set_multicast_list)(struct net_device *dev); -+ * This function is called when the multicast address list changes. -+ * -+ * int (*ndo_set_mac_address)(struct net_device *dev, void *addr); -+ * This function is called when the Media Access Control address -+ * needs to be changed. If this interface is not defined, the -+ * mac address can not be changed. -+ * -+ * int (*ndo_validate_addr)(struct net_device *dev); -+ * Test if Media Access Control address is valid for the device. -+ * -+ * int (*ndo_do_ioctl)(struct net_device *dev, struct ifreq *ifr, int cmd); -+ * Called when a user request an ioctl which can't be handled by -+ * the generic interface code. If not defined ioctl's return -+ * not supported error code. -+ * -+ * int (*ndo_set_config)(struct net_device *dev, struct ifmap *map); -+ * Used to set network devices bus interface parameters. This interface -+ * is retained for legacy reason, new devices should use the bus -+ * interface (PCI) for low level management. -+ * -+ * int (*ndo_change_mtu)(struct net_device *dev, int new_mtu); -+ * Called when a user wants to change the Maximum Transfer Unit -+ * of a device. If not defined, any request to change MTU will -+ * will return an error. -+ * -+ * void (*ndo_tx_timeout)(struct net_device *dev); -+ * Callback uses when the transmitter has not made any progress -+ * for dev->watchdog ticks. -+ * -+ * struct net_device_stats* (*ndo_get_stats)(struct net_device *dev); -+ * Called when a user wants to get the network device usage -+ * statistics. If not defined, the counters in dev->stats will -+ * be used. -+ * -+ * void (*ndo_vlan_rx_register)(struct net_device *dev, struct vlan_group *grp); -+ * If device support VLAN receive accleration -+ * (ie. dev->features & NETIF_F_HW_VLAN_RX), then this function is called -+ * when vlan groups for the device changes. Note: grp is NULL -+ * if no vlan's groups are being used. -+ * -+ * void (*ndo_vlan_rx_add_vid)(struct net_device *dev, unsigned short vid); -+ * If device support VLAN filtering (dev->features & NETIF_F_HW_VLAN_FILTER) -+ * this function is called when a VLAN id is registered. -+ * -+ * void (*ndo_vlan_rx_kill_vid)(struct net_device *dev, unsigned short vid); -+ * If device support VLAN filtering (dev->features & NETIF_F_HW_VLAN_FILTER) -+ * this function is called when a VLAN id is unregistered. -+ * -+ * void (*ndo_poll_controller)(struct net_device *dev); -+ * -+ * SR-IOV management functions. -+ * int (*ndo_set_vf_mac)(struct net_device *dev, int vf, u8* mac); -+ * int (*ndo_set_vf_vlan)(struct net_device *dev, int vf, u16 vlan, u8 qos); -+ * int (*ndo_set_vf_tx_rate)(struct net_device *dev, int vf, int rate); -+ * int (*ndo_get_vf_config)(struct net_device *dev, -+ * int vf, struct ifla_vf_info *ivf); -+ * int (*ndo_set_vf_port)(struct net_device *dev, int vf, -+ * struct nlattr *port[]); -+ * int (*ndo_get_vf_port)(struct net_device *dev, int vf, struct sk_buff *skb); -+ */ -+#define HAVE_NET_DEVICE_OPS -+struct net_device_ops { -+ int (*ndo_init)(struct net_device *dev); -+ void (*ndo_uninit)(struct net_device *dev); -+ int (*ndo_open)(struct net_device *dev); -+ int (*ndo_stop)(struct net_device *dev); -+ netdev_tx_t (*ndo_start_xmit) (struct sk_buff *skb, -+ struct net_device *dev); -+ u16 (*ndo_select_queue)(struct net_device *dev, -+ struct sk_buff *skb); -+ void (*ndo_change_rx_flags)(struct net_device *dev, -+ int flags); -+ void (*ndo_set_rx_mode)(struct net_device *dev); -+ void (*ndo_set_multicast_list)(struct net_device *dev); -+ int (*ndo_set_mac_address)(struct net_device *dev, -+ void *addr); -+ int (*ndo_validate_addr)(struct net_device *dev); -+ int (*ndo_do_ioctl)(struct net_device *dev, -+ struct ifreq *ifr, int cmd); -+ int (*ndo_set_config)(struct net_device *dev, -+ struct ifmap *map); -+ int (*ndo_change_mtu)(struct net_device *dev, -+ int new_mtu); -+ int (*ndo_neigh_setup)(struct net_device *dev, -+ struct neigh_parms *); -+ void (*ndo_tx_timeout) (struct net_device *dev); -+ -+ struct net_device_stats* (*ndo_get_stats)(struct net_device *dev); -+ -+ void (*ndo_vlan_rx_register)(struct net_device *dev, -+ struct vlan_group *grp); -+ void (*ndo_vlan_rx_add_vid)(struct net_device *dev, -+ unsigned short vid); -+ void (*ndo_vlan_rx_kill_vid)(struct net_device *dev, -+ unsigned short vid); -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ void (*ndo_poll_controller)(struct net_device *dev); -+ void (*ndo_netpoll_cleanup)(struct net_device *dev); -+#endif -+ int (*ndo_set_vf_mac)(struct net_device *dev, -+ int queue, u8 *mac); -+ int (*ndo_set_vf_vlan)(struct net_device *dev, -+ int queue, u16 vlan, u8 qos); -+ int (*ndo_set_vf_tx_rate)(struct net_device *dev, -+ int vf, int rate); -+ int (*ndo_get_vf_config)(struct net_device *dev, -+ int vf, -+ struct ifla_vf_info *ivf); -+ int (*ndo_set_vf_port)(struct net_device *dev, -+ int vf, -+ struct nlattr *port[]); -+ int (*ndo_get_vf_port)(struct net_device *dev, -+ int vf, struct sk_buff *skb); -+#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) -+ int (*ndo_fcoe_enable)(struct net_device *dev); -+ int (*ndo_fcoe_disable)(struct net_device *dev); -+ int (*ndo_fcoe_ddp_setup)(struct net_device *dev, -+ u16 xid, -+ struct scatterlist *sgl, -+ unsigned int sgc); -+ int (*ndo_fcoe_ddp_done)(struct net_device *dev, -+ u16 xid); -+#define NETDEV_FCOE_WWNN 0 -+#define NETDEV_FCOE_WWPN 1 -+ int (*ndo_fcoe_get_wwn)(struct net_device *dev, -+ u64 *wwn, int type); -+#endif -+}; ++ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, ++ VSC73XX_MAC_CFG, VSC7385_MAC_CFG_RESET); ++ if (err) ++ goto err; + -+/* -+ * The DEVICE structure. -+ * Actually, this whole structure is a big mistake. It mixes I/O -+ * data with strictly "high-level" data, and it has to know about -+ * almost every data structure used in the INET module. -+ * -+ * FIXME: cleanup struct net_device such that network protocol info -+ * moves out. -+ */ ++ t = VSC73XX_MAC_CFG_INIT; ++ t |= VSC73XX_MAC_CFG_TX_IPG(pdata->mac_cfg.tx_ipg); ++ t |= VSC73XX_MAC_CFG_CLK_SEL(pdata->mac_cfg.clk_sel); ++ if (pdata->mac_cfg.bit2) ++ t |= VSC73XX_MAC_CFG_BIT2; + -+struct net_device { ++ err = vsc7385_write(vsc, VSC73XX_BLOCK_MAC, VSC73XX_SUBBLOCK_PORT_MAC, ++ VSC73XX_MAC_CFG, t); ++ if (err) ++ goto err; + -+ /* -+ * This is the first field of the "visible" part of this structure -+ * (i.e. as seen by users in the "Space.c" file). It is the name -+ * the interface. -+ */ -+ char name[IFNAMSIZ]; ++ return 0; + -+ struct pm_qos_request_list *pm_qos_req; ++ err: ++ return err; ++} + -+ /* device name hash chain */ -+ struct hlist_node name_hlist; -+ /* snmp alias */ -+ char *ifalias; ++static int vsc7385_detect(struct vsc7385 *vsc) ++{ ++ struct spi_device *spi = vsc->spi; ++ u32 t; ++ u32 id; ++ u32 rev; ++ int err; + -+ /* -+ * I/O specific fields -+ * FIXME: Merge these and struct ifmap into one -+ */ -+ unsigned long mem_end; /* shared mem end */ -+ unsigned long mem_start; /* shared mem start */ -+ unsigned long base_addr; /* device I/O address */ -+ unsigned int irq; /* device IRQ number */ ++ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_MBOX_VAL, &t); ++ if (err) { ++ dev_err(&spi->dev, "unable to read mailbox, err=%d\n", err); ++ return err; ++ } + -+ /* -+ * Some hardware also needs these fields, but they are not -+ * part of the usual set specified in Space.c. -+ */ ++ if (t == 0xffffffff) { ++ dev_dbg(&spi->dev, "assert chip reset\n"); ++ if (vsc->pdata->reset) ++ vsc->pdata->reset(); + -+ unsigned char if_port; /* Selectable AUI, TP,..*/ -+ unsigned char dma; /* DMA channel */ -+ -+ unsigned long state; -+ -+ struct list_head dev_list; -+ struct list_head napi_list; -+ struct list_head unreg_list; -+ -+ /* Net device features */ -+ unsigned long features; -+#define NETIF_F_SG 1 /* Scatter/gather IO. */ -+#define NETIF_F_IP_CSUM 2 /* Can checksum TCP/UDP over IPv4. */ -+#define NETIF_F_NO_CSUM 4 /* Does not require checksum. F.e. loopack. */ -+#define NETIF_F_HW_CSUM 8 /* Can checksum all the packets. */ -+#define NETIF_F_IPV6_CSUM 16 /* Can checksum TCP/UDP over IPV6 */ -+#define NETIF_F_HIGHDMA 32 /* Can DMA to high memory. */ -+#define NETIF_F_FRAGLIST 64 /* Scatter/gather IO. */ -+#define NETIF_F_HW_VLAN_TX 128 /* Transmit VLAN hw acceleration */ -+#define NETIF_F_HW_VLAN_RX 256 /* Receive VLAN hw acceleration */ -+#define NETIF_F_HW_VLAN_FILTER 512 /* Receive filtering on VLAN */ -+#define NETIF_F_VLAN_CHALLENGED 1024 /* Device cannot handle VLAN packets */ -+#define NETIF_F_GSO 2048 /* Enable software GSO. */ -+#define NETIF_F_LLTX 4096 /* LockLess TX - deprecated. Please */ -+ /* do not use LLTX in new drivers */ -+#define NETIF_F_NETNS_LOCAL 8192 /* Does not change network namespaces */ -+#define NETIF_F_GRO 16384 /* Generic receive offload */ -+#define NETIF_F_LRO 32768 /* large receive offload */ -+ -+/* the GSO_MASK reserves bits 16 through 23 */ -+#define NETIF_F_FCOE_CRC (1 << 24) /* FCoE CRC32 */ -+#define NETIF_F_SCTP_CSUM (1 << 25) /* SCTP checksum offload */ -+#define NETIF_F_FCOE_MTU (1 << 26) /* Supports max FCoE MTU, 2158 bytes*/ -+#define NETIF_F_NTUPLE (1 << 27) /* N-tuple filters supported */ -+#define NETIF_F_RXHASH (1 << 28) /* Receive hashing offload */ -+ -+ /* Segmentation offload features */ -+#define NETIF_F_GSO_SHIFT 16 -+#define NETIF_F_GSO_MASK 0x00ff0000 -+#define NETIF_F_TSO (SKB_GSO_TCPV4 << NETIF_F_GSO_SHIFT) -+#define NETIF_F_UFO (SKB_GSO_UDP << NETIF_F_GSO_SHIFT) -+#define NETIF_F_GSO_ROBUST (SKB_GSO_DODGY << NETIF_F_GSO_SHIFT) -+#define NETIF_F_TSO_ECN (SKB_GSO_TCP_ECN << NETIF_F_GSO_SHIFT) -+#define NETIF_F_TSO6 (SKB_GSO_TCPV6 << NETIF_F_GSO_SHIFT) -+#define NETIF_F_FSO (SKB_GSO_FCOE << NETIF_F_GSO_SHIFT) -+ -+ /* List of features with software fallbacks. */ -+#define NETIF_F_GSO_SOFTWARE (NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6) -+ -+ -+#define NETIF_F_GEN_CSUM (NETIF_F_NO_CSUM | NETIF_F_HW_CSUM) -+#define NETIF_F_V4_CSUM (NETIF_F_GEN_CSUM | NETIF_F_IP_CSUM) -+#define NETIF_F_V6_CSUM (NETIF_F_GEN_CSUM | NETIF_F_IPV6_CSUM) -+#define NETIF_F_ALL_CSUM (NETIF_F_V4_CSUM | NETIF_F_V6_CSUM) ++ } + -+ /* -+ * If one device supports one of these features, then enable them -+ * for all in netdev_increment_features. -+ */ -+#define NETIF_F_ONE_FOR_ALL (NETIF_F_GSO_SOFTWARE | NETIF_F_GSO_ROBUST | \ -+ NETIF_F_SG | NETIF_F_HIGHDMA | \ -+ NETIF_F_FRAGLIST) -+ -+ /* Interface index. Unique device identifier */ -+ int ifindex; -+ int iflink; -+ -+ struct net_device_stats stats; -+ -+#ifdef CONFIG_WIRELESS_EXT -+ /* List of functions to handle Wireless Extensions (instead of ioctl). -+ * See for details. Jean II */ -+ const struct iw_handler_def * wireless_handlers; -+ /* Instance data managed by the core of Wireless Extensions. */ -+ struct iw_public_data * wireless_data; -+#endif -+ /* Management operations */ -+ const struct net_device_ops *netdev_ops; -+ const struct ethtool_ops *ethtool_ops; ++ err = vsc7385_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, ++ VSC73XX_ICPU_CHIPID, &t); ++ if (err) { ++ dev_err(&spi->dev, "unable to read chip id, err=%d\n", err); ++ return err; ++ } ++ ++ id = (t >> VSC73XX_ICPU_CHIPID_ID_SHIFT) & VSC73XX_ICPU_CHIPID_ID_MASK; ++ switch (id) { ++ case VSC73XX_ICPU_CHIPID_ID_7385: ++ case VSC73XX_ICPU_CHIPID_ID_7395: ++ break; ++ default: ++ dev_err(&spi->dev, "unsupported chip, id=%04x\n", id); ++ return -ENODEV; ++ } ++ ++ rev = (t >> VSC73XX_ICPU_CHIPID_REV_SHIFT) & ++ VSC73XX_ICPU_CHIPID_REV_MASK; ++ dev_info(&spi->dev, "VSC%04X (rev. %d) switch found \n", id, rev); + -+ /* Hardware header description */ -+ const struct header_ops *header_ops; ++ return 0; ++} + -+ unsigned int flags; /* interface flags (a la BSD) */ -+ unsigned short gflags; -+ unsigned short priv_flags; /* Like 'flags' but invisible to userspace. */ -+ unsigned short padded; /* How much padding added by alloc_netdev() */ ++static int __devinit vsc7385_probe(struct spi_device *spi) ++{ ++ struct vsc7385 *vsc; ++ struct vsc7385_platform_data *pdata; ++ int err; + -+ unsigned char operstate; /* RFC2863 operstate */ -+ unsigned char link_mode; /* mapping policy to operstate */ ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION"\n"); + -+ unsigned int mtu; /* interface MTU value */ -+ unsigned short type; /* interface hardware type */ -+ unsigned short hard_header_len; /* hardware hdr length */ ++ pdata = spi->dev.platform_data; ++ if (!pdata) { ++ dev_err(&spi->dev, "no platform data specified\n"); ++ return-ENODEV; ++ } + -+ /* extra head- and tailroom the hardware may need, but not in all cases -+ * can this be guaranteed, especially tailroom. Some cases also use -+ * LL_MAX_HEADER instead to allocate the skb. -+ */ -+ unsigned short needed_headroom; -+ unsigned short needed_tailroom; ++ vsc = kzalloc(sizeof(*vsc), GFP_KERNEL); ++ if (!vsc) { ++ dev_err(&spi->dev, "no memory for private data\n"); ++ return-ENOMEM; ++ } + -+ struct net_device *master; /* Pointer to master device of a group, -+ * which this device is member of. -+ */ ++ mutex_init(&vsc->lock); ++ vsc->pdata = pdata; ++ vsc->spi = spi_dev_get(spi); ++ dev_set_drvdata(&spi->dev, vsc); + -+ /* Interface address info. */ -+ unsigned char perm_addr[MAX_ADDR_LEN]; /* permanent hw address */ -+ unsigned char addr_len; /* hardware address length */ -+ unsigned short dev_id; /* for shared network cards */ ++ spi->mode = SPI_MODE_0; ++ spi->bits_per_word = 8; ++ err = spi_setup(spi); ++ if (err) { ++ dev_err(&spi->dev, "spi_setup failed, err=%d \n", err); ++ goto err_drvdata; ++ } + -+ spinlock_t addr_list_lock; -+ struct netdev_hw_addr_list uc; /* Unicast mac addresses */ -+ struct netdev_hw_addr_list mc; /* Multicast mac addresses */ -+ int uc_promisc; -+ unsigned int promiscuity; -+ unsigned int allmulti; ++ err = vsc7385_detect(vsc); ++ if (err) { ++ dev_err(&spi->dev, "no chip found, err=%d \n", err); ++ goto err_drvdata; ++ } + ++ err = vsc7385_upload_ucode(vsc); ++ if (err) ++ goto err_drvdata; + -+ /* Protocol specific pointers */ -+ -+#ifdef CONFIG_NET_DSA -+ void *dsa_ptr; /* dsa specific data */ -+#endif -+ void *atalk_ptr; /* AppleTalk link */ -+ void *ip_ptr; /* IPv4 specific data */ -+ void *dn_ptr; /* DECnet specific data */ -+ void *ip6_ptr; /* IPv6 specific data */ -+ void *ec_ptr; /* Econet specific data */ -+ void *ax25_ptr; /* AX.25 specific data */ -+ struct wireless_dev *ieee80211_ptr; /* IEEE 802.11 specific data, -+ assign before registering */ ++ err = vsc7385_setup(vsc); ++ if (err) ++ goto err_drvdata; + -+/* -+ * Cache line mostly used on receive path (including eth_type_trans()) -+ */ -+ unsigned long last_rx; /* Time of last Rx */ -+ /* Interface address info used in eth_type_trans() */ -+ unsigned char *dev_addr; /* hw address, (before bcast -+ because most packets are -+ unicast) */ ++ return 0; + -+ struct netdev_hw_addr_list dev_addrs; /* list of device -+ hw addresses */ ++ err_drvdata: ++ dev_set_drvdata(&spi->dev, NULL); ++ kfree(vsc); ++ return err; ++} + -+ unsigned char broadcast[MAX_ADDR_LEN]; /* hw bcast add */ ++static int __devexit vsc7385_remove(struct spi_device *spi) ++{ ++ struct vsc7385_data *vsc; + -+#ifdef CONFIG_RPS -+ struct kset *queues_kset; ++ vsc = dev_get_drvdata(&spi->dev); ++ dev_set_drvdata(&spi->dev, NULL); ++ kfree(vsc); + -+ struct netdev_rx_queue *_rx; ++ return 0; ++} + -+ /* Number of RX queues allocated at alloc_netdev_mq() time */ -+ unsigned int num_rx_queues; -+#endif ++static struct spi_driver vsc7385_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .bus = &spi_bus_type, ++ .owner = THIS_MODULE, ++ }, ++ .probe = vsc7385_probe, ++ .remove = __devexit_p(vsc7385_remove), ++}; + -+ struct netdev_queue rx_queue; ++static int __init vsc7385_init(void) ++{ ++ return spi_register_driver(&vsc7385_driver); ++} ++module_init(vsc7385_init); + -+ struct netdev_queue *_tx ____cacheline_aligned_in_smp; ++static void __exit vsc7385_exit(void) ++{ ++ spi_unregister_driver(&vsc7385_driver); ++} ++module_exit(vsc7385_exit); + -+ /* Number of TX queues allocated at alloc_netdev_mq() time */ -+ unsigned int num_tx_queues; ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos "); ++MODULE_LICENSE("GPL v2"); + -+ /* Number of TX queues currently active in device */ -+ unsigned int real_num_tx_queues; +diff -Nur linux-2.6.36.orig/drivers/usb/host/Kconfig linux-2.6.36/drivers/usb/host/Kconfig +--- linux-2.6.36.orig/drivers/usb/host/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/usb/host/Kconfig 2010-11-18 21:16:15.000000000 +0100 +@@ -112,6 +112,13 @@ + support both high speed and full speed devices, or high speed + devices only. + ++config USB_EHCI_AR71XX ++ bool "USB EHCI support for AR71xx" ++ depends on USB_EHCI_HCD && ATHEROS_AR71XX ++ default y ++ help ++ Support for Atheros AR71xx built-in EHCI controller + -+ /* root qdisc from userspace point of view */ -+ struct Qdisc *qdisc; + config USB_EHCI_FSL + bool "Support for Freescale on-chip EHCI USB controller" + depends on USB_EHCI_HCD && FSL_SOC +@@ -225,6 +232,13 @@ + Enables support for the on-chip OHCI controller on + OMAP3 and later chips. + ++config USB_OHCI_AR71XX ++ bool "USB OHCI support for Atheros AR71xx" ++ depends on USB_OHCI_HCD && ATHEROS_AR71XX ++ default y ++ help ++ Support for Atheros AR71xx built-in OHCI controller + -+ unsigned long tx_queue_len; /* Max frames per queue allowed */ -+ spinlock_t tx_global_lock; + config USB_OHCI_HCD_PPC_SOC + bool "OHCI support for on-chip PPC USB controller" + depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx) +diff -Nur linux-2.6.36.orig/drivers/usb/host/ehci-ar71xx.c linux-2.6.36/drivers/usb/host/ehci-ar71xx.c +--- linux-2.6.36.orig/drivers/usb/host/ehci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/usb/host/ehci-ar71xx.c 2010-11-18 21:16:15.000000000 +0100 +@@ -0,0 +1,242 @@ +/* -+ * One part is mostly used on xmit path (device) ++ * Bus Glue for Atheros AR71xx built-in EHCI controller. ++ * ++ * Copyright (C) 2008-2010 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Copyright (C) 2007 Atheros Communications, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ -+ /* These may be needed for future network-power-down code. */ -+ -+ /* -+ * trans_start here is expensive for high speed devices on SMP, -+ * please use netdev_queue->trans_start instead. -+ */ -+ unsigned long trans_start; /* Time (in jiffies) of last Tx */ -+ -+ int watchdog_timeo; /* used by dev_watchdog() */ -+ struct timer_list watchdog_timer; + -+ /* Number of references to this device */ -+ atomic_t refcnt ____cacheline_aligned_in_smp; -+ -+ /* delayed register/unregister */ -+ struct list_head todo_list; -+ /* device index hash chain */ -+ struct hlist_node index_hlist; ++#include ++#include + -+ struct list_head link_watch_list; ++#include + -+ /* register/unregister state machine */ -+ enum { NETREG_UNINITIALIZED=0, -+ NETREG_REGISTERED, /* completed register_netdevice */ -+ NETREG_UNREGISTERING, /* called unregister_netdevice */ -+ NETREG_UNREGISTERED, /* completed unregister todo */ -+ NETREG_RELEASED, /* called free_netdev */ -+ NETREG_DUMMY, /* dummy device for NAPI poll */ -+ } reg_state:16; ++extern int usb_disabled(void); + -+ enum { -+ RTNL_LINK_INITIALIZED, -+ RTNL_LINK_INITIALIZING, -+ } rtnl_link_state:16; ++static int ehci_ar71xx_init(struct usb_hcd *hcd) ++{ ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ int ret; + -+ /* Called from unregister, can be used to call free_netdev */ -+ void (*destructor)(struct net_device *dev); ++ ehci->caps = hcd->regs; ++ ehci->regs = hcd->regs + ++ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); ++ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + -+#ifdef CONFIG_NETPOLL -+ struct netpoll_info *npinfo; -+#endif ++ ehci->sbrn = 0x20; ++ ehci->has_synopsys_hc_bug = 1; + -+#ifdef CONFIG_NET_NS -+ /* Network namespace this network device is inside */ -+ struct net *nd_net; -+#endif ++ ehci_reset(ehci); + -+ /* mid-layer private */ -+ void *ml_priv; ++ ret = ehci_init(hcd); ++ if (ret) ++ return ret; + -+ /* bridge stuff */ -+ struct net_bridge_port *br_port; -+ /* macvlan */ -+ struct macvlan_port *macvlan_port; -+ /* GARP */ -+ struct garp_port *garp_port; ++ ehci_port_power(ehci, 0); + -+ /* class/net/name entry */ -+ struct device dev; -+ /* space for optional device, statistics, and wireless sysfs groups */ -+ const struct attribute_group *sysfs_groups[4]; ++ return 0; ++} + -+ /* rtnetlink link ops */ -+ const struct rtnl_link_ops *rtnl_link_ops; ++static int ehci_ar91xx_init(struct usb_hcd *hcd) ++{ ++ struct ehci_hcd *ehci = hcd_to_ehci(hcd); ++ int ret; + -+ /* VLAN feature mask */ -+ unsigned long vlan_features; ++ ehci->caps = hcd->regs + 0x100; ++ ehci->regs = hcd->regs + 0x100 + ++ HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); ++ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + -+ /* for setting kernel sock attribute on TCP connection setup */ -+#define GSO_MAX_SIZE 65536 -+ unsigned int gso_max_size; ++ hcd->has_tt = 1; ++ ehci->sbrn = 0x20; + -+#ifdef CONFIG_DCB -+ /* Data Center Bridging netlink ops */ -+ const struct dcbnl_rtnl_ops *dcbnl_ops; -+#endif ++ ehci_reset(ehci); + -+#if defined(CONFIG_FCOE) || defined(CONFIG_FCOE_MODULE) -+ /* max exchange id for FCoE LRO by ddp */ -+ unsigned int fcoe_ddp_xid; -+#endif -+ /* n-tuple filter list attached to this device */ -+ struct ethtool_rx_ntuple_list ethtool_ntuple_list; -+}; -+#define to_net_dev(d) container_of(d, struct net_device, dev) ++ ret = ehci_init(hcd); ++ if (ret) ++ return ret; + -+#define NETDEV_ALIGN 32 ++ ehci_port_power(ehci, 0); + -+static inline -+struct netdev_queue *netdev_get_tx_queue(const struct net_device *dev, -+ unsigned int index) -+{ -+ return &dev->_tx[index]; ++ return 0; +} + -+static inline void netdev_for_each_tx_queue(struct net_device *dev, -+ void (*f)(struct net_device *, -+ struct netdev_queue *, -+ void *), -+ void *arg) ++static int ehci_ar71xx_probe(const struct hc_driver *driver, ++ struct usb_hcd **hcd_out, ++ struct platform_device *pdev) +{ -+ unsigned int i; ++ struct usb_hcd *hcd; ++ struct resource *res; ++ int irq; ++ int ret; + -+ for (i = 0; i < dev->num_tx_queues; i++) -+ f(dev, &dev->_tx[i], arg); -+} ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) { ++ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ } ++ irq = res->start; + -+/* -+ * Net namespace inlines -+ */ -+static inline -+struct net *dev_net(const struct net_device *dev) -+{ -+#ifdef CONFIG_NET_NS -+ return dev->nd_net; -+#else -+ return &init_net; -+#endif -+} ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_dbg(&pdev->dev, "no base address specified for %s\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ } + -+static inline -+void dev_net_set(struct net_device *dev, struct net *net) -+{ -+#ifdef CONFIG_NET_NS -+ release_net(dev->nd_net); -+ dev->nd_net = hold_net(net); -+#endif -+} ++ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); ++ if (!hcd) ++ return -ENOMEM; + -+static inline bool netdev_uses_dsa_tags(struct net_device *dev) -+{ -+#ifdef CONFIG_NET_DSA_TAG_DSA -+ if (dev->dsa_ptr != NULL) -+ return dsa_uses_dsa_tags(dev->dsa_ptr); -+#endif ++ hcd->rsrc_start = res->start; ++ hcd->rsrc_len = res->end - res->start + 1; + -+ return 0; -+} ++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { ++ dev_dbg(&pdev->dev, "controller already in use\n"); ++ ret = -EBUSY; ++ goto err_put_hcd; ++ } + -+#ifndef CONFIG_NET_NS -+static inline void skb_set_dev(struct sk_buff *skb, struct net_device *dev) -+{ -+ skb->dev = dev; -+} -+#else /* CONFIG_NET_NS */ -+void skb_set_dev(struct sk_buff *skb, struct net_device *dev); -+#endif ++ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) { ++ dev_dbg(&pdev->dev, "error mapping memory\n"); ++ ret = -EFAULT; ++ goto err_release_region; ++ } + -+static inline bool netdev_uses_trailer_tags(struct net_device *dev) -+{ -+#ifdef CONFIG_NET_DSA_TAG_TRAILER -+ if (dev->dsa_ptr != NULL) -+ return dsa_uses_trailer_tags(dev->dsa_ptr); -+#endif ++ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); ++ if (ret) ++ goto err_iounmap; + + return 0; ++ ++ err_iounmap: ++ iounmap(hcd->regs); ++ ++ err_release_region: ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ err_put_hcd: ++ usb_put_hcd(hcd); ++ return ret; +} + -+/** -+ * netdev_priv - access network device private data -+ * @dev: network device -+ * -+ * Get network device private data -+ */ -+static inline void *netdev_priv(const struct net_device *dev) ++static void ehci_ar71xx_remove(struct usb_hcd *hcd, ++ struct platform_device *pdev) +{ -+ return (char *)dev + ALIGN(sizeof(struct net_device), NETDEV_ALIGN); ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ usb_put_hcd(hcd); +} + -+/* Set the sysfs physical device reference for the network logical device -+ * if set prior to registration will cause a symlink during initialization. -+ */ -+#define SET_NETDEV_DEV(net, pdev) ((net)->dev.parent = (pdev)) ++static const struct hc_driver ehci_ar71xx_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Atheros AR71xx built-in EHCI controller", ++ .hcd_priv_size = sizeof(struct ehci_hcd), + -+/* Set the sysfs device type for the network logical device to allow -+ * fin grained indentification of different network device types. For -+ * example Ethernet, Wirelss LAN, Bluetooth, WiMAX etc. -+ */ -+#define SET_NETDEV_DEVTYPE(net, devtype) ((net)->dev.type = (devtype)) -+ -+/** -+ * netif_napi_add - initialize a napi context -+ * @dev: network device -+ * @napi: napi context -+ * @poll: polling function -+ * @weight: default weight -+ * -+ * netif_napi_add() must be used to initialize a napi context prior to calling -+ * *any* of the other napi related functions. -+ */ -+void netif_napi_add(struct net_device *dev, struct napi_struct *napi, -+ int (*poll)(struct napi_struct *, int), int weight); ++ .irq = ehci_irq, ++ .flags = HCD_MEMORY | HCD_USB2, + -+/** -+ * netif_napi_del - remove a napi context -+ * @napi: napi context -+ * -+ * netif_napi_del() removes a napi context from the network device napi list -+ */ -+void netif_napi_del(struct napi_struct *napi); ++ .reset = ehci_ar71xx_init, ++ .start = ehci_run, ++ .stop = ehci_stop, ++ .shutdown = ehci_shutdown, + -+struct napi_gro_cb { -+ /* Virtual address of skb_shinfo(skb)->frags[0].page + offset. */ -+ void *frag0; ++ .urb_enqueue = ehci_urb_enqueue, ++ .urb_dequeue = ehci_urb_dequeue, ++ .endpoint_disable = ehci_endpoint_disable, ++ .endpoint_reset = ehci_endpoint_reset, + -+ /* Length of frag0. */ -+ unsigned int frag0_len; ++ .get_frame_number = ehci_get_frame, + -+ /* This indicates where we are processing relative to skb->data. */ -+ int data_offset; ++ .hub_status_data = ehci_hub_status_data, ++ .hub_control = ehci_hub_control, ++#ifdef CONFIG_PM ++ .hub_suspend = ehci_hub_suspend, ++ .hub_resume = ehci_hub_resume, ++#endif ++ .relinquish_port = ehci_relinquish_port, ++ .port_handed_over = ehci_port_handed_over, + -+ /* This is non-zero if the packet may be of the same flow. */ -+ int same_flow; ++ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, ++}; + -+ /* This is non-zero if the packet cannot be merged with the new skb. */ -+ int flush; ++static const struct hc_driver ehci_ar91xx_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Atheros AR91xx built-in EHCI controller", ++ .hcd_priv_size = sizeof(struct ehci_hcd), ++ .irq = ehci_irq, ++ .flags = HCD_MEMORY | HCD_USB2, + -+ /* Number of segments aggregated. */ -+ int count; ++ .reset = ehci_ar91xx_init, ++ .start = ehci_run, ++ .stop = ehci_stop, ++ .shutdown = ehci_shutdown, + -+ /* Free the skb? */ -+ int free; -+}; -+ -+#define NAPI_GRO_CB(skb) ((struct napi_gro_cb *)(skb)->cb) -+ -+struct packet_type { -+ __be16 type; /* This is really htons(ether_type). */ -+ struct net_device *dev; /* NULL is wildcarded here */ -+ int (*func) (struct sk_buff *, -+ struct net_device *, -+ struct packet_type *, -+ struct net_device *); -+ struct sk_buff *(*gso_segment)(struct sk_buff *skb, -+ int features); -+ int (*gso_send_check)(struct sk_buff *skb); -+ struct sk_buff **(*gro_receive)(struct sk_buff **head, -+ struct sk_buff *skb); -+ int (*gro_complete)(struct sk_buff *skb); -+ void *af_packet_priv; -+ struct list_head list; -+}; ++ .urb_enqueue = ehci_urb_enqueue, ++ .urb_dequeue = ehci_urb_dequeue, ++ .endpoint_disable = ehci_endpoint_disable, ++ .endpoint_reset = ehci_endpoint_reset, + -+#include -+#include -+ -+extern rwlock_t dev_base_lock; /* Device list lock */ -+ -+ -+#define for_each_netdev(net, d) \ -+ list_for_each_entry(d, &(net)->dev_base_head, dev_list) -+#define for_each_netdev_reverse(net, d) \ -+ list_for_each_entry_reverse(d, &(net)->dev_base_head, dev_list) -+#define for_each_netdev_rcu(net, d) \ -+ list_for_each_entry_rcu(d, &(net)->dev_base_head, dev_list) -+#define for_each_netdev_safe(net, d, n) \ -+ list_for_each_entry_safe(d, n, &(net)->dev_base_head, dev_list) -+#define for_each_netdev_continue(net, d) \ -+ list_for_each_entry_continue(d, &(net)->dev_base_head, dev_list) -+#define for_each_netdev_continue_rcu(net, d) \ -+ list_for_each_entry_continue_rcu(d, &(net)->dev_base_head, dev_list) -+#define net_device_entry(lh) list_entry(lh, struct net_device, dev_list) -+ -+static inline struct net_device *next_net_device(struct net_device *dev) -+{ -+ struct list_head *lh; -+ struct net *net; -+ -+ net = dev_net(dev); -+ lh = dev->dev_list.next; -+ return lh == &net->dev_base_head ? NULL : net_device_entry(lh); -+} -+ -+static inline struct net_device *next_net_device_rcu(struct net_device *dev) -+{ -+ struct list_head *lh; -+ struct net *net; -+ -+ net = dev_net(dev); -+ lh = rcu_dereference(dev->dev_list.next); -+ return lh == &net->dev_base_head ? NULL : net_device_entry(lh); -+} -+ -+static inline struct net_device *first_net_device(struct net *net) -+{ -+ return list_empty(&net->dev_base_head) ? NULL : -+ net_device_entry(net->dev_base_head.next); -+} -+ -+extern int netdev_boot_setup_check(struct net_device *dev); -+extern unsigned long netdev_boot_base(const char *prefix, int unit); -+extern struct net_device *dev_getbyhwaddr(struct net *net, unsigned short type, char *hwaddr); -+extern struct net_device *dev_getfirstbyhwtype(struct net *net, unsigned short type); -+extern struct net_device *__dev_getfirstbyhwtype(struct net *net, unsigned short type); -+extern void dev_add_pack(struct packet_type *pt); -+extern void dev_remove_pack(struct packet_type *pt); -+extern void __dev_remove_pack(struct packet_type *pt); -+ -+extern struct net_device *dev_get_by_flags(struct net *net, unsigned short flags, -+ unsigned short mask); -+extern struct net_device *dev_get_by_name(struct net *net, const char *name); -+extern struct net_device *dev_get_by_name_rcu(struct net *net, const char *name); -+extern struct net_device *__dev_get_by_name(struct net *net, const char *name); -+extern int dev_alloc_name(struct net_device *dev, const char *name); -+extern int dev_open(struct net_device *dev); -+extern int dev_close(struct net_device *dev); -+extern void dev_disable_lro(struct net_device *dev); -+extern int dev_queue_xmit(struct sk_buff *skb); -+extern int register_netdevice(struct net_device *dev); -+extern void unregister_netdevice_queue(struct net_device *dev, -+ struct list_head *head); -+extern void unregister_netdevice_many(struct list_head *head); -+static inline void unregister_netdevice(struct net_device *dev) -+{ -+ unregister_netdevice_queue(dev, NULL); -+} -+ -+extern void free_netdev(struct net_device *dev); -+extern void synchronize_net(void); -+extern int register_netdevice_notifier(struct notifier_block *nb); -+extern int unregister_netdevice_notifier(struct notifier_block *nb); -+extern int init_dummy_netdev(struct net_device *dev); -+extern void netdev_resync_ops(struct net_device *dev); -+ -+extern int call_netdevice_notifiers(unsigned long val, struct net_device *dev); -+extern struct net_device *dev_get_by_index(struct net *net, int ifindex); -+extern struct net_device *__dev_get_by_index(struct net *net, int ifindex); -+extern struct net_device *dev_get_by_index_rcu(struct net *net, int ifindex); -+extern int dev_restart(struct net_device *dev); -+#ifdef CONFIG_NETPOLL_TRAP -+extern int netpoll_trap(void); ++ .get_frame_number = ehci_get_frame, ++ ++ .hub_status_data = ehci_hub_status_data, ++ .hub_control = ehci_hub_control, ++#ifdef CONFIG_PM ++ .hub_suspend = ehci_hub_suspend, ++ .hub_resume = ehci_hub_resume, +#endif -+extern int skb_gro_receive(struct sk_buff **head, -+ struct sk_buff *skb); -+extern void skb_gro_reset_offset(struct sk_buff *skb); ++ .relinquish_port = ehci_relinquish_port, ++ .port_handed_over = ehci_port_handed_over, + -+static inline unsigned int skb_gro_offset(const struct sk_buff *skb) -+{ -+ return NAPI_GRO_CB(skb)->data_offset; -+} ++ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete, ++}; + -+static inline unsigned int skb_gro_len(const struct sk_buff *skb) ++static int ehci_ar71xx_driver_probe(struct platform_device *pdev) +{ -+ return skb->len - NAPI_GRO_CB(skb)->data_offset; -+} ++ struct ar71xx_ehci_platform_data *pdata; ++ struct usb_hcd *hcd = NULL; ++ int ret; + -+static inline void skb_gro_pull(struct sk_buff *skb, unsigned int len) -+{ -+ NAPI_GRO_CB(skb)->data_offset += len; -+} ++ if (usb_disabled()) ++ return -ENODEV; ++ ++ pdata = pdev->dev.platform_data; ++ if (!pdata) { ++ dev_err(&pdev->dev, "no platform data specified for %s\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ } + -+static inline void *skb_gro_header_fast(struct sk_buff *skb, -+ unsigned int offset) -+{ -+ return NAPI_GRO_CB(skb)->frag0 + offset; -+} ++ if (pdata->is_ar91xx) ++ ret = ehci_ar71xx_probe(&ehci_ar91xx_hc_driver, &hcd, pdev); ++ else ++ ret = ehci_ar71xx_probe(&ehci_ar71xx_hc_driver, &hcd, pdev); + -+static inline int skb_gro_header_hard(struct sk_buff *skb, unsigned int hlen) -+{ -+ return NAPI_GRO_CB(skb)->frag0_len < hlen; ++ return ret; +} + -+static inline void *skb_gro_header_slow(struct sk_buff *skb, unsigned int hlen, -+ unsigned int offset) ++static int ehci_ar71xx_driver_remove(struct platform_device *pdev) +{ -+ NAPI_GRO_CB(skb)->frag0 = NULL; -+ NAPI_GRO_CB(skb)->frag0_len = 0; -+ return pskb_may_pull(skb, hlen) ? skb->data + offset : NULL; -+} ++ struct usb_hcd *hcd = platform_get_drvdata(pdev); + -+static inline void *skb_gro_mac_header(struct sk_buff *skb) -+{ -+ return NAPI_GRO_CB(skb)->frag0 ?: skb_mac_header(skb); ++ ehci_ar71xx_remove(hcd, pdev); ++ return 0; +} + -+static inline void *skb_gro_network_header(struct sk_buff *skb) -+{ -+ return (NAPI_GRO_CB(skb)->frag0 ?: skb->data) + -+ skb_network_offset(skb); -+} ++MODULE_ALIAS("platform:ar71xx-ehci"); + -+static inline int dev_hard_header(struct sk_buff *skb, struct net_device *dev, -+ unsigned short type, -+ const void *daddr, const void *saddr, -+ unsigned len) -+{ -+ if (!dev->header_ops || !dev->header_ops->create) -+ return 0; ++static struct platform_driver ehci_ar71xx_driver = { ++ .probe = ehci_ar71xx_driver_probe, ++ .remove = ehci_ar71xx_driver_remove, ++ .driver = { ++ .name = "ar71xx-ehci", ++ } ++}; +diff -Nur linux-2.6.36.orig/drivers/usb/host/ehci-hcd.c linux-2.6.36/drivers/usb/host/ehci-hcd.c +--- linux-2.6.36.orig/drivers/usb/host/ehci-hcd.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/usb/host/ehci-hcd.c 2010-11-18 21:16:15.000000000 +0100 +@@ -1197,6 +1197,11 @@ + #define PLATFORM_DRIVER ehci_atmel_driver + #endif + ++#ifdef CONFIG_USB_EHCI_AR71XX ++#include "ehci-ar71xx.c" ++#define PLATFORM_DRIVER ehci_ar71xx_driver ++#endif + -+ return dev->header_ops->create(skb, dev, type, daddr, saddr, len); -+} + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ + !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \ + !defined(XILINX_OF_PLATFORM_DRIVER) +diff -Nur linux-2.6.36.orig/drivers/usb/host/ohci-ar71xx.c linux-2.6.36/drivers/usb/host/ohci-ar71xx.c +--- linux-2.6.36.orig/drivers/usb/host/ohci-ar71xx.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/usb/host/ohci-ar71xx.c 2010-11-18 21:16:16.000000000 +0100 +@@ -0,0 +1,165 @@ ++/* ++ * OHCI HCD (Host Controller Driver) for USB. ++ * ++ * Bus Glue for Atheros AR71xx built-in OHCI controller. ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * Parts of this file are based on Atheros' 2.6.15 BSP ++ * Copyright (C) 2007 Atheros Communications, Inc. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ */ + -+static inline int dev_parse_header(const struct sk_buff *skb, -+ unsigned char *haddr) -+{ -+ const struct net_device *dev = skb->dev; ++#include ++#include + -+ if (!dev->header_ops || !dev->header_ops->parse) -+ return 0; -+ return dev->header_ops->parse(skb, haddr); -+} ++extern int usb_disabled(void); + -+typedef int gifconf_func_t(struct net_device * dev, char __user * bufptr, int len); -+extern int register_gifconf(unsigned int family, gifconf_func_t * gifconf); -+static inline int unregister_gifconf(unsigned int family) ++static int usb_hcd_ar71xx_probe(const struct hc_driver *driver, ++ struct platform_device *pdev) +{ -+ return register_gifconf(family, NULL); -+} ++ struct usb_hcd *hcd; ++ struct resource *res; ++ int irq; ++ int ret; + -+/* -+ * Incoming packets are placed on per-cpu queues -+ */ -+struct softnet_data { -+ struct Qdisc *output_queue; -+ struct Qdisc **output_queue_tailp; -+ struct list_head poll_list; -+ struct sk_buff *completion_queue; -+ struct sk_buff_head process_queue; -+ -+ /* stats */ -+ unsigned int processed; -+ unsigned int time_squeeze; -+ unsigned int cpu_collision; -+ unsigned int received_rps; -+ -+#ifdef CONFIG_RPS -+ struct softnet_data *rps_ipi_list; -+ -+ /* Elements below can be accessed between CPUs for RPS */ -+ struct call_single_data csd ____cacheline_aligned_in_smp; -+ struct softnet_data *rps_ipi_next; -+ unsigned int cpu; -+ unsigned int input_queue_head; -+ unsigned int input_queue_tail; -+#endif -+ unsigned dropped; -+ struct sk_buff_head input_pkt_queue; -+ struct napi_struct backlog; -+}; ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!res) { ++ dev_dbg(&pdev->dev, "no IRQ specified for %s\n", ++ dev_name(&pdev->dev)); ++ return -ENODEV; ++ } ++ irq = res->start; + -+static inline void input_queue_head_incr(struct softnet_data *sd) -+{ -+#ifdef CONFIG_RPS -+ sd->input_queue_head++; -+#endif -+} ++ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev)); ++ if (!hcd) ++ return -ENOMEM; + -+static inline void input_queue_tail_incr_save(struct softnet_data *sd, -+ unsigned int *qtail) -+{ -+#ifdef CONFIG_RPS -+ *qtail = ++sd->input_queue_tail; -+#endif -+} ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!res) { ++ dev_dbg(&pdev->dev, "no base address specified for %s\n", ++ dev_name(&pdev->dev)); ++ ret = -ENODEV; ++ goto err_put_hcd; ++ } ++ hcd->rsrc_start = res->start; ++ hcd->rsrc_len = res->end - res->start + 1; + -+DECLARE_PER_CPU_ALIGNED(struct softnet_data, softnet_data); ++ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { ++ dev_dbg(&pdev->dev, "controller already in use\n"); ++ ret = -EBUSY; ++ goto err_put_hcd; ++ } + -+#define HAVE_NETIF_QUEUE ++ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); ++ if (!hcd->regs) { ++ dev_dbg(&pdev->dev, "error mapping memory\n"); ++ ret = -EFAULT; ++ goto err_release_region; ++ } + -+extern void __netif_schedule(struct Qdisc *q); ++ ohci_hcd_init(hcd_to_ohci(hcd)); + -+static inline void netif_schedule_queue(struct netdev_queue *txq) -+{ -+ if (!test_bit(__QUEUE_STATE_XOFF, &txq->state)) -+ __netif_schedule(txq->qdisc); -+} ++ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); ++ if (ret) ++ goto err_stop_hcd; + -+static inline void netif_tx_schedule_all(struct net_device *dev) -+{ -+ unsigned int i; ++ return 0; + -+ for (i = 0; i < dev->num_tx_queues; i++) -+ netif_schedule_queue(netdev_get_tx_queue(dev, i)); ++ err_stop_hcd: ++ iounmap(hcd->regs); ++ err_release_region: ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ err_put_hcd: ++ usb_put_hcd(hcd); ++ return ret; +} + -+static inline void netif_tx_start_queue(struct netdev_queue *dev_queue) ++void usb_hcd_ar71xx_remove(struct usb_hcd *hcd, struct platform_device *pdev) +{ -+ clear_bit(__QUEUE_STATE_XOFF, &dev_queue->state); ++ usb_remove_hcd(hcd); ++ iounmap(hcd->regs); ++ release_mem_region(hcd->rsrc_start, hcd->rsrc_len); ++ usb_put_hcd(hcd); +} + -+/** -+ * netif_start_queue - allow transmit -+ * @dev: network device -+ * -+ * Allow upper layers to call the device hard_start_xmit routine. -+ */ -+static inline void netif_start_queue(struct net_device *dev) ++static int __devinit ohci_ar71xx_start(struct usb_hcd *hcd) +{ -+ netif_tx_start_queue(netdev_get_tx_queue(dev, 0)); -+} ++ struct ohci_hcd *ohci = hcd_to_ohci(hcd); ++ int ret; + -+static inline void netif_tx_start_all_queues(struct net_device *dev) -+{ -+ unsigned int i; ++ ret = ohci_init(ohci); ++ if (ret < 0) ++ return ret; + -+ for (i = 0; i < dev->num_tx_queues; i++) { -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, i); -+ netif_tx_start_queue(txq); -+ } -+} ++ ret = ohci_run(ohci); ++ if (ret < 0) ++ goto err; + -+static inline void netif_tx_wake_queue(struct netdev_queue *dev_queue) -+{ -+#ifdef CONFIG_NETPOLL_TRAP -+ if (netpoll_trap()) { -+ netif_tx_start_queue(dev_queue); -+ return; -+ } -+#endif -+ if (test_and_clear_bit(__QUEUE_STATE_XOFF, &dev_queue->state)) -+ __netif_schedule(dev_queue->qdisc); -+} ++ return 0; + -+/** -+ * netif_wake_queue - restart transmit -+ * @dev: network device -+ * -+ * Allow upper layers to call the device hard_start_xmit routine. -+ * Used for flow control when transmit resources are available. -+ */ -+static inline void netif_wake_queue(struct net_device *dev) -+{ -+ netif_tx_wake_queue(netdev_get_tx_queue(dev, 0)); ++ err: ++ ohci_stop(hcd); ++ return ret; +} + -+static inline void netif_tx_wake_all_queues(struct net_device *dev) -+{ -+ unsigned int i; ++static const struct hc_driver ohci_ar71xx_hc_driver = { ++ .description = hcd_name, ++ .product_desc = "Atheros AR71xx built-in OHCI controller", ++ .hcd_priv_size = sizeof(struct ohci_hcd), + -+ for (i = 0; i < dev->num_tx_queues; i++) { -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, i); -+ netif_tx_wake_queue(txq); -+ } -+} ++ .irq = ohci_irq, ++ .flags = HCD_USB11 | HCD_MEMORY, + -+static inline void netif_tx_stop_queue(struct netdev_queue *dev_queue) -+{ -+ set_bit(__QUEUE_STATE_XOFF, &dev_queue->state); -+} ++ .start = ohci_ar71xx_start, ++ .stop = ohci_stop, ++ .shutdown = ohci_shutdown, + -+/** -+ * netif_stop_queue - stop transmitted packets -+ * @dev: network device -+ * -+ * Stop upper layers calling the device hard_start_xmit routine. -+ * Used for flow control when transmit resources are unavailable. -+ */ -+static inline void netif_stop_queue(struct net_device *dev) -+{ -+ netif_tx_stop_queue(netdev_get_tx_queue(dev, 0)); -+} ++ .urb_enqueue = ohci_urb_enqueue, ++ .urb_dequeue = ohci_urb_dequeue, ++ .endpoint_disable = ohci_endpoint_disable, + -+static inline void netif_tx_stop_all_queues(struct net_device *dev) -+{ -+ unsigned int i; ++ /* ++ * scheduling support ++ */ ++ .get_frame_number = ohci_get_frame, + -+ for (i = 0; i < dev->num_tx_queues; i++) { -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, i); -+ netif_tx_stop_queue(txq); -+ } -+} ++ /* ++ * root hub support ++ */ ++ .hub_status_data = ohci_hub_status_data, ++ .hub_control = ohci_hub_control, ++ .start_port_reset = ohci_start_port_reset, ++}; + -+static inline int netif_tx_queue_stopped(const struct netdev_queue *dev_queue) ++static int ohci_hcd_ar71xx_drv_probe(struct platform_device *pdev) +{ -+ return test_bit(__QUEUE_STATE_XOFF, &dev_queue->state); -+} ++ if (usb_disabled()) ++ return -ENODEV; + -+/** -+ * netif_queue_stopped - test if transmit queue is flowblocked -+ * @dev: network device -+ * -+ * Test if transmit queue on device is currently unable to send. -+ */ -+static inline int netif_queue_stopped(const struct net_device *dev) -+{ -+ return netif_tx_queue_stopped(netdev_get_tx_queue(dev, 0)); ++ return usb_hcd_ar71xx_probe(&ohci_ar71xx_hc_driver, pdev); +} + -+static inline int netif_tx_queue_frozen(const struct netdev_queue *dev_queue) ++static int ohci_hcd_ar71xx_drv_remove(struct platform_device *pdev) +{ -+ return test_bit(__QUEUE_STATE_FROZEN, &dev_queue->state); -+} ++ struct usb_hcd *hcd = platform_get_drvdata(pdev); + -+/** -+ * netif_running - test if up -+ * @dev: network device -+ * -+ * Test if the device has been brought up. -+ */ -+static inline int netif_running(const struct net_device *dev) -+{ -+ return test_bit(__LINK_STATE_START, &dev->state); ++ usb_hcd_ar71xx_remove(hcd, pdev); ++ return 0; +} + -+/* -+ * Routines to manage the subqueues on a device. We only need start -+ * stop, and a check if it's stopped. All other device management is -+ * done at the overall netdevice level. -+ * Also test the device if we're multiqueue. -+ */ ++MODULE_ALIAS("platform:ar71xx-ohci"); ++ ++static struct platform_driver ohci_hcd_ar71xx_driver = { ++ .probe = ohci_hcd_ar71xx_drv_probe, ++ .remove = ohci_hcd_ar71xx_drv_remove, ++ .shutdown = usb_hcd_platform_shutdown, ++ .driver = { ++ .name = "ar71xx-ohci", ++ .owner = THIS_MODULE, ++ }, ++}; +diff -Nur linux-2.6.36.orig/drivers/usb/host/ohci-hcd.c linux-2.6.36/drivers/usb/host/ohci-hcd.c +--- linux-2.6.36.orig/drivers/usb/host/ohci-hcd.c 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/usb/host/ohci-hcd.c 2010-11-18 21:16:16.000000000 +0100 +@@ -1100,6 +1100,11 @@ + #define PLATFORM_DRIVER ohci_hcd_jz4740_driver + #endif + ++#ifdef CONFIG_USB_OHCI_AR71XX ++#include "ohci-ar71xx.c" ++#define PLATFORM_DRIVER ohci_hcd_ar71xx_driver ++#endif ++ + #if !defined(PCI_DRIVER) && \ + !defined(PLATFORM_DRIVER) && \ + !defined(OMAP1_PLATFORM_DRIVER) && \ +diff -Nur linux-2.6.36.orig/drivers/watchdog/Kconfig linux-2.6.36/drivers/watchdog/Kconfig +--- linux-2.6.36.orig/drivers/watchdog/Kconfig 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/watchdog/Kconfig 2010-11-18 21:16:17.000000000 +0100 +@@ -916,6 +916,13 @@ + from the first interrupt, it is then only poked when the + device is written. + ++config AR71XX_WDT ++ tristate "Atheros AR71xx Watchdog Timer" ++ depends on ATHEROS_AR71XX ++ help ++ Hardware driver for the built-in watchdog timer on the Atheros ++ AR71xx SoCs. + -+/** -+ * netif_start_subqueue - allow sending packets on subqueue -+ * @dev: network device -+ * @queue_index: sub queue index + # PARISC Architecture + + # POWERPC Architecture +diff -Nur linux-2.6.36.orig/drivers/watchdog/Makefile linux-2.6.36/drivers/watchdog/Makefile +--- linux-2.6.36.orig/drivers/watchdog/Makefile 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/drivers/watchdog/Makefile 2010-11-18 21:17:24.000000000 +0100 +@@ -116,6 +116,7 @@ + obj-$(CONFIG_SIBYTE_WDOG) += sb_wdog.o + obj-$(CONFIG_AR7_WDT) += ar7_wdt.o + obj-$(CONFIG_TXX9_WDT) += txx9wdt.o ++obj-$(CONFIG_AR71XX_WDT) += ar71xx_wdt.o + obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o + octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o + +diff -Nur linux-2.6.36.orig/drivers/watchdog/ar71xx_wdt.c linux-2.6.36/drivers/watchdog/ar71xx_wdt.c +--- linux-2.6.36.orig/drivers/watchdog/ar71xx_wdt.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/drivers/watchdog/ar71xx_wdt.c 2010-11-18 21:16:17.000000000 +0100 +@@ -0,0 +1,270 @@ ++/* ++ * Driver for the Atheros AR71xx SoC's built-in hardware watchdog timer. ++ * ++ * Copyright (C) 2008 Gabor Juhos ++ * Copyright (C) 2008 Imre Kaloz ++ * ++ * This driver was based on: drivers/watchdog/ixp4xx_wdt.c ++ * Author: Deepak Saxena ++ * Copyright 2004 (c) MontaVista, Software, Inc. ++ * ++ * which again was based on sa1100 driver, ++ * Copyright (C) 2000 Oleg Drokin ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + * -+ * Start individual transmit queue of a device with multiple transmit queues. + */ -+static inline void netif_start_subqueue(struct net_device *dev, u16 queue_index) -+{ -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue_index); + -+ netif_tx_start_queue(txq); -+} ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include + -+/** -+ * netif_stop_subqueue - stop sending packets on subqueue -+ * @dev: network device -+ * @queue_index: sub queue index -+ * -+ * Stop individual transmit queue of a device with multiple transmit queues. -+ */ -+static inline void netif_stop_subqueue(struct net_device *dev, u16 queue_index) -+{ -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue_index); -+#ifdef CONFIG_NETPOLL_TRAP -+ if (netpoll_trap()) -+ return; -+#endif -+ netif_tx_stop_queue(txq); -+} ++#include + -+/** -+ * netif_subqueue_stopped - test status of subqueue -+ * @dev: network device -+ * @queue_index: sub queue index -+ * -+ * Check individual transmit queue of a device with multiple transmit queues. -+ */ -+static inline int __netif_subqueue_stopped(const struct net_device *dev, -+ u16 queue_index) -+{ -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue_index); ++#define DRV_NAME "ar71xx-wdt" ++#define DRV_DESC "Atheros AR71xx hardware watchdog driver" ++#define DRV_VERSION "0.1.0" + -+ return netif_tx_queue_stopped(txq); -+} ++#define WDT_TIMEOUT 15 /* seconds */ + -+static inline int netif_subqueue_stopped(const struct net_device *dev, -+ struct sk_buff *skb) -+{ -+ return __netif_subqueue_stopped(dev, skb_get_queue_mapping(skb)); -+} ++static int nowayout = WATCHDOG_NOWAYOUT; + -+/** -+ * netif_wake_subqueue - allow sending packets on subqueue -+ * @dev: network device -+ * @queue_index: sub queue index -+ * -+ * Resume individual transmit queue of a device with multiple transmit queues. -+ */ -+static inline void netif_wake_subqueue(struct net_device *dev, u16 queue_index) -+{ -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue_index); -+#ifdef CONFIG_NETPOLL_TRAP -+ if (netpoll_trap()) -+ return; ++#ifdef CONFIG_WATCHDOG_NOWAYOUT ++module_param(nowayout, int, 0); ++MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started " ++ "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); +#endif -+ if (test_and_clear_bit(__QUEUE_STATE_XOFF, &txq->state)) -+ __netif_schedule(txq->qdisc); -+} + -+/** -+ * netif_is_multiqueue - test if device has multiple transmit queues -+ * @dev: network device -+ * -+ * Check if device has multiple transmit queues -+ */ -+static inline int netif_is_multiqueue(const struct net_device *dev) -+{ -+ return (dev->num_tx_queues > 1); -+} ++static unsigned long wdt_flags; + -+extern void netif_set_real_num_tx_queues(struct net_device *dev, -+ unsigned int txq); ++#define WDT_FLAGS_BUSY 0 ++#define WDT_FLAGS_EXPECT_CLOSE 1 + -+/* Use this variant when it is known for sure that it -+ * is executing from hardware interrupt context or with hardware interrupts -+ * disabled. -+ */ -+extern void dev_kfree_skb_irq(struct sk_buff *skb); ++static int wdt_timeout = WDT_TIMEOUT; ++static int boot_status; ++static int max_timeout; + -+/* Use this variant in places where it could be invoked -+ * from either hardware interrupt or other context, with hardware interrupts -+ * either disabled or enabled. -+ */ -+extern void dev_kfree_skb_any(struct sk_buff *skb); -+ -+#define HAVE_NETIF_RX 1 -+extern int netif_rx(struct sk_buff *skb); -+extern int netif_rx_ni(struct sk_buff *skb); -+#define HAVE_NETIF_RECEIVE_SKB 1 -+extern int netif_receive_skb(struct sk_buff *skb); -+extern gro_result_t dev_gro_receive(struct napi_struct *napi, -+ struct sk_buff *skb); -+extern gro_result_t napi_skb_finish(gro_result_t ret, struct sk_buff *skb); -+extern gro_result_t napi_gro_receive(struct napi_struct *napi, -+ struct sk_buff *skb); -+extern void napi_reuse_skb(struct napi_struct *napi, -+ struct sk_buff *skb); -+extern struct sk_buff * napi_get_frags(struct napi_struct *napi); -+extern gro_result_t napi_frags_finish(struct napi_struct *napi, -+ struct sk_buff *skb, -+ gro_result_t ret); -+extern struct sk_buff * napi_frags_skb(struct napi_struct *napi); -+extern gro_result_t napi_gro_frags(struct napi_struct *napi); -+ -+static inline void napi_free_frags(struct napi_struct *napi) -+{ -+ kfree_skb(napi->skb); -+ napi->skb = NULL; -+} -+ -+extern void netif_nit_deliver(struct sk_buff *skb); -+extern int dev_valid_name(const char *name); -+extern int dev_ioctl(struct net *net, unsigned int cmd, void __user *); -+extern int dev_ethtool(struct net *net, struct ifreq *); -+extern unsigned dev_get_flags(const struct net_device *); -+extern int __dev_change_flags(struct net_device *, unsigned int flags); -+extern int dev_change_flags(struct net_device *, unsigned); -+extern void __dev_notify_flags(struct net_device *, unsigned int old_flags); -+extern int dev_change_name(struct net_device *, const char *); -+extern int dev_set_alias(struct net_device *, const char *, size_t); -+extern int dev_change_net_namespace(struct net_device *, -+ struct net *, const char *); -+extern int dev_set_mtu(struct net_device *, int); -+extern int dev_set_mac_address(struct net_device *, -+ struct sockaddr *); -+extern int dev_hard_start_xmit(struct sk_buff *skb, -+ struct net_device *dev, -+ struct netdev_queue *txq); -+extern int dev_forward_skb(struct net_device *dev, -+ struct sk_buff *skb); -+ -+extern int netdev_budget; -+ -+/* Called by rtnetlink.c:rtnl_unlock() */ -+extern void netdev_run_todo(void); -+ -+/** -+ * dev_put - release reference to device -+ * @dev: network device -+ * -+ * Release reference to device to allow it to be freed. -+ */ -+static inline void dev_put(struct net_device *dev) ++static void inline ar71xx_wdt_keepalive(void) +{ -+ atomic_dec(&dev->refcnt); ++ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG, ar71xx_ahb_freq * wdt_timeout); +} + -+/** -+ * dev_hold - get reference to device -+ * @dev: network device -+ * -+ * Hold reference to device to keep it from being freed. -+ */ -+static inline void dev_hold(struct net_device *dev) ++static void inline ar71xx_wdt_enable(void) +{ -+ atomic_inc(&dev->refcnt); ++ printk(KERN_DEBUG DRV_NAME ": enabling watchdog timer\n"); ++ ar71xx_wdt_keepalive(); ++ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_FCR); +} + -+/* Carrier loss detection, dial on demand. The functions netif_carrier_on -+ * and _off may be called from IRQ context, but it is caller -+ * who is responsible for serialization of these calls. -+ * -+ * The name carrier is inappropriate, these functions should really be -+ * called netif_lowerlayer_*() because they represent the state of any -+ * kind of lower layer not just hardware media. -+ */ -+ -+extern void linkwatch_fire_event(struct net_device *dev); -+extern void linkwatch_forget_dev(struct net_device *dev); -+ -+/** -+ * netif_carrier_ok - test if carrier present -+ * @dev: network device -+ * -+ * Check if carrier is present on device -+ */ -+static inline int netif_carrier_ok(const struct net_device *dev) ++static void inline ar71xx_wdt_disable(void) +{ -+ return !test_bit(__LINK_STATE_NOCARRIER, &dev->state); ++ printk(KERN_DEBUG DRV_NAME ": disabling watchdog timer\n"); ++ ar71xx_reset_wr(AR71XX_RESET_REG_WDOG_CTRL, WDOG_CTRL_ACTION_NONE); +} + -+extern unsigned long dev_trans_start(struct net_device *dev); -+ -+extern void __netdev_watchdog_up(struct net_device *dev); -+ -+extern void netif_carrier_on(struct net_device *dev); ++static int ar71xx_wdt_set_timeout(int val) ++{ ++ if (val < 1 || val > max_timeout) ++ return -EINVAL; + -+extern void netif_carrier_off(struct net_device *dev); ++ wdt_timeout = val; ++ ar71xx_wdt_keepalive(); + -+extern void netif_notify_peers(struct net_device *dev); ++ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs\n", wdt_timeout); + -+/** -+ * netif_dormant_on - mark device as dormant. -+ * @dev: network device -+ * -+ * Mark device as dormant (as per RFC2863). -+ * -+ * The dormant state indicates that the relevant interface is not -+ * actually in a condition to pass packets (i.e., it is not 'up') but is -+ * in a "pending" state, waiting for some external event. For "on- -+ * demand" interfaces, this new state identifies the situation where the -+ * interface is waiting for events to place it in the up state. -+ * -+ */ -+static inline void netif_dormant_on(struct net_device *dev) -+{ -+ if (!test_and_set_bit(__LINK_STATE_DORMANT, &dev->state)) -+ linkwatch_fire_event(dev); ++ return 0; +} + -+/** -+ * netif_dormant_off - set device as not dormant. -+ * @dev: network device -+ * -+ * Device is not in dormant state. -+ */ -+static inline void netif_dormant_off(struct net_device *dev) ++static int ar71xx_wdt_open(struct inode *inode, struct file *file) +{ -+ if (test_and_clear_bit(__LINK_STATE_DORMANT, &dev->state)) -+ linkwatch_fire_event(dev); -+} ++ if (test_and_set_bit(WDT_FLAGS_BUSY, &wdt_flags)) ++ return -EBUSY; + -+/** -+ * netif_dormant - test if carrier present -+ * @dev: network device -+ * -+ * Check if carrier is present on device -+ */ -+static inline int netif_dormant(const struct net_device *dev) -+{ -+ return test_bit(__LINK_STATE_DORMANT, &dev->state); -+} ++ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + ++ ar71xx_wdt_enable(); + -+/** -+ * netif_oper_up - test if device is operational -+ * @dev: network device -+ * -+ * Check if carrier is operational -+ */ -+static inline int netif_oper_up(const struct net_device *dev) -+{ -+ return (dev->operstate == IF_OPER_UP || -+ dev->operstate == IF_OPER_UNKNOWN /* backward compat */); ++ return nonseekable_open(inode, file); +} + -+/** -+ * netif_device_present - is device available or removed -+ * @dev: network device -+ * -+ * Check if device has not been removed from system. -+ */ -+static inline int netif_device_present(struct net_device *dev) ++static int ar71xx_wdt_release(struct inode *inode, struct file *file) +{ -+ return test_bit(__LINK_STATE_PRESENT, &dev->state); -+} -+ -+extern void netif_device_detach(struct net_device *dev); -+ -+extern void netif_device_attach(struct net_device *dev); ++ if (test_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags)) { ++ ar71xx_wdt_disable(); ++ } else { ++ printk(KERN_CRIT DRV_NAME ": device closed unexpectedly, " ++ "watchdog timer will not stop!\n"); ++ } + -+/* -+ * Network interface message level settings -+ */ -+#define HAVE_NETIF_MSG 1 -+ -+enum { -+ NETIF_MSG_DRV = 0x0001, -+ NETIF_MSG_PROBE = 0x0002, -+ NETIF_MSG_LINK = 0x0004, -+ NETIF_MSG_TIMER = 0x0008, -+ NETIF_MSG_IFDOWN = 0x0010, -+ NETIF_MSG_IFUP = 0x0020, -+ NETIF_MSG_RX_ERR = 0x0040, -+ NETIF_MSG_TX_ERR = 0x0080, -+ NETIF_MSG_TX_QUEUED = 0x0100, -+ NETIF_MSG_INTR = 0x0200, -+ NETIF_MSG_TX_DONE = 0x0400, -+ NETIF_MSG_RX_STATUS = 0x0800, -+ NETIF_MSG_PKTDATA = 0x1000, -+ NETIF_MSG_HW = 0x2000, -+ NETIF_MSG_WOL = 0x4000, -+}; -+ -+#define netif_msg_drv(p) ((p)->msg_enable & NETIF_MSG_DRV) -+#define netif_msg_probe(p) ((p)->msg_enable & NETIF_MSG_PROBE) -+#define netif_msg_link(p) ((p)->msg_enable & NETIF_MSG_LINK) -+#define netif_msg_timer(p) ((p)->msg_enable & NETIF_MSG_TIMER) -+#define netif_msg_ifdown(p) ((p)->msg_enable & NETIF_MSG_IFDOWN) -+#define netif_msg_ifup(p) ((p)->msg_enable & NETIF_MSG_IFUP) -+#define netif_msg_rx_err(p) ((p)->msg_enable & NETIF_MSG_RX_ERR) -+#define netif_msg_tx_err(p) ((p)->msg_enable & NETIF_MSG_TX_ERR) -+#define netif_msg_tx_queued(p) ((p)->msg_enable & NETIF_MSG_TX_QUEUED) -+#define netif_msg_intr(p) ((p)->msg_enable & NETIF_MSG_INTR) -+#define netif_msg_tx_done(p) ((p)->msg_enable & NETIF_MSG_TX_DONE) -+#define netif_msg_rx_status(p) ((p)->msg_enable & NETIF_MSG_RX_STATUS) -+#define netif_msg_pktdata(p) ((p)->msg_enable & NETIF_MSG_PKTDATA) -+#define netif_msg_hw(p) ((p)->msg_enable & NETIF_MSG_HW) -+#define netif_msg_wol(p) ((p)->msg_enable & NETIF_MSG_WOL) -+ -+static inline u32 netif_msg_init(int debug_value, int default_msg_enable_bits) -+{ -+ /* use default */ -+ if (debug_value < 0 || debug_value >= (sizeof(u32) * 8)) -+ return default_msg_enable_bits; -+ if (debug_value == 0) /* no output */ -+ return 0; -+ /* set low N bits */ -+ return (1 << debug_value) - 1; -+} ++ clear_bit(WDT_FLAGS_BUSY, &wdt_flags); ++ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + -+static inline void __netif_tx_lock(struct netdev_queue *txq, int cpu) -+{ -+ spin_lock(&txq->_xmit_lock); -+ txq->xmit_lock_owner = cpu; ++ return 0; +} + -+static inline void __netif_tx_lock_bh(struct netdev_queue *txq) ++static ssize_t ar71xx_wdt_write(struct file *file, const char *data, ++ size_t len, loff_t *ppos) +{ -+ spin_lock_bh(&txq->_xmit_lock); -+ txq->xmit_lock_owner = smp_processor_id(); -+} ++ if (len) { ++ if (!nowayout) { ++ size_t i; + -+static inline int __netif_tx_trylock(struct netdev_queue *txq) -+{ -+ int ok = spin_trylock(&txq->_xmit_lock); -+ if (likely(ok)) -+ txq->xmit_lock_owner = smp_processor_id(); -+ return ok; -+} ++ clear_bit(WDT_FLAGS_EXPECT_CLOSE, &wdt_flags); + -+static inline void __netif_tx_unlock(struct netdev_queue *txq) -+{ -+ txq->xmit_lock_owner = -1; -+ spin_unlock(&txq->_xmit_lock); -+} ++ for (i = 0; i != len; i++) { ++ char c; + -+static inline void __netif_tx_unlock_bh(struct netdev_queue *txq) -+{ -+ txq->xmit_lock_owner = -1; -+ spin_unlock_bh(&txq->_xmit_lock); -+} ++ if (get_user(c, data + i)) ++ return -EFAULT; + -+static inline void txq_trans_update(struct netdev_queue *txq) -+{ -+ if (txq->xmit_lock_owner != -1) -+ txq->trans_start = jiffies; -+} ++ if (c == 'V') ++ set_bit(WDT_FLAGS_EXPECT_CLOSE, ++ &wdt_flags); ++ } ++ } + -+/** -+ * netif_tx_lock - grab network device transmit lock -+ * @dev: network device -+ * -+ * Get network device transmit lock -+ */ -+static inline void netif_tx_lock(struct net_device *dev) -+{ -+ unsigned int i; -+ int cpu; -+ -+ spin_lock(&dev->tx_global_lock); -+ cpu = smp_processor_id(); -+ for (i = 0; i < dev->num_tx_queues; i++) { -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, i); -+ -+ /* We are the only thread of execution doing a -+ * freeze, but we have to grab the _xmit_lock in -+ * order to synchronize with threads which are in -+ * the ->hard_start_xmit() handler and already -+ * checked the frozen bit. -+ */ -+ __netif_tx_lock(txq, cpu); -+ set_bit(__QUEUE_STATE_FROZEN, &txq->state); -+ __netif_tx_unlock(txq); ++ ar71xx_wdt_keepalive(); + } -+} + -+static inline void netif_tx_lock_bh(struct net_device *dev) -+{ -+ local_bh_disable(); -+ netif_tx_lock(dev); ++ return len; +} + -+static inline void netif_tx_unlock(struct net_device *dev) ++static struct watchdog_info ar71xx_wdt_info = { ++ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | ++ WDIOF_MAGICCLOSE | WDIOF_CARDRESET, ++ .firmware_version = 0, ++ .identity = "AR71XX watchdog", ++}; ++ ++static int ar71xx_wdt_ioctl(struct inode *inode, struct file *file, ++ unsigned int cmd, unsigned long arg) +{ -+ unsigned int i; ++ int t; ++ int ret; + -+ for (i = 0; i < dev->num_tx_queues; i++) { -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, i); ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ ret = copy_to_user((struct watchdog_info *)arg, ++ &ar71xx_wdt_info, ++ sizeof(&ar71xx_wdt_info)) ? -EFAULT : 0; ++ break; + -+ /* No need to grab the _xmit_lock here. If the -+ * queue is not stopped for another reason, we -+ * force a schedule. -+ */ -+ clear_bit(__QUEUE_STATE_FROZEN, &txq->state); -+ netif_schedule_queue(txq); -+ } -+ spin_unlock(&dev->tx_global_lock); -+} ++ case WDIOC_GETSTATUS: ++ ret = put_user(0, (int *)arg) ? -EFAULT : 0; ++ break; + -+static inline void netif_tx_unlock_bh(struct net_device *dev) -+{ -+ netif_tx_unlock(dev); -+ local_bh_enable(); -+} ++ case WDIOC_GETBOOTSTATUS: ++ ret = put_user(boot_status, (int *)arg) ? -EFAULT : 0; ++ break; + -+#define HARD_TX_LOCK(dev, txq, cpu) { \ -+ if ((dev->features & NETIF_F_LLTX) == 0) { \ -+ __netif_tx_lock(txq, cpu); \ -+ } \ -+} ++ case WDIOC_KEEPALIVE: ++ ar71xx_wdt_keepalive(); ++ ret = 0; ++ break; + -+#define HARD_TX_UNLOCK(dev, txq) { \ -+ if ((dev->features & NETIF_F_LLTX) == 0) { \ -+ __netif_tx_unlock(txq); \ -+ } \ -+} ++ case WDIOC_SETTIMEOUT: ++ ret = get_user(t, (int *)arg) ? -EFAULT : 0; ++ if (ret) ++ break; + -+static inline void netif_tx_disable(struct net_device *dev) -+{ -+ unsigned int i; -+ int cpu; ++ ret = ar71xx_wdt_set_timeout(t); ++ if (ret) ++ break; + -+ local_bh_disable(); -+ cpu = smp_processor_id(); -+ for (i = 0; i < dev->num_tx_queues; i++) { -+ struct netdev_queue *txq = netdev_get_tx_queue(dev, i); ++ /* fallthrough */ ++ case WDIOC_GETTIMEOUT: ++ ret = put_user(wdt_timeout, (int *)arg) ? -EFAULT : 0; ++ break; + -+ __netif_tx_lock(txq, cpu); -+ netif_tx_stop_queue(txq); -+ __netif_tx_unlock(txq); ++ default: ++ ret = -ENOTTY; ++ break; + } -+ local_bh_enable(); -+} -+ -+static inline void netif_addr_lock(struct net_device *dev) -+{ -+ spin_lock(&dev->addr_list_lock); -+} + -+static inline void netif_addr_lock_bh(struct net_device *dev) -+{ -+ spin_lock_bh(&dev->addr_list_lock); ++ return ret; +} + -+static inline void netif_addr_unlock(struct net_device *dev) -+{ -+ spin_unlock(&dev->addr_list_lock); -+} ++static const struct file_operations ar71xx_wdt_fops = { ++ .owner = THIS_MODULE, ++ .write = ar71xx_wdt_write, ++ .ioctl = ar71xx_wdt_ioctl, ++ .open = ar71xx_wdt_open, ++ .release = ar71xx_wdt_release, ++}; + -+static inline void netif_addr_unlock_bh(struct net_device *dev) -+{ -+ spin_unlock_bh(&dev->addr_list_lock); -+} ++static struct miscdevice ar71xx_wdt_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &ar71xx_wdt_fops, ++}; + -+/* -+ * dev_addrs walker. Should be used only for read access. Call with -+ * rcu_read_lock held. -+ */ -+#define for_each_dev_addr(dev, ha) \ -+ list_for_each_entry_rcu(ha, &dev->dev_addrs.list, list) -+ -+/* These functions live elsewhere (drivers/net/net_init.c, but related) */ -+ -+extern void ether_setup(struct net_device *dev); -+ -+/* Support for loadable net-drivers */ -+extern struct net_device *alloc_netdev_mq(int sizeof_priv, const char *name, -+ void (*setup)(struct net_device *), -+ unsigned int queue_count); -+#define alloc_netdev(sizeof_priv, name, setup) \ -+ alloc_netdev_mq(sizeof_priv, name, setup, 1) -+extern int register_netdev(struct net_device *dev); -+extern void unregister_netdev(struct net_device *dev); -+ -+/* General hardware address lists handling functions */ -+extern int __hw_addr_add_multiple(struct netdev_hw_addr_list *to_list, -+ struct netdev_hw_addr_list *from_list, -+ int addr_len, unsigned char addr_type); -+extern void __hw_addr_del_multiple(struct netdev_hw_addr_list *to_list, -+ struct netdev_hw_addr_list *from_list, -+ int addr_len, unsigned char addr_type); -+extern int __hw_addr_sync(struct netdev_hw_addr_list *to_list, -+ struct netdev_hw_addr_list *from_list, -+ int addr_len); -+extern void __hw_addr_unsync(struct netdev_hw_addr_list *to_list, -+ struct netdev_hw_addr_list *from_list, -+ int addr_len); -+extern void __hw_addr_flush(struct netdev_hw_addr_list *list); -+extern void __hw_addr_init(struct netdev_hw_addr_list *list); -+ -+/* Functions used for device addresses handling */ -+extern int dev_addr_add(struct net_device *dev, unsigned char *addr, -+ unsigned char addr_type); -+extern int dev_addr_del(struct net_device *dev, unsigned char *addr, -+ unsigned char addr_type); -+extern int dev_addr_add_multiple(struct net_device *to_dev, -+ struct net_device *from_dev, -+ unsigned char addr_type); -+extern int dev_addr_del_multiple(struct net_device *to_dev, -+ struct net_device *from_dev, -+ unsigned char addr_type); -+extern void dev_addr_flush(struct net_device *dev); -+extern int dev_addr_init(struct net_device *dev); -+ -+/* Functions used for unicast addresses handling */ -+extern int dev_uc_add(struct net_device *dev, unsigned char *addr); -+extern int dev_uc_del(struct net_device *dev, unsigned char *addr); -+extern int dev_uc_sync(struct net_device *to, struct net_device *from); -+extern void dev_uc_unsync(struct net_device *to, struct net_device *from); -+extern void dev_uc_flush(struct net_device *dev); -+extern void dev_uc_init(struct net_device *dev); -+ -+/* Functions used for multicast addresses handling */ -+extern int dev_mc_add(struct net_device *dev, unsigned char *addr); -+extern int dev_mc_add_global(struct net_device *dev, unsigned char *addr); -+extern int dev_mc_del(struct net_device *dev, unsigned char *addr); -+extern int dev_mc_del_global(struct net_device *dev, unsigned char *addr); -+extern int dev_mc_sync(struct net_device *to, struct net_device *from); -+extern void dev_mc_unsync(struct net_device *to, struct net_device *from); -+extern void dev_mc_flush(struct net_device *dev); -+extern void dev_mc_init(struct net_device *dev); -+ -+/* Functions used for secondary unicast and multicast support */ -+extern void dev_set_rx_mode(struct net_device *dev); -+extern void __dev_set_rx_mode(struct net_device *dev); -+extern int dev_set_promiscuity(struct net_device *dev, int inc); -+extern int dev_set_allmulti(struct net_device *dev, int inc); -+extern void netdev_state_change(struct net_device *dev); -+extern int netdev_bonding_change(struct net_device *dev, -+ unsigned long event); -+extern void netdev_features_change(struct net_device *dev); -+/* Load a device via the kmod */ -+extern void dev_load(struct net *net, const char *name); -+extern void dev_mcast_init(void); -+extern const struct net_device_stats *dev_get_stats(struct net_device *dev); -+extern void dev_txq_stats_fold(const struct net_device *dev, struct net_device_stats *stats); -+ -+extern int netdev_max_backlog; -+extern int netdev_tstamp_prequeue; -+extern int weight_p; -+extern int netdev_set_master(struct net_device *dev, struct net_device *master); -+extern int skb_checksum_help(struct sk_buff *skb); -+extern struct sk_buff *skb_gso_segment(struct sk_buff *skb, int features); -+#ifdef CONFIG_BUG -+extern void netdev_rx_csum_fault(struct net_device *dev); -+#else -+static inline void netdev_rx_csum_fault(struct net_device *dev) ++static int __devinit ar71xx_wdt_probe(struct platform_device *pdev) +{ -+} -+#endif -+/* rx skb timestamps */ -+extern void net_enable_timestamp(void); -+extern void net_disable_timestamp(void); -+ -+#ifdef CONFIG_PROC_FS -+extern void *dev_seq_start(struct seq_file *seq, loff_t *pos); -+extern void *dev_seq_next(struct seq_file *seq, void *v, loff_t *pos); -+extern void dev_seq_stop(struct seq_file *seq, void *v); -+#endif -+ -+extern int netdev_class_create_file(struct class_attribute *class_attr); -+extern void netdev_class_remove_file(struct class_attribute *class_attr); -+ -+extern char *netdev_drivername(const struct net_device *dev, char *buffer, int len); ++ int ret; + -+extern void linkwatch_run_queue(void); ++ max_timeout = (0xfffffffful / ar71xx_ahb_freq); ++ wdt_timeout = (max_timeout < WDT_TIMEOUT) ? max_timeout : WDT_TIMEOUT; + -+unsigned long netdev_increment_features(unsigned long all, unsigned long one, -+ unsigned long mask); -+unsigned long netdev_fix_features(unsigned long features, const char *name); ++ boot_status = ++ (ar71xx_reset_rr(AR71XX_RESET_REG_WDOG_CTRL) & WDOG_CTRL_LAST_RESET) ? ++ WDIOF_CARDRESET : 0; + -+void netif_stacked_transfer_operstate(const struct net_device *rootdev, -+ struct net_device *dev); ++ ret = misc_register(&ar71xx_wdt_miscdev); ++ if (ret) ++ goto err_out; + -+static inline int net_gso_ok(int features, int gso_type) -+{ -+ int feature = gso_type << NETIF_F_GSO_SHIFT; -+ return (features & feature) == feature; -+} ++ printk(KERN_INFO DRV_DESC " version " DRV_VERSION "\n"); + -+static inline int skb_gso_ok(struct sk_buff *skb, int features) -+{ -+ return net_gso_ok(features, skb_shinfo(skb)->gso_type) && -+ (!skb_has_frags(skb) || (features & NETIF_F_FRAGLIST)); -+} ++ printk(KERN_DEBUG DRV_NAME ": timeout=%d secs (max=%d)\n", ++ wdt_timeout, max_timeout); + -+static inline int netif_needs_gso(struct net_device *dev, struct sk_buff *skb) -+{ -+ return skb_is_gso(skb) && -+ (!skb_gso_ok(skb, dev->features) || -+ unlikely(skb->ip_summed != CHECKSUM_PARTIAL)); -+} ++ return 0; + -+static inline void netif_set_gso_max_size(struct net_device *dev, -+ unsigned int size) -+{ -+ dev->gso_max_size = size; ++err_out: ++ return ret; +} + -+extern int __skb_bond_should_drop(struct sk_buff *skb, -+ struct net_device *master); -+ -+static inline int skb_bond_should_drop(struct sk_buff *skb, -+ struct net_device *master) ++static int __devexit ar71xx_wdt_remove(struct platform_device *pdev) +{ -+ if (master) -+ return __skb_bond_should_drop(skb, master); ++ misc_deregister(&ar71xx_wdt_miscdev); + return 0; +} + -+extern struct pernet_operations __net_initdata loopback_net_ops; ++static struct platform_driver ar71xx_wdt_driver = { ++ .probe = ar71xx_wdt_probe, ++ .remove = __devexit_p(ar71xx_wdt_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; + -+static inline int dev_ethtool_get_settings(struct net_device *dev, -+ struct ethtool_cmd *cmd) ++static int __init ar71xx_wdt_init(void) +{ -+ if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings) -+ return -EOPNOTSUPP; -+ return dev->ethtool_ops->get_settings(dev, cmd); ++ return platform_driver_register(&ar71xx_wdt_driver); +} ++module_init(ar71xx_wdt_init); + -+static inline u32 dev_ethtool_get_rx_csum(struct net_device *dev) ++static void __exit ar71xx_wdt_exit(void) +{ -+ if (!dev->ethtool_ops || !dev->ethtool_ops->get_rx_csum) -+ return 0; -+ return dev->ethtool_ops->get_rx_csum(dev); ++ platform_driver_unregister(&ar71xx_wdt_driver); +} ++module_exit(ar71xx_wdt_exit); + -+static inline u32 dev_ethtool_get_flags(struct net_device *dev) -+{ -+ if (!dev->ethtool_ops || !dev->ethtool_ops->get_flags) -+ return 0; -+ return dev->ethtool_ops->get_flags(dev); -+} -+ -+/* Logging, debugging and troubleshooting/diagnostic helpers. */ -+ -+/* netdev_printk helpers, similar to dev_printk */ -+ -+static inline const char *netdev_name(const struct net_device *dev) -+{ -+ if (dev->reg_state != NETREG_REGISTERED) -+ return "(unregistered net_device)"; -+ return dev->name; -+} -+ -+#define netdev_printk(level, netdev, format, args...) \ -+ dev_printk(level, (netdev)->dev.parent, \ -+ "%s: " format, \ -+ netdev_name(netdev), ##args) -+ -+#define netdev_emerg(dev, format, args...) \ -+ netdev_printk(KERN_EMERG, dev, format, ##args) -+#define netdev_alert(dev, format, args...) \ -+ netdev_printk(KERN_ALERT, dev, format, ##args) -+#define netdev_crit(dev, format, args...) \ -+ netdev_printk(KERN_CRIT, dev, format, ##args) -+#define netdev_err(dev, format, args...) \ -+ netdev_printk(KERN_ERR, dev, format, ##args) -+#define netdev_warn(dev, format, args...) \ -+ netdev_printk(KERN_WARNING, dev, format, ##args) -+#define netdev_notice(dev, format, args...) \ -+ netdev_printk(KERN_NOTICE, dev, format, ##args) -+#define netdev_info(dev, format, args...) \ -+ netdev_printk(KERN_INFO, dev, format, ##args) -+ -+#if defined(DEBUG) -+#define netdev_dbg(__dev, format, args...) \ -+ netdev_printk(KERN_DEBUG, __dev, format, ##args) -+#elif defined(CONFIG_DYNAMIC_DEBUG) -+#define netdev_dbg(__dev, format, args...) \ -+do { \ -+ dynamic_dev_dbg((__dev)->dev.parent, "%s: " format, \ -+ netdev_name(__dev), ##args); \ -+} while (0) -+#else -+#define netdev_dbg(__dev, format, args...) \ -+({ \ -+ if (0) \ -+ netdev_printk(KERN_DEBUG, __dev, format, ##args); \ -+ 0; \ -+}) -+#endif -+ -+#if defined(VERBOSE_DEBUG) -+#define netdev_vdbg netdev_dbg -+#else -+ -+#define netdev_vdbg(dev, format, args...) \ -+({ \ -+ if (0) \ -+ netdev_printk(KERN_DEBUG, dev, format, ##args); \ -+ 0; \ -+}) -+#endif ++MODULE_DESCRIPTION(DRV_DESC); ++MODULE_VERSION(DRV_VERSION); ++MODULE_AUTHOR("Gabor Juhos +- * Copyright (c) 2009 Imre Kaloz ++ * ath9k platform data defines + * +- * Permission to use, copy, modify, and/or distribute this software for any +- * purpose with or without fee is hereby granted, provided that the above +- * copyright notice and this permission notice appear in all copies. ++ * Copyright (C) 2008 Gabor Juhos + * +- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. + */ + + #ifndef _LINUX_ATH9K_PLATFORM_H +@@ -23,6 +15,9 @@ + + struct ath9k_platform_data { + u16 eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS]; ++ u8 *macaddr; + ++ unsigned long quirk_wndr3700:1; + }; + + #endif /* _LINUX_ATH9K_PLATFORM_H */ +diff -Nur linux-2.6.36.orig/include/linux/gpio_buttons.h linux-2.6.36/include/linux/gpio_buttons.h +--- linux-2.6.36.orig/include/linux/gpio_buttons.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/include/linux/gpio_buttons.h 2010-11-18 21:16:18.000000000 +0100 +@@ -0,0 +1,33 @@ +/* -+ * netdev_WARN() acts like dev_printk(), but with the key difference -+ * of using a WARN/WARN_ON to get the message out, including the -+ * file/line information and a backtrace. ++ * Definitions for the GPIO buttons interface driver ++ * ++ * Copyright (C) 2007-2010 Gabor Juhos ++ * ++ * This file was based on: /include/linux/gpio_keys.h ++ * The original gpio_keys.h seems not to have a license. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * + */ -+#define netdev_WARN(dev, format, args...) \ -+ WARN(1, "netdevice: %s\n" format, netdev_name(dev), ##args); + -+/* netif printk helpers, similar to netdev_printk */ ++#ifndef _GPIO_BUTTONS_H_ ++#define _GPIO_BUTTONS_H_ + -+#define netif_printk(priv, type, level, dev, fmt, args...) \ -+do { \ -+ if (netif_msg_##type(priv)) \ -+ netdev_printk(level, (dev), fmt, ##args); \ -+} while (0) ++struct gpio_button { ++ int gpio; /* GPIO line number */ ++ int active_low; ++ char *desc; /* button description */ ++ int type; /* input event type (EV_KEY, EV_SW) */ ++ int code; /* input event code (KEY_*, SW_*) */ ++ int threshold; /* count threshold */ ++}; + -+#define netif_emerg(priv, type, dev, fmt, args...) \ -+ netif_printk(priv, type, KERN_EMERG, dev, fmt, ##args) -+#define netif_alert(priv, type, dev, fmt, args...) \ -+ netif_printk(priv, type, KERN_ALERT, dev, fmt, ##args) -+#define netif_crit(priv, type, dev, fmt, args...) \ -+ netif_printk(priv, type, KERN_CRIT, dev, fmt, ##args) -+#define netif_err(priv, type, dev, fmt, args...) \ -+ netif_printk(priv, type, KERN_ERR, dev, fmt, ##args) -+#define netif_warn(priv, type, dev, fmt, args...) \ -+ netif_printk(priv, type, KERN_WARNING, dev, fmt, ##args) -+#define netif_notice(priv, type, dev, fmt, args...) \ -+ netif_printk(priv, type, KERN_NOTICE, dev, fmt, ##args) -+#define netif_info(priv, type, dev, fmt, args...) \ -+ netif_printk(priv, type, KERN_INFO, (dev), fmt, ##args) -+ -+#if defined(DEBUG) -+#define netif_dbg(priv, type, dev, format, args...) \ -+ netif_printk(priv, type, KERN_DEBUG, dev, format, ##args) -+#elif defined(CONFIG_DYNAMIC_DEBUG) -+#define netif_dbg(priv, type, netdev, format, args...) \ -+do { \ -+ if (netif_msg_##type(priv)) \ -+ dynamic_dev_dbg((netdev)->dev.parent, \ -+ "%s: " format, \ -+ netdev_name(netdev), ##args); \ -+} while (0) -+#else -+#define netif_dbg(priv, type, dev, format, args...) \ -+({ \ -+ if (0) \ -+ netif_printk(priv, type, KERN_DEBUG, dev, format, ##args); \ -+ 0; \ -+}) -+#endif ++struct gpio_buttons_platform_data { ++ struct gpio_button *buttons; ++ int nbuttons; /* number of buttons */ ++ int poll_interval; /* polling interval */ ++}; + -+#if defined(VERBOSE_DEBUG) -+#define netif_vdbg netif_dbg -+#else -+#define netif_vdbg(priv, type, dev, format, args...) \ -+({ \ -+ if (0) \ -+ netif_printk(priv, type, KERN_DEBUG, dev, format, ##args); \ -+ 0; \ -+}) -+#endif ++#endif /* _GPIO_BUTTONS_H_ */ +diff -Nur linux-2.6.36.orig/include/linux/gpio_dev.h linux-2.6.36/include/linux/gpio_dev.h +--- linux-2.6.36.orig/include/linux/gpio_dev.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/include/linux/gpio_dev.h 2010-11-18 21:16:18.000000000 +0100 +@@ -0,0 +1,11 @@ ++#ifndef _GPIODEV_H__ ++#define _GPIODEV_H__ + -+#endif /* __KERNEL__ */ ++#define IOC_GPIODEV_MAGIC 'B' ++#define GPIO_GET _IO(IOC_GPIODEV_MAGIC, 10) ++#define GPIO_SET _IO(IOC_GPIODEV_MAGIC, 11) ++#define GPIO_CLEAR _IO(IOC_GPIODEV_MAGIC, 12) ++#define GPIO_DIR_IN _IO(IOC_GPIODEV_MAGIC, 13) ++#define GPIO_DIR_OUT _IO(IOC_GPIODEV_MAGIC, 14) + -+#endif /* _LINUX_NETDEVICE_H */ -diff -Nur linux-2.6.35.7.orig/include/linux/nxp_74hc153.h linux-2.6.35.7/include/linux/nxp_74hc153.h ---- linux-2.6.35.7.orig/include/linux/nxp_74hc153.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/include/linux/nxp_74hc153.h 2010-10-14 20:28:01.798101112 +0200 ++#endif +diff -Nur linux-2.6.36.orig/include/linux/netdevice.h linux-2.6.36/include/linux/netdevice.h +--- linux-2.6.36.orig/include/linux/netdevice.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/include/linux/netdevice.h 2010-11-18 21:16:18.000000000 +0100 +@@ -949,6 +949,7 @@ + void *ax25_ptr; /* AX.25 specific data */ + struct wireless_dev *ieee80211_ptr; /* IEEE 802.11 specific data, + assign before registering */ ++ void *phy_ptr; /* PHY device specific data */ + + /* + * Cache line mostly used on receive path (including eth_type_trans()) +diff -Nur linux-2.6.36.orig/include/linux/nxp_74hc153.h linux-2.6.36/include/linux/nxp_74hc153.h +--- linux-2.6.36.orig/include/linux/nxp_74hc153.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/include/linux/nxp_74hc153.h 2010-11-18 21:16:19.000000000 +0100 @@ -0,0 +1,24 @@ +/* + * NXP 74HC153 - Dual 4-input multiplexer defines @@ -32470,10 +17440,10 @@ diff -Nur linux-2.6.35.7.orig/include/linux/nxp_74hc153.h linux-2.6.35.7/include +}; + +#endif /* _NXP_74HC153_H */ -diff -Nur linux-2.6.35.7.orig/include/linux/phy.h linux-2.6.35.7/include/linux/phy.h ---- linux-2.6.35.7.orig/include/linux/phy.h 2010-09-29 03:09:08.000000000 +0200 -+++ linux-2.6.35.7/include/linux/phy.h 2010-10-14 20:28:01.834368168 +0200 -@@ -330,6 +330,20 @@ +diff -Nur linux-2.6.36.orig/include/linux/phy.h linux-2.6.36/include/linux/phy.h +--- linux-2.6.36.orig/include/linux/phy.h 2010-10-20 22:30:22.000000000 +0200 ++++ linux-2.6.36/include/linux/phy.h 2010-11-18 21:16:19.000000000 +0100 +@@ -332,6 +332,20 @@ void (*adjust_link)(struct net_device *dev); void (*adjust_state)(struct net_device *dev); @@ -32494,540 +17464,17 @@ diff -Nur linux-2.6.35.7.orig/include/linux/phy.h linux-2.6.35.7/include/linux/p }; #define to_phy_device(d) container_of(d, struct phy_device, dev) -@@ -497,6 +511,7 @@ +@@ -519,6 +533,7 @@ void phy_stop_machine(struct phy_device *phydev); int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); +int phy_ethtool_ioctl(struct phy_device *phydev, void *useraddr); int phy_mii_ioctl(struct phy_device *phydev, - struct mii_ioctl_data *mii_data, int cmd); + struct ifreq *ifr, int cmd); int phy_start_interrupts(struct phy_device *phydev); -diff -Nur linux-2.6.35.7.orig/include/linux/phy.h.orig linux-2.6.35.7/include/linux/phy.h.orig ---- linux-2.6.35.7.orig/include/linux/phy.h.orig 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/include/linux/phy.h.orig 2010-09-29 03:09:08.000000000 +0200 -@@ -0,0 +1,519 @@ -+/* -+ * include/linux/phy.h -+ * -+ * Framework and drivers for configuring and reading different PHYs -+ * Based on code in sungem_phy.c and gianfar_phy.c -+ * -+ * Author: Andy Fleming -+ * -+ * Copyright (c) 2004 Freescale Semiconductor, Inc. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#ifndef __PHY_H -+#define __PHY_H -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#define PHY_BASIC_FEATURES (SUPPORTED_10baseT_Half | \ -+ SUPPORTED_10baseT_Full | \ -+ SUPPORTED_100baseT_Half | \ -+ SUPPORTED_100baseT_Full | \ -+ SUPPORTED_Autoneg | \ -+ SUPPORTED_TP | \ -+ SUPPORTED_MII) -+ -+#define PHY_GBIT_FEATURES (PHY_BASIC_FEATURES | \ -+ SUPPORTED_1000baseT_Half | \ -+ SUPPORTED_1000baseT_Full) -+ -+/* -+ * Set phydev->irq to PHY_POLL if interrupts are not supported, -+ * or not desired for this PHY. Set to PHY_IGNORE_INTERRUPT if -+ * the attached driver handles the interrupt -+ */ -+#define PHY_POLL -1 -+#define PHY_IGNORE_INTERRUPT -2 -+ -+#define PHY_HAS_INTERRUPT 0x00000001 -+#define PHY_HAS_MAGICANEG 0x00000002 -+ -+/* Interface Mode definitions */ -+typedef enum { -+ PHY_INTERFACE_MODE_MII, -+ PHY_INTERFACE_MODE_GMII, -+ PHY_INTERFACE_MODE_SGMII, -+ PHY_INTERFACE_MODE_TBI, -+ PHY_INTERFACE_MODE_RMII, -+ PHY_INTERFACE_MODE_RGMII, -+ PHY_INTERFACE_MODE_RGMII_ID, -+ PHY_INTERFACE_MODE_RGMII_RXID, -+ PHY_INTERFACE_MODE_RGMII_TXID, -+ PHY_INTERFACE_MODE_RTBI -+} phy_interface_t; -+ -+ -+#define PHY_INIT_TIMEOUT 100000 -+#define PHY_STATE_TIME 1 -+#define PHY_FORCE_TIMEOUT 10 -+#define PHY_AN_TIMEOUT 10 -+ -+#define PHY_MAX_ADDR 32 -+ -+/* Used when trying to connect to a specific phy (mii bus id:phy device id) */ -+#define PHY_ID_FMT "%s:%02x" -+ -+/* -+ * Need to be a little smaller than phydev->dev.bus_id to leave room -+ * for the ":%02x" -+ */ -+#define MII_BUS_ID_SIZE (20 - 3) -+ -+/* Or MII_ADDR_C45 into regnum for read/write on mii_bus to enable the 21 bit -+ IEEE 802.3ae clause 45 addressing mode used by 10GIGE phy chips. */ -+#define MII_ADDR_C45 (1<<30) -+ -+/* -+ * The Bus class for PHYs. Devices which provide access to -+ * PHYs should register using this structure -+ */ -+struct mii_bus { -+ const char *name; -+ char id[MII_BUS_ID_SIZE]; -+ void *priv; -+ int (*read)(struct mii_bus *bus, int phy_id, int regnum); -+ int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val); -+ int (*reset)(struct mii_bus *bus); -+ -+ /* -+ * A lock to ensure that only one thing can read/write -+ * the MDIO bus at a time -+ */ -+ struct mutex mdio_lock; -+ -+ struct device *parent; -+ enum { -+ MDIOBUS_ALLOCATED = 1, -+ MDIOBUS_REGISTERED, -+ MDIOBUS_UNREGISTERED, -+ MDIOBUS_RELEASED, -+ } state; -+ struct device dev; -+ -+ /* list of all PHYs on bus */ -+ struct phy_device *phy_map[PHY_MAX_ADDR]; -+ -+ /* Phy addresses to be ignored when probing */ -+ u32 phy_mask; -+ -+ /* -+ * Pointer to an array of interrupts, each PHY's -+ * interrupt at the index matching its address -+ */ -+ int *irq; -+}; -+#define to_mii_bus(d) container_of(d, struct mii_bus, dev) -+ -+struct mii_bus *mdiobus_alloc(void); -+int mdiobus_register(struct mii_bus *bus); -+void mdiobus_unregister(struct mii_bus *bus); -+void mdiobus_free(struct mii_bus *bus); -+struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr); -+int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum); -+int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val); -+ -+ -+#define PHY_INTERRUPT_DISABLED 0x0 -+#define PHY_INTERRUPT_ENABLED 0x80000000 -+ -+/* PHY state machine states: -+ * -+ * DOWN: PHY device and driver are not ready for anything. probe -+ * should be called if and only if the PHY is in this state, -+ * given that the PHY device exists. -+ * - PHY driver probe function will, depending on the PHY, set -+ * the state to STARTING or READY -+ * -+ * STARTING: PHY device is coming up, and the ethernet driver is -+ * not ready. PHY drivers may set this in the probe function. -+ * If they do, they are responsible for making sure the state is -+ * eventually set to indicate whether the PHY is UP or READY, -+ * depending on the state when the PHY is done starting up. -+ * - PHY driver will set the state to READY -+ * - start will set the state to PENDING -+ * -+ * READY: PHY is ready to send and receive packets, but the -+ * controller is not. By default, PHYs which do not implement -+ * probe will be set to this state by phy_probe(). If the PHY -+ * driver knows the PHY is ready, and the PHY state is STARTING, -+ * then it sets this STATE. -+ * - start will set the state to UP -+ * -+ * PENDING: PHY device is coming up, but the ethernet driver is -+ * ready. phy_start will set this state if the PHY state is -+ * STARTING. -+ * - PHY driver will set the state to UP when the PHY is ready -+ * -+ * UP: The PHY and attached device are ready to do work. -+ * Interrupts should be started here. -+ * - timer moves to AN -+ * -+ * AN: The PHY is currently negotiating the link state. Link is -+ * therefore down for now. phy_timer will set this state when it -+ * detects the state is UP. config_aneg will set this state -+ * whenever called with phydev->autoneg set to AUTONEG_ENABLE. -+ * - If autonegotiation finishes, but there's no link, it sets -+ * the state to NOLINK. -+ * - If aneg finishes with link, it sets the state to RUNNING, -+ * and calls adjust_link -+ * - If autonegotiation did not finish after an arbitrary amount -+ * of time, autonegotiation should be tried again if the PHY -+ * supports "magic" autonegotiation (back to AN) -+ * - If it didn't finish, and no magic_aneg, move to FORCING. -+ * -+ * NOLINK: PHY is up, but not currently plugged in. -+ * - If the timer notes that the link comes back, we move to RUNNING -+ * - config_aneg moves to AN -+ * - phy_stop moves to HALTED -+ * -+ * FORCING: PHY is being configured with forced settings -+ * - if link is up, move to RUNNING -+ * - If link is down, we drop to the next highest setting, and -+ * retry (FORCING) after a timeout -+ * - phy_stop moves to HALTED -+ * -+ * RUNNING: PHY is currently up, running, and possibly sending -+ * and/or receiving packets -+ * - timer will set CHANGELINK if we're polling (this ensures the -+ * link state is polled every other cycle of this state machine, -+ * which makes it every other second) -+ * - irq will set CHANGELINK -+ * - config_aneg will set AN -+ * - phy_stop moves to HALTED -+ * -+ * CHANGELINK: PHY experienced a change in link state -+ * - timer moves to RUNNING if link -+ * - timer moves to NOLINK if the link is down -+ * - phy_stop moves to HALTED -+ * -+ * HALTED: PHY is up, but no polling or interrupts are done. Or -+ * PHY is in an error state. -+ * -+ * - phy_start moves to RESUMING -+ * -+ * RESUMING: PHY was halted, but now wants to run again. -+ * - If we are forcing, or aneg is done, timer moves to RUNNING -+ * - If aneg is not done, timer moves to AN -+ * - phy_stop moves to HALTED -+ */ -+enum phy_state { -+ PHY_DOWN=0, -+ PHY_STARTING, -+ PHY_READY, -+ PHY_PENDING, -+ PHY_UP, -+ PHY_AN, -+ PHY_RUNNING, -+ PHY_NOLINK, -+ PHY_FORCING, -+ PHY_CHANGELINK, -+ PHY_HALTED, -+ PHY_RESUMING -+}; -+ -+/* phy_device: An instance of a PHY -+ * -+ * drv: Pointer to the driver for this PHY instance -+ * bus: Pointer to the bus this PHY is on -+ * dev: driver model device structure for this PHY -+ * phy_id: UID for this device found during discovery -+ * state: state of the PHY for management purposes -+ * dev_flags: Device-specific flags used by the PHY driver. -+ * addr: Bus address of PHY -+ * link_timeout: The number of timer firings to wait before the -+ * giving up on the current attempt at acquiring a link -+ * irq: IRQ number of the PHY's interrupt (-1 if none) -+ * phy_timer: The timer for handling the state machine -+ * phy_queue: A work_queue for the interrupt -+ * attached_dev: The attached enet driver's device instance ptr -+ * adjust_link: Callback for the enet controller to respond to -+ * changes in the link state. -+ * adjust_state: Callback for the enet driver to respond to -+ * changes in the state machine. -+ * -+ * speed, duplex, pause, supported, advertising, and -+ * autoneg are used like in mii_if_info -+ * -+ * interrupts currently only supports enabled or disabled, -+ * but could be changed in the future to support enabling -+ * and disabling specific interrupts -+ * -+ * Contains some infrastructure for polling and interrupt -+ * handling, as well as handling shifts in PHY hardware state -+ */ -+struct phy_device { -+ /* Information about the PHY type */ -+ /* And management functions */ -+ struct phy_driver *drv; -+ -+ struct mii_bus *bus; -+ -+ struct device dev; -+ -+ u32 phy_id; -+ -+ enum phy_state state; -+ -+ u32 dev_flags; -+ -+ phy_interface_t interface; -+ -+ /* Bus address of the PHY (0-32) */ -+ int addr; -+ -+ /* -+ * forced speed & duplex (no autoneg) -+ * partner speed & duplex & pause (autoneg) -+ */ -+ int speed; -+ int duplex; -+ int pause; -+ int asym_pause; -+ -+ /* The most recently read link state */ -+ int link; -+ -+ /* Enabled Interrupts */ -+ u32 interrupts; -+ -+ /* Union of PHY and Attached devices' supported modes */ -+ /* See mii.h for more info */ -+ u32 supported; -+ u32 advertising; -+ -+ int autoneg; -+ -+ int link_timeout; -+ -+ /* -+ * Interrupt number for this PHY -+ * -1 means no interrupt -+ */ -+ int irq; -+ -+ /* private data pointer */ -+ /* For use by PHYs to maintain extra state */ -+ void *priv; -+ -+ /* Interrupt and Polling infrastructure */ -+ struct work_struct phy_queue; -+ struct delayed_work state_queue; -+ atomic_t irq_disable; -+ -+ struct mutex lock; -+ -+ struct net_device *attached_dev; -+ -+ void (*adjust_link)(struct net_device *dev); -+ -+ void (*adjust_state)(struct net_device *dev); -+}; -+#define to_phy_device(d) container_of(d, struct phy_device, dev) -+ -+/* struct phy_driver: Driver structure for a particular PHY type -+ * -+ * phy_id: The result of reading the UID registers of this PHY -+ * type, and ANDing them with the phy_id_mask. This driver -+ * only works for PHYs with IDs which match this field -+ * name: The friendly name of this PHY type -+ * phy_id_mask: Defines the important bits of the phy_id -+ * features: A list of features (speed, duplex, etc) supported -+ * by this PHY -+ * flags: A bitfield defining certain other features this PHY -+ * supports (like interrupts) -+ * -+ * The drivers must implement config_aneg and read_status. All -+ * other functions are optional. Note that none of these -+ * functions should be called from interrupt time. The goal is -+ * for the bus read/write functions to be able to block when the -+ * bus transaction is happening, and be freed up by an interrupt -+ * (The MPC85xx has this ability, though it is not currently -+ * supported in the driver). -+ */ -+struct phy_driver { -+ u32 phy_id; -+ char *name; -+ unsigned int phy_id_mask; -+ u32 features; -+ u32 flags; -+ -+ /* -+ * Called to initialize the PHY, -+ * including after a reset -+ */ -+ int (*config_init)(struct phy_device *phydev); -+ -+ /* -+ * Called during discovery. Used to set -+ * up device-specific structures, if any -+ */ -+ int (*probe)(struct phy_device *phydev); -+ -+ /* PHY Power Management */ -+ int (*suspend)(struct phy_device *phydev); -+ int (*resume)(struct phy_device *phydev); -+ -+ /* -+ * Configures the advertisement and resets -+ * autonegotiation if phydev->autoneg is on, -+ * forces the speed to the current settings in phydev -+ * if phydev->autoneg is off -+ */ -+ int (*config_aneg)(struct phy_device *phydev); -+ -+ /* Determines the negotiated speed and duplex */ -+ int (*read_status)(struct phy_device *phydev); -+ -+ /* Clears any pending interrupts */ -+ int (*ack_interrupt)(struct phy_device *phydev); -+ -+ /* Enables or disables interrupts */ -+ int (*config_intr)(struct phy_device *phydev); -+ -+ /* -+ * Checks if the PHY generated an interrupt. -+ * For multi-PHY devices with shared PHY interrupt pin -+ */ -+ int (*did_interrupt)(struct phy_device *phydev); -+ -+ /* Clears up any memory if needed */ -+ void (*remove)(struct phy_device *phydev); -+ -+ struct device_driver driver; -+}; -+#define to_phy_driver(d) container_of(d, struct phy_driver, driver) -+ -+#define PHY_ANY_ID "MATCH ANY PHY" -+#define PHY_ANY_UID 0xffffffff -+ -+/* A Structure for boards to register fixups with the PHY Lib */ -+struct phy_fixup { -+ struct list_head list; -+ char bus_id[20]; -+ u32 phy_uid; -+ u32 phy_uid_mask; -+ int (*run)(struct phy_device *phydev); -+}; -+ -+/** -+ * phy_read - Convenience function for reading a given PHY register -+ * @phydev: the phy_device struct -+ * @regnum: register number to read -+ * -+ * NOTE: MUST NOT be called from interrupt context, -+ * because the bus read/write functions may wait for an interrupt -+ * to conclude the operation. -+ */ -+static inline int phy_read(struct phy_device *phydev, u32 regnum) -+{ -+ return mdiobus_read(phydev->bus, phydev->addr, regnum); -+} -+ -+/** -+ * phy_write - Convenience function for writing a given PHY register -+ * @phydev: the phy_device struct -+ * @regnum: register number to write -+ * @val: value to write to @regnum -+ * -+ * NOTE: MUST NOT be called from interrupt context, -+ * because the bus read/write functions may wait for an interrupt -+ * to conclude the operation. -+ */ -+static inline int phy_write(struct phy_device *phydev, u32 regnum, u16 val) -+{ -+ return mdiobus_write(phydev->bus, phydev->addr, regnum, val); -+} -+ -+int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id); -+struct phy_device* get_phy_device(struct mii_bus *bus, int addr); -+int phy_device_register(struct phy_device *phy); -+int phy_clear_interrupt(struct phy_device *phydev); -+int phy_config_interrupt(struct phy_device *phydev, u32 interrupts); -+int phy_init_hw(struct phy_device *phydev); -+int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, -+ u32 flags, phy_interface_t interface); -+struct phy_device * phy_attach(struct net_device *dev, -+ const char *bus_id, u32 flags, phy_interface_t interface); -+struct phy_device *phy_find_first(struct mii_bus *bus); -+int phy_connect_direct(struct net_device *dev, struct phy_device *phydev, -+ void (*handler)(struct net_device *), u32 flags, -+ phy_interface_t interface); -+struct phy_device * phy_connect(struct net_device *dev, const char *bus_id, -+ void (*handler)(struct net_device *), u32 flags, -+ phy_interface_t interface); -+void phy_disconnect(struct phy_device *phydev); -+void phy_detach(struct phy_device *phydev); -+void phy_start(struct phy_device *phydev); -+void phy_stop(struct phy_device *phydev); -+int phy_start_aneg(struct phy_device *phydev); -+ -+void phy_sanitize_settings(struct phy_device *phydev); -+int phy_stop_interrupts(struct phy_device *phydev); -+int phy_enable_interrupts(struct phy_device *phydev); -+int phy_disable_interrupts(struct phy_device *phydev); -+ -+static inline int phy_read_status(struct phy_device *phydev) { -+ return phydev->drv->read_status(phydev); -+} -+ -+int genphy_config_advert(struct phy_device *phydev); -+int genphy_setup_forced(struct phy_device *phydev); -+int genphy_restart_aneg(struct phy_device *phydev); -+int genphy_config_aneg(struct phy_device *phydev); -+int genphy_update_link(struct phy_device *phydev); -+int genphy_read_status(struct phy_device *phydev); -+int genphy_suspend(struct phy_device *phydev); -+int genphy_resume(struct phy_device *phydev); -+void phy_driver_unregister(struct phy_driver *drv); -+int phy_driver_register(struct phy_driver *new_driver); -+void phy_prepare_link(struct phy_device *phydev, -+ void (*adjust_link)(struct net_device *)); -+void phy_state_machine(struct work_struct *work); -+void phy_start_machine(struct phy_device *phydev, -+ void (*handler)(struct net_device *)); -+void phy_stop_machine(struct phy_device *phydev); -+int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd); -+int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd); -+int phy_mii_ioctl(struct phy_device *phydev, -+ struct mii_ioctl_data *mii_data, int cmd); -+int phy_start_interrupts(struct phy_device *phydev); -+void phy_print_status(struct phy_device *phydev); -+struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id); -+void phy_device_free(struct phy_device *phydev); -+ -+int phy_register_fixup(const char *bus_id, u32 phy_uid, u32 phy_uid_mask, -+ int (*run)(struct phy_device *)); -+int phy_register_fixup_for_id(const char *bus_id, -+ int (*run)(struct phy_device *)); -+int phy_register_fixup_for_uid(u32 phy_uid, u32 phy_uid_mask, -+ int (*run)(struct phy_device *)); -+int phy_scan_fixups(struct phy_device *phydev); -+ -+int __init mdio_bus_init(void); -+void mdio_bus_exit(void); -+ -+extern struct bus_type mdio_bus_type; -+#endif /* __PHY_H */ -diff -Nur linux-2.6.35.7.orig/include/linux/spi/vsc7385.h linux-2.6.35.7/include/linux/spi/vsc7385.h ---- linux-2.6.35.7.orig/include/linux/spi/vsc7385.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/include/linux/spi/vsc7385.h 2010-10-14 20:28:01.878101023 +0200 +diff -Nur linux-2.6.36.orig/include/linux/spi/vsc7385.h linux-2.6.36/include/linux/spi/vsc7385.h +--- linux-2.6.36.orig/include/linux/spi/vsc7385.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/include/linux/spi/vsc7385.h 2010-11-18 21:16:19.000000000 +0100 @@ -0,0 +1,19 @@ +/* + * Platform data definition for the Vitesse VSC7385 ethernet switch driver @@ -33048,9 +17495,9 @@ diff -Nur linux-2.6.35.7.orig/include/linux/spi/vsc7385.h linux-2.6.35.7/include + u32 clk_sel:3; + } mac_cfg; +}; -diff -Nur linux-2.6.35.7.orig/net/dsa/ar7240.c linux-2.6.35.7/net/dsa/ar7240.c ---- linux-2.6.35.7.orig/net/dsa/ar7240.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/net/dsa/ar7240.c 2010-10-14 20:28:01.915601104 +0200 +diff -Nur linux-2.6.36.orig/net/dsa/ar7240.c linux-2.6.36/net/dsa/ar7240.c +--- linux-2.6.36.orig/net/dsa/ar7240.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/net/dsa/ar7240.c 2010-11-18 21:16:19.000000000 +0100 @@ -0,0 +1,736 @@ +/* + * DSA driver for the built-in ethernet switch of the Atheros AR7240 SoC @@ -33788,9 +18235,9 @@ diff -Nur linux-2.6.35.7.orig/net/dsa/ar7240.c linux-2.6.35.7/net/dsa/ar7240.c + unregister_switch_driver(&ar7240_dsa_driver); +} +module_exit(dsa_ar7240_cleanup); -diff -Nur linux-2.6.35.7.orig/net/dsa/mv88e6063.c linux-2.6.35.7/net/dsa/mv88e6063.c ---- linux-2.6.35.7.orig/net/dsa/mv88e6063.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/net/dsa/mv88e6063.c 2010-10-14 20:28:01.954381749 +0200 +diff -Nur linux-2.6.36.orig/net/dsa/mv88e6063.c linux-2.6.36/net/dsa/mv88e6063.c +--- linux-2.6.36.orig/net/dsa/mv88e6063.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/net/dsa/mv88e6063.c 2010-11-18 21:16:19.000000000 +0100 @@ -0,0 +1,294 @@ +/* + * net/dsa/mv88e6063.c - Driver for Marvell 88e6063 switch chips @@ -34086,9 +18533,9 @@ diff -Nur linux-2.6.35.7.orig/net/dsa/mv88e6063.c linux-2.6.35.7/net/dsa/mv88e60 + unregister_switch_driver(&mv88e6063_switch_driver); +} +module_exit(mv88e6063_cleanup); -diff -Nur linux-2.6.35.7.orig/net/dsa/tag_qinq.c linux-2.6.35.7/net/dsa/tag_qinq.c ---- linux-2.6.35.7.orig/net/dsa/tag_qinq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux-2.6.35.7/net/dsa/tag_qinq.c 2010-10-14 20:28:01.998101297 +0200 +diff -Nur linux-2.6.36.orig/net/dsa/tag_qinq.c linux-2.6.36/net/dsa/tag_qinq.c +--- linux-2.6.36.orig/net/dsa/tag_qinq.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux-2.6.36/net/dsa/tag_qinq.c 2010-11-18 21:16:19.000000000 +0100 @@ -0,0 +1,127 @@ +/* + * net/dsa/tag_qinq.c - QinQ tag format handling -- cgit v1.2.3