From 5ae969ac63f67e0c8c6ab4363a3c3012fcd2efe5 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Tue, 23 Sep 2014 13:42:26 +0200 Subject: add m68k patch --- package/qemu/patches/qemu-2.1.0-m68k.patch | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 package/qemu/patches/qemu-2.1.0-m68k.patch (limited to 'package/qemu') diff --git a/package/qemu/patches/qemu-2.1.0-m68k.patch b/package/qemu/patches/qemu-2.1.0-m68k.patch new file mode 100644 index 000000000..65b917b0a --- /dev/null +++ b/package/qemu/patches/qemu-2.1.0-m68k.patch @@ -0,0 +1,35 @@ +--- qemu-2.1.0/hw/m68k/mcf_intc.c 2014-08-01 16:12:17.000000000 +0200 ++++ qemu-2.1.0.m68k/hw/m68k/mcf_intc.c 2014-08-12 11:41:52.416975339 +0200 +@@ -65,6 +65,10 @@ + return (uint32_t)(s->ifr >> 32); + case 0x14: + return (uint32_t)s->ifr; ++ /* Reading from SIMR and CIMR return 0 */ ++ case 0x1c: ++ case 0x1d: ++ return 0; + case 0xe0: /* SWIACK. */ + return s->active_vector; + case 0xe1: case 0xe2: case 0xe3: case 0xe4: +@@ -102,6 +106,20 @@ + case 0x0c: + s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; + break; ++ /* SIMR allows to easily mask interrupts */ ++ case 0x1c: ++ if (val & 0x40) ++ s->imr = ~0ull; ++ else ++ s->imr |= (1 << (val & 0x3f)); ++ break; ++ /* CIMR allows to easily unmask interrupts */ ++ case 0x1d: ++ if (val & 0x40) ++ s->imr = 0ull; ++ else ++ s->imr &= ~(1 << (val & 0x3f)); ++ break; + default: + hw_error("mcf_intc_write: Bad write offset %d\n", offset); + break; + -- cgit v1.2.3