From 1557f0ea6e1ae6c363544b853c805d4ee5900ec3 Mon Sep 17 00:00:00 2001 From: Waldemar Brodkorb Date: Fri, 11 Jun 2021 15:28:11 +0200 Subject: gcc: update 8/9 --- target/config/Config.in.compiler | 4 +- toolchain/gcc/Makefile.inc | 8 +- toolchain/gcc/patches/7.4.0/add-crtreloc.frv | 12 - .../gcc/patches/7.4.0/c6x-disable-multilib.patch | 10 - .../7.4.0/disable-split-stack-nothread.patch | 10 - toolchain/gcc/patches/7.4.0/ia64-fix-libgcc.patch | 17 - toolchain/gcc/patches/7.4.0/j2.patch | 343 --------------------- .../gcc/patches/7.4.0/m68k-coldfire-pr68467.patch | 43 --- toolchain/gcc/patches/7.4.0/m68k-musl.patch | 25 -- toolchain/gcc/patches/7.4.0/microblaze.patch | 23 -- toolchain/gcc/patches/7.4.0/musl-s390x.patch | 13 - toolchain/gcc/patches/7.4.0/nios2-softfp.patch | 14 - toolchain/gcc/patches/7.5.0/add-crtreloc.frv | 12 + .../gcc/patches/7.5.0/c6x-disable-multilib.patch | 10 + .../7.5.0/disable-split-stack-nothread.patch | 10 + toolchain/gcc/patches/7.5.0/ia64-fix-libgcc.patch | 17 + toolchain/gcc/patches/7.5.0/j2.patch | 343 +++++++++++++++++++++ .../gcc/patches/7.5.0/m68k-coldfire-pr68467.patch | 43 +++ toolchain/gcc/patches/7.5.0/m68k-musl.patch | 25 ++ toolchain/gcc/patches/7.5.0/microblaze.patch | 23 ++ toolchain/gcc/patches/7.5.0/musl-s390x.patch | 13 + toolchain/gcc/patches/7.5.0/nios2-softfp.patch | 14 + .../8.4.0/0002-xtensa-fix-PR-target-91880.patch | 49 --- toolchain/gcc/patches/8.4.0/add-crtreloc.frv | 12 - .../gcc/patches/8.4.0/c6x-disable-multilib.patch | 10 - toolchain/gcc/patches/8.4.0/ia64-fix-libgcc.patch | 17 - toolchain/gcc/patches/8.4.0/j2.patch | 343 --------------------- toolchain/gcc/patches/8.4.0/m68k-musl.patch | 25 -- toolchain/gcc/patches/8.4.0/musl-s390x.patch | 13 - toolchain/gcc/patches/8.4.0/nios2-softfp.patch | 14 - toolchain/gcc/patches/8.5.0/add-crtreloc.frv | 12 + .../gcc/patches/8.5.0/c6x-disable-multilib.patch | 10 + toolchain/gcc/patches/8.5.0/ia64-fix-libgcc.patch | 17 + toolchain/gcc/patches/8.5.0/j2.patch | 343 +++++++++++++++++++++ toolchain/gcc/patches/8.5.0/m68k-musl.patch | 25 ++ toolchain/gcc/patches/8.5.0/musl-s390x.patch | 13 + toolchain/gcc/patches/8.5.0/nios2-softfp.patch | 14 + toolchain/gcc/patches/9.3.0/or1k.patch | 61 ---- toolchain/gcc/patches/9.4.0/or1k.patch | 61 ++++ 39 files changed, 1011 insertions(+), 1060 deletions(-) delete mode 100644 toolchain/gcc/patches/7.4.0/add-crtreloc.frv delete mode 100644 toolchain/gcc/patches/7.4.0/c6x-disable-multilib.patch delete mode 100644 toolchain/gcc/patches/7.4.0/disable-split-stack-nothread.patch delete mode 100644 toolchain/gcc/patches/7.4.0/ia64-fix-libgcc.patch delete mode 100644 toolchain/gcc/patches/7.4.0/j2.patch delete mode 100644 toolchain/gcc/patches/7.4.0/m68k-coldfire-pr68467.patch delete mode 100644 toolchain/gcc/patches/7.4.0/m68k-musl.patch delete mode 100644 toolchain/gcc/patches/7.4.0/microblaze.patch delete mode 100644 toolchain/gcc/patches/7.4.0/musl-s390x.patch delete mode 100644 toolchain/gcc/patches/7.4.0/nios2-softfp.patch create mode 100644 toolchain/gcc/patches/7.5.0/add-crtreloc.frv create mode 100644 toolchain/gcc/patches/7.5.0/c6x-disable-multilib.patch create mode 100644 toolchain/gcc/patches/7.5.0/disable-split-stack-nothread.patch create mode 100644 toolchain/gcc/patches/7.5.0/ia64-fix-libgcc.patch create mode 100644 toolchain/gcc/patches/7.5.0/j2.patch create mode 100644 toolchain/gcc/patches/7.5.0/m68k-coldfire-pr68467.patch create mode 100644 toolchain/gcc/patches/7.5.0/m68k-musl.patch create mode 100644 toolchain/gcc/patches/7.5.0/microblaze.patch create mode 100644 toolchain/gcc/patches/7.5.0/musl-s390x.patch create mode 100644 toolchain/gcc/patches/7.5.0/nios2-softfp.patch delete mode 100644 toolchain/gcc/patches/8.4.0/0002-xtensa-fix-PR-target-91880.patch delete mode 100644 toolchain/gcc/patches/8.4.0/add-crtreloc.frv delete mode 100644 toolchain/gcc/patches/8.4.0/c6x-disable-multilib.patch delete mode 100644 toolchain/gcc/patches/8.4.0/ia64-fix-libgcc.patch delete mode 100644 toolchain/gcc/patches/8.4.0/j2.patch delete mode 100644 toolchain/gcc/patches/8.4.0/m68k-musl.patch delete mode 100644 toolchain/gcc/patches/8.4.0/musl-s390x.patch delete mode 100644 toolchain/gcc/patches/8.4.0/nios2-softfp.patch create mode 100644 toolchain/gcc/patches/8.5.0/add-crtreloc.frv create mode 100644 toolchain/gcc/patches/8.5.0/c6x-disable-multilib.patch create mode 100644 toolchain/gcc/patches/8.5.0/ia64-fix-libgcc.patch create mode 100644 toolchain/gcc/patches/8.5.0/j2.patch create mode 100644 toolchain/gcc/patches/8.5.0/m68k-musl.patch create mode 100644 toolchain/gcc/patches/8.5.0/musl-s390x.patch create mode 100644 toolchain/gcc/patches/8.5.0/nios2-softfp.patch delete mode 100644 toolchain/gcc/patches/9.3.0/or1k.patch create mode 100644 toolchain/gcc/patches/9.4.0/or1k.patch diff --git a/target/config/Config.in.compiler b/target/config/Config.in.compiler index 451151cb5..a28dd4b5a 100644 --- a/target/config/Config.in.compiler +++ b/target/config/Config.in.compiler @@ -36,7 +36,7 @@ config ADK_TOOLCHAIN_GCC_10 depends on !ADK_TARGET_ARCH_NDS32 config ADK_TOOLCHAIN_GCC_9 - bool "9.3.0" + bool "9.4.0" depends on !ADK_TARGET_ARCH_ARC depends on !ADK_TARGET_ARCH_AVR32 depends on !ADK_TARGET_ARCH_METAG @@ -45,7 +45,7 @@ config ADK_TOOLCHAIN_GCC_9 depends on !ADK_TARGET_CPU_ARM_CORTEX_A53 config ADK_TOOLCHAIN_GCC_8 - bool "8.4.0" + bool "8.5.0" depends on !ADK_TARGET_ARCH_ARC depends on !ADK_TARGET_ARCH_AVR32 depends on !ADK_TARGET_ARCH_CSKY diff --git a/toolchain/gcc/Makefile.inc b/toolchain/gcc/Makefile.inc index 90728356e..52b1ae4b2 100644 --- a/toolchain/gcc/Makefile.inc +++ b/toolchain/gcc/Makefile.inc @@ -11,16 +11,16 @@ DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz LIBSTDCXXVER:= 26 endif ifeq ($(ADK_TOOLCHAIN_GCC_9),y) -PKG_VERSION:= 9.3.0 -PKG_HASH:= 71e197867611f6054aa1119b13a0c0abac12834765fe2d81f35ac57f84f742d1 +PKG_VERSION:= 9.4.0 +PKG_HASH:= c95da32f440378d7751dd95533186f7fc05ceb4fb65eb5b85234e6299eb9838e PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} PKG_RELEASE:= 1 DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz LIBSTDCXXVER:= 25 endif ifeq ($(ADK_TOOLCHAIN_GCC_8),y) -PKG_VERSION:= 8.4.0 -PKG_HASH:= e30a6e52d10e1f27ed55104ad233c30bd1e99cfb5ff98ab022dc941edd1b2dd4 +PKG_VERSION:= 8.5.0 +PKG_HASH:= d308841a511bb830a6100397b0042db24ce11f642dab6ea6ee44842e5325ed50 PKG_SITES:= ${MASTER_SITE_GNU:=gcc/gcc-${PKG_VERSION}/} PKG_RELEASE:= 1 DISTFILES:= ${PKG_NAME}-${PKG_VERSION}.tar.xz diff --git a/toolchain/gcc/patches/7.4.0/add-crtreloc.frv b/toolchain/gcc/patches/7.4.0/add-crtreloc.frv deleted file mode 100644 index dce4a0ea0..000000000 --- a/toolchain/gcc/patches/7.4.0/add-crtreloc.frv +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur gcc-7.1.0.orig/gcc/config/frv/linux.h gcc-7.1.0/gcc/config/frv/linux.h ---- gcc-7.1.0.orig/gcc/config/frv/linux.h 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.1.0/gcc/config/frv/linux.h 2017-06-07 14:52:44.289044131 +0200 -@@ -27,7 +27,7 @@ - - #undef STARTFILE_SPEC - #define STARTFILE_SPEC \ -- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ -+ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} crtreloc.o%s \ - crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}" - - #undef ENDFILE_SPEC diff --git a/toolchain/gcc/patches/7.4.0/c6x-disable-multilib.patch b/toolchain/gcc/patches/7.4.0/c6x-disable-multilib.patch deleted file mode 100644 index 8637b2cd2..000000000 --- a/toolchain/gcc/patches/7.4.0/c6x-disable-multilib.patch +++ /dev/null @@ -1,10 +0,0 @@ -diff -Nur gcc-7.3.0.orig/gcc/config/c6x/t-c6x-uclinux gcc-7.3.0/gcc/config/c6x/t-c6x-uclinux ---- gcc-7.3.0.orig/gcc/config/c6x/t-c6x-uclinux 2011-11-02 16:23:48.424740000 +0100 -+++ gcc-7.3.0/gcc/config/c6x/t-c6x-uclinux 2018-06-01 08:14:36.679894633 +0200 -@@ -1,3 +1,3 @@ --MULTILIB_OSDIRNAMES = march.c674x=!c674x --MULTILIB_OSDIRNAMES += mbig-endian=!be --MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x -+MULTILIB_OSDIRNAMES = -+#MULTILIB_OSDIRNAMES += mbig-endian=!be -+#MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x diff --git a/toolchain/gcc/patches/7.4.0/disable-split-stack-nothread.patch b/toolchain/gcc/patches/7.4.0/disable-split-stack-nothread.patch deleted file mode 100644 index 0038d7573..000000000 --- a/toolchain/gcc/patches/7.4.0/disable-split-stack-nothread.patch +++ /dev/null @@ -1,10 +0,0 @@ -diff -Nur gcc-7.1.0.orig/libgcc/config/t-stack gcc-7.1.0/libgcc/config/t-stack ---- gcc-7.1.0.orig/libgcc/config/t-stack 2010-10-01 21:31:49.000000000 +0200 -+++ gcc-7.1.0/libgcc/config/t-stack 2017-06-23 19:55:25.215965555 +0200 -@@ -1,4 +1,6 @@ - # Makefile fragment to provide generic support for -fsplit-stack. - # This should be used in config.host for any host which supports - # -fsplit-stack. -+ifeq ($(enable_threads),yes) - LIB2ADD_ST += $(srcdir)/generic-morestack.c $(srcdir)/generic-morestack-thread.c -+endif diff --git a/toolchain/gcc/patches/7.4.0/ia64-fix-libgcc.patch b/toolchain/gcc/patches/7.4.0/ia64-fix-libgcc.patch deleted file mode 100644 index f1f3c8d2d..000000000 --- a/toolchain/gcc/patches/7.4.0/ia64-fix-libgcc.patch +++ /dev/null @@ -1,17 +0,0 @@ -diff -Nur gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c gcc-6.3.0/libgcc/config/ia64/fde-glibc.c ---- gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c 2016-01-04 15:30:50.000000000 +0100 -+++ gcc-6.3.0/libgcc/config/ia64/fde-glibc.c 2017-03-05 13:07:33.316600613 +0100 -@@ -25,6 +25,8 @@ - /* Locate the FDE entry for a given address, using glibc ld.so routines - to avoid register/deregister calls at DSO load/unload. */ - -+#ifndef inhibit_libc -+ - #ifndef _GNU_SOURCE - #define _GNU_SOURCE 1 - #endif -@@ -159,3 +161,4 @@ - - return data.ret; - } -+#endif diff --git a/toolchain/gcc/patches/7.4.0/j2.patch b/toolchain/gcc/patches/7.4.0/j2.patch deleted file mode 100644 index aafbe0ea9..000000000 --- a/toolchain/gcc/patches/7.4.0/j2.patch +++ /dev/null @@ -1,343 +0,0 @@ -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh-protos.h gcc-7.3.0/gcc/config/sh/sh-protos.h ---- gcc-7.3.0.orig/gcc/config/sh/sh-protos.h 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/sh-protos.h 2018-06-03 02:20:50.000000000 +0200 -@@ -35,6 +35,9 @@ - SFUNC_STATIC - }; - -+#define TARGET_ATOMIC_HARD_CAS \ -+ (selected_atomic_model ().type == sh_atomic_model::hard_cas) -+ - #ifdef RTX_CODE - extern rtx sh_fsca_sf2int (void); - extern rtx sh_fsca_int2sf (void); -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.c gcc-7.3.0/gcc/config/sh/sh.c ---- gcc-7.3.0.orig/gcc/config/sh/sh.c 2017-04-04 00:30:56.000000000 +0200 -+++ gcc-7.3.0/gcc/config/sh/sh.c 2018-06-03 02:20:50.000000000 +0200 -@@ -662,6 +662,7 @@ - model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; - model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; - model_names[sh_atomic_model::soft_imask] = "soft-imask"; -+ model_names[sh_atomic_model::hard_cas] = "hard-cas"; - - const char* model_cdef_names[sh_atomic_model::num_models]; - model_cdef_names[sh_atomic_model::none] = "NONE"; -@@ -669,6 +670,7 @@ - model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; - model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; - model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; -+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; - - sh_atomic_model ret; - ret.type = sh_atomic_model::none; -@@ -747,6 +749,9 @@ - if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) - err_ret ("cannot use atomic model %s in user mode", ret.name); - -+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) -+ err_ret ("atomic model %s is only available J2 targets", ret.name); -+ - return ret; - - #undef err_ret -@@ -803,6 +808,8 @@ - sh_cpu = PROCESSOR_SH2E; - if (TARGET_SH2A) - sh_cpu = PROCESSOR_SH2A; -+ if (TARGET_SHJ2) -+ sh_cpu = PROCESSOR_SHJ2; - if (TARGET_SH3) - sh_cpu = PROCESSOR_SH3; - if (TARGET_SH3E) -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.h gcc-7.3.0/gcc/config/sh/sh.h ---- gcc-7.3.0.orig/gcc/config/sh/sh.h 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/sh.h 2018-06-03 02:20:50.000000000 +0200 -@@ -83,6 +83,7 @@ - #define SUPPORT_SH4_SINGLE 1 - #define SUPPORT_SH2A 1 - #define SUPPORT_SH2A_SINGLE 1 -+#define SUPPORT_SHJ2 1 - #endif - - #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) -@@ -115,6 +116,7 @@ - #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) - #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) - #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) -+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) - - #if SUPPORT_SH1 - #define SUPPORT_SH2 1 -@@ -122,6 +124,7 @@ - #if SUPPORT_SH2 - #define SUPPORT_SH3 1 - #define SUPPORT_SH2A_NOFPU 1 -+#define SUPPORT_SHJ2 1 - #endif - #if SUPPORT_SH3 - #define SUPPORT_SH4_NOFPU 1 -@@ -154,7 +157,7 @@ - #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ - | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ - | MASK_HARD_SH4 | MASK_FPU_SINGLE \ -- | MASK_FPU_SINGLE_ONLY) -+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) - - /* This defaults us to big-endian. */ - #ifndef TARGET_ENDIAN_DEFAULT -@@ -229,7 +232,8 @@ - %{m2a-single:--isa=sh2a} \ - %{m2a-single-only:--isa=sh2a} \ - %{m2a-nofpu:--isa=sh2a-nofpu} \ --%{m4al:-dsp}" -+%{m4al:-dsp} \ -+%{mj2:-isa=j2}" - - #define ASM_SPEC SH_ASM_SPEC - -@@ -345,6 +349,7 @@ - hard_llcs, - soft_tcb, - soft_imask, -+ hard_cas, - - num_models - }; -@@ -1568,7 +1573,7 @@ - - /* Nonzero if the target supports dynamic shift instructions - like shad and shld. */ --#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) -+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) - - /* The cost of using the dynamic shift insns (shad, shld) are the same - if they are available. If they are not available a library function will -@@ -1833,6 +1838,7 @@ - PROCESSOR_SH2, - PROCESSOR_SH2E, - PROCESSOR_SH2A, -+ PROCESSOR_SHJ2, - PROCESSOR_SH3, - PROCESSOR_SH3E, - PROCESSOR_SH4, -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.opt gcc-7.3.0/gcc/config/sh/sh.opt ---- gcc-7.3.0.orig/gcc/config/sh/sh.opt 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/sh.opt 2018-06-03 02:20:50.000000000 +0200 -@@ -65,6 +65,10 @@ - Target RejectNegative Condition(SUPPORT_SH2E) - Generate SH2e code. - -+mj2 -+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) -+Generate J2 code. -+ - m3 - Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) - Generate SH3 code. -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sync.md gcc-7.3.0/gcc/config/sh/sync.md ---- gcc-7.3.0.orig/gcc/config/sh/sync.md 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/sync.md 2018-06-03 02:20:50.000000000 +0200 -@@ -240,6 +240,9 @@ - || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) - atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, - exp_val, new_val); -+ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) -+ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, -+ exp_val, new_val); - else if (TARGET_ATOMIC_SOFT_GUSA) - atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, - exp_val, new_val); -@@ -306,6 +309,57 @@ - } - [(set_attr "length" "14")]) - -+(define_expand "atomic_compare_and_swapsi_cas" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") -+ (match_operand:SI 2 "register_operand" "r") -+ (match_operand:SI 3 "register_operand" "r")] -+ UNSPECV_CMPXCHG_1))] -+ "TARGET_ATOMIC_HARD_CAS" -+{ -+ rtx mem = gen_rtx_REG (SImode, 0); -+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); -+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); -+ DONE; -+}) -+ -+(define_insn "shj2_cas" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "register_operand" "=r") -+ (match_operand:SI 2 "register_operand" "r") -+ (match_operand:SI 3 "register_operand" "0")] -+ UNSPECV_CMPXCHG_1)) -+ (set (reg:SI T_REG) -+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] -+ "TARGET_ATOMIC_HARD_CAS" -+ "cas.l %2,%0,@%1" -+ [(set_attr "length" "2")] -+) -+ -+(define_expand "atomic_compare_and_swapqi_cas" -+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") -+ (match_operand:SI 2 "arith_operand" "rI08") -+ (match_operand:SI 3 "arith_operand" "rI08")] -+ UNSPECV_CMPXCHG_1))] -+ "TARGET_ATOMIC_HARD_CAS" -+{FAIL;} -+) -+ -+(define_expand "atomic_compare_and_swaphi_cas" -+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") -+ (match_operand:SI 2 "arith_operand" "rI08") -+ (match_operand:SI 3 "arith_operand" "rI08")] -+ UNSPECV_CMPXCHG_1))] -+ "TARGET_ATOMIC_HARD_CAS" -+{FAIL;} -+) -+ - ;; The QIHImode llcs patterns modify the address register of the memory - ;; operand. In order to express that, we have to open code the memory - ;; operand. Initially the insn is expanded like every other atomic insn -diff -Nur gcc-7.3.0.orig/gcc/config/sh/t-sh gcc-7.3.0/gcc/config/sh/t-sh ---- gcc-7.3.0.orig/gcc/config/sh/t-sh 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/t-sh 2018-06-03 02:20:50.000000000 +0200 -@@ -50,7 +50,8 @@ - m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ - m2a-single,m2a-single-only \ - m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ -- m4,m4-100,m4-200,m4-300,m4a; do \ -+ m4,m4-100,m4-200,m4-300,m4a \ -+ mj2; do \ - subst= ; \ - for lib in `echo $$abi|tr , ' '` ; do \ - if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ -@@ -63,9 +64,9 @@ - - # SH1 and SH2A support big endian only. - ifeq ($(DEFAULT_ENDIAN),ml) --MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) -+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) - else --MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) -+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) - endif - - MULTILIB_OSDIRNAMES = \ -@@ -87,7 +88,8 @@ - m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ - m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ - m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ -- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al -+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ -+ mj2=!j2 - - $(out_object_file): gt-sh.h - gt-sh.h : s-gtype ; @true -diff -Nur gcc-7.3.0.orig/gcc/config.gcc gcc-7.3.0/gcc/config.gcc ---- gcc-7.3.0.orig/gcc/config.gcc 2018-01-08 14:39:11.000000000 +0100 -+++ gcc-7.3.0/gcc/config.gcc 2018-06-03 02:20:50.000000000 +0200 -@@ -474,7 +474,7 @@ - extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" - ;; - # Note the 'l'; we need to be able to match e.g. "shle" or "shl". --sh[123456789lbe]*-*-* | sh-*-*) -+sh[123456789lbej]*-*-* | sh-*-*) - cpu_type=sh - extra_options="${extra_options} fused-madd.opt" - extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" -@@ -2664,18 +2664,18 @@ - extra_options="${extra_options} s390/tpf.opt" - tmake_file="${tmake_file} s390/t-s390" - ;; --sh-*-elf* | sh[12346l]*-*-elf* | \ -- sh-*-linux* | sh[2346lbe]*-*-linux* | \ -+sh-*-elf* | sh[12346lj]*-*-elf* | \ -+ sh-*-linux* | sh[2346lbej]*-*-linux* | \ - sh-*-netbsdelf* | shl*-*-netbsdelf*) - tmake_file="${tmake_file} sh/t-sh sh/t-elf" - if test x${with_endian} = x; then - case ${target} in -- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; -+ sh[j1234]*be-*-* | sh[n1234]*eb-*-*) with_endian=big ;; - shbe-*-* | sheb-*-*) with_endian=big,little ;; - sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; - shl* | sh*-*-linux* | \ - sh-superh-elf) with_endian=little,big ;; -- sh[1234]*-*-*) with_endian=big ;; -+ sh[j1234]*-*-*) with_endian=big ;; - *) with_endian=big,little ;; - esac - fi -@@ -2742,6 +2742,7 @@ - sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; - sh2a*) sh_cpu_target=sh2a ;; - sh2e*) sh_cpu_target=sh2e ;; -+ shj2*) sh_cpu_target=shj2;; - sh2*) sh_cpu_target=sh2 ;; - *) sh_cpu_target=sh1 ;; - esac -@@ -2763,7 +2764,7 @@ - sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ - sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ - sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ -- sh3e | sh3 | sh2e | sh2 | sh1) ;; -+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; - "") sh_cpu_default=${sh_cpu_target} ;; - *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; - esac -@@ -2772,9 +2773,9 @@ - case ${target} in - sh[1234]*) sh_multilibs=${sh_cpu_target} ;; - sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; -- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; -+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; - sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; -- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; -+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; - esac - if test x$with_fp = xno; then - sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" -@@ -2789,7 +2790,8 @@ - m1 | m2 | m2e | m3 | m3e | \ - m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ - m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ -- m2a | m2a-single | m2a-single-only | m2a-nofpu) -+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ -+ mj2) - # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition - # It is passed to MULTIILIB_OPTIONS verbatim. - TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" -@@ -2806,7 +2808,7 @@ - done - TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` - if test x${enable_incomplete_targets} = xyes ; then -- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" -+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" - fi - tm_file="$tm_file ./sysroot-suffix.h" - tmake_file="$tmake_file t-sysroot-suffix" -@@ -4380,6 +4382,8 @@ - ;; - m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) - ;; -+ mj2) -+ ;; - *) - echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 - echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 -@@ -4589,7 +4593,7 @@ - tmake_file="rs6000/t-rs6000 ${tmake_file}" - ;; - -- sh[123456ble]*-*-* | sh-*-*) -+ sh[123456blej]*-*-* | sh-*-*) - c_target_objs="${c_target_objs} sh-c.o" - cxx_target_objs="${cxx_target_objs} sh-c.o" - ;; diff --git a/toolchain/gcc/patches/7.4.0/m68k-coldfire-pr68467.patch b/toolchain/gcc/patches/7.4.0/m68k-coldfire-pr68467.patch deleted file mode 100644 index 45e9eb0ba..000000000 --- a/toolchain/gcc/patches/7.4.0/m68k-coldfire-pr68467.patch +++ /dev/null @@ -1,43 +0,0 @@ -diff -Nur gcc-7.2.0.orig/gcc/config/m68k/m68k.c gcc-7.2.0/gcc/config/m68k/m68k.c ---- gcc-7.2.0.orig/gcc/config/m68k/m68k.c 2017-04-03 22:30:56.274463000 +0000 -+++ gcc-7.2.0/gcc/config/m68k/m68k.c 2018-01-27 02:16:53.779367849 +0000 -@@ -182,6 +182,8 @@ - const_tree, bool); - static bool m68k_cannot_force_const_mem (machine_mode mode, rtx x); - static bool m68k_output_addr_const_extra (FILE *, rtx); -+static machine_mode m68k_promote_function_mode (const_tree, machine_mode, -+ int *, const_tree, int); - static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED; - static enum flt_eval_method - m68k_excess_precision (enum excess_precision_type); -@@ -332,6 +334,9 @@ - #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL - #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128 - -+#undef TARGET_PROMOTE_FUNCTION_MODE -+#define TARGET_PROMOTE_FUNCTION_MODE m68k_promote_function_mode -+ - static const struct attribute_spec m68k_attribute_table[] = - { - /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, -@@ -6571,4 +6576,20 @@ - return FLT_EVAL_METHOD_UNPREDICTABLE; - } - -+/* Implement TARGET_PROMOTE_FUNCTION_MODE. */ -+ -+static machine_mode -+m68k_promote_function_mode (const_tree type, machine_mode mode, -+ int *punsignedp ATTRIBUTE_UNUSED, -+ const_tree fntype ATTRIBUTE_UNUSED, -+ int for_return) -+{ -+ /* Promote libcall arguments narrower than int to match the normal C -+ ABI (for which promotions are handled via -+ TARGET_PROMOTE_PROTOTYPES). */ -+ if (type == NULL_TREE && !for_return && (mode == QImode || mode == HImode)) -+ return SImode; -+ return mode; -+} -+ - #include "gt-m68k.h" diff --git a/toolchain/gcc/patches/7.4.0/m68k-musl.patch b/toolchain/gcc/patches/7.4.0/m68k-musl.patch deleted file mode 100644 index a7effec4c..000000000 --- a/toolchain/gcc/patches/7.4.0/m68k-musl.patch +++ /dev/null @@ -1,25 +0,0 @@ -diff -Nur gcc-7.3.0.orig/gcc/config/m68k/linux.h gcc-7.3.0/gcc/config/m68k/linux.h ---- gcc-7.3.0.orig/gcc/config/m68k/linux.h 2017-01-06 22:21:02.000000000 +0100 -+++ gcc-7.3.0/gcc/config/m68k/linux.h 2018-10-05 06:38:51.000000000 +0200 -@@ -73,6 +73,9 @@ - - #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" - -+#undef MUSL_DYNAMIC_LINKER -+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" -+ - #undef LINK_SPEC - #define LINK_SPEC "-m m68kelf %{shared} \ - %{!shared: \ -diff -Nur gcc-7.3.0.orig/libgcc/config/m68k/linux-unwind.h gcc-7.3.0/libgcc/config/m68k/linux-unwind.h ---- gcc-7.3.0.orig/libgcc/config/m68k/linux-unwind.h 2017-07-04 12:22:56.000000000 +0200 -+++ gcc-7.3.0/libgcc/config/m68k/linux-unwind.h 2018-10-05 06:38:51.000000000 +0200 -@@ -37,7 +37,7 @@ - stack_t uc_stack; - mcontext_t uc_mcontext; - unsigned long uc_filler[80]; -- __sigset_t uc_sigmask; -+ sigset_t uc_sigmask; - }; - - #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/toolchain/gcc/patches/7.4.0/microblaze.patch b/toolchain/gcc/patches/7.4.0/microblaze.patch deleted file mode 100644 index eb6c08492..000000000 --- a/toolchain/gcc/patches/7.4.0/microblaze.patch +++ /dev/null @@ -1,23 +0,0 @@ -revert 6dcad60c0ef48af584395a40feeb256fb82986a8 -as it breaks any userland in qemu - -diff -Nur gcc-6.3.0.orig/gcc/config/microblaze/microblaze.h gcc-6.3.0/gcc/config/microblaze/microblaze.h ---- gcc-6.3.0.orig/gcc/config/microblaze/microblaze.h 2016-01-21 18:10:54.000000000 +0100 -+++ gcc-6.3.0/gcc/config/microblaze/microblaze.h 2017-05-26 18:33:31.297534916 +0200 -@@ -253,14 +253,14 @@ - #define FIXED_REGISTERS \ - { \ - 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ -- 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 1, 1 \ - } - - #define CALL_USED_REGISTERS \ - { \ - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ -- 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ -+ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1, 1, 1, 1 \ - } - #define GP_REG_FIRST 0 diff --git a/toolchain/gcc/patches/7.4.0/musl-s390x.patch b/toolchain/gcc/patches/7.4.0/musl-s390x.patch deleted file mode 100644 index 1163bdbf4..000000000 --- a/toolchain/gcc/patches/7.4.0/musl-s390x.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff -Nur gcc-7.2.0.orig/gcc/config/s390/linux.h gcc-7.2.0/gcc/config/s390/linux.h ---- gcc-7.2.0.orig/gcc/config/s390/linux.h 2017-02-06 11:25:05.513198000 +0100 -+++ gcc-7.2.0/gcc/config/s390/linux.h 2017-10-30 13:22:45.348170100 +0100 -@@ -76,6 +76,9 @@ - #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" - #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" - -+#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" -+#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" -+ - #undef LINK_SPEC - #define LINK_SPEC \ - "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/toolchain/gcc/patches/7.4.0/nios2-softfp.patch b/toolchain/gcc/patches/7.4.0/nios2-softfp.patch deleted file mode 100644 index c677c6c2f..000000000 --- a/toolchain/gcc/patches/7.4.0/nios2-softfp.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -Nur gcc-6.2.0.orig/libgcc/config.host gcc-6.2.0/libgcc/config.host ---- gcc-6.2.0.orig/libgcc/config.host 2016-05-17 08:15:52.000000000 +0200 -+++ gcc-6.2.0/libgcc/config.host 2016-10-15 14:42:53.971919904 +0200 -@@ -962,6 +962,10 @@ - ;; - esac - ;; -+nios2-*-linux-uclibc*) -+ tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc t-softfp-sfdf t-softfp" -+ md_unwind_header=nios2/linux-unwind.h -+ ;; - nios2-*-linux*) - tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc" - md_unwind_header=nios2/linux-unwind.h diff --git a/toolchain/gcc/patches/7.5.0/add-crtreloc.frv b/toolchain/gcc/patches/7.5.0/add-crtreloc.frv new file mode 100644 index 000000000..dce4a0ea0 --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/add-crtreloc.frv @@ -0,0 +1,12 @@ +diff -Nur gcc-7.1.0.orig/gcc/config/frv/linux.h gcc-7.1.0/gcc/config/frv/linux.h +--- gcc-7.1.0.orig/gcc/config/frv/linux.h 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.1.0/gcc/config/frv/linux.h 2017-06-07 14:52:44.289044131 +0200 +@@ -27,7 +27,7 @@ + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ +- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ ++ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} crtreloc.o%s \ + crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}" + + #undef ENDFILE_SPEC diff --git a/toolchain/gcc/patches/7.5.0/c6x-disable-multilib.patch b/toolchain/gcc/patches/7.5.0/c6x-disable-multilib.patch new file mode 100644 index 000000000..8637b2cd2 --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/c6x-disable-multilib.patch @@ -0,0 +1,10 @@ +diff -Nur gcc-7.3.0.orig/gcc/config/c6x/t-c6x-uclinux gcc-7.3.0/gcc/config/c6x/t-c6x-uclinux +--- gcc-7.3.0.orig/gcc/config/c6x/t-c6x-uclinux 2011-11-02 16:23:48.424740000 +0100 ++++ gcc-7.3.0/gcc/config/c6x/t-c6x-uclinux 2018-06-01 08:14:36.679894633 +0200 +@@ -1,3 +1,3 @@ +-MULTILIB_OSDIRNAMES = march.c674x=!c674x +-MULTILIB_OSDIRNAMES += mbig-endian=!be +-MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x ++MULTILIB_OSDIRNAMES = ++#MULTILIB_OSDIRNAMES += mbig-endian=!be ++#MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x diff --git a/toolchain/gcc/patches/7.5.0/disable-split-stack-nothread.patch b/toolchain/gcc/patches/7.5.0/disable-split-stack-nothread.patch new file mode 100644 index 000000000..0038d7573 --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/disable-split-stack-nothread.patch @@ -0,0 +1,10 @@ +diff -Nur gcc-7.1.0.orig/libgcc/config/t-stack gcc-7.1.0/libgcc/config/t-stack +--- gcc-7.1.0.orig/libgcc/config/t-stack 2010-10-01 21:31:49.000000000 +0200 ++++ gcc-7.1.0/libgcc/config/t-stack 2017-06-23 19:55:25.215965555 +0200 +@@ -1,4 +1,6 @@ + # Makefile fragment to provide generic support for -fsplit-stack. + # This should be used in config.host for any host which supports + # -fsplit-stack. ++ifeq ($(enable_threads),yes) + LIB2ADD_ST += $(srcdir)/generic-morestack.c $(srcdir)/generic-morestack-thread.c ++endif diff --git a/toolchain/gcc/patches/7.5.0/ia64-fix-libgcc.patch b/toolchain/gcc/patches/7.5.0/ia64-fix-libgcc.patch new file mode 100644 index 000000000..f1f3c8d2d --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/ia64-fix-libgcc.patch @@ -0,0 +1,17 @@ +diff -Nur gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c gcc-6.3.0/libgcc/config/ia64/fde-glibc.c +--- gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c 2016-01-04 15:30:50.000000000 +0100 ++++ gcc-6.3.0/libgcc/config/ia64/fde-glibc.c 2017-03-05 13:07:33.316600613 +0100 +@@ -25,6 +25,8 @@ + /* Locate the FDE entry for a given address, using glibc ld.so routines + to avoid register/deregister calls at DSO load/unload. */ + ++#ifndef inhibit_libc ++ + #ifndef _GNU_SOURCE + #define _GNU_SOURCE 1 + #endif +@@ -159,3 +161,4 @@ + + return data.ret; + } ++#endif diff --git a/toolchain/gcc/patches/7.5.0/j2.patch b/toolchain/gcc/patches/7.5.0/j2.patch new file mode 100644 index 000000000..aafbe0ea9 --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/j2.patch @@ -0,0 +1,343 @@ +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh-protos.h gcc-7.3.0/gcc/config/sh/sh-protos.h +--- gcc-7.3.0.orig/gcc/config/sh/sh-protos.h 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/sh-protos.h 2018-06-03 02:20:50.000000000 +0200 +@@ -35,6 +35,9 @@ + SFUNC_STATIC + }; + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #ifdef RTX_CODE + extern rtx sh_fsca_sf2int (void); + extern rtx sh_fsca_int2sf (void); +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.c gcc-7.3.0/gcc/config/sh/sh.c +--- gcc-7.3.0.orig/gcc/config/sh/sh.c 2017-04-04 00:30:56.000000000 +0200 ++++ gcc-7.3.0/gcc/config/sh/sh.c 2018-06-03 02:20:50.000000000 +0200 +@@ -662,6 +662,7 @@ + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -669,6 +670,7 @@ + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -747,6 +749,9 @@ + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -803,6 +808,8 @@ + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.h gcc-7.3.0/gcc/config/sh/sh.h +--- gcc-7.3.0.orig/gcc/config/sh/sh.h 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/sh.h 2018-06-03 02:20:50.000000000 +0200 +@@ -83,6 +83,7 @@ + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -115,6 +116,7 @@ + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -122,6 +124,7 @@ + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -154,7 +157,7 @@ + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -229,7 +232,8 @@ + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -345,6 +349,7 @@ + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -1568,7 +1573,7 @@ + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1833,6 +1838,7 @@ + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.opt gcc-7.3.0/gcc/config/sh/sh.opt +--- gcc-7.3.0.orig/gcc/config/sh/sh.opt 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/sh.opt 2018-06-03 02:20:50.000000000 +0200 +@@ -65,6 +65,10 @@ + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sync.md gcc-7.3.0/gcc/config/sh/sync.md +--- gcc-7.3.0.orig/gcc/config/sh/sync.md 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/sync.md 2018-06-03 02:20:50.000000000 +0200 +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff -Nur gcc-7.3.0.orig/gcc/config/sh/t-sh gcc-7.3.0/gcc/config/sh/t-sh +--- gcc-7.3.0.orig/gcc/config/sh/t-sh 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/t-sh 2018-06-03 02:20:50.000000000 +0200 +@@ -50,7 +50,8 @@ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true +diff -Nur gcc-7.3.0.orig/gcc/config.gcc gcc-7.3.0/gcc/config.gcc +--- gcc-7.3.0.orig/gcc/config.gcc 2018-01-08 14:39:11.000000000 +0100 ++++ gcc-7.3.0/gcc/config.gcc 2018-06-03 02:20:50.000000000 +0200 +@@ -474,7 +474,7 @@ + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2664,18 +2664,18 @@ + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[n1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2742,6 +2742,7 @@ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2763,7 +2764,7 @@ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2772,9 +2773,9 @@ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2789,7 +2790,8 @@ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2806,7 +2808,7 @@ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4380,6 +4382,8 @@ + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4589,7 +4593,7 @@ + tmake_file="rs6000/t-rs6000 ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; diff --git a/toolchain/gcc/patches/7.5.0/m68k-coldfire-pr68467.patch b/toolchain/gcc/patches/7.5.0/m68k-coldfire-pr68467.patch new file mode 100644 index 000000000..45e9eb0ba --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/m68k-coldfire-pr68467.patch @@ -0,0 +1,43 @@ +diff -Nur gcc-7.2.0.orig/gcc/config/m68k/m68k.c gcc-7.2.0/gcc/config/m68k/m68k.c +--- gcc-7.2.0.orig/gcc/config/m68k/m68k.c 2017-04-03 22:30:56.274463000 +0000 ++++ gcc-7.2.0/gcc/config/m68k/m68k.c 2018-01-27 02:16:53.779367849 +0000 +@@ -182,6 +182,8 @@ + const_tree, bool); + static bool m68k_cannot_force_const_mem (machine_mode mode, rtx x); + static bool m68k_output_addr_const_extra (FILE *, rtx); ++static machine_mode m68k_promote_function_mode (const_tree, machine_mode, ++ int *, const_tree, int); + static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED; + static enum flt_eval_method + m68k_excess_precision (enum excess_precision_type); +@@ -332,6 +334,9 @@ + #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL + #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128 + ++#undef TARGET_PROMOTE_FUNCTION_MODE ++#define TARGET_PROMOTE_FUNCTION_MODE m68k_promote_function_mode ++ + static const struct attribute_spec m68k_attribute_table[] = + { + /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, +@@ -6571,4 +6576,20 @@ + return FLT_EVAL_METHOD_UNPREDICTABLE; + } + ++/* Implement TARGET_PROMOTE_FUNCTION_MODE. */ ++ ++static machine_mode ++m68k_promote_function_mode (const_tree type, machine_mode mode, ++ int *punsignedp ATTRIBUTE_UNUSED, ++ const_tree fntype ATTRIBUTE_UNUSED, ++ int for_return) ++{ ++ /* Promote libcall arguments narrower than int to match the normal C ++ ABI (for which promotions are handled via ++ TARGET_PROMOTE_PROTOTYPES). */ ++ if (type == NULL_TREE && !for_return && (mode == QImode || mode == HImode)) ++ return SImode; ++ return mode; ++} ++ + #include "gt-m68k.h" diff --git a/toolchain/gcc/patches/7.5.0/m68k-musl.patch b/toolchain/gcc/patches/7.5.0/m68k-musl.patch new file mode 100644 index 000000000..a7effec4c --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/m68k-musl.patch @@ -0,0 +1,25 @@ +diff -Nur gcc-7.3.0.orig/gcc/config/m68k/linux.h gcc-7.3.0/gcc/config/m68k/linux.h +--- gcc-7.3.0.orig/gcc/config/m68k/linux.h 2017-01-06 22:21:02.000000000 +0100 ++++ gcc-7.3.0/gcc/config/m68k/linux.h 2018-10-05 06:38:51.000000000 +0200 +@@ -73,6 +73,9 @@ + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "-m m68kelf %{shared} \ + %{!shared: \ +diff -Nur gcc-7.3.0.orig/libgcc/config/m68k/linux-unwind.h gcc-7.3.0/libgcc/config/m68k/linux-unwind.h +--- gcc-7.3.0.orig/libgcc/config/m68k/linux-unwind.h 2017-07-04 12:22:56.000000000 +0200 ++++ gcc-7.3.0/libgcc/config/m68k/linux-unwind.h 2018-10-05 06:38:51.000000000 +0200 +@@ -37,7 +37,7 @@ + stack_t uc_stack; + mcontext_t uc_mcontext; + unsigned long uc_filler[80]; +- __sigset_t uc_sigmask; ++ sigset_t uc_sigmask; + }; + + #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/toolchain/gcc/patches/7.5.0/microblaze.patch b/toolchain/gcc/patches/7.5.0/microblaze.patch new file mode 100644 index 000000000..eb6c08492 --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/microblaze.patch @@ -0,0 +1,23 @@ +revert 6dcad60c0ef48af584395a40feeb256fb82986a8 +as it breaks any userland in qemu + +diff -Nur gcc-6.3.0.orig/gcc/config/microblaze/microblaze.h gcc-6.3.0/gcc/config/microblaze/microblaze.h +--- gcc-6.3.0.orig/gcc/config/microblaze/microblaze.h 2016-01-21 18:10:54.000000000 +0100 ++++ gcc-6.3.0/gcc/config/microblaze/microblaze.h 2017-05-26 18:33:31.297534916 +0200 +@@ -253,14 +253,14 @@ + #define FIXED_REGISTERS \ + { \ + 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \ +- 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1 \ + } + + #define CALL_USED_REGISTERS \ + { \ + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ +- 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ ++ 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 1, 1, 1, 1 \ + } + #define GP_REG_FIRST 0 diff --git a/toolchain/gcc/patches/7.5.0/musl-s390x.patch b/toolchain/gcc/patches/7.5.0/musl-s390x.patch new file mode 100644 index 000000000..1163bdbf4 --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/musl-s390x.patch @@ -0,0 +1,13 @@ +diff -Nur gcc-7.2.0.orig/gcc/config/s390/linux.h gcc-7.2.0/gcc/config/s390/linux.h +--- gcc-7.2.0.orig/gcc/config/s390/linux.h 2017-02-06 11:25:05.513198000 +0100 ++++ gcc-7.2.0/gcc/config/s390/linux.h 2017-10-30 13:22:45.348170100 +0100 +@@ -76,6 +76,9 @@ + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" + #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" + ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC \ + "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/toolchain/gcc/patches/7.5.0/nios2-softfp.patch b/toolchain/gcc/patches/7.5.0/nios2-softfp.patch new file mode 100644 index 000000000..c677c6c2f --- /dev/null +++ b/toolchain/gcc/patches/7.5.0/nios2-softfp.patch @@ -0,0 +1,14 @@ +diff -Nur gcc-6.2.0.orig/libgcc/config.host gcc-6.2.0/libgcc/config.host +--- gcc-6.2.0.orig/libgcc/config.host 2016-05-17 08:15:52.000000000 +0200 ++++ gcc-6.2.0/libgcc/config.host 2016-10-15 14:42:53.971919904 +0200 +@@ -962,6 +962,10 @@ + ;; + esac + ;; ++nios2-*-linux-uclibc*) ++ tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc t-softfp-sfdf t-softfp" ++ md_unwind_header=nios2/linux-unwind.h ++ ;; + nios2-*-linux*) + tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc" + md_unwind_header=nios2/linux-unwind.h diff --git a/toolchain/gcc/patches/8.4.0/0002-xtensa-fix-PR-target-91880.patch b/toolchain/gcc/patches/8.4.0/0002-xtensa-fix-PR-target-91880.patch deleted file mode 100644 index e65352501..000000000 --- a/toolchain/gcc/patches/8.4.0/0002-xtensa-fix-PR-target-91880.patch +++ /dev/null @@ -1,49 +0,0 @@ -From 7c11710230921246156aecc20eb4b6ccaeaaa473 Mon Sep 17 00:00:00 2001 -From: Max Filippov -Date: Tue, 24 Sep 2019 04:15:17 -0700 -Subject: [PATCH] xtensa: fix PR target/91880 - -Xtensa hwloop_optimize segfaults when zero overhead loop is about to be -inserted as the first instruction of the function. -Insert zero overhead loop instruction into new basic block before the -loop when basic block that precedes the loop is empty. - -2019-09-26 Max Filippov -gcc/ - * config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead - loop instruction into new basic block before the loop when basic - block that precedes the loop is empty. - -Signed-off-by: Max Filippov ---- -Backported from: r276166 - - gcc/config/xtensa/xtensa.c | 5 ++-- - 1 file changed, 3 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c -index ee5612441e25..2527468d57db 100644 ---- a/gcc/config/xtensa/xtensa.c -+++ b/gcc/config/xtensa/xtensa.c -@@ -4232,7 +4232,9 @@ hwloop_optimize (hwloop_info loop) - - seq = get_insns (); - -- if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1) -+ entry_after = BB_END (entry_bb); -+ if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1 -+ || !entry_after) - { - basic_block new_bb; - edge e; -@@ -4253,7 +4255,6 @@ hwloop_optimize (hwloop_info loop) - } - else - { -- entry_after = BB_END (entry_bb); - while (DEBUG_INSN_P (entry_after) - || (NOTE_P (entry_after) - && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK)) --- -2.11.0 - diff --git a/toolchain/gcc/patches/8.4.0/add-crtreloc.frv b/toolchain/gcc/patches/8.4.0/add-crtreloc.frv deleted file mode 100644 index 30de24cdc..000000000 --- a/toolchain/gcc/patches/8.4.0/add-crtreloc.frv +++ /dev/null @@ -1,12 +0,0 @@ -diff -Nur gcc-8.3.0.orig/gcc/config/frv/linux.h gcc-8.3.0/gcc/config/frv/linux.h ---- gcc-8.3.0.orig/gcc/config/frv/linux.h 2018-01-03 11:03:58.000000000 +0100 -+++ gcc-8.3.0/gcc/config/frv/linux.h 2019-10-08 10:52:00.176295821 +0200 -@@ -27,7 +27,7 @@ - - #undef STARTFILE_SPEC - #define STARTFILE_SPEC \ -- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ -+ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} crtreloc.o%s \ - crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}" - - #undef ENDFILE_SPEC diff --git a/toolchain/gcc/patches/8.4.0/c6x-disable-multilib.patch b/toolchain/gcc/patches/8.4.0/c6x-disable-multilib.patch deleted file mode 100644 index cbee6f785..000000000 --- a/toolchain/gcc/patches/8.4.0/c6x-disable-multilib.patch +++ /dev/null @@ -1,10 +0,0 @@ -diff -Nur gcc-8.3.0.orig/gcc/config/c6x/t-c6x-uclinux gcc-8.3.0/gcc/config/c6x/t-c6x-uclinux ---- gcc-8.3.0.orig/gcc/config/c6x/t-c6x-uclinux 2011-11-02 16:23:48.000000000 +0100 -+++ gcc-8.3.0/gcc/config/c6x/t-c6x-uclinux 2019-10-08 07:49:50.255159650 +0200 -@@ -1,3 +1,3 @@ --MULTILIB_OSDIRNAMES = march.c674x=!c674x --MULTILIB_OSDIRNAMES += mbig-endian=!be --MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x -+MULTILIB_OSDIRNAMES = -+#MULTILIB_OSDIRNAMES += mbig-endian=!be -+#MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x diff --git a/toolchain/gcc/patches/8.4.0/ia64-fix-libgcc.patch b/toolchain/gcc/patches/8.4.0/ia64-fix-libgcc.patch deleted file mode 100644 index f1f3c8d2d..000000000 --- a/toolchain/gcc/patches/8.4.0/ia64-fix-libgcc.patch +++ /dev/null @@ -1,17 +0,0 @@ -diff -Nur gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c gcc-6.3.0/libgcc/config/ia64/fde-glibc.c ---- gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c 2016-01-04 15:30:50.000000000 +0100 -+++ gcc-6.3.0/libgcc/config/ia64/fde-glibc.c 2017-03-05 13:07:33.316600613 +0100 -@@ -25,6 +25,8 @@ - /* Locate the FDE entry for a given address, using glibc ld.so routines - to avoid register/deregister calls at DSO load/unload. */ - -+#ifndef inhibit_libc -+ - #ifndef _GNU_SOURCE - #define _GNU_SOURCE 1 - #endif -@@ -159,3 +161,4 @@ - - return data.ret; - } -+#endif diff --git a/toolchain/gcc/patches/8.4.0/j2.patch b/toolchain/gcc/patches/8.4.0/j2.patch deleted file mode 100644 index aafbe0ea9..000000000 --- a/toolchain/gcc/patches/8.4.0/j2.patch +++ /dev/null @@ -1,343 +0,0 @@ -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh-protos.h gcc-7.3.0/gcc/config/sh/sh-protos.h ---- gcc-7.3.0.orig/gcc/config/sh/sh-protos.h 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/sh-protos.h 2018-06-03 02:20:50.000000000 +0200 -@@ -35,6 +35,9 @@ - SFUNC_STATIC - }; - -+#define TARGET_ATOMIC_HARD_CAS \ -+ (selected_atomic_model ().type == sh_atomic_model::hard_cas) -+ - #ifdef RTX_CODE - extern rtx sh_fsca_sf2int (void); - extern rtx sh_fsca_int2sf (void); -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.c gcc-7.3.0/gcc/config/sh/sh.c ---- gcc-7.3.0.orig/gcc/config/sh/sh.c 2017-04-04 00:30:56.000000000 +0200 -+++ gcc-7.3.0/gcc/config/sh/sh.c 2018-06-03 02:20:50.000000000 +0200 -@@ -662,6 +662,7 @@ - model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; - model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; - model_names[sh_atomic_model::soft_imask] = "soft-imask"; -+ model_names[sh_atomic_model::hard_cas] = "hard-cas"; - - const char* model_cdef_names[sh_atomic_model::num_models]; - model_cdef_names[sh_atomic_model::none] = "NONE"; -@@ -669,6 +670,7 @@ - model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; - model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; - model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; -+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; - - sh_atomic_model ret; - ret.type = sh_atomic_model::none; -@@ -747,6 +749,9 @@ - if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) - err_ret ("cannot use atomic model %s in user mode", ret.name); - -+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) -+ err_ret ("atomic model %s is only available J2 targets", ret.name); -+ - return ret; - - #undef err_ret -@@ -803,6 +808,8 @@ - sh_cpu = PROCESSOR_SH2E; - if (TARGET_SH2A) - sh_cpu = PROCESSOR_SH2A; -+ if (TARGET_SHJ2) -+ sh_cpu = PROCESSOR_SHJ2; - if (TARGET_SH3) - sh_cpu = PROCESSOR_SH3; - if (TARGET_SH3E) -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.h gcc-7.3.0/gcc/config/sh/sh.h ---- gcc-7.3.0.orig/gcc/config/sh/sh.h 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/sh.h 2018-06-03 02:20:50.000000000 +0200 -@@ -83,6 +83,7 @@ - #define SUPPORT_SH4_SINGLE 1 - #define SUPPORT_SH2A 1 - #define SUPPORT_SH2A_SINGLE 1 -+#define SUPPORT_SHJ2 1 - #endif - - #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) -@@ -115,6 +116,7 @@ - #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) - #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) - #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) -+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) - - #if SUPPORT_SH1 - #define SUPPORT_SH2 1 -@@ -122,6 +124,7 @@ - #if SUPPORT_SH2 - #define SUPPORT_SH3 1 - #define SUPPORT_SH2A_NOFPU 1 -+#define SUPPORT_SHJ2 1 - #endif - #if SUPPORT_SH3 - #define SUPPORT_SH4_NOFPU 1 -@@ -154,7 +157,7 @@ - #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ - | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ - | MASK_HARD_SH4 | MASK_FPU_SINGLE \ -- | MASK_FPU_SINGLE_ONLY) -+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) - - /* This defaults us to big-endian. */ - #ifndef TARGET_ENDIAN_DEFAULT -@@ -229,7 +232,8 @@ - %{m2a-single:--isa=sh2a} \ - %{m2a-single-only:--isa=sh2a} \ - %{m2a-nofpu:--isa=sh2a-nofpu} \ --%{m4al:-dsp}" -+%{m4al:-dsp} \ -+%{mj2:-isa=j2}" - - #define ASM_SPEC SH_ASM_SPEC - -@@ -345,6 +349,7 @@ - hard_llcs, - soft_tcb, - soft_imask, -+ hard_cas, - - num_models - }; -@@ -1568,7 +1573,7 @@ - - /* Nonzero if the target supports dynamic shift instructions - like shad and shld. */ --#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) -+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) - - /* The cost of using the dynamic shift insns (shad, shld) are the same - if they are available. If they are not available a library function will -@@ -1833,6 +1838,7 @@ - PROCESSOR_SH2, - PROCESSOR_SH2E, - PROCESSOR_SH2A, -+ PROCESSOR_SHJ2, - PROCESSOR_SH3, - PROCESSOR_SH3E, - PROCESSOR_SH4, -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.opt gcc-7.3.0/gcc/config/sh/sh.opt ---- gcc-7.3.0.orig/gcc/config/sh/sh.opt 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/sh.opt 2018-06-03 02:20:50.000000000 +0200 -@@ -65,6 +65,10 @@ - Target RejectNegative Condition(SUPPORT_SH2E) - Generate SH2e code. - -+mj2 -+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) -+Generate J2 code. -+ - m3 - Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) - Generate SH3 code. -diff -Nur gcc-7.3.0.orig/gcc/config/sh/sync.md gcc-7.3.0/gcc/config/sh/sync.md ---- gcc-7.3.0.orig/gcc/config/sh/sync.md 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/sync.md 2018-06-03 02:20:50.000000000 +0200 -@@ -240,6 +240,9 @@ - || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) - atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, - exp_val, new_val); -+ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) -+ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, -+ exp_val, new_val); - else if (TARGET_ATOMIC_SOFT_GUSA) - atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, - exp_val, new_val); -@@ -306,6 +309,57 @@ - } - [(set_attr "length" "14")]) - -+(define_expand "atomic_compare_and_swapsi_cas" -+ [(set (match_operand:SI 0 "register_operand" "=r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") -+ (match_operand:SI 2 "register_operand" "r") -+ (match_operand:SI 3 "register_operand" "r")] -+ UNSPECV_CMPXCHG_1))] -+ "TARGET_ATOMIC_HARD_CAS" -+{ -+ rtx mem = gen_rtx_REG (SImode, 0); -+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); -+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); -+ DONE; -+}) -+ -+(define_insn "shj2_cas" -+ [(set (match_operand:SI 0 "register_operand" "=&r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "register_operand" "=r") -+ (match_operand:SI 2 "register_operand" "r") -+ (match_operand:SI 3 "register_operand" "0")] -+ UNSPECV_CMPXCHG_1)) -+ (set (reg:SI T_REG) -+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] -+ "TARGET_ATOMIC_HARD_CAS" -+ "cas.l %2,%0,@%1" -+ [(set_attr "length" "2")] -+) -+ -+(define_expand "atomic_compare_and_swapqi_cas" -+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") -+ (match_operand:SI 2 "arith_operand" "rI08") -+ (match_operand:SI 3 "arith_operand" "rI08")] -+ UNSPECV_CMPXCHG_1))] -+ "TARGET_ATOMIC_HARD_CAS" -+{FAIL;} -+) -+ -+(define_expand "atomic_compare_and_swaphi_cas" -+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") -+ (unspec_volatile:SI -+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") -+ (match_operand:SI 2 "arith_operand" "rI08") -+ (match_operand:SI 3 "arith_operand" "rI08")] -+ UNSPECV_CMPXCHG_1))] -+ "TARGET_ATOMIC_HARD_CAS" -+{FAIL;} -+) -+ - ;; The QIHImode llcs patterns modify the address register of the memory - ;; operand. In order to express that, we have to open code the memory - ;; operand. Initially the insn is expanded like every other atomic insn -diff -Nur gcc-7.3.0.orig/gcc/config/sh/t-sh gcc-7.3.0/gcc/config/sh/t-sh ---- gcc-7.3.0.orig/gcc/config/sh/t-sh 2017-01-01 13:07:43.000000000 +0100 -+++ gcc-7.3.0/gcc/config/sh/t-sh 2018-06-03 02:20:50.000000000 +0200 -@@ -50,7 +50,8 @@ - m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ - m2a-single,m2a-single-only \ - m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ -- m4,m4-100,m4-200,m4-300,m4a; do \ -+ m4,m4-100,m4-200,m4-300,m4a \ -+ mj2; do \ - subst= ; \ - for lib in `echo $$abi|tr , ' '` ; do \ - if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ -@@ -63,9 +64,9 @@ - - # SH1 and SH2A support big endian only. - ifeq ($(DEFAULT_ENDIAN),ml) --MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) -+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) - else --MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) -+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) - endif - - MULTILIB_OSDIRNAMES = \ -@@ -87,7 +88,8 @@ - m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ - m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ - m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ -- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al -+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ -+ mj2=!j2 - - $(out_object_file): gt-sh.h - gt-sh.h : s-gtype ; @true -diff -Nur gcc-7.3.0.orig/gcc/config.gcc gcc-7.3.0/gcc/config.gcc ---- gcc-7.3.0.orig/gcc/config.gcc 2018-01-08 14:39:11.000000000 +0100 -+++ gcc-7.3.0/gcc/config.gcc 2018-06-03 02:20:50.000000000 +0200 -@@ -474,7 +474,7 @@ - extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" - ;; - # Note the 'l'; we need to be able to match e.g. "shle" or "shl". --sh[123456789lbe]*-*-* | sh-*-*) -+sh[123456789lbej]*-*-* | sh-*-*) - cpu_type=sh - extra_options="${extra_options} fused-madd.opt" - extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" -@@ -2664,18 +2664,18 @@ - extra_options="${extra_options} s390/tpf.opt" - tmake_file="${tmake_file} s390/t-s390" - ;; --sh-*-elf* | sh[12346l]*-*-elf* | \ -- sh-*-linux* | sh[2346lbe]*-*-linux* | \ -+sh-*-elf* | sh[12346lj]*-*-elf* | \ -+ sh-*-linux* | sh[2346lbej]*-*-linux* | \ - sh-*-netbsdelf* | shl*-*-netbsdelf*) - tmake_file="${tmake_file} sh/t-sh sh/t-elf" - if test x${with_endian} = x; then - case ${target} in -- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; -+ sh[j1234]*be-*-* | sh[n1234]*eb-*-*) with_endian=big ;; - shbe-*-* | sheb-*-*) with_endian=big,little ;; - sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; - shl* | sh*-*-linux* | \ - sh-superh-elf) with_endian=little,big ;; -- sh[1234]*-*-*) with_endian=big ;; -+ sh[j1234]*-*-*) with_endian=big ;; - *) with_endian=big,little ;; - esac - fi -@@ -2742,6 +2742,7 @@ - sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; - sh2a*) sh_cpu_target=sh2a ;; - sh2e*) sh_cpu_target=sh2e ;; -+ shj2*) sh_cpu_target=shj2;; - sh2*) sh_cpu_target=sh2 ;; - *) sh_cpu_target=sh1 ;; - esac -@@ -2763,7 +2764,7 @@ - sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ - sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ - sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ -- sh3e | sh3 | sh2e | sh2 | sh1) ;; -+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; - "") sh_cpu_default=${sh_cpu_target} ;; - *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; - esac -@@ -2772,9 +2773,9 @@ - case ${target} in - sh[1234]*) sh_multilibs=${sh_cpu_target} ;; - sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; -- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; -+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; - sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; -- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; -+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; - esac - if test x$with_fp = xno; then - sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" -@@ -2789,7 +2790,8 @@ - m1 | m2 | m2e | m3 | m3e | \ - m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ - m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ -- m2a | m2a-single | m2a-single-only | m2a-nofpu) -+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ -+ mj2) - # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition - # It is passed to MULTIILIB_OPTIONS verbatim. - TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" -@@ -2806,7 +2808,7 @@ - done - TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` - if test x${enable_incomplete_targets} = xyes ; then -- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" -+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" - fi - tm_file="$tm_file ./sysroot-suffix.h" - tmake_file="$tmake_file t-sysroot-suffix" -@@ -4380,6 +4382,8 @@ - ;; - m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) - ;; -+ mj2) -+ ;; - *) - echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 - echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 -@@ -4589,7 +4593,7 @@ - tmake_file="rs6000/t-rs6000 ${tmake_file}" - ;; - -- sh[123456ble]*-*-* | sh-*-*) -+ sh[123456blej]*-*-* | sh-*-*) - c_target_objs="${c_target_objs} sh-c.o" - cxx_target_objs="${cxx_target_objs} sh-c.o" - ;; diff --git a/toolchain/gcc/patches/8.4.0/m68k-musl.patch b/toolchain/gcc/patches/8.4.0/m68k-musl.patch deleted file mode 100644 index a7effec4c..000000000 --- a/toolchain/gcc/patches/8.4.0/m68k-musl.patch +++ /dev/null @@ -1,25 +0,0 @@ -diff -Nur gcc-7.3.0.orig/gcc/config/m68k/linux.h gcc-7.3.0/gcc/config/m68k/linux.h ---- gcc-7.3.0.orig/gcc/config/m68k/linux.h 2017-01-06 22:21:02.000000000 +0100 -+++ gcc-7.3.0/gcc/config/m68k/linux.h 2018-10-05 06:38:51.000000000 +0200 -@@ -73,6 +73,9 @@ - - #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" - -+#undef MUSL_DYNAMIC_LINKER -+#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" -+ - #undef LINK_SPEC - #define LINK_SPEC "-m m68kelf %{shared} \ - %{!shared: \ -diff -Nur gcc-7.3.0.orig/libgcc/config/m68k/linux-unwind.h gcc-7.3.0/libgcc/config/m68k/linux-unwind.h ---- gcc-7.3.0.orig/libgcc/config/m68k/linux-unwind.h 2017-07-04 12:22:56.000000000 +0200 -+++ gcc-7.3.0/libgcc/config/m68k/linux-unwind.h 2018-10-05 06:38:51.000000000 +0200 -@@ -37,7 +37,7 @@ - stack_t uc_stack; - mcontext_t uc_mcontext; - unsigned long uc_filler[80]; -- __sigset_t uc_sigmask; -+ sigset_t uc_sigmask; - }; - - #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/toolchain/gcc/patches/8.4.0/musl-s390x.patch b/toolchain/gcc/patches/8.4.0/musl-s390x.patch deleted file mode 100644 index 1163bdbf4..000000000 --- a/toolchain/gcc/patches/8.4.0/musl-s390x.patch +++ /dev/null @@ -1,13 +0,0 @@ -diff -Nur gcc-7.2.0.orig/gcc/config/s390/linux.h gcc-7.2.0/gcc/config/s390/linux.h ---- gcc-7.2.0.orig/gcc/config/s390/linux.h 2017-02-06 11:25:05.513198000 +0100 -+++ gcc-7.2.0/gcc/config/s390/linux.h 2017-10-30 13:22:45.348170100 +0100 -@@ -76,6 +76,9 @@ - #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" - #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" - -+#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" -+#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" -+ - #undef LINK_SPEC - #define LINK_SPEC \ - "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/toolchain/gcc/patches/8.4.0/nios2-softfp.patch b/toolchain/gcc/patches/8.4.0/nios2-softfp.patch deleted file mode 100644 index c677c6c2f..000000000 --- a/toolchain/gcc/patches/8.4.0/nios2-softfp.patch +++ /dev/null @@ -1,14 +0,0 @@ -diff -Nur gcc-6.2.0.orig/libgcc/config.host gcc-6.2.0/libgcc/config.host ---- gcc-6.2.0.orig/libgcc/config.host 2016-05-17 08:15:52.000000000 +0200 -+++ gcc-6.2.0/libgcc/config.host 2016-10-15 14:42:53.971919904 +0200 -@@ -962,6 +962,10 @@ - ;; - esac - ;; -+nios2-*-linux-uclibc*) -+ tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc t-softfp-sfdf t-softfp" -+ md_unwind_header=nios2/linux-unwind.h -+ ;; - nios2-*-linux*) - tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc" - md_unwind_header=nios2/linux-unwind.h diff --git a/toolchain/gcc/patches/8.5.0/add-crtreloc.frv b/toolchain/gcc/patches/8.5.0/add-crtreloc.frv new file mode 100644 index 000000000..30de24cdc --- /dev/null +++ b/toolchain/gcc/patches/8.5.0/add-crtreloc.frv @@ -0,0 +1,12 @@ +diff -Nur gcc-8.3.0.orig/gcc/config/frv/linux.h gcc-8.3.0/gcc/config/frv/linux.h +--- gcc-8.3.0.orig/gcc/config/frv/linux.h 2018-01-03 11:03:58.000000000 +0100 ++++ gcc-8.3.0/gcc/config/frv/linux.h 2019-10-08 10:52:00.176295821 +0200 +@@ -27,7 +27,7 @@ + + #undef STARTFILE_SPEC + #define STARTFILE_SPEC \ +- "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} \ ++ "%{!shared: %{pg|p|profile:gcrt1.o%s;pie:Scrt1.o%s;:crt1.o%s}} crtreloc.o%s \ + crti.o%s %{static:crtbeginT.o%s;shared|pie:crtbeginS.o%s;:crtbegin.o%s}" + + #undef ENDFILE_SPEC diff --git a/toolchain/gcc/patches/8.5.0/c6x-disable-multilib.patch b/toolchain/gcc/patches/8.5.0/c6x-disable-multilib.patch new file mode 100644 index 000000000..cbee6f785 --- /dev/null +++ b/toolchain/gcc/patches/8.5.0/c6x-disable-multilib.patch @@ -0,0 +1,10 @@ +diff -Nur gcc-8.3.0.orig/gcc/config/c6x/t-c6x-uclinux gcc-8.3.0/gcc/config/c6x/t-c6x-uclinux +--- gcc-8.3.0.orig/gcc/config/c6x/t-c6x-uclinux 2011-11-02 16:23:48.000000000 +0100 ++++ gcc-8.3.0/gcc/config/c6x/t-c6x-uclinux 2019-10-08 07:49:50.255159650 +0200 +@@ -1,3 +1,3 @@ +-MULTILIB_OSDIRNAMES = march.c674x=!c674x +-MULTILIB_OSDIRNAMES += mbig-endian=!be +-MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x ++MULTILIB_OSDIRNAMES = ++#MULTILIB_OSDIRNAMES += mbig-endian=!be ++#MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x diff --git a/toolchain/gcc/patches/8.5.0/ia64-fix-libgcc.patch b/toolchain/gcc/patches/8.5.0/ia64-fix-libgcc.patch new file mode 100644 index 000000000..f1f3c8d2d --- /dev/null +++ b/toolchain/gcc/patches/8.5.0/ia64-fix-libgcc.patch @@ -0,0 +1,17 @@ +diff -Nur gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c gcc-6.3.0/libgcc/config/ia64/fde-glibc.c +--- gcc-6.3.0.orig/libgcc/config/ia64/fde-glibc.c 2016-01-04 15:30:50.000000000 +0100 ++++ gcc-6.3.0/libgcc/config/ia64/fde-glibc.c 2017-03-05 13:07:33.316600613 +0100 +@@ -25,6 +25,8 @@ + /* Locate the FDE entry for a given address, using glibc ld.so routines + to avoid register/deregister calls at DSO load/unload. */ + ++#ifndef inhibit_libc ++ + #ifndef _GNU_SOURCE + #define _GNU_SOURCE 1 + #endif +@@ -159,3 +161,4 @@ + + return data.ret; + } ++#endif diff --git a/toolchain/gcc/patches/8.5.0/j2.patch b/toolchain/gcc/patches/8.5.0/j2.patch new file mode 100644 index 000000000..aafbe0ea9 --- /dev/null +++ b/toolchain/gcc/patches/8.5.0/j2.patch @@ -0,0 +1,343 @@ +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh-protos.h gcc-7.3.0/gcc/config/sh/sh-protos.h +--- gcc-7.3.0.orig/gcc/config/sh/sh-protos.h 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/sh-protos.h 2018-06-03 02:20:50.000000000 +0200 +@@ -35,6 +35,9 @@ + SFUNC_STATIC + }; + ++#define TARGET_ATOMIC_HARD_CAS \ ++ (selected_atomic_model ().type == sh_atomic_model::hard_cas) ++ + #ifdef RTX_CODE + extern rtx sh_fsca_sf2int (void); + extern rtx sh_fsca_int2sf (void); +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.c gcc-7.3.0/gcc/config/sh/sh.c +--- gcc-7.3.0.orig/gcc/config/sh/sh.c 2017-04-04 00:30:56.000000000 +0200 ++++ gcc-7.3.0/gcc/config/sh/sh.c 2018-06-03 02:20:50.000000000 +0200 +@@ -662,6 +662,7 @@ + model_names[sh_atomic_model::hard_llcs] = "hard-llcs"; + model_names[sh_atomic_model::soft_tcb] = "soft-tcb"; + model_names[sh_atomic_model::soft_imask] = "soft-imask"; ++ model_names[sh_atomic_model::hard_cas] = "hard-cas"; + + const char* model_cdef_names[sh_atomic_model::num_models]; + model_cdef_names[sh_atomic_model::none] = "NONE"; +@@ -669,6 +670,7 @@ + model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS"; + model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB"; + model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK"; ++ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS"; + + sh_atomic_model ret; + ret.type = sh_atomic_model::none; +@@ -747,6 +749,9 @@ + if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE) + err_ret ("cannot use atomic model %s in user mode", ret.name); + ++ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2) ++ err_ret ("atomic model %s is only available J2 targets", ret.name); ++ + return ret; + + #undef err_ret +@@ -803,6 +808,8 @@ + sh_cpu = PROCESSOR_SH2E; + if (TARGET_SH2A) + sh_cpu = PROCESSOR_SH2A; ++ if (TARGET_SHJ2) ++ sh_cpu = PROCESSOR_SHJ2; + if (TARGET_SH3) + sh_cpu = PROCESSOR_SH3; + if (TARGET_SH3E) +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.h gcc-7.3.0/gcc/config/sh/sh.h +--- gcc-7.3.0.orig/gcc/config/sh/sh.h 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/sh.h 2018-06-03 02:20:50.000000000 +0200 +@@ -83,6 +83,7 @@ + #define SUPPORT_SH4_SINGLE 1 + #define SUPPORT_SH2A 1 + #define SUPPORT_SH2A_SINGLE 1 ++#define SUPPORT_SHJ2 1 + #endif + + #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) +@@ -115,6 +116,7 @@ + #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) + #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) + #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) ++#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2) + + #if SUPPORT_SH1 + #define SUPPORT_SH2 1 +@@ -122,6 +124,7 @@ + #if SUPPORT_SH2 + #define SUPPORT_SH3 1 + #define SUPPORT_SH2A_NOFPU 1 ++#define SUPPORT_SHJ2 1 + #endif + #if SUPPORT_SH3 + #define SUPPORT_SH4_NOFPU 1 +@@ -154,7 +157,7 @@ + #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ + | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ + | MASK_HARD_SH4 | MASK_FPU_SINGLE \ +- | MASK_FPU_SINGLE_ONLY) ++ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2) + + /* This defaults us to big-endian. */ + #ifndef TARGET_ENDIAN_DEFAULT +@@ -229,7 +232,8 @@ + %{m2a-single:--isa=sh2a} \ + %{m2a-single-only:--isa=sh2a} \ + %{m2a-nofpu:--isa=sh2a-nofpu} \ +-%{m4al:-dsp}" ++%{m4al:-dsp} \ ++%{mj2:-isa=j2}" + + #define ASM_SPEC SH_ASM_SPEC + +@@ -345,6 +349,7 @@ + hard_llcs, + soft_tcb, + soft_imask, ++ hard_cas, + + num_models + }; +@@ -1568,7 +1573,7 @@ + + /* Nonzero if the target supports dynamic shift instructions + like shad and shld. */ +-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) ++#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2) + + /* The cost of using the dynamic shift insns (shad, shld) are the same + if they are available. If they are not available a library function will +@@ -1833,6 +1838,7 @@ + PROCESSOR_SH2, + PROCESSOR_SH2E, + PROCESSOR_SH2A, ++ PROCESSOR_SHJ2, + PROCESSOR_SH3, + PROCESSOR_SH3E, + PROCESSOR_SH4, +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sh.opt gcc-7.3.0/gcc/config/sh/sh.opt +--- gcc-7.3.0.orig/gcc/config/sh/sh.opt 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/sh.opt 2018-06-03 02:20:50.000000000 +0200 +@@ -65,6 +65,10 @@ + Target RejectNegative Condition(SUPPORT_SH2E) + Generate SH2e code. + ++mj2 ++Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2) ++Generate J2 code. ++ + m3 + Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3) + Generate SH3 code. +diff -Nur gcc-7.3.0.orig/gcc/config/sh/sync.md gcc-7.3.0/gcc/config/sh/sync.md +--- gcc-7.3.0.orig/gcc/config/sh/sync.md 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/sync.md 2018-06-03 02:20:50.000000000 +0200 +@@ -240,6 +240,9 @@ + || (TARGET_SH4A && mode == SImode && !TARGET_ATOMIC_STRICT)) + atomic_insn = gen_atomic_compare_and_swap_hard (old_val, mem, + exp_val, new_val); ++ else if (TARGET_ATOMIC_HARD_CAS && mode == SImode) ++ atomic_insn = gen_atomic_compare_and_swap_cas (old_val, mem, ++ exp_val, new_val); + else if (TARGET_ATOMIC_SOFT_GUSA) + atomic_insn = gen_atomic_compare_and_swap_soft_gusa (old_val, mem, + exp_val, new_val); +@@ -306,6 +309,57 @@ + } + [(set_attr "length" "14")]) + ++(define_expand "atomic_compare_and_swapsi_cas" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "r")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{ ++ rtx mem = gen_rtx_REG (SImode, 0); ++ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0))); ++ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3])); ++ DONE; ++}) ++ ++(define_insn "shj2_cas" ++ [(set (match_operand:SI 0 "register_operand" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "register_operand" "=r") ++ (match_operand:SI 2 "register_operand" "r") ++ (match_operand:SI 3 "register_operand" "0")] ++ UNSPECV_CMPXCHG_1)) ++ (set (reg:SI T_REG) ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))] ++ "TARGET_ATOMIC_HARD_CAS" ++ "cas.l %2,%0,@%1" ++ [(set_attr "length" "2")] ++) ++ ++(define_expand "atomic_compare_and_swapqi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ ++(define_expand "atomic_compare_and_swaphi_cas" ++ [(set (match_operand:SI 0 "arith_reg_dest" "=&r") ++ (unspec_volatile:SI ++ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra") ++ (match_operand:SI 2 "arith_operand" "rI08") ++ (match_operand:SI 3 "arith_operand" "rI08")] ++ UNSPECV_CMPXCHG_1))] ++ "TARGET_ATOMIC_HARD_CAS" ++{FAIL;} ++) ++ + ;; The QIHImode llcs patterns modify the address register of the memory + ;; operand. In order to express that, we have to open code the memory + ;; operand. Initially the insn is expanded like every other atomic insn +diff -Nur gcc-7.3.0.orig/gcc/config/sh/t-sh gcc-7.3.0/gcc/config/sh/t-sh +--- gcc-7.3.0.orig/gcc/config/sh/t-sh 2017-01-01 13:07:43.000000000 +0100 ++++ gcc-7.3.0/gcc/config/sh/t-sh 2018-06-03 02:20:50.000000000 +0200 +@@ -50,7 +50,8 @@ + m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \ + m2a-single,m2a-single-only \ + m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \ +- m4,m4-100,m4-200,m4-300,m4a; do \ ++ m4,m4-100,m4-200,m4-300,m4a \ ++ mj2; do \ + subst= ; \ + for lib in `echo $$abi|tr , ' '` ; do \ + if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \ +@@ -63,9 +64,9 @@ + + # SH1 and SH2A support big endian only. + ifeq ($(DEFAULT_ENDIAN),ml) +-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + else +-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG) ++MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG) + endif + + MULTILIB_OSDIRNAMES = \ +@@ -87,7 +88,8 @@ + m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \ + m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \ + m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \ +- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al ++ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \ ++ mj2=!j2 + + $(out_object_file): gt-sh.h + gt-sh.h : s-gtype ; @true +diff -Nur gcc-7.3.0.orig/gcc/config.gcc gcc-7.3.0/gcc/config.gcc +--- gcc-7.3.0.orig/gcc/config.gcc 2018-01-08 14:39:11.000000000 +0100 ++++ gcc-7.3.0/gcc/config.gcc 2018-06-03 02:20:50.000000000 +0200 +@@ -474,7 +474,7 @@ + extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h" + ;; + # Note the 'l'; we need to be able to match e.g. "shle" or "shl". +-sh[123456789lbe]*-*-* | sh-*-*) ++sh[123456789lbej]*-*-* | sh-*-*) + cpu_type=sh + extra_options="${extra_options} fused-madd.opt" + extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o" +@@ -2664,18 +2664,18 @@ + extra_options="${extra_options} s390/tpf.opt" + tmake_file="${tmake_file} s390/t-s390" + ;; +-sh-*-elf* | sh[12346l]*-*-elf* | \ +- sh-*-linux* | sh[2346lbe]*-*-linux* | \ ++sh-*-elf* | sh[12346lj]*-*-elf* | \ ++ sh-*-linux* | sh[2346lbej]*-*-linux* | \ + sh-*-netbsdelf* | shl*-*-netbsdelf*) + tmake_file="${tmake_file} sh/t-sh sh/t-elf" + if test x${with_endian} = x; then + case ${target} in +- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;; ++ sh[j1234]*be-*-* | sh[n1234]*eb-*-*) with_endian=big ;; + shbe-*-* | sheb-*-*) with_endian=big,little ;; + sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;; + shl* | sh*-*-linux* | \ + sh-superh-elf) with_endian=little,big ;; +- sh[1234]*-*-*) with_endian=big ;; ++ sh[j1234]*-*-*) with_endian=big ;; + *) with_endian=big,little ;; + esac + fi +@@ -2742,6 +2742,7 @@ + sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;; + sh2a*) sh_cpu_target=sh2a ;; + sh2e*) sh_cpu_target=sh2e ;; ++ shj2*) sh_cpu_target=shj2;; + sh2*) sh_cpu_target=sh2 ;; + *) sh_cpu_target=sh1 ;; + esac +@@ -2763,7 +2764,7 @@ + sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \ + sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \ + sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \ +- sh3e | sh3 | sh2e | sh2 | sh1) ;; ++ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;; + "") sh_cpu_default=${sh_cpu_target} ;; + *) echo "with_cpu=$with_cpu not supported"; exit 1 ;; + esac +@@ -2772,9 +2773,9 @@ + case ${target} in + sh[1234]*) sh_multilibs=${sh_cpu_target} ;; + sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;; +- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;; ++ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;; + sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;; +- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;; ++ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;; + esac + if test x$with_fp = xno; then + sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`" +@@ -2789,7 +2790,8 @@ + m1 | m2 | m2e | m3 | m3e | \ + m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\ + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \ +- m2a | m2a-single | m2a-single-only | m2a-nofpu) ++ m2a | m2a-single | m2a-single-only | m2a-nofpu | \ ++ mj2) + # TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition + # It is passed to MULTIILIB_OPTIONS verbatim. + TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}" +@@ -2806,7 +2808,7 @@ + done + TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'` + if test x${enable_incomplete_targets} = xyes ; then +- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1" ++ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1" + fi + tm_file="$tm_file ./sysroot-suffix.h" + tmake_file="$tmake_file t-sysroot-suffix" +@@ -4380,6 +4382,8 @@ + ;; + m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al) + ;; ++ mj2) ++ ;; + *) + echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2 + echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2 +@@ -4589,7 +4593,7 @@ + tmake_file="rs6000/t-rs6000 ${tmake_file}" + ;; + +- sh[123456ble]*-*-* | sh-*-*) ++ sh[123456blej]*-*-* | sh-*-*) + c_target_objs="${c_target_objs} sh-c.o" + cxx_target_objs="${cxx_target_objs} sh-c.o" + ;; diff --git a/toolchain/gcc/patches/8.5.0/m68k-musl.patch b/toolchain/gcc/patches/8.5.0/m68k-musl.patch new file mode 100644 index 000000000..a7effec4c --- /dev/null +++ b/toolchain/gcc/patches/8.5.0/m68k-musl.patch @@ -0,0 +1,25 @@ +diff -Nur gcc-7.3.0.orig/gcc/config/m68k/linux.h gcc-7.3.0/gcc/config/m68k/linux.h +--- gcc-7.3.0.orig/gcc/config/m68k/linux.h 2017-01-06 22:21:02.000000000 +0100 ++++ gcc-7.3.0/gcc/config/m68k/linux.h 2018-10-05 06:38:51.000000000 +0200 +@@ -73,6 +73,9 @@ + + #define GLIBC_DYNAMIC_LINKER "/lib/ld.so.1" + ++#undef MUSL_DYNAMIC_LINKER ++#define MUSL_DYNAMIC_LINKER "/lib/ld-musl-m68k.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC "-m m68kelf %{shared} \ + %{!shared: \ +diff -Nur gcc-7.3.0.orig/libgcc/config/m68k/linux-unwind.h gcc-7.3.0/libgcc/config/m68k/linux-unwind.h +--- gcc-7.3.0.orig/libgcc/config/m68k/linux-unwind.h 2017-07-04 12:22:56.000000000 +0200 ++++ gcc-7.3.0/libgcc/config/m68k/linux-unwind.h 2018-10-05 06:38:51.000000000 +0200 +@@ -37,7 +37,7 @@ + stack_t uc_stack; + mcontext_t uc_mcontext; + unsigned long uc_filler[80]; +- __sigset_t uc_sigmask; ++ sigset_t uc_sigmask; + }; + + #define MD_FALLBACK_FRAME_STATE_FOR m68k_fallback_frame_state diff --git a/toolchain/gcc/patches/8.5.0/musl-s390x.patch b/toolchain/gcc/patches/8.5.0/musl-s390x.patch new file mode 100644 index 000000000..1163bdbf4 --- /dev/null +++ b/toolchain/gcc/patches/8.5.0/musl-s390x.patch @@ -0,0 +1,13 @@ +diff -Nur gcc-7.2.0.orig/gcc/config/s390/linux.h gcc-7.2.0/gcc/config/s390/linux.h +--- gcc-7.2.0.orig/gcc/config/s390/linux.h 2017-02-06 11:25:05.513198000 +0100 ++++ gcc-7.2.0/gcc/config/s390/linux.h 2017-10-30 13:22:45.348170100 +0100 +@@ -76,6 +76,9 @@ + #define GLIBC_DYNAMIC_LINKER32 "/lib/ld.so.1" + #define GLIBC_DYNAMIC_LINKER64 "/lib/ld64.so.1" + ++#define MUSL_DYNAMIC_LINKER32 "/lib/ld-musl-s390.so.1" ++#define MUSL_DYNAMIC_LINKER64 "/lib/ld-musl-s390x.so.1" ++ + #undef LINK_SPEC + #define LINK_SPEC \ + "%{m31:-m elf_s390}%{m64:-m elf64_s390} \ diff --git a/toolchain/gcc/patches/8.5.0/nios2-softfp.patch b/toolchain/gcc/patches/8.5.0/nios2-softfp.patch new file mode 100644 index 000000000..c677c6c2f --- /dev/null +++ b/toolchain/gcc/patches/8.5.0/nios2-softfp.patch @@ -0,0 +1,14 @@ +diff -Nur gcc-6.2.0.orig/libgcc/config.host gcc-6.2.0/libgcc/config.host +--- gcc-6.2.0.orig/libgcc/config.host 2016-05-17 08:15:52.000000000 +0200 ++++ gcc-6.2.0/libgcc/config.host 2016-10-15 14:42:53.971919904 +0200 +@@ -962,6 +962,10 @@ + ;; + esac + ;; ++nios2-*-linux-uclibc*) ++ tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc t-softfp-sfdf t-softfp" ++ md_unwind_header=nios2/linux-unwind.h ++ ;; + nios2-*-linux*) + tmake_file="$tmake_file nios2/t-nios2 nios2/t-linux t-libgcc-pic t-slibgcc-libgcc" + md_unwind_header=nios2/linux-unwind.h diff --git a/toolchain/gcc/patches/9.3.0/or1k.patch b/toolchain/gcc/patches/9.3.0/or1k.patch deleted file mode 100644 index 8ec5ec956..000000000 --- a/toolchain/gcc/patches/9.3.0/or1k.patch +++ /dev/null @@ -1,61 +0,0 @@ -diff -Nur gcc-9.2.0.orig/gcc/config/or1k/constraints.md gcc-9.2.0/gcc/config/or1k/constraints.md ---- gcc-9.2.0.orig/gcc/config/or1k/constraints.md 2019-01-01 13:31:55.000000000 +0100 -+++ gcc-9.2.0/gcc/config/or1k/constraints.md 2019-10-07 10:59:48.995389485 +0200 -@@ -32,6 +32,9 @@ - (define_register_constraint "c" "SIBCALL_REGS" - "Registers which can hold a sibling call address") - -+(define_register_constraint "t" "GOT_REGS" -+ "Registers which can be used to store the Global Offset Table (GOT) address.") -+ - ;; Immediates - (define_constraint "I" - "A signed 16-bit immediate in the range -32768 to 32767." -diff -Nur gcc-9.2.0.orig/gcc/config/or1k/or1k.h gcc-9.2.0/gcc/config/or1k/or1k.h ---- gcc-9.2.0.orig/gcc/config/or1k/or1k.h 2019-01-01 13:31:55.000000000 +0100 -+++ gcc-9.2.0/gcc/config/or1k/or1k.h 2019-10-07 12:14:41.334692831 +0200 -@@ -189,6 +189,7 @@ - { - NO_REGS, - SIBCALL_REGS, -+ GOT_REGS, - GENERAL_REGS, - FLAG_REGS, - ALL_REGS, -@@ -200,6 +201,7 @@ - #define REG_CLASS_NAMES { \ - "NO_REGS", \ - "SIBCALL_REGS", \ -+ "GOT_REGS", \ - "GENERAL_REGS", \ - "FLAG_REGS", \ - "ALL_REGS" } -@@ -212,6 +214,7 @@ - #define REG_CLASS_CONTENTS \ - { { 0x00000000, 0x00000000 }, \ - { SIBCALL_REGS_MASK, 0 }, \ -+ { 0xfffffdff, 0x00000000 }, \ - { 0xffffffff, 0x00000003 }, \ - { 0x00000000, 0x00000004 }, \ - { 0xffffffff, 0x00000007 } \ -diff -Nur gcc-9.2.0.orig/gcc/config/or1k/or1k.md gcc-9.2.0/gcc/config/or1k/or1k.md ---- gcc-9.2.0.orig/gcc/config/or1k/or1k.md 2019-01-01 13:31:55.000000000 +0100 -+++ gcc-9.2.0/gcc/config/or1k/or1k.md 2019-10-07 10:59:48.999389485 +0200 -@@ -595,7 +595,7 @@ - ;; set_got pattern below. This works because the set_got_tmp insn is the - ;; first insn in the stream and that it isn't moved during RA. - (define_insn "set_got_tmp" -- [(set (match_operand:SI 0 "register_operand" "=r") -+ [(set (match_operand:SI 0 "register_operand" "=t") - (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))] - "" - { -@@ -604,7 +604,7 @@ - - ;; The insn to initialize the GOT. - (define_insn "set_got" -- [(set (match_operand:SI 0 "register_operand" "=r") -+ [(set (match_operand:SI 0 "register_operand" "=t") - (unspec:SI [(const_int 0)] UNSPEC_SET_GOT)) - (clobber (reg:SI LR_REGNUM))] - "" diff --git a/toolchain/gcc/patches/9.4.0/or1k.patch b/toolchain/gcc/patches/9.4.0/or1k.patch new file mode 100644 index 000000000..8ec5ec956 --- /dev/null +++ b/toolchain/gcc/patches/9.4.0/or1k.patch @@ -0,0 +1,61 @@ +diff -Nur gcc-9.2.0.orig/gcc/config/or1k/constraints.md gcc-9.2.0/gcc/config/or1k/constraints.md +--- gcc-9.2.0.orig/gcc/config/or1k/constraints.md 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/gcc/config/or1k/constraints.md 2019-10-07 10:59:48.995389485 +0200 +@@ -32,6 +32,9 @@ + (define_register_constraint "c" "SIBCALL_REGS" + "Registers which can hold a sibling call address") + ++(define_register_constraint "t" "GOT_REGS" ++ "Registers which can be used to store the Global Offset Table (GOT) address.") ++ + ;; Immediates + (define_constraint "I" + "A signed 16-bit immediate in the range -32768 to 32767." +diff -Nur gcc-9.2.0.orig/gcc/config/or1k/or1k.h gcc-9.2.0/gcc/config/or1k/or1k.h +--- gcc-9.2.0.orig/gcc/config/or1k/or1k.h 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/gcc/config/or1k/or1k.h 2019-10-07 12:14:41.334692831 +0200 +@@ -189,6 +189,7 @@ + { + NO_REGS, + SIBCALL_REGS, ++ GOT_REGS, + GENERAL_REGS, + FLAG_REGS, + ALL_REGS, +@@ -200,6 +201,7 @@ + #define REG_CLASS_NAMES { \ + "NO_REGS", \ + "SIBCALL_REGS", \ ++ "GOT_REGS", \ + "GENERAL_REGS", \ + "FLAG_REGS", \ + "ALL_REGS" } +@@ -212,6 +214,7 @@ + #define REG_CLASS_CONTENTS \ + { { 0x00000000, 0x00000000 }, \ + { SIBCALL_REGS_MASK, 0 }, \ ++ { 0xfffffdff, 0x00000000 }, \ + { 0xffffffff, 0x00000003 }, \ + { 0x00000000, 0x00000004 }, \ + { 0xffffffff, 0x00000007 } \ +diff -Nur gcc-9.2.0.orig/gcc/config/or1k/or1k.md gcc-9.2.0/gcc/config/or1k/or1k.md +--- gcc-9.2.0.orig/gcc/config/or1k/or1k.md 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/gcc/config/or1k/or1k.md 2019-10-07 10:59:48.999389485 +0200 +@@ -595,7 +595,7 @@ + ;; set_got pattern below. This works because the set_got_tmp insn is the + ;; first insn in the stream and that it isn't moved during RA. + (define_insn "set_got_tmp" +- [(set (match_operand:SI 0 "register_operand" "=r") ++ [(set (match_operand:SI 0 "register_operand" "=t") + (unspec_volatile:SI [(const_int 0)] UNSPECV_SET_GOT))] + "" + { +@@ -604,7 +604,7 @@ + + ;; The insn to initialize the GOT. + (define_insn "set_got" +- [(set (match_operand:SI 0 "register_operand" "=r") ++ [(set (match_operand:SI 0 "register_operand" "=t") + (unspec:SI [(const_int 0)] UNSPEC_SET_GOT)) + (clobber (reg:SI LR_REGNUM))] + "" -- cgit v1.2.3