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-rw-r--r--target/linux/patches/6.0.11/board-rockpi4-0003-arm64-dts-pcie.patch35
-rw-r--r--target/linux/patches/6.0.11/rockchip-115200.patch12
-rw-r--r--target/linux/patches/6.0.11/rockchip-audio.patch12
-rw-r--r--target/linux/patches/6.0.11/rockchip-pcie-timeout.patch16
4 files changed, 75 insertions, 0 deletions
diff --git a/target/linux/patches/6.0.11/board-rockpi4-0003-arm64-dts-pcie.patch b/target/linux/patches/6.0.11/board-rockpi4-0003-arm64-dts-pcie.patch
new file mode 100644
index 000000000..1777e7a86
--- /dev/null
+++ b/target/linux/patches/6.0.11/board-rockpi4-0003-arm64-dts-pcie.patch
@@ -0,0 +1,35 @@
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+index 1ae1ebd4e..2f84397d5 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+@@ -62,6 +62,8 @@
+ regulator-name = "vcc3v3_pcie";
+ regulator-always-on;
+ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+@@ -434,6 +459,21 @@
+ gpio1830-supply = <&vcc_3v0>;
+ };
+
++&pcie0 {
++ ep-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
++ num-lanes = <4>;
++ max-link-speed = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_clkreqnb_cpm>;
++ vpcie12v-supply = <&vcc12v_dcin>;
++ vpcie3v3-supply = <&vcc3v3_pcie>;
++ status = "okay";
++};
++
++&pcie_phy {
++ status = "okay";
++};
++
+ &pmu_io_domains {
+ status = "okay";
+
diff --git a/target/linux/patches/6.0.11/rockchip-115200.patch b/target/linux/patches/6.0.11/rockchip-115200.patch
new file mode 100644
index 000000000..ad8a2d7a7
--- /dev/null
+++ b/target/linux/patches/6.0.11/rockchip-115200.patch
@@ -0,0 +1,12 @@
+diff -Nur linux-5.15.81.orig/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi linux-5.15.81/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+--- linux-5.15.81.orig/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi 2022-12-02 17:41:12.000000000 +0100
++++ linux-5.15.81/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi 2022-12-22 09:51:57.370394227 +0100
+@@ -17,7 +17,7 @@
+ };
+
+ chosen {
+- stdout-path = "serial2:1500000n8";
++ stdout-path = "serial2:115200n8";
+ };
+
+ clkin_gmac: external-gmac-clock {
diff --git a/target/linux/patches/6.0.11/rockchip-audio.patch b/target/linux/patches/6.0.11/rockchip-audio.patch
new file mode 100644
index 000000000..9520d2ad2
--- /dev/null
+++ b/target/linux/patches/6.0.11/rockchip-audio.patch
@@ -0,0 +1,12 @@
+diff -Nur linux-6.0.11.orig/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi linux-6.0.11/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+--- linux-6.0.11.orig/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi 2022-12-02 17:43:18.000000000 +0100
++++ linux-6.0.11/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi 2022-12-24 19:48:31.620199852 +0100
+@@ -452,6 +452,8 @@
+ clocks = <&cru SCLK_I2S_8CH_OUT>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <RK_PA0 IRQ_TYPE_LEVEL_HIGH>;
+
+ port {
+ es8316_p0_0: endpoint {
diff --git a/target/linux/patches/6.0.11/rockchip-pcie-timeout.patch b/target/linux/patches/6.0.11/rockchip-pcie-timeout.patch
new file mode 100644
index 000000000..2ef7df2da
--- /dev/null
+++ b/target/linux/patches/6.0.11/rockchip-pcie-timeout.patch
@@ -0,0 +1,16 @@
+diff -Nur linux-6.0.11.orig/drivers/pci/controller/pcie-rockchip-host.c linux-6.0.11/drivers/pci/controller/pcie-rockchip-host.c
+--- linux-6.0.11.orig/drivers/pci/controller/pcie-rockchip-host.c 2022-12-02 17:43:18.000000000 +0100
++++ linux-6.0.11/drivers/pci/controller/pcie-rockchip-host.c 2022-12-24 11:12:25.753213273 +0100
+@@ -327,10 +327,10 @@
+
+ gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
+
+- /* 500ms timeout value should be enough for Gen1/2 training */
++ /* 1000ms timeout value should be enough for Gen1/2 training */
+ err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
+ status, PCIE_LINK_UP(status), 20,
+- 500 * USEC_PER_MSEC);
++ 1000 * USEC_PER_MSEC);
+ if (err) {
+ dev_err(dev, "PCIe link training gen1 timeout!\n");
+ goto err_power_off_phy;