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-rw-r--r--package/etrax-tools/Makefile30
-rwxr-xr-xpackage/etrax-tools/src/boot_linux511
-rw-r--r--package/etrax-tools/src/e100boot/LICENSE26
-rw-r--r--package/etrax-tools/src/e100boot/Makefile70
-rw-r--r--package/etrax-tools/src/e100boot/cbl/Makefile25
-rwxr-xr-xpackage/etrax-tools/src/e100boot/cbl/free_size42
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/Makefile6
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/common.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/common_init.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/crt0.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/e100boot_version.c1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/e100boot_version.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/flash.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/hwregs.d2
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net/net_init.d2
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/Makefile6
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/common.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/common_init.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/crt0.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/e100boot_version.c1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/e100boot_version.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/flash.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/hwregs.d2
-rw-r--r--package/etrax-tools/src/e100boot/cbl/net_noleds/net_init.d2
-rw-r--r--package/etrax-tools/src/e100boot/cbl/rules.cbl55
-rwxr-xr-xpackage/etrax-tools/src/e100boot/cbl/ser.imabin0 -> 6546 bytes
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/Makefile6
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/common.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/common_init.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/crt0.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/e100boot_version.c1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/e100boot_version.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/flash.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/hwregs.d2
-rwxr-xr-xpackage/etrax-tools/src/e100boot/cbl/ser/ser.outbin0 -> 9257 bytes
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser/ser_init.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/Makefile6
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/common.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/common_init.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/crt0.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/e100boot_version.c1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/e100boot_version.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/flash.d1
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/hwregs.d2
-rw-r--r--package/etrax-tools/src/e100boot/cbl/ser_noleds/ser_init.d3
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/common.c486
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/common_init.c209
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/compiler.h10
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/crt0.S17
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/debug.h0
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/e100boot.h332
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/flash.c1125
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/hwregs.c1713
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/hwregs.h44822
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/hwregs_def.h5435
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/hwregs_int.h25386
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/ldscript38
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/net_init.c218
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/project.h10
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/ser_init.c117
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/sv_addr.agh7323
-rw-r--r--package/etrax-tools/src/e100boot/cbl/src/sv_addr_ag.h137
-rw-r--r--package/etrax-tools/src/e100boot/doc/Makefile17
-rw-r--r--package/etrax-tools/src/e100boot/doc/e100boot.1401
-rw-r--r--package/etrax-tools/src/e100boot/doc/e100boot.html395
-rw-r--r--package/etrax-tools/src/e100boot/doc/e100boot.pod314
-rw-r--r--package/etrax-tools/src/e100boot/doc/pod2htmd.tmp2
-rw-r--r--package/etrax-tools/src/e100boot/doc/pod2htmi.tmp2
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/CHANGES267
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/FILES50
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/INSTALL328
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/Makefile173
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/Makefile.conf2
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/Makefile.in173
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/README49
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sparcbin0 -> 5212 bytes
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sun3bin0 -> 4267 bytes
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sun4c.4.0.3cbin0 -> 5368 bytes
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/VERSION1
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/aclocal.m4706
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/bpf/net/bpf.h264
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/bpf/net/bpf_filter.c532
l---------package/etrax-tools/src/e100boot/libpcap-0.4/bpf_filter.c1
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/bpf_image.c288
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/config.cache35
-rwxr-xr-xpackage/etrax-tools/src/e100boot/libpcap-0.4/config.guess693
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/config.log61
-rwxr-xr-xpackage/etrax-tools/src/e100boot/libpcap-0.4/config.status179
-rwxr-xr-xpackage/etrax-tools/src/e100boot/libpcap-0.4/config.sub927
-rwxr-xr-xpackage/etrax-tools/src/e100boot/libpcap-0.4/configure2137
-rwxr-xr-xpackage/etrax-tools/src/e100boot/libpcap-0.4/configure.in189
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/etherent.c159
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/ethertype.h76
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/gencode.c1944
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/gencode.h179
l---------package/etrax-tools/src/e100boot/libpcap-0.4/gnuc.h1
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/grammar.c2380
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/grammar.y281
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/inet.c219
-rwxr-xr-xpackage/etrax-tools/src/e100boot/libpcap-0.4/install-sh250
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/lbl/gnuc.h43
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-solaris2.h54
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-sunos4.h215
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-ultrix4.h39
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/linux-include/netinet/if_ether.h88
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/linux-include/netinet/ip_var.h178
-rwxr-xr-xpackage/etrax-tools/src/e100boot/libpcap-0.4/mkdep109
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/nametoaddr.c372
l---------package/etrax-tools/src/e100boot/libpcap-0.4/net1
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/optimize.c2004
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-bpf.c263
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-dlpi.c848
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-enet.c227
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-int.h117
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-linux.c352
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-namedb.h76
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-nit.c244
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-nit.h19
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-null.c73
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-pf.c351
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-pf.h19
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-snit.c300
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap-snoop.c216
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap.3340
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap.c206
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/pcap.h137
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/ppp.h50
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/rmlinks3
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/savefile.c352
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/scanner.c2242
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/scanner.l203
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/tokdefs.h160
-rw-r--r--package/etrax-tools/src/e100boot/libpcap-0.4/version.c1
-rw-r--r--package/etrax-tools/src/e100boot/sbl/Makefile77
-rw-r--r--package/etrax-tools/src/e100boot/sbl/Makefile.in76
-rw-r--r--package/etrax-tools/src/e100boot/sbl/boot_images.c35
-rw-r--r--package/etrax-tools/src/e100boot/sbl/boot_images.h20
-rwxr-xr-xpackage/etrax-tools/src/e100boot/sbl/cconv158
-rw-r--r--package/etrax-tools/src/e100boot/sbl/common.c1677
-rw-r--r--package/etrax-tools/src/e100boot/sbl/common.h57
-rw-r--r--package/etrax-tools/src/e100boot/sbl/conf.h139
-rw-r--r--package/etrax-tools/src/e100boot/sbl/conf.h.in138
-rw-r--r--package/etrax-tools/src/e100boot/sbl/config.cache48
-rw-r--r--package/etrax-tools/src/e100boot/sbl/config.log90
-rwxr-xr-xpackage/etrax-tools/src/e100boot/sbl/config.status330
-rwxr-xr-xpackage/etrax-tools/src/e100boot/sbl/configure1405
-rw-r--r--package/etrax-tools/src/e100boot/sbl/configure.in19
-rwxr-xr-xpackage/etrax-tools/src/e100boot/sbl/create_regs.pl14
-rw-r--r--package/etrax-tools/src/e100boot/sbl/net_ima.c891
-rw-r--r--package/etrax-tools/src/e100boot/sbl/net_noleds_ima.c873
-rw-r--r--package/etrax-tools/src/e100boot/sbl/network.c706
-rw-r--r--package/etrax-tools/src/e100boot/sbl/network.h42
-rw-r--r--package/etrax-tools/src/e100boot/sbl/reg_des.h141
-rw-r--r--package/etrax-tools/src/e100boot/sbl/ser_ima.c825
-rw-r--r--package/etrax-tools/src/e100boot/sbl/ser_noleds_ima.c807
-rw-r--r--package/etrax-tools/src/e100boot/sbl/serial.c637
-rw-r--r--package/etrax-tools/src/e100boot/sbl/serial.h26
-rw-r--r--package/etrax-tools/src/e100boot/sbl/win32/Makefile8
-rwxr-xr-xpackage/etrax-tools/src/e100boot/sbl/win32/boot_images.c35
-rw-r--r--package/etrax-tools/src/e100boot/sbl/win32/common.c1651
-rwxr-xr-xpackage/etrax-tools/src/e100boot/sbl/win32/network.c681
-rw-r--r--package/etrax-tools/src/e100boot/sendserial/Makefile3
-rw-r--r--package/etrax-tools/src/e100boot/sendserial/sendserial.c769
-rw-r--r--package/etrax-tools/src/mkfimage.c72
164 files changed, 124246 insertions, 0 deletions
diff --git a/package/etrax-tools/Makefile b/package/etrax-tools/Makefile
new file mode 100644
index 000000000..9e4b51227
--- /dev/null
+++ b/package/etrax-tools/Makefile
@@ -0,0 +1,30 @@
+# This file is part of the OpenADK project. OpenADK is copyrighted
+# material, please see the LICENCE file in the top-level directory.
+
+include $(ADK_TOPDIR)/rules.mk
+
+PKG_NAME:= etrax-tools
+PKG_VERSION:= 1.0
+PKG_RELEASE:= 1
+PKG_DESCR:= flash tools for cris etrax boards
+PKG_SECTION:= base/tools
+
+NO_DISTFILES:= 1
+
+PKG_CFLINE_ETRAX_TOOLS:=depends on ADK_HOST_ONLY
+
+include $(ADK_TOPDIR)/mk/host.mk
+include $(ADK_TOPDIR)/mk/package.mk
+
+$(eval $(call HOST_template,ETRAX_TOOLS,etrax-tools,$(PKG_VERSION)-${PKG_RELEASE}))
+
+HOST_STYLE:= manual
+
+host-build:
+ (cd ${WRKBUILD}/e100boot && env ${HOST_MAKE_ENV} ${MAKE} -f ${MAKE_FILE} \
+ ${HOST_MAKE_FLAGS} ${HOST_ALL_TARGET}) $(MAKE_TRACE)
+
+cmake-hostinstall:
+
+include ${ADK_TOPDIR}/mk/host-bottom.mk
+include $(ADK_TOPDIR)/mk/pkg-bottom.mk
diff --git a/package/etrax-tools/src/boot_linux b/package/etrax-tools/src/boot_linux
new file mode 100755
index 000000000..f7da261e2
--- /dev/null
+++ b/package/etrax-tools/src/boot_linux
@@ -0,0 +1,511 @@
+#!/usr/bin/perl -w
+
+#*****************************************************************************
+#!
+#! FILE NAME : boot_linux
+#!
+#! PARAMETERS : -b <bootimage> the name of the boot image to use
+#! -d <device> the interface to use, e.g., eth1
+#! (defaults is eth0)
+#! -f save it in flash memory at address 0x10000
+#! -F save it in flash memory at address 0
+#! -h show some help
+#! -i <image> name of the image to use (default is fimage)
+#! -o <offset> the offset in the flash where the flashing
+#! starts
+#! -O <offset> the offset in the image file where the
+#! flashing starts from
+#! -p print the resulting etrax100boot command
+#! instead of executing it
+#! -s <size> how much to flash (default is the size of
+#! the flash minus the offset specified using
+#! -o or -f)
+#! -S <size> the size of the flash
+#!
+#! All sizes and offsets above can be specified as decimal
+#! numbers, or as hexadecimal numbers by prefixing them with 0x.
+#! It is also possible to use the suffixes k and M to specify
+#! kilo (1024) or mega (1048576).
+#!
+#! DESCRIPTION: Extract the start of the image and any registers that should
+#! be set from the kimage or fimage file, and then boot it.
+#!
+#! FUNCTIONS : convert_size
+#! extract_hw_settings
+#! get_dword
+#! calculate_sdram_init
+#! sdram_command
+#! print_help
+#!
+#!----------------------------------------------------------------------------
+#! HISTORY
+#!
+#! $Log: boot_linux,v $
+#! Revision 1.16 2004/11/01 16:32:27 starvik
+#! Corrected help text to avoid confusion
+#!
+#! Revision 1.15 2003/01/29 11:48:57 pkj
+#! Calculate a flash size large enough for the given image if the
+#! -S option is not specified.
+#!
+#! Revision 1.14 2002/11/18 14:40:09 pkj
+#! Make use of the --loop option to etrax100boot when initialising
+#! SDRAM memories. This requires a lot fewer options to be passed
+#! to the boot loader.
+#!
+#! Revision 1.13 2002/08/15 16:29:02 pkj
+#! * The -S option now accepts the size in bytes (just like the -s option).
+#! For backwards compatibility it still assumes sizes of 16 and less to
+#! be specified in MB.
+#! * The suffixes k and M can now be used with all sizes and offsets to
+#! specify them in kilo or mega.
+#!
+#! Revision 1.12 2002/08/15 15:27:34 pkj
+#! Use $opts{'x'} instead of $opt_x.
+#!
+#! Revision 1.11 2002/07/04 17:06:39 pkj
+#! * No longer specifies a bootfile by default (not needed any longer).
+#! * Implemented option -b to specify a bootfile.
+#! * Removed references to option -l (it was never implemented).
+#!
+#! Revision 1.10 2002/06/04 11:50:23 starvik
+#! Check if mrs_data is specified in kernelconfig (necessary for MCM)
+#!
+#! Revision 1.9 2002/01/29 10:38:26 pkj
+#! Change illegal to invalid.
+#!
+#! Revision 1.8 2001/09/13 12:32:10 pkj
+#! * Added option -S to specify the size of the flash (in MB), as -s
+#! is used to specify how much to flash nowadays.
+#! * Made the default size of the flash depend on the size of the image
+#! file. If it is bigger than 0x200100 then the flash is assumed to
+#! be 4 MB, otherwise it is assumed to be 2 MB.
+#! * Added verification of various options.
+#!
+#! Revision 1.7 2001/09/13 10:25:11 pkj
+#! Minor clean-up.
+#!
+#! Revision 1.6 2001/06/29 10:05:16 pkj
+#! Corrected check for SDRAM.
+#!
+#! Revision 1.5 2001/06/29 09:11:55 pkj
+#! Synchronised boot_elinux and boot_linux.
+#!
+#!----------------------------------------------------------------------------
+#! (C) Copyright 2001, Axis Communications AB, LUND, SWEDEN
+#!****************************************************************************
+
+#****************** INCLUDE FILES SECTION ************************************
+
+use strict;
+
+use Getopt::Std;
+use File::Basename;
+
+#****************** VARIABLE DECLARATION SECTION *****************************
+
+use vars qw($my_name %opts);
+use vars qw($text_start $cmd);
+use vars qw($image_name $image_size);
+use vars qw($offset $source_offset $flash_size $flashing_size);
+use vars qw($sdram_timing_address $sdram_config_address);
+use vars qw($sdram_precharge $sdram_nop $sdram_refresh $sdram_mrs);
+
+#****************** CONSTANT SECTION *****************************************
+
+# Register addresses
+$sdram_timing_address = "b0000008";
+$sdram_config_address = "b000000c";
+
+# SDRAM commands
+$sdram_precharge = 3;
+$sdram_nop = 0;
+$sdram_refresh = 2;
+$sdram_mrs = 1;
+
+#****************** MAIN PROGRAM SECTION *************************************
+
+# The name of this program.
+$my_name = basename($0);
+
+# Get options
+getopts('b:d:fFhi:o:O:ps:S:', \%opts);
+
+&print_help if ($opts{'h'});
+
+# Name and existance of the image
+$image_name = ($opts{'i'} ? $opts{'i'} : 'fimage');
+die "Could not find the image $image_name!\n" unless (-s $image_name);
+
+if ($opts{'f'} || $opts{'F'})
+{
+ $image_size = -s $image_name;
+
+ $offset = ($opts{'f'} ? 0x10000 : 0);
+
+ $offset = &convert_size($opts{'o'}) if (defined($opts{'o'}));
+
+ die("$my_name: Invalid destination offset\n") if ($offset !~ /^\d+$/);
+
+ my $base_name = basename($image_name);
+ if ($base_name eq 'timage' || $base_name eq 'flash1.img')
+ {
+ $source_offset = 0;
+ }
+ else
+ {
+ $source_offset = $offset;
+ }
+
+ $source_offset = &convert_size($opts{'O'}) if (defined($opts{'O'}));
+
+ die("$my_name: Invalid source offset\n") if ($source_offset !~ /^\d+$/);
+ die("$my_name: Source offset > image size\n") if ($source_offset > $image_size);
+
+ if (defined($opts{'S'}))
+ {
+ # Backwards compatibility to allow specifying the flash size in MB
+ # without using an M suffix
+ $opts{'S'} .= 'M' if ($opts{'S'} =~ /^\d+$/ && $opts{'S'} <= 16);
+
+ $flash_size = &convert_size($opts{'S'});
+ }
+ else
+ {
+ # Calculate a flash size large enough for the image without the checksum
+ # and HWID.
+ $flash_size = ($image_size - $source_offset + $offset) & 0xFFFF0000;
+ }
+
+ die("$my_name: Invalid flash size\n") if ($flash_size !~ /^\d+$/);
+ die("$my_name: Destination offset > flash size\n") if ($offset > $flash_size);
+ if (defined($opts{'s'}))
+ {
+ $flashing_size = &convert_size($opts{'s'});
+ }
+ else
+ {
+ $flashing_size = $flash_size - $offset;
+ }
+
+ die("$my_name: Invalid size to flash\n") if ($flashing_size !~ /^\d+$/);
+
+ if ($flashing_size > $flash_size - $offset)
+ {
+ $flashing_size = $flash_size - $offset;
+ printf("Warning: Flashing size limited to 0x%lx due to the offset (0x%lx) and flash size (0x%lx).\n", $flashing_size, $offset, $flash_size);
+ }
+
+ if ($flashing_size > $image_size - $source_offset)
+ {
+ $flashing_size = $image_size - $source_offset;
+ printf("Warning: Flashing size limited to 0x%lx due to the offset (0x%lx) and image size (0x%lx).\n", $flashing_size, $source_offset, $image_size);
+ }
+}
+
+# Create the command line to boot the image
+if (system('./etrax100boot --help > /dev/null') == 0)
+{
+ $cmd = './etrax100boot';
+}
+elsif (system('svinto_boot --help > /dev/null') == 0)
+{
+ $cmd = 'svinto_boot';
+}
+else
+{
+ die("Cannot find e100boot program in your PATH!\n");
+}
+
+$cmd .= " --device $opts{'d'}" if ($opts{'d'});
+
+$cmd .= &extract_hw_settings;
+
+$cmd .= " --bootfile $opts{'b'}" if ($opts{'b'});
+$cmd .= " --file $image_name $text_start";
+
+if ($opts{'f'} || $opts{'F'})
+{
+ $cmd .= sprintf(" --flash %lx %lx %lx --jump 0",
+ hex($text_start) + $source_offset, $offset, $flashing_size);
+}
+else
+{
+ $cmd .= " --jump $text_start";
+}
+
+if ($opts{'p'})
+{
+ print "Command:\n$cmd\n";
+}
+else
+{
+ system($cmd);
+}
+
+exit 0;
+
+#****************** FUNCTION DEFINITION SECTION ******************************
+
+#*****************************************************************************
+##
+## FUNCTION NAME: convert_size
+##
+##****************************************************************************
+
+sub convert_size
+{
+ my($arg) = @_;
+ my $size;
+
+ if ($arg =~ /^0x([\da-fA-F]+)([kM])?$/)
+ {
+ $size = hex($1);
+ }
+ elsif ($arg =~ /^(\d+)([kM])?$/)
+ {
+ $size = $1;
+ }
+ else
+ {
+ return -1;
+ }
+
+ if (!defined($2))
+ {
+ return $size;
+ }
+ elsif ($2 eq 'k')
+ {
+ return $size * 1024;
+ }
+ elsif ($2 eq 'M')
+ {
+ return $size * 1048576;
+ }
+}
+
+#*****************************************************************************
+##
+## FUNCTION NAME: extract_hw_settings
+##
+##****************************************************************************
+
+sub extract_hw_settings
+{
+ my $data;
+ my $dbg_port;
+ my $sdram_enabled;
+ my $return_value = "";
+ my $sdram_config;
+
+ # The hw information table has the following format
+ #
+ # "HW_PARAM_MAGIC"
+ # text_start (dword)
+ # serial debg port (dword)
+ # sdram enabled (dword)
+ # register address (dword)
+ # register value (dword)
+ # ...
+ # 0
+
+ open(FILE, "$image_name") || die("Could not open '$image_name'");
+
+ while (<FILE>)
+ {
+ if (m/HW_PARAM_MAGIC/g)
+ {
+ # Seek to first byte after magic
+ seek(FILE, -length($_) + pos($_), 1);
+ last;
+ }
+ }
+
+ $text_start = &get_dword;
+ $dbg_port = &get_dword;
+ $sdram_enabled = int(&get_dword);
+
+ while (1)
+ {
+ my $register = &get_dword;
+ my $value = &get_dword;
+
+ last if ($register eq "00000000");
+
+ if ($sdram_enabled)
+ {
+ if ($register eq $sdram_config_address)
+ {
+ $sdram_config = $value;
+ }
+ elsif ($register eq $sdram_timing_address)
+ {
+ $return_value .= &calculate_sdram_init($value, $sdram_config);
+ next;
+ }
+ }
+
+ $return_value .= " --setreg $register $value";
+ }
+
+ close(FILE);
+
+ return $return_value;
+}
+
+#*****************************************************************************
+##
+## FUNCTION NAME: get_dword
+##
+##****************************************************************************
+
+sub get_dword
+{
+ my $data;
+
+ read(FILE, $data, 4);
+ return unpack("H8", pack("V", unpack("N", $data)));
+}
+
+#*****************************************************************************
+##
+## FUNCTION NAME: calculate_sdram_init
+##
+##****************************************************************************
+
+sub calculate_sdram_init
+{
+ # Refer to ETRAX 100LX Designers Reference for a description of SDRAM
+ # initialization
+ my $sdram_init_val = hex($_[0]);
+ my $sdram_config_val = hex($_[1]);
+ my $bus_width = $sdram_config_val & 0x00800000;
+ my $speed;
+ my $cas_latency;
+ my $mrs_data;
+ my $temp;
+ my $return_value;
+ my $value;
+
+ $mrs_data = ($sdram_init_val & 0x00ff0000) >> 16;
+ $sdram_init_val &= 0x8000ffff; # Make sure mrs data is 0
+ $sdram_init_val |= 0x80000000; # Make sure sdram is enabled
+ $speed = $sdram_init_val & 0x1000;
+ $cas_latency = $sdram_init_val & 0x3;
+ if ($speed) # 100 MHz
+ {
+ $cas_latency += 2;
+ }
+ else # 50 MHz
+ {
+ $cas_latency += 1;
+ }
+
+ # Calculate value of mrs_data
+ # CAS latency = 2 && bus_width = 32 => 0x40
+ # CAS latency = 3 && bus_width = 32 => 0x60
+ # CAS latency = 2 && bus_width = 16 => 0x20
+ # CAS latency = 3 && bus_width = 16 => 0x30
+ if ($mrs_data == 0)
+ {
+ if ($bus_width == 0) # 16 bits
+ {
+ $mrs_data = $cas_latency == 2 ? 0x20 : 0x30;
+ }
+ else # 32 bits
+ {
+ $mrs_data = $cas_latency == 2 ? 0x40 : 0x60;
+ }
+ }
+
+ $temp = $sdram_init_val | 0x0000c000; # Disable refresh
+ $return_value .= &sdram_command($temp);
+ $return_value .= " --pause 20000";
+
+ $return_value .= &sdram_command($temp, $sdram_precharge);
+ $return_value .= &sdram_command($temp, $sdram_nop);
+
+ $return_value .= " --setreg +0 7";
+ $return_value .= " --label label1";
+ $return_value .= &sdram_command($temp, $sdram_refresh);
+ $return_value .= &sdram_command($temp, $sdram_nop);
+ $return_value .= " --loop +0 label1";
+
+ $return_value .= &sdram_command($temp, $sdram_mrs, $mrs_data);
+ $return_value .= &sdram_command($temp, $sdram_nop);
+
+ $return_value .= &sdram_command($sdram_init_val);
+
+ return $return_value;
+}
+
+#*****************************************************************************
+##
+## FUNCTION NAME: sdram_command
+##
+##****************************************************************************
+
+sub sdram_command
+{
+ my($temp, $value, $mrs_data) = @_;
+
+ $value ||= 0;
+ if ($value == $sdram_mrs)
+ {
+ $value = sprintf("%lx", $temp | ($value << 9) | ($mrs_data << 16));
+ }
+ else
+ {
+ $value = sprintf("%lx", $temp | ($value << 9));
+ }
+
+ return " --setreg $sdram_timing_address $value";
+}
+
+#*****************************************************************************
+##
+## FUNCTION NAME: print_help
+##
+##****************************************************************************
+
+sub print_help
+{
+ print "\nAXIS $my_name, ", '$Revision: 1.16 $ $Date: 2004/11/01 16:32:27 $ ', "\n";
+ die <<EOT;
+Copyright (C) 2001-2002 Axis Communications AB
+
+DESCRIPTION:
+ This program is used to boot (and flash) a linux image to a box.
+ It tries to extract the required ETRAX 100 settings from the image file.
+
+SYNTAX:
+ $my_name [options]
+
+OPTIONS:
+ -b <bootfile> : The boot image to use.
+ -d <device> : The network interface to use, default is eth0.
+ -f : Save the image in the flash memory starting at
+ address 0x10000.
+ -F : Save the image in the flash memory starting at
+ address 0.
+ -h : Print this help text.
+ -i <image> : The path and name of the image to use, default
+ is fimage.
+ -o <offset> : The offset in the flash where the flashing starts.
+ -O <offset> : The offset in the image file where the flashing
+ starts from.
+ -p : Print the resulting etrax100boot command instead
+ of executing it.
+ -s <size> : How much to flash (default is the size of the
+ flash minus the offset specified using -o or -f).
+ -S <size> : The size of the flash.
+
+ All sizes and offsets above can be specified as decimal numbers, or as
+ hexadecimal numbers by prefixing them with 0x. It is also possible to use
+ the suffixes k and M to specify kilo (1024) or mega (1048576).
+
+EOT
+}
+
+#****************** END OF FILE boot_linux ***********************************
diff --git a/package/etrax-tools/src/e100boot/LICENSE b/package/etrax-tools/src/e100boot/LICENSE
new file mode 100644
index 000000000..afbcf2ec6
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/LICENSE
@@ -0,0 +1,26 @@
+Copyright (c) 2004, 2005 Axis Communications AB. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+1. Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+2. Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+3. Neither the name of Axis Communications AB nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY AXIS COMMUNCATIONS AB ``AS IS'' AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGE.
diff --git a/package/etrax-tools/src/e100boot/Makefile b/package/etrax-tools/src/e100boot/Makefile
new file mode 100644
index 000000000..828b40221
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/Makefile
@@ -0,0 +1,70 @@
+#
+# Top Makefile for e100boot
+# $Id: Makefile,v 1.20 2003/06/04 12:22:23 pkj Exp $
+#
+
+# Change these paths if necessary. Can also be specified on cmdline as
+# 'make INSTALL_PATH=/foo/bar/'.
+
+INSTALL_NAME = e100boot
+INSTALL_PATH = /usr/local
+INSTALL_PATH_BIN = $(INSTALL_PATH)/bin
+INSTALL_PATH_DOC = $(INSTALL_PATH)/man/man1
+
+DIRS = libpcap-0.4 sbl doc
+
+-include $(AXIS_TOP_DIR)/tools/build/Rules.axis
+ifdef prefix
+INSTALL_PATH = $(prefix)
+endif
+
+INSTALL ?= install
+
+all: conf $(DIRS)
+ @for d in $(DIRS); do \
+ echo -e "\n### Making $$d"; \
+ $(MAKE) -C $$d || exit; \
+ done
+
+conf: $(DIRS)
+ @for d in $(DIRS); do \
+ if [ -x $$d/configure ] && [ ! -e $$d/Makefile ]; then \
+ echo -e "\n### Configuring $$d"; \
+ cd $$d; ./configure || exit; cd ..; \
+ fi; \
+ done
+
+tar: clean
+ @echo -e "\n### Making tarball."
+ tar -C ../ -zcf e100boot.tgz --exclude e100boot.tgz --exclude RCS --exclude CVS e100boot
+
+
+install: all
+ $(INSTALL) -d $(INSTALL_PATH_BIN) $(INSTALL_PATH_DOC)
+ $(INSTALL) sbl/e100boot.stripped $(INSTALL_PATH_BIN)/$(INSTALL_NAME)
+ $(INSTALL) -m 0644 doc/e100boot.1 $(INSTALL_PATH_DOC)/$(INSTALL_NAME).1
+
+install.setuid:
+ @echo -e "\n### Make install.setuid"; \
+ if ! [ -e $(INSTALL_PATH_BIN)/$(INSTALL_NAME) ]; then \
+ echo -e "\n### Binary $(INSTALL_PATH_BIN)/$(INSTALL_NAME) does not exist! Make install first."; \
+ elif [ `id -u` = 0 ]; then \
+ chown root.root $(INSTALL_PATH_BIN)/$(INSTALL_NAME); \
+ chmod +s $(INSTALL_PATH_BIN)/$(INSTALL_NAME); \
+ else \
+ echo "### You must do this as root!"; \
+ fi
+
+clean:
+ @for d in $(DIRS); do \
+ if [ -e $$d/Makefile ]; then \
+ echo -e "\n### Cleaning $$d"; \
+ $(MAKE) -C $$d clean || exit; \
+ fi; \
+ done
+
+configsubs: conf configsubs-dirs
+
+configsubs-dirs:
+ $(MAKE) -C libpcap-0.4 configsubs
+ $(MAKE) -C sbl configsubs
diff --git a/package/etrax-tools/src/e100boot/cbl/Makefile b/package/etrax-tools/src/e100boot/cbl/Makefile
new file mode 100644
index 000000000..af7ed075d
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/Makefile
@@ -0,0 +1,25 @@
+#
+# Makefile to generate .ima files for e100boot
+#
+# Hacked by ronny, rehacked by ronny
+#
+# $Id: Makefile,v 1.26 2003/03/13 14:18:31 cii Exp $
+#
+
+DIRS := net net_noleds ser ser_noleds
+
+all: $(DIRS)
+ @for d in $(DIRS); do \
+ echo -e "\n### Making $$d"; \
+ make -C $$d || exit; \
+ done
+ @echo "***************************************************************"
+ @./free_size
+ @echo "***************************************************************"
+
+clean:
+ rm -f *.ima
+ @for d in $(DIRS); do \
+ echo -e "\n### Cleaning $$d"; \
+ make -C $$d clean || exit; \
+ done;
diff --git a/package/etrax-tools/src/e100boot/cbl/free_size b/package/etrax-tools/src/e100boot/cbl/free_size
new file mode 100755
index 000000000..73e1365e4
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/free_size
@@ -0,0 +1,42 @@
+#!/bin/sh
+#
+# Calculates the size left in ETRAX cache when bootloader is loaded.
+#
+
+BOOT_FILE=`dirname $0`/net/net.out
+HEADER_FILE=`dirname $0`/src/e100boot.h
+
+for FILE in $BOOT_FILE $HEADER_FILE; do
+ if [ ! -f $FILE ]; then
+ echo "Could not find the file \"$FILE\"!"
+ exit 1
+ fi
+done
+
+# The cache size is given in hex
+CACHE_SIZE=2000
+
+BSS_SIZE=`nm-cris $BOOT_FILE | grep Ebss | cut -d ' ' -f 1 | tr a-f A-F`
+
+TEXT_SIZE=`nm-cris $BOOT_FILE | grep Stext | cut -d ' ' -f 1 | tr a-f A-F`
+
+IO_BUF_END=`grep IO_BUF_END $HEADER_FILE | awk '{ print $3 }' | \
+ cut -d x -f 2 | tr a-f A-F`
+
+IO_BUF_START=`grep IO_BUF_START $HEADER_FILE | awk '{ print $3 }' | \
+ cut -d x -f 2 | tr a-f A-F`
+
+FREE_SIZE=`echo "ibase=16 ; \
+ $CACHE_SIZE - \
+ ($BSS_SIZE - $TEXT_SIZE + $IO_BUF_END - $IO_BUF_START)" | \
+ bc`
+
+echo "Free cache size when cbl is loaded will be:"
+echo -e "\t$FREE_SIZE bytes - size of stack"
+
+if [ $FREE_SIZE -lt 0 ]; then
+ echo "Bootloader is too large! You will have to do some optimizing..."
+ exit 1
+fi
+
+exit 0
diff --git a/package/etrax-tools/src/e100boot/cbl/net/Makefile b/package/etrax-tools/src/e100boot/cbl/net/Makefile
new file mode 100644
index 000000000..a77cc5d6c
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/Makefile
@@ -0,0 +1,6 @@
+#
+# $Id: Makefile,v 1.1 2002/07/01 14:36:40 pkj Exp $
+#
+
+IMAGE := net.ima
+include ../rules.cbl
diff --git a/package/etrax-tools/src/e100boot/cbl/net/common.d b/package/etrax-tools/src/e100boot/cbl/net/common.d
new file mode 100644
index 000000000..efe422d77
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/common.d
@@ -0,0 +1,3 @@
+common.o: ../src/common.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net/common_init.d b/package/etrax-tools/src/e100boot/cbl/net/common_init.d
new file mode 100644
index 000000000..3591272ad
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/common_init.d
@@ -0,0 +1,3 @@
+common_init.o: ../src/common_init.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net/crt0.d b/package/etrax-tools/src/e100boot/cbl/net/crt0.d
new file mode 100644
index 000000000..e33f99ad1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/crt0.d
@@ -0,0 +1 @@
+crt0.o: ../src/crt0.S
diff --git a/package/etrax-tools/src/e100boot/cbl/net/e100boot_version.c b/package/etrax-tools/src/e100boot/cbl/net/e100boot_version.c
new file mode 100644
index 000000000..7600f6d19
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/e100boot_version.c
@@ -0,0 +1 @@
+char e100boot_version[] = "This bootloader was built by root on Wed May 16 21:31:41 CEST 2007.\r\n";
diff --git a/package/etrax-tools/src/e100boot/cbl/net/e100boot_version.d b/package/etrax-tools/src/e100boot/cbl/net/e100boot_version.d
new file mode 100644
index 000000000..fd4569336
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/e100boot_version.d
@@ -0,0 +1 @@
+e100boot_version.o: e100boot_version.c
diff --git a/package/etrax-tools/src/e100boot/cbl/net/flash.d b/package/etrax-tools/src/e100boot/cbl/net/flash.d
new file mode 100644
index 000000000..f11cf6824
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/flash.d
@@ -0,0 +1 @@
+flash.o: ../src/flash.c ../src/e100boot.h ../src/compiler.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net/hwregs.d b/package/etrax-tools/src/e100boot/cbl/net/hwregs.d
new file mode 100644
index 000000000..7158582d0
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/hwregs.d
@@ -0,0 +1,2 @@
+hwregs.o: ../src/hwregs.c ../src/compiler.h ../src/hwregs.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net/net_init.d b/package/etrax-tools/src/e100boot/cbl/net/net_init.d
new file mode 100644
index 000000000..c2b32bf28
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net/net_init.d
@@ -0,0 +1,2 @@
+net_init.o: ../src/net_init.c ../src/sv_addr_ag.h ../src/sv_addr.agh \
+ ../src/e100boot.h ../src/compiler.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/Makefile b/package/etrax-tools/src/e100boot/cbl/net_noleds/Makefile
new file mode 100644
index 000000000..9479cbab8
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/Makefile
@@ -0,0 +1,6 @@
+#
+# $Id: Makefile,v 1.1 2002/07/01 14:36:51 pkj Exp $
+#
+
+IMAGE := net_noleds.ima
+include ../rules.cbl
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/common.d b/package/etrax-tools/src/e100boot/cbl/net_noleds/common.d
new file mode 100644
index 000000000..efe422d77
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/common.d
@@ -0,0 +1,3 @@
+common.o: ../src/common.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/common_init.d b/package/etrax-tools/src/e100boot/cbl/net_noleds/common_init.d
new file mode 100644
index 000000000..3591272ad
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/common_init.d
@@ -0,0 +1,3 @@
+common_init.o: ../src/common_init.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/crt0.d b/package/etrax-tools/src/e100boot/cbl/net_noleds/crt0.d
new file mode 100644
index 000000000..e33f99ad1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/crt0.d
@@ -0,0 +1 @@
+crt0.o: ../src/crt0.S
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/e100boot_version.c b/package/etrax-tools/src/e100boot/cbl/net_noleds/e100boot_version.c
new file mode 100644
index 000000000..b503ab3b0
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/e100boot_version.c
@@ -0,0 +1 @@
+char e100boot_version[] = "This bootloader was built by root on Wed May 16 21:31:43 CEST 2007.\r\n";
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/e100boot_version.d b/package/etrax-tools/src/e100boot/cbl/net_noleds/e100boot_version.d
new file mode 100644
index 000000000..fd4569336
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/e100boot_version.d
@@ -0,0 +1 @@
+e100boot_version.o: e100boot_version.c
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/flash.d b/package/etrax-tools/src/e100boot/cbl/net_noleds/flash.d
new file mode 100644
index 000000000..f11cf6824
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/flash.d
@@ -0,0 +1 @@
+flash.o: ../src/flash.c ../src/e100boot.h ../src/compiler.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/hwregs.d b/package/etrax-tools/src/e100boot/cbl/net_noleds/hwregs.d
new file mode 100644
index 000000000..7158582d0
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/hwregs.d
@@ -0,0 +1,2 @@
+hwregs.o: ../src/hwregs.c ../src/compiler.h ../src/hwregs.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h
diff --git a/package/etrax-tools/src/e100boot/cbl/net_noleds/net_init.d b/package/etrax-tools/src/e100boot/cbl/net_noleds/net_init.d
new file mode 100644
index 000000000..c2b32bf28
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/net_noleds/net_init.d
@@ -0,0 +1,2 @@
+net_init.o: ../src/net_init.c ../src/sv_addr_ag.h ../src/sv_addr.agh \
+ ../src/e100boot.h ../src/compiler.h
diff --git a/package/etrax-tools/src/e100boot/cbl/rules.cbl b/package/etrax-tools/src/e100boot/cbl/rules.cbl
new file mode 100644
index 000000000..545909055
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/rules.cbl
@@ -0,0 +1,55 @@
+#
+# $Id: rules.cbl,v 1.4 2005/04/20 11:18:54 starvik Exp $
+#
+
+VPATH := .:../src
+
+ifeq ($(findstring _noleds,$(IMAGE)),_noleds)
+USE_LEDS := 0
+else
+USE_LEDS := 1
+endif
+
+MAKEFLAGS := r
+INCS := -I.
+DEFS := -DUSE_LEDS=$(USE_LEDS)
+CFLAGS := -Os -Wall -Wmissing-prototypes -W -Wa,-N -nostdinc $(INCS) $(DEFS) -MMD
+ASFLAGS := $(CFLAGS)
+LNFLAGS := -Wl,--section-start,.startup=0x380000f0 -nostdlib -Os -Wl,-T../src/ldscript
+CC := cris-axis-elf-gcc
+
+OUT := $(patsubst %.ima,%.out,$(IMAGE))
+
+OBJS = crt0.o common_init.o
+ifeq ($(findstring net,$(IMAGE)),net)
+OBJS += net_init.o
+else
+OBJS += ser_init.o
+endif
+OBJS += common.o flash.o hwregs.o e100boot_version.o
+
+all: ../$(IMAGE)
+
+$(OUT): $(OBJS) ldscript
+ $(CC) -o $@ $(LNFLAGS) $(OBJS)
+
+../%.ima: %.out
+ bin-cris -o $@ $<
+ @find $@ -printf '# Size of image $@ is %s bytes.\n\n'
+
+$(OBJS): ../rules.cbl Makefile
+
+# We don't want this to be a dummy and be recreated every time we build,
+# only after a make clean
+e100boot_version.c:
+ @echo "Generating version file....."
+ @echo 'char e100boot_version[] = "This bootloader was built by '`id -u -n`' on '`date`'.\r\n";' > $@
+
+dummy:
+
+clean:
+ rm -rf *.o *.d *.out *.ima deps e100boot_version.c
+
+ifneq ($(MAKECMDGOALS),clean)
+-include *.d
+endif
diff --git a/package/etrax-tools/src/e100boot/cbl/ser.ima b/package/etrax-tools/src/e100boot/cbl/ser.ima
new file mode 100755
index 000000000..388ccc381
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser.ima
Binary files differ
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/Makefile b/package/etrax-tools/src/e100boot/cbl/ser/Makefile
new file mode 100644
index 000000000..0905a5a5b
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/Makefile
@@ -0,0 +1,6 @@
+#
+# $Id: Makefile,v 1.1 2002/07/01 14:37:01 pkj Exp $
+#
+
+IMAGE := ser.ima
+include ../rules.cbl
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/common.d b/package/etrax-tools/src/e100boot/cbl/ser/common.d
new file mode 100644
index 000000000..efe422d77
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/common.d
@@ -0,0 +1,3 @@
+common.o: ../src/common.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/common_init.d b/package/etrax-tools/src/e100boot/cbl/ser/common_init.d
new file mode 100644
index 000000000..3591272ad
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/common_init.d
@@ -0,0 +1,3 @@
+common_init.o: ../src/common_init.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/crt0.d b/package/etrax-tools/src/e100boot/cbl/ser/crt0.d
new file mode 100644
index 000000000..e33f99ad1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/crt0.d
@@ -0,0 +1 @@
+crt0.o: ../src/crt0.S
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/e100boot_version.c b/package/etrax-tools/src/e100boot/cbl/ser/e100boot_version.c
new file mode 100644
index 000000000..6ffd0de21
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/e100boot_version.c
@@ -0,0 +1 @@
+char e100boot_version[] = "This bootloader was built by root on Wed May 16 21:31:44 CEST 2007.\r\n";
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/e100boot_version.d b/package/etrax-tools/src/e100boot/cbl/ser/e100boot_version.d
new file mode 100644
index 000000000..fd4569336
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/e100boot_version.d
@@ -0,0 +1 @@
+e100boot_version.o: e100boot_version.c
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/flash.d b/package/etrax-tools/src/e100boot/cbl/ser/flash.d
new file mode 100644
index 000000000..f11cf6824
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/flash.d
@@ -0,0 +1 @@
+flash.o: ../src/flash.c ../src/e100boot.h ../src/compiler.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/hwregs.d b/package/etrax-tools/src/e100boot/cbl/ser/hwregs.d
new file mode 100644
index 000000000..7158582d0
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/hwregs.d
@@ -0,0 +1,2 @@
+hwregs.o: ../src/hwregs.c ../src/compiler.h ../src/hwregs.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/ser.out b/package/etrax-tools/src/e100boot/cbl/ser/ser.out
new file mode 100755
index 000000000..5c6156b7e
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/ser.out
Binary files differ
diff --git a/package/etrax-tools/src/e100boot/cbl/ser/ser_init.d b/package/etrax-tools/src/e100boot/cbl/ser/ser_init.d
new file mode 100644
index 000000000..89a6d90de
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser/ser_init.d
@@ -0,0 +1,3 @@
+ser_init.o: ../src/ser_init.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/sv_addr_ag.h ../src/sv_addr.agh ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/Makefile b/package/etrax-tools/src/e100boot/cbl/ser_noleds/Makefile
new file mode 100644
index 000000000..9bb999c38
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/Makefile
@@ -0,0 +1,6 @@
+#
+# $Id: Makefile,v 1.1 2002/07/01 14:37:10 pkj Exp $
+#
+
+IMAGE := ser_noleds.ima
+include ../rules.cbl
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/common.d b/package/etrax-tools/src/e100boot/cbl/ser_noleds/common.d
new file mode 100644
index 000000000..efe422d77
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/common.d
@@ -0,0 +1,3 @@
+common.o: ../src/common.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/common_init.d b/package/etrax-tools/src/e100boot/cbl/ser_noleds/common_init.d
new file mode 100644
index 000000000..3591272ad
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/common_init.d
@@ -0,0 +1,3 @@
+common_init.o: ../src/common_init.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/crt0.d b/package/etrax-tools/src/e100boot/cbl/ser_noleds/crt0.d
new file mode 100644
index 000000000..e33f99ad1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/crt0.d
@@ -0,0 +1 @@
+crt0.o: ../src/crt0.S
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/e100boot_version.c b/package/etrax-tools/src/e100boot/cbl/ser_noleds/e100boot_version.c
new file mode 100644
index 000000000..c4753698d
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/e100boot_version.c
@@ -0,0 +1 @@
+char e100boot_version[] = "This bootloader was built by root on Wed May 16 21:31:46 CEST 2007.\r\n";
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/e100boot_version.d b/package/etrax-tools/src/e100boot/cbl/ser_noleds/e100boot_version.d
new file mode 100644
index 000000000..fd4569336
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/e100boot_version.d
@@ -0,0 +1 @@
+e100boot_version.o: e100boot_version.c
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/flash.d b/package/etrax-tools/src/e100boot/cbl/ser_noleds/flash.d
new file mode 100644
index 000000000..f11cf6824
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/flash.d
@@ -0,0 +1 @@
+flash.o: ../src/flash.c ../src/e100boot.h ../src/compiler.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/hwregs.d b/package/etrax-tools/src/e100boot/cbl/ser_noleds/hwregs.d
new file mode 100644
index 000000000..7158582d0
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/hwregs.d
@@ -0,0 +1,2 @@
+hwregs.o: ../src/hwregs.c ../src/compiler.h ../src/hwregs.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h
diff --git a/package/etrax-tools/src/e100boot/cbl/ser_noleds/ser_init.d b/package/etrax-tools/src/e100boot/cbl/ser_noleds/ser_init.d
new file mode 100644
index 000000000..89a6d90de
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/ser_noleds/ser_init.d
@@ -0,0 +1,3 @@
+ser_init.o: ../src/ser_init.c ../src/hwregs.h ../src/compiler.h \
+ ../src/debug.h ../src/project.h ../src/hwregs_def.h ../src/hwregs_int.h \
+ ../src/sv_addr_ag.h ../src/sv_addr.agh ../src/e100boot.h
diff --git a/package/etrax-tools/src/e100boot/cbl/src/common.c b/package/etrax-tools/src/e100boot/cbl/src/common.c
new file mode 100644
index 000000000..e4ebdc40d
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/common.c
@@ -0,0 +1,486 @@
+#include "hwregs.h"
+#include "e100boot.h"
+
+static void toggle_led(void);
+
+static void read_load_info(void);
+static void decode_load_info(void);
+
+static void read_file(byte* addr, udword size);
+
+#if USE_PRINT_DESCR
+static void print_descr(dma_descr_T *d);
+#endif
+
+static int memory_test(udword addr, udword size, udword *failed_address);
+static void memory_dump(udword *from, udword *to);
+
+extern byte _Stext[];
+extern byte _Edata[];
+
+#ifdef USE_BAUDRATE_CHANGING
+byte change_baudrate;
+udword new_baudrate;
+#endif
+
+void
+level2_boot(void)
+{
+#if USE_LEDS
+ REG_SET(R_PORT_PA_DATA, data_out, 0xaa);
+#endif
+
+#if 0
+ io_buf_next = (byte*)IO_BUF_START;
+ io_buf_cur = (byte*)IO_BUF_START;
+#endif
+
+#if 1
+ send_string("\r\n\r\nDevice ID = ");
+ send_hex(ntohl(tx_header.id), NL);
+ send_string(e100boot_version);
+#endif
+
+#if 1
+ {
+ udword sum = 0;
+ byte *b;
+
+ for (b = (byte*)_Stext; b != (byte*)_Edata; b++) {
+ sum += *b;
+ }
+ send_string("Checksum of bootloader is ");
+ send_hex(sum, NL);
+ }
+#endif
+
+ read_load_info();
+
+ __asm__ volatile ("jump _start");
+}
+
+void
+toggle_led(void)
+{
+#if USE_LEDS
+ REG_SET(R_PORT_PA_DATA, data_out, 0x55);
+
+ while (1) {
+ REG_SET(R_PORT_PA_DATA, data_out, ~REG_GET(R_PORT_PA_READ, data_in));
+ {
+ volatile udword i;
+
+ for (i = 0; i != 2000000; i++)
+ ;
+ }
+ }
+#else
+ while (1) {
+ }
+#endif
+}
+
+void
+read_load_info(void)
+{
+#ifdef USE_BAUDRATE_CHANGING
+ change_baudrate = 0;
+#endif
+
+ send_string("Waiting for load info.\r\n");
+
+ send_ack();
+
+ read_file((byte*)IO_BUF_START, IO_BUF_END - IO_BUF_START - CRC_LEN);
+ send_string("Got load info.\r\n");
+ decode_load_info();
+
+#ifdef USE_BAUDRATE_CHANGING
+ if (change_baudrate) {
+ REG_WR(R_SERIAL0_BAUD, new_baudrate);
+ {
+ udword i = 0;
+
+ while (i++ < 1000000)
+ ;
+ }
+ send_ack();
+ }
+#endif
+
+ toggle_led();
+}
+
+void
+decode_load_info(void)
+{
+ udword *type_p = (udword*)IO_BUF_START;
+ udword failed_address;
+ udword i;
+ command_T *cmd;
+
+ while (type_p != (udword*)(IO_BUF_END - CRC_LEN)) { /* !!! */
+// send_hex(type_p, NL);
+ *type_p = ntohl(*type_p);
+// send_hex(*type_p, NL);
+ type_p++;
+ }
+
+// memory_dump(IO_BUF_START, IO_BUF_END);
+
+ cmd = (command_T*)IO_BUF_START;
+ while (cmd->type) {
+ switch (cmd->type) {
+ case PACKET_INFO:
+ send_string("PACKET_INFO\r\n");
+ send_hex(cmd->args.packet_info.addr, NL);
+ send_hex(cmd->args.packet_info.size, NL);
+
+ seq--;
+ send_ack();
+ seq++;
+
+ read_file((byte*)cmd->args.packet_info.addr, cmd->args.packet_info.size);
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.packet_info;
+ break;
+
+ case SET_REGISTER:
+ send_string("SET_REGISTER\r\n");
+ send_hex(cmd->args.set_register.addr, NL);
+ send_hex(cmd->args.set_register.val, NL);
+
+ *(udword*)cmd->args.set_register.addr = cmd->args.set_register.val;
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.set_register;
+ break;
+
+ case GET_REGISTER:
+ send_string("GET_REGISTER\r\n");
+ send_hex(cmd->args.get_register.addr, NL);
+ send_hex(*(udword*)cmd->args.get_register.addr, NL);
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.get_register;
+ break;
+
+ case PAUSE_LOOP:
+ send_string("PAUSE_LOOP\r\n");
+ send_hex(cmd->args.pause_loop.pause, NL);
+
+ for (i = cmd->args.pause_loop.pause; i; i--)
+ ;
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.pause_loop;
+ break;
+
+ case MEM_VERIFY:
+ send_string("MEM_VERIFY\r\n");
+ send_hex(cmd->args.mem_verify.addr, NL);
+ send_hex(cmd->args.mem_verify.val, NL);
+
+ if (*(udword*)cmd->args.mem_verify.addr != cmd->args.mem_verify.val) {
+ send_string("verify failed\r\n");
+ goto decode_failed;
+ }
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.mem_verify;
+ break;
+
+ case MEM_TEST:
+ send_string("MEM_TEST\r\n");
+ send_hex(cmd->args.mem_test.from, NL);
+ send_hex(cmd->args.mem_test.to, NL);
+
+ if (!memory_test(cmd->args.mem_test.from,
+ cmd->args.mem_test.to,
+ &failed_address)) {
+ send_string("### Memory test failed at ");
+ send_hex(failed_address, NL);
+ memory_dump((udword*)DWORD_ALIGN(failed_address - 64),
+ (udword*)DWORD_ALIGN(failed_address + 64));
+ goto decode_failed;
+ }
+ send_string("Passed memory test.\r\n");
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.mem_test;
+ break;
+
+ case MEM_DUMP:
+ send_string("MEM_DUMP\r\n");
+ send_hex(cmd->args.mem_dump.from_addr, NL);
+ send_hex(cmd->args.mem_dump.to_addr, NL);
+
+ memory_dump((udword*)cmd->args.mem_dump.from_addr,
+ (udword*)cmd->args.mem_dump.to_addr);
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.mem_dump;
+ break;
+
+ case MEM_CLEAR:
+ send_string("MEM_CLEAR\r\n");
+ send_hex(cmd->args.mem_clear.from_addr, NL);
+ send_hex(cmd->args.mem_clear.to_addr, NL);
+
+ for (i = cmd->args.mem_clear.from_addr;
+ i <= cmd->args.mem_clear.to_addr;
+ i++) {
+ *(byte*)i = 0x00;
+ }
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.mem_clear;
+ break;
+
+ case FLASH:
+ send_string("FLASH\r\n");
+ send_hex((udword)cmd->args.flash.source, NL);
+ send_hex(cmd->args.flash.offset, NL);
+ send_hex(cmd->args.flash.size, NL);
+
+ if ((i = flash_write(cmd->args.flash.source,
+ cmd->args.flash.offset,
+ cmd->args.flash.size)) != ERR_FLASH_OK) {
+ if (i == ERR_FLASH_VERIFY) {
+ udword size =
+ (cmd->args.flash.size < 65536 ? cmd->args.flash.size : 65536);
+
+ /* Try to erase the first block(s) we tried to flash to prevent a
+ unit which failed to flash correctly from booting */
+ flash_write(NULL, cmd->args.flash.offset, size);
+ }
+
+ goto decode_failed;
+ }
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.flash;
+ break;
+
+ case JUMP:
+#if 1
+ /* for the printf function in our libc */
+ REG_WR(R_DMA_CH8_FIRST, *(udword*)&tx_header.dest[0]);
+ REG_WR(R_DMA_CH9_FIRST, *(uword*)&tx_header.dest[4]);
+// REG_WR(R_NETWORK_SA_1, &tx_header.dest[4]);
+// REG_WR(R_NETWORK_SA_2, tx_header.id);
+#endif
+ send_string("JUMP\r\n");
+ send_hex(cmd->args.jump.addr, NL);
+ send_string("END\r\n");
+
+ __asm__ volatile ("jump %0" :: "r" (cmd->args.jump.addr));
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.jump;
+ break;
+
+ case LOOP:
+ send_string("LOOP\r\n");
+ send_hex(cmd->args.bne.addr, NL);
+ send_hex(cmd->args.bne.target, NL);
+
+ if (*(udword*)cmd->args.bne.addr) {
+ (*(udword*)cmd->args.bne.addr)--;
+ (byte*)cmd = cmd->args.bne.target;
+ }
+ else {
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.bne;
+ }
+ break;
+
+#ifdef USE_BAUDRATE_CHANGING
+ case BAUDRATE:
+ send_string("BAUDRATE\r\n");
+ send_hex(cmd->args.br.baudrate, NL);
+
+ new_baudrate = cmd->args.br.baudrate;
+
+ (byte*)cmd += sizeof cmd->type + sizeof cmd->args.br;
+ break;
+#endif
+
+ default:
+ send_string("### Unknown type: ");
+ send_hex(cmd->type, NL);
+
+ goto decode_failed;
+ break;
+ }
+ }
+
+decode_failed:
+ send_string("END\r\n");
+}
+
+void
+read_file(byte* addr, udword size)
+{
+ udword nbr_read_last;
+ udword sum;
+ byte *b;
+ byte *from;
+
+/* send_string(">read_file\r\n"); */
+
+ nbr_read = 0;
+ nbr_read_last = 0;
+ target_address = (udword)addr;
+
+ if (interface == NETWORK) {
+ rx_descr2.buf = (udword)addr;
+ bytes_to_read = size;
+ rx_descr2.sw_len = size + CRC_LEN > 1500 ? 1500 : size + CRC_LEN;
+/* rx_descr2.sw_len = 1500; */
+
+ REG_SET(R_DMA_CH1_FIRST, first, (udword)&rx_descr);
+
+ /* Restart receiver so descriptor is re-read. */
+ REG_SET(R_DMA_CH1_CMD, cmd, reset);
+ while (REG_EQL(R_DMA_CH1_CMD, cmd, reset)) {
+ }
+
+ REG_SET(R_DMA_CH1_CMD, cmd, start);
+
+ while (1) {
+/* send_hex(rx_descr2.hw_len, NL); */
+ from = (byte*)rx_descr2.buf;
+ if (read_data()) {
+ if (nbr_read < size) {
+ REG_SET(R_DMA_CH1_CMD, cmd, start);
+ }
+
+#if USE_PRINT_DESCR
+ print_descr(&rx_descr);
+ print_descr(&rx_descr2);
+#endif
+
+#if 0
+ send_string("Read ");
+ send_hex(rx_descr2.hw_len - CRC_LEN, NO_NL);
+ send_string(" bytes. ");
+ send_hex((udword)from, NO_NL);
+ send_string(" - ");
+ send_hex(rx_descr2.buf-1, NO_NL);
+ send_string(" (");
+ send_hex(nbr_read, NO_NL);
+ send_string("/");
+ send_hex(size, NO_NL);
+ send_string(")\r\n");
+#endif
+
+ nbr_read_last = nbr_read;
+/* from = (byte*)rx_descr2.buf; */
+
+ if (nbr_read >= size) {
+ break;
+ }
+ }
+ }
+ }
+ else { /* interface != NETWORK */
+ while (nbr_read < size) {
+ read_data();
+ }
+ }
+
+ sum = 0;
+ for (b = addr; b != (byte*)(addr+size); b++) {
+ sum += *b;
+ }
+ send_string("Checksum of file is ");
+ send_hex(sum, NL);
+
+/* memory_dump((udword*)addr, (udword*)addr+size); */
+/* send_string("<read_file\r\n"); */
+}
+
+#if USE_PRINT_DESCR
+void
+print_descr(dma_descr_T *d)
+{
+ send_string("Descriptor at ");
+ send_hex((udword)d, NL);
+
+ send_string("ctrl : ");
+ send_hex(d->ctrl, NL);
+
+ send_string("sw_len : ");
+ send_hex(d->sw_len, NL);
+
+ send_string("next : ");
+ send_hex(d->next, NL);
+
+ send_string("buf : ");
+ send_hex(d->buf, NL);
+
+ send_string("status : ");
+ send_hex(d->status, NL);
+
+ send_string("hw_len : ");
+ send_hex(d->hw_len, NL);
+}
+#endif
+
+int
+memory_test(udword from, udword to, udword *failed_address)
+{
+ udword i;
+ udword j;
+ byte b;
+
+ /* At each dword (but bytewise) write the inverse of the adress,
+ check that it worked, then write the inverse of the last byte
+ written. Exit on fail. The memory after a successfull test will
+ be:
+
+ 0xC0000000 : 0xC0000000 0xC0000004 0xC0000008 0xC000000C
+ 0xC0000010 : 0xC0000010 0xC0000014 0xC0000018 0xC000001C
+ */
+
+ for (i = from; i < to; i += 4) {
+ for (j = 0; (j != sizeof(udword)) && (i+j < to); j++) {
+ b = ((~i) >> (j*8)) & 0xff;
+ *(volatile byte*)(i+j) = b;
+ if (*(volatile byte*)(i+j) == b) {
+ *(volatile byte*)(i+j) = ~b;
+ }
+ else {
+ *failed_address = i+j;
+ send_string("### Memory test 1 failed at ");
+ send_hex(*failed_address, NL);
+ return FALSE;
+ }
+ }
+ }
+
+ /* Run through entire region, check bytewise that the dwords contain
+ the address to the dword. Exit on fail. */
+
+ for (i = from; i < to; i += 4) {
+ for (j = 0; (j != sizeof(udword)) && (i+j < to); j++) {
+ b = (i >> (j*8)) & 0xff;
+ if (*(volatile byte*)(i+j) != b) {
+ *failed_address = i+j;
+ send_string("### Memory test 2 failed at ");
+ send_hex(*failed_address, NL);
+ return FALSE;
+ }
+ }
+ }
+
+ return TRUE;
+}
+
+void
+memory_dump(udword *from, udword *to)
+{
+ udword *i = from;
+ int j;
+
+ for (; i <= to; i += 4) {
+ send_hex((udword)i, NO_NL);
+ send_string(" :");
+ for(j = 0; j != 4 && (i+j <= to); j++) {
+ send_string(" ");
+ send_hex(*(udword*)(i+j), NO_NL);
+ }
+ send_string("\r\n");
+ }
+}
diff --git a/package/etrax-tools/src/e100boot/cbl/src/common_init.c b/package/etrax-tools/src/e100boot/cbl/src/common_init.c
new file mode 100644
index 000000000..8104a4df3
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/common_init.c
@@ -0,0 +1,209 @@
+/*****************************************************************************
+*!
+*! FILE NAME : common_init.c
+*!
+*! DESCRIPTION: This piece of code is loaded at bootstrap and is put in the
+*! cache at 0x380000F0. Depending of how R_BUS_STATUS<2:1> is
+*! set different kinds of bootstrap is performed.
+*!
+*! 00 - Normal boot. No bootstrap is performed and this code
+*! is never loaded.
+*! 01 - Serial boot. 784 bytes is loaded and execution starts
+*! at 0x380000F0.
+*! 11 - Parallel boot. 784 bytes is loaded and execution starts
+*! at 0x380000F0.
+*! 10 - Network boot. 1484 bytes is loaded and execution start
+*! at 0x380000F4.
+*!
+*! ---------------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! 980326 Ronny Ranerup Initial version
+*! Sep 20 1999 Jonas Dellenvall Added port3 debug support
+*! 20020206 ronny Yeah, and I removed it again...
+*!
+*! ---------------------------------------------------------------------------
+*! (C) Copyright 1998-2002, Axis Communications AB, LUND, SWEDEN
+*!***************************************************************************/
+
+/*
+
+ Misc notes:
+
+ It is very important to keep this file short. This and the boot
+ interface specific parts must fit into the first boot packet.
+
+*/
+
+/****************** INCLUDE FILES SECTION ***********************************/
+
+#include "hwregs.h"
+#include "e100boot.h"
+
+/****************** CONSTANT AND MACRO SECTION ******************************/
+
+/****************** TYPE DEFINITION SECTION *********************************/
+
+/****************** LOCAL FUNCTION DECLARATION SECTION **********************/
+
+static int timeout(void);
+
+/****************** GLOBAL VARIABLE DECLARATION SECTION *********************/
+
+udword nbr_read; /* How many bytes has been read from current file */
+byte interface; /* Which I/O interface is the current one */
+byte set_dest; /* Have we set the destination address in tx_header */
+udword last_timeout;
+
+struct packet_header_T tx_header;
+dma_descr_T tx_descr; /* For packet header */
+dma_descr_T tx_descr2; /* packet data */
+
+struct packet_header_T rx_header;
+dma_descr_T rx_descr; /* For packet header */
+dma_descr_T rx_descr2; /* packet data */
+
+udword seq; /* Sequence number of next wanted packet */
+byte serial_up;
+
+/****************** LOCAL VARIABLE DECLARATION SECTION **********************/
+
+/****************** FUNCTION DEFINITION SECTION *****************************/
+
+void
+crt1(void)
+{
+ /* Do this only once so we don't reset the timers and destroy the 32
+ bit timer-register used as random number generator */
+
+ REG_SET__R_TIMER_CTRL(
+ timerdiv1, 0,
+ timerdiv0, 0,
+ presc_timer1, normal,
+ i1, clr,
+ tm1, run,
+ clksel1, cascade0,
+ presc_ext, prescale,
+ i0, clr,
+ tm0, run,
+ clksel0, c9600Hz);
+
+ REG_SET__R_TIMER_CTRL(
+ timerdiv1, 0,
+ timerdiv0, 0,
+ presc_timer1, normal,
+ i1, nop,
+ tm1, run,
+ clksel1, cascade0,
+ presc_ext, prescale,
+ i0, nop,
+ tm0, run,
+ clksel0, c9600Hz);
+
+ start();
+}
+
+void
+start(void)
+{
+#if USE_LEDS
+ REG_SET__R_PORT_PA_DIR(
+ dir7, output,
+ dir6, output,
+ dir5, output,
+ dir4, output,
+ dir3, output,
+ dir2, output,
+ dir1, output,
+ dir0, input); /* not for prodtest */
+
+ REG_SET__R_PORT_PA_DATA(data_out, 0);
+
+ REG_SET__R_PORT_PB_DIR(
+ dir7, output,
+ dir6, output,
+ dir5, output,
+ dir4, output,
+ dir3, output,
+ dir2, output,
+ dir1, output,
+ dir0, output);
+
+ REG_SET__R_PORT_PB_DATA(data_out, 0xff);
+#endif
+
+ /* We must initialize all (global) variables here, since the .data
+ and .bss area are used before they are loaded. */
+
+ //serial_up = FALSE;
+ nbr_read = 0;
+
+ /* Get a random value to use as id. */
+ tx_header.id = htonl(REG_RD(R_TIMER_DATA));
+
+ /* timer01 is used as timer. */
+ last_timeout = REG_GET(R_TIMER01_DATA, count);
+
+ interface = REG_GET(R_BUS_STATUS, boot) - 1; /* 0,1,2 */
+ rx_descr2.status = 0;
+
+ /* Initialize the boot interface */
+ init_interface();
+ send_ack(); /* Ack the first bootpacket, i.e. this code. seq 0. */
+
+ while (1) {
+ if (read_data()) {
+ if (nbr_read >= (udword)bytes_to_read) {
+ break;
+ }
+ else if (interface == NETWORK) {
+ REG_SET(R_DMA_CH1_CMD, cmd, start);
+ }
+ }
+ }
+
+#if USE_LEDS
+ REG_SET(R_PORT_PA_DATA, data_out, 0x55);
+#endif
+
+ level2_boot();
+}
+
+int
+read_data(void)
+{
+ if (handle_read()) {
+ return TRUE;
+ }
+
+ if (timeout()) {
+ send_ack();
+ }
+
+ return FALSE;
+}
+
+int
+timeout(void)
+{
+ volatile int now = REG_GET(R_TIMER01_DATA, count);
+ int elapsed;
+ int wait_time = 9600;
+
+ elapsed = last_timeout - now;
+
+ if (elapsed < 0) {
+ elapsed = -elapsed;
+ }
+
+ if (elapsed > wait_time) {
+ last_timeout = now;
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/****************** END OF FILE common_init.c *******************************/
diff --git a/package/etrax-tools/src/e100boot/cbl/src/compiler.h b/package/etrax-tools/src/e100boot/cbl/src/compiler.h
new file mode 100644
index 000000000..004d0d105
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/compiler.h
@@ -0,0 +1,10 @@
+#ifndef _COMPILER_H
+#define _COMPILER_H
+
+typedef int dword;
+typedef unsigned int udword;
+typedef signed short word;
+typedef unsigned short uword;
+typedef unsigned char byte;
+
+#endif
diff --git a/package/etrax-tools/src/e100boot/cbl/src/crt0.S b/package/etrax-tools/src/e100boot/cbl/src/crt0.S
new file mode 100644
index 000000000..466d19c7e
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/crt0.S
@@ -0,0 +1,17 @@
+ .global crt0 ; Needed because of a bug in binutils
+ .global _target_address
+ .global _bytes_to_read
+
+ .section .startup, "ax"
+
+ nop
+ nop
+
+
+crt0:
+ move.d 0x38001f00, sp
+ jump _crt1
+
+_bytes_to_read: .dword 0x12345678
+_target_address: .dword 0x87654321
+
diff --git a/package/etrax-tools/src/e100boot/cbl/src/debug.h b/package/etrax-tools/src/e100boot/cbl/src/debug.h
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/debug.h
diff --git a/package/etrax-tools/src/e100boot/cbl/src/e100boot.h b/package/etrax-tools/src/e100boot/cbl/src/e100boot.h
new file mode 100644
index 000000000..d9fea143a
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/e100boot.h
@@ -0,0 +1,332 @@
+/* $Id: e100boot.h,v 1.9 2003/12/16 09:04:07 magnusmn Exp $ */
+
+#include "compiler.h"
+
+#define DMA_DESCR__out_priority__BITNR 5
+#define DMA_DESCR__out_priority__WIDTH 1
+#define DMA_DESCR__out_priority__normal 0
+#define DMA_DESCR__out_priority__high 1
+
+#define DMA_DESCR__ecp_cmd__BITNR 4
+#define DMA_DESCR__ecp_cmd__WIDTH 1
+#define DMA_DESCR__ecp_cmd__normal 0
+#define DMA_DESCR__ecp_cmd__high 1
+
+#define DMA_DESCR__tx_err__BITNR 4
+#define DMA_DESCR__tx_err__WIDTH 1
+#define DMA_DESCR__tx_err__enable 1
+#define DMA_DESCR__tx_err__disable 0
+
+#define DMA_DESCR__intr__BITNR 3
+#define DMA_DESCR__intr__WIDTH 1
+#define DMA_DESCR__intr__enable 1
+#define DMA_DESCR__intr__disable 0
+
+#define DMA_DESCR__wait__BITNR 2
+#define DMA_DESCR__wait__WIDTH 1
+#define DMA_DESCR__wait__enable 1
+#define DMA_DESCR__wait__disable 0
+
+#define DMA_DESCR__eop__BITNR 1
+#define DMA_DESCR__eop__WIDTH 1
+#define DMA_DESCR__eop__enable 1
+#define DMA_DESCR__eop__disable 0
+
+#define DMA_DESCR__eol__BITNR 0
+#define DMA_DESCR__eol__WIDTH 1
+#define DMA_DESCR__eol__enable 1
+#define DMA_DESCR__eol__disable 0
+
+#define DMA_DESCR__sw_len__BITNR 0
+#define DMA_DESCR__sw_len__WIDTH 16
+
+#define DMA_DESCR__next__BITNR 0
+#define DMA_DESCR__next__WIDTH 32
+
+#define DMA_DESCR__buf__BITNR 0
+#define DMA_DESCR__buf__WIDTH 32
+
+#define DMA_DESCR__fifo_len__BITNR 8
+#define DMA_DESCR__fifo_len__WIDTH 7
+
+#define DMA_DESCR__crc_err__BITNR 7
+#define DMA_DESCR__crc_err__WIDTH 1
+#define DMA_DESCR__crc_err__enable 1
+#define DMA_DESCR__crc_err__disable 0
+
+#define DMA_DESCR__align_err__BITNR 6
+#define DMA_DESCR__align_err__WIDTH 1
+#define DMA_DESCR__align_err__enable 1
+#define DMA_DESCR__align_err__disable 0
+
+#define DMA_DESCR__in_priority__BITNR 5
+#define DMA_DESCR__in_priority__WIDTH 1
+#define DMA_DESCR__in_priority__high 1
+#define DMA_DESCR__in_priority__normal 0
+
+#define DMA_DESCR__stop__BITNR 4
+#define DMA_DESCR__stop__WIDTH 1
+
+#define DMA_DESCR__rd_eop__BITNR 1
+#define DMA_DESCR__rd_eop__WIDTH 1
+
+#define DMA_DESCR__hw_len__BITNR 0
+#define DMA_DESCR__hw_len__WIDTH 16
+
+#define SET_ETHER_ADDR(a0_0,a0_1,a0_2,a0_3,a0_4,a0_5,a1_0,a1_1,a1_2,a1_3,a1_4,a1_5) \
+ *R_NETWORK_SA_0 = a0_0 | (a0_1 << 8) | (a0_2 << 16) | (a0_3 << 24); \
+ *R_NETWORK_SA_1 = a0_4 | (a0_5 << 8) | (a1_0 << 16) | (a1_1 << 24); \
+ *R_NETWORK_SA_2 = a1_2 | (a1_3 << 8) | (a1_4 << 16) | (a1_5 << 24);
+
+#define DWORD_ALIGN(x) ((x) & 0xfffffffc)
+
+#define CRC_LEN 4
+
+#define TRUE 1
+#define FALSE 0
+
+#define NL 1
+#define NO_NL 0
+
+#define SERIAL 0
+#define NETWORK 1
+#define PARALLEL 2
+
+#define STRING 0
+#define INT 1
+#define ACK 2
+#define BOOT_PACKET 3
+#define BOOT_CMDS 4
+#define NET_INT 5
+#define NET_INT_NL 6
+
+#define JUMP 1
+#define MEM_TEST 2
+#define PACKET_INFO 3
+#define SET_REGISTER 4
+#define GET_REGISTER 5
+#define MEM_DUMP 6
+#define MEM_CLEAR 7
+#define MEM_VERIFY 8
+#define FLASH 9
+#define PAUSE_LOOP 10
+#define LOOP 11
+#define BAUDRATE 12
+
+#define ERR_FLASH_OK 0
+#define ERR_FLASH_NONE 1
+#define ERR_FLASH_TOO_SMALL 2
+#define ERR_FLASH_VERIFY 3
+#define ERR_FLASH_ERASE 4
+
+#define TIMEOUT_LIMIT ( ((6250 * 1000) / 0xffff) / 2)
+
+#define TX_CTRL_EOP \
+(IO_STATE(DMA_DESCR, intr, disable) |\
+ IO_STATE(DMA_DESCR, wait, enable) |\
+ IO_STATE(DMA_DESCR, eop, enable) |\
+ IO_STATE(DMA_DESCR, eol, enable))
+
+#define TX_CTRL \
+ (IO_STATE(DMA_DESCR, intr, disable) |\
+ IO_STATE(DMA_DESCR, wait, disable) |\
+ IO_STATE(DMA_DESCR, eop, disable) |\
+ IO_STATE(DMA_DESCR, eol, disable))
+
+#define LOAD_ADDRESS 0x38001000
+#define SIZEOF_BOOT_LEVEL_1 2048
+
+/* This is where the commands are transfered to. */
+#define IO_BUF_START 0x38001f00
+#define IO_BUF_END 0x380020f0 /* bootcode start + cache size */
+
+/* This should only be used in the cbl, but if we compile the sbl for
+ * elinux then __CRIS__ will be defined, and these are already defined
+ * in uC-libc. Check that __linux__ is not defined as well!
+ */
+
+#if defined(__CRIS__) && !defined(__linux__)
+#define NULL ((void*)0)
+
+static inline udword
+htonl(udword x)
+{
+ __asm__ ("swapwb %0" : "=r" (x) : "0" (x));
+
+ return(x);
+}
+#ifndef ntohl
+#define ntohl(x) htonl(x)
+#endif
+
+static inline uword
+htons(uword x)
+{
+ __asm__ ("swapb %0" : "=r" (x) : "0" (x));
+
+ return(x);
+}
+#ifndef ntohs
+#define ntohs(x) htons(x)
+#endif
+#endif
+
+/*#define ntohs(x) \*/
+/*((unsigned short)((((unsigned short)(x) & 0x00ffU) << 8) | \*/
+/* (((unsigned short)(x) & 0xff00U) >> 8)))*/
+/* */
+
+/*#define ntohl(x) \*/
+/*((unsigned long int)((((unsigned long int)(x) & 0x000000ffU) << 24) | \*/
+/* (((unsigned long int)(x) & 0x0000ff00U) << 8) | \*/
+/* (((unsigned long int)(x) & 0x00ff0000U) >> 8) | \*/
+/* (((unsigned long int)(x) & 0xff000000U) >> 24)))*/
+
+struct packet_header_T /* Size = 38 */
+{
+ byte dest[6];
+ byte src[6];
+ uword length;
+ udword snap1;
+ udword snap2;
+ udword tag;
+ udword seq;
+ udword type;
+ udword id;
+} __attribute__ ((packed));
+
+typedef struct dma_descr_T {
+ uword sw_len; /* 0-1 */
+ uword ctrl; /* 2-3 */
+ udword next; /* 4-7 */
+ udword buf; /* 8-11 */
+ uword hw_len; /* 12-13 */
+ uword status; /* 14-15 */
+} dma_descr_T;
+
+typedef struct packet_info_T {
+ udword addr;
+ udword size;
+} packet_info_T;
+
+typedef struct set_register_T {
+ udword addr;
+ udword val;
+} set_register_T;
+
+typedef struct get_register_T {
+ udword addr;
+} get_register_T;
+
+typedef struct pause_loop_T {
+ udword pause;
+} pause_loop_T;
+
+typedef struct mem_verify_T {
+ udword addr;
+ udword val;
+} mem_verify_T;
+
+typedef struct mem_test_T {
+ udword from;
+ udword to;
+} mem_test_T;
+
+typedef struct mem_dump_T {
+ udword from_addr;
+ udword to_addr;
+} mem_dump_T;
+
+typedef struct mem_clear_T {
+ udword from_addr;
+ udword to_addr;
+} mem_clear_T;
+
+typedef struct flash_T {
+ unsigned char *source;
+ udword offset;
+ udword size;
+} flash_T;
+
+typedef struct jump_T {
+ udword addr;
+} jump_T;
+
+typedef struct bne_T {
+ udword addr;
+ udword target;
+} bne_T;
+
+typedef struct br_T {
+ udword baudrate;
+} br_T;
+
+typedef struct command_T {
+ udword type;
+ union {
+ packet_info_T packet_info;
+ set_register_T set_register;
+ get_register_T get_register;
+ pause_loop_T pause_loop;
+ mem_verify_T mem_verify;
+ mem_test_T mem_test;
+ mem_dump_T mem_dump;
+ mem_clear_T mem_clear;
+ flash_T flash;
+ jump_T jump;
+ bne_T bne;
+ br_T br;
+ } args;
+} command_T;
+
+#define NETWORK_HEADER_LENGTH sizeof(struct packet_header_T)
+
+void crt1(void);
+void start(void);
+void level2_boot(void);
+int read_data(void);
+int handle_network_read(void);
+int flash_write(const unsigned char *source, unsigned int offset, unsigned int size);
+
+void init_interface(void);
+int handle_read(void);
+void send_ack(void);
+void send_string(char *str);
+void send_hex(udword v, byte nl);
+
+extern char e100boot_version[];
+
+extern volatile udword bytes_to_read;
+extern volatile udword target_address;
+
+extern udword nbr_read;
+extern byte interface;
+extern byte set_dest;
+extern udword last_timeout;
+extern byte *io_buf_next;
+extern byte *io_buf_cur;
+
+extern struct packet_header_T tx_header;
+extern dma_descr_T tx_descr;
+extern dma_descr_T tx_descr2;
+
+extern struct packet_header_T rx_header;
+extern dma_descr_T rx_descr;
+extern dma_descr_T rx_descr2;
+
+extern uword timeout_limit;
+extern udword seq;
+extern byte serial_up;
+
+enum { /* Available in: */
+ d_eol = (1 << 0), /* flags */
+ d_eop = (1 << 1), /* flags & status */
+ d_wait = (1 << 2), /* flags */
+ d_int = (1 << 3), /* flags */
+ d_txerr = (1 << 4), /* flags */
+ d_stop = (1 << 4), /* status */
+ d_ecp = (1 << 4), /* flags & status */
+ d_pri = (1 << 5), /* flags & status */
+ d_alignerr = (1 << 6), /* status */
+ d_crcerr = (1 << 7) /* status */
+};
diff --git a/package/etrax-tools/src/e100boot/cbl/src/flash.c b/package/etrax-tools/src/e100boot/cbl/src/flash.c
new file mode 100644
index 000000000..892e98ad7
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/flash.c
@@ -0,0 +1,1125 @@
+/* $Id: flash.c,v 1.39 2004/04/20 07:57:57 jonashg Exp $
+ *
+ * Stolen from the eLinux kernel and stripped down.
+ *
+ * HISTORY:
+ *
+ * $Log: flash.c,v $
+ * Revision 1.39 2004/04/20 07:57:57 jonashg
+ * Clear flash_status fields to make it possible to flash several images
+ * sequentially.
+ *
+ * Revision 1.38 2003/12/16 09:04:07 magnusmn
+ * Removed FLASHFILL command
+ *
+ * Revision 1.37 2003/12/16 08:49:01 magnusmn
+ * Merging change_branch--fast_flash
+ *
+ * Revision 1.36.2.6 2003/12/15 17:21:27 magnusmn
+ * Reset counter when continuing with operations the next sector.
+ *
+ * Revision 1.36.2.5 2003/12/15 11:35:57 magnusmn
+ * Bail out if we try to erase the same sector more that 10 times
+ *
+ * Revision 1.36.2.4 2003/12/12 12:07:10 magnusmn
+ * FIX for ST M29W320DT
+ * Some chip need a reset to bring them back to read mode again.
+ *
+ * Revision 1.36.2.3 2003/11/10 16:38:04 orjanf
+ * Unified Erasing/Writing messages
+ *
+ * Revision 1.36.2.2 2003/11/10 15:52:34 magnusmn
+ * More info on a sector basis
+ *
+ * Revision 1.36.2.1 2003/11/07 16:23:20 magnusmn
+ * o Only erase a flash sector if we need to, that is if the source content isn't already is in place.
+ * o Don't erase a flash sector that already contain ones.
+ * o Don't write ones to a (d)word that already contain ones.
+ * o If there are two flashes, switch flash after an erase operation is started on one of them.
+ * o Flash fill doesn't work yet.
+ * o No timeout implemented, we will continue to erase/program until we succeed.
+ * o Interleave not tested.
+ *
+ * Revision 1.36 2003/10/16 17:08:51 jonashg
+ * Bugfix: reversed CFI-tables wasn't handled correctly since regions support was
+ * merged.
+ *
+ * Revision 1.35 2003/10/14 13:43:41 pkj
+ * Fixed compiler warnings.
+ *
+ * Revision 1.34 2003/10/14 10:48:13 magnusmn
+ * No need to write ones to a (d)word where there already are ones. This will save time during flash programming.
+ *
+ * Revision 1.33 2003/10/10 11:46:25 jonashg
+ * Merged change_branch--regions_support.
+ *
+ * Revision 1.32.2.3 2003/10/10 09:38:13 jonashg
+ * Corrected calculation of current region and sector before erase.
+ *
+ * Revision 1.32.2.2 2003/10/09 16:31:26 jonashg
+ * Regions support in JEDEC probe.
+ *
+ * Revision 1.32.2.1 2003/09/19 15:28:22 jonashg
+ * Support for unusual region layouts. It only works for CFI compliant chips (yet).
+ *
+ * Revision 1.32 2002/12/13 15:55:54 jonashg
+ * Fix for ST M29W160ET. It seems to need a reset before erase (even though the
+ * probe functions did reset it).
+ *
+ * Revision 1.31 2002/07/01 14:37:25 pkj
+ * Merged with the ASIC version of e100boot. Main difference is that
+ * information about the executed commands are sent back to e100boot
+ * instead of being sent to the debug port. This means there is no
+ * longer any need to use different boot loaders for different
+ * debug ports.
+ *
+ * Revision 1.30 2002/06/26 13:28:29 pkj
+ * flash_write() can now be used to erase an area (by specifying
+ * source as NULL), and to fill an area with the first udword of
+ * source by setting do_fill to TRUE).
+ *
+ * Revision 1.29 2002/06/26 13:19:37 pkj
+ * * flash_write() now returns a status code.
+ * * timeout is now decremented correctly in flash_write_part() to
+ * actually be able to trigger the timeout message.
+ * * Fixed all compiler warnings.
+ *
+ * Revision 1.28 2002/06/20 12:58:18 pkj
+ * Changed svinto_boot.h to e100boot.h
+ *
+ * Revision 1.27 2002/06/19 14:00:29 pkj
+ * * Broke out the probing of the flash chips from flash_write()
+ * into flash_probe_chips().
+ * * flash_probe_chips() is not limited to two chips or that the
+ * first chip exists.
+ *
+ * Revision 1.26 2002/02/21 14:37:52 jonashg
+ * Optimized away my sanity. It's back now I think.
+ *
+ * Revision 1.25 2002/02/21 14:28:24 jonashg
+ * Added support for Atmel AT49?V16?T (had to optimize a bit to make room).
+ *
+ * Revision 1.24 2002/01/31 14:36:14 jonashg
+ * * Added support for Atmel AT49[BL]V16[01] (the chip used in the ETRAX MCM).
+ * * Replaced concurrent sector erase with sequential (we have found three
+ * different chips that cannot erase multiple sectors at the same time,
+ * one of the is the chip in the MCM). I haven't noticed any performance
+ * loss on chips (CFI and non-CFI) that can erase all sectors at the same
+ * time either (maybe they don't really erase them at the same time in
+ * hardware).
+ * * Added check for manufacturer id as well as device id (should have been
+ * done a long time ago).
+ *
+ * Revision 1.23 2001/11/21 15:52:44 jonashg
+ * Almost readable.
+ *
+ * Revision 1.22 2001/11/21 15:24:38 jonashg
+ * Increased readability and decreased size some 40bytes.
+ *
+ * Revision 1.21 2001/11/20 13:40:12 starvik
+ * Corrected handling for CFI capable bottom boot flashes
+ * Shorted some strings to make more space available
+ *
+ * Revision 1.20 2001/08/08 17:51:28 pkj
+ * Made it possible to flash at a start offset other than zero when
+ * there are more than one physical flash chip available. Previously
+ * it always started flashing from the start of the first flash if
+ * there were more than one, even though the start offset was set to
+ * something else...
+ *
+ * Revision 1.19 2001/06/19 14:51:17 jonashg
+ * Added support for non-CFI flash Toshiba TC58FVT800.
+ *
+ * Revision 1.18 2001/04/05 06:32:39 starvik
+ * Works with flashes with multiple banks
+ *
+ * Revision 1.17 2001/03/06 15:21:16 jonashg
+ * More output to user.
+ *
+ * Revision 1.16 2001/03/06 14:11:16 jonashg
+ * * Switch to second device correctly when flashing images that extend past the
+ * first device.
+ * * Only enter autoselect mode once saves a few bytes (not needed before reading
+ * device id, since it was done before reading manufacturer id).
+ * * A few unnecessary resets removed to save another few bytes.
+ *
+ * Revision 1.15 2001/02/28 14:52:43 jonashg
+ * * Reverted to old sector erase sequence (that was correct).
+ * * A bit of executable size optimization (a few hundred bytes).
+ * * Cleanup.
+ *
+ * Revision 1.14 2001/02/27 14:18:59 jonashg
+ * * Write full erase command sequence to all sectors that should be erased.
+ * * Write 16bit erase command to non-interleaved chips.
+ *
+ * Revision 1.13 2001/02/23 11:03:41 jonashg
+ * Added support for 2 x 16Mb flashes (32-bits buswidth).
+ * The CFI probe does not detect two parallel flash devices, but the normal
+ * probe does (it should be easy to add that in the CFI-probe, but I didn't
+ * have any hardware to try it on and the size of the executable is getting
+ * pretty close to the size of the ETRAX cache).
+ *
+ * Revision 1.12 2001/02/12 13:59:00 jonashg
+ * Bugfix: pointer arithmetics made bootsector calculation go wrong.
+ *
+ * Revision 1.11 2000/11/10 08:02:23 starvik
+ * Added CFI support
+ *
+ * Revision 1.10 2000/10/26 13:47:32 johana
+ * Added support for Fujitsu flash 16MBit (2MByte) MBM29LV160BE and MBM29LV160TE.
+ * NOT VERIFIED YET!
+ *
+ * Revision 1.9 2000/06/28 13:02:50 bjornw
+ * * Added support for SST39LF800 and SST39LF160 flashes
+ * * Fixed some indentation issues
+ *
+ * Revision 1.8 2000/06/13 11:51:11 starvik
+ * Support for two flashes. Second flash is erased and programmed if program
+ * is larger than first flash.
+ *
+ * Revision 1.7 2000/04/13 16:06:15 macce
+ * See if flash is empty before erasing it. Might save some production time.
+ *
+ * Revision 1.6 2000/01/27 17:52:07 bjornw
+ * * Added Toshiba flashes
+ * * Added proper bootblock erase for the different flashes
+ * (this caused the verify errors when trying to do ./flashitall before)
+ *
+ * Revision 1.5 2000/01/20 11:41:28 finn
+ * Improved the verify error printouts in flash_write.
+ *
+ * Revision 1.4 1999/12/21 19:32:53 bjornw
+ * Dont choke on full chip erases even though we dont implement it efficiently.
+ *
+ * Revision 1.3 1999/11/12 01:30:04 bjornw
+ * Added wait for busy to be ready. Removed some warnings.
+ *
+ * Revision 1.2 1999/10/27 07:42:42 johana
+ * Added support for ST M29W800T flash used in 5600
+ *
+ * Revision 1.1 1999/10/27 01:37:12 bjornw
+ * Wrote routines to erase and flash data into a flash ROM.
+ *
+ */
+
+#include "e100boot.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define FDEBUG(x) x
+#else
+#define FDEBUG(x)
+#endif
+
+/* Try turning of some of these if you run into space problems. */
+#define CFI_PROBE
+#define JEDEC_PROBE
+#define INTERLEAVE
+
+#define TYPE_X16 (16 / 8)
+
+#define nop() __asm__("nop")
+
+#define safe_printk send_string
+
+static char *message_bottom_boot_8 = "8Mb BB";
+static char *message_top_boot_8 = "8Mb TB";
+static char *message_bottom_boot_16 = "16Mb BB";
+static char *message_top_boot_16 = "16Mb TB";
+static char *message_top_boot_32 = "32Mb TB";
+
+enum {
+ /* Addresses */
+ ADDR_UNLOCK_1 = 0x0555,
+ ADDR_UNLOCK_2 = 0x02AA,
+ ADDR_MANUFACTURER = 0x0000,
+ ADDR_DEVICE_ID = 0x0001,
+ ADDR_CFI_QUERY = 0x0055,
+
+ /* Commands */
+ CMD_UNLOCK_DATA_1 = 0x00AA,
+ CMD_UNLOCK_DATA_2 = 0x0055,
+ CMD_MANUFACTURER_UNLOCK_DATA = 0x0090,
+ CMD_PROGRAM_UNLOCK_DATA = 0x00A0,
+ CMD_RESET_DATA = 0x00F0,
+ CMD_SECTOR_ERASE_UNLOCK_DATA_1 = 0x0080,
+ CMD_SECTOR_ERASE_UNLOCK_DATA_2 = 0x0030,
+ CMD_CFI_QUERY_DATA = 0x0098,
+
+ /* Offsets */
+ OFFSET_CFI_ID = 0x10,
+ OFFSET_CFI_SIZE = 0x27,
+ OFFSET_CFI_BLOCK_COUNT = 0x2C,
+ OFFSET_CFI_BLOCK = 0x2D,
+
+ /* Manufacturers */
+ MANUFACTURER_AMD = 0x01,
+ MANUFACTURER_ATMEL = 0x1F,
+ MANUFACTURER_FUJITSU = 0x04,
+ MANUFACTURER_SST = 0xBF,
+ MANUFACTURER_ST = 0x20,
+ MANUFACTURER_TOSHIBA = 0x98,
+
+
+ /* To save precious space we store mfr and dev id together */
+
+ /* AMD devices */
+ AM29F800BB = 0x00012258,
+ AM29F800BT = 0x000122D6,
+ AM29LV800BB = 0x0001225B,
+ AM29LV800BT = 0x000122DA,
+ AM29LV160BT = 0x000122C4,
+
+ /* Atmel devices */
+ AT49xV16x = 0x001F00C0,
+ AT49xV16xT = 0x001F00C2,
+ AT49BV32xAT = 0x001F00C9,
+
+ /* Fujitsu devices */
+ MBM29LV160TE = 0x000422C4,
+ MBM29LV160BE = 0x00042249,
+
+ /* SST devices */
+ SST39LF800 = 0x00BF2781,
+ SST39LF160 = 0x00BF2782,
+
+ /* ST devices */
+ M29W800T = 0x002000D7, /* Used in 5600, similar
+ * to AM29LV800, but no
+ * unlock bypass
+ */
+ /* Toshiba devices */
+ TC58FVT160 = 0x009800C2,
+ TC58FVB160 = 0x00980043,
+ TC58FVT800 = 0x0098004F,
+
+ /* Toggle bit mask */
+ D6_MASK = 0x40
+};
+
+struct region {
+ unsigned long offset;
+ unsigned int sector_size;
+ unsigned int numsectors;
+};
+
+#define MAXREGIONS 8
+
+struct chip {
+ volatile unsigned char *base;
+#ifdef INTERLEAVE
+ byte interleave;
+ byte buswidth;
+#endif
+ unsigned int size;
+ unsigned short numregions;
+ struct region regions[MAXREGIONS];
+};
+
+/* Allocate flash structures and initialize base. */
+static struct chip chips[2] = {
+ { (unsigned char *)0x80000000,
+#ifdef INTERLEAVE
+ 0, 0,
+#endif
+ 0, 0, { } },
+ { (unsigned char *)0x84000000,
+#ifdef INTERLEAVE
+ 0, 0,
+#endif
+ 0, 0, { } }
+};
+
+
+
+static unsigned int
+wide_read(struct chip *flash, unsigned long offset)
+{
+#ifdef INTERLEAVE
+ switch (flash->buswidth) {
+ case 2:
+#endif
+ return *((uword *)(flash->base + offset));
+
+#ifdef INTERLEAVE
+ case 4:
+ return *((udword *)(flash->base + offset));
+ }
+
+ return 0;
+#endif
+}
+
+static int
+wide_write_chunk(struct chip *flash, unsigned long offset, const void *chunk)
+{
+#ifdef INTERLEAVE
+ switch (flash->buswidth) {
+ case 2:
+#endif
+ *((uword *)(flash->base + offset)) = *((uword *)chunk);
+ return 2;
+
+#ifdef INTERLEAVE
+ case 4:
+ *((udword *)(flash->base + offset)) = *((udword *)chunk);
+ return 4;
+ }
+
+ return 0;
+#endif
+}
+
+static void
+wide_cmd(struct chip *flash, udword cmd, unsigned long offset)
+{
+#ifdef INTERLEAVE
+ if (flash->interleave == 1) {
+#endif
+ offset <<= 1;
+#ifdef INTERLEAVE
+ } else if (flash->interleave == 2) {
+ cmd |= (cmd << 16);
+ offset <<= 2;
+ } else {
+ safe_printk("Unsupported interleave!\n");
+ return;
+ }
+#endif
+
+ wide_write_chunk(flash, offset, &cmd);
+}
+
+static void
+flash_unlock(struct chip *flash)
+{
+ wide_cmd(flash, CMD_UNLOCK_DATA_1, ADDR_UNLOCK_1);
+ wide_cmd(flash, CMD_UNLOCK_DATA_2, ADDR_UNLOCK_2);
+}
+
+static int
+flash_is_busy(struct chip *flash, unsigned long offset)
+{
+#ifdef INTERLEAVE
+ if (flash->interleave == 2) {
+ udword read1, read2;
+
+ read1 = wide_read(flash, offset);
+ read2 = wide_read(flash, offset);
+ return (((read1 >> 16) & D6_MASK) !=
+ ((read2 >> 16) & D6_MASK)) ||
+ (((read1 & 0xffff) & D6_MASK) !=
+ ((read2 & 0xffff) & D6_MASK));
+ }
+#endif
+
+ return ((wide_read(flash, offset) & D6_MASK) !=
+ (wide_read(flash, offset) & D6_MASK));
+}
+
+
+
+#ifdef CFI_PROBE
+static int
+try_cfi(struct chip *flash)
+{
+ int offset_shift = 1;
+
+#ifdef INTERLEAVE
+ if (flash->interleave == 2) {
+ offset_shift = 2;
+ }
+#endif
+
+ /* Enter CFI mode */
+ wide_cmd(flash, CMD_CFI_QUERY_DATA, ADDR_CFI_QUERY);
+
+ /* Check if flash responds correctly */
+ if ((byte)wide_read(flash, (OFFSET_CFI_ID+0) << offset_shift) == 'Q' &&
+ (byte)wide_read(flash, (OFFSET_CFI_ID+1) << offset_shift) == 'R' &&
+ (byte)wide_read(flash, (OFFSET_CFI_ID+2) << offset_shift) == 'Y') {
+ int block; /* Current block */
+ int block_count; /* Number of blocks */
+ unsigned int offset = 0; /* Offset into flash */
+ int reverse = 0; /* Reverse block table */
+ int primary; /* Offset to vendor specific table */
+
+ safe_printk("Found 1 x CFI at ");
+ send_hex((udword)flash->base, NL);
+
+ flash->size =
+ 1 << wide_read(flash, OFFSET_CFI_SIZE << offset_shift);
+
+ /* CFI stores flash organization in blocks. Each block contains
+ * a number of sectors with the same size
+ */
+ block_count = wide_read(flash, OFFSET_CFI_BLOCK_COUNT <<
+ offset_shift);
+
+ /* Check if table is reversed */
+ primary = wide_read(flash, (OFFSET_CFI_ID+5) << offset_shift);
+ /* For CFI version 1.0 we don't know. Assume that id & 0x80 */
+ /* indicates top boot */
+ if ((byte)wide_read(flash, (primary+4) << offset_shift) == 0x30)
+ {
+ /* read device id */
+ wide_cmd(flash, CMD_RESET_DATA, ADDR_UNLOCK_1);
+ flash_unlock(flash);
+ wide_cmd(flash, CMD_MANUFACTURER_UNLOCK_DATA,
+ ADDR_UNLOCK_1);
+ reverse = wide_read(flash, ADDR_DEVICE_ID * TYPE_X16
+#ifdef INTERLEAVE
+ * flash->interleave
+#endif
+ ) & 0x80;
+ wide_cmd(flash, CMD_CFI_QUERY_DATA, ADDR_CFI_QUERY);
+ } else {
+ reverse = ((byte)wide_read(flash,
+ (primary+15) << offset_shift) == 3);
+ }
+
+ flash->numregions = block_count;
+ if (block_count > MAXREGIONS) {
+ safe_printk("Too many regions on chip!\n");
+ return 0;
+ }
+
+ /* Blocks are stored backwards compared to flash organization */
+ for (block = reverse ? block_count - 1 : 0;
+ reverse ? block >= 0 : block < block_count;
+ reverse ? block-- : block++) {
+ int region;
+
+ /* Size of each sector in block. Size is stored as
+ * sector_size / 256.
+ */
+ int sector_size =
+ (wide_read(flash, (OFFSET_CFI_BLOCK+block * 4+2) <<
+ offset_shift)
+ |
+ (wide_read(flash, (OFFSET_CFI_BLOCK+block * 4+3) <<
+ offset_shift) << 8)
+ ) << 8;
+
+ /* Number of sectors */
+ int sector_count =
+ (wide_read(flash, (OFFSET_CFI_BLOCK+block * 4+0) <<
+ offset_shift)
+ |
+ (wide_read(flash, (OFFSET_CFI_BLOCK+block * 4+1) <<
+ offset_shift) << 8)
+ ) + 1;
+
+ region = reverse? block_count - 1 - block : block;
+ flash->regions[region].offset = offset;
+ flash->regions[region].sector_size = sector_size;
+ flash->regions[region].numsectors = sector_count;
+
+ /* Can't use multiplication (we have no lib). */
+ {
+ int temp;
+ for (temp = 0 ; temp < sector_count ; temp++) {
+ offset += sector_size;
+ }
+ }
+
+FDEBUG(
+ if (reverse) {
+ safe_printk("NOTE! reversed table:\n");
+ }
+ safe_printk("region: ");
+ send_hex((udword)region, NL);
+ safe_printk(" offset: ");
+ send_hex((udword)flash->regions[region].offset, NL);
+ safe_printk(" sector_size: ");
+ send_hex((udword)flash->regions[region].sector_size, NL);
+ safe_printk(" numsectors: ");
+ send_hex((udword)flash->regions[region].numsectors, NL);
+)
+
+ /* Some flashes (SST) store information about alternate
+ * block sizes. Ignore those by breaking when the sum
+ * of the sector sizes == flash size.
+ */
+ if (offset == flash->size) {
+ break;
+ }
+ }
+
+ /* reset */
+ wide_cmd(flash, CMD_RESET_DATA, ADDR_UNLOCK_1);
+
+ return 1;
+ }
+
+ /* reset */
+ wide_cmd(flash, CMD_RESET_DATA, ADDR_UNLOCK_1);
+
+ return 0;
+}
+#endif
+
+
+
+static int
+flash_probe(struct chip *flash)
+{
+ char *message;
+ udword dev_id;
+ udword mfr_id;
+ udword id;
+
+ if (flash->size
+#ifdef CFI_PROBE
+ || try_cfi(flash)
+#endif
+ ) {
+ return 1;
+ }
+
+#ifdef JEDEC_PROBE
+ /* Read manufacturer ID. */
+ flash_unlock(flash);
+ wide_cmd(flash, CMD_MANUFACTURER_UNLOCK_DATA, ADDR_UNLOCK_1);
+ mfr_id = wide_read(flash, ADDR_MANUFACTURER * TYPE_X16
+#ifdef INTERLEAVE
+ * flash->interleave
+#endif
+ );
+ /* Read device ID. */
+ dev_id = wide_read(flash, ADDR_DEVICE_ID * TYPE_X16
+#ifdef INTERLEAVE
+ * flash->interleave
+#endif
+ );
+FDEBUG(
+ safe_printk("mfr_id: ");
+ send_hex(mfr_id, NL);
+ safe_printk("dev_id: ");
+ send_hex(dev_id, NL);
+)
+
+#ifdef INTERLEAVE
+ if ((flash->interleave == 2) &&
+ ((mfr_id >> 16) == (mfr_id & 0xffff)) &&
+ ((dev_id >> 16) == (dev_id & 0xffff))) {
+ mfr_id &= 0xffff;
+ dev_id &= 0xffff;
+ }
+#endif
+
+ id = (mfr_id << 16) | dev_id;
+
+ /* reset */
+ wide_cmd(flash, CMD_RESET_DATA, ADDR_UNLOCK_1);
+
+ /* Check device type and fill in correct sizes. */
+ switch (id) {
+ case AM29LV160BT:
+ case TC58FVT160:
+ // case MBM29LV160TE: /* This is same id as AM29LV160BT */
+ message = message_top_boot_16;
+
+ flash->size = 0x00200000;
+
+ flash->regions[0].offset = 0x00000000;
+ flash->regions[0].sector_size = 0x10000;
+ flash->regions[0].numsectors = 31;
+
+ flash->regions[1].offset = 0x001F0000;
+ flash->regions[1].sector_size = 0x08000;
+ flash->regions[1].numsectors = 1;
+
+ flash->regions[2].offset = 0x001F8000;
+ flash->regions[2].sector_size = 0x02000;
+ flash->regions[2].numsectors = 2;
+
+ flash->regions[3].offset = 0x001FC000;
+ flash->regions[3].sector_size = 0x04000;
+ flash->regions[3].numsectors = 1;
+ break;
+
+ // case AM29LV160BB:
+ case TC58FVB160:
+ case MBM29LV160BE:
+ message = message_bottom_boot_16;
+
+ flash->size = 0x00200000;
+
+ flash->regions[0].offset = 0x00000000;
+ flash->regions[0].sector_size = 0x04000;
+ flash->regions[0].numsectors = 1;
+
+ flash->regions[1].offset = 0x00004000;
+ flash->regions[1].sector_size = 0x02000;
+ flash->regions[1].numsectors = 2;
+
+ flash->regions[2].offset = 0x00008000;
+ flash->regions[2].sector_size = 0x08000;
+ flash->regions[2].numsectors = 1;
+
+ flash->regions[3].offset = 0x00010000;
+ flash->regions[3].sector_size = 0x10000;
+ flash->regions[3].numsectors = 31;
+ break;
+
+ case AM29LV800BB:
+ case AM29F800BB:
+ message = message_bottom_boot_8;
+
+ flash->size = 0x00100000;
+
+ flash->regions[0].offset = 0x00000000;
+ flash->regions[0].sector_size = 0x04000;
+ flash->regions[0].numsectors = 1;
+
+ flash->regions[1].offset = 0x00004000;
+ flash->regions[1].sector_size = 0x02000;
+ flash->regions[1].numsectors = 2;
+
+ flash->regions[2].offset = 0x00008000;
+ flash->regions[2].sector_size = 0x08000;
+ flash->regions[2].numsectors = 1;
+
+ flash->regions[3].offset = 0x00010000;
+ flash->regions[3].sector_size = 0x10000;
+ flash->regions[3].numsectors = 15;
+ break;
+
+ case M29W800T:
+ case AM29LV800BT:
+ case AM29F800BT:
+ case TC58FVT800:
+ message = message_top_boot_8;
+
+ flash->size = 0x00100000;
+
+ flash->regions[0].offset = 0x00000000;
+ flash->regions[0].sector_size = 0x10000;
+ flash->regions[0].numsectors = 15;
+
+ flash->regions[1].offset = 0x000F0000;
+ flash->regions[1].sector_size = 0x08000;
+ flash->regions[1].numsectors = 1;
+
+ flash->regions[2].offset = 0x000F8000;
+ flash->regions[2].sector_size = 0x02000;
+ flash->regions[2].numsectors = 2;
+
+ flash->regions[3].offset = 0x000FC000;
+ flash->regions[3].sector_size = 0x04000;
+ flash->regions[3].numsectors = 1;
+
+ break;
+
+ case AT49xV16x:
+ message = message_bottom_boot_16;
+
+ flash->size = 0x00200000;
+
+ flash->regions[0].offset = 0x00000000;
+ flash->regions[0].sector_size = 0x02000;
+ flash->regions[0].numsectors = 8;
+
+ flash->regions[1].offset = 0x00010000;
+ flash->regions[1].sector_size = 0x10000;
+ flash->regions[1].numsectors = 31;
+
+ break;
+
+ case AT49xV16xT:
+ message = message_top_boot_16;
+
+ flash->size = 0x00200000;
+
+ flash->regions[0].offset = 0x00000000;
+ flash->regions[0].sector_size = 0x10000;
+ flash->regions[0].numsectors = 31;
+
+ flash->regions[1].offset = 0x001F0000;
+ flash->regions[1].sector_size = 0x02000;
+ flash->regions[1].numsectors = 8;
+
+ break;
+
+ case AT49BV32xAT:
+ message = message_top_boot_32;
+
+ flash->size = 0x00400000;
+
+ flash->regions[0].offset = 0x00000000;
+ flash->regions[0].sector_size = 0x10000;
+ flash->regions[0].numsectors = 63;
+
+ flash->regions[1].offset = 0x001F0000;
+ flash->regions[1].sector_size = 0x02000;
+ flash->regions[1].numsectors = 8;
+
+ break;
+
+ default:
+#endif
+#ifdef INTERLEAVE
+ if (flash->interleave == 1) {
+#endif
+ safe_printk("No single x16 at ");
+#ifdef INTERLEAVE
+ } else {
+ safe_printk("No interleaved x16 at ");
+ }
+#endif
+ send_hex((udword)flash->base, NL);
+
+ return 0;
+#ifdef JEDEC_PROBE
+ }
+
+ safe_printk("Found ");
+#ifdef INTERLEAVE
+ if (flash->interleave == 1) {
+#endif
+ safe_printk("1");
+#ifdef INTERLEAVE
+ }
+ if (flash->interleave == 2) {
+ int count = 0;
+
+ flash->size <<= 1;
+ while (count < MAXREGIONS) {
+ flash->regions[count].offset <<= 1;
+ flash->regions[count].sector_size <<= 1;
+ count++;
+ }
+ safe_printk("2");
+ }
+#endif
+ safe_printk(" x ");
+ safe_printk(message);
+ safe_printk(" at ");
+ send_hex((udword)flash->base, NL);
+
+ return 1;
+#endif
+}
+
+/* Start erase of a sector but do no wait for completion */
+static void
+start_sector_erase(struct chip *flash, unsigned long offset)
+{
+ flash_unlock(flash);
+ wide_cmd(flash, CMD_SECTOR_ERASE_UNLOCK_DATA_1, ADDR_UNLOCK_1);
+ flash_unlock(flash);
+
+#ifdef INTERLEAVE
+ if (flash->interleave == 2) {
+ *(udword *)(flash->base+offset) = (CMD_SECTOR_ERASE_UNLOCK_DATA_2 << 16) |
+ CMD_SECTOR_ERASE_UNLOCK_DATA_2;
+ } else {
+#endif
+ *(uword *)(flash->base+offset) = CMD_SECTOR_ERASE_UNLOCK_DATA_2;
+#ifdef INTERLEAVE
+ }
+#endif
+}
+
+/* Return the size of the sector at the given offset */
+static int
+find_sector_size(struct chip *flash, unsigned long offset)
+{
+ unsigned int i, j;
+ int region_size;
+ /* Sanity check */
+ if (offset >= flash->size)
+ return 0;
+
+ for(i=0; i < MAXREGIONS; i++)
+ if (offset >= flash->regions[i].offset) {
+ region_size=0;
+ for (j=0; j < flash->regions[i].numsectors; j++)
+ region_size += flash->regions[i].sector_size;
+ if (offset < flash->regions[i].offset + region_size)
+ return flash->regions[i].sector_size;
+ }
+
+ /* Should not happen */
+ return 0;
+}
+
+/* Check and see if we need to erase the sector */
+/* The return values mean */
+/* 0: The source and destination are the same. */
+/* 1: The source and destination are not the same, but flash sector already contains only ones. */
+/* 2: The source and destination are not the same and the flash sector is tainted by some zeroes. */
+static char
+need_to_erase(struct chip *flash, unsigned long offset, const unsigned char *source, int size)
+{
+ int i;
+ unsigned long j;
+
+ for (i = 0; i < size; i+=2)
+ if (*(uword*)(flash->base + i + offset) != *(uword*)(source + i)) {
+ /* Check if the sector only contain zeroes */
+ for (j = offset; j < (size + offset); j+=2) {
+ if (*(uword*)(flash->base + j) != 0xffff)
+ return 2;
+ }
+ return 1;
+ }
+
+ /* The source is equal to the destination */
+ return 0;
+}
+
+static unsigned int
+flash_probe_chips(void)
+{
+ unsigned int tot_size = 0;
+ unsigned int i = 0;
+
+ for (; i < sizeof chips/sizeof *chips; i++) {
+#ifdef INTERLEAVE
+ byte interleave;
+
+ for (interleave = 1; interleave < 4; interleave *= 2) {
+ chips[i].interleave = interleave;
+ if (interleave == 1) {
+ chips[i].buswidth = sizeof(uword);
+ } else {
+ chips[i].buswidth = sizeof(udword);
+ }
+
+ if (flash_probe(&chips[i])) {
+ break;
+ }
+ }
+#else
+ flash_probe(&chips[i]);
+#endif
+
+ tot_size += chips[i].size;
+ }
+
+ return tot_size;
+}
+
+/* Program a sector (given by size) at the given offset. Do not write only ones. */
+static void
+program_sector(struct chip *flash, unsigned long offset, const unsigned char *source, int size)
+{
+ int chunk_size = 0;
+ int bytes_written = 0;
+
+
+ while (bytes_written < size) {
+ if (
+#ifdef INTERLEAVE
+ (flash->buswidth == 2) &&
+#endif
+ *(uword*)(source + bytes_written) == 0xffff) {
+ chunk_size=2;
+ }
+#ifdef INTERLEAVE
+ else if ((flash->buswidth == 4) && *(udword*)(source + bytes_written) == 0xffffffff) {
+ chunk_size=4;
+ }
+#endif
+ else {
+ flash_unlock(flash);
+ wide_cmd(flash, CMD_PROGRAM_UNLOCK_DATA, ADDR_UNLOCK_1);
+ chunk_size = wide_write_chunk(flash, offset + bytes_written, source + bytes_written);
+ while(flash_is_busy(flash, offset + bytes_written))
+ /* Nothing */
+ ;
+ }
+
+ bytes_written += chunk_size;
+ }
+}
+
+int
+flash_write(const unsigned char *source, unsigned int offset, unsigned int size)
+{
+ struct flash_status {
+ unsigned char busy; /* Indicates if the flash is busy */
+ const unsigned char *src; /* From where to get the source info */
+ unsigned long offset; /* Start operations in flash at this offset */
+ unsigned int size; /* Size to erase/program (if needed) */
+ unsigned int bytes_done; /* Bytes written (if needed) */
+ unsigned int erase_attempts; /* Keep track how many times we try to erase the same sector */
+ };
+
+ unsigned int tot_size = flash_probe_chips();
+ unsigned int i, j;
+ unsigned int current_sector_size;
+ unsigned long current_offset;
+ const unsigned char *current_src;
+ char need_erase;
+ struct flash_status *current_flash = NULL;
+
+ static struct flash_status flash_status[2] = {
+ { 0, NULL, 0, 0, 0, 0 },
+ { 0, NULL, 0, 0, 0, 0 }
+ };
+
+ if (!tot_size) {
+ /* No chips found, bail out. */
+ return ERR_FLASH_NONE;
+ }
+
+ if (offset + size > tot_size) {
+ safe_printk("Fatal: flash is too small.\n");
+ return ERR_FLASH_TOO_SMALL;
+ }
+
+ /* Initiate the flash_status structs so that we can keep track of what needs to be done
+ on the different flash chips */
+
+ /* Operations only on flash chip 1 */
+ if (offset >= (&chips[0])->size) {
+ flash_status[0].size = 0;
+ flash_status[1].src = source;
+ flash_status[1].offset = offset - (&chips[0])->size;
+ flash_status[1].size = size;
+ }
+ /* Operations on both flash chips */
+ else if ((offset < (&chips[0])->size) && ((offset+size) > (&chips[0])->size)) {
+ flash_status[0].src = source;
+ flash_status[0].offset = offset;
+ flash_status[0].size = (&chips[0])->size - offset;
+ flash_status[1].src = source + flash_status[0].size;
+ flash_status[1].offset = 0;
+ flash_status[1].size = size - flash_status[0].size;
+ }
+ /* Operations only on flash chip 0 */
+ else {
+ flash_status[0].src = source;
+ flash_status[0].offset = offset;
+ flash_status[0].size = size;
+ flash_status[1].size = 0;
+ }
+ flash_status[0].busy = 0;
+ flash_status[0].bytes_done = 0;
+ flash_status[0].erase_attempts = 0;
+ flash_status[1].busy = 0;
+ flash_status[1].bytes_done = 0;
+ flash_status[1].erase_attempts = 0;
+#if 0
+ for (i = 0; i < 2; i++) {
+ safe_printk("\nFlash ");
+ send_hex(i, NL);
+ safe_printk("src:\t");
+ send_hex((int)flash_status[i].src, NL);
+ safe_printk("offset:\t");
+ send_hex(flash_status[i].offset, NL);
+ safe_printk("size:\t");
+ send_hex(flash_status[i].size, NL);
+ safe_printk("\n");
+ }
+#endif
+
+ /* Erase and write */
+
+ i = 0; /* Start operations on flash 0 */
+
+#define CHANGE_FLASH
+
+ while (((&flash_status[0])->bytes_done + (&flash_status[1])->bytes_done) < size) {
+
+ struct flash_status *previous_flash = &flash_status[i ? 0 : 1];
+ current_flash = &flash_status[i];
+
+#ifdef CHANGE_FLASH
+ /* Change flash only if:
+ - There is a flash to change to and operations should be made on that flash *AND*
+ - There is more to write to the previous flash *AND*
+ - Operations should be made on the current flash *OR*
+ - The current flash is busy *OR*
+ - All has been written to the current flash */
+
+ if (previous_flash->size && (previous_flash->bytes_done < previous_flash->size) &&
+ (!current_flash->size || current_flash->busy ||
+ current_flash->bytes_done == current_flash->size))
+ i = i ? 0 : 1; /* Change flash chip */
+#else
+ /* Finish one flash chip before continuing on the next one */
+
+ if ((&flash_status[i])->bytes_done == (&flash_status[i])->size)
+ i = i ? 0 : 1; /* Change flash chip */
+#endif
+ /* Bail out if we have tried to erase the same sector more that 10 times. */
+ if(current_flash->erase_attempts > 10) {
+ safe_printk("Sector erase error\n");
+ return ERR_FLASH_ERASE;
+ }
+
+ /* Get the current status from the chip we are about to access */
+ current_flash = &flash_status[i];
+ current_offset = current_flash->offset + current_flash->bytes_done;
+ current_src = current_flash->src + current_flash->bytes_done;
+ current_sector_size = find_sector_size(&chips[i], current_offset);
+
+ /* Make sure that the chip we are about to access has finished erasing */
+ if (current_flash->busy) {
+ while (flash_is_busy(&chips[i], current_offset))
+ /* nothing */
+ ;
+ current_flash->busy = 0;
+ }
+
+ /* Some flash chip need a reset to bring them back to read mode again. */
+ wide_cmd(&chips[i], CMD_RESET_DATA, ADDR_UNLOCK_1);
+
+ /* Find out if we need to erase the sector or not */
+ need_erase = need_to_erase(&chips[i], current_offset, current_src, current_sector_size);
+
+ if (need_erase == 0) {
+ current_flash->bytes_done += current_sector_size;
+ current_flash->erase_attempts = 0;
+ send_hex((int)(&chips[i])->base + current_offset, 0);
+ safe_printk(": No need to write\n");
+ continue;
+ } else if (need_erase == 1) {
+ /* Erased, not worth printing. */
+ }
+ else if (need_erase == 2) {
+ send_hex((int)(&chips[i])->base + current_offset, 0);
+ safe_printk(": Erasing ");
+ send_hex(current_sector_size, 0);
+ safe_printk(" bytes\n");
+ start_sector_erase(&chips[i], current_offset);
+ current_flash->busy=1;
+ current_flash->erase_attempts++;
+ continue;
+ }
+
+ /* The sector is ready to be programmed */
+ send_hex((int)(&chips[i])->base + current_offset, 0);
+ safe_printk(": Writing ");
+ send_hex(current_sector_size, 0);
+ safe_printk(" bytes\n");
+ program_sector(&chips[i], current_offset, current_src, current_sector_size);
+ current_flash->bytes_done += current_sector_size;
+ current_flash->erase_attempts = 0;
+ }
+
+ /* Verify that the flash chip(s) have the correct content */
+ for (i = 0; i < 2; i++) {
+ current_flash = &flash_status[i];
+ if (!current_flash->size)
+ continue;
+ send_hex((int)(&chips[i])->base, 0);
+ safe_printk(": Verifying...");
+ for (j = 0; j < current_flash->size; j+=2) {
+ if (*(uword*)(current_flash->offset + j + (&chips[i])->base) !=
+ *(uword*)(current_flash->src + j)) {
+ safe_printk("Error at ");
+ send_hex(j, NL);
+ return ERR_FLASH_VERIFY;
+ }
+ }
+ safe_printk("OK\n");
+ }
+
+ return ERR_FLASH_OK;
+}
diff --git a/package/etrax-tools/src/e100boot/cbl/src/hwregs.c b/package/etrax-tools/src/e100boot/cbl/src/hwregs.c
new file mode 100644
index 000000000..3e0f32ff2
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/hwregs.c
@@ -0,0 +1,1713 @@
+/*!**********************************************************************
+*!
+*! FILE NAME: hwregs.c
+*!
+*! DESCRIPTION: Shadow register and initiated flag variables,
+*! and a function for initialization of these variables.
+*!
+*!
+*! FUNCTIONS: void init_shadow__hwregs( void )
+*!
+*! NOTE: This file is automatically generated, do _not_ edit.
+*! Created: Thu Oct 3 01:21:27 2002
+*! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp
+*! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168
+*! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3
+*!
+*! NOTE: init_shadow__hwregs() initiate all write only registers
+*! described in /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd.
+*! Since one physical register may have several logical names you
+*! must choose which of the logical registers to initiate.
+*! This is done by the 'USE_GROUP__group-name' macro in the
+*! hwregs_def.h file.
+*!
+*! As an example, in Etrax100 the following logical registers are
+*! all the same physical register at address 0xb0000044:
+*!
+*! R_ATA_CONFIG
+*! R_PAR0_CONFIG
+*! R_SCSI0_CTRL
+*! R_SHARED_RAM_ADDR
+*!
+*!----------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! Apr 01 1998 Jan Bengtsson Initial version
+*!----------------------------------------------------------------------
+*!
+*! (C) Copyright 1998, Axis Communications AB, LUND, SWEDEN
+*!
+*!**********************************************************************/
+/* %Z% %M% %I% %G% */
+
+/********************** INCLUDE FILES SECTION **************************/
+
+#include "compiler.h"
+#include "hwregs.h"
+
+#if REG_DEBUG
+#include <string.h>
+#endif
+
+/********************** CONSTANT AND MACRO SECTION *********************/
+
+/********************** TYPE DEFINITION SECTION ************************/
+
+/********************** LOCAL FUNCTION DECLARATION SECTION *************/
+
+/********************** GLOBAL VARIABLE DECLARATION SECTION ************/
+
+#ifndef REG_NO_SHADOW
+/* Shadows for write only registers. */
+reg_shadow_type__hwregs reg_shadow__hwregs;
+#else
+/* Use constant zero as shadow when there isn't a shadow register. */
+reg_shadow_type__hwregs reg_shadow__hwregs = 0;
+#endif
+
+#if REG_DEBUG
+#ifndef REG_NO_SHADOW
+/* Initiated flags for shadow registers. */
+reg_initiated_type__hwregs reg_initiated__hwregs;
+#else
+/* No need for initiated flags when there isn't a shadow register. */
+reg_initiated_type__hwregs reg_initiated__hwregs = 0;
+#endif
+#endif
+
+/********************** FUNCTION DEFINITION SECTION ********************/
+
+/*#**********************************************************************
+*#
+*# FUNCTION NAME: init_shadow__hwregs
+*#
+*# PARAMETERS : none
+*#
+*# RETURNS : nothing
+*#
+*# SIDE EFFECTS : Writes initial values to all write only registers
+*# and their associated shadow registers. If REG_DEBUG
+*# is non zero the reg_initiated struct is also initiated.
+*#
+*# DESCRIPTION : Initiate write only registers, their shadows, and in
+*# debug mode the initiated flags. Default values for
+*# the initialization are defined in hwregs_def.h.
+*#
+*# Note that one physical register may have several
+*# logical names, and that you have to modify this
+*# function to only initiate the physical register once!
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*#
+*#**********************************************************************/
+
+void init_shadow__hwregs( void )
+{
+#if REG_DEBUG && !defined(REG_NO_SHADOW)
+ /* Initiate reg_initiated__hwregs struct to 0xff. */
+ memset( &reg_initiated__hwregs, 0xff, sizeof(reg_initiated_type__hwregs) );
+#endif
+
+#ifndef REG_NO_INIT_SHADOW
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_ALT_SER_BAUDRATE(
+ ser3_tr, R_ALT_SER_BAUDRATE__ser3_tr__DEFAULT,
+ ser3_rec, R_ALT_SER_BAUDRATE__ser3_rec__DEFAULT,
+ ser2_tr, R_ALT_SER_BAUDRATE__ser2_tr__DEFAULT,
+ ser2_rec, R_ALT_SER_BAUDRATE__ser2_rec__DEFAULT,
+ ser1_tr, R_ALT_SER_BAUDRATE__ser1_tr__DEFAULT,
+ ser1_rec, R_ALT_SER_BAUDRATE__ser1_rec__DEFAULT,
+ ser0_tr, R_ALT_SER_BAUDRATE__ser0_tr__DEFAULT,
+ ser0_rec, R_ALT_SER_BAUDRATE__ser0_rec__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__ATA_interface_registers
+ REG_SET__R_ATA_CONFIG(
+ enable, R_ATA_CONFIG__enable__DEFAULT,
+ dma_strobe, R_ATA_CONFIG__dma_strobe__DEFAULT,
+ dma_hold, R_ATA_CONFIG__dma_hold__DEFAULT,
+ pio_setup, R_ATA_CONFIG__pio_setup__DEFAULT,
+ pio_strobe, R_ATA_CONFIG__pio_strobe__DEFAULT,
+ pio_hold, R_ATA_CONFIG__pio_hold__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__ATA_interface_registers
+ REG_SET__R_ATA_CTRL_DATA(
+ sel, R_ATA_CTRL_DATA__sel__DEFAULT,
+ cs1, R_ATA_CTRL_DATA__cs1__DEFAULT,
+ cs0, R_ATA_CTRL_DATA__cs0__DEFAULT,
+ addr, R_ATA_CTRL_DATA__addr__DEFAULT,
+ rw, R_ATA_CTRL_DATA__rw__DEFAULT,
+ src_dst, R_ATA_CTRL_DATA__src_dst__DEFAULT,
+ handsh, R_ATA_CTRL_DATA__handsh__DEFAULT,
+ multi, R_ATA_CTRL_DATA__multi__DEFAULT,
+ dma_size, R_ATA_CTRL_DATA__dma_size__DEFAULT,
+ data, R_ATA_CTRL_DATA__data__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Bus_interface_configuration_registers
+ REG_SET__R_BUS_CONFIG(
+ sram_type, R_BUS_CONFIG__sram_type__DEFAULT,
+ dma_burst, R_BUS_CONFIG__dma_burst__DEFAULT,
+ pcs4_7_wr, R_BUS_CONFIG__pcs4_7_wr__DEFAULT,
+ pcs0_3_wr, R_BUS_CONFIG__pcs0_3_wr__DEFAULT,
+ sram_wr, R_BUS_CONFIG__sram_wr__DEFAULT,
+ flash_wr, R_BUS_CONFIG__flash_wr__DEFAULT,
+ pcs4_7_bw, R_BUS_CONFIG__pcs4_7_bw__DEFAULT,
+ pcs0_3_bw, R_BUS_CONFIG__pcs0_3_bw__DEFAULT,
+ sram_bw, R_BUS_CONFIG__sram_bw__DEFAULT,
+ flash_bw, R_BUS_CONFIG__flash_bw__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Timer_registers
+ REG_SET__R_CLOCK_PRESCALE(
+ ser_presc, R_CLOCK_PRESCALE__ser_presc__DEFAULT,
+ tim_presc, R_CLOCK_PRESCALE__tim_presc__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH0_CLR_INTR(
+ clr_eop, R_DMA_CH0_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH0_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH1_CLR_INTR(
+ clr_eop, R_DMA_CH1_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH1_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH2_CLR_INTR(
+ clr_eop, R_DMA_CH2_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH2_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH3_CLR_INTR(
+ clr_eop, R_DMA_CH3_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH3_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH4_CLR_INTR(
+ clr_eop, R_DMA_CH4_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH4_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH5_CLR_INTR(
+ clr_eop, R_DMA_CH5_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH5_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH6_CLR_INTR(
+ clr_eop, R_DMA_CH6_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH6_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH7_CLR_INTR(
+ clr_eop, R_DMA_CH7_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH7_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH8_CLR_INTR(
+ clr_eop, R_DMA_CH8_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH8_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH8_SUB0_CLR_INTR(
+ clr_descr, R_DMA_CH8_SUB0_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH8_SUB1_CLR_INTR(
+ clr_descr, R_DMA_CH8_SUB1_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH8_SUB2_CLR_INTR(
+ clr_descr, R_DMA_CH8_SUB2_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH8_SUB3_CLR_INTR(
+ clr_descr, R_DMA_CH8_SUB3_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_DMA_CH9_CLR_INTR(
+ clr_eop, R_DMA_CH9_CLR_INTR__clr_eop__DEFAULT,
+ clr_descr, R_DMA_CH9_CLR_INTR__clr_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Bus_interface_configuration_registers
+ REG_SET__R_DRAM_CONFIG(
+ wmm1, R_DRAM_CONFIG__wmm1__DEFAULT,
+ wmm0, R_DRAM_CONFIG__wmm0__DEFAULT,
+ sh1, R_DRAM_CONFIG__sh1__DEFAULT,
+ sh0, R_DRAM_CONFIG__sh0__DEFAULT,
+ w, R_DRAM_CONFIG__w__DEFAULT,
+ c, R_DRAM_CONFIG__c__DEFAULT,
+ e, R_DRAM_CONFIG__e__DEFAULT,
+ group_sel, R_DRAM_CONFIG__group_sel__DEFAULT,
+ ca1, R_DRAM_CONFIG__ca1__DEFAULT,
+ bank23sel, R_DRAM_CONFIG__bank23sel__DEFAULT,
+ ca0, R_DRAM_CONFIG__ca0__DEFAULT,
+ bank01sel, R_DRAM_CONFIG__bank01sel__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Bus_interface_configuration_registers
+ REG_SET__R_DRAM_TIMING(
+ sdram, R_DRAM_TIMING__sdram__DEFAULT,
+ ref, R_DRAM_TIMING__ref__DEFAULT,
+ rp, R_DRAM_TIMING__rp__DEFAULT,
+ rs, R_DRAM_TIMING__rs__DEFAULT,
+ rh, R_DRAM_TIMING__rh__DEFAULT,
+ w, R_DRAM_TIMING__w__DEFAULT,
+ c, R_DRAM_TIMING__c__DEFAULT,
+ cz, R_DRAM_TIMING__cz__DEFAULT,
+ cp, R_DRAM_TIMING__cp__DEFAULT,
+ cw, R_DRAM_TIMING__cw__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__External_DMA_registers
+ REG_SET__R_EXT_DMA_0_ADDR(
+ ext0_addr, R_EXT_DMA_0_ADDR__ext0_addr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__External_DMA_registers
+ REG_SET__R_EXT_DMA_0_CMD(
+ cnt, R_EXT_DMA_0_CMD__cnt__DEFAULT,
+ rqpol, R_EXT_DMA_0_CMD__rqpol__DEFAULT,
+ apol, R_EXT_DMA_0_CMD__apol__DEFAULT,
+ rq_ack, R_EXT_DMA_0_CMD__rq_ack__DEFAULT,
+ wid, R_EXT_DMA_0_CMD__wid__DEFAULT,
+ dir, R_EXT_DMA_0_CMD__dir__DEFAULT,
+ run, R_EXT_DMA_0_CMD__run__DEFAULT,
+ trf_count, R_EXT_DMA_0_CMD__trf_count__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__External_DMA_registers
+ REG_SET__R_EXT_DMA_1_ADDR(
+ ext0_addr, R_EXT_DMA_1_ADDR__ext0_addr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__External_DMA_registers
+ REG_SET__R_EXT_DMA_1_CMD(
+ cnt, R_EXT_DMA_1_CMD__cnt__DEFAULT,
+ rqpol, R_EXT_DMA_1_CMD__rqpol__DEFAULT,
+ apol, R_EXT_DMA_1_CMD__apol__DEFAULT,
+ rq_ack, R_EXT_DMA_1_CMD__rq_ack__DEFAULT,
+ wid, R_EXT_DMA_1_CMD__wid__DEFAULT,
+ dir, R_EXT_DMA_1_CMD__dir__DEFAULT,
+ run, R_EXT_DMA_1_CMD__run__DEFAULT,
+ trf_count, R_EXT_DMA_1_CMD__trf_count__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_config_registers
+ REG_SET__R_GEN_CONFIG(
+ par_w, R_GEN_CONFIG__par_w__DEFAULT,
+ usb2, R_GEN_CONFIG__usb2__DEFAULT,
+ usb1, R_GEN_CONFIG__usb1__DEFAULT,
+ g24dir, R_GEN_CONFIG__g24dir__DEFAULT,
+ g16_23dir, R_GEN_CONFIG__g16_23dir__DEFAULT,
+ g8_15dir, R_GEN_CONFIG__g8_15dir__DEFAULT,
+ g0dir, R_GEN_CONFIG__g0dir__DEFAULT,
+ dma9, R_GEN_CONFIG__dma9__DEFAULT,
+ dma8, R_GEN_CONFIG__dma8__DEFAULT,
+ dma7, R_GEN_CONFIG__dma7__DEFAULT,
+ dma6, R_GEN_CONFIG__dma6__DEFAULT,
+ dma5, R_GEN_CONFIG__dma5__DEFAULT,
+ dma4, R_GEN_CONFIG__dma4__DEFAULT,
+ dma3, R_GEN_CONFIG__dma3__DEFAULT,
+ dma2, R_GEN_CONFIG__dma2__DEFAULT,
+ mio_w, R_GEN_CONFIG__mio_w__DEFAULT,
+ ser3, R_GEN_CONFIG__ser3__DEFAULT,
+ par1, R_GEN_CONFIG__par1__DEFAULT,
+ scsi0w, R_GEN_CONFIG__scsi0w__DEFAULT,
+ scsi1, R_GEN_CONFIG__scsi1__DEFAULT,
+ mio, R_GEN_CONFIG__mio__DEFAULT,
+ ser2, R_GEN_CONFIG__ser2__DEFAULT,
+ par0, R_GEN_CONFIG__par0__DEFAULT,
+ ata, R_GEN_CONFIG__ata__DEFAULT,
+ scsi0, R_GEN_CONFIG__scsi0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_config_registers
+ REG_SET__R_GEN_CONFIG_II(
+ sermode3, R_GEN_CONFIG_II__sermode3__DEFAULT,
+ sermode1, R_GEN_CONFIG_II__sermode1__DEFAULT,
+ ext_clk, R_GEN_CONFIG_II__ext_clk__DEFAULT,
+ ser3, R_GEN_CONFIG_II__ser3__DEFAULT,
+ ser2, R_GEN_CONFIG_II__ser2__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ REG_SET__R_IRQ_MASK0_CLR(
+ nmi_pin, R_IRQ_MASK0_CLR__nmi_pin__DEFAULT,
+ watchdog_nmi, R_IRQ_MASK0_CLR__watchdog_nmi__DEFAULT,
+ sqe_test_error, R_IRQ_MASK0_CLR__sqe_test_error__DEFAULT,
+ carrier_loss, R_IRQ_MASK0_CLR__carrier_loss__DEFAULT,
+ deferred, R_IRQ_MASK0_CLR__deferred__DEFAULT,
+ late_col, R_IRQ_MASK0_CLR__late_col__DEFAULT,
+ multiple_col, R_IRQ_MASK0_CLR__multiple_col__DEFAULT,
+ single_col, R_IRQ_MASK0_CLR__single_col__DEFAULT,
+ congestion, R_IRQ_MASK0_CLR__congestion__DEFAULT,
+ oversize, R_IRQ_MASK0_CLR__oversize__DEFAULT,
+ alignment_error, R_IRQ_MASK0_CLR__alignment_error__DEFAULT,
+ crc_error, R_IRQ_MASK0_CLR__crc_error__DEFAULT,
+ overrun, R_IRQ_MASK0_CLR__overrun__DEFAULT,
+ underrun, R_IRQ_MASK0_CLR__underrun__DEFAULT,
+ excessive_col, R_IRQ_MASK0_CLR__excessive_col__DEFAULT,
+ mdio, R_IRQ_MASK0_CLR__mdio__DEFAULT,
+ ata_drq3, R_IRQ_MASK0_CLR__ata_drq3__DEFAULT,
+ ata_drq2, R_IRQ_MASK0_CLR__ata_drq2__DEFAULT,
+ ata_drq1, R_IRQ_MASK0_CLR__ata_drq1__DEFAULT,
+ ata_drq0, R_IRQ_MASK0_CLR__ata_drq0__DEFAULT,
+ par0_ecp_cmd, R_IRQ_MASK0_CLR__par0_ecp_cmd__DEFAULT,
+ par0_peri, R_IRQ_MASK0_CLR__par0_peri__DEFAULT,
+ par0_data, R_IRQ_MASK0_CLR__par0_data__DEFAULT,
+ par0_ready, R_IRQ_MASK0_CLR__par0_ready__DEFAULT,
+ ata_dmaend, R_IRQ_MASK0_CLR__ata_dmaend__DEFAULT,
+ irq_ext_vector_nr, R_IRQ_MASK0_CLR__irq_ext_vector_nr__DEFAULT,
+ irq_int_vector_nr, R_IRQ_MASK0_CLR__irq_int_vector_nr__DEFAULT,
+ ext_dma1, R_IRQ_MASK0_CLR__ext_dma1__DEFAULT,
+ ext_dma0, R_IRQ_MASK0_CLR__ext_dma0__DEFAULT,
+ timer1, R_IRQ_MASK0_CLR__timer1__DEFAULT,
+ timer0, R_IRQ_MASK0_CLR__timer0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ REG_SET__R_IRQ_MASK0_SET(
+ nmi_pin, R_IRQ_MASK0_SET__nmi_pin__DEFAULT,
+ watchdog_nmi, R_IRQ_MASK0_SET__watchdog_nmi__DEFAULT,
+ sqe_test_error, R_IRQ_MASK0_SET__sqe_test_error__DEFAULT,
+ carrier_loss, R_IRQ_MASK0_SET__carrier_loss__DEFAULT,
+ deferred, R_IRQ_MASK0_SET__deferred__DEFAULT,
+ late_col, R_IRQ_MASK0_SET__late_col__DEFAULT,
+ multiple_col, R_IRQ_MASK0_SET__multiple_col__DEFAULT,
+ single_col, R_IRQ_MASK0_SET__single_col__DEFAULT,
+ congestion, R_IRQ_MASK0_SET__congestion__DEFAULT,
+ oversize, R_IRQ_MASK0_SET__oversize__DEFAULT,
+ alignment_error, R_IRQ_MASK0_SET__alignment_error__DEFAULT,
+ crc_error, R_IRQ_MASK0_SET__crc_error__DEFAULT,
+ overrun, R_IRQ_MASK0_SET__overrun__DEFAULT,
+ underrun, R_IRQ_MASK0_SET__underrun__DEFAULT,
+ excessive_col, R_IRQ_MASK0_SET__excessive_col__DEFAULT,
+ mdio, R_IRQ_MASK0_SET__mdio__DEFAULT,
+ ata_drq3, R_IRQ_MASK0_SET__ata_drq3__DEFAULT,
+ ata_drq2, R_IRQ_MASK0_SET__ata_drq2__DEFAULT,
+ ata_drq1, R_IRQ_MASK0_SET__ata_drq1__DEFAULT,
+ ata_drq0, R_IRQ_MASK0_SET__ata_drq0__DEFAULT,
+ par0_ecp_cmd, R_IRQ_MASK0_SET__par0_ecp_cmd__DEFAULT,
+ par0_peri, R_IRQ_MASK0_SET__par0_peri__DEFAULT,
+ par0_data, R_IRQ_MASK0_SET__par0_data__DEFAULT,
+ par0_ready, R_IRQ_MASK0_SET__par0_ready__DEFAULT,
+ ata_dmaend, R_IRQ_MASK0_SET__ata_dmaend__DEFAULT,
+ irq_ext_vector_nr, R_IRQ_MASK0_SET__irq_ext_vector_nr__DEFAULT,
+ irq_int_vector_nr, R_IRQ_MASK0_SET__irq_int_vector_nr__DEFAULT,
+ ext_dma1, R_IRQ_MASK0_SET__ext_dma1__DEFAULT,
+ ext_dma0, R_IRQ_MASK0_SET__ext_dma0__DEFAULT,
+ timer1, R_IRQ_MASK0_SET__timer1__DEFAULT,
+ timer0, R_IRQ_MASK0_SET__timer0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ REG_SET__R_IRQ_MASK1_CLR(
+ sw_int7, R_IRQ_MASK1_CLR__sw_int7__DEFAULT,
+ sw_int6, R_IRQ_MASK1_CLR__sw_int6__DEFAULT,
+ sw_int5, R_IRQ_MASK1_CLR__sw_int5__DEFAULT,
+ sw_int4, R_IRQ_MASK1_CLR__sw_int4__DEFAULT,
+ sw_int3, R_IRQ_MASK1_CLR__sw_int3__DEFAULT,
+ sw_int2, R_IRQ_MASK1_CLR__sw_int2__DEFAULT,
+ sw_int1, R_IRQ_MASK1_CLR__sw_int1__DEFAULT,
+ sw_int0, R_IRQ_MASK1_CLR__sw_int0__DEFAULT,
+ par1_ecp_cmd, R_IRQ_MASK1_CLR__par1_ecp_cmd__DEFAULT,
+ par1_peri, R_IRQ_MASK1_CLR__par1_peri__DEFAULT,
+ par1_data, R_IRQ_MASK1_CLR__par1_data__DEFAULT,
+ par1_ready, R_IRQ_MASK1_CLR__par1_ready__DEFAULT,
+ ser3_ready, R_IRQ_MASK1_CLR__ser3_ready__DEFAULT,
+ ser3_data, R_IRQ_MASK1_CLR__ser3_data__DEFAULT,
+ ser2_ready, R_IRQ_MASK1_CLR__ser2_ready__DEFAULT,
+ ser2_data, R_IRQ_MASK1_CLR__ser2_data__DEFAULT,
+ ser1_ready, R_IRQ_MASK1_CLR__ser1_ready__DEFAULT,
+ ser1_data, R_IRQ_MASK1_CLR__ser1_data__DEFAULT,
+ ser0_ready, R_IRQ_MASK1_CLR__ser0_ready__DEFAULT,
+ ser0_data, R_IRQ_MASK1_CLR__ser0_data__DEFAULT,
+ pa7, R_IRQ_MASK1_CLR__pa7__DEFAULT,
+ pa6, R_IRQ_MASK1_CLR__pa6__DEFAULT,
+ pa5, R_IRQ_MASK1_CLR__pa5__DEFAULT,
+ pa4, R_IRQ_MASK1_CLR__pa4__DEFAULT,
+ pa3, R_IRQ_MASK1_CLR__pa3__DEFAULT,
+ pa2, R_IRQ_MASK1_CLR__pa2__DEFAULT,
+ pa1, R_IRQ_MASK1_CLR__pa1__DEFAULT,
+ pa0, R_IRQ_MASK1_CLR__pa0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ REG_SET__R_IRQ_MASK1_SET(
+ sw_int7, R_IRQ_MASK1_SET__sw_int7__DEFAULT,
+ sw_int6, R_IRQ_MASK1_SET__sw_int6__DEFAULT,
+ sw_int5, R_IRQ_MASK1_SET__sw_int5__DEFAULT,
+ sw_int4, R_IRQ_MASK1_SET__sw_int4__DEFAULT,
+ sw_int3, R_IRQ_MASK1_SET__sw_int3__DEFAULT,
+ sw_int2, R_IRQ_MASK1_SET__sw_int2__DEFAULT,
+ sw_int1, R_IRQ_MASK1_SET__sw_int1__DEFAULT,
+ sw_int0, R_IRQ_MASK1_SET__sw_int0__DEFAULT,
+ par1_ecp_cmd, R_IRQ_MASK1_SET__par1_ecp_cmd__DEFAULT,
+ par1_peri, R_IRQ_MASK1_SET__par1_peri__DEFAULT,
+ par1_data, R_IRQ_MASK1_SET__par1_data__DEFAULT,
+ par1_ready, R_IRQ_MASK1_SET__par1_ready__DEFAULT,
+ ser3_ready, R_IRQ_MASK1_SET__ser3_ready__DEFAULT,
+ ser3_data, R_IRQ_MASK1_SET__ser3_data__DEFAULT,
+ ser2_ready, R_IRQ_MASK1_SET__ser2_ready__DEFAULT,
+ ser2_data, R_IRQ_MASK1_SET__ser2_data__DEFAULT,
+ ser1_ready, R_IRQ_MASK1_SET__ser1_ready__DEFAULT,
+ ser1_data, R_IRQ_MASK1_SET__ser1_data__DEFAULT,
+ ser0_ready, R_IRQ_MASK1_SET__ser0_ready__DEFAULT,
+ ser0_data, R_IRQ_MASK1_SET__ser0_data__DEFAULT,
+ pa7, R_IRQ_MASK1_SET__pa7__DEFAULT,
+ pa6, R_IRQ_MASK1_SET__pa6__DEFAULT,
+ pa5, R_IRQ_MASK1_SET__pa5__DEFAULT,
+ pa4, R_IRQ_MASK1_SET__pa4__DEFAULT,
+ pa3, R_IRQ_MASK1_SET__pa3__DEFAULT,
+ pa2, R_IRQ_MASK1_SET__pa2__DEFAULT,
+ pa1, R_IRQ_MASK1_SET__pa1__DEFAULT,
+ pa0, R_IRQ_MASK1_SET__pa0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ REG_SET__R_IRQ_MASK2_CLR(
+ dma8_sub3_descr, R_IRQ_MASK2_CLR__dma8_sub3_descr__DEFAULT,
+ dma8_sub2_descr, R_IRQ_MASK2_CLR__dma8_sub2_descr__DEFAULT,
+ dma8_sub1_descr, R_IRQ_MASK2_CLR__dma8_sub1_descr__DEFAULT,
+ dma8_sub0_descr, R_IRQ_MASK2_CLR__dma8_sub0_descr__DEFAULT,
+ dma9_eop, R_IRQ_MASK2_CLR__dma9_eop__DEFAULT,
+ dma9_descr, R_IRQ_MASK2_CLR__dma9_descr__DEFAULT,
+ dma8_eop, R_IRQ_MASK2_CLR__dma8_eop__DEFAULT,
+ dma8_descr, R_IRQ_MASK2_CLR__dma8_descr__DEFAULT,
+ dma7_eop, R_IRQ_MASK2_CLR__dma7_eop__DEFAULT,
+ dma7_descr, R_IRQ_MASK2_CLR__dma7_descr__DEFAULT,
+ dma6_eop, R_IRQ_MASK2_CLR__dma6_eop__DEFAULT,
+ dma6_descr, R_IRQ_MASK2_CLR__dma6_descr__DEFAULT,
+ dma5_eop, R_IRQ_MASK2_CLR__dma5_eop__DEFAULT,
+ dma5_descr, R_IRQ_MASK2_CLR__dma5_descr__DEFAULT,
+ dma4_eop, R_IRQ_MASK2_CLR__dma4_eop__DEFAULT,
+ dma4_descr, R_IRQ_MASK2_CLR__dma4_descr__DEFAULT,
+ dma3_eop, R_IRQ_MASK2_CLR__dma3_eop__DEFAULT,
+ dma3_descr, R_IRQ_MASK2_CLR__dma3_descr__DEFAULT,
+ dma2_eop, R_IRQ_MASK2_CLR__dma2_eop__DEFAULT,
+ dma2_descr, R_IRQ_MASK2_CLR__dma2_descr__DEFAULT,
+ dma1_eop, R_IRQ_MASK2_CLR__dma1_eop__DEFAULT,
+ dma1_descr, R_IRQ_MASK2_CLR__dma1_descr__DEFAULT,
+ dma0_eop, R_IRQ_MASK2_CLR__dma0_eop__DEFAULT,
+ dma0_descr, R_IRQ_MASK2_CLR__dma0_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ REG_SET__R_IRQ_MASK2_SET(
+ dma8_sub3_descr, R_IRQ_MASK2_SET__dma8_sub3_descr__DEFAULT,
+ dma8_sub2_descr, R_IRQ_MASK2_SET__dma8_sub2_descr__DEFAULT,
+ dma8_sub1_descr, R_IRQ_MASK2_SET__dma8_sub1_descr__DEFAULT,
+ dma8_sub0_descr, R_IRQ_MASK2_SET__dma8_sub0_descr__DEFAULT,
+ dma9_eop, R_IRQ_MASK2_SET__dma9_eop__DEFAULT,
+ dma9_descr, R_IRQ_MASK2_SET__dma9_descr__DEFAULT,
+ dma8_eop, R_IRQ_MASK2_SET__dma8_eop__DEFAULT,
+ dma8_descr, R_IRQ_MASK2_SET__dma8_descr__DEFAULT,
+ dma7_eop, R_IRQ_MASK2_SET__dma7_eop__DEFAULT,
+ dma7_descr, R_IRQ_MASK2_SET__dma7_descr__DEFAULT,
+ dma6_eop, R_IRQ_MASK2_SET__dma6_eop__DEFAULT,
+ dma6_descr, R_IRQ_MASK2_SET__dma6_descr__DEFAULT,
+ dma5_eop, R_IRQ_MASK2_SET__dma5_eop__DEFAULT,
+ dma5_descr, R_IRQ_MASK2_SET__dma5_descr__DEFAULT,
+ dma4_eop, R_IRQ_MASK2_SET__dma4_eop__DEFAULT,
+ dma4_descr, R_IRQ_MASK2_SET__dma4_descr__DEFAULT,
+ dma3_eop, R_IRQ_MASK2_SET__dma3_eop__DEFAULT,
+ dma3_descr, R_IRQ_MASK2_SET__dma3_descr__DEFAULT,
+ dma2_eop, R_IRQ_MASK2_SET__dma2_eop__DEFAULT,
+ dma2_descr, R_IRQ_MASK2_SET__dma2_descr__DEFAULT,
+ dma1_eop, R_IRQ_MASK2_SET__dma1_eop__DEFAULT,
+ dma1_descr, R_IRQ_MASK2_SET__dma1_descr__DEFAULT,
+ dma0_eop, R_IRQ_MASK2_SET__dma0_eop__DEFAULT,
+ dma0_descr, R_IRQ_MASK2_SET__dma0_descr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__MMU_registers
+ REG_SET__R_MMU_CONFIG(
+ mmu_enable, R_MMU_CONFIG__mmu_enable__DEFAULT,
+ inv_excp, R_MMU_CONFIG__inv_excp__DEFAULT,
+ acc_excp, R_MMU_CONFIG__acc_excp__DEFAULT,
+ we_excp, R_MMU_CONFIG__we_excp__DEFAULT,
+ seg_f, R_MMU_CONFIG__seg_f__DEFAULT,
+ seg_e, R_MMU_CONFIG__seg_e__DEFAULT,
+ seg_d, R_MMU_CONFIG__seg_d__DEFAULT,
+ seg_c, R_MMU_CONFIG__seg_c__DEFAULT,
+ seg_b, R_MMU_CONFIG__seg_b__DEFAULT,
+ seg_a, R_MMU_CONFIG__seg_a__DEFAULT,
+ seg_9, R_MMU_CONFIG__seg_9__DEFAULT,
+ seg_8, R_MMU_CONFIG__seg_8__DEFAULT,
+ seg_7, R_MMU_CONFIG__seg_7__DEFAULT,
+ seg_6, R_MMU_CONFIG__seg_6__DEFAULT,
+ seg_5, R_MMU_CONFIG__seg_5__DEFAULT,
+ seg_4, R_MMU_CONFIG__seg_4__DEFAULT,
+ seg_3, R_MMU_CONFIG__seg_3__DEFAULT,
+ seg_2, R_MMU_CONFIG__seg_2__DEFAULT,
+ seg_1, R_MMU_CONFIG__seg_1__DEFAULT,
+ seg_0, R_MMU_CONFIG__seg_0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__MMU_registers
+ REG_SET__R_MMU_CTRL(
+ inv_excp, R_MMU_CTRL__inv_excp__DEFAULT,
+ acc_excp, R_MMU_CTRL__acc_excp__DEFAULT,
+ we_excp, R_MMU_CTRL__we_excp__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__MMU_registers
+ REG_SET__R_MMU_ENABLE(
+ mmu_enable, R_MMU_ENABLE__mmu_enable__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__MMU_registers
+ REG_SET__R_MMU_KBASE_HI(
+ base_f, R_MMU_KBASE_HI__base_f__DEFAULT,
+ base_e, R_MMU_KBASE_HI__base_e__DEFAULT,
+ base_d, R_MMU_KBASE_HI__base_d__DEFAULT,
+ base_c, R_MMU_KBASE_HI__base_c__DEFAULT,
+ base_b, R_MMU_KBASE_HI__base_b__DEFAULT,
+ base_a, R_MMU_KBASE_HI__base_a__DEFAULT,
+ base_9, R_MMU_KBASE_HI__base_9__DEFAULT,
+ base_8, R_MMU_KBASE_HI__base_8__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__MMU_registers
+ REG_SET__R_MMU_KBASE_LO(
+ base_7, R_MMU_KBASE_LO__base_7__DEFAULT,
+ base_6, R_MMU_KBASE_LO__base_6__DEFAULT,
+ base_5, R_MMU_KBASE_LO__base_5__DEFAULT,
+ base_4, R_MMU_KBASE_LO__base_4__DEFAULT,
+ base_3, R_MMU_KBASE_LO__base_3__DEFAULT,
+ base_2, R_MMU_KBASE_LO__base_2__DEFAULT,
+ base_1, R_MMU_KBASE_LO__base_1__DEFAULT,
+ base_0, R_MMU_KBASE_LO__base_0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__MMU_registers
+ REG_SET__R_MMU_KSEG(
+ seg_f, R_MMU_KSEG__seg_f__DEFAULT,
+ seg_e, R_MMU_KSEG__seg_e__DEFAULT,
+ seg_d, R_MMU_KSEG__seg_d__DEFAULT,
+ seg_c, R_MMU_KSEG__seg_c__DEFAULT,
+ seg_b, R_MMU_KSEG__seg_b__DEFAULT,
+ seg_a, R_MMU_KSEG__seg_a__DEFAULT,
+ seg_9, R_MMU_KSEG__seg_9__DEFAULT,
+ seg_8, R_MMU_KSEG__seg_8__DEFAULT,
+ seg_7, R_MMU_KSEG__seg_7__DEFAULT,
+ seg_6, R_MMU_KSEG__seg_6__DEFAULT,
+ seg_5, R_MMU_KSEG__seg_5__DEFAULT,
+ seg_4, R_MMU_KSEG__seg_4__DEFAULT,
+ seg_3, R_MMU_KSEG__seg_3__DEFAULT,
+ seg_2, R_MMU_KSEG__seg_2__DEFAULT,
+ seg_1, R_MMU_KSEG__seg_1__DEFAULT,
+ seg_0, R_MMU_KSEG__seg_0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_GA_0(
+ ga_low, R_NETWORK_GA_0__ga_low__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_GA_1(
+ ga_high, R_NETWORK_GA_1__ga_high__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_GEN_CONFIG(
+ loopback, R_NETWORK_GEN_CONFIG__loopback__DEFAULT,
+ frame, R_NETWORK_GEN_CONFIG__frame__DEFAULT,
+ vg, R_NETWORK_GEN_CONFIG__vg__DEFAULT,
+ phy, R_NETWORK_GEN_CONFIG__phy__DEFAULT,
+ enable, R_NETWORK_GEN_CONFIG__enable__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_MGM_CTRL(
+ txd_pins, R_NETWORK_MGM_CTRL__txd_pins__DEFAULT,
+ txer_pin, R_NETWORK_MGM_CTRL__txer_pin__DEFAULT,
+ mdck, R_NETWORK_MGM_CTRL__mdck__DEFAULT,
+ mdoe, R_NETWORK_MGM_CTRL__mdoe__DEFAULT,
+ mdio, R_NETWORK_MGM_CTRL__mdio__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_REC_CONFIG(
+ max_size, R_NETWORK_REC_CONFIG__max_size__DEFAULT,
+ duplex, R_NETWORK_REC_CONFIG__duplex__DEFAULT,
+ bad_crc, R_NETWORK_REC_CONFIG__bad_crc__DEFAULT,
+ oversize, R_NETWORK_REC_CONFIG__oversize__DEFAULT,
+ undersize, R_NETWORK_REC_CONFIG__undersize__DEFAULT,
+ all_roots, R_NETWORK_REC_CONFIG__all_roots__DEFAULT,
+ tr_broadcast, R_NETWORK_REC_CONFIG__tr_broadcast__DEFAULT,
+ broadcast, R_NETWORK_REC_CONFIG__broadcast__DEFAULT,
+ individual, R_NETWORK_REC_CONFIG__individual__DEFAULT,
+ ma1, R_NETWORK_REC_CONFIG__ma1__DEFAULT,
+ ma0, R_NETWORK_REC_CONFIG__ma0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_SA_0(
+ ma0_low, R_NETWORK_SA_0__ma0_low__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_SA_1(
+ ma1_low, R_NETWORK_SA_1__ma1_low__DEFAULT,
+ ma0_high, R_NETWORK_SA_1__ma0_high__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_SA_2(
+ ma1_high, R_NETWORK_SA_2__ma1_high__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Network_interface_registers
+ REG_SET__R_NETWORK_TR_CTRL(
+ clr_error, R_NETWORK_TR_CTRL__clr_error__DEFAULT,
+ delay, R_NETWORK_TR_CTRL__delay__DEFAULT,
+ cancel, R_NETWORK_TR_CTRL__cancel__DEFAULT,
+ cd, R_NETWORK_TR_CTRL__cd__DEFAULT,
+ retry, R_NETWORK_TR_CTRL__retry__DEFAULT,
+ pad, R_NETWORK_TR_CTRL__pad__DEFAULT,
+ crc, R_NETWORK_TR_CTRL__crc__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Parallel_printer_port_registers
+ REG_SET__R_PAR0_CONFIG(
+ ioe, R_PAR0_CONFIG__ioe__DEFAULT,
+ iseli, R_PAR0_CONFIG__iseli__DEFAULT,
+ iautofd, R_PAR0_CONFIG__iautofd__DEFAULT,
+ istrb, R_PAR0_CONFIG__istrb__DEFAULT,
+ iinit, R_PAR0_CONFIG__iinit__DEFAULT,
+ iperr, R_PAR0_CONFIG__iperr__DEFAULT,
+ iack, R_PAR0_CONFIG__iack__DEFAULT,
+ ibusy, R_PAR0_CONFIG__ibusy__DEFAULT,
+ ifault, R_PAR0_CONFIG__ifault__DEFAULT,
+ isel, R_PAR0_CONFIG__isel__DEFAULT,
+ ext_mode, R_PAR0_CONFIG__ext_mode__DEFAULT,
+ wide, R_PAR0_CONFIG__wide__DEFAULT,
+ dma, R_PAR0_CONFIG__dma__DEFAULT,
+ rle_in, R_PAR0_CONFIG__rle_in__DEFAULT,
+ rle_out, R_PAR0_CONFIG__rle_out__DEFAULT,
+ enable, R_PAR0_CONFIG__enable__DEFAULT,
+ force, R_PAR0_CONFIG__force__DEFAULT,
+ ign_ack, R_PAR0_CONFIG__ign_ack__DEFAULT,
+ oe_ack, R_PAR0_CONFIG__oe_ack__DEFAULT,
+ mode, R_PAR0_CONFIG__mode__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Parallel_printer_port_registers
+ REG_SET__R_PAR0_CTRL(
+ ctrl, R_PAR0_CTRL__ctrl__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Parallel_printer_port_registers
+ REG_SET__R_PAR0_CTRL_DATA(
+ peri_int, R_PAR0_CTRL_DATA__peri_int__DEFAULT,
+ oe, R_PAR0_CTRL_DATA__oe__DEFAULT,
+ seli, R_PAR0_CTRL_DATA__seli__DEFAULT,
+ autofd, R_PAR0_CTRL_DATA__autofd__DEFAULT,
+ strb, R_PAR0_CTRL_DATA__strb__DEFAULT,
+ init, R_PAR0_CTRL_DATA__init__DEFAULT,
+ ecp_cmd, R_PAR0_CTRL_DATA__ecp_cmd__DEFAULT,
+ data, R_PAR0_CTRL_DATA__data__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Parallel_printer_port_registers
+ REG_SET__R_PAR0_DELAY(
+ fine_hold, R_PAR0_DELAY__fine_hold__DEFAULT,
+ hold, R_PAR0_DELAY__hold__DEFAULT,
+ fine_strb, R_PAR0_DELAY__fine_strb__DEFAULT,
+ strobe, R_PAR0_DELAY__strobe__DEFAULT,
+ fine_setup, R_PAR0_DELAY__fine_setup__DEFAULT,
+ setup, R_PAR0_DELAY__setup__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Parallel_printer_port_registers
+ REG_SET__R_PAR1_CONFIG(
+ ioe, R_PAR1_CONFIG__ioe__DEFAULT,
+ iseli, R_PAR1_CONFIG__iseli__DEFAULT,
+ iautofd, R_PAR1_CONFIG__iautofd__DEFAULT,
+ istrb, R_PAR1_CONFIG__istrb__DEFAULT,
+ iinit, R_PAR1_CONFIG__iinit__DEFAULT,
+ iperr, R_PAR1_CONFIG__iperr__DEFAULT,
+ iack, R_PAR1_CONFIG__iack__DEFAULT,
+ ibusy, R_PAR1_CONFIG__ibusy__DEFAULT,
+ ifault, R_PAR1_CONFIG__ifault__DEFAULT,
+ isel, R_PAR1_CONFIG__isel__DEFAULT,
+ ext_mode, R_PAR1_CONFIG__ext_mode__DEFAULT,
+ dma, R_PAR1_CONFIG__dma__DEFAULT,
+ rle_in, R_PAR1_CONFIG__rle_in__DEFAULT,
+ rle_out, R_PAR1_CONFIG__rle_out__DEFAULT,
+ enable, R_PAR1_CONFIG__enable__DEFAULT,
+ force, R_PAR1_CONFIG__force__DEFAULT,
+ ign_ack, R_PAR1_CONFIG__ign_ack__DEFAULT,
+ oe_ack, R_PAR1_CONFIG__oe_ack__DEFAULT,
+ mode, R_PAR1_CONFIG__mode__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Parallel_printer_port_registers
+ REG_SET__R_PAR1_CTRL(
+ ctrl, R_PAR1_CTRL__ctrl__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Parallel_printer_port_registers
+ REG_SET__R_PAR1_CTRL_DATA(
+ peri_int, R_PAR1_CTRL_DATA__peri_int__DEFAULT,
+ oe, R_PAR1_CTRL_DATA__oe__DEFAULT,
+ seli, R_PAR1_CTRL_DATA__seli__DEFAULT,
+ autofd, R_PAR1_CTRL_DATA__autofd__DEFAULT,
+ strb, R_PAR1_CTRL_DATA__strb__DEFAULT,
+ init, R_PAR1_CTRL_DATA__init__DEFAULT,
+ ecp_cmd, R_PAR1_CTRL_DATA__ecp_cmd__DEFAULT,
+ data, R_PAR1_CTRL_DATA__data__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Parallel_printer_port_registers
+ REG_SET__R_PAR1_DELAY(
+ fine_hold, R_PAR1_DELAY__fine_hold__DEFAULT,
+ hold, R_PAR1_DELAY__hold__DEFAULT,
+ fine_strb, R_PAR1_DELAY__fine_strb__DEFAULT,
+ strobe, R_PAR1_DELAY__strobe__DEFAULT,
+ fine_setup, R_PAR1_DELAY__fine_setup__DEFAULT,
+ setup, R_PAR1_DELAY__setup__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_port_configuration_registers
+ REG_SET__R_PORT_PA_DATA(
+ data_out, R_PORT_PA_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_port_configuration_registers
+ REG_SET__R_PORT_PA_DIR(
+ dir7, R_PORT_PA_DIR__dir7__DEFAULT,
+ dir6, R_PORT_PA_DIR__dir6__DEFAULT,
+ dir5, R_PORT_PA_DIR__dir5__DEFAULT,
+ dir4, R_PORT_PA_DIR__dir4__DEFAULT,
+ dir3, R_PORT_PA_DIR__dir3__DEFAULT,
+ dir2, R_PORT_PA_DIR__dir2__DEFAULT,
+ dir1, R_PORT_PA_DIR__dir1__DEFAULT,
+ dir0, R_PORT_PA_DIR__dir0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_port_configuration_registers
+ REG_SET__R_PORT_PA_SET(
+ dir7, R_PORT_PA_SET__dir7__DEFAULT,
+ dir6, R_PORT_PA_SET__dir6__DEFAULT,
+ dir5, R_PORT_PA_SET__dir5__DEFAULT,
+ dir4, R_PORT_PA_SET__dir4__DEFAULT,
+ dir3, R_PORT_PA_SET__dir3__DEFAULT,
+ dir2, R_PORT_PA_SET__dir2__DEFAULT,
+ dir1, R_PORT_PA_SET__dir1__DEFAULT,
+ dir0, R_PORT_PA_SET__dir0__DEFAULT,
+ data_out, R_PORT_PA_SET__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_port_configuration_registers
+ REG_SET__R_PORT_PB_CONFIG(
+ cs7, R_PORT_PB_CONFIG__cs7__DEFAULT,
+ cs6, R_PORT_PB_CONFIG__cs6__DEFAULT,
+ cs5, R_PORT_PB_CONFIG__cs5__DEFAULT,
+ cs4, R_PORT_PB_CONFIG__cs4__DEFAULT,
+ cs3, R_PORT_PB_CONFIG__cs3__DEFAULT,
+ cs2, R_PORT_PB_CONFIG__cs2__DEFAULT,
+ scsi1, R_PORT_PB_CONFIG__scsi1__DEFAULT,
+ scsi0, R_PORT_PB_CONFIG__scsi0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_port_configuration_registers
+ REG_SET__R_PORT_PB_DATA(
+ data_out, R_PORT_PB_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_port_configuration_registers
+ REG_SET__R_PORT_PB_DIR(
+ dir7, R_PORT_PB_DIR__dir7__DEFAULT,
+ dir6, R_PORT_PB_DIR__dir6__DEFAULT,
+ dir5, R_PORT_PB_DIR__dir5__DEFAULT,
+ dir4, R_PORT_PB_DIR__dir4__DEFAULT,
+ dir3, R_PORT_PB_DIR__dir3__DEFAULT,
+ dir2, R_PORT_PB_DIR__dir2__DEFAULT,
+ dir1, R_PORT_PB_DIR__dir1__DEFAULT,
+ dir0, R_PORT_PB_DIR__dir0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_port_configuration_registers
+ REG_SET__R_PORT_PB_I2C(
+ syncser3, R_PORT_PB_I2C__syncser3__DEFAULT,
+ syncser1, R_PORT_PB_I2C__syncser1__DEFAULT,
+ i2c_en, R_PORT_PB_I2C__i2c_en__DEFAULT,
+ i2c_d, R_PORT_PB_I2C__i2c_d__DEFAULT,
+ i2c_clk, R_PORT_PB_I2C__i2c_clk__DEFAULT,
+ i2c_oe_, R_PORT_PB_I2C__i2c_oe___DEFAULT
+ );
+#endif
+
+#if USE_GROUP__General_port_configuration_registers
+ REG_SET__R_PORT_PB_SET(
+ syncser3, R_PORT_PB_SET__syncser3__DEFAULT,
+ syncser1, R_PORT_PB_SET__syncser1__DEFAULT,
+ i2c_en, R_PORT_PB_SET__i2c_en__DEFAULT,
+ i2c_d, R_PORT_PB_SET__i2c_d__DEFAULT,
+ i2c_clk, R_PORT_PB_SET__i2c_clk__DEFAULT,
+ i2c_oe_, R_PORT_PB_SET__i2c_oe___DEFAULT,
+ cs7, R_PORT_PB_SET__cs7__DEFAULT,
+ cs6, R_PORT_PB_SET__cs6__DEFAULT,
+ cs5, R_PORT_PB_SET__cs5__DEFAULT,
+ cs4, R_PORT_PB_SET__cs4__DEFAULT,
+ cs3, R_PORT_PB_SET__cs3__DEFAULT,
+ cs2, R_PORT_PB_SET__cs2__DEFAULT,
+ scsi1, R_PORT_PB_SET__scsi1__DEFAULT,
+ scsi0, R_PORT_PB_SET__scsi0__DEFAULT,
+ dir7, R_PORT_PB_SET__dir7__DEFAULT,
+ dir6, R_PORT_PB_SET__dir6__DEFAULT,
+ dir5, R_PORT_PB_SET__dir5__DEFAULT,
+ dir4, R_PORT_PB_SET__dir4__DEFAULT,
+ dir3, R_PORT_PB_SET__dir3__DEFAULT,
+ dir2, R_PORT_PB_SET__dir2__DEFAULT,
+ dir1, R_PORT_PB_SET__dir1__DEFAULT,
+ dir0, R_PORT_PB_SET__dir0__DEFAULT,
+ data_out, R_PORT_PB_SET__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI0_CMD(
+ asynch_setup, R_SCSI0_CMD__asynch_setup__DEFAULT,
+ command, R_SCSI0_CMD__command__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI0_CMD_DATA(
+ parity_in, R_SCSI0_CMD_DATA__parity_in__DEFAULT,
+ skip, R_SCSI0_CMD_DATA__skip__DEFAULT,
+ clr_status, R_SCSI0_CMD_DATA__clr_status__DEFAULT,
+ asynch_setup, R_SCSI0_CMD_DATA__asynch_setup__DEFAULT,
+ command, R_SCSI0_CMD_DATA__command__DEFAULT,
+ data_out, R_SCSI0_CMD_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI0_CTRL(
+ id_type, R_SCSI0_CTRL__id_type__DEFAULT,
+ sel_timeout, R_SCSI0_CTRL__sel_timeout__DEFAULT,
+ synch_per, R_SCSI0_CTRL__synch_per__DEFAULT,
+ rst, R_SCSI0_CTRL__rst__DEFAULT,
+ atn, R_SCSI0_CTRL__atn__DEFAULT,
+ my_id, R_SCSI0_CTRL__my_id__DEFAULT,
+ target_id, R_SCSI0_CTRL__target_id__DEFAULT,
+ fast_20, R_SCSI0_CTRL__fast_20__DEFAULT,
+ bus_width, R_SCSI0_CTRL__bus_width__DEFAULT,
+ synch, R_SCSI0_CTRL__synch__DEFAULT,
+ enable, R_SCSI0_CTRL__enable__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI0_DATA(
+ data_out, R_SCSI0_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI0_STATUS_CTRL(
+ parity_in, R_SCSI0_STATUS_CTRL__parity_in__DEFAULT,
+ skip, R_SCSI0_STATUS_CTRL__skip__DEFAULT,
+ clr_status, R_SCSI0_STATUS_CTRL__clr_status__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI1_CMD(
+ asynch_setup, R_SCSI1_CMD__asynch_setup__DEFAULT,
+ command, R_SCSI1_CMD__command__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI1_CMD_DATA(
+ parity_in, R_SCSI1_CMD_DATA__parity_in__DEFAULT,
+ skip, R_SCSI1_CMD_DATA__skip__DEFAULT,
+ clr_status, R_SCSI1_CMD_DATA__clr_status__DEFAULT,
+ asynch_setup, R_SCSI1_CMD_DATA__asynch_setup__DEFAULT,
+ command, R_SCSI1_CMD_DATA__command__DEFAULT,
+ data_out, R_SCSI1_CMD_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI1_CTRL(
+ id_type, R_SCSI1_CTRL__id_type__DEFAULT,
+ sel_timeout, R_SCSI1_CTRL__sel_timeout__DEFAULT,
+ synch_per, R_SCSI1_CTRL__synch_per__DEFAULT,
+ rst, R_SCSI1_CTRL__rst__DEFAULT,
+ atn, R_SCSI1_CTRL__atn__DEFAULT,
+ my_id, R_SCSI1_CTRL__my_id__DEFAULT,
+ target_id, R_SCSI1_CTRL__target_id__DEFAULT,
+ fast_20, R_SCSI1_CTRL__fast_20__DEFAULT,
+ bus_width, R_SCSI1_CTRL__bus_width__DEFAULT,
+ synch, R_SCSI1_CTRL__synch__DEFAULT,
+ enable, R_SCSI1_CTRL__enable__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI1_DATA(
+ data_out, R_SCSI1_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__SCSI_registers
+ REG_SET__R_SCSI1_STATUS_CTRL(
+ parity_in, R_SCSI1_STATUS_CTRL__parity_in__DEFAULT,
+ skip, R_SCSI1_STATUS_CTRL__skip__DEFAULT,
+ clr_status, R_SCSI1_STATUS_CTRL__clr_status__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Bus_interface_configuration_registers
+ REG_SET__R_SDRAM_CONFIG(
+ wmm1, R_SDRAM_CONFIG__wmm1__DEFAULT,
+ wmm0, R_SDRAM_CONFIG__wmm0__DEFAULT,
+ sh1, R_SDRAM_CONFIG__sh1__DEFAULT,
+ sh0, R_SDRAM_CONFIG__sh0__DEFAULT,
+ w, R_SDRAM_CONFIG__w__DEFAULT,
+ type1, R_SDRAM_CONFIG__type1__DEFAULT,
+ type0, R_SDRAM_CONFIG__type0__DEFAULT,
+ group_sel, R_SDRAM_CONFIG__group_sel__DEFAULT,
+ ca1, R_SDRAM_CONFIG__ca1__DEFAULT,
+ bank_sel1, R_SDRAM_CONFIG__bank_sel1__DEFAULT,
+ ca0, R_SDRAM_CONFIG__ca0__DEFAULT,
+ bank_sel0, R_SDRAM_CONFIG__bank_sel0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Bus_interface_configuration_registers
+ REG_SET__R_SDRAM_TIMING(
+ sdram, R_SDRAM_TIMING__sdram__DEFAULT,
+ mrs_data, R_SDRAM_TIMING__mrs_data__DEFAULT,
+ ref, R_SDRAM_TIMING__ref__DEFAULT,
+ ddr, R_SDRAM_TIMING__ddr__DEFAULT,
+ clk100, R_SDRAM_TIMING__clk100__DEFAULT,
+ ps, R_SDRAM_TIMING__ps__DEFAULT,
+ cmd, R_SDRAM_TIMING__cmd__DEFAULT,
+ pde, R_SDRAM_TIMING__pde__DEFAULT,
+ rc, R_SDRAM_TIMING__rc__DEFAULT,
+ rp, R_SDRAM_TIMING__rp__DEFAULT,
+ rcd, R_SDRAM_TIMING__rcd__DEFAULT,
+ cl, R_SDRAM_TIMING__cl__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL0_BAUD(
+ tr_baud, R_SERIAL0_BAUD__tr_baud__DEFAULT,
+ rec_baud, R_SERIAL0_BAUD__rec_baud__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL0_CTRL(
+ tr_baud, R_SERIAL0_CTRL__tr_baud__DEFAULT,
+ rec_baud, R_SERIAL0_CTRL__rec_baud__DEFAULT,
+ dma_err, R_SERIAL0_CTRL__dma_err__DEFAULT,
+ rec_enable, R_SERIAL0_CTRL__rec_enable__DEFAULT,
+ rts_, R_SERIAL0_CTRL__rts___DEFAULT,
+ sampling, R_SERIAL0_CTRL__sampling__DEFAULT,
+ rec_stick_par, R_SERIAL0_CTRL__rec_stick_par__DEFAULT,
+ rec_par, R_SERIAL0_CTRL__rec_par__DEFAULT,
+ rec_par_en, R_SERIAL0_CTRL__rec_par_en__DEFAULT,
+ rec_bitnr, R_SERIAL0_CTRL__rec_bitnr__DEFAULT,
+ txd, R_SERIAL0_CTRL__txd__DEFAULT,
+ tr_enable, R_SERIAL0_CTRL__tr_enable__DEFAULT,
+ auto_cts, R_SERIAL0_CTRL__auto_cts__DEFAULT,
+ stop_bits, R_SERIAL0_CTRL__stop_bits__DEFAULT,
+ tr_stick_par, R_SERIAL0_CTRL__tr_stick_par__DEFAULT,
+ tr_par, R_SERIAL0_CTRL__tr_par__DEFAULT,
+ tr_par_en, R_SERIAL0_CTRL__tr_par_en__DEFAULT,
+ tr_bitnr, R_SERIAL0_CTRL__tr_bitnr__DEFAULT,
+ data_out, R_SERIAL0_CTRL__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL0_REC_CTRL(
+ dma_err, R_SERIAL0_REC_CTRL__dma_err__DEFAULT,
+ rec_enable, R_SERIAL0_REC_CTRL__rec_enable__DEFAULT,
+ rts_, R_SERIAL0_REC_CTRL__rts___DEFAULT,
+ sampling, R_SERIAL0_REC_CTRL__sampling__DEFAULT,
+ rec_stick_par, R_SERIAL0_REC_CTRL__rec_stick_par__DEFAULT,
+ rec_par, R_SERIAL0_REC_CTRL__rec_par__DEFAULT,
+ rec_par_en, R_SERIAL0_REC_CTRL__rec_par_en__DEFAULT,
+ rec_bitnr, R_SERIAL0_REC_CTRL__rec_bitnr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL0_TR_CTRL(
+ txd, R_SERIAL0_TR_CTRL__txd__DEFAULT,
+ tr_enable, R_SERIAL0_TR_CTRL__tr_enable__DEFAULT,
+ auto_cts, R_SERIAL0_TR_CTRL__auto_cts__DEFAULT,
+ stop_bits, R_SERIAL0_TR_CTRL__stop_bits__DEFAULT,
+ tr_stick_par, R_SERIAL0_TR_CTRL__tr_stick_par__DEFAULT,
+ tr_par, R_SERIAL0_TR_CTRL__tr_par__DEFAULT,
+ tr_par_en, R_SERIAL0_TR_CTRL__tr_par_en__DEFAULT,
+ tr_bitnr, R_SERIAL0_TR_CTRL__tr_bitnr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL0_TR_DATA(
+ data_out, R_SERIAL0_TR_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL0_XOFF(
+ tx_stop, R_SERIAL0_XOFF__tx_stop__DEFAULT,
+ auto_xoff, R_SERIAL0_XOFF__auto_xoff__DEFAULT,
+ xoff_char, R_SERIAL0_XOFF__xoff_char__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL1_BAUD(
+ tr_baud, R_SERIAL1_BAUD__tr_baud__DEFAULT,
+ rec_baud, R_SERIAL1_BAUD__rec_baud__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL1_CTRL(
+ tr_baud, R_SERIAL1_CTRL__tr_baud__DEFAULT,
+ rec_baud, R_SERIAL1_CTRL__rec_baud__DEFAULT,
+ dma_err, R_SERIAL1_CTRL__dma_err__DEFAULT,
+ rec_enable, R_SERIAL1_CTRL__rec_enable__DEFAULT,
+ rts_, R_SERIAL1_CTRL__rts___DEFAULT,
+ sampling, R_SERIAL1_CTRL__sampling__DEFAULT,
+ rec_stick_par, R_SERIAL1_CTRL__rec_stick_par__DEFAULT,
+ rec_par, R_SERIAL1_CTRL__rec_par__DEFAULT,
+ rec_par_en, R_SERIAL1_CTRL__rec_par_en__DEFAULT,
+ rec_bitnr, R_SERIAL1_CTRL__rec_bitnr__DEFAULT,
+ txd, R_SERIAL1_CTRL__txd__DEFAULT,
+ tr_enable, R_SERIAL1_CTRL__tr_enable__DEFAULT,
+ auto_cts, R_SERIAL1_CTRL__auto_cts__DEFAULT,
+ stop_bits, R_SERIAL1_CTRL__stop_bits__DEFAULT,
+ tr_stick_par, R_SERIAL1_CTRL__tr_stick_par__DEFAULT,
+ tr_par, R_SERIAL1_CTRL__tr_par__DEFAULT,
+ tr_par_en, R_SERIAL1_CTRL__tr_par_en__DEFAULT,
+ tr_bitnr, R_SERIAL1_CTRL__tr_bitnr__DEFAULT,
+ data_out, R_SERIAL1_CTRL__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL1_REC_CTRL(
+ dma_err, R_SERIAL1_REC_CTRL__dma_err__DEFAULT,
+ rec_enable, R_SERIAL1_REC_CTRL__rec_enable__DEFAULT,
+ rts_, R_SERIAL1_REC_CTRL__rts___DEFAULT,
+ sampling, R_SERIAL1_REC_CTRL__sampling__DEFAULT,
+ rec_stick_par, R_SERIAL1_REC_CTRL__rec_stick_par__DEFAULT,
+ rec_par, R_SERIAL1_REC_CTRL__rec_par__DEFAULT,
+ rec_par_en, R_SERIAL1_REC_CTRL__rec_par_en__DEFAULT,
+ rec_bitnr, R_SERIAL1_REC_CTRL__rec_bitnr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL1_TR_CTRL(
+ txd, R_SERIAL1_TR_CTRL__txd__DEFAULT,
+ tr_enable, R_SERIAL1_TR_CTRL__tr_enable__DEFAULT,
+ auto_cts, R_SERIAL1_TR_CTRL__auto_cts__DEFAULT,
+ stop_bits, R_SERIAL1_TR_CTRL__stop_bits__DEFAULT,
+ tr_stick_par, R_SERIAL1_TR_CTRL__tr_stick_par__DEFAULT,
+ tr_par, R_SERIAL1_TR_CTRL__tr_par__DEFAULT,
+ tr_par_en, R_SERIAL1_TR_CTRL__tr_par_en__DEFAULT,
+ tr_bitnr, R_SERIAL1_TR_CTRL__tr_bitnr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL1_TR_DATA(
+ data_out, R_SERIAL1_TR_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL1_XOFF(
+ tx_stop, R_SERIAL1_XOFF__tx_stop__DEFAULT,
+ auto_xoff, R_SERIAL1_XOFF__auto_xoff__DEFAULT,
+ xoff_char, R_SERIAL1_XOFF__xoff_char__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL2_BAUD(
+ tr_baud, R_SERIAL2_BAUD__tr_baud__DEFAULT,
+ rec_baud, R_SERIAL2_BAUD__rec_baud__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL2_CTRL(
+ tr_baud, R_SERIAL2_CTRL__tr_baud__DEFAULT,
+ rec_baud, R_SERIAL2_CTRL__rec_baud__DEFAULT,
+ dma_err, R_SERIAL2_CTRL__dma_err__DEFAULT,
+ rec_enable, R_SERIAL2_CTRL__rec_enable__DEFAULT,
+ rts_, R_SERIAL2_CTRL__rts___DEFAULT,
+ sampling, R_SERIAL2_CTRL__sampling__DEFAULT,
+ rec_stick_par, R_SERIAL2_CTRL__rec_stick_par__DEFAULT,
+ rec_par, R_SERIAL2_CTRL__rec_par__DEFAULT,
+ rec_par_en, R_SERIAL2_CTRL__rec_par_en__DEFAULT,
+ rec_bitnr, R_SERIAL2_CTRL__rec_bitnr__DEFAULT,
+ txd, R_SERIAL2_CTRL__txd__DEFAULT,
+ tr_enable, R_SERIAL2_CTRL__tr_enable__DEFAULT,
+ auto_cts, R_SERIAL2_CTRL__auto_cts__DEFAULT,
+ stop_bits, R_SERIAL2_CTRL__stop_bits__DEFAULT,
+ tr_stick_par, R_SERIAL2_CTRL__tr_stick_par__DEFAULT,
+ tr_par, R_SERIAL2_CTRL__tr_par__DEFAULT,
+ tr_par_en, R_SERIAL2_CTRL__tr_par_en__DEFAULT,
+ tr_bitnr, R_SERIAL2_CTRL__tr_bitnr__DEFAULT,
+ data_out, R_SERIAL2_CTRL__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL2_REC_CTRL(
+ dma_err, R_SERIAL2_REC_CTRL__dma_err__DEFAULT,
+ rec_enable, R_SERIAL2_REC_CTRL__rec_enable__DEFAULT,
+ rts_, R_SERIAL2_REC_CTRL__rts___DEFAULT,
+ sampling, R_SERIAL2_REC_CTRL__sampling__DEFAULT,
+ rec_stick_par, R_SERIAL2_REC_CTRL__rec_stick_par__DEFAULT,
+ rec_par, R_SERIAL2_REC_CTRL__rec_par__DEFAULT,
+ rec_par_en, R_SERIAL2_REC_CTRL__rec_par_en__DEFAULT,
+ rec_bitnr, R_SERIAL2_REC_CTRL__rec_bitnr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL2_TR_CTRL(
+ txd, R_SERIAL2_TR_CTRL__txd__DEFAULT,
+ tr_enable, R_SERIAL2_TR_CTRL__tr_enable__DEFAULT,
+ auto_cts, R_SERIAL2_TR_CTRL__auto_cts__DEFAULT,
+ stop_bits, R_SERIAL2_TR_CTRL__stop_bits__DEFAULT,
+ tr_stick_par, R_SERIAL2_TR_CTRL__tr_stick_par__DEFAULT,
+ tr_par, R_SERIAL2_TR_CTRL__tr_par__DEFAULT,
+ tr_par_en, R_SERIAL2_TR_CTRL__tr_par_en__DEFAULT,
+ tr_bitnr, R_SERIAL2_TR_CTRL__tr_bitnr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL2_TR_DATA(
+ data_out, R_SERIAL2_TR_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL2_XOFF(
+ tx_stop, R_SERIAL2_XOFF__tx_stop__DEFAULT,
+ auto_xoff, R_SERIAL2_XOFF__auto_xoff__DEFAULT,
+ xoff_char, R_SERIAL2_XOFF__xoff_char__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL3_BAUD(
+ tr_baud, R_SERIAL3_BAUD__tr_baud__DEFAULT,
+ rec_baud, R_SERIAL3_BAUD__rec_baud__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL3_CTRL(
+ tr_baud, R_SERIAL3_CTRL__tr_baud__DEFAULT,
+ rec_baud, R_SERIAL3_CTRL__rec_baud__DEFAULT,
+ dma_err, R_SERIAL3_CTRL__dma_err__DEFAULT,
+ rec_enable, R_SERIAL3_CTRL__rec_enable__DEFAULT,
+ rts_, R_SERIAL3_CTRL__rts___DEFAULT,
+ sampling, R_SERIAL3_CTRL__sampling__DEFAULT,
+ rec_stick_par, R_SERIAL3_CTRL__rec_stick_par__DEFAULT,
+ rec_par, R_SERIAL3_CTRL__rec_par__DEFAULT,
+ rec_par_en, R_SERIAL3_CTRL__rec_par_en__DEFAULT,
+ rec_bitnr, R_SERIAL3_CTRL__rec_bitnr__DEFAULT,
+ txd, R_SERIAL3_CTRL__txd__DEFAULT,
+ tr_enable, R_SERIAL3_CTRL__tr_enable__DEFAULT,
+ auto_cts, R_SERIAL3_CTRL__auto_cts__DEFAULT,
+ stop_bits, R_SERIAL3_CTRL__stop_bits__DEFAULT,
+ tr_stick_par, R_SERIAL3_CTRL__tr_stick_par__DEFAULT,
+ tr_par, R_SERIAL3_CTRL__tr_par__DEFAULT,
+ tr_par_en, R_SERIAL3_CTRL__tr_par_en__DEFAULT,
+ tr_bitnr, R_SERIAL3_CTRL__tr_bitnr__DEFAULT,
+ data_out, R_SERIAL3_CTRL__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL3_REC_CTRL(
+ dma_err, R_SERIAL3_REC_CTRL__dma_err__DEFAULT,
+ rec_enable, R_SERIAL3_REC_CTRL__rec_enable__DEFAULT,
+ rts_, R_SERIAL3_REC_CTRL__rts___DEFAULT,
+ sampling, R_SERIAL3_REC_CTRL__sampling__DEFAULT,
+ rec_stick_par, R_SERIAL3_REC_CTRL__rec_stick_par__DEFAULT,
+ rec_par, R_SERIAL3_REC_CTRL__rec_par__DEFAULT,
+ rec_par_en, R_SERIAL3_REC_CTRL__rec_par_en__DEFAULT,
+ rec_bitnr, R_SERIAL3_REC_CTRL__rec_bitnr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL3_TR_CTRL(
+ txd, R_SERIAL3_TR_CTRL__txd__DEFAULT,
+ tr_enable, R_SERIAL3_TR_CTRL__tr_enable__DEFAULT,
+ auto_cts, R_SERIAL3_TR_CTRL__auto_cts__DEFAULT,
+ stop_bits, R_SERIAL3_TR_CTRL__stop_bits__DEFAULT,
+ tr_stick_par, R_SERIAL3_TR_CTRL__tr_stick_par__DEFAULT,
+ tr_par, R_SERIAL3_TR_CTRL__tr_par__DEFAULT,
+ tr_par_en, R_SERIAL3_TR_CTRL__tr_par_en__DEFAULT,
+ tr_bitnr, R_SERIAL3_TR_CTRL__tr_bitnr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL3_TR_DATA(
+ data_out, R_SERIAL3_TR_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Serial_port_registers
+ REG_SET__R_SERIAL3_XOFF(
+ tx_stop, R_SERIAL3_XOFF__tx_stop__DEFAULT,
+ auto_xoff, R_SERIAL3_XOFF__auto_xoff__DEFAULT,
+ xoff_char, R_SERIAL3_XOFF__xoff_char__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Timer_registers
+ REG_SET__R_SERIAL_PRESCALE(
+ ser_presc, R_SERIAL_PRESCALE__ser_presc__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__DMA_registers
+ REG_SET__R_SET_EOP(
+ ch9_eop, R_SET_EOP__ch9_eop__DEFAULT,
+ ch7_eop, R_SET_EOP__ch7_eop__DEFAULT,
+ ch5_eop, R_SET_EOP__ch5_eop__DEFAULT,
+ ch3_eop, R_SET_EOP__ch3_eop__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Shared_RAM_interface_registers
+ REG_SET__R_SHARED_RAM_ADDR(
+ base_addr, R_SHARED_RAM_ADDR__base_addr__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Shared_RAM_interface_registers
+ REG_SET__R_SHARED_RAM_CONFIG(
+ width, R_SHARED_RAM_CONFIG__width__DEFAULT,
+ enable, R_SHARED_RAM_CONFIG__enable__DEFAULT,
+ pint, R_SHARED_RAM_CONFIG__pint__DEFAULT,
+ clri, R_SHARED_RAM_CONFIG__clri__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Test_mode_registers
+ REG_SET__R_SINGLE_STEP(
+ single_step, R_SINGLE_STEP__single_step__DEFAULT,
+ step_wr, R_SINGLE_STEP__step_wr__DEFAULT,
+ step_rd, R_SINGLE_STEP__step_rd__DEFAULT,
+ step_fetch, R_SINGLE_STEP__step_fetch__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+ REG_SET__R_SYNC_SERIAL1_CTRL(
+ tr_baud, R_SYNC_SERIAL1_CTRL__tr_baud__DEFAULT,
+ dma_enable, R_SYNC_SERIAL1_CTRL__dma_enable__DEFAULT,
+ mode, R_SYNC_SERIAL1_CTRL__mode__DEFAULT,
+ error, R_SYNC_SERIAL1_CTRL__error__DEFAULT,
+ rec_enable, R_SYNC_SERIAL1_CTRL__rec_enable__DEFAULT,
+ f_synctype, R_SYNC_SERIAL1_CTRL__f_synctype__DEFAULT,
+ f_syncsize, R_SYNC_SERIAL1_CTRL__f_syncsize__DEFAULT,
+ f_sync, R_SYNC_SERIAL1_CTRL__f_sync__DEFAULT,
+ clk_mode, R_SYNC_SERIAL1_CTRL__clk_mode__DEFAULT,
+ clk_halt, R_SYNC_SERIAL1_CTRL__clk_halt__DEFAULT,
+ bitorder, R_SYNC_SERIAL1_CTRL__bitorder__DEFAULT,
+ tr_enable, R_SYNC_SERIAL1_CTRL__tr_enable__DEFAULT,
+ wordsize, R_SYNC_SERIAL1_CTRL__wordsize__DEFAULT,
+ buf_empty, R_SYNC_SERIAL1_CTRL__buf_empty__DEFAULT,
+ buf_full, R_SYNC_SERIAL1_CTRL__buf_full__DEFAULT,
+ flow_ctrl, R_SYNC_SERIAL1_CTRL__flow_ctrl__DEFAULT,
+ clk_polarity, R_SYNC_SERIAL1_CTRL__clk_polarity__DEFAULT,
+ frame_polarity, R_SYNC_SERIAL1_CTRL__frame_polarity__DEFAULT,
+ status_polarity, R_SYNC_SERIAL1_CTRL__status_polarity__DEFAULT,
+ clk_driver, R_SYNC_SERIAL1_CTRL__clk_driver__DEFAULT,
+ frame_driver, R_SYNC_SERIAL1_CTRL__frame_driver__DEFAULT,
+ status_driver, R_SYNC_SERIAL1_CTRL__status_driver__DEFAULT,
+ def_out0, R_SYNC_SERIAL1_CTRL__def_out0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+ REG_SET__R_SYNC_SERIAL1_TR_BYTE(
+ data_out, R_SYNC_SERIAL1_TR_BYTE__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+ REG_SET__R_SYNC_SERIAL1_TR_DATA(
+ data_out, R_SYNC_SERIAL1_TR_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+ REG_SET__R_SYNC_SERIAL1_TR_WORD(
+ data_out, R_SYNC_SERIAL1_TR_WORD__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+ REG_SET__R_SYNC_SERIAL3_CTRL(
+ tr_baud, R_SYNC_SERIAL3_CTRL__tr_baud__DEFAULT,
+ dma_enable, R_SYNC_SERIAL3_CTRL__dma_enable__DEFAULT,
+ mode, R_SYNC_SERIAL3_CTRL__mode__DEFAULT,
+ error, R_SYNC_SERIAL3_CTRL__error__DEFAULT,
+ rec_enable, R_SYNC_SERIAL3_CTRL__rec_enable__DEFAULT,
+ f_synctype, R_SYNC_SERIAL3_CTRL__f_synctype__DEFAULT,
+ f_syncsize, R_SYNC_SERIAL3_CTRL__f_syncsize__DEFAULT,
+ f_sync, R_SYNC_SERIAL3_CTRL__f_sync__DEFAULT,
+ clk_mode, R_SYNC_SERIAL3_CTRL__clk_mode__DEFAULT,
+ clk_halt, R_SYNC_SERIAL3_CTRL__clk_halt__DEFAULT,
+ bitorder, R_SYNC_SERIAL3_CTRL__bitorder__DEFAULT,
+ tr_enable, R_SYNC_SERIAL3_CTRL__tr_enable__DEFAULT,
+ wordsize, R_SYNC_SERIAL3_CTRL__wordsize__DEFAULT,
+ buf_empty, R_SYNC_SERIAL3_CTRL__buf_empty__DEFAULT,
+ buf_full, R_SYNC_SERIAL3_CTRL__buf_full__DEFAULT,
+ flow_ctrl, R_SYNC_SERIAL3_CTRL__flow_ctrl__DEFAULT,
+ clk_polarity, R_SYNC_SERIAL3_CTRL__clk_polarity__DEFAULT,
+ frame_polarity, R_SYNC_SERIAL3_CTRL__frame_polarity__DEFAULT,
+ status_polarity, R_SYNC_SERIAL3_CTRL__status_polarity__DEFAULT,
+ clk_driver, R_SYNC_SERIAL3_CTRL__clk_driver__DEFAULT,
+ frame_driver, R_SYNC_SERIAL3_CTRL__frame_driver__DEFAULT,
+ status_driver, R_SYNC_SERIAL3_CTRL__status_driver__DEFAULT,
+ def_out0, R_SYNC_SERIAL3_CTRL__def_out0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+ REG_SET__R_SYNC_SERIAL3_TR_BYTE(
+ data_out, R_SYNC_SERIAL3_TR_BYTE__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+ REG_SET__R_SYNC_SERIAL3_TR_DATA(
+ data_out, R_SYNC_SERIAL3_TR_DATA__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+ REG_SET__R_SYNC_SERIAL3_TR_WORD(
+ data_out, R_SYNC_SERIAL3_TR_WORD__data_out__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Timer_registers
+ REG_SET__R_SYNC_SERIAL_PRESCALE(
+ clk_sel_u3, R_SYNC_SERIAL_PRESCALE__clk_sel_u3__DEFAULT,
+ word_stb_sel_u3, R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__DEFAULT,
+ clk_sel_u1, R_SYNC_SERIAL_PRESCALE__clk_sel_u1__DEFAULT,
+ word_stb_sel_u1, R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__DEFAULT,
+ prescaler, R_SYNC_SERIAL_PRESCALE__prescaler__DEFAULT,
+ warp_mode, R_SYNC_SERIAL_PRESCALE__warp_mode__DEFAULT,
+ frame_rate, R_SYNC_SERIAL_PRESCALE__frame_rate__DEFAULT,
+ word_rate, R_SYNC_SERIAL_PRESCALE__word_rate__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Test_mode_registers
+ REG_SET__R_TEST_MODE(
+ single_step, R_TEST_MODE__single_step__DEFAULT,
+ step_wr, R_TEST_MODE__step_wr__DEFAULT,
+ step_rd, R_TEST_MODE__step_rd__DEFAULT,
+ step_fetch, R_TEST_MODE__step_fetch__DEFAULT,
+ mmu_test, R_TEST_MODE__mmu_test__DEFAULT,
+ usb_test, R_TEST_MODE__usb_test__DEFAULT,
+ scsi_timer_test, R_TEST_MODE__scsi_timer_test__DEFAULT,
+ backoff, R_TEST_MODE__backoff__DEFAULT,
+ snmp_test, R_TEST_MODE__snmp_test__DEFAULT,
+ snmp_inc, R_TEST_MODE__snmp_inc__DEFAULT,
+ ser_loop, R_TEST_MODE__ser_loop__DEFAULT,
+ baudrate, R_TEST_MODE__baudrate__DEFAULT,
+ timer, R_TEST_MODE__timer__DEFAULT,
+ cache_test, R_TEST_MODE__cache_test__DEFAULT,
+ tag_test, R_TEST_MODE__tag_test__DEFAULT,
+ cache_enable, R_TEST_MODE__cache_enable__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Timer_registers
+ REG_SET__R_TIMER_CTRL(
+ timerdiv1, R_TIMER_CTRL__timerdiv1__DEFAULT,
+ timerdiv0, R_TIMER_CTRL__timerdiv0__DEFAULT,
+ presc_timer1, R_TIMER_CTRL__presc_timer1__DEFAULT,
+ i1, R_TIMER_CTRL__i1__DEFAULT,
+ tm1, R_TIMER_CTRL__tm1__DEFAULT,
+ clksel1, R_TIMER_CTRL__clksel1__DEFAULT,
+ presc_ext, R_TIMER_CTRL__presc_ext__DEFAULT,
+ i0, R_TIMER_CTRL__i0__DEFAULT,
+ tm0, R_TIMER_CTRL__tm0__DEFAULT,
+ clksel0, R_TIMER_CTRL__clksel0__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Timer_registers
+ REG_SET__R_TIMER_PRESCALE(
+ tim_presc, R_TIMER_PRESCALE__tim_presc__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__USB_interface_control_registers
+ REG_SET__R_USB_IRQ_MASK_CLR(
+ iso_eof, R_USB_IRQ_MASK_CLR__iso_eof__DEFAULT,
+ intr_eof, R_USB_IRQ_MASK_CLR__intr_eof__DEFAULT,
+ iso_eot, R_USB_IRQ_MASK_CLR__iso_eot__DEFAULT,
+ intr_eot, R_USB_IRQ_MASK_CLR__intr_eot__DEFAULT,
+ ctl_eot, R_USB_IRQ_MASK_CLR__ctl_eot__DEFAULT,
+ bulk_eot, R_USB_IRQ_MASK_CLR__bulk_eot__DEFAULT,
+ epid_attn, R_USB_IRQ_MASK_CLR__epid_attn__DEFAULT,
+ sof, R_USB_IRQ_MASK_CLR__sof__DEFAULT,
+ port_status, R_USB_IRQ_MASK_CLR__port_status__DEFAULT,
+ ctl_status, R_USB_IRQ_MASK_CLR__ctl_status__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__USB_interface_control_registers
+ REG_SET__R_USB_IRQ_MASK_CLR_DEV(
+ out_eot, R_USB_IRQ_MASK_CLR_DEV__out_eot__DEFAULT,
+ ep3_in_eot, R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__DEFAULT,
+ ep2_in_eot, R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__DEFAULT,
+ ep1_in_eot, R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__DEFAULT,
+ ep0_in_eot, R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__DEFAULT,
+ epid_attn, R_USB_IRQ_MASK_CLR_DEV__epid_attn__DEFAULT,
+ sof, R_USB_IRQ_MASK_CLR_DEV__sof__DEFAULT,
+ port_status, R_USB_IRQ_MASK_CLR_DEV__port_status__DEFAULT,
+ ctl_status, R_USB_IRQ_MASK_CLR_DEV__ctl_status__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__USB_interface_control_registers
+ REG_SET__R_USB_IRQ_MASK_SET(
+ iso_eof, R_USB_IRQ_MASK_SET__iso_eof__DEFAULT,
+ intr_eof, R_USB_IRQ_MASK_SET__intr_eof__DEFAULT,
+ iso_eot, R_USB_IRQ_MASK_SET__iso_eot__DEFAULT,
+ intr_eot, R_USB_IRQ_MASK_SET__intr_eot__DEFAULT,
+ ctl_eot, R_USB_IRQ_MASK_SET__ctl_eot__DEFAULT,
+ bulk_eot, R_USB_IRQ_MASK_SET__bulk_eot__DEFAULT,
+ epid_attn, R_USB_IRQ_MASK_SET__epid_attn__DEFAULT,
+ sof, R_USB_IRQ_MASK_SET__sof__DEFAULT,
+ port_status, R_USB_IRQ_MASK_SET__port_status__DEFAULT,
+ ctl_status, R_USB_IRQ_MASK_SET__ctl_status__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__USB_interface_control_registers
+ REG_SET__R_USB_IRQ_MASK_SET_DEV(
+ out_eot, R_USB_IRQ_MASK_SET_DEV__out_eot__DEFAULT,
+ ep3_in_eot, R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__DEFAULT,
+ ep2_in_eot, R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__DEFAULT,
+ ep1_in_eot, R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__DEFAULT,
+ ep0_in_eot, R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__DEFAULT,
+ epid_attn, R_USB_IRQ_MASK_SET_DEV__epid_attn__DEFAULT,
+ sof, R_USB_IRQ_MASK_SET_DEV__sof__DEFAULT,
+ port_status, R_USB_IRQ_MASK_SET_DEV__port_status__DEFAULT,
+ ctl_status, R_USB_IRQ_MASK_SET_DEV__ctl_status__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__USB_interface_control_registers
+ REG_SET__R_USB_PORT1_DISABLE(
+ disable, R_USB_PORT1_DISABLE__disable__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__USB_interface_control_registers
+ REG_SET__R_USB_PORT2_DISABLE(
+ disable, R_USB_PORT2_DISABLE__disable__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ REG_SET__R_VECT_MASK_CLR(
+ usb, R_VECT_MASK_CLR__usb__DEFAULT,
+ dma9, R_VECT_MASK_CLR__dma9__DEFAULT,
+ dma8, R_VECT_MASK_CLR__dma8__DEFAULT,
+ dma7, R_VECT_MASK_CLR__dma7__DEFAULT,
+ dma6, R_VECT_MASK_CLR__dma6__DEFAULT,
+ dma5, R_VECT_MASK_CLR__dma5__DEFAULT,
+ dma4, R_VECT_MASK_CLR__dma4__DEFAULT,
+ dma3, R_VECT_MASK_CLR__dma3__DEFAULT,
+ dma2, R_VECT_MASK_CLR__dma2__DEFAULT,
+ dma1, R_VECT_MASK_CLR__dma1__DEFAULT,
+ dma0, R_VECT_MASK_CLR__dma0__DEFAULT,
+ ext_dma1, R_VECT_MASK_CLR__ext_dma1__DEFAULT,
+ ext_dma0, R_VECT_MASK_CLR__ext_dma0__DEFAULT,
+ pa, R_VECT_MASK_CLR__pa__DEFAULT,
+ irq_intnr, R_VECT_MASK_CLR__irq_intnr__DEFAULT,
+ sw, R_VECT_MASK_CLR__sw__DEFAULT,
+ serial, R_VECT_MASK_CLR__serial__DEFAULT,
+ snmp, R_VECT_MASK_CLR__snmp__DEFAULT,
+ network, R_VECT_MASK_CLR__network__DEFAULT,
+ scsi1, R_VECT_MASK_CLR__scsi1__DEFAULT,
+ scsi0, R_VECT_MASK_CLR__scsi0__DEFAULT,
+ timer1, R_VECT_MASK_CLR__timer1__DEFAULT,
+ timer0, R_VECT_MASK_CLR__timer0__DEFAULT,
+ nmi, R_VECT_MASK_CLR__nmi__DEFAULT,
+ some, R_VECT_MASK_CLR__some__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ REG_SET__R_VECT_MASK_SET(
+ usb, R_VECT_MASK_SET__usb__DEFAULT,
+ dma9, R_VECT_MASK_SET__dma9__DEFAULT,
+ dma8, R_VECT_MASK_SET__dma8__DEFAULT,
+ dma7, R_VECT_MASK_SET__dma7__DEFAULT,
+ dma6, R_VECT_MASK_SET__dma6__DEFAULT,
+ dma5, R_VECT_MASK_SET__dma5__DEFAULT,
+ dma4, R_VECT_MASK_SET__dma4__DEFAULT,
+ dma3, R_VECT_MASK_SET__dma3__DEFAULT,
+ dma2, R_VECT_MASK_SET__dma2__DEFAULT,
+ dma1, R_VECT_MASK_SET__dma1__DEFAULT,
+ dma0, R_VECT_MASK_SET__dma0__DEFAULT,
+ ext_dma1, R_VECT_MASK_SET__ext_dma1__DEFAULT,
+ ext_dma0, R_VECT_MASK_SET__ext_dma0__DEFAULT,
+ pa, R_VECT_MASK_SET__pa__DEFAULT,
+ irq_intnr, R_VECT_MASK_SET__irq_intnr__DEFAULT,
+ sw, R_VECT_MASK_SET__sw__DEFAULT,
+ serial, R_VECT_MASK_SET__serial__DEFAULT,
+ snmp, R_VECT_MASK_SET__snmp__DEFAULT,
+ network, R_VECT_MASK_SET__network__DEFAULT,
+ scsi1, R_VECT_MASK_SET__scsi1__DEFAULT,
+ scsi0, R_VECT_MASK_SET__scsi0__DEFAULT,
+ timer1, R_VECT_MASK_SET__timer1__DEFAULT,
+ timer0, R_VECT_MASK_SET__timer0__DEFAULT,
+ nmi, R_VECT_MASK_SET__nmi__DEFAULT,
+ some, R_VECT_MASK_SET__some__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Bus_interface_configuration_registers
+ REG_SET__R_WAITSTATES(
+ pcs4_7_zw, R_WAITSTATES__pcs4_7_zw__DEFAULT,
+ pcs4_7_ew, R_WAITSTATES__pcs4_7_ew__DEFAULT,
+ pcs4_7_lw, R_WAITSTATES__pcs4_7_lw__DEFAULT,
+ pcs0_3_zw, R_WAITSTATES__pcs0_3_zw__DEFAULT,
+ pcs0_3_ew, R_WAITSTATES__pcs0_3_ew__DEFAULT,
+ pcs0_3_lw, R_WAITSTATES__pcs0_3_lw__DEFAULT,
+ sram_zw, R_WAITSTATES__sram_zw__DEFAULT,
+ sram_ew, R_WAITSTATES__sram_ew__DEFAULT,
+ sram_lw, R_WAITSTATES__sram_lw__DEFAULT,
+ flash_zw, R_WAITSTATES__flash_zw__DEFAULT,
+ flash_ew, R_WAITSTATES__flash_ew__DEFAULT,
+ flash_lw, R_WAITSTATES__flash_lw__DEFAULT
+ );
+#endif
+
+#if USE_GROUP__Timer_registers
+ REG_SET__R_WATCHDOG(
+ key, R_WATCHDOG__key__DEFAULT,
+ enable, R_WATCHDOG__enable__DEFAULT
+ );
+#endif
+#endif
+} /* init_shadow__hwregs */
diff --git a/package/etrax-tools/src/e100boot/cbl/src/hwregs.h b/package/etrax-tools/src/e100boot/cbl/src/hwregs.h
new file mode 100644
index 000000000..9210a9faa
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/hwregs.h
@@ -0,0 +1,44822 @@
+/*!**********************************************************************
+*!
+*! FILE NAME: hwregs.h
+*!
+*! DESCRIPTION: Interface to shadow registers.
+*!
+*! FUNCTIONS: none
+*!
+*! NOTE: This file is automatically generated, do _not_ edit.
+*! Created: Thu Oct 3 01:21:27 2002
+*! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp
+*! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168
+*! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3
+*!
+*! MACROS: REG_GET
+*! REG_IGET
+*! REG_VGET
+*! REG_SET
+*! REG_ISET
+*! REG_VSET
+*! REG_SET_VAL
+*! REG_SET__register-name (one for each register)
+*! REG_SET__register-name__SHADOW (one for each register)
+*! REG_MASK__register-name (one for each register)
+*! REG_VAL__register-name (one for each register)
+*! REG_EQL
+*! REG_IEQL
+*! REG_VEQL
+*! REG_VAL
+*! REG_CHK_VAL
+*! REG_RD
+*! REG_IRD
+*! REG_WR
+*! REG_IWR
+*! REG_ADDR
+*! REG_BITNR
+*!
+*!----------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! Apr 01 1998 Jan Bengtsson Initial version
+*! Oct 01 2002 Hans-Peter Nilsson Large mechanical changes to correct
+*! use of the ## operator.
+*!----------------------------------------------------------------------
+*!
+*! (C) Copyright 1998, 2002 Axis Communications AB, LUND, SWEDEN
+*!
+*!**********************************************************************/
+/* %Z% %M% %I% %G% */
+
+#ifndef __HWREGS_H__
+#define __HWREGS_H__
+
+/********************** INCLUDE FILES SECTION **************************/
+#ifndef __ASSEMBLER__
+#include "compiler.h"
+#include "debug.h"
+#endif /* __ASSEMBLER__ */
+
+#include "project.h"
+#include "hwregs_def.h"
+
+#ifndef __ASSEMBLER__
+
+#ifndef __REG_GENERAL_1_H__
+#define __REG_GENERAL_1_H__
+
+/*
+** This part of hwregs.h is common to all shadow
+** register modules, and should therefore only be included once to
+** avoid macro redefinitions.
+*/
+
+/* REG_DEBUG is by default controlled by DEBUG from debug.h. */
+#ifndef REG_DEBUG
+#ifdef DEBUG
+#define REG_DEBUG 1
+#else
+#define REG_DEBUG 0
+#endif /* DEBUG */
+#endif /* REG_DEBUG */
+
+#endif /* __REG_GENERAL_1_H__ */
+
+#endif /* __ASSEMBLER__ */
+
+/********************** TYPE DEFINITION SECTION ************************/
+#ifndef __ASSEMBLER__
+
+#ifndef REG_NO_SHADOW
+
+/* Only write only registers need a shadow register. */
+
+typedef struct {
+#if USE_GROUP__Bus_interface_configuration_registers
+ byte R_WAITSTATES[4];
+ byte R_BUS_CONFIG[4];
+ byte R_DRAM_TIMING[4];
+ byte R_DRAM_CONFIG[4];
+#endif
+#if USE_GROUP__External_DMA_registers
+ byte R_EXT_DMA_0_CMD[4];
+ byte R_EXT_DMA_0_ADDR[4];
+ byte R_EXT_DMA_1_CMD[4];
+ byte R_EXT_DMA_1_ADDR[4];
+#endif
+#if USE_GROUP__Timer_registers
+ byte R_TIMER_CTRL[4];
+ byte R_WATCHDOG[4];
+#endif
+#if USE_GROUP__General_config_registers
+ byte R_GEN_CONFIG[4];
+#endif
+#if USE_GROUP__General_port_configuration_registers
+ byte R_PORT_PA_SET[4];
+#endif
+#if USE_GROUP__General_config_registers
+ byte R_GEN_CONFIG_II[4];
+#endif
+#if USE_GROUP__General_port_configuration_registers
+ byte R_PORT_PB_SET[4];
+#endif
+#if USE_GROUP__DMA_registers
+ byte R_SET_EOP[4];
+#endif
+#if USE_GROUP__ATA_interface_registers || \
+ USE_GROUP__Parallel_printer_port_registers || \
+ USE_GROUP__SCSI_registers || \
+ USE_GROUP__Shared_RAM_interface_registers
+ byte R_ATA_CTRL_DATA[4];
+ byte R_ATA_CONFIG[4];
+#endif
+#if USE_GROUP__Parallel_printer_port_registers
+ byte R_PAR0_DELAY[4];
+#endif
+#if USE_GROUP__Parallel_printer_port_registers || \
+ USE_GROUP__SCSI_registers || \
+ USE_GROUP__USB_interface_control_registers
+ byte R_PAR1_CTRL_DATA[4];
+#endif
+#if USE_GROUP__Parallel_printer_port_registers || \
+ USE_GROUP__SCSI_registers
+ byte R_PAR1_CONFIG[4];
+#endif
+#if USE_GROUP__Parallel_printer_port_registers
+ byte R_PAR1_DELAY[4];
+#endif
+#if USE_GROUP__Serial_port_registers
+ byte R_ALT_SER_BAUDRATE[4];
+ byte R_SERIAL0_CTRL[4];
+ byte R_SERIAL0_XOFF[4];
+#endif
+#if USE_GROUP__Serial_port_registers || \
+ USE_GROUP__Syncrounous_serial_port_registers || \
+ USE_GROUP__USB_interface_control_registers
+ byte R_SERIAL1_CTRL[4];
+#endif
+#if USE_GROUP__Serial_port_registers || \
+ USE_GROUP__Syncrounous_serial_port_registers
+ byte R_SERIAL1_XOFF[4];
+#endif
+#if USE_GROUP__Serial_port_registers
+ byte R_SERIAL2_CTRL[4];
+ byte R_SERIAL2_XOFF[4];
+#endif
+#if USE_GROUP__Serial_port_registers || \
+ USE_GROUP__Syncrounous_serial_port_registers
+ byte R_SERIAL3_CTRL[4];
+ byte R_SERIAL3_XOFF[4];
+#endif
+#if USE_GROUP__Network_interface_registers
+ byte R_NETWORK_SA_0[4];
+ byte R_NETWORK_SA_1[4];
+ byte R_NETWORK_SA_2[4];
+ byte R_NETWORK_GA_0[4];
+ byte R_NETWORK_GA_1[4];
+ byte R_NETWORK_REC_CONFIG[4];
+ byte R_NETWORK_GEN_CONFIG[4];
+ byte R_NETWORK_TR_CTRL[4];
+ byte R_NETWORK_MGM_CTRL[4];
+#endif
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ byte R_IRQ_MASK0_CLR[4];
+ byte R_IRQ_MASK0_SET[4];
+ byte R_IRQ_MASK1_CLR[4];
+ byte R_IRQ_MASK1_SET[4];
+ byte R_IRQ_MASK2_CLR[4];
+ byte R_IRQ_MASK2_SET[4];
+ byte R_VECT_MASK_CLR[4];
+ byte R_VECT_MASK_SET[4];
+#endif
+#if USE_GROUP__Timer_registers
+ byte R_CLOCK_PRESCALE[4];
+ byte R_SYNC_SERIAL_PRESCALE[4];
+#endif
+#if USE_GROUP__Test_mode_registers
+ byte R_TEST_MODE[4];
+#endif
+#if USE_GROUP__DMA_registers
+ byte R_DMA_CH0_CLR_INTR[1];
+ byte R_DMA_CH1_CLR_INTR[1];
+ byte R_DMA_CH2_CLR_INTR[1];
+ byte R_DMA_CH3_CLR_INTR[1];
+ byte R_DMA_CH4_CLR_INTR[1];
+ byte R_DMA_CH8_SUB0_CLR_INTR[1];
+ byte R_DMA_CH5_CLR_INTR[1];
+ byte R_DMA_CH8_SUB1_CLR_INTR[1];
+ byte R_DMA_CH6_CLR_INTR[1];
+ byte R_DMA_CH8_SUB2_CLR_INTR[1];
+ byte R_DMA_CH7_CLR_INTR[1];
+ byte R_DMA_CH8_SUB3_CLR_INTR[1];
+ byte R_DMA_CH8_CLR_INTR[1];
+ byte R_DMA_CH9_CLR_INTR[1];
+#endif
+#if USE_GROUP__USB_interface_control_registers
+ byte R_USB_IRQ_MASK_SET[2];
+ byte R_USB_IRQ_MASK_CLR[2];
+#endif
+#if USE_GROUP__MMU_registers
+ byte R_MMU_CONFIG[4];
+ byte R_MMU_KBASE_LO[4];
+ byte R_MMU_KBASE_HI[4];
+#endif
+} reg_shadow_type__hwregs;
+
+#else /* REG_NO_SHADOW */
+
+typedef const udword reg_shadow_type__hwregs;
+
+#endif /* REG_NO_SHADOW */
+
+extern reg_shadow_type__hwregs reg_shadow__hwregs;
+
+#if REG_DEBUG
+
+/*
+ * Only write only registers need an initiated flag.
+ * Flag is set to all ones at startup, and cleared to
+ * zero when initiated.
+ */
+
+#ifndef REG_NO_SHADOW
+
+typedef struct {
+#if USE_GROUP__Bus_interface_configuration_registers
+ byte R_WAITSTATES[4];
+ byte R_BUS_CONFIG[4];
+ byte R_DRAM_TIMING[4];
+ byte R_DRAM_CONFIG[4];
+#endif
+#if USE_GROUP__External_DMA_registers
+ byte R_EXT_DMA_0_CMD[4];
+ byte R_EXT_DMA_0_ADDR[4];
+ byte R_EXT_DMA_1_CMD[4];
+ byte R_EXT_DMA_1_ADDR[4];
+#endif
+#if USE_GROUP__Timer_registers
+ byte R_TIMER_CTRL[4];
+ byte R_WATCHDOG[4];
+#endif
+#if USE_GROUP__General_config_registers
+ byte R_GEN_CONFIG[4];
+#endif
+#if USE_GROUP__General_port_configuration_registers
+ byte R_PORT_PA_SET[4];
+#endif
+#if USE_GROUP__General_config_registers
+ byte R_GEN_CONFIG_II[4];
+#endif
+#if USE_GROUP__General_port_configuration_registers
+ byte R_PORT_PB_SET[4];
+#endif
+#if USE_GROUP__DMA_registers
+ byte R_SET_EOP[4];
+#endif
+#if USE_GROUP__ATA_interface_registers || \
+ USE_GROUP__Parallel_printer_port_registers || \
+ USE_GROUP__SCSI_registers || \
+ USE_GROUP__Shared_RAM_interface_registers
+ byte R_ATA_CTRL_DATA[4];
+ byte R_ATA_CONFIG[4];
+#endif
+#if USE_GROUP__Parallel_printer_port_registers
+ byte R_PAR0_DELAY[4];
+#endif
+#if USE_GROUP__Parallel_printer_port_registers || \
+ USE_GROUP__SCSI_registers || \
+ USE_GROUP__USB_interface_control_registers
+ byte R_PAR1_CTRL_DATA[4];
+#endif
+#if USE_GROUP__Parallel_printer_port_registers || \
+ USE_GROUP__SCSI_registers
+ byte R_PAR1_CONFIG[4];
+#endif
+#if USE_GROUP__Parallel_printer_port_registers
+ byte R_PAR1_DELAY[4];
+#endif
+#if USE_GROUP__Serial_port_registers
+ byte R_ALT_SER_BAUDRATE[4];
+ byte R_SERIAL0_CTRL[4];
+ byte R_SERIAL0_XOFF[4];
+#endif
+#if USE_GROUP__Serial_port_registers || \
+ USE_GROUP__Syncrounous_serial_port_registers || \
+ USE_GROUP__USB_interface_control_registers
+ byte R_SERIAL1_CTRL[4];
+#endif
+#if USE_GROUP__Serial_port_registers || \
+ USE_GROUP__Syncrounous_serial_port_registers
+ byte R_SERIAL1_XOFF[4];
+#endif
+#if USE_GROUP__Serial_port_registers
+ byte R_SERIAL2_CTRL[4];
+ byte R_SERIAL2_XOFF[4];
+#endif
+#if USE_GROUP__Serial_port_registers || \
+ USE_GROUP__Syncrounous_serial_port_registers
+ byte R_SERIAL3_CTRL[4];
+ byte R_SERIAL3_XOFF[4];
+#endif
+#if USE_GROUP__Network_interface_registers
+ byte R_NETWORK_SA_0[4];
+ byte R_NETWORK_SA_1[4];
+ byte R_NETWORK_SA_2[4];
+ byte R_NETWORK_GA_0[4];
+ byte R_NETWORK_GA_1[4];
+ byte R_NETWORK_REC_CONFIG[4];
+ byte R_NETWORK_GEN_CONFIG[4];
+ byte R_NETWORK_TR_CTRL[4];
+ byte R_NETWORK_MGM_CTRL[4];
+#endif
+#if USE_GROUP__Interrupt_mask_and_status_registers
+ byte R_IRQ_MASK0_CLR[4];
+ byte R_IRQ_MASK0_SET[4];
+ byte R_IRQ_MASK1_CLR[4];
+ byte R_IRQ_MASK1_SET[4];
+ byte R_IRQ_MASK2_CLR[4];
+ byte R_IRQ_MASK2_SET[4];
+ byte R_VECT_MASK_CLR[4];
+ byte R_VECT_MASK_SET[4];
+#endif
+#if USE_GROUP__Timer_registers
+ byte R_CLOCK_PRESCALE[4];
+ byte R_SYNC_SERIAL_PRESCALE[4];
+#endif
+#if USE_GROUP__Test_mode_registers
+ byte R_TEST_MODE[4];
+#endif
+#if USE_GROUP__DMA_registers
+ byte R_DMA_CH0_CLR_INTR[1];
+ byte R_DMA_CH1_CLR_INTR[1];
+ byte R_DMA_CH2_CLR_INTR[1];
+ byte R_DMA_CH3_CLR_INTR[1];
+ byte R_DMA_CH4_CLR_INTR[1];
+ byte R_DMA_CH8_SUB0_CLR_INTR[1];
+ byte R_DMA_CH5_CLR_INTR[1];
+ byte R_DMA_CH8_SUB1_CLR_INTR[1];
+ byte R_DMA_CH6_CLR_INTR[1];
+ byte R_DMA_CH8_SUB2_CLR_INTR[1];
+ byte R_DMA_CH7_CLR_INTR[1];
+ byte R_DMA_CH8_SUB3_CLR_INTR[1];
+ byte R_DMA_CH8_CLR_INTR[1];
+ byte R_DMA_CH9_CLR_INTR[1];
+#endif
+#if USE_GROUP__USB_interface_control_registers
+ byte R_USB_IRQ_MASK_SET[2];
+ byte R_USB_IRQ_MASK_CLR[2];
+#endif
+#if USE_GROUP__MMU_registers
+ byte R_MMU_CONFIG[4];
+ byte R_MMU_KBASE_LO[4];
+ byte R_MMU_KBASE_HI[4];
+#endif
+} reg_initiated_type__hwregs;
+
+#else /* REG_NO_SHADOW */
+
+typedef const udword reg_initiated_type__hwregs;
+
+#endif /* REG_NO_SHADOW */
+
+extern reg_initiated_type__hwregs reg_initiated__hwregs;
+
+#endif /* REG_DEBUG */
+
+extern void init_shadow__hwregs();
+
+#endif /* __ASSEMBLER__ */
+
+
+/********************** CONSTANT AND MACRO SECTION *********************/
+#ifndef __REG_GENERAL_2_H__
+#define __REG_GENERAL_2_H__
+
+/*
+** This part of hwregs.h is common to all shadow
+** register modules, and should therefore only be included once to
+** avoid macro redefinitions.
+*/
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Register type-casts
+ */
+#define REG_TYPECAST_UDWORD (volatile udword*)
+#define REG_TYPECAST_RO_UDWORD (const volatile udword*)
+#define REG_TYPECAST_UWORD (volatile uword*)
+#define REG_TYPECAST_RO_UWORD (const volatile uword*)
+#define REG_TYPECAST_BYTE (volatile byte*)
+#define REG_TYPECAST_RO_BYTE (const volatile byte*)
+
+/*
+ * Shadow register type-casts
+ */
+#define REG_STYPECAST_UDWORD (udword*)
+#define REG_STYPECAST_UWORD (uword*)
+#define REG_STYPECAST_BYTE (byte*)
+
+#else
+
+/*
+ * Register type-casts
+ */
+#define REG_TYPECAST_UDWORD
+#define REG_TYPECAST_RO_UDWORD
+#define REG_TYPECAST_UWORD
+#define REG_TYPECAST_RO_UWORD
+#define REG_TYPECAST_BYTE
+#define REG_TYPECAST_RO_BYTE
+
+/*
+ * Shadow register type-casts
+ */
+#define REG_STYPECAST_UDWORD
+#define REG_STYPECAST_UWORD
+#define REG_STYPECAST_BYTE
+
+#endif
+
+
+#define REG_UDWORD udword
+#define REG_UWORD uword
+#define REG_BYTE byte
+
+#define REG__on 0xffffffffU
+#define REG__off 0
+
+#endif /* __REG_GENERAL_2_H__ */
+
+#include "hwregs_int.h"
+
+#ifndef __REG_GENERAL_3_H__
+#define __REG_GENERAL_3_H__
+
+/*
+** This part of hwregs.h is common to all shadow
+** register modules, and should therefore only be included once to
+** avoid macro redefinitions.
+*/
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_GET
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*#
+*# RETURNS : Value of field field in register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR.
+*#
+*# DESCRIPTION : Read a field in a register. Also see description
+*# of REG_GET_WO, REG_GET_RO, and REG_GET_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_GET(reg,field) ( \
+ reg##__GET(reg##_, field##_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IGET
+*#
+*# PARAMETERS : i : Interface number.
+*# reg : Name of a register.
+*# field : Name of a field.
+*#
+*# RETURNS : Value of field field in register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR, and REG_IERROR.
+*#
+*# DESCRIPTION : Read a field in a register for interface i.
+*# Also see description of REG_IGET_WO, REG_IGET_RO,
+*# and REG_IGET_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_IGET(i,reg,field) ( \
+ reg##__IGET(i, reg##_, field##_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VGET
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*# var : Variable or value to read from.
+*#
+*# RETURNS : Value of field field in variable var.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Interprets variable var as register reg, and read field
+*# field from variable var.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*#**********************************************************************/
+
+#define REG_VGET(reg,field,var) ( \
+ ((reg##__TYPE var) & reg##__##field##__##field##__MASK) >> \
+ reg##__##field##__BITNR \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*# val : Value to write to field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in register reg.
+*# Parameter reg must be a write only or read write
+*# register. Also see description of REG_SET_WO, and
+*# REG_SET_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_SET(reg,field,val) ( \
+ reg##__SET(reg##_, field##_, val) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_ISET
+*#
+*# PARAMETERS : i : Interface number.
+*# reg : Name of a register.
+*# field : Name of a field.
+*# val : Value to write to field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_IERROR, REG_SERROR, and REG_VERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in register reg
+*# of interface i. Parameter reg must be a write only
+*# or read write register. Also see description of
+*# REG_ISET_WO, and REG_ISET_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_ISET(i,reg,field,val) ( \
+ reg##__ISET(i, reg##_, field##_, val) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VSET
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*# val : Value to write to field.
+*# var : Variable to write to.
+*#
+*# RETURNS : Integer value of variable var after write.
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR.
+*#
+*# DESCRIPTION : Interpret variable var as register reg, and write val
+*# parameter to field field in variable var.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_VSET(reg,field,val,var) ( \
+ var = \
+ ((reg##__TYPE var) & REG_IMASK (reg##_, field##_)) | \
+ (reg##__##field##__##field##__VAL(reg##_, field##_, val) << \
+ reg##__##field##__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET_VAL
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*# val : Integer value to write to symbolic field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in register reg.
+*# Parameter reg must be a write only or read write register.
+*# Also see description of REG_SET_VAL_WO, and REG_SET_VAL_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_SET_VAL(reg,field,val) ( \
+ reg##__SET_VAL(reg##_, field##_, val) \
+)
+
+/*
+ * See end of file for these.
+ *
+ * #define REG_SET__register-name
+ * #define REG_SET__register-name__SHADOW
+ * #define REG_MASK__register-name
+ * #define REG_VAL__register-name
+ */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_EQL
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*# val : Value to compare with field.
+*#
+*# RETURNS : TRUE, FALSE
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
+*#
+*# DESCRIPTION : Compare val parameter with field field in register reg.
+*# Also description of REG_EQL_WO, REG_EQL_RO, and
+*# REG_EQL_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+#define REG_EQL(reg,field,val) ( \
+ reg##__EQL(reg##_, field##_, val) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IEQL
+*#
+*# PARAMETERS : i : Interface number.
+*# reg : Name of a register.
+*# field : Name of a field.
+*# val : Value to compare with field.
+*#
+*# RETURNS : TRUE, FALSE
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR, REG_IERROR, and REG_SERROR.
+*#
+*# DESCRIPTION : Compare val parameter with field field in register reg
+*# of interface i. Also see description of REG_IEQL_WO,
+*# REG_IEQ_RO, and REG_IEQL_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_IEQL(i,reg,field,val) ( \
+ reg##__IEQL(i,reg##_,field##_,val) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VEQL
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*# val : Value to compare with field.
+*# var : Variable (or value) to compare with.
+*#
+*# RETURNS : TRUE, FALSE
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR.
+*#
+*# DESCRIPTION : Interprets variable var as register reg, and compare
+*# compare field field with parameter val.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_VEQL(reg,field,val,var) ( \
+ ( ((reg##__TYPE (var)) & reg##__##field##__##field##__MASK) >> \
+ reg##__##field##__BITNR \
+ ) == reg##__##field##__##field##__VAL(reg##_, field##_, val) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*# val : A symbolic constant.
+*#
+*# RETURNS : val or (val << REG_VERROR()) macro.
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR macro.
+*#
+*# DESCRIPTION : Convert a symbolic constant to an integer value.
+*# Intended to be used for enumerated fields. Also
+*# Also works for value fields, in which case the val
+*# parameter is checked for range and returned if OK,
+*# and if val is out of range (val << REG_VERROR) is
+*# returned. Also see description of REG_VAL_VAL, and
+*# REG_VAL_ENUM.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg and field parameters when
+*# passing on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL(reg,field,val) ( \
+ reg##__##field##__##field##__VAL(reg##_, field##_, val) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_CHK_VAL
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field.
+*# val : An integer value.
+*#
+*# RETURNS : 1 if val is within allowed range for field, otherwise 0.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Check if parameter val is within the field range,
+*# and return 1 if it is, otherwise 0.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*#**********************************************************************/
+
+#define REG_CHK_VAL(reg,field,val) ( \
+ (udword)(~(val)) <= (udword)(~(reg##__##field##__MIN)) && \
+ (udword)(val) <= (udword)(reg##__##field##__MAX) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_RD
+*#
+*# PARAMETERS : reg : Name of a register.
+*#
+*# RETURNS : Contents of register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR.
+*#
+*# DESCRIPTION : Read contents of register reg. Also see description of
+*# REG_RD_WO, REG_RD_RO, and REG_RD_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg parameter when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_RD(reg) ( \
+ reg##__RD(reg##_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IRD
+*#
+*# PARAMETERS : i : Interface number.
+*# reg : Name of a register.
+*#
+*# RETURNS : Contents of register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR and REG_IERROR.
+*#
+*# DESCRIPTION : Read contents of register reg. Also see description of
+*# REG_IRD_WO, REG_IRD_RO, and REG_IRD_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg parameter when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_IRD(i,reg) ( \
+ reg##__IRD(i,reg##_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_WR
+*#
+*# PARAMETERS : reg : Name of a register.
+*# var : Variable (or value) to write to reg.
+*#
+*# RETURNS : integer value written to register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR.
+*#
+*# DESCRIPTION : Write value of var parameter to register reg. Also see
+*# description of REG_WR_WO, and REG_WR_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg parameter when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_WR(reg,var) ( \
+ reg##__WR(reg##_,var) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IWR
+*#
+*# PARAMETERS : i : Interface number.
+*# reg : Name of a register.
+*# var : Variable (or value) to write to reg.
+*#
+*# RETURNS : integer value written to register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR.
+*#
+*# DESCRIPTION : Write value of var parameter to register reg of
+*# interface i. Also see description of REG_IWR_WO,
+*# and REG_IWR_RW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to reg parameter when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_IWR(i,reg,var) ( \
+ reg##__IWR(i##_, reg##_, var) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_ADDR
+*#
+*# PARAMETERS : reg : Name of a register.
+*#
+*# RETURNS : Address to register reg.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Calculate address to register reg.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*#**********************************************************************/
+
+#define REG_ADDR(reg) ( \
+ reg##__ADDR \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_BITNR
+*#
+*# PARAMETERS : reg : Name of a register.
+*# field : Name of a field in register reg.
+*#
+*# RETURNS : Position of least significant bit of field in reg..
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Calculate position of least significant bit of
+*# field field in register reg.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*#**********************************************************************/
+
+#define REG_BITNR(reg,field) ( \
+ reg##__##field##__BITNR \
+)
+
+#endif /* __REG_GENERAL_3_H__ */
+
+
+/*
+ * R_ALT_SER_BAUDRATE
+ * - type: WO
+ * - addr: 0xb000005c
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_ALT_SER_BAUDRATE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_ALT_SER_BAUDRATE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_ALT_SER_BAUDRATE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_ALT_SER_BAUDRATE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_ALT_SER_BAUDRATE__SADDR = ( \
+ REG_INITIATED(R_ALT_SER_BAUDRATE_) \
+ REG_VAL__R_ALT_SER_BAUDRATE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_ALT_SER_BAUDRATE__WRITE(R_ALT_SER_BAUDRATE__ADDR, *R_ALT_SER_BAUDRATE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_ALT_SER_BAUDRATE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_ALT_SER_BAUDRATE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_ALT_SER_BAUDRATE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_ALT_SER_BAUDRATE__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_ALT_SER_BAUDRATE__SADDR = ( \
+ REG_INITIATED(R_ALT_SER_BAUDRATE_) \
+ REG_VAL__R_ALT_SER_BAUDRATE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_ALT_SER_BAUDRATE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_ALT_SER_BAUDRATE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_ALT_SER_BAUDRATE__ser3_tr__##f1##__MASK & REG__##v1) | \
+ (R_ALT_SER_BAUDRATE__ser3_rec__##f2##__MASK & REG__##v2) | \
+ (R_ALT_SER_BAUDRATE__ser2_tr__##f3##__MASK & REG__##v3) | \
+ (R_ALT_SER_BAUDRATE__ser2_rec__##f4##__MASK & REG__##v4) | \
+ (R_ALT_SER_BAUDRATE__ser1_tr__##f5##__MASK & REG__##v5) | \
+ (R_ALT_SER_BAUDRATE__ser1_rec__##f6##__MASK & REG__##v6) | \
+ (R_ALT_SER_BAUDRATE__ser0_tr__##f7##__MASK & REG__##v7) | \
+ (R_ALT_SER_BAUDRATE__ser0_rec__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ALT_SER_BAUDRATE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ALT_SER_BAUDRATE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_ALT_SER_BAUDRATE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_ALT_SER_BAUDRATE__ser3_tr__##f1##__VAL(R_ALT_SER_BAUDRATE_, ser3_tr_, v1) << R_ALT_SER_BAUDRATE__ser3_tr__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser3_rec__##f2##__VAL(R_ALT_SER_BAUDRATE_, ser3_rec_, v2) << R_ALT_SER_BAUDRATE__ser3_rec__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser2_tr__##f3##__VAL(R_ALT_SER_BAUDRATE_, ser2_tr_, v3) << R_ALT_SER_BAUDRATE__ser2_tr__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser2_rec__##f4##__VAL(R_ALT_SER_BAUDRATE_, ser2_rec_, v4) << R_ALT_SER_BAUDRATE__ser2_rec__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser1_tr__##f5##__VAL(R_ALT_SER_BAUDRATE_, ser1_tr_, v5) << R_ALT_SER_BAUDRATE__ser1_tr__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser1_rec__##f6##__VAL(R_ALT_SER_BAUDRATE_, ser1_rec_, v6) << R_ALT_SER_BAUDRATE__ser1_rec__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser0_tr__##f7##__VAL(R_ALT_SER_BAUDRATE_, ser0_tr_, v7) << R_ALT_SER_BAUDRATE__ser0_tr__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser0_rec__##f8##__VAL(R_ALT_SER_BAUDRATE_, ser0_rec_, v8) << R_ALT_SER_BAUDRATE__ser0_rec__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ALT_SER_BAUDRATE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ALT_SER_BAUDRATE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_ALT_SER_BAUDRATE_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_ALT_SER_BAUDRATE__ser3_tr__##f1_##_VAL(R_ALT_SER_BAUDRATE_, ser3_tr_, v1) << R_ALT_SER_BAUDRATE__ser3_tr__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser3_rec__##f2_##_VAL(R_ALT_SER_BAUDRATE_, ser3_rec_, v2) << R_ALT_SER_BAUDRATE__ser3_rec__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser2_tr__##f3_##_VAL(R_ALT_SER_BAUDRATE_, ser2_tr_, v3) << R_ALT_SER_BAUDRATE__ser2_tr__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser2_rec__##f4_##_VAL(R_ALT_SER_BAUDRATE_, ser2_rec_, v4) << R_ALT_SER_BAUDRATE__ser2_rec__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser1_tr__##f5_##_VAL(R_ALT_SER_BAUDRATE_, ser1_tr_, v5) << R_ALT_SER_BAUDRATE__ser1_tr__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser1_rec__##f6_##_VAL(R_ALT_SER_BAUDRATE_, ser1_rec_, v6) << R_ALT_SER_BAUDRATE__ser1_rec__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser0_tr__##f7_##_VAL(R_ALT_SER_BAUDRATE_, ser0_tr_, v7) << R_ALT_SER_BAUDRATE__ser0_tr__BITNR) | \
+ (R_ALT_SER_BAUDRATE__ser0_rec__##f8_##_VAL(R_ALT_SER_BAUDRATE_, ser0_rec_, v8) << R_ALT_SER_BAUDRATE__ser0_rec__BITNR) \
+)
+
+#endif
+
+/*
+ * R_ATA_CONFIG
+ * - type: WO
+ * - addr: 0xb0000044
+ * - group: ATA interface registers
+ */
+
+#if USE_GROUP__ATA_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_ATA_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_ATA_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_ATA_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_ATA_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_ATA_CONFIG__SADDR = ( \
+ REG_INITIATED(R_ATA_CONFIG_) \
+ REG_VAL__R_ATA_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ), \
+ R_ATA_CONFIG__WRITE(R_ATA_CONFIG__ADDR, *R_ATA_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_ATA_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_ATA_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_ATA_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_ATA_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_ATA_CONFIG__SADDR = ( \
+ REG_INITIATED(R_ATA_CONFIG_) \
+ REG_VAL__R_ATA_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_ATA_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_ATA_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_ATA_CONFIG__enable__##f1##__MASK & REG__##v1) | \
+ (R_ATA_CONFIG__dma_strobe__##f2##__MASK & REG__##v2) | \
+ (R_ATA_CONFIG__dma_hold__##f3##__MASK & REG__##v3) | \
+ (R_ATA_CONFIG__pio_setup__##f4##__MASK & REG__##v4) | \
+ (R_ATA_CONFIG__pio_strobe__##f5##__MASK & REG__##v5) | \
+ (R_ATA_CONFIG__pio_hold__##f6##__MASK & REG__##v6) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ATA_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ATA_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_ATA_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_ATA_CONFIG__enable__##f1##__VAL(R_ATA_CONFIG_, enable_, v1) << R_ATA_CONFIG__enable__BITNR) | \
+ (R_ATA_CONFIG__dma_strobe__##f2##__VAL(R_ATA_CONFIG_, dma_strobe_, v2) << R_ATA_CONFIG__dma_strobe__BITNR) | \
+ (R_ATA_CONFIG__dma_hold__##f3##__VAL(R_ATA_CONFIG_, dma_hold_, v3) << R_ATA_CONFIG__dma_hold__BITNR) | \
+ (R_ATA_CONFIG__pio_setup__##f4##__VAL(R_ATA_CONFIG_, pio_setup_, v4) << R_ATA_CONFIG__pio_setup__BITNR) | \
+ (R_ATA_CONFIG__pio_strobe__##f5##__VAL(R_ATA_CONFIG_, pio_strobe_, v5) << R_ATA_CONFIG__pio_strobe__BITNR) | \
+ (R_ATA_CONFIG__pio_hold__##f6##__VAL(R_ATA_CONFIG_, pio_hold_, v6) << R_ATA_CONFIG__pio_hold__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ATA_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ATA_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_ATA_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \
+ (R_ATA_CONFIG__enable__##f1_##_VAL(R_ATA_CONFIG_, enable_, v1) << R_ATA_CONFIG__enable__BITNR) | \
+ (R_ATA_CONFIG__dma_strobe__##f2_##_VAL(R_ATA_CONFIG_, dma_strobe_, v2) << R_ATA_CONFIG__dma_strobe__BITNR) | \
+ (R_ATA_CONFIG__dma_hold__##f3_##_VAL(R_ATA_CONFIG_, dma_hold_, v3) << R_ATA_CONFIG__dma_hold__BITNR) | \
+ (R_ATA_CONFIG__pio_setup__##f4_##_VAL(R_ATA_CONFIG_, pio_setup_, v4) << R_ATA_CONFIG__pio_setup__BITNR) | \
+ (R_ATA_CONFIG__pio_strobe__##f5_##_VAL(R_ATA_CONFIG_, pio_strobe_, v5) << R_ATA_CONFIG__pio_strobe__BITNR) | \
+ (R_ATA_CONFIG__pio_hold__##f6_##_VAL(R_ATA_CONFIG_, pio_hold_, v6) << R_ATA_CONFIG__pio_hold__BITNR) \
+)
+
+#endif
+
+/*
+ * R_ATA_CTRL_DATA
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: ATA interface registers
+ */
+
+#if USE_GROUP__ATA_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_ATA_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_ATA_CTRL_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_ATA_CTRL_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_ATA_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_ATA_CTRL_DATA__SADDR = ( \
+ REG_INITIATED(R_ATA_CTRL_DATA_) \
+ REG_VAL__R_ATA_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ), \
+ R_ATA_CTRL_DATA__WRITE(R_ATA_CTRL_DATA__ADDR, *R_ATA_CTRL_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_ATA_CTRL_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_ATA_CTRL_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_ATA_CTRL_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_ATA_CTRL_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_ATA_CTRL_DATA__SADDR = ( \
+ REG_INITIATED(R_ATA_CTRL_DATA_) \
+ REG_VAL__R_ATA_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_ATA_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_ATA_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_ATA_CTRL_DATA__sel__##f1##__MASK & REG__##v1) | \
+ (R_ATA_CTRL_DATA__cs1__##f2##__MASK & REG__##v2) | \
+ (R_ATA_CTRL_DATA__cs0__##f3##__MASK & REG__##v3) | \
+ (R_ATA_CTRL_DATA__addr__##f4##__MASK & REG__##v4) | \
+ (R_ATA_CTRL_DATA__rw__##f5##__MASK & REG__##v5) | \
+ (R_ATA_CTRL_DATA__src_dst__##f6##__MASK & REG__##v6) | \
+ (R_ATA_CTRL_DATA__handsh__##f7##__MASK & REG__##v7) | \
+ (R_ATA_CTRL_DATA__multi__##f8##__MASK & REG__##v8) | \
+ (R_ATA_CTRL_DATA__dma_size__##f9##__MASK & REG__##v9) | \
+ (R_ATA_CTRL_DATA__data__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ATA_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ATA_CTRL_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_ATA_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_ATA_CTRL_DATA__sel__##f1##__VAL(R_ATA_CTRL_DATA_, sel_, v1) << R_ATA_CTRL_DATA__sel__BITNR) | \
+ (R_ATA_CTRL_DATA__cs1__##f2##__VAL(R_ATA_CTRL_DATA_, cs1_, v2) << R_ATA_CTRL_DATA__cs1__BITNR) | \
+ (R_ATA_CTRL_DATA__cs0__##f3##__VAL(R_ATA_CTRL_DATA_, cs0_, v3) << R_ATA_CTRL_DATA__cs0__BITNR) | \
+ (R_ATA_CTRL_DATA__addr__##f4##__VAL(R_ATA_CTRL_DATA_, addr_, v4) << R_ATA_CTRL_DATA__addr__BITNR) | \
+ (R_ATA_CTRL_DATA__rw__##f5##__VAL(R_ATA_CTRL_DATA_, rw_, v5) << R_ATA_CTRL_DATA__rw__BITNR) | \
+ (R_ATA_CTRL_DATA__src_dst__##f6##__VAL(R_ATA_CTRL_DATA_, src_dst_, v6) << R_ATA_CTRL_DATA__src_dst__BITNR) | \
+ (R_ATA_CTRL_DATA__handsh__##f7##__VAL(R_ATA_CTRL_DATA_, handsh_, v7) << R_ATA_CTRL_DATA__handsh__BITNR) | \
+ (R_ATA_CTRL_DATA__multi__##f8##__VAL(R_ATA_CTRL_DATA_, multi_, v8) << R_ATA_CTRL_DATA__multi__BITNR) | \
+ (R_ATA_CTRL_DATA__dma_size__##f9##__VAL(R_ATA_CTRL_DATA_, dma_size_, v9) << R_ATA_CTRL_DATA__dma_size__BITNR) | \
+ (R_ATA_CTRL_DATA__data__##f10##__VAL(R_ATA_CTRL_DATA_, data_, v10) << R_ATA_CTRL_DATA__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ATA_CTRL_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ATA_CTRL_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_ATA_CTRL_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_ATA_CTRL_DATA__sel__##f1_##_VAL(R_ATA_CTRL_DATA_, sel_, v1) << R_ATA_CTRL_DATA__sel__BITNR) | \
+ (R_ATA_CTRL_DATA__cs1__##f2_##_VAL(R_ATA_CTRL_DATA_, cs1_, v2) << R_ATA_CTRL_DATA__cs1__BITNR) | \
+ (R_ATA_CTRL_DATA__cs0__##f3_##_VAL(R_ATA_CTRL_DATA_, cs0_, v3) << R_ATA_CTRL_DATA__cs0__BITNR) | \
+ (R_ATA_CTRL_DATA__addr__##f4_##_VAL(R_ATA_CTRL_DATA_, addr_, v4) << R_ATA_CTRL_DATA__addr__BITNR) | \
+ (R_ATA_CTRL_DATA__rw__##f5_##_VAL(R_ATA_CTRL_DATA_, rw_, v5) << R_ATA_CTRL_DATA__rw__BITNR) | \
+ (R_ATA_CTRL_DATA__src_dst__##f6_##_VAL(R_ATA_CTRL_DATA_, src_dst_, v6) << R_ATA_CTRL_DATA__src_dst__BITNR) | \
+ (R_ATA_CTRL_DATA__handsh__##f7_##_VAL(R_ATA_CTRL_DATA_, handsh_, v7) << R_ATA_CTRL_DATA__handsh__BITNR) | \
+ (R_ATA_CTRL_DATA__multi__##f8_##_VAL(R_ATA_CTRL_DATA_, multi_, v8) << R_ATA_CTRL_DATA__multi__BITNR) | \
+ (R_ATA_CTRL_DATA__dma_size__##f9_##_VAL(R_ATA_CTRL_DATA_, dma_size_, v9) << R_ATA_CTRL_DATA__dma_size__BITNR) | \
+ (R_ATA_CTRL_DATA__data__##f10_##_VAL(R_ATA_CTRL_DATA_, data_, v10) << R_ATA_CTRL_DATA__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_ATA_STATUS_DATA
+ * - type: RO
+ * - addr: 0xb0000040
+ * - group: ATA interface registers
+ */
+
+#if USE_GROUP__ATA_interface_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_ATA_STATUS_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_ATA_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_ATA_STATUS_DATA__busy__##f1##__MASK & REG__##v1) | \
+ (R_ATA_STATUS_DATA__tr_rdy__##f2##__MASK & REG__##v2) | \
+ (R_ATA_STATUS_DATA__dav__##f3##__MASK & REG__##v3) | \
+ (R_ATA_STATUS_DATA__data__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ATA_STATUS_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ATA_STATUS_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_ATA_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_ATA_STATUS_DATA__busy__##f1##__VAL(R_ATA_STATUS_DATA_, busy_, v1) << R_ATA_STATUS_DATA__busy__BITNR) | \
+ (R_ATA_STATUS_DATA__tr_rdy__##f2##__VAL(R_ATA_STATUS_DATA_, tr_rdy_, v2) << R_ATA_STATUS_DATA__tr_rdy__BITNR) | \
+ (R_ATA_STATUS_DATA__dav__##f3##__VAL(R_ATA_STATUS_DATA_, dav_, v3) << R_ATA_STATUS_DATA__dav__BITNR) | \
+ (R_ATA_STATUS_DATA__data__##f4##__VAL(R_ATA_STATUS_DATA_, data_, v4) << R_ATA_STATUS_DATA__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ATA_STATUS_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ATA_STATUS_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_ATA_STATUS_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_ATA_STATUS_DATA__busy__##f1_##_VAL(R_ATA_STATUS_DATA_, busy_, v1) << R_ATA_STATUS_DATA__busy__BITNR) | \
+ (R_ATA_STATUS_DATA__tr_rdy__##f2_##_VAL(R_ATA_STATUS_DATA_, tr_rdy_, v2) << R_ATA_STATUS_DATA__tr_rdy__BITNR) | \
+ (R_ATA_STATUS_DATA__dav__##f3_##_VAL(R_ATA_STATUS_DATA_, dav_, v3) << R_ATA_STATUS_DATA__dav__BITNR) | \
+ (R_ATA_STATUS_DATA__data__##f4_##_VAL(R_ATA_STATUS_DATA_, data_, v4) << R_ATA_STATUS_DATA__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_ATA_TRANSFER_CNT
+ * - type: RW
+ * - addr: 0xb0000048
+ * - group: ATA interface registers
+ */
+
+#if USE_GROUP__ATA_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_ATA_TRANSFER_CNT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_ATA_TRANSFER_CNT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_ATA_TRANSFER_CNT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_ATA_TRANSFER_CNT(f1,v1) ( \
+ R_ATA_TRANSFER_CNT__WRITE(R_ATA_TRANSFER_CNT__ADDR, ( \
+ REG_VAL__R_ATA_TRANSFER_CNT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_ATA_TRANSFER_CNT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_ATA_TRANSFER_CNT(f1,v1) ( \
+ (R_ATA_TRANSFER_CNT__count__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ATA_TRANSFER_CNT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ATA_TRANSFER_CNT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_ATA_TRANSFER_CNT(f1,v1) ( \
+ (R_ATA_TRANSFER_CNT__count__##f1##__VAL(R_ATA_TRANSFER_CNT_, count_, v1) << R_ATA_TRANSFER_CNT__count__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_ATA_TRANSFER_CNT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_ATA_TRANSFER_CNT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_ATA_TRANSFER_CNT_(f1_,v1) ( \
+ (R_ATA_TRANSFER_CNT__count__##f1_##_VAL(R_ATA_TRANSFER_CNT_, count_, v1) << R_ATA_TRANSFER_CNT__count__BITNR) \
+)
+
+#endif
+
+/*
+ * R_BUS_CONFIG
+ * - type: WO
+ * - addr: 0xb0000004
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_BUS_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_BUS_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_BUS_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_BUS_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_BUS_CONFIG__SADDR = ( \
+ REG_INITIATED(R_BUS_CONFIG_) \
+ REG_VAL__R_BUS_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ), \
+ R_BUS_CONFIG__WRITE(R_BUS_CONFIG__ADDR, *R_BUS_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_BUS_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_BUS_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_BUS_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_BUS_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_BUS_CONFIG__SADDR = ( \
+ REG_INITIATED(R_BUS_CONFIG_) \
+ REG_VAL__R_BUS_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_BUS_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_BUS_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_BUS_CONFIG__sram_type__##f1##__MASK & REG__##v1) | \
+ (R_BUS_CONFIG__dma_burst__##f2##__MASK & REG__##v2) | \
+ (R_BUS_CONFIG__pcs4_7_wr__##f3##__MASK & REG__##v3) | \
+ (R_BUS_CONFIG__pcs0_3_wr__##f4##__MASK & REG__##v4) | \
+ (R_BUS_CONFIG__sram_wr__##f5##__MASK & REG__##v5) | \
+ (R_BUS_CONFIG__flash_wr__##f6##__MASK & REG__##v6) | \
+ (R_BUS_CONFIG__pcs4_7_bw__##f7##__MASK & REG__##v7) | \
+ (R_BUS_CONFIG__pcs0_3_bw__##f8##__MASK & REG__##v8) | \
+ (R_BUS_CONFIG__sram_bw__##f9##__MASK & REG__##v9) | \
+ (R_BUS_CONFIG__flash_bw__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_BUS_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_BUS_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_BUS_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_BUS_CONFIG__sram_type__##f1##__VAL(R_BUS_CONFIG_, sram_type_, v1) << R_BUS_CONFIG__sram_type__BITNR) | \
+ (R_BUS_CONFIG__dma_burst__##f2##__VAL(R_BUS_CONFIG_, dma_burst_, v2) << R_BUS_CONFIG__dma_burst__BITNR) | \
+ (R_BUS_CONFIG__pcs4_7_wr__##f3##__VAL(R_BUS_CONFIG_, pcs4_7_wr_, v3) << R_BUS_CONFIG__pcs4_7_wr__BITNR) | \
+ (R_BUS_CONFIG__pcs0_3_wr__##f4##__VAL(R_BUS_CONFIG_, pcs0_3_wr_, v4) << R_BUS_CONFIG__pcs0_3_wr__BITNR) | \
+ (R_BUS_CONFIG__sram_wr__##f5##__VAL(R_BUS_CONFIG_, sram_wr_, v5) << R_BUS_CONFIG__sram_wr__BITNR) | \
+ (R_BUS_CONFIG__flash_wr__##f6##__VAL(R_BUS_CONFIG_, flash_wr_, v6) << R_BUS_CONFIG__flash_wr__BITNR) | \
+ (R_BUS_CONFIG__pcs4_7_bw__##f7##__VAL(R_BUS_CONFIG_, pcs4_7_bw_, v7) << R_BUS_CONFIG__pcs4_7_bw__BITNR) | \
+ (R_BUS_CONFIG__pcs0_3_bw__##f8##__VAL(R_BUS_CONFIG_, pcs0_3_bw_, v8) << R_BUS_CONFIG__pcs0_3_bw__BITNR) | \
+ (R_BUS_CONFIG__sram_bw__##f9##__VAL(R_BUS_CONFIG_, sram_bw_, v9) << R_BUS_CONFIG__sram_bw__BITNR) | \
+ (R_BUS_CONFIG__flash_bw__##f10##__VAL(R_BUS_CONFIG_, flash_bw_, v10) << R_BUS_CONFIG__flash_bw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_BUS_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_BUS_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_BUS_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_BUS_CONFIG__sram_type__##f1_##_VAL(R_BUS_CONFIG_, sram_type_, v1) << R_BUS_CONFIG__sram_type__BITNR) | \
+ (R_BUS_CONFIG__dma_burst__##f2_##_VAL(R_BUS_CONFIG_, dma_burst_, v2) << R_BUS_CONFIG__dma_burst__BITNR) | \
+ (R_BUS_CONFIG__pcs4_7_wr__##f3_##_VAL(R_BUS_CONFIG_, pcs4_7_wr_, v3) << R_BUS_CONFIG__pcs4_7_wr__BITNR) | \
+ (R_BUS_CONFIG__pcs0_3_wr__##f4_##_VAL(R_BUS_CONFIG_, pcs0_3_wr_, v4) << R_BUS_CONFIG__pcs0_3_wr__BITNR) | \
+ (R_BUS_CONFIG__sram_wr__##f5_##_VAL(R_BUS_CONFIG_, sram_wr_, v5) << R_BUS_CONFIG__sram_wr__BITNR) | \
+ (R_BUS_CONFIG__flash_wr__##f6_##_VAL(R_BUS_CONFIG_, flash_wr_, v6) << R_BUS_CONFIG__flash_wr__BITNR) | \
+ (R_BUS_CONFIG__pcs4_7_bw__##f7_##_VAL(R_BUS_CONFIG_, pcs4_7_bw_, v7) << R_BUS_CONFIG__pcs4_7_bw__BITNR) | \
+ (R_BUS_CONFIG__pcs0_3_bw__##f8_##_VAL(R_BUS_CONFIG_, pcs0_3_bw_, v8) << R_BUS_CONFIG__pcs0_3_bw__BITNR) | \
+ (R_BUS_CONFIG__sram_bw__##f9_##_VAL(R_BUS_CONFIG_, sram_bw_, v9) << R_BUS_CONFIG__sram_bw__BITNR) | \
+ (R_BUS_CONFIG__flash_bw__##f10_##_VAL(R_BUS_CONFIG_, flash_bw_, v10) << R_BUS_CONFIG__flash_bw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_BUS_STATUS
+ * - type: RO
+ * - addr: 0xb0000004
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_BUS_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_BUS_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_BUS_STATUS__pll_lock_tm__##f1##__MASK & REG__##v1) | \
+ (R_BUS_STATUS__both_faults__##f2##__MASK & REG__##v2) | \
+ (R_BUS_STATUS__bsen___##f3##__MASK & REG__##v3) | \
+ (R_BUS_STATUS__boot__##f4##__MASK & REG__##v4) | \
+ (R_BUS_STATUS__flashw__##f5##__MASK & REG__##v5) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_BUS_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_BUS_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_BUS_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_BUS_STATUS__pll_lock_tm__##f1##__VAL(R_BUS_STATUS_, pll_lock_tm_, v1) << R_BUS_STATUS__pll_lock_tm__BITNR) | \
+ (R_BUS_STATUS__both_faults__##f2##__VAL(R_BUS_STATUS_, both_faults_, v2) << R_BUS_STATUS__both_faults__BITNR) | \
+ (R_BUS_STATUS__bsen___##f3##__VAL(R_BUS_STATUS_, bsen__, v3) << R_BUS_STATUS__bsen___BITNR) | \
+ (R_BUS_STATUS__boot__##f4##__VAL(R_BUS_STATUS_, boot_, v4) << R_BUS_STATUS__boot__BITNR) | \
+ (R_BUS_STATUS__flashw__##f5##__VAL(R_BUS_STATUS_, flashw_, v5) << R_BUS_STATUS__flashw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_BUS_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_BUS_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_BUS_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \
+ (R_BUS_STATUS__pll_lock_tm__##f1_##_VAL(R_BUS_STATUS_, pll_lock_tm_, v1) << R_BUS_STATUS__pll_lock_tm__BITNR) | \
+ (R_BUS_STATUS__both_faults__##f2_##_VAL(R_BUS_STATUS_, both_faults_, v2) << R_BUS_STATUS__both_faults__BITNR) | \
+ (R_BUS_STATUS__bsen___##f3_##_VAL(R_BUS_STATUS_, bsen__, v3) << R_BUS_STATUS__bsen___BITNR) | \
+ (R_BUS_STATUS__boot__##f4_##_VAL(R_BUS_STATUS_, boot_, v4) << R_BUS_STATUS__boot__BITNR) | \
+ (R_BUS_STATUS__flashw__##f5_##_VAL(R_BUS_STATUS_, flashw_, v5) << R_BUS_STATUS__flashw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_CLOCK_PRESCALE
+ * - type: WO
+ * - addr: 0xb00000f0
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_CLOCK_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_CLOCK_PRESCALE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_CLOCK_PRESCALE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_CLOCK_PRESCALE(f1,v1,f2,v2) ( \
+ *R_CLOCK_PRESCALE__SADDR = ( \
+ REG_INITIATED(R_CLOCK_PRESCALE_) \
+ REG_VAL__R_CLOCK_PRESCALE_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_CLOCK_PRESCALE__WRITE(R_CLOCK_PRESCALE__ADDR, *R_CLOCK_PRESCALE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_CLOCK_PRESCALE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_CLOCK_PRESCALE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_CLOCK_PRESCALE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_CLOCK_PRESCALE__SHADOW(f1,v1,f2,v2) ( \
+ *R_CLOCK_PRESCALE__SADDR = ( \
+ REG_INITIATED(R_CLOCK_PRESCALE_) \
+ REG_VAL__R_CLOCK_PRESCALE_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_CLOCK_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_CLOCK_PRESCALE(f1,v1,f2,v2) ( \
+ (R_CLOCK_PRESCALE__ser_presc__##f1##__MASK & REG__##v1) | \
+ (R_CLOCK_PRESCALE__tim_presc__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_CLOCK_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_CLOCK_PRESCALE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_CLOCK_PRESCALE(f1,v1,f2,v2) ( \
+ (R_CLOCK_PRESCALE__ser_presc__##f1##__VAL(R_CLOCK_PRESCALE_, ser_presc_, v1) << R_CLOCK_PRESCALE__ser_presc__BITNR) | \
+ (R_CLOCK_PRESCALE__tim_presc__##f2##__VAL(R_CLOCK_PRESCALE_, tim_presc_, v2) << R_CLOCK_PRESCALE__tim_presc__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_CLOCK_PRESCALE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_CLOCK_PRESCALE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_CLOCK_PRESCALE_(f1_,v1,f2_,v2) ( \
+ (R_CLOCK_PRESCALE__ser_presc__##f1_##_VAL(R_CLOCK_PRESCALE_, ser_presc_, v1) << R_CLOCK_PRESCALE__ser_presc__BITNR) | \
+ (R_CLOCK_PRESCALE__tim_presc__##f2_##_VAL(R_CLOCK_PRESCALE_, tim_presc_, v2) << R_CLOCK_PRESCALE__tim_presc__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH0_BUF
+ * - type: RW
+ * - addr: 0xb0000108
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH0_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH0_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH0_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH0_BUF(f1,v1) ( \
+ R_DMA_CH0_BUF__WRITE(R_DMA_CH0_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH0_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH0_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH0_BUF(f1,v1) ( \
+ (R_DMA_CH0_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_BUF(f1,v1) ( \
+ (R_DMA_CH0_BUF__buf__##f1##__VAL(R_DMA_CH0_BUF_, buf_, v1) << R_DMA_CH0_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_BUF_(f1_,v1) ( \
+ (R_DMA_CH0_BUF__buf__##f1_##_VAL(R_DMA_CH0_BUF_, buf_, v1) << R_DMA_CH0_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH0_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001d1
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH0_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH0_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH0_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH0_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH0_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH0_CLR_INTR_) \
+ REG_VAL__R_DMA_CH0_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH0_CLR_INTR__WRITE(R_DMA_CH0_CLR_INTR__ADDR, *R_DMA_CH0_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH0_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH0_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH0_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH0_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH0_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH0_CLR_INTR_) \
+ REG_VAL__R_DMA_CH0_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH0_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH0_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH0_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH0_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH0_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH0_CLR_INTR_, clr_eop_, v1) << R_DMA_CH0_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH0_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH0_CLR_INTR_, clr_descr_, v2) << R_DMA_CH0_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH0_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH0_CLR_INTR_, clr_eop_, v1) << R_DMA_CH0_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH0_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH0_CLR_INTR_, clr_descr_, v2) << R_DMA_CH0_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH0_CMD
+ * - type: RW
+ * - addr: 0xb00001d0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH0_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH0_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH0_CMD(f1,v1) ( \
+ R_DMA_CH0_CMD__WRITE(R_DMA_CH0_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH0_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH0_CMD(f1,v1) ( \
+ (R_DMA_CH0_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_CMD(f1,v1) ( \
+ (R_DMA_CH0_CMD__cmd__##f1##__VAL(R_DMA_CH0_CMD_, cmd_, v1) << R_DMA_CH0_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_CMD_(f1_,v1) ( \
+ (R_DMA_CH0_CMD__cmd__##f1_##_VAL(R_DMA_CH0_CMD_, cmd_, v1) << R_DMA_CH0_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH0_DESCR
+ * - type: RW
+ * - addr: 0xb000010c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH0_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH0_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH0_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH0_DESCR(f1,v1) ( \
+ R_DMA_CH0_DESCR__WRITE(R_DMA_CH0_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH0_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH0_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH0_DESCR(f1,v1) ( \
+ (R_DMA_CH0_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_DESCR(f1,v1) ( \
+ (R_DMA_CH0_DESCR__descr__##f1##__VAL(R_DMA_CH0_DESCR_, descr_, v1) << R_DMA_CH0_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_DESCR_(f1_,v1) ( \
+ (R_DMA_CH0_DESCR__descr__##f1_##_VAL(R_DMA_CH0_DESCR_, descr_, v1) << R_DMA_CH0_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH0_FIRST
+ * - type: RW
+ * - addr: 0xb00001a0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH0_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH0_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH0_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH0_FIRST(f1,v1) ( \
+ R_DMA_CH0_FIRST__WRITE(R_DMA_CH0_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH0_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH0_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH0_FIRST(f1,v1) ( \
+ (R_DMA_CH0_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_FIRST(f1,v1) ( \
+ (R_DMA_CH0_FIRST__first__##f1##__VAL(R_DMA_CH0_FIRST_, first_, v1) << R_DMA_CH0_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_FIRST_(f1_,v1) ( \
+ (R_DMA_CH0_FIRST__first__##f1_##_VAL(R_DMA_CH0_FIRST_, first_, v1) << R_DMA_CH0_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH0_HWSW
+ * - type: RW
+ * - addr: 0xb0000100
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH0_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH0_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH0_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH0_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH0_HWSW__WRITE(R_DMA_CH0_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH0_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH0_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH0_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH0_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH0_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH0_HWSW__hw__##f1##__VAL(R_DMA_CH0_HWSW_, hw_, v1) << R_DMA_CH0_HWSW__hw__BITNR) | \
+ (R_DMA_CH0_HWSW__sw__##f2##__VAL(R_DMA_CH0_HWSW_, sw_, v2) << R_DMA_CH0_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH0_HWSW__hw__##f1_##_VAL(R_DMA_CH0_HWSW_, hw_, v1) << R_DMA_CH0_HWSW__hw__BITNR) | \
+ (R_DMA_CH0_HWSW__sw__##f2_##_VAL(R_DMA_CH0_HWSW_, sw_, v2) << R_DMA_CH0_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH0_NEXT
+ * - type: RW
+ * - addr: 0xb0000104
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH0_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH0_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH0_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH0_NEXT(f1,v1) ( \
+ R_DMA_CH0_NEXT__WRITE(R_DMA_CH0_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH0_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH0_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH0_NEXT(f1,v1) ( \
+ (R_DMA_CH0_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_NEXT(f1,v1) ( \
+ (R_DMA_CH0_NEXT__next__##f1##__VAL(R_DMA_CH0_NEXT_, next_, v1) << R_DMA_CH0_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_NEXT_(f1_,v1) ( \
+ (R_DMA_CH0_NEXT__next__##f1_##_VAL(R_DMA_CH0_NEXT_, next_, v1) << R_DMA_CH0_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH0_STATUS
+ * - type: RO
+ * - addr: 0xb00001d2
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH0_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH0_STATUS(f1,v1) ( \
+ (R_DMA_CH0_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_STATUS(f1,v1) ( \
+ (R_DMA_CH0_STATUS__avail__##f1##__VAL(R_DMA_CH0_STATUS_, avail_, v1) << R_DMA_CH0_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH0_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH0_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH0_STATUS_(f1_,v1) ( \
+ (R_DMA_CH0_STATUS__avail__##f1_##_VAL(R_DMA_CH0_STATUS_, avail_, v1) << R_DMA_CH0_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH1_BUF
+ * - type: RW
+ * - addr: 0xb0000118
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH1_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH1_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH1_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH1_BUF(f1,v1) ( \
+ R_DMA_CH1_BUF__WRITE(R_DMA_CH1_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH1_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH1_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH1_BUF(f1,v1) ( \
+ (R_DMA_CH1_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_BUF(f1,v1) ( \
+ (R_DMA_CH1_BUF__buf__##f1##__VAL(R_DMA_CH1_BUF_, buf_, v1) << R_DMA_CH1_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_BUF_(f1_,v1) ( \
+ (R_DMA_CH1_BUF__buf__##f1_##_VAL(R_DMA_CH1_BUF_, buf_, v1) << R_DMA_CH1_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH1_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001d5
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH1_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH1_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH1_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH1_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH1_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH1_CLR_INTR_) \
+ REG_VAL__R_DMA_CH1_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH1_CLR_INTR__WRITE(R_DMA_CH1_CLR_INTR__ADDR, *R_DMA_CH1_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH1_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH1_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH1_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH1_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH1_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH1_CLR_INTR_) \
+ REG_VAL__R_DMA_CH1_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH1_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH1_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH1_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH1_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH1_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH1_CLR_INTR_, clr_eop_, v1) << R_DMA_CH1_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH1_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH1_CLR_INTR_, clr_descr_, v2) << R_DMA_CH1_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH1_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH1_CLR_INTR_, clr_eop_, v1) << R_DMA_CH1_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH1_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH1_CLR_INTR_, clr_descr_, v2) << R_DMA_CH1_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH1_CMD
+ * - type: RW
+ * - addr: 0xb00001d4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH1_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH1_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH1_CMD(f1,v1) ( \
+ R_DMA_CH1_CMD__WRITE(R_DMA_CH1_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH1_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH1_CMD(f1,v1) ( \
+ (R_DMA_CH1_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_CMD(f1,v1) ( \
+ (R_DMA_CH1_CMD__cmd__##f1##__VAL(R_DMA_CH1_CMD_, cmd_, v1) << R_DMA_CH1_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_CMD_(f1_,v1) ( \
+ (R_DMA_CH1_CMD__cmd__##f1_##_VAL(R_DMA_CH1_CMD_, cmd_, v1) << R_DMA_CH1_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH1_DESCR
+ * - type: RW
+ * - addr: 0xb000011c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH1_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH1_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH1_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH1_DESCR(f1,v1) ( \
+ R_DMA_CH1_DESCR__WRITE(R_DMA_CH1_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH1_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH1_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH1_DESCR(f1,v1) ( \
+ (R_DMA_CH1_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_DESCR(f1,v1) ( \
+ (R_DMA_CH1_DESCR__descr__##f1##__VAL(R_DMA_CH1_DESCR_, descr_, v1) << R_DMA_CH1_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_DESCR_(f1_,v1) ( \
+ (R_DMA_CH1_DESCR__descr__##f1_##_VAL(R_DMA_CH1_DESCR_, descr_, v1) << R_DMA_CH1_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH1_FIRST
+ * - type: RW
+ * - addr: 0xb00001a4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH1_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH1_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH1_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH1_FIRST(f1,v1) ( \
+ R_DMA_CH1_FIRST__WRITE(R_DMA_CH1_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH1_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH1_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH1_FIRST(f1,v1) ( \
+ (R_DMA_CH1_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_FIRST(f1,v1) ( \
+ (R_DMA_CH1_FIRST__first__##f1##__VAL(R_DMA_CH1_FIRST_, first_, v1) << R_DMA_CH1_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_FIRST_(f1_,v1) ( \
+ (R_DMA_CH1_FIRST__first__##f1_##_VAL(R_DMA_CH1_FIRST_, first_, v1) << R_DMA_CH1_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH1_HWSW
+ * - type: RW
+ * - addr: 0xb0000110
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH1_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH1_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH1_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH1_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH1_HWSW__WRITE(R_DMA_CH1_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH1_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH1_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH1_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH1_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH1_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH1_HWSW__hw__##f1##__VAL(R_DMA_CH1_HWSW_, hw_, v1) << R_DMA_CH1_HWSW__hw__BITNR) | \
+ (R_DMA_CH1_HWSW__sw__##f2##__VAL(R_DMA_CH1_HWSW_, sw_, v2) << R_DMA_CH1_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH1_HWSW__hw__##f1_##_VAL(R_DMA_CH1_HWSW_, hw_, v1) << R_DMA_CH1_HWSW__hw__BITNR) | \
+ (R_DMA_CH1_HWSW__sw__##f2_##_VAL(R_DMA_CH1_HWSW_, sw_, v2) << R_DMA_CH1_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH1_NEXT
+ * - type: RW
+ * - addr: 0xb0000114
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH1_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH1_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH1_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH1_NEXT(f1,v1) ( \
+ R_DMA_CH1_NEXT__WRITE(R_DMA_CH1_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH1_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH1_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH1_NEXT(f1,v1) ( \
+ (R_DMA_CH1_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_NEXT(f1,v1) ( \
+ (R_DMA_CH1_NEXT__next__##f1##__VAL(R_DMA_CH1_NEXT_, next_, v1) << R_DMA_CH1_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_NEXT_(f1_,v1) ( \
+ (R_DMA_CH1_NEXT__next__##f1_##_VAL(R_DMA_CH1_NEXT_, next_, v1) << R_DMA_CH1_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH1_STATUS
+ * - type: RO
+ * - addr: 0xb00001d6
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH1_STATUS(f1,v1) ( \
+ (R_DMA_CH1_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_STATUS(f1,v1) ( \
+ (R_DMA_CH1_STATUS__avail__##f1##__VAL(R_DMA_CH1_STATUS_, avail_, v1) << R_DMA_CH1_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH1_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH1_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH1_STATUS_(f1_,v1) ( \
+ (R_DMA_CH1_STATUS__avail__##f1_##_VAL(R_DMA_CH1_STATUS_, avail_, v1) << R_DMA_CH1_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH2_BUF
+ * - type: RW
+ * - addr: 0xb0000128
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH2_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH2_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH2_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH2_BUF(f1,v1) ( \
+ R_DMA_CH2_BUF__WRITE(R_DMA_CH2_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH2_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH2_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH2_BUF(f1,v1) ( \
+ (R_DMA_CH2_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_BUF(f1,v1) ( \
+ (R_DMA_CH2_BUF__buf__##f1##__VAL(R_DMA_CH2_BUF_, buf_, v1) << R_DMA_CH2_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_BUF_(f1_,v1) ( \
+ (R_DMA_CH2_BUF__buf__##f1_##_VAL(R_DMA_CH2_BUF_, buf_, v1) << R_DMA_CH2_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH2_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001d9
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH2_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH2_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH2_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH2_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH2_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH2_CLR_INTR_) \
+ REG_VAL__R_DMA_CH2_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH2_CLR_INTR__WRITE(R_DMA_CH2_CLR_INTR__ADDR, *R_DMA_CH2_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH2_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH2_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH2_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH2_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH2_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH2_CLR_INTR_) \
+ REG_VAL__R_DMA_CH2_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH2_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH2_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH2_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH2_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH2_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH2_CLR_INTR_, clr_eop_, v1) << R_DMA_CH2_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH2_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH2_CLR_INTR_, clr_descr_, v2) << R_DMA_CH2_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH2_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH2_CLR_INTR_, clr_eop_, v1) << R_DMA_CH2_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH2_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH2_CLR_INTR_, clr_descr_, v2) << R_DMA_CH2_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH2_CMD
+ * - type: RW
+ * - addr: 0xb00001d8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH2_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH2_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH2_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH2_CMD(f1,v1) ( \
+ R_DMA_CH2_CMD__WRITE(R_DMA_CH2_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH2_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH2_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH2_CMD(f1,v1) ( \
+ (R_DMA_CH2_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_CMD(f1,v1) ( \
+ (R_DMA_CH2_CMD__cmd__##f1##__VAL(R_DMA_CH2_CMD_, cmd_, v1) << R_DMA_CH2_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_CMD_(f1_,v1) ( \
+ (R_DMA_CH2_CMD__cmd__##f1_##_VAL(R_DMA_CH2_CMD_, cmd_, v1) << R_DMA_CH2_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH2_DESCR
+ * - type: RW
+ * - addr: 0xb000012c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH2_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH2_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH2_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH2_DESCR(f1,v1) ( \
+ R_DMA_CH2_DESCR__WRITE(R_DMA_CH2_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH2_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH2_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH2_DESCR(f1,v1) ( \
+ (R_DMA_CH2_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_DESCR(f1,v1) ( \
+ (R_DMA_CH2_DESCR__descr__##f1##__VAL(R_DMA_CH2_DESCR_, descr_, v1) << R_DMA_CH2_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_DESCR_(f1_,v1) ( \
+ (R_DMA_CH2_DESCR__descr__##f1_##_VAL(R_DMA_CH2_DESCR_, descr_, v1) << R_DMA_CH2_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH2_FIRST
+ * - type: RW
+ * - addr: 0xb00001a8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH2_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH2_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH2_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH2_FIRST(f1,v1) ( \
+ R_DMA_CH2_FIRST__WRITE(R_DMA_CH2_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH2_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH2_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH2_FIRST(f1,v1) ( \
+ (R_DMA_CH2_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_FIRST(f1,v1) ( \
+ (R_DMA_CH2_FIRST__first__##f1##__VAL(R_DMA_CH2_FIRST_, first_, v1) << R_DMA_CH2_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_FIRST_(f1_,v1) ( \
+ (R_DMA_CH2_FIRST__first__##f1_##_VAL(R_DMA_CH2_FIRST_, first_, v1) << R_DMA_CH2_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH2_HWSW
+ * - type: RW
+ * - addr: 0xb0000120
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH2_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH2_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH2_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH2_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH2_HWSW__WRITE(R_DMA_CH2_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH2_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH2_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH2_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH2_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH2_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH2_HWSW__hw__##f1##__VAL(R_DMA_CH2_HWSW_, hw_, v1) << R_DMA_CH2_HWSW__hw__BITNR) | \
+ (R_DMA_CH2_HWSW__sw__##f2##__VAL(R_DMA_CH2_HWSW_, sw_, v2) << R_DMA_CH2_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH2_HWSW__hw__##f1_##_VAL(R_DMA_CH2_HWSW_, hw_, v1) << R_DMA_CH2_HWSW__hw__BITNR) | \
+ (R_DMA_CH2_HWSW__sw__##f2_##_VAL(R_DMA_CH2_HWSW_, sw_, v2) << R_DMA_CH2_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH2_NEXT
+ * - type: RW
+ * - addr: 0xb0000124
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH2_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH2_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH2_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH2_NEXT(f1,v1) ( \
+ R_DMA_CH2_NEXT__WRITE(R_DMA_CH2_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH2_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH2_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH2_NEXT(f1,v1) ( \
+ (R_DMA_CH2_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_NEXT(f1,v1) ( \
+ (R_DMA_CH2_NEXT__next__##f1##__VAL(R_DMA_CH2_NEXT_, next_, v1) << R_DMA_CH2_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_NEXT_(f1_,v1) ( \
+ (R_DMA_CH2_NEXT__next__##f1_##_VAL(R_DMA_CH2_NEXT_, next_, v1) << R_DMA_CH2_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH2_STATUS
+ * - type: RO
+ * - addr: 0xb00001da
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH2_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH2_STATUS(f1,v1) ( \
+ (R_DMA_CH2_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_STATUS(f1,v1) ( \
+ (R_DMA_CH2_STATUS__avail__##f1##__VAL(R_DMA_CH2_STATUS_, avail_, v1) << R_DMA_CH2_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH2_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH2_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH2_STATUS_(f1_,v1) ( \
+ (R_DMA_CH2_STATUS__avail__##f1_##_VAL(R_DMA_CH2_STATUS_, avail_, v1) << R_DMA_CH2_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH3_BUF
+ * - type: RW
+ * - addr: 0xb0000138
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH3_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH3_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH3_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH3_BUF(f1,v1) ( \
+ R_DMA_CH3_BUF__WRITE(R_DMA_CH3_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH3_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH3_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH3_BUF(f1,v1) ( \
+ (R_DMA_CH3_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_BUF(f1,v1) ( \
+ (R_DMA_CH3_BUF__buf__##f1##__VAL(R_DMA_CH3_BUF_, buf_, v1) << R_DMA_CH3_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_BUF_(f1_,v1) ( \
+ (R_DMA_CH3_BUF__buf__##f1_##_VAL(R_DMA_CH3_BUF_, buf_, v1) << R_DMA_CH3_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH3_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001dd
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH3_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH3_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH3_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH3_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH3_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH3_CLR_INTR_) \
+ REG_VAL__R_DMA_CH3_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH3_CLR_INTR__WRITE(R_DMA_CH3_CLR_INTR__ADDR, *R_DMA_CH3_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH3_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH3_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH3_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH3_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH3_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH3_CLR_INTR_) \
+ REG_VAL__R_DMA_CH3_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH3_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH3_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH3_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH3_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH3_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH3_CLR_INTR_, clr_eop_, v1) << R_DMA_CH3_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH3_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH3_CLR_INTR_, clr_descr_, v2) << R_DMA_CH3_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH3_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH3_CLR_INTR_, clr_eop_, v1) << R_DMA_CH3_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH3_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH3_CLR_INTR_, clr_descr_, v2) << R_DMA_CH3_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH3_CMD
+ * - type: RW
+ * - addr: 0xb00001dc
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH3_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH3_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH3_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH3_CMD(f1,v1) ( \
+ R_DMA_CH3_CMD__WRITE(R_DMA_CH3_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH3_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH3_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH3_CMD(f1,v1) ( \
+ (R_DMA_CH3_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_CMD(f1,v1) ( \
+ (R_DMA_CH3_CMD__cmd__##f1##__VAL(R_DMA_CH3_CMD_, cmd_, v1) << R_DMA_CH3_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_CMD_(f1_,v1) ( \
+ (R_DMA_CH3_CMD__cmd__##f1_##_VAL(R_DMA_CH3_CMD_, cmd_, v1) << R_DMA_CH3_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH3_DESCR
+ * - type: RW
+ * - addr: 0xb000013c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH3_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH3_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH3_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH3_DESCR(f1,v1) ( \
+ R_DMA_CH3_DESCR__WRITE(R_DMA_CH3_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH3_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH3_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH3_DESCR(f1,v1) ( \
+ (R_DMA_CH3_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_DESCR(f1,v1) ( \
+ (R_DMA_CH3_DESCR__descr__##f1##__VAL(R_DMA_CH3_DESCR_, descr_, v1) << R_DMA_CH3_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_DESCR_(f1_,v1) ( \
+ (R_DMA_CH3_DESCR__descr__##f1_##_VAL(R_DMA_CH3_DESCR_, descr_, v1) << R_DMA_CH3_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH3_FIRST
+ * - type: RW
+ * - addr: 0xb00001ac
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH3_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH3_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH3_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH3_FIRST(f1,v1) ( \
+ R_DMA_CH3_FIRST__WRITE(R_DMA_CH3_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH3_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH3_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH3_FIRST(f1,v1) ( \
+ (R_DMA_CH3_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_FIRST(f1,v1) ( \
+ (R_DMA_CH3_FIRST__first__##f1##__VAL(R_DMA_CH3_FIRST_, first_, v1) << R_DMA_CH3_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_FIRST_(f1_,v1) ( \
+ (R_DMA_CH3_FIRST__first__##f1_##_VAL(R_DMA_CH3_FIRST_, first_, v1) << R_DMA_CH3_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH3_HWSW
+ * - type: RW
+ * - addr: 0xb0000130
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH3_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH3_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH3_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH3_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH3_HWSW__WRITE(R_DMA_CH3_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH3_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH3_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH3_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH3_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH3_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH3_HWSW__hw__##f1##__VAL(R_DMA_CH3_HWSW_, hw_, v1) << R_DMA_CH3_HWSW__hw__BITNR) | \
+ (R_DMA_CH3_HWSW__sw__##f2##__VAL(R_DMA_CH3_HWSW_, sw_, v2) << R_DMA_CH3_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH3_HWSW__hw__##f1_##_VAL(R_DMA_CH3_HWSW_, hw_, v1) << R_DMA_CH3_HWSW__hw__BITNR) | \
+ (R_DMA_CH3_HWSW__sw__##f2_##_VAL(R_DMA_CH3_HWSW_, sw_, v2) << R_DMA_CH3_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH3_NEXT
+ * - type: RW
+ * - addr: 0xb0000134
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH3_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH3_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH3_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH3_NEXT(f1,v1) ( \
+ R_DMA_CH3_NEXT__WRITE(R_DMA_CH3_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH3_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH3_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH3_NEXT(f1,v1) ( \
+ (R_DMA_CH3_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_NEXT(f1,v1) ( \
+ (R_DMA_CH3_NEXT__next__##f1##__VAL(R_DMA_CH3_NEXT_, next_, v1) << R_DMA_CH3_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_NEXT_(f1_,v1) ( \
+ (R_DMA_CH3_NEXT__next__##f1_##_VAL(R_DMA_CH3_NEXT_, next_, v1) << R_DMA_CH3_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH3_STATUS
+ * - type: RO
+ * - addr: 0xb00001de
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH3_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH3_STATUS(f1,v1) ( \
+ (R_DMA_CH3_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_STATUS(f1,v1) ( \
+ (R_DMA_CH3_STATUS__avail__##f1##__VAL(R_DMA_CH3_STATUS_, avail_, v1) << R_DMA_CH3_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH3_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH3_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH3_STATUS_(f1_,v1) ( \
+ (R_DMA_CH3_STATUS__avail__##f1_##_VAL(R_DMA_CH3_STATUS_, avail_, v1) << R_DMA_CH3_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH4_BUF
+ * - type: RW
+ * - addr: 0xb0000148
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH4_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH4_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH4_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH4_BUF(f1,v1) ( \
+ R_DMA_CH4_BUF__WRITE(R_DMA_CH4_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH4_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH4_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH4_BUF(f1,v1) ( \
+ (R_DMA_CH4_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_BUF(f1,v1) ( \
+ (R_DMA_CH4_BUF__buf__##f1##__VAL(R_DMA_CH4_BUF_, buf_, v1) << R_DMA_CH4_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_BUF_(f1_,v1) ( \
+ (R_DMA_CH4_BUF__buf__##f1_##_VAL(R_DMA_CH4_BUF_, buf_, v1) << R_DMA_CH4_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH4_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e1
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH4_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH4_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH4_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH4_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH4_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH4_CLR_INTR_) \
+ REG_VAL__R_DMA_CH4_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH4_CLR_INTR__WRITE(R_DMA_CH4_CLR_INTR__ADDR, *R_DMA_CH4_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH4_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH4_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH4_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH4_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH4_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH4_CLR_INTR_) \
+ REG_VAL__R_DMA_CH4_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH4_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH4_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH4_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH4_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH4_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH4_CLR_INTR_, clr_eop_, v1) << R_DMA_CH4_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH4_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH4_CLR_INTR_, clr_descr_, v2) << R_DMA_CH4_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH4_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH4_CLR_INTR_, clr_eop_, v1) << R_DMA_CH4_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH4_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH4_CLR_INTR_, clr_descr_, v2) << R_DMA_CH4_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH4_CMD
+ * - type: RW
+ * - addr: 0xb00001e0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH4_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH4_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH4_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH4_CMD(f1,v1) ( \
+ R_DMA_CH4_CMD__WRITE(R_DMA_CH4_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH4_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH4_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH4_CMD(f1,v1) ( \
+ (R_DMA_CH4_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_CMD(f1,v1) ( \
+ (R_DMA_CH4_CMD__cmd__##f1##__VAL(R_DMA_CH4_CMD_, cmd_, v1) << R_DMA_CH4_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_CMD_(f1_,v1) ( \
+ (R_DMA_CH4_CMD__cmd__##f1_##_VAL(R_DMA_CH4_CMD_, cmd_, v1) << R_DMA_CH4_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH4_DESCR
+ * - type: RW
+ * - addr: 0xb000014c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH4_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH4_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH4_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH4_DESCR(f1,v1) ( \
+ R_DMA_CH4_DESCR__WRITE(R_DMA_CH4_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH4_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH4_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH4_DESCR(f1,v1) ( \
+ (R_DMA_CH4_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_DESCR(f1,v1) ( \
+ (R_DMA_CH4_DESCR__descr__##f1##__VAL(R_DMA_CH4_DESCR_, descr_, v1) << R_DMA_CH4_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_DESCR_(f1_,v1) ( \
+ (R_DMA_CH4_DESCR__descr__##f1_##_VAL(R_DMA_CH4_DESCR_, descr_, v1) << R_DMA_CH4_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH4_FIRST
+ * - type: RW
+ * - addr: 0xb00001b0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH4_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH4_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH4_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH4_FIRST(f1,v1) ( \
+ R_DMA_CH4_FIRST__WRITE(R_DMA_CH4_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH4_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH4_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH4_FIRST(f1,v1) ( \
+ (R_DMA_CH4_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_FIRST(f1,v1) ( \
+ (R_DMA_CH4_FIRST__first__##f1##__VAL(R_DMA_CH4_FIRST_, first_, v1) << R_DMA_CH4_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_FIRST_(f1_,v1) ( \
+ (R_DMA_CH4_FIRST__first__##f1_##_VAL(R_DMA_CH4_FIRST_, first_, v1) << R_DMA_CH4_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH4_HWSW
+ * - type: RW
+ * - addr: 0xb0000140
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH4_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH4_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH4_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH4_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH4_HWSW__WRITE(R_DMA_CH4_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH4_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH4_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH4_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH4_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH4_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH4_HWSW__hw__##f1##__VAL(R_DMA_CH4_HWSW_, hw_, v1) << R_DMA_CH4_HWSW__hw__BITNR) | \
+ (R_DMA_CH4_HWSW__sw__##f2##__VAL(R_DMA_CH4_HWSW_, sw_, v2) << R_DMA_CH4_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH4_HWSW__hw__##f1_##_VAL(R_DMA_CH4_HWSW_, hw_, v1) << R_DMA_CH4_HWSW__hw__BITNR) | \
+ (R_DMA_CH4_HWSW__sw__##f2_##_VAL(R_DMA_CH4_HWSW_, sw_, v2) << R_DMA_CH4_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH4_NEXT
+ * - type: RW
+ * - addr: 0xb0000144
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH4_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH4_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH4_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH4_NEXT(f1,v1) ( \
+ R_DMA_CH4_NEXT__WRITE(R_DMA_CH4_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH4_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH4_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH4_NEXT(f1,v1) ( \
+ (R_DMA_CH4_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_NEXT(f1,v1) ( \
+ (R_DMA_CH4_NEXT__next__##f1##__VAL(R_DMA_CH4_NEXT_, next_, v1) << R_DMA_CH4_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_NEXT_(f1_,v1) ( \
+ (R_DMA_CH4_NEXT__next__##f1_##_VAL(R_DMA_CH4_NEXT_, next_, v1) << R_DMA_CH4_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH4_STATUS
+ * - type: RO
+ * - addr: 0xb00001e2
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH4_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH4_STATUS(f1,v1) ( \
+ (R_DMA_CH4_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_STATUS(f1,v1) ( \
+ (R_DMA_CH4_STATUS__avail__##f1##__VAL(R_DMA_CH4_STATUS_, avail_, v1) << R_DMA_CH4_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH4_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH4_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH4_STATUS_(f1_,v1) ( \
+ (R_DMA_CH4_STATUS__avail__##f1_##_VAL(R_DMA_CH4_STATUS_, avail_, v1) << R_DMA_CH4_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH5_BUF
+ * - type: RW
+ * - addr: 0xb0000158
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH5_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH5_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH5_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH5_BUF(f1,v1) ( \
+ R_DMA_CH5_BUF__WRITE(R_DMA_CH5_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH5_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH5_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH5_BUF(f1,v1) ( \
+ (R_DMA_CH5_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_BUF(f1,v1) ( \
+ (R_DMA_CH5_BUF__buf__##f1##__VAL(R_DMA_CH5_BUF_, buf_, v1) << R_DMA_CH5_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_BUF_(f1_,v1) ( \
+ (R_DMA_CH5_BUF__buf__##f1_##_VAL(R_DMA_CH5_BUF_, buf_, v1) << R_DMA_CH5_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH5_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e5
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH5_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH5_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH5_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH5_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH5_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH5_CLR_INTR_) \
+ REG_VAL__R_DMA_CH5_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH5_CLR_INTR__WRITE(R_DMA_CH5_CLR_INTR__ADDR, *R_DMA_CH5_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH5_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH5_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH5_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH5_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH5_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH5_CLR_INTR_) \
+ REG_VAL__R_DMA_CH5_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH5_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH5_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH5_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH5_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH5_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH5_CLR_INTR_, clr_eop_, v1) << R_DMA_CH5_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH5_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH5_CLR_INTR_, clr_descr_, v2) << R_DMA_CH5_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH5_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH5_CLR_INTR_, clr_eop_, v1) << R_DMA_CH5_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH5_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH5_CLR_INTR_, clr_descr_, v2) << R_DMA_CH5_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH5_CMD
+ * - type: RW
+ * - addr: 0xb00001e4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH5_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH5_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH5_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH5_CMD(f1,v1) ( \
+ R_DMA_CH5_CMD__WRITE(R_DMA_CH5_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH5_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH5_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH5_CMD(f1,v1) ( \
+ (R_DMA_CH5_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_CMD(f1,v1) ( \
+ (R_DMA_CH5_CMD__cmd__##f1##__VAL(R_DMA_CH5_CMD_, cmd_, v1) << R_DMA_CH5_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_CMD_(f1_,v1) ( \
+ (R_DMA_CH5_CMD__cmd__##f1_##_VAL(R_DMA_CH5_CMD_, cmd_, v1) << R_DMA_CH5_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH5_DESCR
+ * - type: RW
+ * - addr: 0xb000015c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH5_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH5_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH5_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH5_DESCR(f1,v1) ( \
+ R_DMA_CH5_DESCR__WRITE(R_DMA_CH5_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH5_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH5_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH5_DESCR(f1,v1) ( \
+ (R_DMA_CH5_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_DESCR(f1,v1) ( \
+ (R_DMA_CH5_DESCR__descr__##f1##__VAL(R_DMA_CH5_DESCR_, descr_, v1) << R_DMA_CH5_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_DESCR_(f1_,v1) ( \
+ (R_DMA_CH5_DESCR__descr__##f1_##_VAL(R_DMA_CH5_DESCR_, descr_, v1) << R_DMA_CH5_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH5_FIRST
+ * - type: RW
+ * - addr: 0xb00001b4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH5_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH5_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH5_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH5_FIRST(f1,v1) ( \
+ R_DMA_CH5_FIRST__WRITE(R_DMA_CH5_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH5_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH5_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH5_FIRST(f1,v1) ( \
+ (R_DMA_CH5_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_FIRST(f1,v1) ( \
+ (R_DMA_CH5_FIRST__first__##f1##__VAL(R_DMA_CH5_FIRST_, first_, v1) << R_DMA_CH5_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_FIRST_(f1_,v1) ( \
+ (R_DMA_CH5_FIRST__first__##f1_##_VAL(R_DMA_CH5_FIRST_, first_, v1) << R_DMA_CH5_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH5_HWSW
+ * - type: RW
+ * - addr: 0xb0000150
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH5_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH5_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH5_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH5_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH5_HWSW__WRITE(R_DMA_CH5_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH5_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH5_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH5_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH5_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH5_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH5_HWSW__hw__##f1##__VAL(R_DMA_CH5_HWSW_, hw_, v1) << R_DMA_CH5_HWSW__hw__BITNR) | \
+ (R_DMA_CH5_HWSW__sw__##f2##__VAL(R_DMA_CH5_HWSW_, sw_, v2) << R_DMA_CH5_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH5_HWSW__hw__##f1_##_VAL(R_DMA_CH5_HWSW_, hw_, v1) << R_DMA_CH5_HWSW__hw__BITNR) | \
+ (R_DMA_CH5_HWSW__sw__##f2_##_VAL(R_DMA_CH5_HWSW_, sw_, v2) << R_DMA_CH5_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH5_NEXT
+ * - type: RW
+ * - addr: 0xb0000154
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH5_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH5_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH5_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH5_NEXT(f1,v1) ( \
+ R_DMA_CH5_NEXT__WRITE(R_DMA_CH5_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH5_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH5_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH5_NEXT(f1,v1) ( \
+ (R_DMA_CH5_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_NEXT(f1,v1) ( \
+ (R_DMA_CH5_NEXT__next__##f1##__VAL(R_DMA_CH5_NEXT_, next_, v1) << R_DMA_CH5_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_NEXT_(f1_,v1) ( \
+ (R_DMA_CH5_NEXT__next__##f1_##_VAL(R_DMA_CH5_NEXT_, next_, v1) << R_DMA_CH5_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH5_STATUS
+ * - type: RO
+ * - addr: 0xb00001e6
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH5_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH5_STATUS(f1,v1) ( \
+ (R_DMA_CH5_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_STATUS(f1,v1) ( \
+ (R_DMA_CH5_STATUS__avail__##f1##__VAL(R_DMA_CH5_STATUS_, avail_, v1) << R_DMA_CH5_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH5_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH5_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH5_STATUS_(f1_,v1) ( \
+ (R_DMA_CH5_STATUS__avail__##f1_##_VAL(R_DMA_CH5_STATUS_, avail_, v1) << R_DMA_CH5_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH6_BUF
+ * - type: RW
+ * - addr: 0xb0000168
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH6_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH6_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH6_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH6_BUF(f1,v1) ( \
+ R_DMA_CH6_BUF__WRITE(R_DMA_CH6_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH6_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH6_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH6_BUF(f1,v1) ( \
+ (R_DMA_CH6_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_BUF(f1,v1) ( \
+ (R_DMA_CH6_BUF__buf__##f1##__VAL(R_DMA_CH6_BUF_, buf_, v1) << R_DMA_CH6_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_BUF_(f1_,v1) ( \
+ (R_DMA_CH6_BUF__buf__##f1_##_VAL(R_DMA_CH6_BUF_, buf_, v1) << R_DMA_CH6_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH6_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e9
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH6_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH6_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH6_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH6_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH6_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH6_CLR_INTR_) \
+ REG_VAL__R_DMA_CH6_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH6_CLR_INTR__WRITE(R_DMA_CH6_CLR_INTR__ADDR, *R_DMA_CH6_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH6_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH6_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH6_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH6_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH6_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH6_CLR_INTR_) \
+ REG_VAL__R_DMA_CH6_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH6_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH6_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH6_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH6_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH6_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH6_CLR_INTR_, clr_eop_, v1) << R_DMA_CH6_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH6_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH6_CLR_INTR_, clr_descr_, v2) << R_DMA_CH6_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH6_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH6_CLR_INTR_, clr_eop_, v1) << R_DMA_CH6_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH6_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH6_CLR_INTR_, clr_descr_, v2) << R_DMA_CH6_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH6_CMD
+ * - type: RW
+ * - addr: 0xb00001e8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH6_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH6_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH6_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH6_CMD(f1,v1) ( \
+ R_DMA_CH6_CMD__WRITE(R_DMA_CH6_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH6_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH6_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH6_CMD(f1,v1) ( \
+ (R_DMA_CH6_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_CMD(f1,v1) ( \
+ (R_DMA_CH6_CMD__cmd__##f1##__VAL(R_DMA_CH6_CMD_, cmd_, v1) << R_DMA_CH6_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_CMD_(f1_,v1) ( \
+ (R_DMA_CH6_CMD__cmd__##f1_##_VAL(R_DMA_CH6_CMD_, cmd_, v1) << R_DMA_CH6_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH6_DESCR
+ * - type: RW
+ * - addr: 0xb000016c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH6_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH6_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH6_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH6_DESCR(f1,v1) ( \
+ R_DMA_CH6_DESCR__WRITE(R_DMA_CH6_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH6_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH6_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH6_DESCR(f1,v1) ( \
+ (R_DMA_CH6_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_DESCR(f1,v1) ( \
+ (R_DMA_CH6_DESCR__descr__##f1##__VAL(R_DMA_CH6_DESCR_, descr_, v1) << R_DMA_CH6_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_DESCR_(f1_,v1) ( \
+ (R_DMA_CH6_DESCR__descr__##f1_##_VAL(R_DMA_CH6_DESCR_, descr_, v1) << R_DMA_CH6_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH6_FIRST
+ * - type: RW
+ * - addr: 0xb00001b8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH6_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH6_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH6_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH6_FIRST(f1,v1) ( \
+ R_DMA_CH6_FIRST__WRITE(R_DMA_CH6_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH6_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH6_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH6_FIRST(f1,v1) ( \
+ (R_DMA_CH6_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_FIRST(f1,v1) ( \
+ (R_DMA_CH6_FIRST__first__##f1##__VAL(R_DMA_CH6_FIRST_, first_, v1) << R_DMA_CH6_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_FIRST_(f1_,v1) ( \
+ (R_DMA_CH6_FIRST__first__##f1_##_VAL(R_DMA_CH6_FIRST_, first_, v1) << R_DMA_CH6_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH6_HWSW
+ * - type: RW
+ * - addr: 0xb0000160
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH6_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH6_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH6_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH6_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH6_HWSW__WRITE(R_DMA_CH6_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH6_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH6_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH6_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH6_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH6_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH6_HWSW__hw__##f1##__VAL(R_DMA_CH6_HWSW_, hw_, v1) << R_DMA_CH6_HWSW__hw__BITNR) | \
+ (R_DMA_CH6_HWSW__sw__##f2##__VAL(R_DMA_CH6_HWSW_, sw_, v2) << R_DMA_CH6_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH6_HWSW__hw__##f1_##_VAL(R_DMA_CH6_HWSW_, hw_, v1) << R_DMA_CH6_HWSW__hw__BITNR) | \
+ (R_DMA_CH6_HWSW__sw__##f2_##_VAL(R_DMA_CH6_HWSW_, sw_, v2) << R_DMA_CH6_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH6_NEXT
+ * - type: RW
+ * - addr: 0xb0000164
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH6_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH6_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH6_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH6_NEXT(f1,v1) ( \
+ R_DMA_CH6_NEXT__WRITE(R_DMA_CH6_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH6_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH6_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH6_NEXT(f1,v1) ( \
+ (R_DMA_CH6_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_NEXT(f1,v1) ( \
+ (R_DMA_CH6_NEXT__next__##f1##__VAL(R_DMA_CH6_NEXT_, next_, v1) << R_DMA_CH6_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_NEXT_(f1_,v1) ( \
+ (R_DMA_CH6_NEXT__next__##f1_##_VAL(R_DMA_CH6_NEXT_, next_, v1) << R_DMA_CH6_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH6_STATUS
+ * - type: RO
+ * - addr: 0xb00001ea
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH6_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH6_STATUS(f1,v1) ( \
+ (R_DMA_CH6_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_STATUS(f1,v1) ( \
+ (R_DMA_CH6_STATUS__avail__##f1##__VAL(R_DMA_CH6_STATUS_, avail_, v1) << R_DMA_CH6_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH6_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH6_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH6_STATUS_(f1_,v1) ( \
+ (R_DMA_CH6_STATUS__avail__##f1_##_VAL(R_DMA_CH6_STATUS_, avail_, v1) << R_DMA_CH6_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH7_BUF
+ * - type: RW
+ * - addr: 0xb0000178
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH7_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH7_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH7_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH7_BUF(f1,v1) ( \
+ R_DMA_CH7_BUF__WRITE(R_DMA_CH7_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH7_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH7_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH7_BUF(f1,v1) ( \
+ (R_DMA_CH7_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_BUF(f1,v1) ( \
+ (R_DMA_CH7_BUF__buf__##f1##__VAL(R_DMA_CH7_BUF_, buf_, v1) << R_DMA_CH7_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_BUF_(f1_,v1) ( \
+ (R_DMA_CH7_BUF__buf__##f1_##_VAL(R_DMA_CH7_BUF_, buf_, v1) << R_DMA_CH7_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH7_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001ed
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH7_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH7_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH7_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH7_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH7_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH7_CLR_INTR_) \
+ REG_VAL__R_DMA_CH7_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH7_CLR_INTR__WRITE(R_DMA_CH7_CLR_INTR__ADDR, *R_DMA_CH7_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH7_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH7_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH7_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH7_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH7_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH7_CLR_INTR_) \
+ REG_VAL__R_DMA_CH7_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH7_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH7_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH7_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH7_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH7_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH7_CLR_INTR_, clr_eop_, v1) << R_DMA_CH7_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH7_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH7_CLR_INTR_, clr_descr_, v2) << R_DMA_CH7_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH7_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH7_CLR_INTR_, clr_eop_, v1) << R_DMA_CH7_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH7_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH7_CLR_INTR_, clr_descr_, v2) << R_DMA_CH7_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH7_CMD
+ * - type: RW
+ * - addr: 0xb00001ec
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH7_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH7_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH7_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH7_CMD(f1,v1) ( \
+ R_DMA_CH7_CMD__WRITE(R_DMA_CH7_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH7_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH7_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH7_CMD(f1,v1) ( \
+ (R_DMA_CH7_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_CMD(f1,v1) ( \
+ (R_DMA_CH7_CMD__cmd__##f1##__VAL(R_DMA_CH7_CMD_, cmd_, v1) << R_DMA_CH7_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_CMD_(f1_,v1) ( \
+ (R_DMA_CH7_CMD__cmd__##f1_##_VAL(R_DMA_CH7_CMD_, cmd_, v1) << R_DMA_CH7_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH7_DESCR
+ * - type: RW
+ * - addr: 0xb000017c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH7_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH7_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH7_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH7_DESCR(f1,v1) ( \
+ R_DMA_CH7_DESCR__WRITE(R_DMA_CH7_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH7_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH7_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH7_DESCR(f1,v1) ( \
+ (R_DMA_CH7_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_DESCR(f1,v1) ( \
+ (R_DMA_CH7_DESCR__descr__##f1##__VAL(R_DMA_CH7_DESCR_, descr_, v1) << R_DMA_CH7_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_DESCR_(f1_,v1) ( \
+ (R_DMA_CH7_DESCR__descr__##f1_##_VAL(R_DMA_CH7_DESCR_, descr_, v1) << R_DMA_CH7_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH7_FIRST
+ * - type: RW
+ * - addr: 0xb00001bc
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH7_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH7_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH7_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH7_FIRST(f1,v1) ( \
+ R_DMA_CH7_FIRST__WRITE(R_DMA_CH7_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH7_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH7_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH7_FIRST(f1,v1) ( \
+ (R_DMA_CH7_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_FIRST(f1,v1) ( \
+ (R_DMA_CH7_FIRST__first__##f1##__VAL(R_DMA_CH7_FIRST_, first_, v1) << R_DMA_CH7_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_FIRST_(f1_,v1) ( \
+ (R_DMA_CH7_FIRST__first__##f1_##_VAL(R_DMA_CH7_FIRST_, first_, v1) << R_DMA_CH7_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH7_HWSW
+ * - type: RW
+ * - addr: 0xb0000170
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH7_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH7_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH7_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH7_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH7_HWSW__WRITE(R_DMA_CH7_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH7_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH7_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH7_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH7_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH7_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH7_HWSW__hw__##f1##__VAL(R_DMA_CH7_HWSW_, hw_, v1) << R_DMA_CH7_HWSW__hw__BITNR) | \
+ (R_DMA_CH7_HWSW__sw__##f2##__VAL(R_DMA_CH7_HWSW_, sw_, v2) << R_DMA_CH7_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH7_HWSW__hw__##f1_##_VAL(R_DMA_CH7_HWSW_, hw_, v1) << R_DMA_CH7_HWSW__hw__BITNR) | \
+ (R_DMA_CH7_HWSW__sw__##f2_##_VAL(R_DMA_CH7_HWSW_, sw_, v2) << R_DMA_CH7_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH7_NEXT
+ * - type: RW
+ * - addr: 0xb0000174
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH7_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH7_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH7_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH7_NEXT(f1,v1) ( \
+ R_DMA_CH7_NEXT__WRITE(R_DMA_CH7_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH7_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH7_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH7_NEXT(f1,v1) ( \
+ (R_DMA_CH7_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_NEXT(f1,v1) ( \
+ (R_DMA_CH7_NEXT__next__##f1##__VAL(R_DMA_CH7_NEXT_, next_, v1) << R_DMA_CH7_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_NEXT_(f1_,v1) ( \
+ (R_DMA_CH7_NEXT__next__##f1_##_VAL(R_DMA_CH7_NEXT_, next_, v1) << R_DMA_CH7_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH7_STATUS
+ * - type: RO
+ * - addr: 0xb00001ee
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH7_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH7_STATUS(f1,v1) ( \
+ (R_DMA_CH7_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_STATUS(f1,v1) ( \
+ (R_DMA_CH7_STATUS__avail__##f1##__VAL(R_DMA_CH7_STATUS_, avail_, v1) << R_DMA_CH7_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH7_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH7_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH7_STATUS_(f1_,v1) ( \
+ (R_DMA_CH7_STATUS__avail__##f1_##_VAL(R_DMA_CH7_STATUS_, avail_, v1) << R_DMA_CH7_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_BUF
+ * - type: RW
+ * - addr: 0xb0000188
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_BUF(f1,v1) ( \
+ R_DMA_CH8_BUF__WRITE(R_DMA_CH8_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH8_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_BUF(f1,v1) ( \
+ (R_DMA_CH8_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_BUF(f1,v1) ( \
+ (R_DMA_CH8_BUF__buf__##f1##__VAL(R_DMA_CH8_BUF_, buf_, v1) << R_DMA_CH8_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_BUF_(f1_,v1) ( \
+ (R_DMA_CH8_BUF__buf__##f1_##_VAL(R_DMA_CH8_BUF_, buf_, v1) << R_DMA_CH8_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001f1
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH8_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH8_CLR_INTR__WRITE(R_DMA_CH8_CLR_INTR__ADDR, *R_DMA_CH8_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH8_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH8_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH8_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH8_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH8_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH8_CLR_INTR_, clr_eop_, v1) << R_DMA_CH8_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH8_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH8_CLR_INTR_, clr_descr_, v2) << R_DMA_CH8_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH8_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH8_CLR_INTR_, clr_eop_, v1) << R_DMA_CH8_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH8_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH8_CLR_INTR_, clr_descr_, v2) << R_DMA_CH8_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_CMD
+ * - type: RW
+ * - addr: 0xb00001f0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_CMD(f1,v1) ( \
+ R_DMA_CH8_CMD__WRITE(R_DMA_CH8_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH8_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_CMD(f1,v1) ( \
+ (R_DMA_CH8_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_CMD(f1,v1) ( \
+ (R_DMA_CH8_CMD__cmd__##f1##__VAL(R_DMA_CH8_CMD_, cmd_, v1) << R_DMA_CH8_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_CMD_(f1_,v1) ( \
+ (R_DMA_CH8_CMD__cmd__##f1_##_VAL(R_DMA_CH8_CMD_, cmd_, v1) << R_DMA_CH8_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_DESCR
+ * - type: RW
+ * - addr: 0xb000018c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_DESCR(f1,v1) ( \
+ R_DMA_CH8_DESCR__WRITE(R_DMA_CH8_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH8_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_DESCR(f1,v1) ( \
+ (R_DMA_CH8_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_DESCR(f1,v1) ( \
+ (R_DMA_CH8_DESCR__descr__##f1##__VAL(R_DMA_CH8_DESCR_, descr_, v1) << R_DMA_CH8_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_DESCR_(f1_,v1) ( \
+ (R_DMA_CH8_DESCR__descr__##f1_##_VAL(R_DMA_CH8_DESCR_, descr_, v1) << R_DMA_CH8_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_FIRST
+ * - type: RW
+ * - addr: 0xb00001c0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_FIRST(f1,v1) ( \
+ R_DMA_CH8_FIRST__WRITE(R_DMA_CH8_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH8_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_FIRST(f1,v1) ( \
+ (R_DMA_CH8_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_FIRST(f1,v1) ( \
+ (R_DMA_CH8_FIRST__first__##f1##__VAL(R_DMA_CH8_FIRST_, first_, v1) << R_DMA_CH8_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_FIRST_(f1_,v1) ( \
+ (R_DMA_CH8_FIRST__first__##f1_##_VAL(R_DMA_CH8_FIRST_, first_, v1) << R_DMA_CH8_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_HWSW
+ * - type: RW
+ * - addr: 0xb0000180
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH8_HWSW__WRITE(R_DMA_CH8_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH8_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH8_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH8_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH8_HWSW__hw__##f1##__VAL(R_DMA_CH8_HWSW_, hw_, v1) << R_DMA_CH8_HWSW__hw__BITNR) | \
+ (R_DMA_CH8_HWSW__sw__##f2##__VAL(R_DMA_CH8_HWSW_, sw_, v2) << R_DMA_CH8_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH8_HWSW__hw__##f1_##_VAL(R_DMA_CH8_HWSW_, hw_, v1) << R_DMA_CH8_HWSW__hw__BITNR) | \
+ (R_DMA_CH8_HWSW__sw__##f2_##_VAL(R_DMA_CH8_HWSW_, sw_, v2) << R_DMA_CH8_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_NEP
+ * - type: RW
+ * - addr: 0xb00001c0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_NEP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_NEP.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_NEP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_NEP(f1,v1) ( \
+ R_DMA_CH8_NEP__WRITE(R_DMA_CH8_NEP__ADDR, ( \
+ REG_VAL__R_DMA_CH8_NEP_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_NEP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_NEP(f1,v1) ( \
+ (R_DMA_CH8_NEP__nep__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_NEP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_NEP.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_NEP(f1,v1) ( \
+ (R_DMA_CH8_NEP__nep__##f1##__VAL(R_DMA_CH8_NEP_, nep_, v1) << R_DMA_CH8_NEP__nep__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_NEP_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_NEP.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_NEP_(f1_,v1) ( \
+ (R_DMA_CH8_NEP__nep__##f1_##_VAL(R_DMA_CH8_NEP_, nep_, v1) << R_DMA_CH8_NEP__nep__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_NEXT
+ * - type: RW
+ * - addr: 0xb0000184
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_NEXT(f1,v1) ( \
+ R_DMA_CH8_NEXT__WRITE(R_DMA_CH8_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH8_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_NEXT(f1,v1) ( \
+ (R_DMA_CH8_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_NEXT(f1,v1) ( \
+ (R_DMA_CH8_NEXT__next__##f1##__VAL(R_DMA_CH8_NEXT_, next_, v1) << R_DMA_CH8_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_NEXT_(f1_,v1) ( \
+ (R_DMA_CH8_NEXT__next__##f1_##_VAL(R_DMA_CH8_NEXT_, next_, v1) << R_DMA_CH8_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_STATUS
+ * - type: RO
+ * - addr: 0xb00001f2
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_STATUS(f1,v1) ( \
+ (R_DMA_CH8_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_STATUS(f1,v1) ( \
+ (R_DMA_CH8_STATUS__avail__##f1##__VAL(R_DMA_CH8_STATUS_, avail_, v1) << R_DMA_CH8_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_STATUS_(f1_,v1) ( \
+ (R_DMA_CH8_STATUS__avail__##f1_##_VAL(R_DMA_CH8_STATUS_, avail_, v1) << R_DMA_CH8_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB
+ * - type: RW
+ * - addr: 0xb000018c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB(f1,v1) ( \
+ R_DMA_CH8_SUB__WRITE(R_DMA_CH8_SUB__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB(f1,v1) ( \
+ (R_DMA_CH8_SUB__sub__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB(f1,v1) ( \
+ (R_DMA_CH8_SUB__sub__##f1##__VAL(R_DMA_CH8_SUB_, sub_, v1) << R_DMA_CH8_SUB__sub__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB_(f1_,v1) ( \
+ (R_DMA_CH8_SUB__sub__##f1_##_VAL(R_DMA_CH8_SUB_, sub_, v1) << R_DMA_CH8_SUB__sub__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB0_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e3
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB0_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB0_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB0_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB0_CLR_INTR(f1,v1) ( \
+ *R_DMA_CH8_SUB0_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_SUB0_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_SUB0_CLR_INTR_(f1##_,v1) \
+ ), \
+ R_DMA_CH8_SUB0_CLR_INTR__WRITE(R_DMA_CH8_SUB0_CLR_INTR__ADDR, *R_DMA_CH8_SUB0_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB0_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB0_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH8_SUB0_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB0_CLR_INTR__SHADOW(f1,v1) ( \
+ *R_DMA_CH8_SUB0_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_SUB0_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_SUB0_CLR_INTR_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB0_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB0_CLR_INTR(f1,v1) ( \
+ (R_DMA_CH8_SUB0_CLR_INTR__clr_descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB0_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB0_CLR_INTR(f1,v1) ( \
+ (R_DMA_CH8_SUB0_CLR_INTR__clr_descr__##f1##__VAL(R_DMA_CH8_SUB0_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB0_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB0_CLR_INTR_(f1_,v1) ( \
+ (R_DMA_CH8_SUB0_CLR_INTR__clr_descr__##f1_##_VAL(R_DMA_CH8_SUB0_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB0_CMD
+ * - type: RW
+ * - addr: 0xb00001d3
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB0_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB0_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB0_CMD(f1,v1) ( \
+ R_DMA_CH8_SUB0_CMD__WRITE(R_DMA_CH8_SUB0_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB0_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB0_CMD(f1,v1) ( \
+ (R_DMA_CH8_SUB0_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB0_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB0_CMD(f1,v1) ( \
+ (R_DMA_CH8_SUB0_CMD__cmd__##f1##__VAL(R_DMA_CH8_SUB0_CMD_, cmd_, v1) << R_DMA_CH8_SUB0_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB0_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB0_CMD_(f1_,v1) ( \
+ (R_DMA_CH8_SUB0_CMD__cmd__##f1_##_VAL(R_DMA_CH8_SUB0_CMD_, cmd_, v1) << R_DMA_CH8_SUB0_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB0_EP
+ * - type: RW
+ * - addr: 0xb00001c8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB0_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB0_EP.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB0_EP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB0_EP(f1,v1) ( \
+ R_DMA_CH8_SUB0_EP__WRITE(R_DMA_CH8_SUB0_EP__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB0_EP_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB0_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB0_EP(f1,v1) ( \
+ (R_DMA_CH8_SUB0_EP__ep__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB0_EP.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB0_EP(f1,v1) ( \
+ (R_DMA_CH8_SUB0_EP__ep__##f1##__VAL(R_DMA_CH8_SUB0_EP_, ep_, v1) << R_DMA_CH8_SUB0_EP__ep__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB0_EP_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB0_EP.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB0_EP_(f1_,v1) ( \
+ (R_DMA_CH8_SUB0_EP__ep__##f1_##_VAL(R_DMA_CH8_SUB0_EP_, ep_, v1) << R_DMA_CH8_SUB0_EP__ep__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB1_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e7
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB1_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB1_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB1_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB1_CLR_INTR(f1,v1) ( \
+ *R_DMA_CH8_SUB1_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_SUB1_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_SUB1_CLR_INTR_(f1##_,v1) \
+ ), \
+ R_DMA_CH8_SUB1_CLR_INTR__WRITE(R_DMA_CH8_SUB1_CLR_INTR__ADDR, *R_DMA_CH8_SUB1_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB1_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB1_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH8_SUB1_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB1_CLR_INTR__SHADOW(f1,v1) ( \
+ *R_DMA_CH8_SUB1_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_SUB1_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_SUB1_CLR_INTR_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB1_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB1_CLR_INTR(f1,v1) ( \
+ (R_DMA_CH8_SUB1_CLR_INTR__clr_descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB1_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB1_CLR_INTR(f1,v1) ( \
+ (R_DMA_CH8_SUB1_CLR_INTR__clr_descr__##f1##__VAL(R_DMA_CH8_SUB1_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB1_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB1_CLR_INTR_(f1_,v1) ( \
+ (R_DMA_CH8_SUB1_CLR_INTR__clr_descr__##f1_##_VAL(R_DMA_CH8_SUB1_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB1_CMD
+ * - type: RW
+ * - addr: 0xb00001d7
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB1_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB1_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB1_CMD(f1,v1) ( \
+ R_DMA_CH8_SUB1_CMD__WRITE(R_DMA_CH8_SUB1_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB1_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB1_CMD(f1,v1) ( \
+ (R_DMA_CH8_SUB1_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB1_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB1_CMD(f1,v1) ( \
+ (R_DMA_CH8_SUB1_CMD__cmd__##f1##__VAL(R_DMA_CH8_SUB1_CMD_, cmd_, v1) << R_DMA_CH8_SUB1_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB1_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB1_CMD_(f1_,v1) ( \
+ (R_DMA_CH8_SUB1_CMD__cmd__##f1_##_VAL(R_DMA_CH8_SUB1_CMD_, cmd_, v1) << R_DMA_CH8_SUB1_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB1_EP
+ * - type: RW
+ * - addr: 0xb00001cc
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB1_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB1_EP.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB1_EP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB1_EP(f1,v1) ( \
+ R_DMA_CH8_SUB1_EP__WRITE(R_DMA_CH8_SUB1_EP__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB1_EP_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB1_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB1_EP(f1,v1) ( \
+ (R_DMA_CH8_SUB1_EP__ep__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB1_EP.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB1_EP(f1,v1) ( \
+ (R_DMA_CH8_SUB1_EP__ep__##f1##__VAL(R_DMA_CH8_SUB1_EP_, ep_, v1) << R_DMA_CH8_SUB1_EP__ep__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB1_EP_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB1_EP.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB1_EP_(f1_,v1) ( \
+ (R_DMA_CH8_SUB1_EP__ep__##f1_##_VAL(R_DMA_CH8_SUB1_EP_, ep_, v1) << R_DMA_CH8_SUB1_EP__ep__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB2_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001eb
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB2_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB2_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB2_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB2_CLR_INTR(f1,v1) ( \
+ *R_DMA_CH8_SUB2_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_SUB2_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_SUB2_CLR_INTR_(f1##_,v1) \
+ ), \
+ R_DMA_CH8_SUB2_CLR_INTR__WRITE(R_DMA_CH8_SUB2_CLR_INTR__ADDR, *R_DMA_CH8_SUB2_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB2_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB2_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH8_SUB2_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB2_CLR_INTR__SHADOW(f1,v1) ( \
+ *R_DMA_CH8_SUB2_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_SUB2_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_SUB2_CLR_INTR_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB2_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB2_CLR_INTR(f1,v1) ( \
+ (R_DMA_CH8_SUB2_CLR_INTR__clr_descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB2_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB2_CLR_INTR(f1,v1) ( \
+ (R_DMA_CH8_SUB2_CLR_INTR__clr_descr__##f1##__VAL(R_DMA_CH8_SUB2_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB2_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB2_CLR_INTR_(f1_,v1) ( \
+ (R_DMA_CH8_SUB2_CLR_INTR__clr_descr__##f1_##_VAL(R_DMA_CH8_SUB2_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB2_CMD
+ * - type: RW
+ * - addr: 0xb00001db
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB2_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB2_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB2_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB2_CMD(f1,v1) ( \
+ R_DMA_CH8_SUB2_CMD__WRITE(R_DMA_CH8_SUB2_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB2_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB2_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB2_CMD(f1,v1) ( \
+ (R_DMA_CH8_SUB2_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB2_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB2_CMD(f1,v1) ( \
+ (R_DMA_CH8_SUB2_CMD__cmd__##f1##__VAL(R_DMA_CH8_SUB2_CMD_, cmd_, v1) << R_DMA_CH8_SUB2_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB2_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB2_CMD_(f1_,v1) ( \
+ (R_DMA_CH8_SUB2_CMD__cmd__##f1_##_VAL(R_DMA_CH8_SUB2_CMD_, cmd_, v1) << R_DMA_CH8_SUB2_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB2_EP
+ * - type: RW
+ * - addr: 0xb00001f8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB2_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB2_EP.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB2_EP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB2_EP(f1,v1) ( \
+ R_DMA_CH8_SUB2_EP__WRITE(R_DMA_CH8_SUB2_EP__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB2_EP_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB2_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB2_EP(f1,v1) ( \
+ (R_DMA_CH8_SUB2_EP__ep__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB2_EP.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB2_EP(f1,v1) ( \
+ (R_DMA_CH8_SUB2_EP__ep__##f1##__VAL(R_DMA_CH8_SUB2_EP_, ep_, v1) << R_DMA_CH8_SUB2_EP__ep__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB2_EP_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB2_EP.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB2_EP_(f1_,v1) ( \
+ (R_DMA_CH8_SUB2_EP__ep__##f1_##_VAL(R_DMA_CH8_SUB2_EP_, ep_, v1) << R_DMA_CH8_SUB2_EP__ep__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB3_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001ef
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB3_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB3_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB3_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB3_CLR_INTR(f1,v1) ( \
+ *R_DMA_CH8_SUB3_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_SUB3_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_SUB3_CLR_INTR_(f1##_,v1) \
+ ), \
+ R_DMA_CH8_SUB3_CLR_INTR__WRITE(R_DMA_CH8_SUB3_CLR_INTR__ADDR, *R_DMA_CH8_SUB3_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB3_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB3_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH8_SUB3_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB3_CLR_INTR__SHADOW(f1,v1) ( \
+ *R_DMA_CH8_SUB3_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH8_SUB3_CLR_INTR_) \
+ REG_VAL__R_DMA_CH8_SUB3_CLR_INTR_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB3_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB3_CLR_INTR(f1,v1) ( \
+ (R_DMA_CH8_SUB3_CLR_INTR__clr_descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB3_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB3_CLR_INTR(f1,v1) ( \
+ (R_DMA_CH8_SUB3_CLR_INTR__clr_descr__##f1##__VAL(R_DMA_CH8_SUB3_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB3_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB3_CLR_INTR_(f1_,v1) ( \
+ (R_DMA_CH8_SUB3_CLR_INTR__clr_descr__##f1_##_VAL(R_DMA_CH8_SUB3_CLR_INTR_, clr_descr_, v1) << R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB3_CMD
+ * - type: RW
+ * - addr: 0xb00001df
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB3_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB3_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB3_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB3_CMD(f1,v1) ( \
+ R_DMA_CH8_SUB3_CMD__WRITE(R_DMA_CH8_SUB3_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB3_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB3_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB3_CMD(f1,v1) ( \
+ (R_DMA_CH8_SUB3_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB3_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB3_CMD(f1,v1) ( \
+ (R_DMA_CH8_SUB3_CMD__cmd__##f1##__VAL(R_DMA_CH8_SUB3_CMD_, cmd_, v1) << R_DMA_CH8_SUB3_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB3_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB3_CMD_(f1_,v1) ( \
+ (R_DMA_CH8_SUB3_CMD__cmd__##f1_##_VAL(R_DMA_CH8_SUB3_CMD_, cmd_, v1) << R_DMA_CH8_SUB3_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB3_EP
+ * - type: RW
+ * - addr: 0xb00001fc
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH8_SUB3_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH8_SUB3_EP.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH8_SUB3_EP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH8_SUB3_EP(f1,v1) ( \
+ R_DMA_CH8_SUB3_EP__WRITE(R_DMA_CH8_SUB3_EP__ADDR, ( \
+ REG_VAL__R_DMA_CH8_SUB3_EP_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH8_SUB3_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH8_SUB3_EP(f1,v1) ( \
+ (R_DMA_CH8_SUB3_EP__ep__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_EP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB3_EP.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB3_EP(f1,v1) ( \
+ (R_DMA_CH8_SUB3_EP__ep__##f1##__VAL(R_DMA_CH8_SUB3_EP_, ep_, v1) << R_DMA_CH8_SUB3_EP__ep__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH8_SUB3_EP_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH8_SUB3_EP.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH8_SUB3_EP_(f1_,v1) ( \
+ (R_DMA_CH8_SUB3_EP__ep__##f1_##_VAL(R_DMA_CH8_SUB3_EP_, ep_, v1) << R_DMA_CH8_SUB3_EP__ep__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH9_BUF
+ * - type: RW
+ * - addr: 0xb0000198
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH9_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH9_BUF.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH9_BUF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH9_BUF(f1,v1) ( \
+ R_DMA_CH9_BUF__WRITE(R_DMA_CH9_BUF__ADDR, ( \
+ REG_VAL__R_DMA_CH9_BUF_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH9_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH9_BUF(f1,v1) ( \
+ (R_DMA_CH9_BUF__buf__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_BUF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_BUF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_BUF(f1,v1) ( \
+ (R_DMA_CH9_BUF__buf__##f1##__VAL(R_DMA_CH9_BUF_, buf_, v1) << R_DMA_CH9_BUF__buf__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_BUF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_BUF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_BUF_(f1_,v1) ( \
+ (R_DMA_CH9_BUF__buf__##f1_##_VAL(R_DMA_CH9_BUF_, buf_, v1) << R_DMA_CH9_BUF__buf__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH9_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001f5
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH9_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH9_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH9_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH9_CLR_INTR(f1,v1,f2,v2) ( \
+ *R_DMA_CH9_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH9_CLR_INTR_) \
+ REG_VAL__R_DMA_CH9_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_DMA_CH9_CLR_INTR__WRITE(R_DMA_CH9_CLR_INTR__ADDR, *R_DMA_CH9_CLR_INTR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH9_CLR_INTR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH9_CLR_INTR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DMA_CH9_CLR_INTR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH9_CLR_INTR__SHADOW(f1,v1,f2,v2) ( \
+ *R_DMA_CH9_CLR_INTR__SADDR = ( \
+ REG_INITIATED(R_DMA_CH9_CLR_INTR_) \
+ REG_VAL__R_DMA_CH9_CLR_INTR_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH9_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH9_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH9_CLR_INTR__clr_eop__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH9_CLR_INTR__clr_descr__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_CLR_INTR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_CLR_INTR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_CLR_INTR(f1,v1,f2,v2) ( \
+ (R_DMA_CH9_CLR_INTR__clr_eop__##f1##__VAL(R_DMA_CH9_CLR_INTR_, clr_eop_, v1) << R_DMA_CH9_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH9_CLR_INTR__clr_descr__##f2##__VAL(R_DMA_CH9_CLR_INTR_, clr_descr_, v2) << R_DMA_CH9_CLR_INTR__clr_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_CLR_INTR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_CLR_INTR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_CLR_INTR_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH9_CLR_INTR__clr_eop__##f1_##_VAL(R_DMA_CH9_CLR_INTR_, clr_eop_, v1) << R_DMA_CH9_CLR_INTR__clr_eop__BITNR) | \
+ (R_DMA_CH9_CLR_INTR__clr_descr__##f2_##_VAL(R_DMA_CH9_CLR_INTR_, clr_descr_, v2) << R_DMA_CH9_CLR_INTR__clr_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH9_CMD
+ * - type: RW
+ * - addr: 0xb00001f4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH9_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH9_CMD.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH9_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH9_CMD(f1,v1) ( \
+ R_DMA_CH9_CMD__WRITE(R_DMA_CH9_CMD__ADDR, ( \
+ REG_VAL__R_DMA_CH9_CMD_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH9_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH9_CMD(f1,v1) ( \
+ (R_DMA_CH9_CMD__cmd__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_CMD(f1,v1) ( \
+ (R_DMA_CH9_CMD__cmd__##f1##__VAL(R_DMA_CH9_CMD_, cmd_, v1) << R_DMA_CH9_CMD__cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_CMD_(f1_,v1) ( \
+ (R_DMA_CH9_CMD__cmd__##f1_##_VAL(R_DMA_CH9_CMD_, cmd_, v1) << R_DMA_CH9_CMD__cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH9_DESCR
+ * - type: RW
+ * - addr: 0xb000019c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH9_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH9_DESCR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH9_DESCR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH9_DESCR(f1,v1) ( \
+ R_DMA_CH9_DESCR__WRITE(R_DMA_CH9_DESCR__ADDR, ( \
+ REG_VAL__R_DMA_CH9_DESCR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH9_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH9_DESCR(f1,v1) ( \
+ (R_DMA_CH9_DESCR__descr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_DESCR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_DESCR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_DESCR(f1,v1) ( \
+ (R_DMA_CH9_DESCR__descr__##f1##__VAL(R_DMA_CH9_DESCR_, descr_, v1) << R_DMA_CH9_DESCR__descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_DESCR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_DESCR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_DESCR_(f1_,v1) ( \
+ (R_DMA_CH9_DESCR__descr__##f1_##_VAL(R_DMA_CH9_DESCR_, descr_, v1) << R_DMA_CH9_DESCR__descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH9_FIRST
+ * - type: RW
+ * - addr: 0xb00001c4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH9_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH9_FIRST.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH9_FIRST.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH9_FIRST(f1,v1) ( \
+ R_DMA_CH9_FIRST__WRITE(R_DMA_CH9_FIRST__ADDR, ( \
+ REG_VAL__R_DMA_CH9_FIRST_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH9_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH9_FIRST(f1,v1) ( \
+ (R_DMA_CH9_FIRST__first__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_FIRST
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_FIRST.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_FIRST(f1,v1) ( \
+ (R_DMA_CH9_FIRST__first__##f1##__VAL(R_DMA_CH9_FIRST_, first_, v1) << R_DMA_CH9_FIRST__first__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_FIRST_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_FIRST.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_FIRST_(f1_,v1) ( \
+ (R_DMA_CH9_FIRST__first__##f1_##_VAL(R_DMA_CH9_FIRST_, first_, v1) << R_DMA_CH9_FIRST__first__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH9_HWSW
+ * - type: RW
+ * - addr: 0xb0000190
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH9_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH9_HWSW.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH9_HWSW.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH9_HWSW(f1,v1,f2,v2) ( \
+ R_DMA_CH9_HWSW__WRITE(R_DMA_CH9_HWSW__ADDR, ( \
+ REG_VAL__R_DMA_CH9_HWSW_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH9_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH9_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH9_HWSW__hw__##f1##__MASK & REG__##v1) | \
+ (R_DMA_CH9_HWSW__sw__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_HWSW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_HWSW.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_HWSW(f1,v1,f2,v2) ( \
+ (R_DMA_CH9_HWSW__hw__##f1##__VAL(R_DMA_CH9_HWSW_, hw_, v1) << R_DMA_CH9_HWSW__hw__BITNR) | \
+ (R_DMA_CH9_HWSW__sw__##f2##__VAL(R_DMA_CH9_HWSW_, sw_, v2) << R_DMA_CH9_HWSW__sw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_HWSW_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_HWSW.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_HWSW_(f1_,v1,f2_,v2) ( \
+ (R_DMA_CH9_HWSW__hw__##f1_##_VAL(R_DMA_CH9_HWSW_, hw_, v1) << R_DMA_CH9_HWSW__hw__BITNR) | \
+ (R_DMA_CH9_HWSW__sw__##f2_##_VAL(R_DMA_CH9_HWSW_, sw_, v2) << R_DMA_CH9_HWSW__sw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH9_NEXT
+ * - type: RW
+ * - addr: 0xb0000194
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DMA_CH9_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DMA_CH9_NEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DMA_CH9_NEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DMA_CH9_NEXT(f1,v1) ( \
+ R_DMA_CH9_NEXT__WRITE(R_DMA_CH9_NEXT__ADDR, ( \
+ REG_VAL__R_DMA_CH9_NEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH9_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH9_NEXT(f1,v1) ( \
+ (R_DMA_CH9_NEXT__next__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_NEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_NEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_NEXT(f1,v1) ( \
+ (R_DMA_CH9_NEXT__next__##f1##__VAL(R_DMA_CH9_NEXT_, next_, v1) << R_DMA_CH9_NEXT__next__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_NEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_NEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_NEXT_(f1_,v1) ( \
+ (R_DMA_CH9_NEXT__next__##f1_##_VAL(R_DMA_CH9_NEXT_, next_, v1) << R_DMA_CH9_NEXT__next__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DMA_CH9_STATUS
+ * - type: RO
+ * - addr: 0xb00001f6
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DMA_CH9_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DMA_CH9_STATUS(f1,v1) ( \
+ (R_DMA_CH9_STATUS__avail__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_STATUS(f1,v1) ( \
+ (R_DMA_CH9_STATUS__avail__##f1##__VAL(R_DMA_CH9_STATUS_, avail_, v1) << R_DMA_CH9_STATUS__avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DMA_CH9_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DMA_CH9_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DMA_CH9_STATUS_(f1_,v1) ( \
+ (R_DMA_CH9_STATUS__avail__##f1_##_VAL(R_DMA_CH9_STATUS_, avail_, v1) << R_DMA_CH9_STATUS__avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DRAM_CONFIG
+ * - type: WO
+ * - addr: 0xb000000c
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DRAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DRAM_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DRAM_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ *R_DRAM_CONFIG__SADDR = ( \
+ REG_INITIATED(R_DRAM_CONFIG_) \
+ REG_VAL__R_DRAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \
+ ), \
+ R_DRAM_CONFIG__WRITE(R_DRAM_CONFIG__ADDR, *R_DRAM_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DRAM_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DRAM_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DRAM_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DRAM_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ *R_DRAM_CONFIG__SADDR = ( \
+ REG_INITIATED(R_DRAM_CONFIG_) \
+ REG_VAL__R_DRAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DRAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_DRAM_CONFIG__wmm1__##f1##__MASK & REG__##v1) | \
+ (R_DRAM_CONFIG__wmm0__##f2##__MASK & REG__##v2) | \
+ (R_DRAM_CONFIG__sh1__##f3##__MASK & REG__##v3) | \
+ (R_DRAM_CONFIG__sh0__##f4##__MASK & REG__##v4) | \
+ (R_DRAM_CONFIG__w__##f5##__MASK & REG__##v5) | \
+ (R_DRAM_CONFIG__c__##f6##__MASK & REG__##v6) | \
+ (R_DRAM_CONFIG__e__##f7##__MASK & REG__##v7) | \
+ (R_DRAM_CONFIG__group_sel__##f8##__MASK & REG__##v8) | \
+ (R_DRAM_CONFIG__ca1__##f9##__MASK & REG__##v9) | \
+ (R_DRAM_CONFIG__bank23sel__##f10##__MASK & REG__##v10) | \
+ (R_DRAM_CONFIG__ca0__##f11##__MASK & REG__##v11) | \
+ (R_DRAM_CONFIG__bank01sel__##f12##__MASK & REG__##v12) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DRAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DRAM_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_DRAM_CONFIG__wmm1__##f1##__VAL(R_DRAM_CONFIG_, wmm1_, v1) << R_DRAM_CONFIG__wmm1__BITNR) | \
+ (R_DRAM_CONFIG__wmm0__##f2##__VAL(R_DRAM_CONFIG_, wmm0_, v2) << R_DRAM_CONFIG__wmm0__BITNR) | \
+ (R_DRAM_CONFIG__sh1__##f3##__VAL(R_DRAM_CONFIG_, sh1_, v3) << R_DRAM_CONFIG__sh1__BITNR) | \
+ (R_DRAM_CONFIG__sh0__##f4##__VAL(R_DRAM_CONFIG_, sh0_, v4) << R_DRAM_CONFIG__sh0__BITNR) | \
+ (R_DRAM_CONFIG__w__##f5##__VAL(R_DRAM_CONFIG_, w_, v5) << R_DRAM_CONFIG__w__BITNR) | \
+ (R_DRAM_CONFIG__c__##f6##__VAL(R_DRAM_CONFIG_, c_, v6) << R_DRAM_CONFIG__c__BITNR) | \
+ (R_DRAM_CONFIG__e__##f7##__VAL(R_DRAM_CONFIG_, e_, v7) << R_DRAM_CONFIG__e__BITNR) | \
+ (R_DRAM_CONFIG__group_sel__##f8##__VAL(R_DRAM_CONFIG_, group_sel_, v8) << R_DRAM_CONFIG__group_sel__BITNR) | \
+ (R_DRAM_CONFIG__ca1__##f9##__VAL(R_DRAM_CONFIG_, ca1_, v9) << R_DRAM_CONFIG__ca1__BITNR) | \
+ (R_DRAM_CONFIG__bank23sel__##f10##__VAL(R_DRAM_CONFIG_, bank23sel_, v10) << R_DRAM_CONFIG__bank23sel__BITNR) | \
+ (R_DRAM_CONFIG__ca0__##f11##__VAL(R_DRAM_CONFIG_, ca0_, v11) << R_DRAM_CONFIG__ca0__BITNR) | \
+ (R_DRAM_CONFIG__bank01sel__##f12##__VAL(R_DRAM_CONFIG_, bank01sel_, v12) << R_DRAM_CONFIG__bank01sel__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DRAM_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DRAM_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DRAM_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \
+ (R_DRAM_CONFIG__wmm1__##f1_##_VAL(R_DRAM_CONFIG_, wmm1_, v1) << R_DRAM_CONFIG__wmm1__BITNR) | \
+ (R_DRAM_CONFIG__wmm0__##f2_##_VAL(R_DRAM_CONFIG_, wmm0_, v2) << R_DRAM_CONFIG__wmm0__BITNR) | \
+ (R_DRAM_CONFIG__sh1__##f3_##_VAL(R_DRAM_CONFIG_, sh1_, v3) << R_DRAM_CONFIG__sh1__BITNR) | \
+ (R_DRAM_CONFIG__sh0__##f4_##_VAL(R_DRAM_CONFIG_, sh0_, v4) << R_DRAM_CONFIG__sh0__BITNR) | \
+ (R_DRAM_CONFIG__w__##f5_##_VAL(R_DRAM_CONFIG_, w_, v5) << R_DRAM_CONFIG__w__BITNR) | \
+ (R_DRAM_CONFIG__c__##f6_##_VAL(R_DRAM_CONFIG_, c_, v6) << R_DRAM_CONFIG__c__BITNR) | \
+ (R_DRAM_CONFIG__e__##f7_##_VAL(R_DRAM_CONFIG_, e_, v7) << R_DRAM_CONFIG__e__BITNR) | \
+ (R_DRAM_CONFIG__group_sel__##f8_##_VAL(R_DRAM_CONFIG_, group_sel_, v8) << R_DRAM_CONFIG__group_sel__BITNR) | \
+ (R_DRAM_CONFIG__ca1__##f9_##_VAL(R_DRAM_CONFIG_, ca1_, v9) << R_DRAM_CONFIG__ca1__BITNR) | \
+ (R_DRAM_CONFIG__bank23sel__##f10_##_VAL(R_DRAM_CONFIG_, bank23sel_, v10) << R_DRAM_CONFIG__bank23sel__BITNR) | \
+ (R_DRAM_CONFIG__ca0__##f11_##_VAL(R_DRAM_CONFIG_, ca0_, v11) << R_DRAM_CONFIG__ca0__BITNR) | \
+ (R_DRAM_CONFIG__bank01sel__##f12_##_VAL(R_DRAM_CONFIG_, bank01sel_, v12) << R_DRAM_CONFIG__bank01sel__BITNR) \
+)
+
+#endif
+
+/*
+ * R_DRAM_TIMING
+ * - type: WO
+ * - addr: 0xb0000008
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DRAM_TIMING
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DRAM_TIMING.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_DRAM_TIMING.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_DRAM_TIMING__SADDR = ( \
+ REG_INITIATED(R_DRAM_TIMING_) \
+ REG_VAL__R_DRAM_TIMING_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ), \
+ R_DRAM_TIMING__WRITE(R_DRAM_TIMING__ADDR, *R_DRAM_TIMING__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_DRAM_TIMING__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_DRAM_TIMING.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_DRAM_TIMING.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_DRAM_TIMING__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_DRAM_TIMING__SADDR = ( \
+ REG_INITIATED(R_DRAM_TIMING_) \
+ REG_VAL__R_DRAM_TIMING_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_DRAM_TIMING
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_DRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_DRAM_TIMING__sdram__##f1##__MASK & REG__##v1) | \
+ (R_DRAM_TIMING__ref__##f2##__MASK & REG__##v2) | \
+ (R_DRAM_TIMING__rp__##f3##__MASK & REG__##v3) | \
+ (R_DRAM_TIMING__rs__##f4##__MASK & REG__##v4) | \
+ (R_DRAM_TIMING__rh__##f5##__MASK & REG__##v5) | \
+ (R_DRAM_TIMING__w__##f6##__MASK & REG__##v6) | \
+ (R_DRAM_TIMING__c__##f7##__MASK & REG__##v7) | \
+ (R_DRAM_TIMING__cz__##f8##__MASK & REG__##v8) | \
+ (R_DRAM_TIMING__cp__##f9##__MASK & REG__##v9) | \
+ (R_DRAM_TIMING__cw__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DRAM_TIMING
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DRAM_TIMING.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_DRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_DRAM_TIMING__sdram__##f1##__VAL(R_DRAM_TIMING_, sdram_, v1) << R_DRAM_TIMING__sdram__BITNR) | \
+ (R_DRAM_TIMING__ref__##f2##__VAL(R_DRAM_TIMING_, ref_, v2) << R_DRAM_TIMING__ref__BITNR) | \
+ (R_DRAM_TIMING__rp__##f3##__VAL(R_DRAM_TIMING_, rp_, v3) << R_DRAM_TIMING__rp__BITNR) | \
+ (R_DRAM_TIMING__rs__##f4##__VAL(R_DRAM_TIMING_, rs_, v4) << R_DRAM_TIMING__rs__BITNR) | \
+ (R_DRAM_TIMING__rh__##f5##__VAL(R_DRAM_TIMING_, rh_, v5) << R_DRAM_TIMING__rh__BITNR) | \
+ (R_DRAM_TIMING__w__##f6##__VAL(R_DRAM_TIMING_, w_, v6) << R_DRAM_TIMING__w__BITNR) | \
+ (R_DRAM_TIMING__c__##f7##__VAL(R_DRAM_TIMING_, c_, v7) << R_DRAM_TIMING__c__BITNR) | \
+ (R_DRAM_TIMING__cz__##f8##__VAL(R_DRAM_TIMING_, cz_, v8) << R_DRAM_TIMING__cz__BITNR) | \
+ (R_DRAM_TIMING__cp__##f9##__VAL(R_DRAM_TIMING_, cp_, v9) << R_DRAM_TIMING__cp__BITNR) | \
+ (R_DRAM_TIMING__cw__##f10##__VAL(R_DRAM_TIMING_, cw_, v10) << R_DRAM_TIMING__cw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_DRAM_TIMING_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_DRAM_TIMING.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_DRAM_TIMING_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_DRAM_TIMING__sdram__##f1_##_VAL(R_DRAM_TIMING_, sdram_, v1) << R_DRAM_TIMING__sdram__BITNR) | \
+ (R_DRAM_TIMING__ref__##f2_##_VAL(R_DRAM_TIMING_, ref_, v2) << R_DRAM_TIMING__ref__BITNR) | \
+ (R_DRAM_TIMING__rp__##f3_##_VAL(R_DRAM_TIMING_, rp_, v3) << R_DRAM_TIMING__rp__BITNR) | \
+ (R_DRAM_TIMING__rs__##f4_##_VAL(R_DRAM_TIMING_, rs_, v4) << R_DRAM_TIMING__rs__BITNR) | \
+ (R_DRAM_TIMING__rh__##f5_##_VAL(R_DRAM_TIMING_, rh_, v5) << R_DRAM_TIMING__rh__BITNR) | \
+ (R_DRAM_TIMING__w__##f6_##_VAL(R_DRAM_TIMING_, w_, v6) << R_DRAM_TIMING__w__BITNR) | \
+ (R_DRAM_TIMING__c__##f7_##_VAL(R_DRAM_TIMING_, c_, v7) << R_DRAM_TIMING__c__BITNR) | \
+ (R_DRAM_TIMING__cz__##f8_##_VAL(R_DRAM_TIMING_, cz_, v8) << R_DRAM_TIMING__cz__BITNR) | \
+ (R_DRAM_TIMING__cp__##f9_##_VAL(R_DRAM_TIMING_, cp_, v9) << R_DRAM_TIMING__cp__BITNR) | \
+ (R_DRAM_TIMING__cw__##f10_##_VAL(R_DRAM_TIMING_, cw_, v10) << R_DRAM_TIMING__cw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_EXT_DMA_0_ADDR
+ * - type: WO
+ * - addr: 0xb0000014
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_EXT_DMA_0_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_EXT_DMA_0_ADDR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_EXT_DMA_0_ADDR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_EXT_DMA_0_ADDR(f1,v1) ( \
+ *R_EXT_DMA_0_ADDR__SADDR = ( \
+ REG_INITIATED(R_EXT_DMA_0_ADDR_) \
+ REG_VAL__R_EXT_DMA_0_ADDR_(f1##_,v1) \
+ ), \
+ R_EXT_DMA_0_ADDR__WRITE(R_EXT_DMA_0_ADDR__ADDR, *R_EXT_DMA_0_ADDR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_EXT_DMA_0_ADDR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_EXT_DMA_0_ADDR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_EXT_DMA_0_ADDR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_EXT_DMA_0_ADDR__SHADOW(f1,v1) ( \
+ *R_EXT_DMA_0_ADDR__SADDR = ( \
+ REG_INITIATED(R_EXT_DMA_0_ADDR_) \
+ REG_VAL__R_EXT_DMA_0_ADDR_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_EXT_DMA_0_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_EXT_DMA_0_ADDR(f1,v1) ( \
+ (R_EXT_DMA_0_ADDR__ext0_addr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_0_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_0_ADDR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_0_ADDR(f1,v1) ( \
+ (R_EXT_DMA_0_ADDR__ext0_addr__##f1##__VAL(R_EXT_DMA_0_ADDR_, ext0_addr_, v1) << R_EXT_DMA_0_ADDR__ext0_addr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_0_ADDR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_0_ADDR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_0_ADDR_(f1_,v1) ( \
+ (R_EXT_DMA_0_ADDR__ext0_addr__##f1_##_VAL(R_EXT_DMA_0_ADDR_, ext0_addr_, v1) << R_EXT_DMA_0_ADDR__ext0_addr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_EXT_DMA_0_CMD
+ * - type: WO
+ * - addr: 0xb0000010
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_EXT_DMA_0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_EXT_DMA_0_CMD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_EXT_DMA_0_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_EXT_DMA_0_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_EXT_DMA_0_CMD__SADDR = ( \
+ REG_INITIATED(R_EXT_DMA_0_CMD_) \
+ REG_VAL__R_EXT_DMA_0_CMD_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_EXT_DMA_0_CMD__WRITE(R_EXT_DMA_0_CMD__ADDR, *R_EXT_DMA_0_CMD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_EXT_DMA_0_CMD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_EXT_DMA_0_CMD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_EXT_DMA_0_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_EXT_DMA_0_CMD__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_EXT_DMA_0_CMD__SADDR = ( \
+ REG_INITIATED(R_EXT_DMA_0_CMD_) \
+ REG_VAL__R_EXT_DMA_0_CMD_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_EXT_DMA_0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_EXT_DMA_0_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_EXT_DMA_0_CMD__cnt__##f1##__MASK & REG__##v1) | \
+ (R_EXT_DMA_0_CMD__rqpol__##f2##__MASK & REG__##v2) | \
+ (R_EXT_DMA_0_CMD__apol__##f3##__MASK & REG__##v3) | \
+ (R_EXT_DMA_0_CMD__rq_ack__##f4##__MASK & REG__##v4) | \
+ (R_EXT_DMA_0_CMD__wid__##f5##__MASK & REG__##v5) | \
+ (R_EXT_DMA_0_CMD__dir__##f6##__MASK & REG__##v6) | \
+ (R_EXT_DMA_0_CMD__run__##f7##__MASK & REG__##v7) | \
+ (R_EXT_DMA_0_CMD__trf_count__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_0_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_0_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_EXT_DMA_0_CMD__cnt__##f1##__VAL(R_EXT_DMA_0_CMD_, cnt_, v1) << R_EXT_DMA_0_CMD__cnt__BITNR) | \
+ (R_EXT_DMA_0_CMD__rqpol__##f2##__VAL(R_EXT_DMA_0_CMD_, rqpol_, v2) << R_EXT_DMA_0_CMD__rqpol__BITNR) | \
+ (R_EXT_DMA_0_CMD__apol__##f3##__VAL(R_EXT_DMA_0_CMD_, apol_, v3) << R_EXT_DMA_0_CMD__apol__BITNR) | \
+ (R_EXT_DMA_0_CMD__rq_ack__##f4##__VAL(R_EXT_DMA_0_CMD_, rq_ack_, v4) << R_EXT_DMA_0_CMD__rq_ack__BITNR) | \
+ (R_EXT_DMA_0_CMD__wid__##f5##__VAL(R_EXT_DMA_0_CMD_, wid_, v5) << R_EXT_DMA_0_CMD__wid__BITNR) | \
+ (R_EXT_DMA_0_CMD__dir__##f6##__VAL(R_EXT_DMA_0_CMD_, dir_, v6) << R_EXT_DMA_0_CMD__dir__BITNR) | \
+ (R_EXT_DMA_0_CMD__run__##f7##__VAL(R_EXT_DMA_0_CMD_, run_, v7) << R_EXT_DMA_0_CMD__run__BITNR) | \
+ (R_EXT_DMA_0_CMD__trf_count__##f8##__VAL(R_EXT_DMA_0_CMD_, trf_count_, v8) << R_EXT_DMA_0_CMD__trf_count__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_0_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_0_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_0_CMD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_EXT_DMA_0_CMD__cnt__##f1_##_VAL(R_EXT_DMA_0_CMD_, cnt_, v1) << R_EXT_DMA_0_CMD__cnt__BITNR) | \
+ (R_EXT_DMA_0_CMD__rqpol__##f2_##_VAL(R_EXT_DMA_0_CMD_, rqpol_, v2) << R_EXT_DMA_0_CMD__rqpol__BITNR) | \
+ (R_EXT_DMA_0_CMD__apol__##f3_##_VAL(R_EXT_DMA_0_CMD_, apol_, v3) << R_EXT_DMA_0_CMD__apol__BITNR) | \
+ (R_EXT_DMA_0_CMD__rq_ack__##f4_##_VAL(R_EXT_DMA_0_CMD_, rq_ack_, v4) << R_EXT_DMA_0_CMD__rq_ack__BITNR) | \
+ (R_EXT_DMA_0_CMD__wid__##f5_##_VAL(R_EXT_DMA_0_CMD_, wid_, v5) << R_EXT_DMA_0_CMD__wid__BITNR) | \
+ (R_EXT_DMA_0_CMD__dir__##f6_##_VAL(R_EXT_DMA_0_CMD_, dir_, v6) << R_EXT_DMA_0_CMD__dir__BITNR) | \
+ (R_EXT_DMA_0_CMD__run__##f7_##_VAL(R_EXT_DMA_0_CMD_, run_, v7) << R_EXT_DMA_0_CMD__run__BITNR) | \
+ (R_EXT_DMA_0_CMD__trf_count__##f8_##_VAL(R_EXT_DMA_0_CMD_, trf_count_, v8) << R_EXT_DMA_0_CMD__trf_count__BITNR) \
+)
+
+#endif
+
+/*
+ * R_EXT_DMA_0_STAT
+ * - type: RO
+ * - addr: 0xb0000010
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_EXT_DMA_0_STAT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_EXT_DMA_0_STAT(f1,v1,f2,v2) ( \
+ (R_EXT_DMA_0_STAT__run__##f1##__MASK & REG__##v1) | \
+ (R_EXT_DMA_0_STAT__trf_count__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_0_STAT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_0_STAT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_0_STAT(f1,v1,f2,v2) ( \
+ (R_EXT_DMA_0_STAT__run__##f1##__VAL(R_EXT_DMA_0_STAT_, run_, v1) << R_EXT_DMA_0_STAT__run__BITNR) | \
+ (R_EXT_DMA_0_STAT__trf_count__##f2##__VAL(R_EXT_DMA_0_STAT_, trf_count_, v2) << R_EXT_DMA_0_STAT__trf_count__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_0_STAT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_0_STAT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_0_STAT_(f1_,v1,f2_,v2) ( \
+ (R_EXT_DMA_0_STAT__run__##f1_##_VAL(R_EXT_DMA_0_STAT_, run_, v1) << R_EXT_DMA_0_STAT__run__BITNR) | \
+ (R_EXT_DMA_0_STAT__trf_count__##f2_##_VAL(R_EXT_DMA_0_STAT_, trf_count_, v2) << R_EXT_DMA_0_STAT__trf_count__BITNR) \
+)
+
+#endif
+
+/*
+ * R_EXT_DMA_1_ADDR
+ * - type: WO
+ * - addr: 0xb000001c
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_EXT_DMA_1_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_EXT_DMA_1_ADDR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_EXT_DMA_1_ADDR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_EXT_DMA_1_ADDR(f1,v1) ( \
+ *R_EXT_DMA_1_ADDR__SADDR = ( \
+ REG_INITIATED(R_EXT_DMA_1_ADDR_) \
+ REG_VAL__R_EXT_DMA_1_ADDR_(f1##_,v1) \
+ ), \
+ R_EXT_DMA_1_ADDR__WRITE(R_EXT_DMA_1_ADDR__ADDR, *R_EXT_DMA_1_ADDR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_EXT_DMA_1_ADDR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_EXT_DMA_1_ADDR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_EXT_DMA_1_ADDR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_EXT_DMA_1_ADDR__SHADOW(f1,v1) ( \
+ *R_EXT_DMA_1_ADDR__SADDR = ( \
+ REG_INITIATED(R_EXT_DMA_1_ADDR_) \
+ REG_VAL__R_EXT_DMA_1_ADDR_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_EXT_DMA_1_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_EXT_DMA_1_ADDR(f1,v1) ( \
+ (R_EXT_DMA_1_ADDR__ext0_addr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_1_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_1_ADDR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_1_ADDR(f1,v1) ( \
+ (R_EXT_DMA_1_ADDR__ext0_addr__##f1##__VAL(R_EXT_DMA_1_ADDR_, ext0_addr_, v1) << R_EXT_DMA_1_ADDR__ext0_addr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_1_ADDR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_1_ADDR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_1_ADDR_(f1_,v1) ( \
+ (R_EXT_DMA_1_ADDR__ext0_addr__##f1_##_VAL(R_EXT_DMA_1_ADDR_, ext0_addr_, v1) << R_EXT_DMA_1_ADDR__ext0_addr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_EXT_DMA_1_CMD
+ * - type: WO
+ * - addr: 0xb0000018
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_EXT_DMA_1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_EXT_DMA_1_CMD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_EXT_DMA_1_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_EXT_DMA_1_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_EXT_DMA_1_CMD__SADDR = ( \
+ REG_INITIATED(R_EXT_DMA_1_CMD_) \
+ REG_VAL__R_EXT_DMA_1_CMD_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_EXT_DMA_1_CMD__WRITE(R_EXT_DMA_1_CMD__ADDR, *R_EXT_DMA_1_CMD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_EXT_DMA_1_CMD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_EXT_DMA_1_CMD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_EXT_DMA_1_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_EXT_DMA_1_CMD__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_EXT_DMA_1_CMD__SADDR = ( \
+ REG_INITIATED(R_EXT_DMA_1_CMD_) \
+ REG_VAL__R_EXT_DMA_1_CMD_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_EXT_DMA_1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_EXT_DMA_1_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_EXT_DMA_1_CMD__cnt__##f1##__MASK & REG__##v1) | \
+ (R_EXT_DMA_1_CMD__rqpol__##f2##__MASK & REG__##v2) | \
+ (R_EXT_DMA_1_CMD__apol__##f3##__MASK & REG__##v3) | \
+ (R_EXT_DMA_1_CMD__rq_ack__##f4##__MASK & REG__##v4) | \
+ (R_EXT_DMA_1_CMD__wid__##f5##__MASK & REG__##v5) | \
+ (R_EXT_DMA_1_CMD__dir__##f6##__MASK & REG__##v6) | \
+ (R_EXT_DMA_1_CMD__run__##f7##__MASK & REG__##v7) | \
+ (R_EXT_DMA_1_CMD__trf_count__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_1_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_1_CMD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_EXT_DMA_1_CMD__cnt__##f1##__VAL(R_EXT_DMA_1_CMD_, cnt_, v1) << R_EXT_DMA_1_CMD__cnt__BITNR) | \
+ (R_EXT_DMA_1_CMD__rqpol__##f2##__VAL(R_EXT_DMA_1_CMD_, rqpol_, v2) << R_EXT_DMA_1_CMD__rqpol__BITNR) | \
+ (R_EXT_DMA_1_CMD__apol__##f3##__VAL(R_EXT_DMA_1_CMD_, apol_, v3) << R_EXT_DMA_1_CMD__apol__BITNR) | \
+ (R_EXT_DMA_1_CMD__rq_ack__##f4##__VAL(R_EXT_DMA_1_CMD_, rq_ack_, v4) << R_EXT_DMA_1_CMD__rq_ack__BITNR) | \
+ (R_EXT_DMA_1_CMD__wid__##f5##__VAL(R_EXT_DMA_1_CMD_, wid_, v5) << R_EXT_DMA_1_CMD__wid__BITNR) | \
+ (R_EXT_DMA_1_CMD__dir__##f6##__VAL(R_EXT_DMA_1_CMD_, dir_, v6) << R_EXT_DMA_1_CMD__dir__BITNR) | \
+ (R_EXT_DMA_1_CMD__run__##f7##__VAL(R_EXT_DMA_1_CMD_, run_, v7) << R_EXT_DMA_1_CMD__run__BITNR) | \
+ (R_EXT_DMA_1_CMD__trf_count__##f8##__VAL(R_EXT_DMA_1_CMD_, trf_count_, v8) << R_EXT_DMA_1_CMD__trf_count__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_1_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_1_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_1_CMD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_EXT_DMA_1_CMD__cnt__##f1_##_VAL(R_EXT_DMA_1_CMD_, cnt_, v1) << R_EXT_DMA_1_CMD__cnt__BITNR) | \
+ (R_EXT_DMA_1_CMD__rqpol__##f2_##_VAL(R_EXT_DMA_1_CMD_, rqpol_, v2) << R_EXT_DMA_1_CMD__rqpol__BITNR) | \
+ (R_EXT_DMA_1_CMD__apol__##f3_##_VAL(R_EXT_DMA_1_CMD_, apol_, v3) << R_EXT_DMA_1_CMD__apol__BITNR) | \
+ (R_EXT_DMA_1_CMD__rq_ack__##f4_##_VAL(R_EXT_DMA_1_CMD_, rq_ack_, v4) << R_EXT_DMA_1_CMD__rq_ack__BITNR) | \
+ (R_EXT_DMA_1_CMD__wid__##f5_##_VAL(R_EXT_DMA_1_CMD_, wid_, v5) << R_EXT_DMA_1_CMD__wid__BITNR) | \
+ (R_EXT_DMA_1_CMD__dir__##f6_##_VAL(R_EXT_DMA_1_CMD_, dir_, v6) << R_EXT_DMA_1_CMD__dir__BITNR) | \
+ (R_EXT_DMA_1_CMD__run__##f7_##_VAL(R_EXT_DMA_1_CMD_, run_, v7) << R_EXT_DMA_1_CMD__run__BITNR) | \
+ (R_EXT_DMA_1_CMD__trf_count__##f8_##_VAL(R_EXT_DMA_1_CMD_, trf_count_, v8) << R_EXT_DMA_1_CMD__trf_count__BITNR) \
+)
+
+#endif
+
+/*
+ * R_EXT_DMA_1_STAT
+ * - type: RO
+ * - addr: 0xb0000018
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_EXT_DMA_1_STAT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_EXT_DMA_1_STAT(f1,v1,f2,v2) ( \
+ (R_EXT_DMA_1_STAT__run__##f1##__MASK & REG__##v1) | \
+ (R_EXT_DMA_1_STAT__trf_count__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_1_STAT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_1_STAT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_1_STAT(f1,v1,f2,v2) ( \
+ (R_EXT_DMA_1_STAT__run__##f1##__VAL(R_EXT_DMA_1_STAT_, run_, v1) << R_EXT_DMA_1_STAT__run__BITNR) | \
+ (R_EXT_DMA_1_STAT__trf_count__##f2##__VAL(R_EXT_DMA_1_STAT_, trf_count_, v2) << R_EXT_DMA_1_STAT__trf_count__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_EXT_DMA_1_STAT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_EXT_DMA_1_STAT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_EXT_DMA_1_STAT_(f1_,v1,f2_,v2) ( \
+ (R_EXT_DMA_1_STAT__run__##f1_##_VAL(R_EXT_DMA_1_STAT_, run_, v1) << R_EXT_DMA_1_STAT__run__BITNR) | \
+ (R_EXT_DMA_1_STAT__trf_count__##f2_##_VAL(R_EXT_DMA_1_STAT_, trf_count_, v2) << R_EXT_DMA_1_STAT__trf_count__BITNR) \
+)
+
+#endif
+
+/*
+ * R_GEN_CONFIG
+ * - type: WO
+ * - addr: 0xb000002c
+ * - group: General config registers
+ */
+
+#if USE_GROUP__General_config_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_GEN_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_GEN_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_GEN_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ *R_GEN_CONFIG__SADDR = ( \
+ REG_INITIATED(R_GEN_CONFIG_) \
+ REG_VAL__R_GEN_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \
+ ), \
+ R_GEN_CONFIG__WRITE(R_GEN_CONFIG__ADDR, *R_GEN_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_GEN_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_GEN_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_GEN_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_GEN_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ *R_GEN_CONFIG__SADDR = ( \
+ REG_INITIATED(R_GEN_CONFIG_) \
+ REG_VAL__R_GEN_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_GEN_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_GEN_CONFIG__par_w__##f1##__MASK & REG__##v1) | \
+ (R_GEN_CONFIG__usb2__##f2##__MASK & REG__##v2) | \
+ (R_GEN_CONFIG__usb1__##f3##__MASK & REG__##v3) | \
+ (R_GEN_CONFIG__g24dir__##f4##__MASK & REG__##v4) | \
+ (R_GEN_CONFIG__g16_23dir__##f5##__MASK & REG__##v5) | \
+ (R_GEN_CONFIG__g8_15dir__##f6##__MASK & REG__##v6) | \
+ (R_GEN_CONFIG__g0dir__##f7##__MASK & REG__##v7) | \
+ (R_GEN_CONFIG__dma9__##f8##__MASK & REG__##v8) | \
+ (R_GEN_CONFIG__dma8__##f9##__MASK & REG__##v9) | \
+ (R_GEN_CONFIG__dma7__##f10##__MASK & REG__##v10) | \
+ (R_GEN_CONFIG__dma6__##f11##__MASK & REG__##v11) | \
+ (R_GEN_CONFIG__dma5__##f12##__MASK & REG__##v12) | \
+ (R_GEN_CONFIG__dma4__##f13##__MASK & REG__##v13) | \
+ (R_GEN_CONFIG__dma3__##f14##__MASK & REG__##v14) | \
+ (R_GEN_CONFIG__dma2__##f15##__MASK & REG__##v15) | \
+ (R_GEN_CONFIG__mio_w__##f16##__MASK & REG__##v16) | \
+ (R_GEN_CONFIG__ser3__##f17##__MASK & REG__##v17) | \
+ (R_GEN_CONFIG__par1__##f18##__MASK & REG__##v18) | \
+ (R_GEN_CONFIG__scsi0w__##f19##__MASK & REG__##v19) | \
+ (R_GEN_CONFIG__scsi1__##f20##__MASK & REG__##v20) | \
+ (R_GEN_CONFIG__mio__##f21##__MASK & REG__##v21) | \
+ (R_GEN_CONFIG__ser2__##f22##__MASK & REG__##v22) | \
+ (R_GEN_CONFIG__par0__##f23##__MASK & REG__##v23) | \
+ (R_GEN_CONFIG__ata__##f24##__MASK & REG__##v24) | \
+ (R_GEN_CONFIG__scsi0__##f25##__MASK & REG__##v25) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_GEN_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_GEN_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_GEN_CONFIG__par_w__##f1##__VAL(R_GEN_CONFIG_, par_w_, v1) << R_GEN_CONFIG__par_w__BITNR) | \
+ (R_GEN_CONFIG__usb2__##f2##__VAL(R_GEN_CONFIG_, usb2_, v2) << R_GEN_CONFIG__usb2__BITNR) | \
+ (R_GEN_CONFIG__usb1__##f3##__VAL(R_GEN_CONFIG_, usb1_, v3) << R_GEN_CONFIG__usb1__BITNR) | \
+ (R_GEN_CONFIG__g24dir__##f4##__VAL(R_GEN_CONFIG_, g24dir_, v4) << R_GEN_CONFIG__g24dir__BITNR) | \
+ (R_GEN_CONFIG__g16_23dir__##f5##__VAL(R_GEN_CONFIG_, g16_23dir_, v5) << R_GEN_CONFIG__g16_23dir__BITNR) | \
+ (R_GEN_CONFIG__g8_15dir__##f6##__VAL(R_GEN_CONFIG_, g8_15dir_, v6) << R_GEN_CONFIG__g8_15dir__BITNR) | \
+ (R_GEN_CONFIG__g0dir__##f7##__VAL(R_GEN_CONFIG_, g0dir_, v7) << R_GEN_CONFIG__g0dir__BITNR) | \
+ (R_GEN_CONFIG__dma9__##f8##__VAL(R_GEN_CONFIG_, dma9_, v8) << R_GEN_CONFIG__dma9__BITNR) | \
+ (R_GEN_CONFIG__dma8__##f9##__VAL(R_GEN_CONFIG_, dma8_, v9) << R_GEN_CONFIG__dma8__BITNR) | \
+ (R_GEN_CONFIG__dma7__##f10##__VAL(R_GEN_CONFIG_, dma7_, v10) << R_GEN_CONFIG__dma7__BITNR) | \
+ (R_GEN_CONFIG__dma6__##f11##__VAL(R_GEN_CONFIG_, dma6_, v11) << R_GEN_CONFIG__dma6__BITNR) | \
+ (R_GEN_CONFIG__dma5__##f12##__VAL(R_GEN_CONFIG_, dma5_, v12) << R_GEN_CONFIG__dma5__BITNR) | \
+ (R_GEN_CONFIG__dma4__##f13##__VAL(R_GEN_CONFIG_, dma4_, v13) << R_GEN_CONFIG__dma4__BITNR) | \
+ (R_GEN_CONFIG__dma3__##f14##__VAL(R_GEN_CONFIG_, dma3_, v14) << R_GEN_CONFIG__dma3__BITNR) | \
+ (R_GEN_CONFIG__dma2__##f15##__VAL(R_GEN_CONFIG_, dma2_, v15) << R_GEN_CONFIG__dma2__BITNR) | \
+ (R_GEN_CONFIG__mio_w__##f16##__VAL(R_GEN_CONFIG_, mio_w_, v16) << R_GEN_CONFIG__mio_w__BITNR) | \
+ (R_GEN_CONFIG__ser3__##f17##__VAL(R_GEN_CONFIG_, ser3_, v17) << R_GEN_CONFIG__ser3__BITNR) | \
+ (R_GEN_CONFIG__par1__##f18##__VAL(R_GEN_CONFIG_, par1_, v18) << R_GEN_CONFIG__par1__BITNR) | \
+ (R_GEN_CONFIG__scsi0w__##f19##__VAL(R_GEN_CONFIG_, scsi0w_, v19) << R_GEN_CONFIG__scsi0w__BITNR) | \
+ (R_GEN_CONFIG__scsi1__##f20##__VAL(R_GEN_CONFIG_, scsi1_, v20) << R_GEN_CONFIG__scsi1__BITNR) | \
+ (R_GEN_CONFIG__mio__##f21##__VAL(R_GEN_CONFIG_, mio_, v21) << R_GEN_CONFIG__mio__BITNR) | \
+ (R_GEN_CONFIG__ser2__##f22##__VAL(R_GEN_CONFIG_, ser2_, v22) << R_GEN_CONFIG__ser2__BITNR) | \
+ (R_GEN_CONFIG__par0__##f23##__VAL(R_GEN_CONFIG_, par0_, v23) << R_GEN_CONFIG__par0__BITNR) | \
+ (R_GEN_CONFIG__ata__##f24##__VAL(R_GEN_CONFIG_, ata_, v24) << R_GEN_CONFIG__ata__BITNR) | \
+ (R_GEN_CONFIG__scsi0__##f25##__VAL(R_GEN_CONFIG_, scsi0_, v25) << R_GEN_CONFIG__scsi0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_GEN_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_GEN_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_GEN_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \
+ (R_GEN_CONFIG__par_w__##f1_##_VAL(R_GEN_CONFIG_, par_w_, v1) << R_GEN_CONFIG__par_w__BITNR) | \
+ (R_GEN_CONFIG__usb2__##f2_##_VAL(R_GEN_CONFIG_, usb2_, v2) << R_GEN_CONFIG__usb2__BITNR) | \
+ (R_GEN_CONFIG__usb1__##f3_##_VAL(R_GEN_CONFIG_, usb1_, v3) << R_GEN_CONFIG__usb1__BITNR) | \
+ (R_GEN_CONFIG__g24dir__##f4_##_VAL(R_GEN_CONFIG_, g24dir_, v4) << R_GEN_CONFIG__g24dir__BITNR) | \
+ (R_GEN_CONFIG__g16_23dir__##f5_##_VAL(R_GEN_CONFIG_, g16_23dir_, v5) << R_GEN_CONFIG__g16_23dir__BITNR) | \
+ (R_GEN_CONFIG__g8_15dir__##f6_##_VAL(R_GEN_CONFIG_, g8_15dir_, v6) << R_GEN_CONFIG__g8_15dir__BITNR) | \
+ (R_GEN_CONFIG__g0dir__##f7_##_VAL(R_GEN_CONFIG_, g0dir_, v7) << R_GEN_CONFIG__g0dir__BITNR) | \
+ (R_GEN_CONFIG__dma9__##f8_##_VAL(R_GEN_CONFIG_, dma9_, v8) << R_GEN_CONFIG__dma9__BITNR) | \
+ (R_GEN_CONFIG__dma8__##f9_##_VAL(R_GEN_CONFIG_, dma8_, v9) << R_GEN_CONFIG__dma8__BITNR) | \
+ (R_GEN_CONFIG__dma7__##f10_##_VAL(R_GEN_CONFIG_, dma7_, v10) << R_GEN_CONFIG__dma7__BITNR) | \
+ (R_GEN_CONFIG__dma6__##f11_##_VAL(R_GEN_CONFIG_, dma6_, v11) << R_GEN_CONFIG__dma6__BITNR) | \
+ (R_GEN_CONFIG__dma5__##f12_##_VAL(R_GEN_CONFIG_, dma5_, v12) << R_GEN_CONFIG__dma5__BITNR) | \
+ (R_GEN_CONFIG__dma4__##f13_##_VAL(R_GEN_CONFIG_, dma4_, v13) << R_GEN_CONFIG__dma4__BITNR) | \
+ (R_GEN_CONFIG__dma3__##f14_##_VAL(R_GEN_CONFIG_, dma3_, v14) << R_GEN_CONFIG__dma3__BITNR) | \
+ (R_GEN_CONFIG__dma2__##f15_##_VAL(R_GEN_CONFIG_, dma2_, v15) << R_GEN_CONFIG__dma2__BITNR) | \
+ (R_GEN_CONFIG__mio_w__##f16_##_VAL(R_GEN_CONFIG_, mio_w_, v16) << R_GEN_CONFIG__mio_w__BITNR) | \
+ (R_GEN_CONFIG__ser3__##f17_##_VAL(R_GEN_CONFIG_, ser3_, v17) << R_GEN_CONFIG__ser3__BITNR) | \
+ (R_GEN_CONFIG__par1__##f18_##_VAL(R_GEN_CONFIG_, par1_, v18) << R_GEN_CONFIG__par1__BITNR) | \
+ (R_GEN_CONFIG__scsi0w__##f19_##_VAL(R_GEN_CONFIG_, scsi0w_, v19) << R_GEN_CONFIG__scsi0w__BITNR) | \
+ (R_GEN_CONFIG__scsi1__##f20_##_VAL(R_GEN_CONFIG_, scsi1_, v20) << R_GEN_CONFIG__scsi1__BITNR) | \
+ (R_GEN_CONFIG__mio__##f21_##_VAL(R_GEN_CONFIG_, mio_, v21) << R_GEN_CONFIG__mio__BITNR) | \
+ (R_GEN_CONFIG__ser2__##f22_##_VAL(R_GEN_CONFIG_, ser2_, v22) << R_GEN_CONFIG__ser2__BITNR) | \
+ (R_GEN_CONFIG__par0__##f23_##_VAL(R_GEN_CONFIG_, par0_, v23) << R_GEN_CONFIG__par0__BITNR) | \
+ (R_GEN_CONFIG__ata__##f24_##_VAL(R_GEN_CONFIG_, ata_, v24) << R_GEN_CONFIG__ata__BITNR) | \
+ (R_GEN_CONFIG__scsi0__##f25_##_VAL(R_GEN_CONFIG_, scsi0_, v25) << R_GEN_CONFIG__scsi0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_GEN_CONFIG_II
+ * - type: WO
+ * - addr: 0xb0000034
+ * - group: General config registers
+ */
+
+#if USE_GROUP__General_config_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_GEN_CONFIG_II
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_GEN_CONFIG_II.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_GEN_CONFIG_II.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_GEN_CONFIG_II(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ *R_GEN_CONFIG_II__SADDR = ( \
+ REG_INITIATED(R_GEN_CONFIG_II_) \
+ REG_VAL__R_GEN_CONFIG_II_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \
+ ), \
+ R_GEN_CONFIG_II__WRITE(R_GEN_CONFIG_II__ADDR, *R_GEN_CONFIG_II__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_GEN_CONFIG_II__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_GEN_CONFIG_II.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_GEN_CONFIG_II.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_GEN_CONFIG_II__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ *R_GEN_CONFIG_II__SADDR = ( \
+ REG_INITIATED(R_GEN_CONFIG_II_) \
+ REG_VAL__R_GEN_CONFIG_II_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_GEN_CONFIG_II
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_GEN_CONFIG_II(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_GEN_CONFIG_II__sermode3__##f1##__MASK & REG__##v1) | \
+ (R_GEN_CONFIG_II__sermode1__##f2##__MASK & REG__##v2) | \
+ (R_GEN_CONFIG_II__ext_clk__##f3##__MASK & REG__##v3) | \
+ (R_GEN_CONFIG_II__ser3__##f4##__MASK & REG__##v4) | \
+ (R_GEN_CONFIG_II__ser2__##f5##__MASK & REG__##v5) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_GEN_CONFIG_II
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_GEN_CONFIG_II.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_GEN_CONFIG_II(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_GEN_CONFIG_II__sermode3__##f1##__VAL(R_GEN_CONFIG_II_, sermode3_, v1) << R_GEN_CONFIG_II__sermode3__BITNR) | \
+ (R_GEN_CONFIG_II__sermode1__##f2##__VAL(R_GEN_CONFIG_II_, sermode1_, v2) << R_GEN_CONFIG_II__sermode1__BITNR) | \
+ (R_GEN_CONFIG_II__ext_clk__##f3##__VAL(R_GEN_CONFIG_II_, ext_clk_, v3) << R_GEN_CONFIG_II__ext_clk__BITNR) | \
+ (R_GEN_CONFIG_II__ser3__##f4##__VAL(R_GEN_CONFIG_II_, ser3_, v4) << R_GEN_CONFIG_II__ser3__BITNR) | \
+ (R_GEN_CONFIG_II__ser2__##f5##__VAL(R_GEN_CONFIG_II_, ser2_, v5) << R_GEN_CONFIG_II__ser2__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_GEN_CONFIG_II_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_GEN_CONFIG_II.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_GEN_CONFIG_II_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \
+ (R_GEN_CONFIG_II__sermode3__##f1_##_VAL(R_GEN_CONFIG_II_, sermode3_, v1) << R_GEN_CONFIG_II__sermode3__BITNR) | \
+ (R_GEN_CONFIG_II__sermode1__##f2_##_VAL(R_GEN_CONFIG_II_, sermode1_, v2) << R_GEN_CONFIG_II__sermode1__BITNR) | \
+ (R_GEN_CONFIG_II__ext_clk__##f3_##_VAL(R_GEN_CONFIG_II_, ext_clk_, v3) << R_GEN_CONFIG_II__ext_clk__BITNR) | \
+ (R_GEN_CONFIG_II__ser3__##f4_##_VAL(R_GEN_CONFIG_II_, ser3_, v4) << R_GEN_CONFIG_II__ser3__BITNR) | \
+ (R_GEN_CONFIG_II__ser2__##f5_##_VAL(R_GEN_CONFIG_II_, ser2_, v5) << R_GEN_CONFIG_II__ser2__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK0_CLR
+ * - type: WO
+ * - addr: 0xb00000c0
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK0_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK0_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_IRQ_MASK0_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK0_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ *R_IRQ_MASK0_CLR__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK0_CLR_) \
+ REG_VAL__R_IRQ_MASK0_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28,f29##_,v29,f30##_,v30,f31##_,v31) \
+ ), \
+ R_IRQ_MASK0_CLR__WRITE(R_IRQ_MASK0_CLR__ADDR, *R_IRQ_MASK0_CLR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK0_CLR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK0_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_IRQ_MASK0_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK0_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ *R_IRQ_MASK0_CLR__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK0_CLR_) \
+ REG_VAL__R_IRQ_MASK0_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28,f29##_,v29,f30##_,v30,f31##_,v31) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK0_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK0_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ (R_IRQ_MASK0_CLR__nmi_pin__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK0_CLR__watchdog_nmi__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK0_CLR__sqe_test_error__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK0_CLR__carrier_loss__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK0_CLR__deferred__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK0_CLR__late_col__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK0_CLR__multiple_col__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK0_CLR__single_col__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK0_CLR__congestion__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK0_CLR__oversize__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK0_CLR__alignment_error__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK0_CLR__crc_error__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK0_CLR__overrun__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK0_CLR__underrun__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK0_CLR__excessive_col__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK0_CLR__mdio__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK0_CLR__ata_drq3__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK0_CLR__ata_drq2__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK0_CLR__ata_drq1__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK0_CLR__ata_drq0__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK0_CLR__par0_ecp_cmd__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK0_CLR__par0_peri__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK0_CLR__par0_data__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK0_CLR__par0_ready__##f24##__MASK & REG__##v24) | \
+ (R_IRQ_MASK0_CLR__ata_dmaend__##f25##__MASK & REG__##v25) | \
+ (R_IRQ_MASK0_CLR__irq_ext_vector_nr__##f26##__MASK & REG__##v26) | \
+ (R_IRQ_MASK0_CLR__irq_int_vector_nr__##f27##__MASK & REG__##v27) | \
+ (R_IRQ_MASK0_CLR__ext_dma1__##f28##__MASK & REG__##v28) | \
+ (R_IRQ_MASK0_CLR__ext_dma0__##f29##__MASK & REG__##v29) | \
+ (R_IRQ_MASK0_CLR__timer1__##f30##__MASK & REG__##v30) | \
+ (R_IRQ_MASK0_CLR__timer0__##f31##__MASK & REG__##v31) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK0_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK0_CLR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK0_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ (R_IRQ_MASK0_CLR__nmi_pin__##f1##__VAL(R_IRQ_MASK0_CLR_, nmi_pin_, v1) << R_IRQ_MASK0_CLR__nmi_pin__BITNR) | \
+ (R_IRQ_MASK0_CLR__watchdog_nmi__##f2##__VAL(R_IRQ_MASK0_CLR_, watchdog_nmi_, v2) << R_IRQ_MASK0_CLR__watchdog_nmi__BITNR) | \
+ (R_IRQ_MASK0_CLR__sqe_test_error__##f3##__VAL(R_IRQ_MASK0_CLR_, sqe_test_error_, v3) << R_IRQ_MASK0_CLR__sqe_test_error__BITNR) | \
+ (R_IRQ_MASK0_CLR__carrier_loss__##f4##__VAL(R_IRQ_MASK0_CLR_, carrier_loss_, v4) << R_IRQ_MASK0_CLR__carrier_loss__BITNR) | \
+ (R_IRQ_MASK0_CLR__deferred__##f5##__VAL(R_IRQ_MASK0_CLR_, deferred_, v5) << R_IRQ_MASK0_CLR__deferred__BITNR) | \
+ (R_IRQ_MASK0_CLR__late_col__##f6##__VAL(R_IRQ_MASK0_CLR_, late_col_, v6) << R_IRQ_MASK0_CLR__late_col__BITNR) | \
+ (R_IRQ_MASK0_CLR__multiple_col__##f7##__VAL(R_IRQ_MASK0_CLR_, multiple_col_, v7) << R_IRQ_MASK0_CLR__multiple_col__BITNR) | \
+ (R_IRQ_MASK0_CLR__single_col__##f8##__VAL(R_IRQ_MASK0_CLR_, single_col_, v8) << R_IRQ_MASK0_CLR__single_col__BITNR) | \
+ (R_IRQ_MASK0_CLR__congestion__##f9##__VAL(R_IRQ_MASK0_CLR_, congestion_, v9) << R_IRQ_MASK0_CLR__congestion__BITNR) | \
+ (R_IRQ_MASK0_CLR__oversize__##f10##__VAL(R_IRQ_MASK0_CLR_, oversize_, v10) << R_IRQ_MASK0_CLR__oversize__BITNR) | \
+ (R_IRQ_MASK0_CLR__alignment_error__##f11##__VAL(R_IRQ_MASK0_CLR_, alignment_error_, v11) << R_IRQ_MASK0_CLR__alignment_error__BITNR) | \
+ (R_IRQ_MASK0_CLR__crc_error__##f12##__VAL(R_IRQ_MASK0_CLR_, crc_error_, v12) << R_IRQ_MASK0_CLR__crc_error__BITNR) | \
+ (R_IRQ_MASK0_CLR__overrun__##f13##__VAL(R_IRQ_MASK0_CLR_, overrun_, v13) << R_IRQ_MASK0_CLR__overrun__BITNR) | \
+ (R_IRQ_MASK0_CLR__underrun__##f14##__VAL(R_IRQ_MASK0_CLR_, underrun_, v14) << R_IRQ_MASK0_CLR__underrun__BITNR) | \
+ (R_IRQ_MASK0_CLR__excessive_col__##f15##__VAL(R_IRQ_MASK0_CLR_, excessive_col_, v15) << R_IRQ_MASK0_CLR__excessive_col__BITNR) | \
+ (R_IRQ_MASK0_CLR__mdio__##f16##__VAL(R_IRQ_MASK0_CLR_, mdio_, v16) << R_IRQ_MASK0_CLR__mdio__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_drq3__##f17##__VAL(R_IRQ_MASK0_CLR_, ata_drq3_, v17) << R_IRQ_MASK0_CLR__ata_drq3__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_drq2__##f18##__VAL(R_IRQ_MASK0_CLR_, ata_drq2_, v18) << R_IRQ_MASK0_CLR__ata_drq2__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_drq1__##f19##__VAL(R_IRQ_MASK0_CLR_, ata_drq1_, v19) << R_IRQ_MASK0_CLR__ata_drq1__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_drq0__##f20##__VAL(R_IRQ_MASK0_CLR_, ata_drq0_, v20) << R_IRQ_MASK0_CLR__ata_drq0__BITNR) | \
+ (R_IRQ_MASK0_CLR__par0_ecp_cmd__##f21##__VAL(R_IRQ_MASK0_CLR_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK0_CLR__par0_peri__##f22##__VAL(R_IRQ_MASK0_CLR_, par0_peri_, v22) << R_IRQ_MASK0_CLR__par0_peri__BITNR) | \
+ (R_IRQ_MASK0_CLR__par0_data__##f23##__VAL(R_IRQ_MASK0_CLR_, par0_data_, v23) << R_IRQ_MASK0_CLR__par0_data__BITNR) | \
+ (R_IRQ_MASK0_CLR__par0_ready__##f24##__VAL(R_IRQ_MASK0_CLR_, par0_ready_, v24) << R_IRQ_MASK0_CLR__par0_ready__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_dmaend__##f25##__VAL(R_IRQ_MASK0_CLR_, ata_dmaend_, v25) << R_IRQ_MASK0_CLR__ata_dmaend__BITNR) | \
+ (R_IRQ_MASK0_CLR__irq_ext_vector_nr__##f26##__VAL(R_IRQ_MASK0_CLR_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_CLR__irq_int_vector_nr__##f27##__VAL(R_IRQ_MASK0_CLR_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_CLR__ext_dma1__##f28##__VAL(R_IRQ_MASK0_CLR_, ext_dma1_, v28) << R_IRQ_MASK0_CLR__ext_dma1__BITNR) | \
+ (R_IRQ_MASK0_CLR__ext_dma0__##f29##__VAL(R_IRQ_MASK0_CLR_, ext_dma0_, v29) << R_IRQ_MASK0_CLR__ext_dma0__BITNR) | \
+ (R_IRQ_MASK0_CLR__timer1__##f30##__VAL(R_IRQ_MASK0_CLR_, timer1_, v30) << R_IRQ_MASK0_CLR__timer1__BITNR) | \
+ (R_IRQ_MASK0_CLR__timer0__##f31##__VAL(R_IRQ_MASK0_CLR_, timer0_, v31) << R_IRQ_MASK0_CLR__timer0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK0_CLR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK0_CLR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK0_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28,f29_,v29,f30_,v30,f31_,v31) ( \
+ (R_IRQ_MASK0_CLR__nmi_pin__##f1_##_VAL(R_IRQ_MASK0_CLR_, nmi_pin_, v1) << R_IRQ_MASK0_CLR__nmi_pin__BITNR) | \
+ (R_IRQ_MASK0_CLR__watchdog_nmi__##f2_##_VAL(R_IRQ_MASK0_CLR_, watchdog_nmi_, v2) << R_IRQ_MASK0_CLR__watchdog_nmi__BITNR) | \
+ (R_IRQ_MASK0_CLR__sqe_test_error__##f3_##_VAL(R_IRQ_MASK0_CLR_, sqe_test_error_, v3) << R_IRQ_MASK0_CLR__sqe_test_error__BITNR) | \
+ (R_IRQ_MASK0_CLR__carrier_loss__##f4_##_VAL(R_IRQ_MASK0_CLR_, carrier_loss_, v4) << R_IRQ_MASK0_CLR__carrier_loss__BITNR) | \
+ (R_IRQ_MASK0_CLR__deferred__##f5_##_VAL(R_IRQ_MASK0_CLR_, deferred_, v5) << R_IRQ_MASK0_CLR__deferred__BITNR) | \
+ (R_IRQ_MASK0_CLR__late_col__##f6_##_VAL(R_IRQ_MASK0_CLR_, late_col_, v6) << R_IRQ_MASK0_CLR__late_col__BITNR) | \
+ (R_IRQ_MASK0_CLR__multiple_col__##f7_##_VAL(R_IRQ_MASK0_CLR_, multiple_col_, v7) << R_IRQ_MASK0_CLR__multiple_col__BITNR) | \
+ (R_IRQ_MASK0_CLR__single_col__##f8_##_VAL(R_IRQ_MASK0_CLR_, single_col_, v8) << R_IRQ_MASK0_CLR__single_col__BITNR) | \
+ (R_IRQ_MASK0_CLR__congestion__##f9_##_VAL(R_IRQ_MASK0_CLR_, congestion_, v9) << R_IRQ_MASK0_CLR__congestion__BITNR) | \
+ (R_IRQ_MASK0_CLR__oversize__##f10_##_VAL(R_IRQ_MASK0_CLR_, oversize_, v10) << R_IRQ_MASK0_CLR__oversize__BITNR) | \
+ (R_IRQ_MASK0_CLR__alignment_error__##f11_##_VAL(R_IRQ_MASK0_CLR_, alignment_error_, v11) << R_IRQ_MASK0_CLR__alignment_error__BITNR) | \
+ (R_IRQ_MASK0_CLR__crc_error__##f12_##_VAL(R_IRQ_MASK0_CLR_, crc_error_, v12) << R_IRQ_MASK0_CLR__crc_error__BITNR) | \
+ (R_IRQ_MASK0_CLR__overrun__##f13_##_VAL(R_IRQ_MASK0_CLR_, overrun_, v13) << R_IRQ_MASK0_CLR__overrun__BITNR) | \
+ (R_IRQ_MASK0_CLR__underrun__##f14_##_VAL(R_IRQ_MASK0_CLR_, underrun_, v14) << R_IRQ_MASK0_CLR__underrun__BITNR) | \
+ (R_IRQ_MASK0_CLR__excessive_col__##f15_##_VAL(R_IRQ_MASK0_CLR_, excessive_col_, v15) << R_IRQ_MASK0_CLR__excessive_col__BITNR) | \
+ (R_IRQ_MASK0_CLR__mdio__##f16_##_VAL(R_IRQ_MASK0_CLR_, mdio_, v16) << R_IRQ_MASK0_CLR__mdio__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_drq3__##f17_##_VAL(R_IRQ_MASK0_CLR_, ata_drq3_, v17) << R_IRQ_MASK0_CLR__ata_drq3__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_drq2__##f18_##_VAL(R_IRQ_MASK0_CLR_, ata_drq2_, v18) << R_IRQ_MASK0_CLR__ata_drq2__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_drq1__##f19_##_VAL(R_IRQ_MASK0_CLR_, ata_drq1_, v19) << R_IRQ_MASK0_CLR__ata_drq1__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_drq0__##f20_##_VAL(R_IRQ_MASK0_CLR_, ata_drq0_, v20) << R_IRQ_MASK0_CLR__ata_drq0__BITNR) | \
+ (R_IRQ_MASK0_CLR__par0_ecp_cmd__##f21_##_VAL(R_IRQ_MASK0_CLR_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK0_CLR__par0_peri__##f22_##_VAL(R_IRQ_MASK0_CLR_, par0_peri_, v22) << R_IRQ_MASK0_CLR__par0_peri__BITNR) | \
+ (R_IRQ_MASK0_CLR__par0_data__##f23_##_VAL(R_IRQ_MASK0_CLR_, par0_data_, v23) << R_IRQ_MASK0_CLR__par0_data__BITNR) | \
+ (R_IRQ_MASK0_CLR__par0_ready__##f24_##_VAL(R_IRQ_MASK0_CLR_, par0_ready_, v24) << R_IRQ_MASK0_CLR__par0_ready__BITNR) | \
+ (R_IRQ_MASK0_CLR__ata_dmaend__##f25_##_VAL(R_IRQ_MASK0_CLR_, ata_dmaend_, v25) << R_IRQ_MASK0_CLR__ata_dmaend__BITNR) | \
+ (R_IRQ_MASK0_CLR__irq_ext_vector_nr__##f26_##_VAL(R_IRQ_MASK0_CLR_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_CLR__irq_int_vector_nr__##f27_##_VAL(R_IRQ_MASK0_CLR_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_CLR__ext_dma1__##f28_##_VAL(R_IRQ_MASK0_CLR_, ext_dma1_, v28) << R_IRQ_MASK0_CLR__ext_dma1__BITNR) | \
+ (R_IRQ_MASK0_CLR__ext_dma0__##f29_##_VAL(R_IRQ_MASK0_CLR_, ext_dma0_, v29) << R_IRQ_MASK0_CLR__ext_dma0__BITNR) | \
+ (R_IRQ_MASK0_CLR__timer1__##f30_##_VAL(R_IRQ_MASK0_CLR_, timer1_, v30) << R_IRQ_MASK0_CLR__timer1__BITNR) | \
+ (R_IRQ_MASK0_CLR__timer0__##f31_##_VAL(R_IRQ_MASK0_CLR_, timer0_, v31) << R_IRQ_MASK0_CLR__timer0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK0_RD
+ * - type: RO
+ * - addr: 0xb00000c0
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK0_RD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK0_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ (R_IRQ_MASK0_RD__nmi_pin__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK0_RD__watchdog_nmi__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK0_RD__sqe_test_error__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK0_RD__carrier_loss__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK0_RD__deferred__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK0_RD__late_col__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK0_RD__multiple_col__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK0_RD__single_col__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK0_RD__congestion__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK0_RD__oversize__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK0_RD__alignment_error__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK0_RD__crc_error__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK0_RD__overrun__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK0_RD__underrun__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK0_RD__excessive_col__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK0_RD__mdio__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK0_RD__ata_drq3__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK0_RD__ata_drq2__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK0_RD__ata_drq1__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK0_RD__ata_drq0__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK0_RD__par0_ecp_cmd__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK0_RD__par0_peri__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK0_RD__par0_data__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK0_RD__par0_ready__##f24##__MASK & REG__##v24) | \
+ (R_IRQ_MASK0_RD__ata_dmaend__##f25##__MASK & REG__##v25) | \
+ (R_IRQ_MASK0_RD__irq_ext_vector_nr__##f26##__MASK & REG__##v26) | \
+ (R_IRQ_MASK0_RD__irq_int_vector_nr__##f27##__MASK & REG__##v27) | \
+ (R_IRQ_MASK0_RD__ext_dma1__##f28##__MASK & REG__##v28) | \
+ (R_IRQ_MASK0_RD__ext_dma0__##f29##__MASK & REG__##v29) | \
+ (R_IRQ_MASK0_RD__timer1__##f30##__MASK & REG__##v30) | \
+ (R_IRQ_MASK0_RD__timer0__##f31##__MASK & REG__##v31) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK0_RD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK0_RD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK0_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ (R_IRQ_MASK0_RD__nmi_pin__##f1##__VAL(R_IRQ_MASK0_RD_, nmi_pin_, v1) << R_IRQ_MASK0_RD__nmi_pin__BITNR) | \
+ (R_IRQ_MASK0_RD__watchdog_nmi__##f2##__VAL(R_IRQ_MASK0_RD_, watchdog_nmi_, v2) << R_IRQ_MASK0_RD__watchdog_nmi__BITNR) | \
+ (R_IRQ_MASK0_RD__sqe_test_error__##f3##__VAL(R_IRQ_MASK0_RD_, sqe_test_error_, v3) << R_IRQ_MASK0_RD__sqe_test_error__BITNR) | \
+ (R_IRQ_MASK0_RD__carrier_loss__##f4##__VAL(R_IRQ_MASK0_RD_, carrier_loss_, v4) << R_IRQ_MASK0_RD__carrier_loss__BITNR) | \
+ (R_IRQ_MASK0_RD__deferred__##f5##__VAL(R_IRQ_MASK0_RD_, deferred_, v5) << R_IRQ_MASK0_RD__deferred__BITNR) | \
+ (R_IRQ_MASK0_RD__late_col__##f6##__VAL(R_IRQ_MASK0_RD_, late_col_, v6) << R_IRQ_MASK0_RD__late_col__BITNR) | \
+ (R_IRQ_MASK0_RD__multiple_col__##f7##__VAL(R_IRQ_MASK0_RD_, multiple_col_, v7) << R_IRQ_MASK0_RD__multiple_col__BITNR) | \
+ (R_IRQ_MASK0_RD__single_col__##f8##__VAL(R_IRQ_MASK0_RD_, single_col_, v8) << R_IRQ_MASK0_RD__single_col__BITNR) | \
+ (R_IRQ_MASK0_RD__congestion__##f9##__VAL(R_IRQ_MASK0_RD_, congestion_, v9) << R_IRQ_MASK0_RD__congestion__BITNR) | \
+ (R_IRQ_MASK0_RD__oversize__##f10##__VAL(R_IRQ_MASK0_RD_, oversize_, v10) << R_IRQ_MASK0_RD__oversize__BITNR) | \
+ (R_IRQ_MASK0_RD__alignment_error__##f11##__VAL(R_IRQ_MASK0_RD_, alignment_error_, v11) << R_IRQ_MASK0_RD__alignment_error__BITNR) | \
+ (R_IRQ_MASK0_RD__crc_error__##f12##__VAL(R_IRQ_MASK0_RD_, crc_error_, v12) << R_IRQ_MASK0_RD__crc_error__BITNR) | \
+ (R_IRQ_MASK0_RD__overrun__##f13##__VAL(R_IRQ_MASK0_RD_, overrun_, v13) << R_IRQ_MASK0_RD__overrun__BITNR) | \
+ (R_IRQ_MASK0_RD__underrun__##f14##__VAL(R_IRQ_MASK0_RD_, underrun_, v14) << R_IRQ_MASK0_RD__underrun__BITNR) | \
+ (R_IRQ_MASK0_RD__excessive_col__##f15##__VAL(R_IRQ_MASK0_RD_, excessive_col_, v15) << R_IRQ_MASK0_RD__excessive_col__BITNR) | \
+ (R_IRQ_MASK0_RD__mdio__##f16##__VAL(R_IRQ_MASK0_RD_, mdio_, v16) << R_IRQ_MASK0_RD__mdio__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_drq3__##f17##__VAL(R_IRQ_MASK0_RD_, ata_drq3_, v17) << R_IRQ_MASK0_RD__ata_drq3__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_drq2__##f18##__VAL(R_IRQ_MASK0_RD_, ata_drq2_, v18) << R_IRQ_MASK0_RD__ata_drq2__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_drq1__##f19##__VAL(R_IRQ_MASK0_RD_, ata_drq1_, v19) << R_IRQ_MASK0_RD__ata_drq1__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_drq0__##f20##__VAL(R_IRQ_MASK0_RD_, ata_drq0_, v20) << R_IRQ_MASK0_RD__ata_drq0__BITNR) | \
+ (R_IRQ_MASK0_RD__par0_ecp_cmd__##f21##__VAL(R_IRQ_MASK0_RD_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK0_RD__par0_peri__##f22##__VAL(R_IRQ_MASK0_RD_, par0_peri_, v22) << R_IRQ_MASK0_RD__par0_peri__BITNR) | \
+ (R_IRQ_MASK0_RD__par0_data__##f23##__VAL(R_IRQ_MASK0_RD_, par0_data_, v23) << R_IRQ_MASK0_RD__par0_data__BITNR) | \
+ (R_IRQ_MASK0_RD__par0_ready__##f24##__VAL(R_IRQ_MASK0_RD_, par0_ready_, v24) << R_IRQ_MASK0_RD__par0_ready__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_dmaend__##f25##__VAL(R_IRQ_MASK0_RD_, ata_dmaend_, v25) << R_IRQ_MASK0_RD__ata_dmaend__BITNR) | \
+ (R_IRQ_MASK0_RD__irq_ext_vector_nr__##f26##__VAL(R_IRQ_MASK0_RD_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_RD__irq_int_vector_nr__##f27##__VAL(R_IRQ_MASK0_RD_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_RD__ext_dma1__##f28##__VAL(R_IRQ_MASK0_RD_, ext_dma1_, v28) << R_IRQ_MASK0_RD__ext_dma1__BITNR) | \
+ (R_IRQ_MASK0_RD__ext_dma0__##f29##__VAL(R_IRQ_MASK0_RD_, ext_dma0_, v29) << R_IRQ_MASK0_RD__ext_dma0__BITNR) | \
+ (R_IRQ_MASK0_RD__timer1__##f30##__VAL(R_IRQ_MASK0_RD_, timer1_, v30) << R_IRQ_MASK0_RD__timer1__BITNR) | \
+ (R_IRQ_MASK0_RD__timer0__##f31##__VAL(R_IRQ_MASK0_RD_, timer0_, v31) << R_IRQ_MASK0_RD__timer0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK0_RD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK0_RD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK0_RD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28,f29_,v29,f30_,v30,f31_,v31) ( \
+ (R_IRQ_MASK0_RD__nmi_pin__##f1_##_VAL(R_IRQ_MASK0_RD_, nmi_pin_, v1) << R_IRQ_MASK0_RD__nmi_pin__BITNR) | \
+ (R_IRQ_MASK0_RD__watchdog_nmi__##f2_##_VAL(R_IRQ_MASK0_RD_, watchdog_nmi_, v2) << R_IRQ_MASK0_RD__watchdog_nmi__BITNR) | \
+ (R_IRQ_MASK0_RD__sqe_test_error__##f3_##_VAL(R_IRQ_MASK0_RD_, sqe_test_error_, v3) << R_IRQ_MASK0_RD__sqe_test_error__BITNR) | \
+ (R_IRQ_MASK0_RD__carrier_loss__##f4_##_VAL(R_IRQ_MASK0_RD_, carrier_loss_, v4) << R_IRQ_MASK0_RD__carrier_loss__BITNR) | \
+ (R_IRQ_MASK0_RD__deferred__##f5_##_VAL(R_IRQ_MASK0_RD_, deferred_, v5) << R_IRQ_MASK0_RD__deferred__BITNR) | \
+ (R_IRQ_MASK0_RD__late_col__##f6_##_VAL(R_IRQ_MASK0_RD_, late_col_, v6) << R_IRQ_MASK0_RD__late_col__BITNR) | \
+ (R_IRQ_MASK0_RD__multiple_col__##f7_##_VAL(R_IRQ_MASK0_RD_, multiple_col_, v7) << R_IRQ_MASK0_RD__multiple_col__BITNR) | \
+ (R_IRQ_MASK0_RD__single_col__##f8_##_VAL(R_IRQ_MASK0_RD_, single_col_, v8) << R_IRQ_MASK0_RD__single_col__BITNR) | \
+ (R_IRQ_MASK0_RD__congestion__##f9_##_VAL(R_IRQ_MASK0_RD_, congestion_, v9) << R_IRQ_MASK0_RD__congestion__BITNR) | \
+ (R_IRQ_MASK0_RD__oversize__##f10_##_VAL(R_IRQ_MASK0_RD_, oversize_, v10) << R_IRQ_MASK0_RD__oversize__BITNR) | \
+ (R_IRQ_MASK0_RD__alignment_error__##f11_##_VAL(R_IRQ_MASK0_RD_, alignment_error_, v11) << R_IRQ_MASK0_RD__alignment_error__BITNR) | \
+ (R_IRQ_MASK0_RD__crc_error__##f12_##_VAL(R_IRQ_MASK0_RD_, crc_error_, v12) << R_IRQ_MASK0_RD__crc_error__BITNR) | \
+ (R_IRQ_MASK0_RD__overrun__##f13_##_VAL(R_IRQ_MASK0_RD_, overrun_, v13) << R_IRQ_MASK0_RD__overrun__BITNR) | \
+ (R_IRQ_MASK0_RD__underrun__##f14_##_VAL(R_IRQ_MASK0_RD_, underrun_, v14) << R_IRQ_MASK0_RD__underrun__BITNR) | \
+ (R_IRQ_MASK0_RD__excessive_col__##f15_##_VAL(R_IRQ_MASK0_RD_, excessive_col_, v15) << R_IRQ_MASK0_RD__excessive_col__BITNR) | \
+ (R_IRQ_MASK0_RD__mdio__##f16_##_VAL(R_IRQ_MASK0_RD_, mdio_, v16) << R_IRQ_MASK0_RD__mdio__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_drq3__##f17_##_VAL(R_IRQ_MASK0_RD_, ata_drq3_, v17) << R_IRQ_MASK0_RD__ata_drq3__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_drq2__##f18_##_VAL(R_IRQ_MASK0_RD_, ata_drq2_, v18) << R_IRQ_MASK0_RD__ata_drq2__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_drq1__##f19_##_VAL(R_IRQ_MASK0_RD_, ata_drq1_, v19) << R_IRQ_MASK0_RD__ata_drq1__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_drq0__##f20_##_VAL(R_IRQ_MASK0_RD_, ata_drq0_, v20) << R_IRQ_MASK0_RD__ata_drq0__BITNR) | \
+ (R_IRQ_MASK0_RD__par0_ecp_cmd__##f21_##_VAL(R_IRQ_MASK0_RD_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK0_RD__par0_peri__##f22_##_VAL(R_IRQ_MASK0_RD_, par0_peri_, v22) << R_IRQ_MASK0_RD__par0_peri__BITNR) | \
+ (R_IRQ_MASK0_RD__par0_data__##f23_##_VAL(R_IRQ_MASK0_RD_, par0_data_, v23) << R_IRQ_MASK0_RD__par0_data__BITNR) | \
+ (R_IRQ_MASK0_RD__par0_ready__##f24_##_VAL(R_IRQ_MASK0_RD_, par0_ready_, v24) << R_IRQ_MASK0_RD__par0_ready__BITNR) | \
+ (R_IRQ_MASK0_RD__ata_dmaend__##f25_##_VAL(R_IRQ_MASK0_RD_, ata_dmaend_, v25) << R_IRQ_MASK0_RD__ata_dmaend__BITNR) | \
+ (R_IRQ_MASK0_RD__irq_ext_vector_nr__##f26_##_VAL(R_IRQ_MASK0_RD_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_RD__irq_int_vector_nr__##f27_##_VAL(R_IRQ_MASK0_RD_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_RD__ext_dma1__##f28_##_VAL(R_IRQ_MASK0_RD_, ext_dma1_, v28) << R_IRQ_MASK0_RD__ext_dma1__BITNR) | \
+ (R_IRQ_MASK0_RD__ext_dma0__##f29_##_VAL(R_IRQ_MASK0_RD_, ext_dma0_, v29) << R_IRQ_MASK0_RD__ext_dma0__BITNR) | \
+ (R_IRQ_MASK0_RD__timer1__##f30_##_VAL(R_IRQ_MASK0_RD_, timer1_, v30) << R_IRQ_MASK0_RD__timer1__BITNR) | \
+ (R_IRQ_MASK0_RD__timer0__##f31_##_VAL(R_IRQ_MASK0_RD_, timer0_, v31) << R_IRQ_MASK0_RD__timer0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK0_SET
+ * - type: WO
+ * - addr: 0xb00000c4
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK0_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK0_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_IRQ_MASK0_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK0_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ *R_IRQ_MASK0_SET__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK0_SET_) \
+ REG_VAL__R_IRQ_MASK0_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28,f29##_,v29,f30##_,v30,f31##_,v31) \
+ ), \
+ R_IRQ_MASK0_SET__WRITE(R_IRQ_MASK0_SET__ADDR, *R_IRQ_MASK0_SET__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK0_SET__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK0_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_IRQ_MASK0_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK0_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ *R_IRQ_MASK0_SET__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK0_SET_) \
+ REG_VAL__R_IRQ_MASK0_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28,f29##_,v29,f30##_,v30,f31##_,v31) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK0_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK0_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ (R_IRQ_MASK0_SET__nmi_pin__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK0_SET__watchdog_nmi__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK0_SET__sqe_test_error__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK0_SET__carrier_loss__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK0_SET__deferred__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK0_SET__late_col__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK0_SET__multiple_col__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK0_SET__single_col__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK0_SET__congestion__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK0_SET__oversize__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK0_SET__alignment_error__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK0_SET__crc_error__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK0_SET__overrun__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK0_SET__underrun__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK0_SET__excessive_col__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK0_SET__mdio__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK0_SET__ata_drq3__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK0_SET__ata_drq2__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK0_SET__ata_drq1__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK0_SET__ata_drq0__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK0_SET__par0_ecp_cmd__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK0_SET__par0_peri__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK0_SET__par0_data__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK0_SET__par0_ready__##f24##__MASK & REG__##v24) | \
+ (R_IRQ_MASK0_SET__ata_dmaend__##f25##__MASK & REG__##v25) | \
+ (R_IRQ_MASK0_SET__irq_ext_vector_nr__##f26##__MASK & REG__##v26) | \
+ (R_IRQ_MASK0_SET__irq_int_vector_nr__##f27##__MASK & REG__##v27) | \
+ (R_IRQ_MASK0_SET__ext_dma1__##f28##__MASK & REG__##v28) | \
+ (R_IRQ_MASK0_SET__ext_dma0__##f29##__MASK & REG__##v29) | \
+ (R_IRQ_MASK0_SET__timer1__##f30##__MASK & REG__##v30) | \
+ (R_IRQ_MASK0_SET__timer0__##f31##__MASK & REG__##v31) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK0_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK0_SET.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK0_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ (R_IRQ_MASK0_SET__nmi_pin__##f1##__VAL(R_IRQ_MASK0_SET_, nmi_pin_, v1) << R_IRQ_MASK0_SET__nmi_pin__BITNR) | \
+ (R_IRQ_MASK0_SET__watchdog_nmi__##f2##__VAL(R_IRQ_MASK0_SET_, watchdog_nmi_, v2) << R_IRQ_MASK0_SET__watchdog_nmi__BITNR) | \
+ (R_IRQ_MASK0_SET__sqe_test_error__##f3##__VAL(R_IRQ_MASK0_SET_, sqe_test_error_, v3) << R_IRQ_MASK0_SET__sqe_test_error__BITNR) | \
+ (R_IRQ_MASK0_SET__carrier_loss__##f4##__VAL(R_IRQ_MASK0_SET_, carrier_loss_, v4) << R_IRQ_MASK0_SET__carrier_loss__BITNR) | \
+ (R_IRQ_MASK0_SET__deferred__##f5##__VAL(R_IRQ_MASK0_SET_, deferred_, v5) << R_IRQ_MASK0_SET__deferred__BITNR) | \
+ (R_IRQ_MASK0_SET__late_col__##f6##__VAL(R_IRQ_MASK0_SET_, late_col_, v6) << R_IRQ_MASK0_SET__late_col__BITNR) | \
+ (R_IRQ_MASK0_SET__multiple_col__##f7##__VAL(R_IRQ_MASK0_SET_, multiple_col_, v7) << R_IRQ_MASK0_SET__multiple_col__BITNR) | \
+ (R_IRQ_MASK0_SET__single_col__##f8##__VAL(R_IRQ_MASK0_SET_, single_col_, v8) << R_IRQ_MASK0_SET__single_col__BITNR) | \
+ (R_IRQ_MASK0_SET__congestion__##f9##__VAL(R_IRQ_MASK0_SET_, congestion_, v9) << R_IRQ_MASK0_SET__congestion__BITNR) | \
+ (R_IRQ_MASK0_SET__oversize__##f10##__VAL(R_IRQ_MASK0_SET_, oversize_, v10) << R_IRQ_MASK0_SET__oversize__BITNR) | \
+ (R_IRQ_MASK0_SET__alignment_error__##f11##__VAL(R_IRQ_MASK0_SET_, alignment_error_, v11) << R_IRQ_MASK0_SET__alignment_error__BITNR) | \
+ (R_IRQ_MASK0_SET__crc_error__##f12##__VAL(R_IRQ_MASK0_SET_, crc_error_, v12) << R_IRQ_MASK0_SET__crc_error__BITNR) | \
+ (R_IRQ_MASK0_SET__overrun__##f13##__VAL(R_IRQ_MASK0_SET_, overrun_, v13) << R_IRQ_MASK0_SET__overrun__BITNR) | \
+ (R_IRQ_MASK0_SET__underrun__##f14##__VAL(R_IRQ_MASK0_SET_, underrun_, v14) << R_IRQ_MASK0_SET__underrun__BITNR) | \
+ (R_IRQ_MASK0_SET__excessive_col__##f15##__VAL(R_IRQ_MASK0_SET_, excessive_col_, v15) << R_IRQ_MASK0_SET__excessive_col__BITNR) | \
+ (R_IRQ_MASK0_SET__mdio__##f16##__VAL(R_IRQ_MASK0_SET_, mdio_, v16) << R_IRQ_MASK0_SET__mdio__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_drq3__##f17##__VAL(R_IRQ_MASK0_SET_, ata_drq3_, v17) << R_IRQ_MASK0_SET__ata_drq3__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_drq2__##f18##__VAL(R_IRQ_MASK0_SET_, ata_drq2_, v18) << R_IRQ_MASK0_SET__ata_drq2__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_drq1__##f19##__VAL(R_IRQ_MASK0_SET_, ata_drq1_, v19) << R_IRQ_MASK0_SET__ata_drq1__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_drq0__##f20##__VAL(R_IRQ_MASK0_SET_, ata_drq0_, v20) << R_IRQ_MASK0_SET__ata_drq0__BITNR) | \
+ (R_IRQ_MASK0_SET__par0_ecp_cmd__##f21##__VAL(R_IRQ_MASK0_SET_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK0_SET__par0_peri__##f22##__VAL(R_IRQ_MASK0_SET_, par0_peri_, v22) << R_IRQ_MASK0_SET__par0_peri__BITNR) | \
+ (R_IRQ_MASK0_SET__par0_data__##f23##__VAL(R_IRQ_MASK0_SET_, par0_data_, v23) << R_IRQ_MASK0_SET__par0_data__BITNR) | \
+ (R_IRQ_MASK0_SET__par0_ready__##f24##__VAL(R_IRQ_MASK0_SET_, par0_ready_, v24) << R_IRQ_MASK0_SET__par0_ready__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_dmaend__##f25##__VAL(R_IRQ_MASK0_SET_, ata_dmaend_, v25) << R_IRQ_MASK0_SET__ata_dmaend__BITNR) | \
+ (R_IRQ_MASK0_SET__irq_ext_vector_nr__##f26##__VAL(R_IRQ_MASK0_SET_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_SET__irq_int_vector_nr__##f27##__VAL(R_IRQ_MASK0_SET_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_SET__ext_dma1__##f28##__VAL(R_IRQ_MASK0_SET_, ext_dma1_, v28) << R_IRQ_MASK0_SET__ext_dma1__BITNR) | \
+ (R_IRQ_MASK0_SET__ext_dma0__##f29##__VAL(R_IRQ_MASK0_SET_, ext_dma0_, v29) << R_IRQ_MASK0_SET__ext_dma0__BITNR) | \
+ (R_IRQ_MASK0_SET__timer1__##f30##__VAL(R_IRQ_MASK0_SET_, timer1_, v30) << R_IRQ_MASK0_SET__timer1__BITNR) | \
+ (R_IRQ_MASK0_SET__timer0__##f31##__VAL(R_IRQ_MASK0_SET_, timer0_, v31) << R_IRQ_MASK0_SET__timer0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK0_SET_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK0_SET.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK0_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28,f29_,v29,f30_,v30,f31_,v31) ( \
+ (R_IRQ_MASK0_SET__nmi_pin__##f1_##_VAL(R_IRQ_MASK0_SET_, nmi_pin_, v1) << R_IRQ_MASK0_SET__nmi_pin__BITNR) | \
+ (R_IRQ_MASK0_SET__watchdog_nmi__##f2_##_VAL(R_IRQ_MASK0_SET_, watchdog_nmi_, v2) << R_IRQ_MASK0_SET__watchdog_nmi__BITNR) | \
+ (R_IRQ_MASK0_SET__sqe_test_error__##f3_##_VAL(R_IRQ_MASK0_SET_, sqe_test_error_, v3) << R_IRQ_MASK0_SET__sqe_test_error__BITNR) | \
+ (R_IRQ_MASK0_SET__carrier_loss__##f4_##_VAL(R_IRQ_MASK0_SET_, carrier_loss_, v4) << R_IRQ_MASK0_SET__carrier_loss__BITNR) | \
+ (R_IRQ_MASK0_SET__deferred__##f5_##_VAL(R_IRQ_MASK0_SET_, deferred_, v5) << R_IRQ_MASK0_SET__deferred__BITNR) | \
+ (R_IRQ_MASK0_SET__late_col__##f6_##_VAL(R_IRQ_MASK0_SET_, late_col_, v6) << R_IRQ_MASK0_SET__late_col__BITNR) | \
+ (R_IRQ_MASK0_SET__multiple_col__##f7_##_VAL(R_IRQ_MASK0_SET_, multiple_col_, v7) << R_IRQ_MASK0_SET__multiple_col__BITNR) | \
+ (R_IRQ_MASK0_SET__single_col__##f8_##_VAL(R_IRQ_MASK0_SET_, single_col_, v8) << R_IRQ_MASK0_SET__single_col__BITNR) | \
+ (R_IRQ_MASK0_SET__congestion__##f9_##_VAL(R_IRQ_MASK0_SET_, congestion_, v9) << R_IRQ_MASK0_SET__congestion__BITNR) | \
+ (R_IRQ_MASK0_SET__oversize__##f10_##_VAL(R_IRQ_MASK0_SET_, oversize_, v10) << R_IRQ_MASK0_SET__oversize__BITNR) | \
+ (R_IRQ_MASK0_SET__alignment_error__##f11_##_VAL(R_IRQ_MASK0_SET_, alignment_error_, v11) << R_IRQ_MASK0_SET__alignment_error__BITNR) | \
+ (R_IRQ_MASK0_SET__crc_error__##f12_##_VAL(R_IRQ_MASK0_SET_, crc_error_, v12) << R_IRQ_MASK0_SET__crc_error__BITNR) | \
+ (R_IRQ_MASK0_SET__overrun__##f13_##_VAL(R_IRQ_MASK0_SET_, overrun_, v13) << R_IRQ_MASK0_SET__overrun__BITNR) | \
+ (R_IRQ_MASK0_SET__underrun__##f14_##_VAL(R_IRQ_MASK0_SET_, underrun_, v14) << R_IRQ_MASK0_SET__underrun__BITNR) | \
+ (R_IRQ_MASK0_SET__excessive_col__##f15_##_VAL(R_IRQ_MASK0_SET_, excessive_col_, v15) << R_IRQ_MASK0_SET__excessive_col__BITNR) | \
+ (R_IRQ_MASK0_SET__mdio__##f16_##_VAL(R_IRQ_MASK0_SET_, mdio_, v16) << R_IRQ_MASK0_SET__mdio__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_drq3__##f17_##_VAL(R_IRQ_MASK0_SET_, ata_drq3_, v17) << R_IRQ_MASK0_SET__ata_drq3__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_drq2__##f18_##_VAL(R_IRQ_MASK0_SET_, ata_drq2_, v18) << R_IRQ_MASK0_SET__ata_drq2__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_drq1__##f19_##_VAL(R_IRQ_MASK0_SET_, ata_drq1_, v19) << R_IRQ_MASK0_SET__ata_drq1__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_drq0__##f20_##_VAL(R_IRQ_MASK0_SET_, ata_drq0_, v20) << R_IRQ_MASK0_SET__ata_drq0__BITNR) | \
+ (R_IRQ_MASK0_SET__par0_ecp_cmd__##f21_##_VAL(R_IRQ_MASK0_SET_, par0_ecp_cmd_, v21) << R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK0_SET__par0_peri__##f22_##_VAL(R_IRQ_MASK0_SET_, par0_peri_, v22) << R_IRQ_MASK0_SET__par0_peri__BITNR) | \
+ (R_IRQ_MASK0_SET__par0_data__##f23_##_VAL(R_IRQ_MASK0_SET_, par0_data_, v23) << R_IRQ_MASK0_SET__par0_data__BITNR) | \
+ (R_IRQ_MASK0_SET__par0_ready__##f24_##_VAL(R_IRQ_MASK0_SET_, par0_ready_, v24) << R_IRQ_MASK0_SET__par0_ready__BITNR) | \
+ (R_IRQ_MASK0_SET__ata_dmaend__##f25_##_VAL(R_IRQ_MASK0_SET_, ata_dmaend_, v25) << R_IRQ_MASK0_SET__ata_dmaend__BITNR) | \
+ (R_IRQ_MASK0_SET__irq_ext_vector_nr__##f26_##_VAL(R_IRQ_MASK0_SET_, irq_ext_vector_nr_, v26) << R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_SET__irq_int_vector_nr__##f27_##_VAL(R_IRQ_MASK0_SET_, irq_int_vector_nr_, v27) << R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR) | \
+ (R_IRQ_MASK0_SET__ext_dma1__##f28_##_VAL(R_IRQ_MASK0_SET_, ext_dma1_, v28) << R_IRQ_MASK0_SET__ext_dma1__BITNR) | \
+ (R_IRQ_MASK0_SET__ext_dma0__##f29_##_VAL(R_IRQ_MASK0_SET_, ext_dma0_, v29) << R_IRQ_MASK0_SET__ext_dma0__BITNR) | \
+ (R_IRQ_MASK0_SET__timer1__##f30_##_VAL(R_IRQ_MASK0_SET_, timer1_, v30) << R_IRQ_MASK0_SET__timer1__BITNR) | \
+ (R_IRQ_MASK0_SET__timer0__##f31_##_VAL(R_IRQ_MASK0_SET_, timer0_, v31) << R_IRQ_MASK0_SET__timer0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK1_CLR
+ * - type: WO
+ * - addr: 0xb00000c8
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK1_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK1_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_IRQ_MASK1_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK1_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ *R_IRQ_MASK1_CLR__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK1_CLR_) \
+ REG_VAL__R_IRQ_MASK1_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28) \
+ ), \
+ R_IRQ_MASK1_CLR__WRITE(R_IRQ_MASK1_CLR__ADDR, *R_IRQ_MASK1_CLR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK1_CLR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK1_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_IRQ_MASK1_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK1_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ *R_IRQ_MASK1_CLR__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK1_CLR_) \
+ REG_VAL__R_IRQ_MASK1_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK1_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK1_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ (R_IRQ_MASK1_CLR__sw_int7__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK1_CLR__sw_int6__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK1_CLR__sw_int5__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK1_CLR__sw_int4__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK1_CLR__sw_int3__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK1_CLR__sw_int2__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK1_CLR__sw_int1__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK1_CLR__sw_int0__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK1_CLR__par1_ecp_cmd__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK1_CLR__par1_peri__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK1_CLR__par1_data__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK1_CLR__par1_ready__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK1_CLR__ser3_ready__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK1_CLR__ser3_data__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK1_CLR__ser2_ready__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK1_CLR__ser2_data__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK1_CLR__ser1_ready__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK1_CLR__ser1_data__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK1_CLR__ser0_ready__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK1_CLR__ser0_data__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK1_CLR__pa7__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK1_CLR__pa6__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK1_CLR__pa5__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK1_CLR__pa4__##f24##__MASK & REG__##v24) | \
+ (R_IRQ_MASK1_CLR__pa3__##f25##__MASK & REG__##v25) | \
+ (R_IRQ_MASK1_CLR__pa2__##f26##__MASK & REG__##v26) | \
+ (R_IRQ_MASK1_CLR__pa1__##f27##__MASK & REG__##v27) | \
+ (R_IRQ_MASK1_CLR__pa0__##f28##__MASK & REG__##v28) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK1_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK1_CLR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK1_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ (R_IRQ_MASK1_CLR__sw_int7__##f1##__VAL(R_IRQ_MASK1_CLR_, sw_int7_, v1) << R_IRQ_MASK1_CLR__sw_int7__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int6__##f2##__VAL(R_IRQ_MASK1_CLR_, sw_int6_, v2) << R_IRQ_MASK1_CLR__sw_int6__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int5__##f3##__VAL(R_IRQ_MASK1_CLR_, sw_int5_, v3) << R_IRQ_MASK1_CLR__sw_int5__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int4__##f4##__VAL(R_IRQ_MASK1_CLR_, sw_int4_, v4) << R_IRQ_MASK1_CLR__sw_int4__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int3__##f5##__VAL(R_IRQ_MASK1_CLR_, sw_int3_, v5) << R_IRQ_MASK1_CLR__sw_int3__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int2__##f6##__VAL(R_IRQ_MASK1_CLR_, sw_int2_, v6) << R_IRQ_MASK1_CLR__sw_int2__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int1__##f7##__VAL(R_IRQ_MASK1_CLR_, sw_int1_, v7) << R_IRQ_MASK1_CLR__sw_int1__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int0__##f8##__VAL(R_IRQ_MASK1_CLR_, sw_int0_, v8) << R_IRQ_MASK1_CLR__sw_int0__BITNR) | \
+ (R_IRQ_MASK1_CLR__par1_ecp_cmd__##f9##__VAL(R_IRQ_MASK1_CLR_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK1_CLR__par1_peri__##f10##__VAL(R_IRQ_MASK1_CLR_, par1_peri_, v10) << R_IRQ_MASK1_CLR__par1_peri__BITNR) | \
+ (R_IRQ_MASK1_CLR__par1_data__##f11##__VAL(R_IRQ_MASK1_CLR_, par1_data_, v11) << R_IRQ_MASK1_CLR__par1_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__par1_ready__##f12##__VAL(R_IRQ_MASK1_CLR_, par1_ready_, v12) << R_IRQ_MASK1_CLR__par1_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser3_ready__##f13##__VAL(R_IRQ_MASK1_CLR_, ser3_ready_, v13) << R_IRQ_MASK1_CLR__ser3_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser3_data__##f14##__VAL(R_IRQ_MASK1_CLR_, ser3_data_, v14) << R_IRQ_MASK1_CLR__ser3_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser2_ready__##f15##__VAL(R_IRQ_MASK1_CLR_, ser2_ready_, v15) << R_IRQ_MASK1_CLR__ser2_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser2_data__##f16##__VAL(R_IRQ_MASK1_CLR_, ser2_data_, v16) << R_IRQ_MASK1_CLR__ser2_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser1_ready__##f17##__VAL(R_IRQ_MASK1_CLR_, ser1_ready_, v17) << R_IRQ_MASK1_CLR__ser1_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser1_data__##f18##__VAL(R_IRQ_MASK1_CLR_, ser1_data_, v18) << R_IRQ_MASK1_CLR__ser1_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser0_ready__##f19##__VAL(R_IRQ_MASK1_CLR_, ser0_ready_, v19) << R_IRQ_MASK1_CLR__ser0_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser0_data__##f20##__VAL(R_IRQ_MASK1_CLR_, ser0_data_, v20) << R_IRQ_MASK1_CLR__ser0_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa7__##f21##__VAL(R_IRQ_MASK1_CLR_, pa7_, v21) << R_IRQ_MASK1_CLR__pa7__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa6__##f22##__VAL(R_IRQ_MASK1_CLR_, pa6_, v22) << R_IRQ_MASK1_CLR__pa6__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa5__##f23##__VAL(R_IRQ_MASK1_CLR_, pa5_, v23) << R_IRQ_MASK1_CLR__pa5__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa4__##f24##__VAL(R_IRQ_MASK1_CLR_, pa4_, v24) << R_IRQ_MASK1_CLR__pa4__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa3__##f25##__VAL(R_IRQ_MASK1_CLR_, pa3_, v25) << R_IRQ_MASK1_CLR__pa3__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa2__##f26##__VAL(R_IRQ_MASK1_CLR_, pa2_, v26) << R_IRQ_MASK1_CLR__pa2__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa1__##f27##__VAL(R_IRQ_MASK1_CLR_, pa1_, v27) << R_IRQ_MASK1_CLR__pa1__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa0__##f28##__VAL(R_IRQ_MASK1_CLR_, pa0_, v28) << R_IRQ_MASK1_CLR__pa0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK1_CLR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK1_CLR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK1_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28) ( \
+ (R_IRQ_MASK1_CLR__sw_int7__##f1_##_VAL(R_IRQ_MASK1_CLR_, sw_int7_, v1) << R_IRQ_MASK1_CLR__sw_int7__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int6__##f2_##_VAL(R_IRQ_MASK1_CLR_, sw_int6_, v2) << R_IRQ_MASK1_CLR__sw_int6__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int5__##f3_##_VAL(R_IRQ_MASK1_CLR_, sw_int5_, v3) << R_IRQ_MASK1_CLR__sw_int5__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int4__##f4_##_VAL(R_IRQ_MASK1_CLR_, sw_int4_, v4) << R_IRQ_MASK1_CLR__sw_int4__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int3__##f5_##_VAL(R_IRQ_MASK1_CLR_, sw_int3_, v5) << R_IRQ_MASK1_CLR__sw_int3__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int2__##f6_##_VAL(R_IRQ_MASK1_CLR_, sw_int2_, v6) << R_IRQ_MASK1_CLR__sw_int2__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int1__##f7_##_VAL(R_IRQ_MASK1_CLR_, sw_int1_, v7) << R_IRQ_MASK1_CLR__sw_int1__BITNR) | \
+ (R_IRQ_MASK1_CLR__sw_int0__##f8_##_VAL(R_IRQ_MASK1_CLR_, sw_int0_, v8) << R_IRQ_MASK1_CLR__sw_int0__BITNR) | \
+ (R_IRQ_MASK1_CLR__par1_ecp_cmd__##f9_##_VAL(R_IRQ_MASK1_CLR_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK1_CLR__par1_peri__##f10_##_VAL(R_IRQ_MASK1_CLR_, par1_peri_, v10) << R_IRQ_MASK1_CLR__par1_peri__BITNR) | \
+ (R_IRQ_MASK1_CLR__par1_data__##f11_##_VAL(R_IRQ_MASK1_CLR_, par1_data_, v11) << R_IRQ_MASK1_CLR__par1_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__par1_ready__##f12_##_VAL(R_IRQ_MASK1_CLR_, par1_ready_, v12) << R_IRQ_MASK1_CLR__par1_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser3_ready__##f13_##_VAL(R_IRQ_MASK1_CLR_, ser3_ready_, v13) << R_IRQ_MASK1_CLR__ser3_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser3_data__##f14_##_VAL(R_IRQ_MASK1_CLR_, ser3_data_, v14) << R_IRQ_MASK1_CLR__ser3_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser2_ready__##f15_##_VAL(R_IRQ_MASK1_CLR_, ser2_ready_, v15) << R_IRQ_MASK1_CLR__ser2_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser2_data__##f16_##_VAL(R_IRQ_MASK1_CLR_, ser2_data_, v16) << R_IRQ_MASK1_CLR__ser2_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser1_ready__##f17_##_VAL(R_IRQ_MASK1_CLR_, ser1_ready_, v17) << R_IRQ_MASK1_CLR__ser1_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser1_data__##f18_##_VAL(R_IRQ_MASK1_CLR_, ser1_data_, v18) << R_IRQ_MASK1_CLR__ser1_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser0_ready__##f19_##_VAL(R_IRQ_MASK1_CLR_, ser0_ready_, v19) << R_IRQ_MASK1_CLR__ser0_ready__BITNR) | \
+ (R_IRQ_MASK1_CLR__ser0_data__##f20_##_VAL(R_IRQ_MASK1_CLR_, ser0_data_, v20) << R_IRQ_MASK1_CLR__ser0_data__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa7__##f21_##_VAL(R_IRQ_MASK1_CLR_, pa7_, v21) << R_IRQ_MASK1_CLR__pa7__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa6__##f22_##_VAL(R_IRQ_MASK1_CLR_, pa6_, v22) << R_IRQ_MASK1_CLR__pa6__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa5__##f23_##_VAL(R_IRQ_MASK1_CLR_, pa5_, v23) << R_IRQ_MASK1_CLR__pa5__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa4__##f24_##_VAL(R_IRQ_MASK1_CLR_, pa4_, v24) << R_IRQ_MASK1_CLR__pa4__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa3__##f25_##_VAL(R_IRQ_MASK1_CLR_, pa3_, v25) << R_IRQ_MASK1_CLR__pa3__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa2__##f26_##_VAL(R_IRQ_MASK1_CLR_, pa2_, v26) << R_IRQ_MASK1_CLR__pa2__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa1__##f27_##_VAL(R_IRQ_MASK1_CLR_, pa1_, v27) << R_IRQ_MASK1_CLR__pa1__BITNR) | \
+ (R_IRQ_MASK1_CLR__pa0__##f28_##_VAL(R_IRQ_MASK1_CLR_, pa0_, v28) << R_IRQ_MASK1_CLR__pa0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK1_RD
+ * - type: RO
+ * - addr: 0xb00000c8
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK1_RD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK1_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ (R_IRQ_MASK1_RD__sw_int7__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK1_RD__sw_int6__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK1_RD__sw_int5__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK1_RD__sw_int4__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK1_RD__sw_int3__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK1_RD__sw_int2__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK1_RD__sw_int1__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK1_RD__sw_int0__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK1_RD__par1_ecp_cmd__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK1_RD__par1_peri__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK1_RD__par1_data__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK1_RD__par1_ready__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK1_RD__ser3_ready__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK1_RD__ser3_data__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK1_RD__ser2_ready__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK1_RD__ser2_data__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK1_RD__ser1_ready__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK1_RD__ser1_data__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK1_RD__ser0_ready__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK1_RD__ser0_data__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK1_RD__pa7__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK1_RD__pa6__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK1_RD__pa5__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK1_RD__pa4__##f24##__MASK & REG__##v24) | \
+ (R_IRQ_MASK1_RD__pa3__##f25##__MASK & REG__##v25) | \
+ (R_IRQ_MASK1_RD__pa2__##f26##__MASK & REG__##v26) | \
+ (R_IRQ_MASK1_RD__pa1__##f27##__MASK & REG__##v27) | \
+ (R_IRQ_MASK1_RD__pa0__##f28##__MASK & REG__##v28) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK1_RD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK1_RD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK1_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ (R_IRQ_MASK1_RD__sw_int7__##f1##__VAL(R_IRQ_MASK1_RD_, sw_int7_, v1) << R_IRQ_MASK1_RD__sw_int7__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int6__##f2##__VAL(R_IRQ_MASK1_RD_, sw_int6_, v2) << R_IRQ_MASK1_RD__sw_int6__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int5__##f3##__VAL(R_IRQ_MASK1_RD_, sw_int5_, v3) << R_IRQ_MASK1_RD__sw_int5__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int4__##f4##__VAL(R_IRQ_MASK1_RD_, sw_int4_, v4) << R_IRQ_MASK1_RD__sw_int4__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int3__##f5##__VAL(R_IRQ_MASK1_RD_, sw_int3_, v5) << R_IRQ_MASK1_RD__sw_int3__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int2__##f6##__VAL(R_IRQ_MASK1_RD_, sw_int2_, v6) << R_IRQ_MASK1_RD__sw_int2__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int1__##f7##__VAL(R_IRQ_MASK1_RD_, sw_int1_, v7) << R_IRQ_MASK1_RD__sw_int1__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int0__##f8##__VAL(R_IRQ_MASK1_RD_, sw_int0_, v8) << R_IRQ_MASK1_RD__sw_int0__BITNR) | \
+ (R_IRQ_MASK1_RD__par1_ecp_cmd__##f9##__VAL(R_IRQ_MASK1_RD_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK1_RD__par1_peri__##f10##__VAL(R_IRQ_MASK1_RD_, par1_peri_, v10) << R_IRQ_MASK1_RD__par1_peri__BITNR) | \
+ (R_IRQ_MASK1_RD__par1_data__##f11##__VAL(R_IRQ_MASK1_RD_, par1_data_, v11) << R_IRQ_MASK1_RD__par1_data__BITNR) | \
+ (R_IRQ_MASK1_RD__par1_ready__##f12##__VAL(R_IRQ_MASK1_RD_, par1_ready_, v12) << R_IRQ_MASK1_RD__par1_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser3_ready__##f13##__VAL(R_IRQ_MASK1_RD_, ser3_ready_, v13) << R_IRQ_MASK1_RD__ser3_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser3_data__##f14##__VAL(R_IRQ_MASK1_RD_, ser3_data_, v14) << R_IRQ_MASK1_RD__ser3_data__BITNR) | \
+ (R_IRQ_MASK1_RD__ser2_ready__##f15##__VAL(R_IRQ_MASK1_RD_, ser2_ready_, v15) << R_IRQ_MASK1_RD__ser2_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser2_data__##f16##__VAL(R_IRQ_MASK1_RD_, ser2_data_, v16) << R_IRQ_MASK1_RD__ser2_data__BITNR) | \
+ (R_IRQ_MASK1_RD__ser1_ready__##f17##__VAL(R_IRQ_MASK1_RD_, ser1_ready_, v17) << R_IRQ_MASK1_RD__ser1_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser1_data__##f18##__VAL(R_IRQ_MASK1_RD_, ser1_data_, v18) << R_IRQ_MASK1_RD__ser1_data__BITNR) | \
+ (R_IRQ_MASK1_RD__ser0_ready__##f19##__VAL(R_IRQ_MASK1_RD_, ser0_ready_, v19) << R_IRQ_MASK1_RD__ser0_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser0_data__##f20##__VAL(R_IRQ_MASK1_RD_, ser0_data_, v20) << R_IRQ_MASK1_RD__ser0_data__BITNR) | \
+ (R_IRQ_MASK1_RD__pa7__##f21##__VAL(R_IRQ_MASK1_RD_, pa7_, v21) << R_IRQ_MASK1_RD__pa7__BITNR) | \
+ (R_IRQ_MASK1_RD__pa6__##f22##__VAL(R_IRQ_MASK1_RD_, pa6_, v22) << R_IRQ_MASK1_RD__pa6__BITNR) | \
+ (R_IRQ_MASK1_RD__pa5__##f23##__VAL(R_IRQ_MASK1_RD_, pa5_, v23) << R_IRQ_MASK1_RD__pa5__BITNR) | \
+ (R_IRQ_MASK1_RD__pa4__##f24##__VAL(R_IRQ_MASK1_RD_, pa4_, v24) << R_IRQ_MASK1_RD__pa4__BITNR) | \
+ (R_IRQ_MASK1_RD__pa3__##f25##__VAL(R_IRQ_MASK1_RD_, pa3_, v25) << R_IRQ_MASK1_RD__pa3__BITNR) | \
+ (R_IRQ_MASK1_RD__pa2__##f26##__VAL(R_IRQ_MASK1_RD_, pa2_, v26) << R_IRQ_MASK1_RD__pa2__BITNR) | \
+ (R_IRQ_MASK1_RD__pa1__##f27##__VAL(R_IRQ_MASK1_RD_, pa1_, v27) << R_IRQ_MASK1_RD__pa1__BITNR) | \
+ (R_IRQ_MASK1_RD__pa0__##f28##__VAL(R_IRQ_MASK1_RD_, pa0_, v28) << R_IRQ_MASK1_RD__pa0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK1_RD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK1_RD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK1_RD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28) ( \
+ (R_IRQ_MASK1_RD__sw_int7__##f1_##_VAL(R_IRQ_MASK1_RD_, sw_int7_, v1) << R_IRQ_MASK1_RD__sw_int7__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int6__##f2_##_VAL(R_IRQ_MASK1_RD_, sw_int6_, v2) << R_IRQ_MASK1_RD__sw_int6__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int5__##f3_##_VAL(R_IRQ_MASK1_RD_, sw_int5_, v3) << R_IRQ_MASK1_RD__sw_int5__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int4__##f4_##_VAL(R_IRQ_MASK1_RD_, sw_int4_, v4) << R_IRQ_MASK1_RD__sw_int4__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int3__##f5_##_VAL(R_IRQ_MASK1_RD_, sw_int3_, v5) << R_IRQ_MASK1_RD__sw_int3__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int2__##f6_##_VAL(R_IRQ_MASK1_RD_, sw_int2_, v6) << R_IRQ_MASK1_RD__sw_int2__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int1__##f7_##_VAL(R_IRQ_MASK1_RD_, sw_int1_, v7) << R_IRQ_MASK1_RD__sw_int1__BITNR) | \
+ (R_IRQ_MASK1_RD__sw_int0__##f8_##_VAL(R_IRQ_MASK1_RD_, sw_int0_, v8) << R_IRQ_MASK1_RD__sw_int0__BITNR) | \
+ (R_IRQ_MASK1_RD__par1_ecp_cmd__##f9_##_VAL(R_IRQ_MASK1_RD_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK1_RD__par1_peri__##f10_##_VAL(R_IRQ_MASK1_RD_, par1_peri_, v10) << R_IRQ_MASK1_RD__par1_peri__BITNR) | \
+ (R_IRQ_MASK1_RD__par1_data__##f11_##_VAL(R_IRQ_MASK1_RD_, par1_data_, v11) << R_IRQ_MASK1_RD__par1_data__BITNR) | \
+ (R_IRQ_MASK1_RD__par1_ready__##f12_##_VAL(R_IRQ_MASK1_RD_, par1_ready_, v12) << R_IRQ_MASK1_RD__par1_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser3_ready__##f13_##_VAL(R_IRQ_MASK1_RD_, ser3_ready_, v13) << R_IRQ_MASK1_RD__ser3_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser3_data__##f14_##_VAL(R_IRQ_MASK1_RD_, ser3_data_, v14) << R_IRQ_MASK1_RD__ser3_data__BITNR) | \
+ (R_IRQ_MASK1_RD__ser2_ready__##f15_##_VAL(R_IRQ_MASK1_RD_, ser2_ready_, v15) << R_IRQ_MASK1_RD__ser2_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser2_data__##f16_##_VAL(R_IRQ_MASK1_RD_, ser2_data_, v16) << R_IRQ_MASK1_RD__ser2_data__BITNR) | \
+ (R_IRQ_MASK1_RD__ser1_ready__##f17_##_VAL(R_IRQ_MASK1_RD_, ser1_ready_, v17) << R_IRQ_MASK1_RD__ser1_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser1_data__##f18_##_VAL(R_IRQ_MASK1_RD_, ser1_data_, v18) << R_IRQ_MASK1_RD__ser1_data__BITNR) | \
+ (R_IRQ_MASK1_RD__ser0_ready__##f19_##_VAL(R_IRQ_MASK1_RD_, ser0_ready_, v19) << R_IRQ_MASK1_RD__ser0_ready__BITNR) | \
+ (R_IRQ_MASK1_RD__ser0_data__##f20_##_VAL(R_IRQ_MASK1_RD_, ser0_data_, v20) << R_IRQ_MASK1_RD__ser0_data__BITNR) | \
+ (R_IRQ_MASK1_RD__pa7__##f21_##_VAL(R_IRQ_MASK1_RD_, pa7_, v21) << R_IRQ_MASK1_RD__pa7__BITNR) | \
+ (R_IRQ_MASK1_RD__pa6__##f22_##_VAL(R_IRQ_MASK1_RD_, pa6_, v22) << R_IRQ_MASK1_RD__pa6__BITNR) | \
+ (R_IRQ_MASK1_RD__pa5__##f23_##_VAL(R_IRQ_MASK1_RD_, pa5_, v23) << R_IRQ_MASK1_RD__pa5__BITNR) | \
+ (R_IRQ_MASK1_RD__pa4__##f24_##_VAL(R_IRQ_MASK1_RD_, pa4_, v24) << R_IRQ_MASK1_RD__pa4__BITNR) | \
+ (R_IRQ_MASK1_RD__pa3__##f25_##_VAL(R_IRQ_MASK1_RD_, pa3_, v25) << R_IRQ_MASK1_RD__pa3__BITNR) | \
+ (R_IRQ_MASK1_RD__pa2__##f26_##_VAL(R_IRQ_MASK1_RD_, pa2_, v26) << R_IRQ_MASK1_RD__pa2__BITNR) | \
+ (R_IRQ_MASK1_RD__pa1__##f27_##_VAL(R_IRQ_MASK1_RD_, pa1_, v27) << R_IRQ_MASK1_RD__pa1__BITNR) | \
+ (R_IRQ_MASK1_RD__pa0__##f28_##_VAL(R_IRQ_MASK1_RD_, pa0_, v28) << R_IRQ_MASK1_RD__pa0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK1_SET
+ * - type: WO
+ * - addr: 0xb00000cc
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK1_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK1_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_IRQ_MASK1_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK1_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ *R_IRQ_MASK1_SET__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK1_SET_) \
+ REG_VAL__R_IRQ_MASK1_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28) \
+ ), \
+ R_IRQ_MASK1_SET__WRITE(R_IRQ_MASK1_SET__ADDR, *R_IRQ_MASK1_SET__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK1_SET__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK1_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_IRQ_MASK1_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK1_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ *R_IRQ_MASK1_SET__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK1_SET_) \
+ REG_VAL__R_IRQ_MASK1_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25,f26##_,v26,f27##_,v27,f28##_,v28) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK1_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK1_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ (R_IRQ_MASK1_SET__sw_int7__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK1_SET__sw_int6__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK1_SET__sw_int5__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK1_SET__sw_int4__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK1_SET__sw_int3__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK1_SET__sw_int2__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK1_SET__sw_int1__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK1_SET__sw_int0__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK1_SET__par1_ecp_cmd__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK1_SET__par1_peri__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK1_SET__par1_data__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK1_SET__par1_ready__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK1_SET__ser3_ready__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK1_SET__ser3_data__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK1_SET__ser2_ready__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK1_SET__ser2_data__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK1_SET__ser1_ready__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK1_SET__ser1_data__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK1_SET__ser0_ready__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK1_SET__ser0_data__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK1_SET__pa7__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK1_SET__pa6__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK1_SET__pa5__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK1_SET__pa4__##f24##__MASK & REG__##v24) | \
+ (R_IRQ_MASK1_SET__pa3__##f25##__MASK & REG__##v25) | \
+ (R_IRQ_MASK1_SET__pa2__##f26##__MASK & REG__##v26) | \
+ (R_IRQ_MASK1_SET__pa1__##f27##__MASK & REG__##v27) | \
+ (R_IRQ_MASK1_SET__pa0__##f28##__MASK & REG__##v28) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK1_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK1_SET.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK1_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ (R_IRQ_MASK1_SET__sw_int7__##f1##__VAL(R_IRQ_MASK1_SET_, sw_int7_, v1) << R_IRQ_MASK1_SET__sw_int7__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int6__##f2##__VAL(R_IRQ_MASK1_SET_, sw_int6_, v2) << R_IRQ_MASK1_SET__sw_int6__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int5__##f3##__VAL(R_IRQ_MASK1_SET_, sw_int5_, v3) << R_IRQ_MASK1_SET__sw_int5__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int4__##f4##__VAL(R_IRQ_MASK1_SET_, sw_int4_, v4) << R_IRQ_MASK1_SET__sw_int4__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int3__##f5##__VAL(R_IRQ_MASK1_SET_, sw_int3_, v5) << R_IRQ_MASK1_SET__sw_int3__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int2__##f6##__VAL(R_IRQ_MASK1_SET_, sw_int2_, v6) << R_IRQ_MASK1_SET__sw_int2__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int1__##f7##__VAL(R_IRQ_MASK1_SET_, sw_int1_, v7) << R_IRQ_MASK1_SET__sw_int1__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int0__##f8##__VAL(R_IRQ_MASK1_SET_, sw_int0_, v8) << R_IRQ_MASK1_SET__sw_int0__BITNR) | \
+ (R_IRQ_MASK1_SET__par1_ecp_cmd__##f9##__VAL(R_IRQ_MASK1_SET_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK1_SET__par1_peri__##f10##__VAL(R_IRQ_MASK1_SET_, par1_peri_, v10) << R_IRQ_MASK1_SET__par1_peri__BITNR) | \
+ (R_IRQ_MASK1_SET__par1_data__##f11##__VAL(R_IRQ_MASK1_SET_, par1_data_, v11) << R_IRQ_MASK1_SET__par1_data__BITNR) | \
+ (R_IRQ_MASK1_SET__par1_ready__##f12##__VAL(R_IRQ_MASK1_SET_, par1_ready_, v12) << R_IRQ_MASK1_SET__par1_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser3_ready__##f13##__VAL(R_IRQ_MASK1_SET_, ser3_ready_, v13) << R_IRQ_MASK1_SET__ser3_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser3_data__##f14##__VAL(R_IRQ_MASK1_SET_, ser3_data_, v14) << R_IRQ_MASK1_SET__ser3_data__BITNR) | \
+ (R_IRQ_MASK1_SET__ser2_ready__##f15##__VAL(R_IRQ_MASK1_SET_, ser2_ready_, v15) << R_IRQ_MASK1_SET__ser2_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser2_data__##f16##__VAL(R_IRQ_MASK1_SET_, ser2_data_, v16) << R_IRQ_MASK1_SET__ser2_data__BITNR) | \
+ (R_IRQ_MASK1_SET__ser1_ready__##f17##__VAL(R_IRQ_MASK1_SET_, ser1_ready_, v17) << R_IRQ_MASK1_SET__ser1_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser1_data__##f18##__VAL(R_IRQ_MASK1_SET_, ser1_data_, v18) << R_IRQ_MASK1_SET__ser1_data__BITNR) | \
+ (R_IRQ_MASK1_SET__ser0_ready__##f19##__VAL(R_IRQ_MASK1_SET_, ser0_ready_, v19) << R_IRQ_MASK1_SET__ser0_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser0_data__##f20##__VAL(R_IRQ_MASK1_SET_, ser0_data_, v20) << R_IRQ_MASK1_SET__ser0_data__BITNR) | \
+ (R_IRQ_MASK1_SET__pa7__##f21##__VAL(R_IRQ_MASK1_SET_, pa7_, v21) << R_IRQ_MASK1_SET__pa7__BITNR) | \
+ (R_IRQ_MASK1_SET__pa6__##f22##__VAL(R_IRQ_MASK1_SET_, pa6_, v22) << R_IRQ_MASK1_SET__pa6__BITNR) | \
+ (R_IRQ_MASK1_SET__pa5__##f23##__VAL(R_IRQ_MASK1_SET_, pa5_, v23) << R_IRQ_MASK1_SET__pa5__BITNR) | \
+ (R_IRQ_MASK1_SET__pa4__##f24##__VAL(R_IRQ_MASK1_SET_, pa4_, v24) << R_IRQ_MASK1_SET__pa4__BITNR) | \
+ (R_IRQ_MASK1_SET__pa3__##f25##__VAL(R_IRQ_MASK1_SET_, pa3_, v25) << R_IRQ_MASK1_SET__pa3__BITNR) | \
+ (R_IRQ_MASK1_SET__pa2__##f26##__VAL(R_IRQ_MASK1_SET_, pa2_, v26) << R_IRQ_MASK1_SET__pa2__BITNR) | \
+ (R_IRQ_MASK1_SET__pa1__##f27##__VAL(R_IRQ_MASK1_SET_, pa1_, v27) << R_IRQ_MASK1_SET__pa1__BITNR) | \
+ (R_IRQ_MASK1_SET__pa0__##f28##__VAL(R_IRQ_MASK1_SET_, pa0_, v28) << R_IRQ_MASK1_SET__pa0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK1_SET_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK1_SET.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK1_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28) ( \
+ (R_IRQ_MASK1_SET__sw_int7__##f1_##_VAL(R_IRQ_MASK1_SET_, sw_int7_, v1) << R_IRQ_MASK1_SET__sw_int7__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int6__##f2_##_VAL(R_IRQ_MASK1_SET_, sw_int6_, v2) << R_IRQ_MASK1_SET__sw_int6__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int5__##f3_##_VAL(R_IRQ_MASK1_SET_, sw_int5_, v3) << R_IRQ_MASK1_SET__sw_int5__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int4__##f4_##_VAL(R_IRQ_MASK1_SET_, sw_int4_, v4) << R_IRQ_MASK1_SET__sw_int4__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int3__##f5_##_VAL(R_IRQ_MASK1_SET_, sw_int3_, v5) << R_IRQ_MASK1_SET__sw_int3__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int2__##f6_##_VAL(R_IRQ_MASK1_SET_, sw_int2_, v6) << R_IRQ_MASK1_SET__sw_int2__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int1__##f7_##_VAL(R_IRQ_MASK1_SET_, sw_int1_, v7) << R_IRQ_MASK1_SET__sw_int1__BITNR) | \
+ (R_IRQ_MASK1_SET__sw_int0__##f8_##_VAL(R_IRQ_MASK1_SET_, sw_int0_, v8) << R_IRQ_MASK1_SET__sw_int0__BITNR) | \
+ (R_IRQ_MASK1_SET__par1_ecp_cmd__##f9_##_VAL(R_IRQ_MASK1_SET_, par1_ecp_cmd_, v9) << R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR) | \
+ (R_IRQ_MASK1_SET__par1_peri__##f10_##_VAL(R_IRQ_MASK1_SET_, par1_peri_, v10) << R_IRQ_MASK1_SET__par1_peri__BITNR) | \
+ (R_IRQ_MASK1_SET__par1_data__##f11_##_VAL(R_IRQ_MASK1_SET_, par1_data_, v11) << R_IRQ_MASK1_SET__par1_data__BITNR) | \
+ (R_IRQ_MASK1_SET__par1_ready__##f12_##_VAL(R_IRQ_MASK1_SET_, par1_ready_, v12) << R_IRQ_MASK1_SET__par1_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser3_ready__##f13_##_VAL(R_IRQ_MASK1_SET_, ser3_ready_, v13) << R_IRQ_MASK1_SET__ser3_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser3_data__##f14_##_VAL(R_IRQ_MASK1_SET_, ser3_data_, v14) << R_IRQ_MASK1_SET__ser3_data__BITNR) | \
+ (R_IRQ_MASK1_SET__ser2_ready__##f15_##_VAL(R_IRQ_MASK1_SET_, ser2_ready_, v15) << R_IRQ_MASK1_SET__ser2_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser2_data__##f16_##_VAL(R_IRQ_MASK1_SET_, ser2_data_, v16) << R_IRQ_MASK1_SET__ser2_data__BITNR) | \
+ (R_IRQ_MASK1_SET__ser1_ready__##f17_##_VAL(R_IRQ_MASK1_SET_, ser1_ready_, v17) << R_IRQ_MASK1_SET__ser1_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser1_data__##f18_##_VAL(R_IRQ_MASK1_SET_, ser1_data_, v18) << R_IRQ_MASK1_SET__ser1_data__BITNR) | \
+ (R_IRQ_MASK1_SET__ser0_ready__##f19_##_VAL(R_IRQ_MASK1_SET_, ser0_ready_, v19) << R_IRQ_MASK1_SET__ser0_ready__BITNR) | \
+ (R_IRQ_MASK1_SET__ser0_data__##f20_##_VAL(R_IRQ_MASK1_SET_, ser0_data_, v20) << R_IRQ_MASK1_SET__ser0_data__BITNR) | \
+ (R_IRQ_MASK1_SET__pa7__##f21_##_VAL(R_IRQ_MASK1_SET_, pa7_, v21) << R_IRQ_MASK1_SET__pa7__BITNR) | \
+ (R_IRQ_MASK1_SET__pa6__##f22_##_VAL(R_IRQ_MASK1_SET_, pa6_, v22) << R_IRQ_MASK1_SET__pa6__BITNR) | \
+ (R_IRQ_MASK1_SET__pa5__##f23_##_VAL(R_IRQ_MASK1_SET_, pa5_, v23) << R_IRQ_MASK1_SET__pa5__BITNR) | \
+ (R_IRQ_MASK1_SET__pa4__##f24_##_VAL(R_IRQ_MASK1_SET_, pa4_, v24) << R_IRQ_MASK1_SET__pa4__BITNR) | \
+ (R_IRQ_MASK1_SET__pa3__##f25_##_VAL(R_IRQ_MASK1_SET_, pa3_, v25) << R_IRQ_MASK1_SET__pa3__BITNR) | \
+ (R_IRQ_MASK1_SET__pa2__##f26_##_VAL(R_IRQ_MASK1_SET_, pa2_, v26) << R_IRQ_MASK1_SET__pa2__BITNR) | \
+ (R_IRQ_MASK1_SET__pa1__##f27_##_VAL(R_IRQ_MASK1_SET_, pa1_, v27) << R_IRQ_MASK1_SET__pa1__BITNR) | \
+ (R_IRQ_MASK1_SET__pa0__##f28_##_VAL(R_IRQ_MASK1_SET_, pa0_, v28) << R_IRQ_MASK1_SET__pa0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK2_CLR
+ * - type: WO
+ * - addr: 0xb00000d0
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK2_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK2_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_IRQ_MASK2_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK2_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ *R_IRQ_MASK2_CLR__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK2_CLR_) \
+ REG_VAL__R_IRQ_MASK2_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24) \
+ ), \
+ R_IRQ_MASK2_CLR__WRITE(R_IRQ_MASK2_CLR__ADDR, *R_IRQ_MASK2_CLR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK2_CLR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK2_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_IRQ_MASK2_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK2_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ *R_IRQ_MASK2_CLR__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK2_CLR_) \
+ REG_VAL__R_IRQ_MASK2_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK2_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK2_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ (R_IRQ_MASK2_CLR__dma8_sub3_descr__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK2_CLR__dma8_sub2_descr__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK2_CLR__dma8_sub1_descr__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK2_CLR__dma8_sub0_descr__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK2_CLR__dma9_eop__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK2_CLR__dma9_descr__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK2_CLR__dma8_eop__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK2_CLR__dma8_descr__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK2_CLR__dma7_eop__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK2_CLR__dma7_descr__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK2_CLR__dma6_eop__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK2_CLR__dma6_descr__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK2_CLR__dma5_eop__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK2_CLR__dma5_descr__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK2_CLR__dma4_eop__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK2_CLR__dma4_descr__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK2_CLR__dma3_eop__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK2_CLR__dma3_descr__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK2_CLR__dma2_eop__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK2_CLR__dma2_descr__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK2_CLR__dma1_eop__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK2_CLR__dma1_descr__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK2_CLR__dma0_eop__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK2_CLR__dma0_descr__##f24##__MASK & REG__##v24) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK2_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK2_CLR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK2_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ (R_IRQ_MASK2_CLR__dma8_sub3_descr__##f1##__VAL(R_IRQ_MASK2_CLR_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_sub2_descr__##f2##__VAL(R_IRQ_MASK2_CLR_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_sub1_descr__##f3##__VAL(R_IRQ_MASK2_CLR_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_sub0_descr__##f4##__VAL(R_IRQ_MASK2_CLR_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma9_eop__##f5##__VAL(R_IRQ_MASK2_CLR_, dma9_eop_, v5) << R_IRQ_MASK2_CLR__dma9_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma9_descr__##f6##__VAL(R_IRQ_MASK2_CLR_, dma9_descr_, v6) << R_IRQ_MASK2_CLR__dma9_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_eop__##f7##__VAL(R_IRQ_MASK2_CLR_, dma8_eop_, v7) << R_IRQ_MASK2_CLR__dma8_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_descr__##f8##__VAL(R_IRQ_MASK2_CLR_, dma8_descr_, v8) << R_IRQ_MASK2_CLR__dma8_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma7_eop__##f9##__VAL(R_IRQ_MASK2_CLR_, dma7_eop_, v9) << R_IRQ_MASK2_CLR__dma7_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma7_descr__##f10##__VAL(R_IRQ_MASK2_CLR_, dma7_descr_, v10) << R_IRQ_MASK2_CLR__dma7_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma6_eop__##f11##__VAL(R_IRQ_MASK2_CLR_, dma6_eop_, v11) << R_IRQ_MASK2_CLR__dma6_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma6_descr__##f12##__VAL(R_IRQ_MASK2_CLR_, dma6_descr_, v12) << R_IRQ_MASK2_CLR__dma6_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma5_eop__##f13##__VAL(R_IRQ_MASK2_CLR_, dma5_eop_, v13) << R_IRQ_MASK2_CLR__dma5_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma5_descr__##f14##__VAL(R_IRQ_MASK2_CLR_, dma5_descr_, v14) << R_IRQ_MASK2_CLR__dma5_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma4_eop__##f15##__VAL(R_IRQ_MASK2_CLR_, dma4_eop_, v15) << R_IRQ_MASK2_CLR__dma4_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma4_descr__##f16##__VAL(R_IRQ_MASK2_CLR_, dma4_descr_, v16) << R_IRQ_MASK2_CLR__dma4_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma3_eop__##f17##__VAL(R_IRQ_MASK2_CLR_, dma3_eop_, v17) << R_IRQ_MASK2_CLR__dma3_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma3_descr__##f18##__VAL(R_IRQ_MASK2_CLR_, dma3_descr_, v18) << R_IRQ_MASK2_CLR__dma3_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma2_eop__##f19##__VAL(R_IRQ_MASK2_CLR_, dma2_eop_, v19) << R_IRQ_MASK2_CLR__dma2_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma2_descr__##f20##__VAL(R_IRQ_MASK2_CLR_, dma2_descr_, v20) << R_IRQ_MASK2_CLR__dma2_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma1_eop__##f21##__VAL(R_IRQ_MASK2_CLR_, dma1_eop_, v21) << R_IRQ_MASK2_CLR__dma1_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma1_descr__##f22##__VAL(R_IRQ_MASK2_CLR_, dma1_descr_, v22) << R_IRQ_MASK2_CLR__dma1_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma0_eop__##f23##__VAL(R_IRQ_MASK2_CLR_, dma0_eop_, v23) << R_IRQ_MASK2_CLR__dma0_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma0_descr__##f24##__VAL(R_IRQ_MASK2_CLR_, dma0_descr_, v24) << R_IRQ_MASK2_CLR__dma0_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK2_CLR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK2_CLR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK2_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24) ( \
+ (R_IRQ_MASK2_CLR__dma8_sub3_descr__##f1_##_VAL(R_IRQ_MASK2_CLR_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_sub2_descr__##f2_##_VAL(R_IRQ_MASK2_CLR_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_sub1_descr__##f3_##_VAL(R_IRQ_MASK2_CLR_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_sub0_descr__##f4_##_VAL(R_IRQ_MASK2_CLR_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma9_eop__##f5_##_VAL(R_IRQ_MASK2_CLR_, dma9_eop_, v5) << R_IRQ_MASK2_CLR__dma9_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma9_descr__##f6_##_VAL(R_IRQ_MASK2_CLR_, dma9_descr_, v6) << R_IRQ_MASK2_CLR__dma9_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_eop__##f7_##_VAL(R_IRQ_MASK2_CLR_, dma8_eop_, v7) << R_IRQ_MASK2_CLR__dma8_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma8_descr__##f8_##_VAL(R_IRQ_MASK2_CLR_, dma8_descr_, v8) << R_IRQ_MASK2_CLR__dma8_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma7_eop__##f9_##_VAL(R_IRQ_MASK2_CLR_, dma7_eop_, v9) << R_IRQ_MASK2_CLR__dma7_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma7_descr__##f10_##_VAL(R_IRQ_MASK2_CLR_, dma7_descr_, v10) << R_IRQ_MASK2_CLR__dma7_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma6_eop__##f11_##_VAL(R_IRQ_MASK2_CLR_, dma6_eop_, v11) << R_IRQ_MASK2_CLR__dma6_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma6_descr__##f12_##_VAL(R_IRQ_MASK2_CLR_, dma6_descr_, v12) << R_IRQ_MASK2_CLR__dma6_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma5_eop__##f13_##_VAL(R_IRQ_MASK2_CLR_, dma5_eop_, v13) << R_IRQ_MASK2_CLR__dma5_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma5_descr__##f14_##_VAL(R_IRQ_MASK2_CLR_, dma5_descr_, v14) << R_IRQ_MASK2_CLR__dma5_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma4_eop__##f15_##_VAL(R_IRQ_MASK2_CLR_, dma4_eop_, v15) << R_IRQ_MASK2_CLR__dma4_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma4_descr__##f16_##_VAL(R_IRQ_MASK2_CLR_, dma4_descr_, v16) << R_IRQ_MASK2_CLR__dma4_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma3_eop__##f17_##_VAL(R_IRQ_MASK2_CLR_, dma3_eop_, v17) << R_IRQ_MASK2_CLR__dma3_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma3_descr__##f18_##_VAL(R_IRQ_MASK2_CLR_, dma3_descr_, v18) << R_IRQ_MASK2_CLR__dma3_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma2_eop__##f19_##_VAL(R_IRQ_MASK2_CLR_, dma2_eop_, v19) << R_IRQ_MASK2_CLR__dma2_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma2_descr__##f20_##_VAL(R_IRQ_MASK2_CLR_, dma2_descr_, v20) << R_IRQ_MASK2_CLR__dma2_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma1_eop__##f21_##_VAL(R_IRQ_MASK2_CLR_, dma1_eop_, v21) << R_IRQ_MASK2_CLR__dma1_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma1_descr__##f22_##_VAL(R_IRQ_MASK2_CLR_, dma1_descr_, v22) << R_IRQ_MASK2_CLR__dma1_descr__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma0_eop__##f23_##_VAL(R_IRQ_MASK2_CLR_, dma0_eop_, v23) << R_IRQ_MASK2_CLR__dma0_eop__BITNR) | \
+ (R_IRQ_MASK2_CLR__dma0_descr__##f24_##_VAL(R_IRQ_MASK2_CLR_, dma0_descr_, v24) << R_IRQ_MASK2_CLR__dma0_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK2_RD
+ * - type: RO
+ * - addr: 0xb00000d0
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK2_RD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK2_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ (R_IRQ_MASK2_RD__dma8_sub3_descr__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK2_RD__dma8_sub2_descr__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK2_RD__dma8_sub1_descr__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK2_RD__dma8_sub0_descr__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK2_RD__dma9_eop__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK2_RD__dma9_descr__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK2_RD__dma8_eop__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK2_RD__dma8_descr__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK2_RD__dma7_eop__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK2_RD__dma7_descr__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK2_RD__dma6_eop__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK2_RD__dma6_descr__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK2_RD__dma5_eop__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK2_RD__dma5_descr__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK2_RD__dma4_eop__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK2_RD__dma4_descr__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK2_RD__dma3_eop__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK2_RD__dma3_descr__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK2_RD__dma2_eop__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK2_RD__dma2_descr__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK2_RD__dma1_eop__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK2_RD__dma1_descr__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK2_RD__dma0_eop__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK2_RD__dma0_descr__##f24##__MASK & REG__##v24) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK2_RD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK2_RD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK2_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ (R_IRQ_MASK2_RD__dma8_sub3_descr__##f1##__VAL(R_IRQ_MASK2_RD_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_sub2_descr__##f2##__VAL(R_IRQ_MASK2_RD_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_sub1_descr__##f3##__VAL(R_IRQ_MASK2_RD_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_sub0_descr__##f4##__VAL(R_IRQ_MASK2_RD_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma9_eop__##f5##__VAL(R_IRQ_MASK2_RD_, dma9_eop_, v5) << R_IRQ_MASK2_RD__dma9_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma9_descr__##f6##__VAL(R_IRQ_MASK2_RD_, dma9_descr_, v6) << R_IRQ_MASK2_RD__dma9_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_eop__##f7##__VAL(R_IRQ_MASK2_RD_, dma8_eop_, v7) << R_IRQ_MASK2_RD__dma8_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_descr__##f8##__VAL(R_IRQ_MASK2_RD_, dma8_descr_, v8) << R_IRQ_MASK2_RD__dma8_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma7_eop__##f9##__VAL(R_IRQ_MASK2_RD_, dma7_eop_, v9) << R_IRQ_MASK2_RD__dma7_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma7_descr__##f10##__VAL(R_IRQ_MASK2_RD_, dma7_descr_, v10) << R_IRQ_MASK2_RD__dma7_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma6_eop__##f11##__VAL(R_IRQ_MASK2_RD_, dma6_eop_, v11) << R_IRQ_MASK2_RD__dma6_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma6_descr__##f12##__VAL(R_IRQ_MASK2_RD_, dma6_descr_, v12) << R_IRQ_MASK2_RD__dma6_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma5_eop__##f13##__VAL(R_IRQ_MASK2_RD_, dma5_eop_, v13) << R_IRQ_MASK2_RD__dma5_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma5_descr__##f14##__VAL(R_IRQ_MASK2_RD_, dma5_descr_, v14) << R_IRQ_MASK2_RD__dma5_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma4_eop__##f15##__VAL(R_IRQ_MASK2_RD_, dma4_eop_, v15) << R_IRQ_MASK2_RD__dma4_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma4_descr__##f16##__VAL(R_IRQ_MASK2_RD_, dma4_descr_, v16) << R_IRQ_MASK2_RD__dma4_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma3_eop__##f17##__VAL(R_IRQ_MASK2_RD_, dma3_eop_, v17) << R_IRQ_MASK2_RD__dma3_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma3_descr__##f18##__VAL(R_IRQ_MASK2_RD_, dma3_descr_, v18) << R_IRQ_MASK2_RD__dma3_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma2_eop__##f19##__VAL(R_IRQ_MASK2_RD_, dma2_eop_, v19) << R_IRQ_MASK2_RD__dma2_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma2_descr__##f20##__VAL(R_IRQ_MASK2_RD_, dma2_descr_, v20) << R_IRQ_MASK2_RD__dma2_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma1_eop__##f21##__VAL(R_IRQ_MASK2_RD_, dma1_eop_, v21) << R_IRQ_MASK2_RD__dma1_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma1_descr__##f22##__VAL(R_IRQ_MASK2_RD_, dma1_descr_, v22) << R_IRQ_MASK2_RD__dma1_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma0_eop__##f23##__VAL(R_IRQ_MASK2_RD_, dma0_eop_, v23) << R_IRQ_MASK2_RD__dma0_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma0_descr__##f24##__VAL(R_IRQ_MASK2_RD_, dma0_descr_, v24) << R_IRQ_MASK2_RD__dma0_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK2_RD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK2_RD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK2_RD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24) ( \
+ (R_IRQ_MASK2_RD__dma8_sub3_descr__##f1_##_VAL(R_IRQ_MASK2_RD_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_sub2_descr__##f2_##_VAL(R_IRQ_MASK2_RD_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_sub1_descr__##f3_##_VAL(R_IRQ_MASK2_RD_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_sub0_descr__##f4_##_VAL(R_IRQ_MASK2_RD_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma9_eop__##f5_##_VAL(R_IRQ_MASK2_RD_, dma9_eop_, v5) << R_IRQ_MASK2_RD__dma9_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma9_descr__##f6_##_VAL(R_IRQ_MASK2_RD_, dma9_descr_, v6) << R_IRQ_MASK2_RD__dma9_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_eop__##f7_##_VAL(R_IRQ_MASK2_RD_, dma8_eop_, v7) << R_IRQ_MASK2_RD__dma8_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma8_descr__##f8_##_VAL(R_IRQ_MASK2_RD_, dma8_descr_, v8) << R_IRQ_MASK2_RD__dma8_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma7_eop__##f9_##_VAL(R_IRQ_MASK2_RD_, dma7_eop_, v9) << R_IRQ_MASK2_RD__dma7_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma7_descr__##f10_##_VAL(R_IRQ_MASK2_RD_, dma7_descr_, v10) << R_IRQ_MASK2_RD__dma7_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma6_eop__##f11_##_VAL(R_IRQ_MASK2_RD_, dma6_eop_, v11) << R_IRQ_MASK2_RD__dma6_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma6_descr__##f12_##_VAL(R_IRQ_MASK2_RD_, dma6_descr_, v12) << R_IRQ_MASK2_RD__dma6_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma5_eop__##f13_##_VAL(R_IRQ_MASK2_RD_, dma5_eop_, v13) << R_IRQ_MASK2_RD__dma5_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma5_descr__##f14_##_VAL(R_IRQ_MASK2_RD_, dma5_descr_, v14) << R_IRQ_MASK2_RD__dma5_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma4_eop__##f15_##_VAL(R_IRQ_MASK2_RD_, dma4_eop_, v15) << R_IRQ_MASK2_RD__dma4_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma4_descr__##f16_##_VAL(R_IRQ_MASK2_RD_, dma4_descr_, v16) << R_IRQ_MASK2_RD__dma4_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma3_eop__##f17_##_VAL(R_IRQ_MASK2_RD_, dma3_eop_, v17) << R_IRQ_MASK2_RD__dma3_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma3_descr__##f18_##_VAL(R_IRQ_MASK2_RD_, dma3_descr_, v18) << R_IRQ_MASK2_RD__dma3_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma2_eop__##f19_##_VAL(R_IRQ_MASK2_RD_, dma2_eop_, v19) << R_IRQ_MASK2_RD__dma2_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma2_descr__##f20_##_VAL(R_IRQ_MASK2_RD_, dma2_descr_, v20) << R_IRQ_MASK2_RD__dma2_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma1_eop__##f21_##_VAL(R_IRQ_MASK2_RD_, dma1_eop_, v21) << R_IRQ_MASK2_RD__dma1_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma1_descr__##f22_##_VAL(R_IRQ_MASK2_RD_, dma1_descr_, v22) << R_IRQ_MASK2_RD__dma1_descr__BITNR) | \
+ (R_IRQ_MASK2_RD__dma0_eop__##f23_##_VAL(R_IRQ_MASK2_RD_, dma0_eop_, v23) << R_IRQ_MASK2_RD__dma0_eop__BITNR) | \
+ (R_IRQ_MASK2_RD__dma0_descr__##f24_##_VAL(R_IRQ_MASK2_RD_, dma0_descr_, v24) << R_IRQ_MASK2_RD__dma0_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_MASK2_SET
+ * - type: WO
+ * - addr: 0xb00000d4
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK2_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK2_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_IRQ_MASK2_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK2_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ *R_IRQ_MASK2_SET__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK2_SET_) \
+ REG_VAL__R_IRQ_MASK2_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24) \
+ ), \
+ R_IRQ_MASK2_SET__WRITE(R_IRQ_MASK2_SET__ADDR, *R_IRQ_MASK2_SET__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_IRQ_MASK2_SET__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_IRQ_MASK2_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_IRQ_MASK2_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_IRQ_MASK2_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ *R_IRQ_MASK2_SET__SADDR = ( \
+ REG_INITIATED(R_IRQ_MASK2_SET_) \
+ REG_VAL__R_IRQ_MASK2_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_MASK2_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_MASK2_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ (R_IRQ_MASK2_SET__dma8_sub3_descr__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_MASK2_SET__dma8_sub2_descr__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_MASK2_SET__dma8_sub1_descr__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_MASK2_SET__dma8_sub0_descr__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_MASK2_SET__dma9_eop__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_MASK2_SET__dma9_descr__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_MASK2_SET__dma8_eop__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_MASK2_SET__dma8_descr__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_MASK2_SET__dma7_eop__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_MASK2_SET__dma7_descr__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_MASK2_SET__dma6_eop__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_MASK2_SET__dma6_descr__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_MASK2_SET__dma5_eop__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_MASK2_SET__dma5_descr__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_MASK2_SET__dma4_eop__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_MASK2_SET__dma4_descr__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_MASK2_SET__dma3_eop__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_MASK2_SET__dma3_descr__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_MASK2_SET__dma2_eop__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_MASK2_SET__dma2_descr__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_MASK2_SET__dma1_eop__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_MASK2_SET__dma1_descr__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_MASK2_SET__dma0_eop__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_MASK2_SET__dma0_descr__##f24##__MASK & REG__##v24) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK2_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK2_SET.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK2_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ (R_IRQ_MASK2_SET__dma8_sub3_descr__##f1##__VAL(R_IRQ_MASK2_SET_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_sub2_descr__##f2##__VAL(R_IRQ_MASK2_SET_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_sub1_descr__##f3##__VAL(R_IRQ_MASK2_SET_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_sub0_descr__##f4##__VAL(R_IRQ_MASK2_SET_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma9_eop__##f5##__VAL(R_IRQ_MASK2_SET_, dma9_eop_, v5) << R_IRQ_MASK2_SET__dma9_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma9_descr__##f6##__VAL(R_IRQ_MASK2_SET_, dma9_descr_, v6) << R_IRQ_MASK2_SET__dma9_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_eop__##f7##__VAL(R_IRQ_MASK2_SET_, dma8_eop_, v7) << R_IRQ_MASK2_SET__dma8_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_descr__##f8##__VAL(R_IRQ_MASK2_SET_, dma8_descr_, v8) << R_IRQ_MASK2_SET__dma8_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma7_eop__##f9##__VAL(R_IRQ_MASK2_SET_, dma7_eop_, v9) << R_IRQ_MASK2_SET__dma7_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma7_descr__##f10##__VAL(R_IRQ_MASK2_SET_, dma7_descr_, v10) << R_IRQ_MASK2_SET__dma7_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma6_eop__##f11##__VAL(R_IRQ_MASK2_SET_, dma6_eop_, v11) << R_IRQ_MASK2_SET__dma6_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma6_descr__##f12##__VAL(R_IRQ_MASK2_SET_, dma6_descr_, v12) << R_IRQ_MASK2_SET__dma6_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma5_eop__##f13##__VAL(R_IRQ_MASK2_SET_, dma5_eop_, v13) << R_IRQ_MASK2_SET__dma5_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma5_descr__##f14##__VAL(R_IRQ_MASK2_SET_, dma5_descr_, v14) << R_IRQ_MASK2_SET__dma5_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma4_eop__##f15##__VAL(R_IRQ_MASK2_SET_, dma4_eop_, v15) << R_IRQ_MASK2_SET__dma4_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma4_descr__##f16##__VAL(R_IRQ_MASK2_SET_, dma4_descr_, v16) << R_IRQ_MASK2_SET__dma4_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma3_eop__##f17##__VAL(R_IRQ_MASK2_SET_, dma3_eop_, v17) << R_IRQ_MASK2_SET__dma3_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma3_descr__##f18##__VAL(R_IRQ_MASK2_SET_, dma3_descr_, v18) << R_IRQ_MASK2_SET__dma3_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma2_eop__##f19##__VAL(R_IRQ_MASK2_SET_, dma2_eop_, v19) << R_IRQ_MASK2_SET__dma2_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma2_descr__##f20##__VAL(R_IRQ_MASK2_SET_, dma2_descr_, v20) << R_IRQ_MASK2_SET__dma2_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma1_eop__##f21##__VAL(R_IRQ_MASK2_SET_, dma1_eop_, v21) << R_IRQ_MASK2_SET__dma1_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma1_descr__##f22##__VAL(R_IRQ_MASK2_SET_, dma1_descr_, v22) << R_IRQ_MASK2_SET__dma1_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma0_eop__##f23##__VAL(R_IRQ_MASK2_SET_, dma0_eop_, v23) << R_IRQ_MASK2_SET__dma0_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma0_descr__##f24##__VAL(R_IRQ_MASK2_SET_, dma0_descr_, v24) << R_IRQ_MASK2_SET__dma0_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_MASK2_SET_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_MASK2_SET.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_MASK2_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24) ( \
+ (R_IRQ_MASK2_SET__dma8_sub3_descr__##f1_##_VAL(R_IRQ_MASK2_SET_, dma8_sub3_descr_, v1) << R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_sub2_descr__##f2_##_VAL(R_IRQ_MASK2_SET_, dma8_sub2_descr_, v2) << R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_sub1_descr__##f3_##_VAL(R_IRQ_MASK2_SET_, dma8_sub1_descr_, v3) << R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_sub0_descr__##f4_##_VAL(R_IRQ_MASK2_SET_, dma8_sub0_descr_, v4) << R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma9_eop__##f5_##_VAL(R_IRQ_MASK2_SET_, dma9_eop_, v5) << R_IRQ_MASK2_SET__dma9_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma9_descr__##f6_##_VAL(R_IRQ_MASK2_SET_, dma9_descr_, v6) << R_IRQ_MASK2_SET__dma9_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_eop__##f7_##_VAL(R_IRQ_MASK2_SET_, dma8_eop_, v7) << R_IRQ_MASK2_SET__dma8_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma8_descr__##f8_##_VAL(R_IRQ_MASK2_SET_, dma8_descr_, v8) << R_IRQ_MASK2_SET__dma8_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma7_eop__##f9_##_VAL(R_IRQ_MASK2_SET_, dma7_eop_, v9) << R_IRQ_MASK2_SET__dma7_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma7_descr__##f10_##_VAL(R_IRQ_MASK2_SET_, dma7_descr_, v10) << R_IRQ_MASK2_SET__dma7_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma6_eop__##f11_##_VAL(R_IRQ_MASK2_SET_, dma6_eop_, v11) << R_IRQ_MASK2_SET__dma6_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma6_descr__##f12_##_VAL(R_IRQ_MASK2_SET_, dma6_descr_, v12) << R_IRQ_MASK2_SET__dma6_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma5_eop__##f13_##_VAL(R_IRQ_MASK2_SET_, dma5_eop_, v13) << R_IRQ_MASK2_SET__dma5_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma5_descr__##f14_##_VAL(R_IRQ_MASK2_SET_, dma5_descr_, v14) << R_IRQ_MASK2_SET__dma5_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma4_eop__##f15_##_VAL(R_IRQ_MASK2_SET_, dma4_eop_, v15) << R_IRQ_MASK2_SET__dma4_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma4_descr__##f16_##_VAL(R_IRQ_MASK2_SET_, dma4_descr_, v16) << R_IRQ_MASK2_SET__dma4_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma3_eop__##f17_##_VAL(R_IRQ_MASK2_SET_, dma3_eop_, v17) << R_IRQ_MASK2_SET__dma3_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma3_descr__##f18_##_VAL(R_IRQ_MASK2_SET_, dma3_descr_, v18) << R_IRQ_MASK2_SET__dma3_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma2_eop__##f19_##_VAL(R_IRQ_MASK2_SET_, dma2_eop_, v19) << R_IRQ_MASK2_SET__dma2_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma2_descr__##f20_##_VAL(R_IRQ_MASK2_SET_, dma2_descr_, v20) << R_IRQ_MASK2_SET__dma2_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma1_eop__##f21_##_VAL(R_IRQ_MASK2_SET_, dma1_eop_, v21) << R_IRQ_MASK2_SET__dma1_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma1_descr__##f22_##_VAL(R_IRQ_MASK2_SET_, dma1_descr_, v22) << R_IRQ_MASK2_SET__dma1_descr__BITNR) | \
+ (R_IRQ_MASK2_SET__dma0_eop__##f23_##_VAL(R_IRQ_MASK2_SET_, dma0_eop_, v23) << R_IRQ_MASK2_SET__dma0_eop__BITNR) | \
+ (R_IRQ_MASK2_SET__dma0_descr__##f24_##_VAL(R_IRQ_MASK2_SET_, dma0_descr_, v24) << R_IRQ_MASK2_SET__dma0_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_READ0
+ * - type: RO
+ * - addr: 0xb00000c4
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_READ0
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_READ0(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ (R_IRQ_READ0__nmi_pin__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_READ0__watchdog_nmi__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_READ0__sqe_test_error__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_READ0__carrier_loss__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_READ0__deferred__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_READ0__late_col__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_READ0__multiple_col__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_READ0__single_col__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_READ0__congestion__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_READ0__oversize__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_READ0__alignment_error__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_READ0__crc_error__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_READ0__overrun__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_READ0__underrun__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_READ0__excessive_col__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_READ0__mdio__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_READ0__ata_drq3__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_READ0__ata_drq2__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_READ0__ata_drq1__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_READ0__ata_drq0__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_READ0__par0_ecp_cmd__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_READ0__par0_peri__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_READ0__par0_data__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_READ0__par0_ready__##f24##__MASK & REG__##v24) | \
+ (R_IRQ_READ0__ata_dmaend__##f25##__MASK & REG__##v25) | \
+ (R_IRQ_READ0__irq_ext_vector_nr__##f26##__MASK & REG__##v26) | \
+ (R_IRQ_READ0__irq_int_vector_nr__##f27##__MASK & REG__##v27) | \
+ (R_IRQ_READ0__ext_dma1__##f28##__MASK & REG__##v28) | \
+ (R_IRQ_READ0__ext_dma0__##f29##__MASK & REG__##v29) | \
+ (R_IRQ_READ0__timer1__##f30##__MASK & REG__##v30) | \
+ (R_IRQ_READ0__timer0__##f31##__MASK & REG__##v31) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_READ0
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_READ0.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_READ0(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28,f29,v29,f30,v30,f31,v31) ( \
+ (R_IRQ_READ0__nmi_pin__##f1##__VAL(R_IRQ_READ0_, nmi_pin_, v1) << R_IRQ_READ0__nmi_pin__BITNR) | \
+ (R_IRQ_READ0__watchdog_nmi__##f2##__VAL(R_IRQ_READ0_, watchdog_nmi_, v2) << R_IRQ_READ0__watchdog_nmi__BITNR) | \
+ (R_IRQ_READ0__sqe_test_error__##f3##__VAL(R_IRQ_READ0_, sqe_test_error_, v3) << R_IRQ_READ0__sqe_test_error__BITNR) | \
+ (R_IRQ_READ0__carrier_loss__##f4##__VAL(R_IRQ_READ0_, carrier_loss_, v4) << R_IRQ_READ0__carrier_loss__BITNR) | \
+ (R_IRQ_READ0__deferred__##f5##__VAL(R_IRQ_READ0_, deferred_, v5) << R_IRQ_READ0__deferred__BITNR) | \
+ (R_IRQ_READ0__late_col__##f6##__VAL(R_IRQ_READ0_, late_col_, v6) << R_IRQ_READ0__late_col__BITNR) | \
+ (R_IRQ_READ0__multiple_col__##f7##__VAL(R_IRQ_READ0_, multiple_col_, v7) << R_IRQ_READ0__multiple_col__BITNR) | \
+ (R_IRQ_READ0__single_col__##f8##__VAL(R_IRQ_READ0_, single_col_, v8) << R_IRQ_READ0__single_col__BITNR) | \
+ (R_IRQ_READ0__congestion__##f9##__VAL(R_IRQ_READ0_, congestion_, v9) << R_IRQ_READ0__congestion__BITNR) | \
+ (R_IRQ_READ0__oversize__##f10##__VAL(R_IRQ_READ0_, oversize_, v10) << R_IRQ_READ0__oversize__BITNR) | \
+ (R_IRQ_READ0__alignment_error__##f11##__VAL(R_IRQ_READ0_, alignment_error_, v11) << R_IRQ_READ0__alignment_error__BITNR) | \
+ (R_IRQ_READ0__crc_error__##f12##__VAL(R_IRQ_READ0_, crc_error_, v12) << R_IRQ_READ0__crc_error__BITNR) | \
+ (R_IRQ_READ0__overrun__##f13##__VAL(R_IRQ_READ0_, overrun_, v13) << R_IRQ_READ0__overrun__BITNR) | \
+ (R_IRQ_READ0__underrun__##f14##__VAL(R_IRQ_READ0_, underrun_, v14) << R_IRQ_READ0__underrun__BITNR) | \
+ (R_IRQ_READ0__excessive_col__##f15##__VAL(R_IRQ_READ0_, excessive_col_, v15) << R_IRQ_READ0__excessive_col__BITNR) | \
+ (R_IRQ_READ0__mdio__##f16##__VAL(R_IRQ_READ0_, mdio_, v16) << R_IRQ_READ0__mdio__BITNR) | \
+ (R_IRQ_READ0__ata_drq3__##f17##__VAL(R_IRQ_READ0_, ata_drq3_, v17) << R_IRQ_READ0__ata_drq3__BITNR) | \
+ (R_IRQ_READ0__ata_drq2__##f18##__VAL(R_IRQ_READ0_, ata_drq2_, v18) << R_IRQ_READ0__ata_drq2__BITNR) | \
+ (R_IRQ_READ0__ata_drq1__##f19##__VAL(R_IRQ_READ0_, ata_drq1_, v19) << R_IRQ_READ0__ata_drq1__BITNR) | \
+ (R_IRQ_READ0__ata_drq0__##f20##__VAL(R_IRQ_READ0_, ata_drq0_, v20) << R_IRQ_READ0__ata_drq0__BITNR) | \
+ (R_IRQ_READ0__par0_ecp_cmd__##f21##__VAL(R_IRQ_READ0_, par0_ecp_cmd_, v21) << R_IRQ_READ0__par0_ecp_cmd__BITNR) | \
+ (R_IRQ_READ0__par0_peri__##f22##__VAL(R_IRQ_READ0_, par0_peri_, v22) << R_IRQ_READ0__par0_peri__BITNR) | \
+ (R_IRQ_READ0__par0_data__##f23##__VAL(R_IRQ_READ0_, par0_data_, v23) << R_IRQ_READ0__par0_data__BITNR) | \
+ (R_IRQ_READ0__par0_ready__##f24##__VAL(R_IRQ_READ0_, par0_ready_, v24) << R_IRQ_READ0__par0_ready__BITNR) | \
+ (R_IRQ_READ0__ata_dmaend__##f25##__VAL(R_IRQ_READ0_, ata_dmaend_, v25) << R_IRQ_READ0__ata_dmaend__BITNR) | \
+ (R_IRQ_READ0__irq_ext_vector_nr__##f26##__VAL(R_IRQ_READ0_, irq_ext_vector_nr_, v26) << R_IRQ_READ0__irq_ext_vector_nr__BITNR) | \
+ (R_IRQ_READ0__irq_int_vector_nr__##f27##__VAL(R_IRQ_READ0_, irq_int_vector_nr_, v27) << R_IRQ_READ0__irq_int_vector_nr__BITNR) | \
+ (R_IRQ_READ0__ext_dma1__##f28##__VAL(R_IRQ_READ0_, ext_dma1_, v28) << R_IRQ_READ0__ext_dma1__BITNR) | \
+ (R_IRQ_READ0__ext_dma0__##f29##__VAL(R_IRQ_READ0_, ext_dma0_, v29) << R_IRQ_READ0__ext_dma0__BITNR) | \
+ (R_IRQ_READ0__timer1__##f30##__VAL(R_IRQ_READ0_, timer1_, v30) << R_IRQ_READ0__timer1__BITNR) | \
+ (R_IRQ_READ0__timer0__##f31##__VAL(R_IRQ_READ0_, timer0_, v31) << R_IRQ_READ0__timer0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_READ0_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_READ0.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_READ0_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28,f29_,v29,f30_,v30,f31_,v31) ( \
+ (R_IRQ_READ0__nmi_pin__##f1_##_VAL(R_IRQ_READ0_, nmi_pin_, v1) << R_IRQ_READ0__nmi_pin__BITNR) | \
+ (R_IRQ_READ0__watchdog_nmi__##f2_##_VAL(R_IRQ_READ0_, watchdog_nmi_, v2) << R_IRQ_READ0__watchdog_nmi__BITNR) | \
+ (R_IRQ_READ0__sqe_test_error__##f3_##_VAL(R_IRQ_READ0_, sqe_test_error_, v3) << R_IRQ_READ0__sqe_test_error__BITNR) | \
+ (R_IRQ_READ0__carrier_loss__##f4_##_VAL(R_IRQ_READ0_, carrier_loss_, v4) << R_IRQ_READ0__carrier_loss__BITNR) | \
+ (R_IRQ_READ0__deferred__##f5_##_VAL(R_IRQ_READ0_, deferred_, v5) << R_IRQ_READ0__deferred__BITNR) | \
+ (R_IRQ_READ0__late_col__##f6_##_VAL(R_IRQ_READ0_, late_col_, v6) << R_IRQ_READ0__late_col__BITNR) | \
+ (R_IRQ_READ0__multiple_col__##f7_##_VAL(R_IRQ_READ0_, multiple_col_, v7) << R_IRQ_READ0__multiple_col__BITNR) | \
+ (R_IRQ_READ0__single_col__##f8_##_VAL(R_IRQ_READ0_, single_col_, v8) << R_IRQ_READ0__single_col__BITNR) | \
+ (R_IRQ_READ0__congestion__##f9_##_VAL(R_IRQ_READ0_, congestion_, v9) << R_IRQ_READ0__congestion__BITNR) | \
+ (R_IRQ_READ0__oversize__##f10_##_VAL(R_IRQ_READ0_, oversize_, v10) << R_IRQ_READ0__oversize__BITNR) | \
+ (R_IRQ_READ0__alignment_error__##f11_##_VAL(R_IRQ_READ0_, alignment_error_, v11) << R_IRQ_READ0__alignment_error__BITNR) | \
+ (R_IRQ_READ0__crc_error__##f12_##_VAL(R_IRQ_READ0_, crc_error_, v12) << R_IRQ_READ0__crc_error__BITNR) | \
+ (R_IRQ_READ0__overrun__##f13_##_VAL(R_IRQ_READ0_, overrun_, v13) << R_IRQ_READ0__overrun__BITNR) | \
+ (R_IRQ_READ0__underrun__##f14_##_VAL(R_IRQ_READ0_, underrun_, v14) << R_IRQ_READ0__underrun__BITNR) | \
+ (R_IRQ_READ0__excessive_col__##f15_##_VAL(R_IRQ_READ0_, excessive_col_, v15) << R_IRQ_READ0__excessive_col__BITNR) | \
+ (R_IRQ_READ0__mdio__##f16_##_VAL(R_IRQ_READ0_, mdio_, v16) << R_IRQ_READ0__mdio__BITNR) | \
+ (R_IRQ_READ0__ata_drq3__##f17_##_VAL(R_IRQ_READ0_, ata_drq3_, v17) << R_IRQ_READ0__ata_drq3__BITNR) | \
+ (R_IRQ_READ0__ata_drq2__##f18_##_VAL(R_IRQ_READ0_, ata_drq2_, v18) << R_IRQ_READ0__ata_drq2__BITNR) | \
+ (R_IRQ_READ0__ata_drq1__##f19_##_VAL(R_IRQ_READ0_, ata_drq1_, v19) << R_IRQ_READ0__ata_drq1__BITNR) | \
+ (R_IRQ_READ0__ata_drq0__##f20_##_VAL(R_IRQ_READ0_, ata_drq0_, v20) << R_IRQ_READ0__ata_drq0__BITNR) | \
+ (R_IRQ_READ0__par0_ecp_cmd__##f21_##_VAL(R_IRQ_READ0_, par0_ecp_cmd_, v21) << R_IRQ_READ0__par0_ecp_cmd__BITNR) | \
+ (R_IRQ_READ0__par0_peri__##f22_##_VAL(R_IRQ_READ0_, par0_peri_, v22) << R_IRQ_READ0__par0_peri__BITNR) | \
+ (R_IRQ_READ0__par0_data__##f23_##_VAL(R_IRQ_READ0_, par0_data_, v23) << R_IRQ_READ0__par0_data__BITNR) | \
+ (R_IRQ_READ0__par0_ready__##f24_##_VAL(R_IRQ_READ0_, par0_ready_, v24) << R_IRQ_READ0__par0_ready__BITNR) | \
+ (R_IRQ_READ0__ata_dmaend__##f25_##_VAL(R_IRQ_READ0_, ata_dmaend_, v25) << R_IRQ_READ0__ata_dmaend__BITNR) | \
+ (R_IRQ_READ0__irq_ext_vector_nr__##f26_##_VAL(R_IRQ_READ0_, irq_ext_vector_nr_, v26) << R_IRQ_READ0__irq_ext_vector_nr__BITNR) | \
+ (R_IRQ_READ0__irq_int_vector_nr__##f27_##_VAL(R_IRQ_READ0_, irq_int_vector_nr_, v27) << R_IRQ_READ0__irq_int_vector_nr__BITNR) | \
+ (R_IRQ_READ0__ext_dma1__##f28_##_VAL(R_IRQ_READ0_, ext_dma1_, v28) << R_IRQ_READ0__ext_dma1__BITNR) | \
+ (R_IRQ_READ0__ext_dma0__##f29_##_VAL(R_IRQ_READ0_, ext_dma0_, v29) << R_IRQ_READ0__ext_dma0__BITNR) | \
+ (R_IRQ_READ0__timer1__##f30_##_VAL(R_IRQ_READ0_, timer1_, v30) << R_IRQ_READ0__timer1__BITNR) | \
+ (R_IRQ_READ0__timer0__##f31_##_VAL(R_IRQ_READ0_, timer0_, v31) << R_IRQ_READ0__timer0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_READ1
+ * - type: RO
+ * - addr: 0xb00000cc
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_READ1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_READ1(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ (R_IRQ_READ1__sw_int7__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_READ1__sw_int6__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_READ1__sw_int5__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_READ1__sw_int4__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_READ1__sw_int3__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_READ1__sw_int2__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_READ1__sw_int1__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_READ1__sw_int0__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_READ1__par1_ecp_cmd__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_READ1__par1_peri__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_READ1__par1_data__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_READ1__par1_ready__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_READ1__ser3_ready__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_READ1__ser3_data__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_READ1__ser2_ready__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_READ1__ser2_data__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_READ1__ser1_ready__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_READ1__ser1_data__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_READ1__ser0_ready__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_READ1__ser0_data__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_READ1__pa7__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_READ1__pa6__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_READ1__pa5__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_READ1__pa4__##f24##__MASK & REG__##v24) | \
+ (R_IRQ_READ1__pa3__##f25##__MASK & REG__##v25) | \
+ (R_IRQ_READ1__pa2__##f26##__MASK & REG__##v26) | \
+ (R_IRQ_READ1__pa1__##f27##__MASK & REG__##v27) | \
+ (R_IRQ_READ1__pa0__##f28##__MASK & REG__##v28) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_READ1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_READ1.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_READ1(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25,f26,v26,f27,v27,f28,v28) ( \
+ (R_IRQ_READ1__sw_int7__##f1##__VAL(R_IRQ_READ1_, sw_int7_, v1) << R_IRQ_READ1__sw_int7__BITNR) | \
+ (R_IRQ_READ1__sw_int6__##f2##__VAL(R_IRQ_READ1_, sw_int6_, v2) << R_IRQ_READ1__sw_int6__BITNR) | \
+ (R_IRQ_READ1__sw_int5__##f3##__VAL(R_IRQ_READ1_, sw_int5_, v3) << R_IRQ_READ1__sw_int5__BITNR) | \
+ (R_IRQ_READ1__sw_int4__##f4##__VAL(R_IRQ_READ1_, sw_int4_, v4) << R_IRQ_READ1__sw_int4__BITNR) | \
+ (R_IRQ_READ1__sw_int3__##f5##__VAL(R_IRQ_READ1_, sw_int3_, v5) << R_IRQ_READ1__sw_int3__BITNR) | \
+ (R_IRQ_READ1__sw_int2__##f6##__VAL(R_IRQ_READ1_, sw_int2_, v6) << R_IRQ_READ1__sw_int2__BITNR) | \
+ (R_IRQ_READ1__sw_int1__##f7##__VAL(R_IRQ_READ1_, sw_int1_, v7) << R_IRQ_READ1__sw_int1__BITNR) | \
+ (R_IRQ_READ1__sw_int0__##f8##__VAL(R_IRQ_READ1_, sw_int0_, v8) << R_IRQ_READ1__sw_int0__BITNR) | \
+ (R_IRQ_READ1__par1_ecp_cmd__##f9##__VAL(R_IRQ_READ1_, par1_ecp_cmd_, v9) << R_IRQ_READ1__par1_ecp_cmd__BITNR) | \
+ (R_IRQ_READ1__par1_peri__##f10##__VAL(R_IRQ_READ1_, par1_peri_, v10) << R_IRQ_READ1__par1_peri__BITNR) | \
+ (R_IRQ_READ1__par1_data__##f11##__VAL(R_IRQ_READ1_, par1_data_, v11) << R_IRQ_READ1__par1_data__BITNR) | \
+ (R_IRQ_READ1__par1_ready__##f12##__VAL(R_IRQ_READ1_, par1_ready_, v12) << R_IRQ_READ1__par1_ready__BITNR) | \
+ (R_IRQ_READ1__ser3_ready__##f13##__VAL(R_IRQ_READ1_, ser3_ready_, v13) << R_IRQ_READ1__ser3_ready__BITNR) | \
+ (R_IRQ_READ1__ser3_data__##f14##__VAL(R_IRQ_READ1_, ser3_data_, v14) << R_IRQ_READ1__ser3_data__BITNR) | \
+ (R_IRQ_READ1__ser2_ready__##f15##__VAL(R_IRQ_READ1_, ser2_ready_, v15) << R_IRQ_READ1__ser2_ready__BITNR) | \
+ (R_IRQ_READ1__ser2_data__##f16##__VAL(R_IRQ_READ1_, ser2_data_, v16) << R_IRQ_READ1__ser2_data__BITNR) | \
+ (R_IRQ_READ1__ser1_ready__##f17##__VAL(R_IRQ_READ1_, ser1_ready_, v17) << R_IRQ_READ1__ser1_ready__BITNR) | \
+ (R_IRQ_READ1__ser1_data__##f18##__VAL(R_IRQ_READ1_, ser1_data_, v18) << R_IRQ_READ1__ser1_data__BITNR) | \
+ (R_IRQ_READ1__ser0_ready__##f19##__VAL(R_IRQ_READ1_, ser0_ready_, v19) << R_IRQ_READ1__ser0_ready__BITNR) | \
+ (R_IRQ_READ1__ser0_data__##f20##__VAL(R_IRQ_READ1_, ser0_data_, v20) << R_IRQ_READ1__ser0_data__BITNR) | \
+ (R_IRQ_READ1__pa7__##f21##__VAL(R_IRQ_READ1_, pa7_, v21) << R_IRQ_READ1__pa7__BITNR) | \
+ (R_IRQ_READ1__pa6__##f22##__VAL(R_IRQ_READ1_, pa6_, v22) << R_IRQ_READ1__pa6__BITNR) | \
+ (R_IRQ_READ1__pa5__##f23##__VAL(R_IRQ_READ1_, pa5_, v23) << R_IRQ_READ1__pa5__BITNR) | \
+ (R_IRQ_READ1__pa4__##f24##__VAL(R_IRQ_READ1_, pa4_, v24) << R_IRQ_READ1__pa4__BITNR) | \
+ (R_IRQ_READ1__pa3__##f25##__VAL(R_IRQ_READ1_, pa3_, v25) << R_IRQ_READ1__pa3__BITNR) | \
+ (R_IRQ_READ1__pa2__##f26##__VAL(R_IRQ_READ1_, pa2_, v26) << R_IRQ_READ1__pa2__BITNR) | \
+ (R_IRQ_READ1__pa1__##f27##__VAL(R_IRQ_READ1_, pa1_, v27) << R_IRQ_READ1__pa1__BITNR) | \
+ (R_IRQ_READ1__pa0__##f28##__VAL(R_IRQ_READ1_, pa0_, v28) << R_IRQ_READ1__pa0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_READ1_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_READ1.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_READ1_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25,f26_,v26,f27_,v27,f28_,v28) ( \
+ (R_IRQ_READ1__sw_int7__##f1_##_VAL(R_IRQ_READ1_, sw_int7_, v1) << R_IRQ_READ1__sw_int7__BITNR) | \
+ (R_IRQ_READ1__sw_int6__##f2_##_VAL(R_IRQ_READ1_, sw_int6_, v2) << R_IRQ_READ1__sw_int6__BITNR) | \
+ (R_IRQ_READ1__sw_int5__##f3_##_VAL(R_IRQ_READ1_, sw_int5_, v3) << R_IRQ_READ1__sw_int5__BITNR) | \
+ (R_IRQ_READ1__sw_int4__##f4_##_VAL(R_IRQ_READ1_, sw_int4_, v4) << R_IRQ_READ1__sw_int4__BITNR) | \
+ (R_IRQ_READ1__sw_int3__##f5_##_VAL(R_IRQ_READ1_, sw_int3_, v5) << R_IRQ_READ1__sw_int3__BITNR) | \
+ (R_IRQ_READ1__sw_int2__##f6_##_VAL(R_IRQ_READ1_, sw_int2_, v6) << R_IRQ_READ1__sw_int2__BITNR) | \
+ (R_IRQ_READ1__sw_int1__##f7_##_VAL(R_IRQ_READ1_, sw_int1_, v7) << R_IRQ_READ1__sw_int1__BITNR) | \
+ (R_IRQ_READ1__sw_int0__##f8_##_VAL(R_IRQ_READ1_, sw_int0_, v8) << R_IRQ_READ1__sw_int0__BITNR) | \
+ (R_IRQ_READ1__par1_ecp_cmd__##f9_##_VAL(R_IRQ_READ1_, par1_ecp_cmd_, v9) << R_IRQ_READ1__par1_ecp_cmd__BITNR) | \
+ (R_IRQ_READ1__par1_peri__##f10_##_VAL(R_IRQ_READ1_, par1_peri_, v10) << R_IRQ_READ1__par1_peri__BITNR) | \
+ (R_IRQ_READ1__par1_data__##f11_##_VAL(R_IRQ_READ1_, par1_data_, v11) << R_IRQ_READ1__par1_data__BITNR) | \
+ (R_IRQ_READ1__par1_ready__##f12_##_VAL(R_IRQ_READ1_, par1_ready_, v12) << R_IRQ_READ1__par1_ready__BITNR) | \
+ (R_IRQ_READ1__ser3_ready__##f13_##_VAL(R_IRQ_READ1_, ser3_ready_, v13) << R_IRQ_READ1__ser3_ready__BITNR) | \
+ (R_IRQ_READ1__ser3_data__##f14_##_VAL(R_IRQ_READ1_, ser3_data_, v14) << R_IRQ_READ1__ser3_data__BITNR) | \
+ (R_IRQ_READ1__ser2_ready__##f15_##_VAL(R_IRQ_READ1_, ser2_ready_, v15) << R_IRQ_READ1__ser2_ready__BITNR) | \
+ (R_IRQ_READ1__ser2_data__##f16_##_VAL(R_IRQ_READ1_, ser2_data_, v16) << R_IRQ_READ1__ser2_data__BITNR) | \
+ (R_IRQ_READ1__ser1_ready__##f17_##_VAL(R_IRQ_READ1_, ser1_ready_, v17) << R_IRQ_READ1__ser1_ready__BITNR) | \
+ (R_IRQ_READ1__ser1_data__##f18_##_VAL(R_IRQ_READ1_, ser1_data_, v18) << R_IRQ_READ1__ser1_data__BITNR) | \
+ (R_IRQ_READ1__ser0_ready__##f19_##_VAL(R_IRQ_READ1_, ser0_ready_, v19) << R_IRQ_READ1__ser0_ready__BITNR) | \
+ (R_IRQ_READ1__ser0_data__##f20_##_VAL(R_IRQ_READ1_, ser0_data_, v20) << R_IRQ_READ1__ser0_data__BITNR) | \
+ (R_IRQ_READ1__pa7__##f21_##_VAL(R_IRQ_READ1_, pa7_, v21) << R_IRQ_READ1__pa7__BITNR) | \
+ (R_IRQ_READ1__pa6__##f22_##_VAL(R_IRQ_READ1_, pa6_, v22) << R_IRQ_READ1__pa6__BITNR) | \
+ (R_IRQ_READ1__pa5__##f23_##_VAL(R_IRQ_READ1_, pa5_, v23) << R_IRQ_READ1__pa5__BITNR) | \
+ (R_IRQ_READ1__pa4__##f24_##_VAL(R_IRQ_READ1_, pa4_, v24) << R_IRQ_READ1__pa4__BITNR) | \
+ (R_IRQ_READ1__pa3__##f25_##_VAL(R_IRQ_READ1_, pa3_, v25) << R_IRQ_READ1__pa3__BITNR) | \
+ (R_IRQ_READ1__pa2__##f26_##_VAL(R_IRQ_READ1_, pa2_, v26) << R_IRQ_READ1__pa2__BITNR) | \
+ (R_IRQ_READ1__pa1__##f27_##_VAL(R_IRQ_READ1_, pa1_, v27) << R_IRQ_READ1__pa1__BITNR) | \
+ (R_IRQ_READ1__pa0__##f28_##_VAL(R_IRQ_READ1_, pa0_, v28) << R_IRQ_READ1__pa0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_IRQ_READ2
+ * - type: RO
+ * - addr: 0xb00000d4
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_IRQ_READ2
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_IRQ_READ2(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ (R_IRQ_READ2__dma8_sub3_descr__##f1##__MASK & REG__##v1) | \
+ (R_IRQ_READ2__dma8_sub2_descr__##f2##__MASK & REG__##v2) | \
+ (R_IRQ_READ2__dma8_sub1_descr__##f3##__MASK & REG__##v3) | \
+ (R_IRQ_READ2__dma8_sub0_descr__##f4##__MASK & REG__##v4) | \
+ (R_IRQ_READ2__dma9_eop__##f5##__MASK & REG__##v5) | \
+ (R_IRQ_READ2__dma9_descr__##f6##__MASK & REG__##v6) | \
+ (R_IRQ_READ2__dma8_eop__##f7##__MASK & REG__##v7) | \
+ (R_IRQ_READ2__dma8_descr__##f8##__MASK & REG__##v8) | \
+ (R_IRQ_READ2__dma7_eop__##f9##__MASK & REG__##v9) | \
+ (R_IRQ_READ2__dma7_descr__##f10##__MASK & REG__##v10) | \
+ (R_IRQ_READ2__dma6_eop__##f11##__MASK & REG__##v11) | \
+ (R_IRQ_READ2__dma6_descr__##f12##__MASK & REG__##v12) | \
+ (R_IRQ_READ2__dma5_eop__##f13##__MASK & REG__##v13) | \
+ (R_IRQ_READ2__dma5_descr__##f14##__MASK & REG__##v14) | \
+ (R_IRQ_READ2__dma4_eop__##f15##__MASK & REG__##v15) | \
+ (R_IRQ_READ2__dma4_descr__##f16##__MASK & REG__##v16) | \
+ (R_IRQ_READ2__dma3_eop__##f17##__MASK & REG__##v17) | \
+ (R_IRQ_READ2__dma3_descr__##f18##__MASK & REG__##v18) | \
+ (R_IRQ_READ2__dma2_eop__##f19##__MASK & REG__##v19) | \
+ (R_IRQ_READ2__dma2_descr__##f20##__MASK & REG__##v20) | \
+ (R_IRQ_READ2__dma1_eop__##f21##__MASK & REG__##v21) | \
+ (R_IRQ_READ2__dma1_descr__##f22##__MASK & REG__##v22) | \
+ (R_IRQ_READ2__dma0_eop__##f23##__MASK & REG__##v23) | \
+ (R_IRQ_READ2__dma0_descr__##f24##__MASK & REG__##v24) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_READ2
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_READ2.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_READ2(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24) ( \
+ (R_IRQ_READ2__dma8_sub3_descr__##f1##__VAL(R_IRQ_READ2_, dma8_sub3_descr_, v1) << R_IRQ_READ2__dma8_sub3_descr__BITNR) | \
+ (R_IRQ_READ2__dma8_sub2_descr__##f2##__VAL(R_IRQ_READ2_, dma8_sub2_descr_, v2) << R_IRQ_READ2__dma8_sub2_descr__BITNR) | \
+ (R_IRQ_READ2__dma8_sub1_descr__##f3##__VAL(R_IRQ_READ2_, dma8_sub1_descr_, v3) << R_IRQ_READ2__dma8_sub1_descr__BITNR) | \
+ (R_IRQ_READ2__dma8_sub0_descr__##f4##__VAL(R_IRQ_READ2_, dma8_sub0_descr_, v4) << R_IRQ_READ2__dma8_sub0_descr__BITNR) | \
+ (R_IRQ_READ2__dma9_eop__##f5##__VAL(R_IRQ_READ2_, dma9_eop_, v5) << R_IRQ_READ2__dma9_eop__BITNR) | \
+ (R_IRQ_READ2__dma9_descr__##f6##__VAL(R_IRQ_READ2_, dma9_descr_, v6) << R_IRQ_READ2__dma9_descr__BITNR) | \
+ (R_IRQ_READ2__dma8_eop__##f7##__VAL(R_IRQ_READ2_, dma8_eop_, v7) << R_IRQ_READ2__dma8_eop__BITNR) | \
+ (R_IRQ_READ2__dma8_descr__##f8##__VAL(R_IRQ_READ2_, dma8_descr_, v8) << R_IRQ_READ2__dma8_descr__BITNR) | \
+ (R_IRQ_READ2__dma7_eop__##f9##__VAL(R_IRQ_READ2_, dma7_eop_, v9) << R_IRQ_READ2__dma7_eop__BITNR) | \
+ (R_IRQ_READ2__dma7_descr__##f10##__VAL(R_IRQ_READ2_, dma7_descr_, v10) << R_IRQ_READ2__dma7_descr__BITNR) | \
+ (R_IRQ_READ2__dma6_eop__##f11##__VAL(R_IRQ_READ2_, dma6_eop_, v11) << R_IRQ_READ2__dma6_eop__BITNR) | \
+ (R_IRQ_READ2__dma6_descr__##f12##__VAL(R_IRQ_READ2_, dma6_descr_, v12) << R_IRQ_READ2__dma6_descr__BITNR) | \
+ (R_IRQ_READ2__dma5_eop__##f13##__VAL(R_IRQ_READ2_, dma5_eop_, v13) << R_IRQ_READ2__dma5_eop__BITNR) | \
+ (R_IRQ_READ2__dma5_descr__##f14##__VAL(R_IRQ_READ2_, dma5_descr_, v14) << R_IRQ_READ2__dma5_descr__BITNR) | \
+ (R_IRQ_READ2__dma4_eop__##f15##__VAL(R_IRQ_READ2_, dma4_eop_, v15) << R_IRQ_READ2__dma4_eop__BITNR) | \
+ (R_IRQ_READ2__dma4_descr__##f16##__VAL(R_IRQ_READ2_, dma4_descr_, v16) << R_IRQ_READ2__dma4_descr__BITNR) | \
+ (R_IRQ_READ2__dma3_eop__##f17##__VAL(R_IRQ_READ2_, dma3_eop_, v17) << R_IRQ_READ2__dma3_eop__BITNR) | \
+ (R_IRQ_READ2__dma3_descr__##f18##__VAL(R_IRQ_READ2_, dma3_descr_, v18) << R_IRQ_READ2__dma3_descr__BITNR) | \
+ (R_IRQ_READ2__dma2_eop__##f19##__VAL(R_IRQ_READ2_, dma2_eop_, v19) << R_IRQ_READ2__dma2_eop__BITNR) | \
+ (R_IRQ_READ2__dma2_descr__##f20##__VAL(R_IRQ_READ2_, dma2_descr_, v20) << R_IRQ_READ2__dma2_descr__BITNR) | \
+ (R_IRQ_READ2__dma1_eop__##f21##__VAL(R_IRQ_READ2_, dma1_eop_, v21) << R_IRQ_READ2__dma1_eop__BITNR) | \
+ (R_IRQ_READ2__dma1_descr__##f22##__VAL(R_IRQ_READ2_, dma1_descr_, v22) << R_IRQ_READ2__dma1_descr__BITNR) | \
+ (R_IRQ_READ2__dma0_eop__##f23##__VAL(R_IRQ_READ2_, dma0_eop_, v23) << R_IRQ_READ2__dma0_eop__BITNR) | \
+ (R_IRQ_READ2__dma0_descr__##f24##__VAL(R_IRQ_READ2_, dma0_descr_, v24) << R_IRQ_READ2__dma0_descr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_IRQ_READ2_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_IRQ_READ2.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_IRQ_READ2_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24) ( \
+ (R_IRQ_READ2__dma8_sub3_descr__##f1_##_VAL(R_IRQ_READ2_, dma8_sub3_descr_, v1) << R_IRQ_READ2__dma8_sub3_descr__BITNR) | \
+ (R_IRQ_READ2__dma8_sub2_descr__##f2_##_VAL(R_IRQ_READ2_, dma8_sub2_descr_, v2) << R_IRQ_READ2__dma8_sub2_descr__BITNR) | \
+ (R_IRQ_READ2__dma8_sub1_descr__##f3_##_VAL(R_IRQ_READ2_, dma8_sub1_descr_, v3) << R_IRQ_READ2__dma8_sub1_descr__BITNR) | \
+ (R_IRQ_READ2__dma8_sub0_descr__##f4_##_VAL(R_IRQ_READ2_, dma8_sub0_descr_, v4) << R_IRQ_READ2__dma8_sub0_descr__BITNR) | \
+ (R_IRQ_READ2__dma9_eop__##f5_##_VAL(R_IRQ_READ2_, dma9_eop_, v5) << R_IRQ_READ2__dma9_eop__BITNR) | \
+ (R_IRQ_READ2__dma9_descr__##f6_##_VAL(R_IRQ_READ2_, dma9_descr_, v6) << R_IRQ_READ2__dma9_descr__BITNR) | \
+ (R_IRQ_READ2__dma8_eop__##f7_##_VAL(R_IRQ_READ2_, dma8_eop_, v7) << R_IRQ_READ2__dma8_eop__BITNR) | \
+ (R_IRQ_READ2__dma8_descr__##f8_##_VAL(R_IRQ_READ2_, dma8_descr_, v8) << R_IRQ_READ2__dma8_descr__BITNR) | \
+ (R_IRQ_READ2__dma7_eop__##f9_##_VAL(R_IRQ_READ2_, dma7_eop_, v9) << R_IRQ_READ2__dma7_eop__BITNR) | \
+ (R_IRQ_READ2__dma7_descr__##f10_##_VAL(R_IRQ_READ2_, dma7_descr_, v10) << R_IRQ_READ2__dma7_descr__BITNR) | \
+ (R_IRQ_READ2__dma6_eop__##f11_##_VAL(R_IRQ_READ2_, dma6_eop_, v11) << R_IRQ_READ2__dma6_eop__BITNR) | \
+ (R_IRQ_READ2__dma6_descr__##f12_##_VAL(R_IRQ_READ2_, dma6_descr_, v12) << R_IRQ_READ2__dma6_descr__BITNR) | \
+ (R_IRQ_READ2__dma5_eop__##f13_##_VAL(R_IRQ_READ2_, dma5_eop_, v13) << R_IRQ_READ2__dma5_eop__BITNR) | \
+ (R_IRQ_READ2__dma5_descr__##f14_##_VAL(R_IRQ_READ2_, dma5_descr_, v14) << R_IRQ_READ2__dma5_descr__BITNR) | \
+ (R_IRQ_READ2__dma4_eop__##f15_##_VAL(R_IRQ_READ2_, dma4_eop_, v15) << R_IRQ_READ2__dma4_eop__BITNR) | \
+ (R_IRQ_READ2__dma4_descr__##f16_##_VAL(R_IRQ_READ2_, dma4_descr_, v16) << R_IRQ_READ2__dma4_descr__BITNR) | \
+ (R_IRQ_READ2__dma3_eop__##f17_##_VAL(R_IRQ_READ2_, dma3_eop_, v17) << R_IRQ_READ2__dma3_eop__BITNR) | \
+ (R_IRQ_READ2__dma3_descr__##f18_##_VAL(R_IRQ_READ2_, dma3_descr_, v18) << R_IRQ_READ2__dma3_descr__BITNR) | \
+ (R_IRQ_READ2__dma2_eop__##f19_##_VAL(R_IRQ_READ2_, dma2_eop_, v19) << R_IRQ_READ2__dma2_eop__BITNR) | \
+ (R_IRQ_READ2__dma2_descr__##f20_##_VAL(R_IRQ_READ2_, dma2_descr_, v20) << R_IRQ_READ2__dma2_descr__BITNR) | \
+ (R_IRQ_READ2__dma1_eop__##f21_##_VAL(R_IRQ_READ2_, dma1_eop_, v21) << R_IRQ_READ2__dma1_eop__BITNR) | \
+ (R_IRQ_READ2__dma1_descr__##f22_##_VAL(R_IRQ_READ2_, dma1_descr_, v22) << R_IRQ_READ2__dma1_descr__BITNR) | \
+ (R_IRQ_READ2__dma0_eop__##f23_##_VAL(R_IRQ_READ2_, dma0_eop_, v23) << R_IRQ_READ2__dma0_eop__BITNR) | \
+ (R_IRQ_READ2__dma0_descr__##f24_##_VAL(R_IRQ_READ2_, dma0_descr_, v24) << R_IRQ_READ2__dma0_descr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_MMU_CAUSE
+ * - type: RO
+ * - addr: 0xb0000250
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_MMU_CAUSE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_MMU_CAUSE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ (R_MMU_CAUSE__vpn__##f1##__MASK & REG__##v1) | \
+ (R_MMU_CAUSE__miss_excp__##f2##__MASK & REG__##v2) | \
+ (R_MMU_CAUSE__inv_excp__##f3##__MASK & REG__##v3) | \
+ (R_MMU_CAUSE__acc_excp__##f4##__MASK & REG__##v4) | \
+ (R_MMU_CAUSE__we_excp__##f5##__MASK & REG__##v5) | \
+ (R_MMU_CAUSE__wr_rd__##f6##__MASK & REG__##v6) | \
+ (R_MMU_CAUSE__page_id__##f7##__MASK & REG__##v7) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_CAUSE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_CAUSE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_CAUSE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ (R_MMU_CAUSE__vpn__##f1##__VAL(R_MMU_CAUSE_, vpn_, v1) << R_MMU_CAUSE__vpn__BITNR) | \
+ (R_MMU_CAUSE__miss_excp__##f2##__VAL(R_MMU_CAUSE_, miss_excp_, v2) << R_MMU_CAUSE__miss_excp__BITNR) | \
+ (R_MMU_CAUSE__inv_excp__##f3##__VAL(R_MMU_CAUSE_, inv_excp_, v3) << R_MMU_CAUSE__inv_excp__BITNR) | \
+ (R_MMU_CAUSE__acc_excp__##f4##__VAL(R_MMU_CAUSE_, acc_excp_, v4) << R_MMU_CAUSE__acc_excp__BITNR) | \
+ (R_MMU_CAUSE__we_excp__##f5##__VAL(R_MMU_CAUSE_, we_excp_, v5) << R_MMU_CAUSE__we_excp__BITNR) | \
+ (R_MMU_CAUSE__wr_rd__##f6##__VAL(R_MMU_CAUSE_, wr_rd_, v6) << R_MMU_CAUSE__wr_rd__BITNR) | \
+ (R_MMU_CAUSE__page_id__##f7##__VAL(R_MMU_CAUSE_, page_id_, v7) << R_MMU_CAUSE__page_id__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_CAUSE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_CAUSE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_CAUSE_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7) ( \
+ (R_MMU_CAUSE__vpn__##f1_##_VAL(R_MMU_CAUSE_, vpn_, v1) << R_MMU_CAUSE__vpn__BITNR) | \
+ (R_MMU_CAUSE__miss_excp__##f2_##_VAL(R_MMU_CAUSE_, miss_excp_, v2) << R_MMU_CAUSE__miss_excp__BITNR) | \
+ (R_MMU_CAUSE__inv_excp__##f3_##_VAL(R_MMU_CAUSE_, inv_excp_, v3) << R_MMU_CAUSE__inv_excp__BITNR) | \
+ (R_MMU_CAUSE__acc_excp__##f4_##_VAL(R_MMU_CAUSE_, acc_excp_, v4) << R_MMU_CAUSE__acc_excp__BITNR) | \
+ (R_MMU_CAUSE__we_excp__##f5_##_VAL(R_MMU_CAUSE_, we_excp_, v5) << R_MMU_CAUSE__we_excp__BITNR) | \
+ (R_MMU_CAUSE__wr_rd__##f6_##_VAL(R_MMU_CAUSE_, wr_rd_, v6) << R_MMU_CAUSE__wr_rd__BITNR) | \
+ (R_MMU_CAUSE__page_id__##f7_##_VAL(R_MMU_CAUSE_, page_id_, v7) << R_MMU_CAUSE__page_id__BITNR) \
+)
+
+#endif
+
+/*
+ * R_MMU_CONFIG
+ * - type: WO
+ * - addr: 0xb0000240
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_MMU_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \
+ *R_MMU_CONFIG__SADDR = ( \
+ REG_INITIATED(R_MMU_CONFIG_) \
+ REG_VAL__R_MMU_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20) \
+ ), \
+ R_MMU_CONFIG__WRITE(R_MMU_CONFIG__ADDR, *R_MMU_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_MMU_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \
+ *R_MMU_CONFIG__SADDR = ( \
+ REG_INITIATED(R_MMU_CONFIG_) \
+ REG_VAL__R_MMU_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_MMU_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_MMU_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \
+ (R_MMU_CONFIG__mmu_enable__##f1##__MASK & REG__##v1) | \
+ (R_MMU_CONFIG__inv_excp__##f2##__MASK & REG__##v2) | \
+ (R_MMU_CONFIG__acc_excp__##f3##__MASK & REG__##v3) | \
+ (R_MMU_CONFIG__we_excp__##f4##__MASK & REG__##v4) | \
+ (R_MMU_CONFIG__seg_f__##f5##__MASK & REG__##v5) | \
+ (R_MMU_CONFIG__seg_e__##f6##__MASK & REG__##v6) | \
+ (R_MMU_CONFIG__seg_d__##f7##__MASK & REG__##v7) | \
+ (R_MMU_CONFIG__seg_c__##f8##__MASK & REG__##v8) | \
+ (R_MMU_CONFIG__seg_b__##f9##__MASK & REG__##v9) | \
+ (R_MMU_CONFIG__seg_a__##f10##__MASK & REG__##v10) | \
+ (R_MMU_CONFIG__seg_9__##f11##__MASK & REG__##v11) | \
+ (R_MMU_CONFIG__seg_8__##f12##__MASK & REG__##v12) | \
+ (R_MMU_CONFIG__seg_7__##f13##__MASK & REG__##v13) | \
+ (R_MMU_CONFIG__seg_6__##f14##__MASK & REG__##v14) | \
+ (R_MMU_CONFIG__seg_5__##f15##__MASK & REG__##v15) | \
+ (R_MMU_CONFIG__seg_4__##f16##__MASK & REG__##v16) | \
+ (R_MMU_CONFIG__seg_3__##f17##__MASK & REG__##v17) | \
+ (R_MMU_CONFIG__seg_2__##f18##__MASK & REG__##v18) | \
+ (R_MMU_CONFIG__seg_1__##f19##__MASK & REG__##v19) | \
+ (R_MMU_CONFIG__seg_0__##f20##__MASK & REG__##v20) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \
+ (R_MMU_CONFIG__mmu_enable__##f1##__VAL(R_MMU_CONFIG_, mmu_enable_, v1) << R_MMU_CONFIG__mmu_enable__BITNR) | \
+ (R_MMU_CONFIG__inv_excp__##f2##__VAL(R_MMU_CONFIG_, inv_excp_, v2) << R_MMU_CONFIG__inv_excp__BITNR) | \
+ (R_MMU_CONFIG__acc_excp__##f3##__VAL(R_MMU_CONFIG_, acc_excp_, v3) << R_MMU_CONFIG__acc_excp__BITNR) | \
+ (R_MMU_CONFIG__we_excp__##f4##__VAL(R_MMU_CONFIG_, we_excp_, v4) << R_MMU_CONFIG__we_excp__BITNR) | \
+ (R_MMU_CONFIG__seg_f__##f5##__VAL(R_MMU_CONFIG_, seg_f_, v5) << R_MMU_CONFIG__seg_f__BITNR) | \
+ (R_MMU_CONFIG__seg_e__##f6##__VAL(R_MMU_CONFIG_, seg_e_, v6) << R_MMU_CONFIG__seg_e__BITNR) | \
+ (R_MMU_CONFIG__seg_d__##f7##__VAL(R_MMU_CONFIG_, seg_d_, v7) << R_MMU_CONFIG__seg_d__BITNR) | \
+ (R_MMU_CONFIG__seg_c__##f8##__VAL(R_MMU_CONFIG_, seg_c_, v8) << R_MMU_CONFIG__seg_c__BITNR) | \
+ (R_MMU_CONFIG__seg_b__##f9##__VAL(R_MMU_CONFIG_, seg_b_, v9) << R_MMU_CONFIG__seg_b__BITNR) | \
+ (R_MMU_CONFIG__seg_a__##f10##__VAL(R_MMU_CONFIG_, seg_a_, v10) << R_MMU_CONFIG__seg_a__BITNR) | \
+ (R_MMU_CONFIG__seg_9__##f11##__VAL(R_MMU_CONFIG_, seg_9_, v11) << R_MMU_CONFIG__seg_9__BITNR) | \
+ (R_MMU_CONFIG__seg_8__##f12##__VAL(R_MMU_CONFIG_, seg_8_, v12) << R_MMU_CONFIG__seg_8__BITNR) | \
+ (R_MMU_CONFIG__seg_7__##f13##__VAL(R_MMU_CONFIG_, seg_7_, v13) << R_MMU_CONFIG__seg_7__BITNR) | \
+ (R_MMU_CONFIG__seg_6__##f14##__VAL(R_MMU_CONFIG_, seg_6_, v14) << R_MMU_CONFIG__seg_6__BITNR) | \
+ (R_MMU_CONFIG__seg_5__##f15##__VAL(R_MMU_CONFIG_, seg_5_, v15) << R_MMU_CONFIG__seg_5__BITNR) | \
+ (R_MMU_CONFIG__seg_4__##f16##__VAL(R_MMU_CONFIG_, seg_4_, v16) << R_MMU_CONFIG__seg_4__BITNR) | \
+ (R_MMU_CONFIG__seg_3__##f17##__VAL(R_MMU_CONFIG_, seg_3_, v17) << R_MMU_CONFIG__seg_3__BITNR) | \
+ (R_MMU_CONFIG__seg_2__##f18##__VAL(R_MMU_CONFIG_, seg_2_, v18) << R_MMU_CONFIG__seg_2__BITNR) | \
+ (R_MMU_CONFIG__seg_1__##f19##__VAL(R_MMU_CONFIG_, seg_1_, v19) << R_MMU_CONFIG__seg_1__BITNR) | \
+ (R_MMU_CONFIG__seg_0__##f20##__VAL(R_MMU_CONFIG_, seg_0_, v20) << R_MMU_CONFIG__seg_0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20) ( \
+ (R_MMU_CONFIG__mmu_enable__##f1_##_VAL(R_MMU_CONFIG_, mmu_enable_, v1) << R_MMU_CONFIG__mmu_enable__BITNR) | \
+ (R_MMU_CONFIG__inv_excp__##f2_##_VAL(R_MMU_CONFIG_, inv_excp_, v2) << R_MMU_CONFIG__inv_excp__BITNR) | \
+ (R_MMU_CONFIG__acc_excp__##f3_##_VAL(R_MMU_CONFIG_, acc_excp_, v3) << R_MMU_CONFIG__acc_excp__BITNR) | \
+ (R_MMU_CONFIG__we_excp__##f4_##_VAL(R_MMU_CONFIG_, we_excp_, v4) << R_MMU_CONFIG__we_excp__BITNR) | \
+ (R_MMU_CONFIG__seg_f__##f5_##_VAL(R_MMU_CONFIG_, seg_f_, v5) << R_MMU_CONFIG__seg_f__BITNR) | \
+ (R_MMU_CONFIG__seg_e__##f6_##_VAL(R_MMU_CONFIG_, seg_e_, v6) << R_MMU_CONFIG__seg_e__BITNR) | \
+ (R_MMU_CONFIG__seg_d__##f7_##_VAL(R_MMU_CONFIG_, seg_d_, v7) << R_MMU_CONFIG__seg_d__BITNR) | \
+ (R_MMU_CONFIG__seg_c__##f8_##_VAL(R_MMU_CONFIG_, seg_c_, v8) << R_MMU_CONFIG__seg_c__BITNR) | \
+ (R_MMU_CONFIG__seg_b__##f9_##_VAL(R_MMU_CONFIG_, seg_b_, v9) << R_MMU_CONFIG__seg_b__BITNR) | \
+ (R_MMU_CONFIG__seg_a__##f10_##_VAL(R_MMU_CONFIG_, seg_a_, v10) << R_MMU_CONFIG__seg_a__BITNR) | \
+ (R_MMU_CONFIG__seg_9__##f11_##_VAL(R_MMU_CONFIG_, seg_9_, v11) << R_MMU_CONFIG__seg_9__BITNR) | \
+ (R_MMU_CONFIG__seg_8__##f12_##_VAL(R_MMU_CONFIG_, seg_8_, v12) << R_MMU_CONFIG__seg_8__BITNR) | \
+ (R_MMU_CONFIG__seg_7__##f13_##_VAL(R_MMU_CONFIG_, seg_7_, v13) << R_MMU_CONFIG__seg_7__BITNR) | \
+ (R_MMU_CONFIG__seg_6__##f14_##_VAL(R_MMU_CONFIG_, seg_6_, v14) << R_MMU_CONFIG__seg_6__BITNR) | \
+ (R_MMU_CONFIG__seg_5__##f15_##_VAL(R_MMU_CONFIG_, seg_5_, v15) << R_MMU_CONFIG__seg_5__BITNR) | \
+ (R_MMU_CONFIG__seg_4__##f16_##_VAL(R_MMU_CONFIG_, seg_4_, v16) << R_MMU_CONFIG__seg_4__BITNR) | \
+ (R_MMU_CONFIG__seg_3__##f17_##_VAL(R_MMU_CONFIG_, seg_3_, v17) << R_MMU_CONFIG__seg_3__BITNR) | \
+ (R_MMU_CONFIG__seg_2__##f18_##_VAL(R_MMU_CONFIG_, seg_2_, v18) << R_MMU_CONFIG__seg_2__BITNR) | \
+ (R_MMU_CONFIG__seg_1__##f19_##_VAL(R_MMU_CONFIG_, seg_1_, v19) << R_MMU_CONFIG__seg_1__BITNR) | \
+ (R_MMU_CONFIG__seg_0__##f20_##_VAL(R_MMU_CONFIG_, seg_0_, v20) << R_MMU_CONFIG__seg_0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_MMU_CONTEXT
+ * - type: RW
+ * - addr: 0xb000024c
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_CONTEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_CONTEXT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_MMU_CONTEXT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_CONTEXT(f1,v1) ( \
+ R_MMU_CONTEXT__WRITE(R_MMU_CONTEXT__ADDR, ( \
+ REG_VAL__R_MMU_CONTEXT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_MMU_CONTEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_MMU_CONTEXT(f1,v1) ( \
+ (R_MMU_CONTEXT__page_id__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_CONTEXT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_CONTEXT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_CONTEXT(f1,v1) ( \
+ (R_MMU_CONTEXT__page_id__##f1##__VAL(R_MMU_CONTEXT_, page_id_, v1) << R_MMU_CONTEXT__page_id__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_CONTEXT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_CONTEXT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_CONTEXT_(f1_,v1) ( \
+ (R_MMU_CONTEXT__page_id__##f1_##_VAL(R_MMU_CONTEXT_, page_id_, v1) << R_MMU_CONTEXT__page_id__BITNR) \
+)
+
+#endif
+
+/*
+ * R_MMU_CTRL
+ * - type: WO
+ * - addr: 0xb0000242
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_MMU_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ *R_MMU_CTRL__SADDR = ( \
+ REG_INITIATED(R_MMU_CTRL_) \
+ REG_VAL__R_MMU_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ), \
+ R_MMU_CTRL__WRITE(R_MMU_CTRL__ADDR, *R_MMU_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_MMU_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_CTRL__SHADOW(f1,v1,f2,v2,f3,v3) ( \
+ *R_MMU_CTRL__SADDR = ( \
+ REG_INITIATED(R_MMU_CTRL_) \
+ REG_VAL__R_MMU_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_MMU_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_MMU_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ (R_MMU_CTRL__inv_excp__##f1##__MASK & REG__##v1) | \
+ (R_MMU_CTRL__acc_excp__##f2##__MASK & REG__##v2) | \
+ (R_MMU_CTRL__we_excp__##f3##__MASK & REG__##v3) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ (R_MMU_CTRL__inv_excp__##f1##__VAL(R_MMU_CTRL_, inv_excp_, v1) << R_MMU_CTRL__inv_excp__BITNR) | \
+ (R_MMU_CTRL__acc_excp__##f2##__VAL(R_MMU_CTRL_, acc_excp_, v2) << R_MMU_CTRL__acc_excp__BITNR) | \
+ (R_MMU_CTRL__we_excp__##f3##__VAL(R_MMU_CTRL_, we_excp_, v3) << R_MMU_CTRL__we_excp__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_CTRL_(f1_,v1,f2_,v2,f3_,v3) ( \
+ (R_MMU_CTRL__inv_excp__##f1_##_VAL(R_MMU_CTRL_, inv_excp_, v1) << R_MMU_CTRL__inv_excp__BITNR) | \
+ (R_MMU_CTRL__acc_excp__##f2_##_VAL(R_MMU_CTRL_, acc_excp_, v2) << R_MMU_CTRL__acc_excp__BITNR) | \
+ (R_MMU_CTRL__we_excp__##f3_##_VAL(R_MMU_CTRL_, we_excp_, v3) << R_MMU_CTRL__we_excp__BITNR) \
+)
+
+#endif
+
+/*
+ * R_MMU_ENABLE
+ * - type: WO
+ * - addr: 0xb0000243
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_ENABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_ENABLE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_MMU_ENABLE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_ENABLE(f1,v1) ( \
+ *R_MMU_ENABLE__SADDR = ( \
+ REG_INITIATED(R_MMU_ENABLE_) \
+ REG_VAL__R_MMU_ENABLE_(f1##_,v1) \
+ ), \
+ R_MMU_ENABLE__WRITE(R_MMU_ENABLE__ADDR, *R_MMU_ENABLE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_ENABLE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_ENABLE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_MMU_ENABLE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_ENABLE__SHADOW(f1,v1) ( \
+ *R_MMU_ENABLE__SADDR = ( \
+ REG_INITIATED(R_MMU_ENABLE_) \
+ REG_VAL__R_MMU_ENABLE_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_MMU_ENABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_MMU_ENABLE(f1,v1) ( \
+ (R_MMU_ENABLE__mmu_enable__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_ENABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_ENABLE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_ENABLE(f1,v1) ( \
+ (R_MMU_ENABLE__mmu_enable__##f1##__VAL(R_MMU_ENABLE_, mmu_enable_, v1) << R_MMU_ENABLE__mmu_enable__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_ENABLE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_ENABLE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_ENABLE_(f1_,v1) ( \
+ (R_MMU_ENABLE__mmu_enable__##f1_##_VAL(R_MMU_ENABLE_, mmu_enable_, v1) << R_MMU_ENABLE__mmu_enable__BITNR) \
+)
+
+#endif
+
+/*
+ * R_MMU_KBASE_HI
+ * - type: WO
+ * - addr: 0xb0000248
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_KBASE_HI
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_KBASE_HI.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_MMU_KBASE_HI.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_KBASE_HI(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_MMU_KBASE_HI__SADDR = ( \
+ REG_INITIATED(R_MMU_KBASE_HI_) \
+ REG_VAL__R_MMU_KBASE_HI_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_MMU_KBASE_HI__WRITE(R_MMU_KBASE_HI__ADDR, *R_MMU_KBASE_HI__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_KBASE_HI__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_KBASE_HI.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_MMU_KBASE_HI.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_KBASE_HI__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_MMU_KBASE_HI__SADDR = ( \
+ REG_INITIATED(R_MMU_KBASE_HI_) \
+ REG_VAL__R_MMU_KBASE_HI_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_MMU_KBASE_HI
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_MMU_KBASE_HI(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_MMU_KBASE_HI__base_f__##f1##__MASK & REG__##v1) | \
+ (R_MMU_KBASE_HI__base_e__##f2##__MASK & REG__##v2) | \
+ (R_MMU_KBASE_HI__base_d__##f3##__MASK & REG__##v3) | \
+ (R_MMU_KBASE_HI__base_c__##f4##__MASK & REG__##v4) | \
+ (R_MMU_KBASE_HI__base_b__##f5##__MASK & REG__##v5) | \
+ (R_MMU_KBASE_HI__base_a__##f6##__MASK & REG__##v6) | \
+ (R_MMU_KBASE_HI__base_9__##f7##__MASK & REG__##v7) | \
+ (R_MMU_KBASE_HI__base_8__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_KBASE_HI
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_KBASE_HI.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_KBASE_HI(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_MMU_KBASE_HI__base_f__##f1##__VAL(R_MMU_KBASE_HI_, base_f_, v1) << R_MMU_KBASE_HI__base_f__BITNR) | \
+ (R_MMU_KBASE_HI__base_e__##f2##__VAL(R_MMU_KBASE_HI_, base_e_, v2) << R_MMU_KBASE_HI__base_e__BITNR) | \
+ (R_MMU_KBASE_HI__base_d__##f3##__VAL(R_MMU_KBASE_HI_, base_d_, v3) << R_MMU_KBASE_HI__base_d__BITNR) | \
+ (R_MMU_KBASE_HI__base_c__##f4##__VAL(R_MMU_KBASE_HI_, base_c_, v4) << R_MMU_KBASE_HI__base_c__BITNR) | \
+ (R_MMU_KBASE_HI__base_b__##f5##__VAL(R_MMU_KBASE_HI_, base_b_, v5) << R_MMU_KBASE_HI__base_b__BITNR) | \
+ (R_MMU_KBASE_HI__base_a__##f6##__VAL(R_MMU_KBASE_HI_, base_a_, v6) << R_MMU_KBASE_HI__base_a__BITNR) | \
+ (R_MMU_KBASE_HI__base_9__##f7##__VAL(R_MMU_KBASE_HI_, base_9_, v7) << R_MMU_KBASE_HI__base_9__BITNR) | \
+ (R_MMU_KBASE_HI__base_8__##f8##__VAL(R_MMU_KBASE_HI_, base_8_, v8) << R_MMU_KBASE_HI__base_8__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_KBASE_HI_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_KBASE_HI.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_KBASE_HI_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_MMU_KBASE_HI__base_f__##f1_##_VAL(R_MMU_KBASE_HI_, base_f_, v1) << R_MMU_KBASE_HI__base_f__BITNR) | \
+ (R_MMU_KBASE_HI__base_e__##f2_##_VAL(R_MMU_KBASE_HI_, base_e_, v2) << R_MMU_KBASE_HI__base_e__BITNR) | \
+ (R_MMU_KBASE_HI__base_d__##f3_##_VAL(R_MMU_KBASE_HI_, base_d_, v3) << R_MMU_KBASE_HI__base_d__BITNR) | \
+ (R_MMU_KBASE_HI__base_c__##f4_##_VAL(R_MMU_KBASE_HI_, base_c_, v4) << R_MMU_KBASE_HI__base_c__BITNR) | \
+ (R_MMU_KBASE_HI__base_b__##f5_##_VAL(R_MMU_KBASE_HI_, base_b_, v5) << R_MMU_KBASE_HI__base_b__BITNR) | \
+ (R_MMU_KBASE_HI__base_a__##f6_##_VAL(R_MMU_KBASE_HI_, base_a_, v6) << R_MMU_KBASE_HI__base_a__BITNR) | \
+ (R_MMU_KBASE_HI__base_9__##f7_##_VAL(R_MMU_KBASE_HI_, base_9_, v7) << R_MMU_KBASE_HI__base_9__BITNR) | \
+ (R_MMU_KBASE_HI__base_8__##f8_##_VAL(R_MMU_KBASE_HI_, base_8_, v8) << R_MMU_KBASE_HI__base_8__BITNR) \
+)
+
+#endif
+
+/*
+ * R_MMU_KBASE_LO
+ * - type: WO
+ * - addr: 0xb0000244
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_KBASE_LO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_KBASE_LO.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_MMU_KBASE_LO.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_KBASE_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_MMU_KBASE_LO__SADDR = ( \
+ REG_INITIATED(R_MMU_KBASE_LO_) \
+ REG_VAL__R_MMU_KBASE_LO_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_MMU_KBASE_LO__WRITE(R_MMU_KBASE_LO__ADDR, *R_MMU_KBASE_LO__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_KBASE_LO__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_KBASE_LO.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_MMU_KBASE_LO.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_KBASE_LO__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_MMU_KBASE_LO__SADDR = ( \
+ REG_INITIATED(R_MMU_KBASE_LO_) \
+ REG_VAL__R_MMU_KBASE_LO_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_MMU_KBASE_LO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_MMU_KBASE_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_MMU_KBASE_LO__base_7__##f1##__MASK & REG__##v1) | \
+ (R_MMU_KBASE_LO__base_6__##f2##__MASK & REG__##v2) | \
+ (R_MMU_KBASE_LO__base_5__##f3##__MASK & REG__##v3) | \
+ (R_MMU_KBASE_LO__base_4__##f4##__MASK & REG__##v4) | \
+ (R_MMU_KBASE_LO__base_3__##f5##__MASK & REG__##v5) | \
+ (R_MMU_KBASE_LO__base_2__##f6##__MASK & REG__##v6) | \
+ (R_MMU_KBASE_LO__base_1__##f7##__MASK & REG__##v7) | \
+ (R_MMU_KBASE_LO__base_0__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_KBASE_LO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_KBASE_LO.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_KBASE_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_MMU_KBASE_LO__base_7__##f1##__VAL(R_MMU_KBASE_LO_, base_7_, v1) << R_MMU_KBASE_LO__base_7__BITNR) | \
+ (R_MMU_KBASE_LO__base_6__##f2##__VAL(R_MMU_KBASE_LO_, base_6_, v2) << R_MMU_KBASE_LO__base_6__BITNR) | \
+ (R_MMU_KBASE_LO__base_5__##f3##__VAL(R_MMU_KBASE_LO_, base_5_, v3) << R_MMU_KBASE_LO__base_5__BITNR) | \
+ (R_MMU_KBASE_LO__base_4__##f4##__VAL(R_MMU_KBASE_LO_, base_4_, v4) << R_MMU_KBASE_LO__base_4__BITNR) | \
+ (R_MMU_KBASE_LO__base_3__##f5##__VAL(R_MMU_KBASE_LO_, base_3_, v5) << R_MMU_KBASE_LO__base_3__BITNR) | \
+ (R_MMU_KBASE_LO__base_2__##f6##__VAL(R_MMU_KBASE_LO_, base_2_, v6) << R_MMU_KBASE_LO__base_2__BITNR) | \
+ (R_MMU_KBASE_LO__base_1__##f7##__VAL(R_MMU_KBASE_LO_, base_1_, v7) << R_MMU_KBASE_LO__base_1__BITNR) | \
+ (R_MMU_KBASE_LO__base_0__##f8##__VAL(R_MMU_KBASE_LO_, base_0_, v8) << R_MMU_KBASE_LO__base_0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_KBASE_LO_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_KBASE_LO.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_KBASE_LO_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_MMU_KBASE_LO__base_7__##f1_##_VAL(R_MMU_KBASE_LO_, base_7_, v1) << R_MMU_KBASE_LO__base_7__BITNR) | \
+ (R_MMU_KBASE_LO__base_6__##f2_##_VAL(R_MMU_KBASE_LO_, base_6_, v2) << R_MMU_KBASE_LO__base_6__BITNR) | \
+ (R_MMU_KBASE_LO__base_5__##f3_##_VAL(R_MMU_KBASE_LO_, base_5_, v3) << R_MMU_KBASE_LO__base_5__BITNR) | \
+ (R_MMU_KBASE_LO__base_4__##f4_##_VAL(R_MMU_KBASE_LO_, base_4_, v4) << R_MMU_KBASE_LO__base_4__BITNR) | \
+ (R_MMU_KBASE_LO__base_3__##f5_##_VAL(R_MMU_KBASE_LO_, base_3_, v5) << R_MMU_KBASE_LO__base_3__BITNR) | \
+ (R_MMU_KBASE_LO__base_2__##f6_##_VAL(R_MMU_KBASE_LO_, base_2_, v6) << R_MMU_KBASE_LO__base_2__BITNR) | \
+ (R_MMU_KBASE_LO__base_1__##f7_##_VAL(R_MMU_KBASE_LO_, base_1_, v7) << R_MMU_KBASE_LO__base_1__BITNR) | \
+ (R_MMU_KBASE_LO__base_0__##f8_##_VAL(R_MMU_KBASE_LO_, base_0_, v8) << R_MMU_KBASE_LO__base_0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_MMU_KSEG
+ * - type: WO
+ * - addr: 0xb0000240
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_KSEG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_KSEG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_MMU_KSEG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_KSEG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \
+ *R_MMU_KSEG__SADDR = ( \
+ REG_INITIATED(R_MMU_KSEG_) \
+ REG_VAL__R_MMU_KSEG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16) \
+ ), \
+ R_MMU_KSEG__WRITE(R_MMU_KSEG__ADDR, *R_MMU_KSEG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_MMU_KSEG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_MMU_KSEG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_MMU_KSEG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_MMU_KSEG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \
+ *R_MMU_KSEG__SADDR = ( \
+ REG_INITIATED(R_MMU_KSEG_) \
+ REG_VAL__R_MMU_KSEG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_MMU_KSEG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_MMU_KSEG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \
+ (R_MMU_KSEG__seg_f__##f1##__MASK & REG__##v1) | \
+ (R_MMU_KSEG__seg_e__##f2##__MASK & REG__##v2) | \
+ (R_MMU_KSEG__seg_d__##f3##__MASK & REG__##v3) | \
+ (R_MMU_KSEG__seg_c__##f4##__MASK & REG__##v4) | \
+ (R_MMU_KSEG__seg_b__##f5##__MASK & REG__##v5) | \
+ (R_MMU_KSEG__seg_a__##f6##__MASK & REG__##v6) | \
+ (R_MMU_KSEG__seg_9__##f7##__MASK & REG__##v7) | \
+ (R_MMU_KSEG__seg_8__##f8##__MASK & REG__##v8) | \
+ (R_MMU_KSEG__seg_7__##f9##__MASK & REG__##v9) | \
+ (R_MMU_KSEG__seg_6__##f10##__MASK & REG__##v10) | \
+ (R_MMU_KSEG__seg_5__##f11##__MASK & REG__##v11) | \
+ (R_MMU_KSEG__seg_4__##f12##__MASK & REG__##v12) | \
+ (R_MMU_KSEG__seg_3__##f13##__MASK & REG__##v13) | \
+ (R_MMU_KSEG__seg_2__##f14##__MASK & REG__##v14) | \
+ (R_MMU_KSEG__seg_1__##f15##__MASK & REG__##v15) | \
+ (R_MMU_KSEG__seg_0__##f16##__MASK & REG__##v16) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_KSEG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_KSEG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_KSEG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \
+ (R_MMU_KSEG__seg_f__##f1##__VAL(R_MMU_KSEG_, seg_f_, v1) << R_MMU_KSEG__seg_f__BITNR) | \
+ (R_MMU_KSEG__seg_e__##f2##__VAL(R_MMU_KSEG_, seg_e_, v2) << R_MMU_KSEG__seg_e__BITNR) | \
+ (R_MMU_KSEG__seg_d__##f3##__VAL(R_MMU_KSEG_, seg_d_, v3) << R_MMU_KSEG__seg_d__BITNR) | \
+ (R_MMU_KSEG__seg_c__##f4##__VAL(R_MMU_KSEG_, seg_c_, v4) << R_MMU_KSEG__seg_c__BITNR) | \
+ (R_MMU_KSEG__seg_b__##f5##__VAL(R_MMU_KSEG_, seg_b_, v5) << R_MMU_KSEG__seg_b__BITNR) | \
+ (R_MMU_KSEG__seg_a__##f6##__VAL(R_MMU_KSEG_, seg_a_, v6) << R_MMU_KSEG__seg_a__BITNR) | \
+ (R_MMU_KSEG__seg_9__##f7##__VAL(R_MMU_KSEG_, seg_9_, v7) << R_MMU_KSEG__seg_9__BITNR) | \
+ (R_MMU_KSEG__seg_8__##f8##__VAL(R_MMU_KSEG_, seg_8_, v8) << R_MMU_KSEG__seg_8__BITNR) | \
+ (R_MMU_KSEG__seg_7__##f9##__VAL(R_MMU_KSEG_, seg_7_, v9) << R_MMU_KSEG__seg_7__BITNR) | \
+ (R_MMU_KSEG__seg_6__##f10##__VAL(R_MMU_KSEG_, seg_6_, v10) << R_MMU_KSEG__seg_6__BITNR) | \
+ (R_MMU_KSEG__seg_5__##f11##__VAL(R_MMU_KSEG_, seg_5_, v11) << R_MMU_KSEG__seg_5__BITNR) | \
+ (R_MMU_KSEG__seg_4__##f12##__VAL(R_MMU_KSEG_, seg_4_, v12) << R_MMU_KSEG__seg_4__BITNR) | \
+ (R_MMU_KSEG__seg_3__##f13##__VAL(R_MMU_KSEG_, seg_3_, v13) << R_MMU_KSEG__seg_3__BITNR) | \
+ (R_MMU_KSEG__seg_2__##f14##__VAL(R_MMU_KSEG_, seg_2_, v14) << R_MMU_KSEG__seg_2__BITNR) | \
+ (R_MMU_KSEG__seg_1__##f15##__VAL(R_MMU_KSEG_, seg_1_, v15) << R_MMU_KSEG__seg_1__BITNR) | \
+ (R_MMU_KSEG__seg_0__##f16##__VAL(R_MMU_KSEG_, seg_0_, v16) << R_MMU_KSEG__seg_0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_MMU_KSEG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_MMU_KSEG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_MMU_KSEG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16) ( \
+ (R_MMU_KSEG__seg_f__##f1_##_VAL(R_MMU_KSEG_, seg_f_, v1) << R_MMU_KSEG__seg_f__BITNR) | \
+ (R_MMU_KSEG__seg_e__##f2_##_VAL(R_MMU_KSEG_, seg_e_, v2) << R_MMU_KSEG__seg_e__BITNR) | \
+ (R_MMU_KSEG__seg_d__##f3_##_VAL(R_MMU_KSEG_, seg_d_, v3) << R_MMU_KSEG__seg_d__BITNR) | \
+ (R_MMU_KSEG__seg_c__##f4_##_VAL(R_MMU_KSEG_, seg_c_, v4) << R_MMU_KSEG__seg_c__BITNR) | \
+ (R_MMU_KSEG__seg_b__##f5_##_VAL(R_MMU_KSEG_, seg_b_, v5) << R_MMU_KSEG__seg_b__BITNR) | \
+ (R_MMU_KSEG__seg_a__##f6_##_VAL(R_MMU_KSEG_, seg_a_, v6) << R_MMU_KSEG__seg_a__BITNR) | \
+ (R_MMU_KSEG__seg_9__##f7_##_VAL(R_MMU_KSEG_, seg_9_, v7) << R_MMU_KSEG__seg_9__BITNR) | \
+ (R_MMU_KSEG__seg_8__##f8_##_VAL(R_MMU_KSEG_, seg_8_, v8) << R_MMU_KSEG__seg_8__BITNR) | \
+ (R_MMU_KSEG__seg_7__##f9_##_VAL(R_MMU_KSEG_, seg_7_, v9) << R_MMU_KSEG__seg_7__BITNR) | \
+ (R_MMU_KSEG__seg_6__##f10_##_VAL(R_MMU_KSEG_, seg_6_, v10) << R_MMU_KSEG__seg_6__BITNR) | \
+ (R_MMU_KSEG__seg_5__##f11_##_VAL(R_MMU_KSEG_, seg_5_, v11) << R_MMU_KSEG__seg_5__BITNR) | \
+ (R_MMU_KSEG__seg_4__##f12_##_VAL(R_MMU_KSEG_, seg_4_, v12) << R_MMU_KSEG__seg_4__BITNR) | \
+ (R_MMU_KSEG__seg_3__##f13_##_VAL(R_MMU_KSEG_, seg_3_, v13) << R_MMU_KSEG__seg_3__BITNR) | \
+ (R_MMU_KSEG__seg_2__##f14_##_VAL(R_MMU_KSEG_, seg_2_, v14) << R_MMU_KSEG__seg_2__BITNR) | \
+ (R_MMU_KSEG__seg_1__##f15_##_VAL(R_MMU_KSEG_, seg_1_, v15) << R_MMU_KSEG__seg_1__BITNR) | \
+ (R_MMU_KSEG__seg_0__##f16_##_VAL(R_MMU_KSEG_, seg_0_, v16) << R_MMU_KSEG__seg_0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_GA_0
+ * - type: WO
+ * - addr: 0xb000008c
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_GA_0
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_GA_0.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_GA_0.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_GA_0(f1,v1) ( \
+ *R_NETWORK_GA_0__SADDR = ( \
+ REG_INITIATED(R_NETWORK_GA_0_) \
+ REG_VAL__R_NETWORK_GA_0_(f1##_,v1) \
+ ), \
+ R_NETWORK_GA_0__WRITE(R_NETWORK_GA_0__ADDR, *R_NETWORK_GA_0__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_GA_0__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_GA_0.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_GA_0.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_GA_0__SHADOW(f1,v1) ( \
+ *R_NETWORK_GA_0__SADDR = ( \
+ REG_INITIATED(R_NETWORK_GA_0_) \
+ REG_VAL__R_NETWORK_GA_0_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_GA_0
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_GA_0(f1,v1) ( \
+ (R_NETWORK_GA_0__ga_low__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_GA_0
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_GA_0.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_GA_0(f1,v1) ( \
+ (R_NETWORK_GA_0__ga_low__##f1##__VAL(R_NETWORK_GA_0_, ga_low_, v1) << R_NETWORK_GA_0__ga_low__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_GA_0_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_GA_0.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_GA_0_(f1_,v1) ( \
+ (R_NETWORK_GA_0__ga_low__##f1_##_VAL(R_NETWORK_GA_0_, ga_low_, v1) << R_NETWORK_GA_0__ga_low__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_GA_1
+ * - type: WO
+ * - addr: 0xb0000090
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_GA_1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_GA_1.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_GA_1.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_GA_1(f1,v1) ( \
+ *R_NETWORK_GA_1__SADDR = ( \
+ REG_INITIATED(R_NETWORK_GA_1_) \
+ REG_VAL__R_NETWORK_GA_1_(f1##_,v1) \
+ ), \
+ R_NETWORK_GA_1__WRITE(R_NETWORK_GA_1__ADDR, *R_NETWORK_GA_1__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_GA_1__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_GA_1.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_GA_1.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_GA_1__SHADOW(f1,v1) ( \
+ *R_NETWORK_GA_1__SADDR = ( \
+ REG_INITIATED(R_NETWORK_GA_1_) \
+ REG_VAL__R_NETWORK_GA_1_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_GA_1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_GA_1(f1,v1) ( \
+ (R_NETWORK_GA_1__ga_high__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_GA_1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_GA_1.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_GA_1(f1,v1) ( \
+ (R_NETWORK_GA_1__ga_high__##f1##__VAL(R_NETWORK_GA_1_, ga_high_, v1) << R_NETWORK_GA_1__ga_high__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_GA_1_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_GA_1.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_GA_1_(f1_,v1) ( \
+ (R_NETWORK_GA_1__ga_high__##f1_##_VAL(R_NETWORK_GA_1_, ga_high_, v1) << R_NETWORK_GA_1__ga_high__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_GEN_CONFIG
+ * - type: WO
+ * - addr: 0xb0000098
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_GEN_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_GEN_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_GEN_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ *R_NETWORK_GEN_CONFIG__SADDR = ( \
+ REG_INITIATED(R_NETWORK_GEN_CONFIG_) \
+ REG_VAL__R_NETWORK_GEN_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \
+ ), \
+ R_NETWORK_GEN_CONFIG__WRITE(R_NETWORK_GEN_CONFIG__ADDR, *R_NETWORK_GEN_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_GEN_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_GEN_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_GEN_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_GEN_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ *R_NETWORK_GEN_CONFIG__SADDR = ( \
+ REG_INITIATED(R_NETWORK_GEN_CONFIG_) \
+ REG_VAL__R_NETWORK_GEN_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_GEN_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_NETWORK_GEN_CONFIG__loopback__##f1##__MASK & REG__##v1) | \
+ (R_NETWORK_GEN_CONFIG__frame__##f2##__MASK & REG__##v2) | \
+ (R_NETWORK_GEN_CONFIG__vg__##f3##__MASK & REG__##v3) | \
+ (R_NETWORK_GEN_CONFIG__phy__##f4##__MASK & REG__##v4) | \
+ (R_NETWORK_GEN_CONFIG__enable__##f5##__MASK & REG__##v5) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_GEN_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_GEN_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_GEN_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_NETWORK_GEN_CONFIG__loopback__##f1##__VAL(R_NETWORK_GEN_CONFIG_, loopback_, v1) << R_NETWORK_GEN_CONFIG__loopback__BITNR) | \
+ (R_NETWORK_GEN_CONFIG__frame__##f2##__VAL(R_NETWORK_GEN_CONFIG_, frame_, v2) << R_NETWORK_GEN_CONFIG__frame__BITNR) | \
+ (R_NETWORK_GEN_CONFIG__vg__##f3##__VAL(R_NETWORK_GEN_CONFIG_, vg_, v3) << R_NETWORK_GEN_CONFIG__vg__BITNR) | \
+ (R_NETWORK_GEN_CONFIG__phy__##f4##__VAL(R_NETWORK_GEN_CONFIG_, phy_, v4) << R_NETWORK_GEN_CONFIG__phy__BITNR) | \
+ (R_NETWORK_GEN_CONFIG__enable__##f5##__VAL(R_NETWORK_GEN_CONFIG_, enable_, v5) << R_NETWORK_GEN_CONFIG__enable__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_GEN_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_GEN_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_GEN_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \
+ (R_NETWORK_GEN_CONFIG__loopback__##f1_##_VAL(R_NETWORK_GEN_CONFIG_, loopback_, v1) << R_NETWORK_GEN_CONFIG__loopback__BITNR) | \
+ (R_NETWORK_GEN_CONFIG__frame__##f2_##_VAL(R_NETWORK_GEN_CONFIG_, frame_, v2) << R_NETWORK_GEN_CONFIG__frame__BITNR) | \
+ (R_NETWORK_GEN_CONFIG__vg__##f3_##_VAL(R_NETWORK_GEN_CONFIG_, vg_, v3) << R_NETWORK_GEN_CONFIG__vg__BITNR) | \
+ (R_NETWORK_GEN_CONFIG__phy__##f4_##_VAL(R_NETWORK_GEN_CONFIG_, phy_, v4) << R_NETWORK_GEN_CONFIG__phy__BITNR) | \
+ (R_NETWORK_GEN_CONFIG__enable__##f5_##_VAL(R_NETWORK_GEN_CONFIG_, enable_, v5) << R_NETWORK_GEN_CONFIG__enable__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_MGM_CTRL
+ * - type: WO
+ * - addr: 0xb00000a0
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_MGM_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_MGM_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_MGM_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_MGM_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ *R_NETWORK_MGM_CTRL__SADDR = ( \
+ REG_INITIATED(R_NETWORK_MGM_CTRL_) \
+ REG_VAL__R_NETWORK_MGM_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \
+ ), \
+ R_NETWORK_MGM_CTRL__WRITE(R_NETWORK_MGM_CTRL__ADDR, *R_NETWORK_MGM_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_MGM_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_MGM_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_MGM_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_MGM_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ *R_NETWORK_MGM_CTRL__SADDR = ( \
+ REG_INITIATED(R_NETWORK_MGM_CTRL_) \
+ REG_VAL__R_NETWORK_MGM_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_MGM_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_MGM_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_NETWORK_MGM_CTRL__txd_pins__##f1##__MASK & REG__##v1) | \
+ (R_NETWORK_MGM_CTRL__txer_pin__##f2##__MASK & REG__##v2) | \
+ (R_NETWORK_MGM_CTRL__mdck__##f3##__MASK & REG__##v3) | \
+ (R_NETWORK_MGM_CTRL__mdoe__##f4##__MASK & REG__##v4) | \
+ (R_NETWORK_MGM_CTRL__mdio__##f5##__MASK & REG__##v5) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_MGM_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_MGM_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_MGM_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_NETWORK_MGM_CTRL__txd_pins__##f1##__VAL(R_NETWORK_MGM_CTRL_, txd_pins_, v1) << R_NETWORK_MGM_CTRL__txd_pins__BITNR) | \
+ (R_NETWORK_MGM_CTRL__txer_pin__##f2##__VAL(R_NETWORK_MGM_CTRL_, txer_pin_, v2) << R_NETWORK_MGM_CTRL__txer_pin__BITNR) | \
+ (R_NETWORK_MGM_CTRL__mdck__##f3##__VAL(R_NETWORK_MGM_CTRL_, mdck_, v3) << R_NETWORK_MGM_CTRL__mdck__BITNR) | \
+ (R_NETWORK_MGM_CTRL__mdoe__##f4##__VAL(R_NETWORK_MGM_CTRL_, mdoe_, v4) << R_NETWORK_MGM_CTRL__mdoe__BITNR) | \
+ (R_NETWORK_MGM_CTRL__mdio__##f5##__VAL(R_NETWORK_MGM_CTRL_, mdio_, v5) << R_NETWORK_MGM_CTRL__mdio__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_MGM_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_MGM_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_MGM_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \
+ (R_NETWORK_MGM_CTRL__txd_pins__##f1_##_VAL(R_NETWORK_MGM_CTRL_, txd_pins_, v1) << R_NETWORK_MGM_CTRL__txd_pins__BITNR) | \
+ (R_NETWORK_MGM_CTRL__txer_pin__##f2_##_VAL(R_NETWORK_MGM_CTRL_, txer_pin_, v2) << R_NETWORK_MGM_CTRL__txer_pin__BITNR) | \
+ (R_NETWORK_MGM_CTRL__mdck__##f3_##_VAL(R_NETWORK_MGM_CTRL_, mdck_, v3) << R_NETWORK_MGM_CTRL__mdck__BITNR) | \
+ (R_NETWORK_MGM_CTRL__mdoe__##f4_##_VAL(R_NETWORK_MGM_CTRL_, mdoe_, v4) << R_NETWORK_MGM_CTRL__mdoe__BITNR) | \
+ (R_NETWORK_MGM_CTRL__mdio__##f5_##_VAL(R_NETWORK_MGM_CTRL_, mdio_, v5) << R_NETWORK_MGM_CTRL__mdio__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_REC_CONFIG
+ * - type: WO
+ * - addr: 0xb0000094
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_REC_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_REC_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_REC_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_REC_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ *R_NETWORK_REC_CONFIG__SADDR = ( \
+ REG_INITIATED(R_NETWORK_REC_CONFIG_) \
+ REG_VAL__R_NETWORK_REC_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \
+ ), \
+ R_NETWORK_REC_CONFIG__WRITE(R_NETWORK_REC_CONFIG__ADDR, *R_NETWORK_REC_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_REC_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_REC_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_REC_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_REC_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ *R_NETWORK_REC_CONFIG__SADDR = ( \
+ REG_INITIATED(R_NETWORK_REC_CONFIG_) \
+ REG_VAL__R_NETWORK_REC_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_REC_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_REC_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ (R_NETWORK_REC_CONFIG__max_size__##f1##__MASK & REG__##v1) | \
+ (R_NETWORK_REC_CONFIG__duplex__##f2##__MASK & REG__##v2) | \
+ (R_NETWORK_REC_CONFIG__bad_crc__##f3##__MASK & REG__##v3) | \
+ (R_NETWORK_REC_CONFIG__oversize__##f4##__MASK & REG__##v4) | \
+ (R_NETWORK_REC_CONFIG__undersize__##f5##__MASK & REG__##v5) | \
+ (R_NETWORK_REC_CONFIG__all_roots__##f6##__MASK & REG__##v6) | \
+ (R_NETWORK_REC_CONFIG__tr_broadcast__##f7##__MASK & REG__##v7) | \
+ (R_NETWORK_REC_CONFIG__broadcast__##f8##__MASK & REG__##v8) | \
+ (R_NETWORK_REC_CONFIG__individual__##f9##__MASK & REG__##v9) | \
+ (R_NETWORK_REC_CONFIG__ma1__##f10##__MASK & REG__##v10) | \
+ (R_NETWORK_REC_CONFIG__ma0__##f11##__MASK & REG__##v11) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_REC_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_REC_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_REC_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ (R_NETWORK_REC_CONFIG__max_size__##f1##__VAL(R_NETWORK_REC_CONFIG_, max_size_, v1) << R_NETWORK_REC_CONFIG__max_size__BITNR) | \
+ (R_NETWORK_REC_CONFIG__duplex__##f2##__VAL(R_NETWORK_REC_CONFIG_, duplex_, v2) << R_NETWORK_REC_CONFIG__duplex__BITNR) | \
+ (R_NETWORK_REC_CONFIG__bad_crc__##f3##__VAL(R_NETWORK_REC_CONFIG_, bad_crc_, v3) << R_NETWORK_REC_CONFIG__bad_crc__BITNR) | \
+ (R_NETWORK_REC_CONFIG__oversize__##f4##__VAL(R_NETWORK_REC_CONFIG_, oversize_, v4) << R_NETWORK_REC_CONFIG__oversize__BITNR) | \
+ (R_NETWORK_REC_CONFIG__undersize__##f5##__VAL(R_NETWORK_REC_CONFIG_, undersize_, v5) << R_NETWORK_REC_CONFIG__undersize__BITNR) | \
+ (R_NETWORK_REC_CONFIG__all_roots__##f6##__VAL(R_NETWORK_REC_CONFIG_, all_roots_, v6) << R_NETWORK_REC_CONFIG__all_roots__BITNR) | \
+ (R_NETWORK_REC_CONFIG__tr_broadcast__##f7##__VAL(R_NETWORK_REC_CONFIG_, tr_broadcast_, v7) << R_NETWORK_REC_CONFIG__tr_broadcast__BITNR) | \
+ (R_NETWORK_REC_CONFIG__broadcast__##f8##__VAL(R_NETWORK_REC_CONFIG_, broadcast_, v8) << R_NETWORK_REC_CONFIG__broadcast__BITNR) | \
+ (R_NETWORK_REC_CONFIG__individual__##f9##__VAL(R_NETWORK_REC_CONFIG_, individual_, v9) << R_NETWORK_REC_CONFIG__individual__BITNR) | \
+ (R_NETWORK_REC_CONFIG__ma1__##f10##__VAL(R_NETWORK_REC_CONFIG_, ma1_, v10) << R_NETWORK_REC_CONFIG__ma1__BITNR) | \
+ (R_NETWORK_REC_CONFIG__ma0__##f11##__VAL(R_NETWORK_REC_CONFIG_, ma0_, v11) << R_NETWORK_REC_CONFIG__ma0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_REC_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_REC_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_REC_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11) ( \
+ (R_NETWORK_REC_CONFIG__max_size__##f1_##_VAL(R_NETWORK_REC_CONFIG_, max_size_, v1) << R_NETWORK_REC_CONFIG__max_size__BITNR) | \
+ (R_NETWORK_REC_CONFIG__duplex__##f2_##_VAL(R_NETWORK_REC_CONFIG_, duplex_, v2) << R_NETWORK_REC_CONFIG__duplex__BITNR) | \
+ (R_NETWORK_REC_CONFIG__bad_crc__##f3_##_VAL(R_NETWORK_REC_CONFIG_, bad_crc_, v3) << R_NETWORK_REC_CONFIG__bad_crc__BITNR) | \
+ (R_NETWORK_REC_CONFIG__oversize__##f4_##_VAL(R_NETWORK_REC_CONFIG_, oversize_, v4) << R_NETWORK_REC_CONFIG__oversize__BITNR) | \
+ (R_NETWORK_REC_CONFIG__undersize__##f5_##_VAL(R_NETWORK_REC_CONFIG_, undersize_, v5) << R_NETWORK_REC_CONFIG__undersize__BITNR) | \
+ (R_NETWORK_REC_CONFIG__all_roots__##f6_##_VAL(R_NETWORK_REC_CONFIG_, all_roots_, v6) << R_NETWORK_REC_CONFIG__all_roots__BITNR) | \
+ (R_NETWORK_REC_CONFIG__tr_broadcast__##f7_##_VAL(R_NETWORK_REC_CONFIG_, tr_broadcast_, v7) << R_NETWORK_REC_CONFIG__tr_broadcast__BITNR) | \
+ (R_NETWORK_REC_CONFIG__broadcast__##f8_##_VAL(R_NETWORK_REC_CONFIG_, broadcast_, v8) << R_NETWORK_REC_CONFIG__broadcast__BITNR) | \
+ (R_NETWORK_REC_CONFIG__individual__##f9_##_VAL(R_NETWORK_REC_CONFIG_, individual_, v9) << R_NETWORK_REC_CONFIG__individual__BITNR) | \
+ (R_NETWORK_REC_CONFIG__ma1__##f10_##_VAL(R_NETWORK_REC_CONFIG_, ma1_, v10) << R_NETWORK_REC_CONFIG__ma1__BITNR) | \
+ (R_NETWORK_REC_CONFIG__ma0__##f11_##_VAL(R_NETWORK_REC_CONFIG_, ma0_, v11) << R_NETWORK_REC_CONFIG__ma0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_SA_0
+ * - type: WO
+ * - addr: 0xb0000080
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_SA_0
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_SA_0.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_SA_0.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_SA_0(f1,v1) ( \
+ *R_NETWORK_SA_0__SADDR = ( \
+ REG_INITIATED(R_NETWORK_SA_0_) \
+ REG_VAL__R_NETWORK_SA_0_(f1##_,v1) \
+ ), \
+ R_NETWORK_SA_0__WRITE(R_NETWORK_SA_0__ADDR, *R_NETWORK_SA_0__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_SA_0__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_SA_0.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_SA_0.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_SA_0__SHADOW(f1,v1) ( \
+ *R_NETWORK_SA_0__SADDR = ( \
+ REG_INITIATED(R_NETWORK_SA_0_) \
+ REG_VAL__R_NETWORK_SA_0_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_SA_0
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_SA_0(f1,v1) ( \
+ (R_NETWORK_SA_0__ma0_low__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_SA_0
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_SA_0.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_SA_0(f1,v1) ( \
+ (R_NETWORK_SA_0__ma0_low__##f1##__VAL(R_NETWORK_SA_0_, ma0_low_, v1) << R_NETWORK_SA_0__ma0_low__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_SA_0_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_SA_0.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_SA_0_(f1_,v1) ( \
+ (R_NETWORK_SA_0__ma0_low__##f1_##_VAL(R_NETWORK_SA_0_, ma0_low_, v1) << R_NETWORK_SA_0__ma0_low__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_SA_1
+ * - type: WO
+ * - addr: 0xb0000084
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_SA_1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_SA_1.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_SA_1.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_SA_1(f1,v1,f2,v2) ( \
+ *R_NETWORK_SA_1__SADDR = ( \
+ REG_INITIATED(R_NETWORK_SA_1_) \
+ REG_VAL__R_NETWORK_SA_1_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_NETWORK_SA_1__WRITE(R_NETWORK_SA_1__ADDR, *R_NETWORK_SA_1__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_SA_1__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_SA_1.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_SA_1.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_SA_1__SHADOW(f1,v1,f2,v2) ( \
+ *R_NETWORK_SA_1__SADDR = ( \
+ REG_INITIATED(R_NETWORK_SA_1_) \
+ REG_VAL__R_NETWORK_SA_1_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_SA_1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_SA_1(f1,v1,f2,v2) ( \
+ (R_NETWORK_SA_1__ma1_low__##f1##__MASK & REG__##v1) | \
+ (R_NETWORK_SA_1__ma0_high__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_SA_1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_SA_1.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_SA_1(f1,v1,f2,v2) ( \
+ (R_NETWORK_SA_1__ma1_low__##f1##__VAL(R_NETWORK_SA_1_, ma1_low_, v1) << R_NETWORK_SA_1__ma1_low__BITNR) | \
+ (R_NETWORK_SA_1__ma0_high__##f2##__VAL(R_NETWORK_SA_1_, ma0_high_, v2) << R_NETWORK_SA_1__ma0_high__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_SA_1_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_SA_1.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_SA_1_(f1_,v1,f2_,v2) ( \
+ (R_NETWORK_SA_1__ma1_low__##f1_##_VAL(R_NETWORK_SA_1_, ma1_low_, v1) << R_NETWORK_SA_1__ma1_low__BITNR) | \
+ (R_NETWORK_SA_1__ma0_high__##f2_##_VAL(R_NETWORK_SA_1_, ma0_high_, v2) << R_NETWORK_SA_1__ma0_high__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_SA_2
+ * - type: WO
+ * - addr: 0xb0000088
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_SA_2
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_SA_2.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_SA_2.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_SA_2(f1,v1) ( \
+ *R_NETWORK_SA_2__SADDR = ( \
+ REG_INITIATED(R_NETWORK_SA_2_) \
+ REG_VAL__R_NETWORK_SA_2_(f1##_,v1) \
+ ), \
+ R_NETWORK_SA_2__WRITE(R_NETWORK_SA_2__ADDR, *R_NETWORK_SA_2__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_SA_2__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_SA_2.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_SA_2.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_SA_2__SHADOW(f1,v1) ( \
+ *R_NETWORK_SA_2__SADDR = ( \
+ REG_INITIATED(R_NETWORK_SA_2_) \
+ REG_VAL__R_NETWORK_SA_2_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_SA_2
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_SA_2(f1,v1) ( \
+ (R_NETWORK_SA_2__ma1_high__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_SA_2
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_SA_2.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_SA_2(f1,v1) ( \
+ (R_NETWORK_SA_2__ma1_high__##f1##__VAL(R_NETWORK_SA_2_, ma1_high_, v1) << R_NETWORK_SA_2__ma1_high__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_SA_2_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_SA_2.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_SA_2_(f1_,v1) ( \
+ (R_NETWORK_SA_2__ma1_high__##f1_##_VAL(R_NETWORK_SA_2_, ma1_high_, v1) << R_NETWORK_SA_2__ma1_high__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_STAT
+ * - type: RO
+ * - addr: 0xb00000a0
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_STAT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_STAT(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_NETWORK_STAT__rxd_pins__##f1##__MASK & REG__##v1) | \
+ (R_NETWORK_STAT__rxer__##f2##__MASK & REG__##v2) | \
+ (R_NETWORK_STAT__underrun__##f3##__MASK & REG__##v3) | \
+ (R_NETWORK_STAT__exc_col__##f4##__MASK & REG__##v4) | \
+ (R_NETWORK_STAT__mdio__##f5##__MASK & REG__##v5) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_STAT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_STAT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_STAT(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_NETWORK_STAT__rxd_pins__##f1##__VAL(R_NETWORK_STAT_, rxd_pins_, v1) << R_NETWORK_STAT__rxd_pins__BITNR) | \
+ (R_NETWORK_STAT__rxer__##f2##__VAL(R_NETWORK_STAT_, rxer_, v2) << R_NETWORK_STAT__rxer__BITNR) | \
+ (R_NETWORK_STAT__underrun__##f3##__VAL(R_NETWORK_STAT_, underrun_, v3) << R_NETWORK_STAT__underrun__BITNR) | \
+ (R_NETWORK_STAT__exc_col__##f4##__VAL(R_NETWORK_STAT_, exc_col_, v4) << R_NETWORK_STAT__exc_col__BITNR) | \
+ (R_NETWORK_STAT__mdio__##f5##__VAL(R_NETWORK_STAT_, mdio_, v5) << R_NETWORK_STAT__mdio__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_STAT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_STAT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_STAT_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \
+ (R_NETWORK_STAT__rxd_pins__##f1_##_VAL(R_NETWORK_STAT_, rxd_pins_, v1) << R_NETWORK_STAT__rxd_pins__BITNR) | \
+ (R_NETWORK_STAT__rxer__##f2_##_VAL(R_NETWORK_STAT_, rxer_, v2) << R_NETWORK_STAT__rxer__BITNR) | \
+ (R_NETWORK_STAT__underrun__##f3_##_VAL(R_NETWORK_STAT_, underrun_, v3) << R_NETWORK_STAT__underrun__BITNR) | \
+ (R_NETWORK_STAT__exc_col__##f4_##_VAL(R_NETWORK_STAT_, exc_col_, v4) << R_NETWORK_STAT__exc_col__BITNR) | \
+ (R_NETWORK_STAT__mdio__##f5_##_VAL(R_NETWORK_STAT_, mdio_, v5) << R_NETWORK_STAT__mdio__BITNR) \
+)
+
+#endif
+
+/*
+ * R_NETWORK_TR_CTRL
+ * - type: WO
+ * - addr: 0xb000009c
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_NETWORK_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ *R_NETWORK_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_NETWORK_TR_CTRL_) \
+ REG_VAL__R_NETWORK_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7) \
+ ), \
+ R_NETWORK_TR_CTRL__WRITE(R_NETWORK_TR_CTRL__ADDR, *R_NETWORK_TR_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_NETWORK_TR_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_NETWORK_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_NETWORK_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_NETWORK_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ *R_NETWORK_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_NETWORK_TR_CTRL_) \
+ REG_VAL__R_NETWORK_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_NETWORK_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_NETWORK_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ (R_NETWORK_TR_CTRL__clr_error__##f1##__MASK & REG__##v1) | \
+ (R_NETWORK_TR_CTRL__delay__##f2##__MASK & REG__##v2) | \
+ (R_NETWORK_TR_CTRL__cancel__##f3##__MASK & REG__##v3) | \
+ (R_NETWORK_TR_CTRL__cd__##f4##__MASK & REG__##v4) | \
+ (R_NETWORK_TR_CTRL__retry__##f5##__MASK & REG__##v5) | \
+ (R_NETWORK_TR_CTRL__pad__##f6##__MASK & REG__##v6) | \
+ (R_NETWORK_TR_CTRL__crc__##f7##__MASK & REG__##v7) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_TR_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ (R_NETWORK_TR_CTRL__clr_error__##f1##__VAL(R_NETWORK_TR_CTRL_, clr_error_, v1) << R_NETWORK_TR_CTRL__clr_error__BITNR) | \
+ (R_NETWORK_TR_CTRL__delay__##f2##__VAL(R_NETWORK_TR_CTRL_, delay_, v2) << R_NETWORK_TR_CTRL__delay__BITNR) | \
+ (R_NETWORK_TR_CTRL__cancel__##f3##__VAL(R_NETWORK_TR_CTRL_, cancel_, v3) << R_NETWORK_TR_CTRL__cancel__BITNR) | \
+ (R_NETWORK_TR_CTRL__cd__##f4##__VAL(R_NETWORK_TR_CTRL_, cd_, v4) << R_NETWORK_TR_CTRL__cd__BITNR) | \
+ (R_NETWORK_TR_CTRL__retry__##f5##__VAL(R_NETWORK_TR_CTRL_, retry_, v5) << R_NETWORK_TR_CTRL__retry__BITNR) | \
+ (R_NETWORK_TR_CTRL__pad__##f6##__VAL(R_NETWORK_TR_CTRL_, pad_, v6) << R_NETWORK_TR_CTRL__pad__BITNR) | \
+ (R_NETWORK_TR_CTRL__crc__##f7##__VAL(R_NETWORK_TR_CTRL_, crc_, v7) << R_NETWORK_TR_CTRL__crc__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_NETWORK_TR_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_NETWORK_TR_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_NETWORK_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7) ( \
+ (R_NETWORK_TR_CTRL__clr_error__##f1_##_VAL(R_NETWORK_TR_CTRL_, clr_error_, v1) << R_NETWORK_TR_CTRL__clr_error__BITNR) | \
+ (R_NETWORK_TR_CTRL__delay__##f2_##_VAL(R_NETWORK_TR_CTRL_, delay_, v2) << R_NETWORK_TR_CTRL__delay__BITNR) | \
+ (R_NETWORK_TR_CTRL__cancel__##f3_##_VAL(R_NETWORK_TR_CTRL_, cancel_, v3) << R_NETWORK_TR_CTRL__cancel__BITNR) | \
+ (R_NETWORK_TR_CTRL__cd__##f4_##_VAL(R_NETWORK_TR_CTRL_, cd_, v4) << R_NETWORK_TR_CTRL__cd__BITNR) | \
+ (R_NETWORK_TR_CTRL__retry__##f5_##_VAL(R_NETWORK_TR_CTRL_, retry_, v5) << R_NETWORK_TR_CTRL__retry__BITNR) | \
+ (R_NETWORK_TR_CTRL__pad__##f6_##_VAL(R_NETWORK_TR_CTRL_, pad_, v6) << R_NETWORK_TR_CTRL__pad__BITNR) | \
+ (R_NETWORK_TR_CTRL__crc__##f7_##_VAL(R_NETWORK_TR_CTRL_, crc_, v7) << R_NETWORK_TR_CTRL__crc__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR0_CONFIG
+ * - type: WO
+ * - addr: 0xb0000044
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR0_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR0_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR0_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR0_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \
+ *R_PAR0_CONFIG__SADDR = ( \
+ REG_INITIATED(R_PAR0_CONFIG_) \
+ REG_VAL__R_PAR0_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20) \
+ ), \
+ R_PAR0_CONFIG__WRITE(R_PAR0_CONFIG__ADDR, *R_PAR0_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR0_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR0_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PAR0_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR0_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \
+ *R_PAR0_CONFIG__SADDR = ( \
+ REG_INITIATED(R_PAR0_CONFIG_) \
+ REG_VAL__R_PAR0_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR0_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR0_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \
+ (R_PAR0_CONFIG__ioe__##f1##__MASK & REG__##v1) | \
+ (R_PAR0_CONFIG__iseli__##f2##__MASK & REG__##v2) | \
+ (R_PAR0_CONFIG__iautofd__##f3##__MASK & REG__##v3) | \
+ (R_PAR0_CONFIG__istrb__##f4##__MASK & REG__##v4) | \
+ (R_PAR0_CONFIG__iinit__##f5##__MASK & REG__##v5) | \
+ (R_PAR0_CONFIG__iperr__##f6##__MASK & REG__##v6) | \
+ (R_PAR0_CONFIG__iack__##f7##__MASK & REG__##v7) | \
+ (R_PAR0_CONFIG__ibusy__##f8##__MASK & REG__##v8) | \
+ (R_PAR0_CONFIG__ifault__##f9##__MASK & REG__##v9) | \
+ (R_PAR0_CONFIG__isel__##f10##__MASK & REG__##v10) | \
+ (R_PAR0_CONFIG__ext_mode__##f11##__MASK & REG__##v11) | \
+ (R_PAR0_CONFIG__wide__##f12##__MASK & REG__##v12) | \
+ (R_PAR0_CONFIG__dma__##f13##__MASK & REG__##v13) | \
+ (R_PAR0_CONFIG__rle_in__##f14##__MASK & REG__##v14) | \
+ (R_PAR0_CONFIG__rle_out__##f15##__MASK & REG__##v15) | \
+ (R_PAR0_CONFIG__enable__##f16##__MASK & REG__##v16) | \
+ (R_PAR0_CONFIG__force__##f17##__MASK & REG__##v17) | \
+ (R_PAR0_CONFIG__ign_ack__##f18##__MASK & REG__##v18) | \
+ (R_PAR0_CONFIG__oe_ack__##f19##__MASK & REG__##v19) | \
+ (R_PAR0_CONFIG__mode__##f20##__MASK & REG__##v20) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20) ( \
+ (R_PAR0_CONFIG__ioe__##f1##__VAL(R_PAR0_CONFIG_, ioe_, v1) << R_PAR0_CONFIG__ioe__BITNR) | \
+ (R_PAR0_CONFIG__iseli__##f2##__VAL(R_PAR0_CONFIG_, iseli_, v2) << R_PAR0_CONFIG__iseli__BITNR) | \
+ (R_PAR0_CONFIG__iautofd__##f3##__VAL(R_PAR0_CONFIG_, iautofd_, v3) << R_PAR0_CONFIG__iautofd__BITNR) | \
+ (R_PAR0_CONFIG__istrb__##f4##__VAL(R_PAR0_CONFIG_, istrb_, v4) << R_PAR0_CONFIG__istrb__BITNR) | \
+ (R_PAR0_CONFIG__iinit__##f5##__VAL(R_PAR0_CONFIG_, iinit_, v5) << R_PAR0_CONFIG__iinit__BITNR) | \
+ (R_PAR0_CONFIG__iperr__##f6##__VAL(R_PAR0_CONFIG_, iperr_, v6) << R_PAR0_CONFIG__iperr__BITNR) | \
+ (R_PAR0_CONFIG__iack__##f7##__VAL(R_PAR0_CONFIG_, iack_, v7) << R_PAR0_CONFIG__iack__BITNR) | \
+ (R_PAR0_CONFIG__ibusy__##f8##__VAL(R_PAR0_CONFIG_, ibusy_, v8) << R_PAR0_CONFIG__ibusy__BITNR) | \
+ (R_PAR0_CONFIG__ifault__##f9##__VAL(R_PAR0_CONFIG_, ifault_, v9) << R_PAR0_CONFIG__ifault__BITNR) | \
+ (R_PAR0_CONFIG__isel__##f10##__VAL(R_PAR0_CONFIG_, isel_, v10) << R_PAR0_CONFIG__isel__BITNR) | \
+ (R_PAR0_CONFIG__ext_mode__##f11##__VAL(R_PAR0_CONFIG_, ext_mode_, v11) << R_PAR0_CONFIG__ext_mode__BITNR) | \
+ (R_PAR0_CONFIG__wide__##f12##__VAL(R_PAR0_CONFIG_, wide_, v12) << R_PAR0_CONFIG__wide__BITNR) | \
+ (R_PAR0_CONFIG__dma__##f13##__VAL(R_PAR0_CONFIG_, dma_, v13) << R_PAR0_CONFIG__dma__BITNR) | \
+ (R_PAR0_CONFIG__rle_in__##f14##__VAL(R_PAR0_CONFIG_, rle_in_, v14) << R_PAR0_CONFIG__rle_in__BITNR) | \
+ (R_PAR0_CONFIG__rle_out__##f15##__VAL(R_PAR0_CONFIG_, rle_out_, v15) << R_PAR0_CONFIG__rle_out__BITNR) | \
+ (R_PAR0_CONFIG__enable__##f16##__VAL(R_PAR0_CONFIG_, enable_, v16) << R_PAR0_CONFIG__enable__BITNR) | \
+ (R_PAR0_CONFIG__force__##f17##__VAL(R_PAR0_CONFIG_, force_, v17) << R_PAR0_CONFIG__force__BITNR) | \
+ (R_PAR0_CONFIG__ign_ack__##f18##__VAL(R_PAR0_CONFIG_, ign_ack_, v18) << R_PAR0_CONFIG__ign_ack__BITNR) | \
+ (R_PAR0_CONFIG__oe_ack__##f19##__VAL(R_PAR0_CONFIG_, oe_ack_, v19) << R_PAR0_CONFIG__oe_ack__BITNR) | \
+ (R_PAR0_CONFIG__mode__##f20##__VAL(R_PAR0_CONFIG_, mode_, v20) << R_PAR0_CONFIG__mode__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20) ( \
+ (R_PAR0_CONFIG__ioe__##f1_##_VAL(R_PAR0_CONFIG_, ioe_, v1) << R_PAR0_CONFIG__ioe__BITNR) | \
+ (R_PAR0_CONFIG__iseli__##f2_##_VAL(R_PAR0_CONFIG_, iseli_, v2) << R_PAR0_CONFIG__iseli__BITNR) | \
+ (R_PAR0_CONFIG__iautofd__##f3_##_VAL(R_PAR0_CONFIG_, iautofd_, v3) << R_PAR0_CONFIG__iautofd__BITNR) | \
+ (R_PAR0_CONFIG__istrb__##f4_##_VAL(R_PAR0_CONFIG_, istrb_, v4) << R_PAR0_CONFIG__istrb__BITNR) | \
+ (R_PAR0_CONFIG__iinit__##f5_##_VAL(R_PAR0_CONFIG_, iinit_, v5) << R_PAR0_CONFIG__iinit__BITNR) | \
+ (R_PAR0_CONFIG__iperr__##f6_##_VAL(R_PAR0_CONFIG_, iperr_, v6) << R_PAR0_CONFIG__iperr__BITNR) | \
+ (R_PAR0_CONFIG__iack__##f7_##_VAL(R_PAR0_CONFIG_, iack_, v7) << R_PAR0_CONFIG__iack__BITNR) | \
+ (R_PAR0_CONFIG__ibusy__##f8_##_VAL(R_PAR0_CONFIG_, ibusy_, v8) << R_PAR0_CONFIG__ibusy__BITNR) | \
+ (R_PAR0_CONFIG__ifault__##f9_##_VAL(R_PAR0_CONFIG_, ifault_, v9) << R_PAR0_CONFIG__ifault__BITNR) | \
+ (R_PAR0_CONFIG__isel__##f10_##_VAL(R_PAR0_CONFIG_, isel_, v10) << R_PAR0_CONFIG__isel__BITNR) | \
+ (R_PAR0_CONFIG__ext_mode__##f11_##_VAL(R_PAR0_CONFIG_, ext_mode_, v11) << R_PAR0_CONFIG__ext_mode__BITNR) | \
+ (R_PAR0_CONFIG__wide__##f12_##_VAL(R_PAR0_CONFIG_, wide_, v12) << R_PAR0_CONFIG__wide__BITNR) | \
+ (R_PAR0_CONFIG__dma__##f13_##_VAL(R_PAR0_CONFIG_, dma_, v13) << R_PAR0_CONFIG__dma__BITNR) | \
+ (R_PAR0_CONFIG__rle_in__##f14_##_VAL(R_PAR0_CONFIG_, rle_in_, v14) << R_PAR0_CONFIG__rle_in__BITNR) | \
+ (R_PAR0_CONFIG__rle_out__##f15_##_VAL(R_PAR0_CONFIG_, rle_out_, v15) << R_PAR0_CONFIG__rle_out__BITNR) | \
+ (R_PAR0_CONFIG__enable__##f16_##_VAL(R_PAR0_CONFIG_, enable_, v16) << R_PAR0_CONFIG__enable__BITNR) | \
+ (R_PAR0_CONFIG__force__##f17_##_VAL(R_PAR0_CONFIG_, force_, v17) << R_PAR0_CONFIG__force__BITNR) | \
+ (R_PAR0_CONFIG__ign_ack__##f18_##_VAL(R_PAR0_CONFIG_, ign_ack_, v18) << R_PAR0_CONFIG__ign_ack__BITNR) | \
+ (R_PAR0_CONFIG__oe_ack__##f19_##_VAL(R_PAR0_CONFIG_, oe_ack_, v19) << R_PAR0_CONFIG__oe_ack__BITNR) | \
+ (R_PAR0_CONFIG__mode__##f20_##_VAL(R_PAR0_CONFIG_, mode_, v20) << R_PAR0_CONFIG__mode__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR0_CTRL
+ * - type: WO
+ * - addr: 0xb0000042
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR0_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR0_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR0_CTRL(f1,v1) ( \
+ *R_PAR0_CTRL__SADDR = ( \
+ REG_INITIATED(R_PAR0_CTRL_) \
+ REG_VAL__R_PAR0_CTRL_(f1##_,v1) \
+ ), \
+ R_PAR0_CTRL__WRITE(R_PAR0_CTRL__ADDR, *R_PAR0_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR0_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR0_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PAR0_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR0_CTRL__SHADOW(f1,v1) ( \
+ *R_PAR0_CTRL__SADDR = ( \
+ REG_INITIATED(R_PAR0_CTRL_) \
+ REG_VAL__R_PAR0_CTRL_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR0_CTRL(f1,v1) ( \
+ (R_PAR0_CTRL__ctrl__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_CTRL(f1,v1) ( \
+ (R_PAR0_CTRL__ctrl__##f1##__VAL(R_PAR0_CTRL_, ctrl_, v1) << R_PAR0_CTRL__ctrl__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_CTRL_(f1_,v1) ( \
+ (R_PAR0_CTRL__ctrl__##f1_##_VAL(R_PAR0_CTRL_, ctrl_, v1) << R_PAR0_CTRL__ctrl__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR0_CTRL_DATA
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR0_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR0_CTRL_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR0_CTRL_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR0_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PAR0_CTRL_DATA__SADDR = ( \
+ REG_INITIATED(R_PAR0_CTRL_DATA_) \
+ REG_VAL__R_PAR0_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_PAR0_CTRL_DATA__WRITE(R_PAR0_CTRL_DATA__ADDR, *R_PAR0_CTRL_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR0_CTRL_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR0_CTRL_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PAR0_CTRL_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR0_CTRL_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PAR0_CTRL_DATA__SADDR = ( \
+ REG_INITIATED(R_PAR0_CTRL_DATA_) \
+ REG_VAL__R_PAR0_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR0_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR0_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PAR0_CTRL_DATA__peri_int__##f1##__MASK & REG__##v1) | \
+ (R_PAR0_CTRL_DATA__oe__##f2##__MASK & REG__##v2) | \
+ (R_PAR0_CTRL_DATA__seli__##f3##__MASK & REG__##v3) | \
+ (R_PAR0_CTRL_DATA__autofd__##f4##__MASK & REG__##v4) | \
+ (R_PAR0_CTRL_DATA__strb__##f5##__MASK & REG__##v5) | \
+ (R_PAR0_CTRL_DATA__init__##f6##__MASK & REG__##v6) | \
+ (R_PAR0_CTRL_DATA__ecp_cmd__##f7##__MASK & REG__##v7) | \
+ (R_PAR0_CTRL_DATA__data__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_CTRL_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PAR0_CTRL_DATA__peri_int__##f1##__VAL(R_PAR0_CTRL_DATA_, peri_int_, v1) << R_PAR0_CTRL_DATA__peri_int__BITNR) | \
+ (R_PAR0_CTRL_DATA__oe__##f2##__VAL(R_PAR0_CTRL_DATA_, oe_, v2) << R_PAR0_CTRL_DATA__oe__BITNR) | \
+ (R_PAR0_CTRL_DATA__seli__##f3##__VAL(R_PAR0_CTRL_DATA_, seli_, v3) << R_PAR0_CTRL_DATA__seli__BITNR) | \
+ (R_PAR0_CTRL_DATA__autofd__##f4##__VAL(R_PAR0_CTRL_DATA_, autofd_, v4) << R_PAR0_CTRL_DATA__autofd__BITNR) | \
+ (R_PAR0_CTRL_DATA__strb__##f5##__VAL(R_PAR0_CTRL_DATA_, strb_, v5) << R_PAR0_CTRL_DATA__strb__BITNR) | \
+ (R_PAR0_CTRL_DATA__init__##f6##__VAL(R_PAR0_CTRL_DATA_, init_, v6) << R_PAR0_CTRL_DATA__init__BITNR) | \
+ (R_PAR0_CTRL_DATA__ecp_cmd__##f7##__VAL(R_PAR0_CTRL_DATA_, ecp_cmd_, v7) << R_PAR0_CTRL_DATA__ecp_cmd__BITNR) | \
+ (R_PAR0_CTRL_DATA__data__##f8##__VAL(R_PAR0_CTRL_DATA_, data_, v8) << R_PAR0_CTRL_DATA__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_CTRL_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_CTRL_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_CTRL_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_PAR0_CTRL_DATA__peri_int__##f1_##_VAL(R_PAR0_CTRL_DATA_, peri_int_, v1) << R_PAR0_CTRL_DATA__peri_int__BITNR) | \
+ (R_PAR0_CTRL_DATA__oe__##f2_##_VAL(R_PAR0_CTRL_DATA_, oe_, v2) << R_PAR0_CTRL_DATA__oe__BITNR) | \
+ (R_PAR0_CTRL_DATA__seli__##f3_##_VAL(R_PAR0_CTRL_DATA_, seli_, v3) << R_PAR0_CTRL_DATA__seli__BITNR) | \
+ (R_PAR0_CTRL_DATA__autofd__##f4_##_VAL(R_PAR0_CTRL_DATA_, autofd_, v4) << R_PAR0_CTRL_DATA__autofd__BITNR) | \
+ (R_PAR0_CTRL_DATA__strb__##f5_##_VAL(R_PAR0_CTRL_DATA_, strb_, v5) << R_PAR0_CTRL_DATA__strb__BITNR) | \
+ (R_PAR0_CTRL_DATA__init__##f6_##_VAL(R_PAR0_CTRL_DATA_, init_, v6) << R_PAR0_CTRL_DATA__init__BITNR) | \
+ (R_PAR0_CTRL_DATA__ecp_cmd__##f7_##_VAL(R_PAR0_CTRL_DATA_, ecp_cmd_, v7) << R_PAR0_CTRL_DATA__ecp_cmd__BITNR) | \
+ (R_PAR0_CTRL_DATA__data__##f8_##_VAL(R_PAR0_CTRL_DATA_, data_, v8) << R_PAR0_CTRL_DATA__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR0_DELAY
+ * - type: WO
+ * - addr: 0xb0000048
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR0_DELAY
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR0_DELAY.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR0_DELAY.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR0_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_PAR0_DELAY__SADDR = ( \
+ REG_INITIATED(R_PAR0_DELAY_) \
+ REG_VAL__R_PAR0_DELAY_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ), \
+ R_PAR0_DELAY__WRITE(R_PAR0_DELAY__ADDR, *R_PAR0_DELAY__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR0_DELAY__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR0_DELAY.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PAR0_DELAY.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR0_DELAY__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_PAR0_DELAY__SADDR = ( \
+ REG_INITIATED(R_PAR0_DELAY_) \
+ REG_VAL__R_PAR0_DELAY_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR0_DELAY
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR0_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_PAR0_DELAY__fine_hold__##f1##__MASK & REG__##v1) | \
+ (R_PAR0_DELAY__hold__##f2##__MASK & REG__##v2) | \
+ (R_PAR0_DELAY__fine_strb__##f3##__MASK & REG__##v3) | \
+ (R_PAR0_DELAY__strobe__##f4##__MASK & REG__##v4) | \
+ (R_PAR0_DELAY__fine_setup__##f5##__MASK & REG__##v5) | \
+ (R_PAR0_DELAY__setup__##f6##__MASK & REG__##v6) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_DELAY
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_DELAY.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_PAR0_DELAY__fine_hold__##f1##__VAL(R_PAR0_DELAY_, fine_hold_, v1) << R_PAR0_DELAY__fine_hold__BITNR) | \
+ (R_PAR0_DELAY__hold__##f2##__VAL(R_PAR0_DELAY_, hold_, v2) << R_PAR0_DELAY__hold__BITNR) | \
+ (R_PAR0_DELAY__fine_strb__##f3##__VAL(R_PAR0_DELAY_, fine_strb_, v3) << R_PAR0_DELAY__fine_strb__BITNR) | \
+ (R_PAR0_DELAY__strobe__##f4##__VAL(R_PAR0_DELAY_, strobe_, v4) << R_PAR0_DELAY__strobe__BITNR) | \
+ (R_PAR0_DELAY__fine_setup__##f5##__VAL(R_PAR0_DELAY_, fine_setup_, v5) << R_PAR0_DELAY__fine_setup__BITNR) | \
+ (R_PAR0_DELAY__setup__##f6##__VAL(R_PAR0_DELAY_, setup_, v6) << R_PAR0_DELAY__setup__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_DELAY_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_DELAY.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_DELAY_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \
+ (R_PAR0_DELAY__fine_hold__##f1_##_VAL(R_PAR0_DELAY_, fine_hold_, v1) << R_PAR0_DELAY__fine_hold__BITNR) | \
+ (R_PAR0_DELAY__hold__##f2_##_VAL(R_PAR0_DELAY_, hold_, v2) << R_PAR0_DELAY__hold__BITNR) | \
+ (R_PAR0_DELAY__fine_strb__##f3_##_VAL(R_PAR0_DELAY_, fine_strb_, v3) << R_PAR0_DELAY__fine_strb__BITNR) | \
+ (R_PAR0_DELAY__strobe__##f4_##_VAL(R_PAR0_DELAY_, strobe_, v4) << R_PAR0_DELAY__strobe__BITNR) | \
+ (R_PAR0_DELAY__fine_setup__##f5_##_VAL(R_PAR0_DELAY_, fine_setup_, v5) << R_PAR0_DELAY__fine_setup__BITNR) | \
+ (R_PAR0_DELAY__setup__##f6_##_VAL(R_PAR0_DELAY_, setup_, v6) << R_PAR0_DELAY__setup__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR0_STATUS
+ * - type: RO
+ * - addr: 0xb0000042
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR0_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_PAR0_STATUS__mode__##f1##__MASK & REG__##v1) | \
+ (R_PAR0_STATUS__perr__##f2##__MASK & REG__##v2) | \
+ (R_PAR0_STATUS__ack__##f3##__MASK & REG__##v3) | \
+ (R_PAR0_STATUS__busy__##f4##__MASK & REG__##v4) | \
+ (R_PAR0_STATUS__fault__##f5##__MASK & REG__##v5) | \
+ (R_PAR0_STATUS__sel__##f6##__MASK & REG__##v6) | \
+ (R_PAR0_STATUS__ext_mode__##f7##__MASK & REG__##v7) | \
+ (R_PAR0_STATUS__ecp_16__##f8##__MASK & REG__##v8) | \
+ (R_PAR0_STATUS__tr_rdy__##f9##__MASK & REG__##v9) | \
+ (R_PAR0_STATUS__dav__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_PAR0_STATUS__mode__##f1##__VAL(R_PAR0_STATUS_, mode_, v1) << R_PAR0_STATUS__mode__BITNR) | \
+ (R_PAR0_STATUS__perr__##f2##__VAL(R_PAR0_STATUS_, perr_, v2) << R_PAR0_STATUS__perr__BITNR) | \
+ (R_PAR0_STATUS__ack__##f3##__VAL(R_PAR0_STATUS_, ack_, v3) << R_PAR0_STATUS__ack__BITNR) | \
+ (R_PAR0_STATUS__busy__##f4##__VAL(R_PAR0_STATUS_, busy_, v4) << R_PAR0_STATUS__busy__BITNR) | \
+ (R_PAR0_STATUS__fault__##f5##__VAL(R_PAR0_STATUS_, fault_, v5) << R_PAR0_STATUS__fault__BITNR) | \
+ (R_PAR0_STATUS__sel__##f6##__VAL(R_PAR0_STATUS_, sel_, v6) << R_PAR0_STATUS__sel__BITNR) | \
+ (R_PAR0_STATUS__ext_mode__##f7##__VAL(R_PAR0_STATUS_, ext_mode_, v7) << R_PAR0_STATUS__ext_mode__BITNR) | \
+ (R_PAR0_STATUS__ecp_16__##f8##__VAL(R_PAR0_STATUS_, ecp_16_, v8) << R_PAR0_STATUS__ecp_16__BITNR) | \
+ (R_PAR0_STATUS__tr_rdy__##f9##__VAL(R_PAR0_STATUS_, tr_rdy_, v9) << R_PAR0_STATUS__tr_rdy__BITNR) | \
+ (R_PAR0_STATUS__dav__##f10##__VAL(R_PAR0_STATUS_, dav_, v10) << R_PAR0_STATUS__dav__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_PAR0_STATUS__mode__##f1_##_VAL(R_PAR0_STATUS_, mode_, v1) << R_PAR0_STATUS__mode__BITNR) | \
+ (R_PAR0_STATUS__perr__##f2_##_VAL(R_PAR0_STATUS_, perr_, v2) << R_PAR0_STATUS__perr__BITNR) | \
+ (R_PAR0_STATUS__ack__##f3_##_VAL(R_PAR0_STATUS_, ack_, v3) << R_PAR0_STATUS__ack__BITNR) | \
+ (R_PAR0_STATUS__busy__##f4_##_VAL(R_PAR0_STATUS_, busy_, v4) << R_PAR0_STATUS__busy__BITNR) | \
+ (R_PAR0_STATUS__fault__##f5_##_VAL(R_PAR0_STATUS_, fault_, v5) << R_PAR0_STATUS__fault__BITNR) | \
+ (R_PAR0_STATUS__sel__##f6_##_VAL(R_PAR0_STATUS_, sel_, v6) << R_PAR0_STATUS__sel__BITNR) | \
+ (R_PAR0_STATUS__ext_mode__##f7_##_VAL(R_PAR0_STATUS_, ext_mode_, v7) << R_PAR0_STATUS__ext_mode__BITNR) | \
+ (R_PAR0_STATUS__ecp_16__##f8_##_VAL(R_PAR0_STATUS_, ecp_16_, v8) << R_PAR0_STATUS__ecp_16__BITNR) | \
+ (R_PAR0_STATUS__tr_rdy__##f9_##_VAL(R_PAR0_STATUS_, tr_rdy_, v9) << R_PAR0_STATUS__tr_rdy__BITNR) | \
+ (R_PAR0_STATUS__dav__##f10_##_VAL(R_PAR0_STATUS_, dav_, v10) << R_PAR0_STATUS__dav__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR0_STATUS_DATA
+ * - type: RO
+ * - addr: 0xb0000040
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR0_STATUS_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR0_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_PAR0_STATUS_DATA__mode__##f1##__MASK & REG__##v1) | \
+ (R_PAR0_STATUS_DATA__perr__##f2##__MASK & REG__##v2) | \
+ (R_PAR0_STATUS_DATA__ack__##f3##__MASK & REG__##v3) | \
+ (R_PAR0_STATUS_DATA__busy__##f4##__MASK & REG__##v4) | \
+ (R_PAR0_STATUS_DATA__fault__##f5##__MASK & REG__##v5) | \
+ (R_PAR0_STATUS_DATA__sel__##f6##__MASK & REG__##v6) | \
+ (R_PAR0_STATUS_DATA__ext_mode__##f7##__MASK & REG__##v7) | \
+ (R_PAR0_STATUS_DATA__ecp_16__##f8##__MASK & REG__##v8) | \
+ (R_PAR0_STATUS_DATA__tr_rdy__##f9##__MASK & REG__##v9) | \
+ (R_PAR0_STATUS_DATA__dav__##f10##__MASK & REG__##v10) | \
+ (R_PAR0_STATUS_DATA__ecp_cmd__##f11##__MASK & REG__##v11) | \
+ (R_PAR0_STATUS_DATA__data__##f12##__MASK & REG__##v12) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_STATUS_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_STATUS_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_PAR0_STATUS_DATA__mode__##f1##__VAL(R_PAR0_STATUS_DATA_, mode_, v1) << R_PAR0_STATUS_DATA__mode__BITNR) | \
+ (R_PAR0_STATUS_DATA__perr__##f2##__VAL(R_PAR0_STATUS_DATA_, perr_, v2) << R_PAR0_STATUS_DATA__perr__BITNR) | \
+ (R_PAR0_STATUS_DATA__ack__##f3##__VAL(R_PAR0_STATUS_DATA_, ack_, v3) << R_PAR0_STATUS_DATA__ack__BITNR) | \
+ (R_PAR0_STATUS_DATA__busy__##f4##__VAL(R_PAR0_STATUS_DATA_, busy_, v4) << R_PAR0_STATUS_DATA__busy__BITNR) | \
+ (R_PAR0_STATUS_DATA__fault__##f5##__VAL(R_PAR0_STATUS_DATA_, fault_, v5) << R_PAR0_STATUS_DATA__fault__BITNR) | \
+ (R_PAR0_STATUS_DATA__sel__##f6##__VAL(R_PAR0_STATUS_DATA_, sel_, v6) << R_PAR0_STATUS_DATA__sel__BITNR) | \
+ (R_PAR0_STATUS_DATA__ext_mode__##f7##__VAL(R_PAR0_STATUS_DATA_, ext_mode_, v7) << R_PAR0_STATUS_DATA__ext_mode__BITNR) | \
+ (R_PAR0_STATUS_DATA__ecp_16__##f8##__VAL(R_PAR0_STATUS_DATA_, ecp_16_, v8) << R_PAR0_STATUS_DATA__ecp_16__BITNR) | \
+ (R_PAR0_STATUS_DATA__tr_rdy__##f9##__VAL(R_PAR0_STATUS_DATA_, tr_rdy_, v9) << R_PAR0_STATUS_DATA__tr_rdy__BITNR) | \
+ (R_PAR0_STATUS_DATA__dav__##f10##__VAL(R_PAR0_STATUS_DATA_, dav_, v10) << R_PAR0_STATUS_DATA__dav__BITNR) | \
+ (R_PAR0_STATUS_DATA__ecp_cmd__##f11##__VAL(R_PAR0_STATUS_DATA_, ecp_cmd_, v11) << R_PAR0_STATUS_DATA__ecp_cmd__BITNR) | \
+ (R_PAR0_STATUS_DATA__data__##f12##__VAL(R_PAR0_STATUS_DATA_, data_, v12) << R_PAR0_STATUS_DATA__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR0_STATUS_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR0_STATUS_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR0_STATUS_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \
+ (R_PAR0_STATUS_DATA__mode__##f1_##_VAL(R_PAR0_STATUS_DATA_, mode_, v1) << R_PAR0_STATUS_DATA__mode__BITNR) | \
+ (R_PAR0_STATUS_DATA__perr__##f2_##_VAL(R_PAR0_STATUS_DATA_, perr_, v2) << R_PAR0_STATUS_DATA__perr__BITNR) | \
+ (R_PAR0_STATUS_DATA__ack__##f3_##_VAL(R_PAR0_STATUS_DATA_, ack_, v3) << R_PAR0_STATUS_DATA__ack__BITNR) | \
+ (R_PAR0_STATUS_DATA__busy__##f4_##_VAL(R_PAR0_STATUS_DATA_, busy_, v4) << R_PAR0_STATUS_DATA__busy__BITNR) | \
+ (R_PAR0_STATUS_DATA__fault__##f5_##_VAL(R_PAR0_STATUS_DATA_, fault_, v5) << R_PAR0_STATUS_DATA__fault__BITNR) | \
+ (R_PAR0_STATUS_DATA__sel__##f6_##_VAL(R_PAR0_STATUS_DATA_, sel_, v6) << R_PAR0_STATUS_DATA__sel__BITNR) | \
+ (R_PAR0_STATUS_DATA__ext_mode__##f7_##_VAL(R_PAR0_STATUS_DATA_, ext_mode_, v7) << R_PAR0_STATUS_DATA__ext_mode__BITNR) | \
+ (R_PAR0_STATUS_DATA__ecp_16__##f8_##_VAL(R_PAR0_STATUS_DATA_, ecp_16_, v8) << R_PAR0_STATUS_DATA__ecp_16__BITNR) | \
+ (R_PAR0_STATUS_DATA__tr_rdy__##f9_##_VAL(R_PAR0_STATUS_DATA_, tr_rdy_, v9) << R_PAR0_STATUS_DATA__tr_rdy__BITNR) | \
+ (R_PAR0_STATUS_DATA__dav__##f10_##_VAL(R_PAR0_STATUS_DATA_, dav_, v10) << R_PAR0_STATUS_DATA__dav__BITNR) | \
+ (R_PAR0_STATUS_DATA__ecp_cmd__##f11_##_VAL(R_PAR0_STATUS_DATA_, ecp_cmd_, v11) << R_PAR0_STATUS_DATA__ecp_cmd__BITNR) | \
+ (R_PAR0_STATUS_DATA__data__##f12_##_VAL(R_PAR0_STATUS_DATA_, data_, v12) << R_PAR0_STATUS_DATA__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR1_CONFIG
+ * - type: WO
+ * - addr: 0xb0000054
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR1_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR1_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR1_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR1_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_PAR1_CONFIG__SADDR = ( \
+ REG_INITIATED(R_PAR1_CONFIG_) \
+ REG_VAL__R_PAR1_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ), \
+ R_PAR1_CONFIG__WRITE(R_PAR1_CONFIG__ADDR, *R_PAR1_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR1_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR1_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PAR1_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR1_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_PAR1_CONFIG__SADDR = ( \
+ REG_INITIATED(R_PAR1_CONFIG_) \
+ REG_VAL__R_PAR1_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR1_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR1_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_PAR1_CONFIG__ioe__##f1##__MASK & REG__##v1) | \
+ (R_PAR1_CONFIG__iseli__##f2##__MASK & REG__##v2) | \
+ (R_PAR1_CONFIG__iautofd__##f3##__MASK & REG__##v3) | \
+ (R_PAR1_CONFIG__istrb__##f4##__MASK & REG__##v4) | \
+ (R_PAR1_CONFIG__iinit__##f5##__MASK & REG__##v5) | \
+ (R_PAR1_CONFIG__iperr__##f6##__MASK & REG__##v6) | \
+ (R_PAR1_CONFIG__iack__##f7##__MASK & REG__##v7) | \
+ (R_PAR1_CONFIG__ibusy__##f8##__MASK & REG__##v8) | \
+ (R_PAR1_CONFIG__ifault__##f9##__MASK & REG__##v9) | \
+ (R_PAR1_CONFIG__isel__##f10##__MASK & REG__##v10) | \
+ (R_PAR1_CONFIG__ext_mode__##f11##__MASK & REG__##v11) | \
+ (R_PAR1_CONFIG__dma__##f12##__MASK & REG__##v12) | \
+ (R_PAR1_CONFIG__rle_in__##f13##__MASK & REG__##v13) | \
+ (R_PAR1_CONFIG__rle_out__##f14##__MASK & REG__##v14) | \
+ (R_PAR1_CONFIG__enable__##f15##__MASK & REG__##v15) | \
+ (R_PAR1_CONFIG__force__##f16##__MASK & REG__##v16) | \
+ (R_PAR1_CONFIG__ign_ack__##f17##__MASK & REG__##v17) | \
+ (R_PAR1_CONFIG__oe_ack__##f18##__MASK & REG__##v18) | \
+ (R_PAR1_CONFIG__mode__##f19##__MASK & REG__##v19) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_PAR1_CONFIG__ioe__##f1##__VAL(R_PAR1_CONFIG_, ioe_, v1) << R_PAR1_CONFIG__ioe__BITNR) | \
+ (R_PAR1_CONFIG__iseli__##f2##__VAL(R_PAR1_CONFIG_, iseli_, v2) << R_PAR1_CONFIG__iseli__BITNR) | \
+ (R_PAR1_CONFIG__iautofd__##f3##__VAL(R_PAR1_CONFIG_, iautofd_, v3) << R_PAR1_CONFIG__iautofd__BITNR) | \
+ (R_PAR1_CONFIG__istrb__##f4##__VAL(R_PAR1_CONFIG_, istrb_, v4) << R_PAR1_CONFIG__istrb__BITNR) | \
+ (R_PAR1_CONFIG__iinit__##f5##__VAL(R_PAR1_CONFIG_, iinit_, v5) << R_PAR1_CONFIG__iinit__BITNR) | \
+ (R_PAR1_CONFIG__iperr__##f6##__VAL(R_PAR1_CONFIG_, iperr_, v6) << R_PAR1_CONFIG__iperr__BITNR) | \
+ (R_PAR1_CONFIG__iack__##f7##__VAL(R_PAR1_CONFIG_, iack_, v7) << R_PAR1_CONFIG__iack__BITNR) | \
+ (R_PAR1_CONFIG__ibusy__##f8##__VAL(R_PAR1_CONFIG_, ibusy_, v8) << R_PAR1_CONFIG__ibusy__BITNR) | \
+ (R_PAR1_CONFIG__ifault__##f9##__VAL(R_PAR1_CONFIG_, ifault_, v9) << R_PAR1_CONFIG__ifault__BITNR) | \
+ (R_PAR1_CONFIG__isel__##f10##__VAL(R_PAR1_CONFIG_, isel_, v10) << R_PAR1_CONFIG__isel__BITNR) | \
+ (R_PAR1_CONFIG__ext_mode__##f11##__VAL(R_PAR1_CONFIG_, ext_mode_, v11) << R_PAR1_CONFIG__ext_mode__BITNR) | \
+ (R_PAR1_CONFIG__dma__##f12##__VAL(R_PAR1_CONFIG_, dma_, v12) << R_PAR1_CONFIG__dma__BITNR) | \
+ (R_PAR1_CONFIG__rle_in__##f13##__VAL(R_PAR1_CONFIG_, rle_in_, v13) << R_PAR1_CONFIG__rle_in__BITNR) | \
+ (R_PAR1_CONFIG__rle_out__##f14##__VAL(R_PAR1_CONFIG_, rle_out_, v14) << R_PAR1_CONFIG__rle_out__BITNR) | \
+ (R_PAR1_CONFIG__enable__##f15##__VAL(R_PAR1_CONFIG_, enable_, v15) << R_PAR1_CONFIG__enable__BITNR) | \
+ (R_PAR1_CONFIG__force__##f16##__VAL(R_PAR1_CONFIG_, force_, v16) << R_PAR1_CONFIG__force__BITNR) | \
+ (R_PAR1_CONFIG__ign_ack__##f17##__VAL(R_PAR1_CONFIG_, ign_ack_, v17) << R_PAR1_CONFIG__ign_ack__BITNR) | \
+ (R_PAR1_CONFIG__oe_ack__##f18##__VAL(R_PAR1_CONFIG_, oe_ack_, v18) << R_PAR1_CONFIG__oe_ack__BITNR) | \
+ (R_PAR1_CONFIG__mode__##f19##__VAL(R_PAR1_CONFIG_, mode_, v19) << R_PAR1_CONFIG__mode__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \
+ (R_PAR1_CONFIG__ioe__##f1_##_VAL(R_PAR1_CONFIG_, ioe_, v1) << R_PAR1_CONFIG__ioe__BITNR) | \
+ (R_PAR1_CONFIG__iseli__##f2_##_VAL(R_PAR1_CONFIG_, iseli_, v2) << R_PAR1_CONFIG__iseli__BITNR) | \
+ (R_PAR1_CONFIG__iautofd__##f3_##_VAL(R_PAR1_CONFIG_, iautofd_, v3) << R_PAR1_CONFIG__iautofd__BITNR) | \
+ (R_PAR1_CONFIG__istrb__##f4_##_VAL(R_PAR1_CONFIG_, istrb_, v4) << R_PAR1_CONFIG__istrb__BITNR) | \
+ (R_PAR1_CONFIG__iinit__##f5_##_VAL(R_PAR1_CONFIG_, iinit_, v5) << R_PAR1_CONFIG__iinit__BITNR) | \
+ (R_PAR1_CONFIG__iperr__##f6_##_VAL(R_PAR1_CONFIG_, iperr_, v6) << R_PAR1_CONFIG__iperr__BITNR) | \
+ (R_PAR1_CONFIG__iack__##f7_##_VAL(R_PAR1_CONFIG_, iack_, v7) << R_PAR1_CONFIG__iack__BITNR) | \
+ (R_PAR1_CONFIG__ibusy__##f8_##_VAL(R_PAR1_CONFIG_, ibusy_, v8) << R_PAR1_CONFIG__ibusy__BITNR) | \
+ (R_PAR1_CONFIG__ifault__##f9_##_VAL(R_PAR1_CONFIG_, ifault_, v9) << R_PAR1_CONFIG__ifault__BITNR) | \
+ (R_PAR1_CONFIG__isel__##f10_##_VAL(R_PAR1_CONFIG_, isel_, v10) << R_PAR1_CONFIG__isel__BITNR) | \
+ (R_PAR1_CONFIG__ext_mode__##f11_##_VAL(R_PAR1_CONFIG_, ext_mode_, v11) << R_PAR1_CONFIG__ext_mode__BITNR) | \
+ (R_PAR1_CONFIG__dma__##f12_##_VAL(R_PAR1_CONFIG_, dma_, v12) << R_PAR1_CONFIG__dma__BITNR) | \
+ (R_PAR1_CONFIG__rle_in__##f13_##_VAL(R_PAR1_CONFIG_, rle_in_, v13) << R_PAR1_CONFIG__rle_in__BITNR) | \
+ (R_PAR1_CONFIG__rle_out__##f14_##_VAL(R_PAR1_CONFIG_, rle_out_, v14) << R_PAR1_CONFIG__rle_out__BITNR) | \
+ (R_PAR1_CONFIG__enable__##f15_##_VAL(R_PAR1_CONFIG_, enable_, v15) << R_PAR1_CONFIG__enable__BITNR) | \
+ (R_PAR1_CONFIG__force__##f16_##_VAL(R_PAR1_CONFIG_, force_, v16) << R_PAR1_CONFIG__force__BITNR) | \
+ (R_PAR1_CONFIG__ign_ack__##f17_##_VAL(R_PAR1_CONFIG_, ign_ack_, v17) << R_PAR1_CONFIG__ign_ack__BITNR) | \
+ (R_PAR1_CONFIG__oe_ack__##f18_##_VAL(R_PAR1_CONFIG_, oe_ack_, v18) << R_PAR1_CONFIG__oe_ack__BITNR) | \
+ (R_PAR1_CONFIG__mode__##f19_##_VAL(R_PAR1_CONFIG_, mode_, v19) << R_PAR1_CONFIG__mode__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR1_CTRL
+ * - type: WO
+ * - addr: 0xb0000052
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR1_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR1_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR1_CTRL(f1,v1) ( \
+ *R_PAR1_CTRL__SADDR = ( \
+ REG_INITIATED(R_PAR1_CTRL_) \
+ REG_VAL__R_PAR1_CTRL_(f1##_,v1) \
+ ), \
+ R_PAR1_CTRL__WRITE(R_PAR1_CTRL__ADDR, *R_PAR1_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR1_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR1_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PAR1_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR1_CTRL__SHADOW(f1,v1) ( \
+ *R_PAR1_CTRL__SADDR = ( \
+ REG_INITIATED(R_PAR1_CTRL_) \
+ REG_VAL__R_PAR1_CTRL_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR1_CTRL(f1,v1) ( \
+ (R_PAR1_CTRL__ctrl__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_CTRL(f1,v1) ( \
+ (R_PAR1_CTRL__ctrl__##f1##__VAL(R_PAR1_CTRL_, ctrl_, v1) << R_PAR1_CTRL__ctrl__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_CTRL_(f1_,v1) ( \
+ (R_PAR1_CTRL__ctrl__##f1_##_VAL(R_PAR1_CTRL_, ctrl_, v1) << R_PAR1_CTRL__ctrl__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR1_CTRL_DATA
+ * - type: WO
+ * - addr: 0xb0000050
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR1_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR1_CTRL_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR1_CTRL_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR1_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PAR1_CTRL_DATA__SADDR = ( \
+ REG_INITIATED(R_PAR1_CTRL_DATA_) \
+ REG_VAL__R_PAR1_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_PAR1_CTRL_DATA__WRITE(R_PAR1_CTRL_DATA__ADDR, *R_PAR1_CTRL_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR1_CTRL_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR1_CTRL_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PAR1_CTRL_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR1_CTRL_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PAR1_CTRL_DATA__SADDR = ( \
+ REG_INITIATED(R_PAR1_CTRL_DATA_) \
+ REG_VAL__R_PAR1_CTRL_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR1_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR1_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PAR1_CTRL_DATA__peri_int__##f1##__MASK & REG__##v1) | \
+ (R_PAR1_CTRL_DATA__oe__##f2##__MASK & REG__##v2) | \
+ (R_PAR1_CTRL_DATA__seli__##f3##__MASK & REG__##v3) | \
+ (R_PAR1_CTRL_DATA__autofd__##f4##__MASK & REG__##v4) | \
+ (R_PAR1_CTRL_DATA__strb__##f5##__MASK & REG__##v5) | \
+ (R_PAR1_CTRL_DATA__init__##f6##__MASK & REG__##v6) | \
+ (R_PAR1_CTRL_DATA__ecp_cmd__##f7##__MASK & REG__##v7) | \
+ (R_PAR1_CTRL_DATA__data__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_CTRL_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_CTRL_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_CTRL_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PAR1_CTRL_DATA__peri_int__##f1##__VAL(R_PAR1_CTRL_DATA_, peri_int_, v1) << R_PAR1_CTRL_DATA__peri_int__BITNR) | \
+ (R_PAR1_CTRL_DATA__oe__##f2##__VAL(R_PAR1_CTRL_DATA_, oe_, v2) << R_PAR1_CTRL_DATA__oe__BITNR) | \
+ (R_PAR1_CTRL_DATA__seli__##f3##__VAL(R_PAR1_CTRL_DATA_, seli_, v3) << R_PAR1_CTRL_DATA__seli__BITNR) | \
+ (R_PAR1_CTRL_DATA__autofd__##f4##__VAL(R_PAR1_CTRL_DATA_, autofd_, v4) << R_PAR1_CTRL_DATA__autofd__BITNR) | \
+ (R_PAR1_CTRL_DATA__strb__##f5##__VAL(R_PAR1_CTRL_DATA_, strb_, v5) << R_PAR1_CTRL_DATA__strb__BITNR) | \
+ (R_PAR1_CTRL_DATA__init__##f6##__VAL(R_PAR1_CTRL_DATA_, init_, v6) << R_PAR1_CTRL_DATA__init__BITNR) | \
+ (R_PAR1_CTRL_DATA__ecp_cmd__##f7##__VAL(R_PAR1_CTRL_DATA_, ecp_cmd_, v7) << R_PAR1_CTRL_DATA__ecp_cmd__BITNR) | \
+ (R_PAR1_CTRL_DATA__data__##f8##__VAL(R_PAR1_CTRL_DATA_, data_, v8) << R_PAR1_CTRL_DATA__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_CTRL_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_CTRL_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_CTRL_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_PAR1_CTRL_DATA__peri_int__##f1_##_VAL(R_PAR1_CTRL_DATA_, peri_int_, v1) << R_PAR1_CTRL_DATA__peri_int__BITNR) | \
+ (R_PAR1_CTRL_DATA__oe__##f2_##_VAL(R_PAR1_CTRL_DATA_, oe_, v2) << R_PAR1_CTRL_DATA__oe__BITNR) | \
+ (R_PAR1_CTRL_DATA__seli__##f3_##_VAL(R_PAR1_CTRL_DATA_, seli_, v3) << R_PAR1_CTRL_DATA__seli__BITNR) | \
+ (R_PAR1_CTRL_DATA__autofd__##f4_##_VAL(R_PAR1_CTRL_DATA_, autofd_, v4) << R_PAR1_CTRL_DATA__autofd__BITNR) | \
+ (R_PAR1_CTRL_DATA__strb__##f5_##_VAL(R_PAR1_CTRL_DATA_, strb_, v5) << R_PAR1_CTRL_DATA__strb__BITNR) | \
+ (R_PAR1_CTRL_DATA__init__##f6_##_VAL(R_PAR1_CTRL_DATA_, init_, v6) << R_PAR1_CTRL_DATA__init__BITNR) | \
+ (R_PAR1_CTRL_DATA__ecp_cmd__##f7_##_VAL(R_PAR1_CTRL_DATA_, ecp_cmd_, v7) << R_PAR1_CTRL_DATA__ecp_cmd__BITNR) | \
+ (R_PAR1_CTRL_DATA__data__##f8_##_VAL(R_PAR1_CTRL_DATA_, data_, v8) << R_PAR1_CTRL_DATA__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR1_DELAY
+ * - type: WO
+ * - addr: 0xb0000058
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR1_DELAY
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR1_DELAY.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR1_DELAY.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR1_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_PAR1_DELAY__SADDR = ( \
+ REG_INITIATED(R_PAR1_DELAY_) \
+ REG_VAL__R_PAR1_DELAY_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ), \
+ R_PAR1_DELAY__WRITE(R_PAR1_DELAY__ADDR, *R_PAR1_DELAY__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR1_DELAY__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR1_DELAY.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PAR1_DELAY.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR1_DELAY__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_PAR1_DELAY__SADDR = ( \
+ REG_INITIATED(R_PAR1_DELAY_) \
+ REG_VAL__R_PAR1_DELAY_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR1_DELAY
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR1_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_PAR1_DELAY__fine_hold__##f1##__MASK & REG__##v1) | \
+ (R_PAR1_DELAY__hold__##f2##__MASK & REG__##v2) | \
+ (R_PAR1_DELAY__fine_strb__##f3##__MASK & REG__##v3) | \
+ (R_PAR1_DELAY__strobe__##f4##__MASK & REG__##v4) | \
+ (R_PAR1_DELAY__fine_setup__##f5##__MASK & REG__##v5) | \
+ (R_PAR1_DELAY__setup__##f6##__MASK & REG__##v6) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_DELAY
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_DELAY.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_DELAY(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_PAR1_DELAY__fine_hold__##f1##__VAL(R_PAR1_DELAY_, fine_hold_, v1) << R_PAR1_DELAY__fine_hold__BITNR) | \
+ (R_PAR1_DELAY__hold__##f2##__VAL(R_PAR1_DELAY_, hold_, v2) << R_PAR1_DELAY__hold__BITNR) | \
+ (R_PAR1_DELAY__fine_strb__##f3##__VAL(R_PAR1_DELAY_, fine_strb_, v3) << R_PAR1_DELAY__fine_strb__BITNR) | \
+ (R_PAR1_DELAY__strobe__##f4##__VAL(R_PAR1_DELAY_, strobe_, v4) << R_PAR1_DELAY__strobe__BITNR) | \
+ (R_PAR1_DELAY__fine_setup__##f5##__VAL(R_PAR1_DELAY_, fine_setup_, v5) << R_PAR1_DELAY__fine_setup__BITNR) | \
+ (R_PAR1_DELAY__setup__##f6##__VAL(R_PAR1_DELAY_, setup_, v6) << R_PAR1_DELAY__setup__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_DELAY_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_DELAY.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_DELAY_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \
+ (R_PAR1_DELAY__fine_hold__##f1_##_VAL(R_PAR1_DELAY_, fine_hold_, v1) << R_PAR1_DELAY__fine_hold__BITNR) | \
+ (R_PAR1_DELAY__hold__##f2_##_VAL(R_PAR1_DELAY_, hold_, v2) << R_PAR1_DELAY__hold__BITNR) | \
+ (R_PAR1_DELAY__fine_strb__##f3_##_VAL(R_PAR1_DELAY_, fine_strb_, v3) << R_PAR1_DELAY__fine_strb__BITNR) | \
+ (R_PAR1_DELAY__strobe__##f4_##_VAL(R_PAR1_DELAY_, strobe_, v4) << R_PAR1_DELAY__strobe__BITNR) | \
+ (R_PAR1_DELAY__fine_setup__##f5_##_VAL(R_PAR1_DELAY_, fine_setup_, v5) << R_PAR1_DELAY__fine_setup__BITNR) | \
+ (R_PAR1_DELAY__setup__##f6_##_VAL(R_PAR1_DELAY_, setup_, v6) << R_PAR1_DELAY__setup__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR1_STATUS
+ * - type: RO
+ * - addr: 0xb0000052
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_PAR1_STATUS__mode__##f1##__MASK & REG__##v1) | \
+ (R_PAR1_STATUS__perr__##f2##__MASK & REG__##v2) | \
+ (R_PAR1_STATUS__ack__##f3##__MASK & REG__##v3) | \
+ (R_PAR1_STATUS__busy__##f4##__MASK & REG__##v4) | \
+ (R_PAR1_STATUS__fault__##f5##__MASK & REG__##v5) | \
+ (R_PAR1_STATUS__sel__##f6##__MASK & REG__##v6) | \
+ (R_PAR1_STATUS__ext_mode__##f7##__MASK & REG__##v7) | \
+ (R_PAR1_STATUS__tr_rdy__##f8##__MASK & REG__##v8) | \
+ (R_PAR1_STATUS__dav__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_PAR1_STATUS__mode__##f1##__VAL(R_PAR1_STATUS_, mode_, v1) << R_PAR1_STATUS__mode__BITNR) | \
+ (R_PAR1_STATUS__perr__##f2##__VAL(R_PAR1_STATUS_, perr_, v2) << R_PAR1_STATUS__perr__BITNR) | \
+ (R_PAR1_STATUS__ack__##f3##__VAL(R_PAR1_STATUS_, ack_, v3) << R_PAR1_STATUS__ack__BITNR) | \
+ (R_PAR1_STATUS__busy__##f4##__VAL(R_PAR1_STATUS_, busy_, v4) << R_PAR1_STATUS__busy__BITNR) | \
+ (R_PAR1_STATUS__fault__##f5##__VAL(R_PAR1_STATUS_, fault_, v5) << R_PAR1_STATUS__fault__BITNR) | \
+ (R_PAR1_STATUS__sel__##f6##__VAL(R_PAR1_STATUS_, sel_, v6) << R_PAR1_STATUS__sel__BITNR) | \
+ (R_PAR1_STATUS__ext_mode__##f7##__VAL(R_PAR1_STATUS_, ext_mode_, v7) << R_PAR1_STATUS__ext_mode__BITNR) | \
+ (R_PAR1_STATUS__tr_rdy__##f8##__VAL(R_PAR1_STATUS_, tr_rdy_, v8) << R_PAR1_STATUS__tr_rdy__BITNR) | \
+ (R_PAR1_STATUS__dav__##f9##__VAL(R_PAR1_STATUS_, dav_, v9) << R_PAR1_STATUS__dav__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_PAR1_STATUS__mode__##f1_##_VAL(R_PAR1_STATUS_, mode_, v1) << R_PAR1_STATUS__mode__BITNR) | \
+ (R_PAR1_STATUS__perr__##f2_##_VAL(R_PAR1_STATUS_, perr_, v2) << R_PAR1_STATUS__perr__BITNR) | \
+ (R_PAR1_STATUS__ack__##f3_##_VAL(R_PAR1_STATUS_, ack_, v3) << R_PAR1_STATUS__ack__BITNR) | \
+ (R_PAR1_STATUS__busy__##f4_##_VAL(R_PAR1_STATUS_, busy_, v4) << R_PAR1_STATUS__busy__BITNR) | \
+ (R_PAR1_STATUS__fault__##f5_##_VAL(R_PAR1_STATUS_, fault_, v5) << R_PAR1_STATUS__fault__BITNR) | \
+ (R_PAR1_STATUS__sel__##f6_##_VAL(R_PAR1_STATUS_, sel_, v6) << R_PAR1_STATUS__sel__BITNR) | \
+ (R_PAR1_STATUS__ext_mode__##f7_##_VAL(R_PAR1_STATUS_, ext_mode_, v7) << R_PAR1_STATUS__ext_mode__BITNR) | \
+ (R_PAR1_STATUS__tr_rdy__##f8_##_VAL(R_PAR1_STATUS_, tr_rdy_, v8) << R_PAR1_STATUS__tr_rdy__BITNR) | \
+ (R_PAR1_STATUS__dav__##f9_##_VAL(R_PAR1_STATUS_, dav_, v9) << R_PAR1_STATUS__dav__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR1_STATUS_DATA
+ * - type: RO
+ * - addr: 0xb0000050
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR1_STATUS_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR1_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ (R_PAR1_STATUS_DATA__mode__##f1##__MASK & REG__##v1) | \
+ (R_PAR1_STATUS_DATA__perr__##f2##__MASK & REG__##v2) | \
+ (R_PAR1_STATUS_DATA__ack__##f3##__MASK & REG__##v3) | \
+ (R_PAR1_STATUS_DATA__busy__##f4##__MASK & REG__##v4) | \
+ (R_PAR1_STATUS_DATA__fault__##f5##__MASK & REG__##v5) | \
+ (R_PAR1_STATUS_DATA__sel__##f6##__MASK & REG__##v6) | \
+ (R_PAR1_STATUS_DATA__ext_mode__##f7##__MASK & REG__##v7) | \
+ (R_PAR1_STATUS_DATA__tr_rdy__##f8##__MASK & REG__##v8) | \
+ (R_PAR1_STATUS_DATA__dav__##f9##__MASK & REG__##v9) | \
+ (R_PAR1_STATUS_DATA__ecp_cmd__##f10##__MASK & REG__##v10) | \
+ (R_PAR1_STATUS_DATA__data__##f11##__MASK & REG__##v11) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_STATUS_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_STATUS_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_STATUS_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ (R_PAR1_STATUS_DATA__mode__##f1##__VAL(R_PAR1_STATUS_DATA_, mode_, v1) << R_PAR1_STATUS_DATA__mode__BITNR) | \
+ (R_PAR1_STATUS_DATA__perr__##f2##__VAL(R_PAR1_STATUS_DATA_, perr_, v2) << R_PAR1_STATUS_DATA__perr__BITNR) | \
+ (R_PAR1_STATUS_DATA__ack__##f3##__VAL(R_PAR1_STATUS_DATA_, ack_, v3) << R_PAR1_STATUS_DATA__ack__BITNR) | \
+ (R_PAR1_STATUS_DATA__busy__##f4##__VAL(R_PAR1_STATUS_DATA_, busy_, v4) << R_PAR1_STATUS_DATA__busy__BITNR) | \
+ (R_PAR1_STATUS_DATA__fault__##f5##__VAL(R_PAR1_STATUS_DATA_, fault_, v5) << R_PAR1_STATUS_DATA__fault__BITNR) | \
+ (R_PAR1_STATUS_DATA__sel__##f6##__VAL(R_PAR1_STATUS_DATA_, sel_, v6) << R_PAR1_STATUS_DATA__sel__BITNR) | \
+ (R_PAR1_STATUS_DATA__ext_mode__##f7##__VAL(R_PAR1_STATUS_DATA_, ext_mode_, v7) << R_PAR1_STATUS_DATA__ext_mode__BITNR) | \
+ (R_PAR1_STATUS_DATA__tr_rdy__##f8##__VAL(R_PAR1_STATUS_DATA_, tr_rdy_, v8) << R_PAR1_STATUS_DATA__tr_rdy__BITNR) | \
+ (R_PAR1_STATUS_DATA__dav__##f9##__VAL(R_PAR1_STATUS_DATA_, dav_, v9) << R_PAR1_STATUS_DATA__dav__BITNR) | \
+ (R_PAR1_STATUS_DATA__ecp_cmd__##f10##__VAL(R_PAR1_STATUS_DATA_, ecp_cmd_, v10) << R_PAR1_STATUS_DATA__ecp_cmd__BITNR) | \
+ (R_PAR1_STATUS_DATA__data__##f11##__VAL(R_PAR1_STATUS_DATA_, data_, v11) << R_PAR1_STATUS_DATA__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR1_STATUS_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR1_STATUS_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR1_STATUS_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11) ( \
+ (R_PAR1_STATUS_DATA__mode__##f1_##_VAL(R_PAR1_STATUS_DATA_, mode_, v1) << R_PAR1_STATUS_DATA__mode__BITNR) | \
+ (R_PAR1_STATUS_DATA__perr__##f2_##_VAL(R_PAR1_STATUS_DATA_, perr_, v2) << R_PAR1_STATUS_DATA__perr__BITNR) | \
+ (R_PAR1_STATUS_DATA__ack__##f3_##_VAL(R_PAR1_STATUS_DATA_, ack_, v3) << R_PAR1_STATUS_DATA__ack__BITNR) | \
+ (R_PAR1_STATUS_DATA__busy__##f4_##_VAL(R_PAR1_STATUS_DATA_, busy_, v4) << R_PAR1_STATUS_DATA__busy__BITNR) | \
+ (R_PAR1_STATUS_DATA__fault__##f5_##_VAL(R_PAR1_STATUS_DATA_, fault_, v5) << R_PAR1_STATUS_DATA__fault__BITNR) | \
+ (R_PAR1_STATUS_DATA__sel__##f6_##_VAL(R_PAR1_STATUS_DATA_, sel_, v6) << R_PAR1_STATUS_DATA__sel__BITNR) | \
+ (R_PAR1_STATUS_DATA__ext_mode__##f7_##_VAL(R_PAR1_STATUS_DATA_, ext_mode_, v7) << R_PAR1_STATUS_DATA__ext_mode__BITNR) | \
+ (R_PAR1_STATUS_DATA__tr_rdy__##f8_##_VAL(R_PAR1_STATUS_DATA_, tr_rdy_, v8) << R_PAR1_STATUS_DATA__tr_rdy__BITNR) | \
+ (R_PAR1_STATUS_DATA__dav__##f9_##_VAL(R_PAR1_STATUS_DATA_, dav_, v9) << R_PAR1_STATUS_DATA__dav__BITNR) | \
+ (R_PAR1_STATUS_DATA__ecp_cmd__##f10_##_VAL(R_PAR1_STATUS_DATA_, ecp_cmd_, v10) << R_PAR1_STATUS_DATA__ecp_cmd__BITNR) | \
+ (R_PAR1_STATUS_DATA__data__##f11_##_VAL(R_PAR1_STATUS_DATA_, data_, v11) << R_PAR1_STATUS_DATA__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PAR_ECP16_DATA
+ * - type: RW
+ * - addr: 0xb0000040
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PAR_ECP16_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PAR_ECP16_DATA.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PAR_ECP16_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PAR_ECP16_DATA(f1,v1) ( \
+ R_PAR_ECP16_DATA__WRITE(R_PAR_ECP16_DATA__ADDR, ( \
+ REG_VAL__R_PAR_ECP16_DATA_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PAR_ECP16_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PAR_ECP16_DATA(f1,v1) ( \
+ (R_PAR_ECP16_DATA__data__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR_ECP16_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR_ECP16_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR_ECP16_DATA(f1,v1) ( \
+ (R_PAR_ECP16_DATA__data__##f1##__VAL(R_PAR_ECP16_DATA_, data_, v1) << R_PAR_ECP16_DATA__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PAR_ECP16_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PAR_ECP16_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PAR_ECP16_DATA_(f1_,v1) ( \
+ (R_PAR_ECP16_DATA__data__##f1_##_VAL(R_PAR_ECP16_DATA_, data_, v1) << R_PAR_ECP16_DATA__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PHY_COUNTERS
+ * - type: RO
+ * - addr: 0xb00000ac
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PHY_COUNTERS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PHY_COUNTERS(f1,v1,f2,v2) ( \
+ (R_PHY_COUNTERS__sqe_test_error__##f1##__MASK & REG__##v1) | \
+ (R_PHY_COUNTERS__carrier_loss__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PHY_COUNTERS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PHY_COUNTERS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PHY_COUNTERS(f1,v1,f2,v2) ( \
+ (R_PHY_COUNTERS__sqe_test_error__##f1##__VAL(R_PHY_COUNTERS_, sqe_test_error_, v1) << R_PHY_COUNTERS__sqe_test_error__BITNR) | \
+ (R_PHY_COUNTERS__carrier_loss__##f2##__VAL(R_PHY_COUNTERS_, carrier_loss_, v2) << R_PHY_COUNTERS__carrier_loss__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PHY_COUNTERS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PHY_COUNTERS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PHY_COUNTERS_(f1_,v1,f2_,v2) ( \
+ (R_PHY_COUNTERS__sqe_test_error__##f1_##_VAL(R_PHY_COUNTERS_, sqe_test_error_, v1) << R_PHY_COUNTERS__sqe_test_error__BITNR) | \
+ (R_PHY_COUNTERS__carrier_loss__##f2_##_VAL(R_PHY_COUNTERS_, carrier_loss_, v2) << R_PHY_COUNTERS__carrier_loss__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_G_DATA
+ * - type: RW
+ * - addr: 0xb0000028
+ * - group: General config registers
+ */
+
+#if USE_GROUP__General_config_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_G_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_G_DATA.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_G_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_G_DATA(f1,v1) ( \
+ R_PORT_G_DATA__WRITE(R_PORT_G_DATA__ADDR, ( \
+ REG_VAL__R_PORT_G_DATA_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_G_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_G_DATA(f1,v1) ( \
+ (R_PORT_G_DATA__data__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_G_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_G_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_G_DATA(f1,v1) ( \
+ (R_PORT_G_DATA__data__##f1##__VAL(R_PORT_G_DATA_, data_, v1) << R_PORT_G_DATA__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_G_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_G_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_G_DATA_(f1_,v1) ( \
+ (R_PORT_G_DATA__data__##f1_##_VAL(R_PORT_G_DATA_, data_, v1) << R_PORT_G_DATA__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PA_DATA
+ * - type: WO
+ * - addr: 0xb0000030
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PA_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PA_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_PA_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PA_DATA(f1,v1) ( \
+ *R_PORT_PA_DATA__SADDR = ( \
+ REG_INITIATED(R_PORT_PA_DATA_) \
+ REG_VAL__R_PORT_PA_DATA_(f1##_,v1) \
+ ), \
+ R_PORT_PA_DATA__WRITE(R_PORT_PA_DATA__ADDR, *R_PORT_PA_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PA_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PA_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PORT_PA_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PA_DATA__SHADOW(f1,v1) ( \
+ *R_PORT_PA_DATA__SADDR = ( \
+ REG_INITIATED(R_PORT_PA_DATA_) \
+ REG_VAL__R_PORT_PA_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PA_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PA_DATA(f1,v1) ( \
+ (R_PORT_PA_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PA_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PA_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PA_DATA(f1,v1) ( \
+ (R_PORT_PA_DATA__data_out__##f1##__VAL(R_PORT_PA_DATA_, data_out_, v1) << R_PORT_PA_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PA_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PA_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PA_DATA_(f1_,v1) ( \
+ (R_PORT_PA_DATA__data_out__##f1_##_VAL(R_PORT_PA_DATA_, data_out_, v1) << R_PORT_PA_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PA_DIR
+ * - type: WO
+ * - addr: 0xb0000031
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PA_DIR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PA_DIR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_PA_DIR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PA_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PORT_PA_DIR__SADDR = ( \
+ REG_INITIATED(R_PORT_PA_DIR_) \
+ REG_VAL__R_PORT_PA_DIR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_PORT_PA_DIR__WRITE(R_PORT_PA_DIR__ADDR, *R_PORT_PA_DIR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PA_DIR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PA_DIR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PORT_PA_DIR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PA_DIR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PORT_PA_DIR__SADDR = ( \
+ REG_INITIATED(R_PORT_PA_DIR_) \
+ REG_VAL__R_PORT_PA_DIR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PA_DIR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PA_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PORT_PA_DIR__dir7__##f1##__MASK & REG__##v1) | \
+ (R_PORT_PA_DIR__dir6__##f2##__MASK & REG__##v2) | \
+ (R_PORT_PA_DIR__dir5__##f3##__MASK & REG__##v3) | \
+ (R_PORT_PA_DIR__dir4__##f4##__MASK & REG__##v4) | \
+ (R_PORT_PA_DIR__dir3__##f5##__MASK & REG__##v5) | \
+ (R_PORT_PA_DIR__dir2__##f6##__MASK & REG__##v6) | \
+ (R_PORT_PA_DIR__dir1__##f7##__MASK & REG__##v7) | \
+ (R_PORT_PA_DIR__dir0__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PA_DIR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PA_DIR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PA_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PORT_PA_DIR__dir7__##f1##__VAL(R_PORT_PA_DIR_, dir7_, v1) << R_PORT_PA_DIR__dir7__BITNR) | \
+ (R_PORT_PA_DIR__dir6__##f2##__VAL(R_PORT_PA_DIR_, dir6_, v2) << R_PORT_PA_DIR__dir6__BITNR) | \
+ (R_PORT_PA_DIR__dir5__##f3##__VAL(R_PORT_PA_DIR_, dir5_, v3) << R_PORT_PA_DIR__dir5__BITNR) | \
+ (R_PORT_PA_DIR__dir4__##f4##__VAL(R_PORT_PA_DIR_, dir4_, v4) << R_PORT_PA_DIR__dir4__BITNR) | \
+ (R_PORT_PA_DIR__dir3__##f5##__VAL(R_PORT_PA_DIR_, dir3_, v5) << R_PORT_PA_DIR__dir3__BITNR) | \
+ (R_PORT_PA_DIR__dir2__##f6##__VAL(R_PORT_PA_DIR_, dir2_, v6) << R_PORT_PA_DIR__dir2__BITNR) | \
+ (R_PORT_PA_DIR__dir1__##f7##__VAL(R_PORT_PA_DIR_, dir1_, v7) << R_PORT_PA_DIR__dir1__BITNR) | \
+ (R_PORT_PA_DIR__dir0__##f8##__VAL(R_PORT_PA_DIR_, dir0_, v8) << R_PORT_PA_DIR__dir0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PA_DIR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PA_DIR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PA_DIR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_PORT_PA_DIR__dir7__##f1_##_VAL(R_PORT_PA_DIR_, dir7_, v1) << R_PORT_PA_DIR__dir7__BITNR) | \
+ (R_PORT_PA_DIR__dir6__##f2_##_VAL(R_PORT_PA_DIR_, dir6_, v2) << R_PORT_PA_DIR__dir6__BITNR) | \
+ (R_PORT_PA_DIR__dir5__##f3_##_VAL(R_PORT_PA_DIR_, dir5_, v3) << R_PORT_PA_DIR__dir5__BITNR) | \
+ (R_PORT_PA_DIR__dir4__##f4_##_VAL(R_PORT_PA_DIR_, dir4_, v4) << R_PORT_PA_DIR__dir4__BITNR) | \
+ (R_PORT_PA_DIR__dir3__##f5_##_VAL(R_PORT_PA_DIR_, dir3_, v5) << R_PORT_PA_DIR__dir3__BITNR) | \
+ (R_PORT_PA_DIR__dir2__##f6_##_VAL(R_PORT_PA_DIR_, dir2_, v6) << R_PORT_PA_DIR__dir2__BITNR) | \
+ (R_PORT_PA_DIR__dir1__##f7_##_VAL(R_PORT_PA_DIR_, dir1_, v7) << R_PORT_PA_DIR__dir1__BITNR) | \
+ (R_PORT_PA_DIR__dir0__##f8_##_VAL(R_PORT_PA_DIR_, dir0_, v8) << R_PORT_PA_DIR__dir0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PA_READ
+ * - type: RO
+ * - addr: 0xb0000030
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PA_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PA_READ(f1,v1) ( \
+ (R_PORT_PA_READ__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PA_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PA_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PA_READ(f1,v1) ( \
+ (R_PORT_PA_READ__data_in__##f1##__VAL(R_PORT_PA_READ_, data_in_, v1) << R_PORT_PA_READ__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PA_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PA_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PA_READ_(f1_,v1) ( \
+ (R_PORT_PA_READ__data_in__##f1_##_VAL(R_PORT_PA_READ_, data_in_, v1) << R_PORT_PA_READ__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PA_SET
+ * - type: WO
+ * - addr: 0xb0000030
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PA_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PA_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_PA_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PA_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ *R_PORT_PA_SET__SADDR = ( \
+ REG_INITIATED(R_PORT_PA_SET_) \
+ REG_VAL__R_PORT_PA_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \
+ ), \
+ R_PORT_PA_SET__WRITE(R_PORT_PA_SET__ADDR, *R_PORT_PA_SET__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PA_SET__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PA_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PORT_PA_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PA_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ *R_PORT_PA_SET__SADDR = ( \
+ REG_INITIATED(R_PORT_PA_SET_) \
+ REG_VAL__R_PORT_PA_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PA_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PA_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_PORT_PA_SET__dir7__##f1##__MASK & REG__##v1) | \
+ (R_PORT_PA_SET__dir6__##f2##__MASK & REG__##v2) | \
+ (R_PORT_PA_SET__dir5__##f3##__MASK & REG__##v3) | \
+ (R_PORT_PA_SET__dir4__##f4##__MASK & REG__##v4) | \
+ (R_PORT_PA_SET__dir3__##f5##__MASK & REG__##v5) | \
+ (R_PORT_PA_SET__dir2__##f6##__MASK & REG__##v6) | \
+ (R_PORT_PA_SET__dir1__##f7##__MASK & REG__##v7) | \
+ (R_PORT_PA_SET__dir0__##f8##__MASK & REG__##v8) | \
+ (R_PORT_PA_SET__data_out__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PA_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PA_SET.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PA_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_PORT_PA_SET__dir7__##f1##__VAL(R_PORT_PA_SET_, dir7_, v1) << R_PORT_PA_SET__dir7__BITNR) | \
+ (R_PORT_PA_SET__dir6__##f2##__VAL(R_PORT_PA_SET_, dir6_, v2) << R_PORT_PA_SET__dir6__BITNR) | \
+ (R_PORT_PA_SET__dir5__##f3##__VAL(R_PORT_PA_SET_, dir5_, v3) << R_PORT_PA_SET__dir5__BITNR) | \
+ (R_PORT_PA_SET__dir4__##f4##__VAL(R_PORT_PA_SET_, dir4_, v4) << R_PORT_PA_SET__dir4__BITNR) | \
+ (R_PORT_PA_SET__dir3__##f5##__VAL(R_PORT_PA_SET_, dir3_, v5) << R_PORT_PA_SET__dir3__BITNR) | \
+ (R_PORT_PA_SET__dir2__##f6##__VAL(R_PORT_PA_SET_, dir2_, v6) << R_PORT_PA_SET__dir2__BITNR) | \
+ (R_PORT_PA_SET__dir1__##f7##__VAL(R_PORT_PA_SET_, dir1_, v7) << R_PORT_PA_SET__dir1__BITNR) | \
+ (R_PORT_PA_SET__dir0__##f8##__VAL(R_PORT_PA_SET_, dir0_, v8) << R_PORT_PA_SET__dir0__BITNR) | \
+ (R_PORT_PA_SET__data_out__##f9##__VAL(R_PORT_PA_SET_, data_out_, v9) << R_PORT_PA_SET__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PA_SET_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PA_SET.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PA_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_PORT_PA_SET__dir7__##f1_##_VAL(R_PORT_PA_SET_, dir7_, v1) << R_PORT_PA_SET__dir7__BITNR) | \
+ (R_PORT_PA_SET__dir6__##f2_##_VAL(R_PORT_PA_SET_, dir6_, v2) << R_PORT_PA_SET__dir6__BITNR) | \
+ (R_PORT_PA_SET__dir5__##f3_##_VAL(R_PORT_PA_SET_, dir5_, v3) << R_PORT_PA_SET__dir5__BITNR) | \
+ (R_PORT_PA_SET__dir4__##f4_##_VAL(R_PORT_PA_SET_, dir4_, v4) << R_PORT_PA_SET__dir4__BITNR) | \
+ (R_PORT_PA_SET__dir3__##f5_##_VAL(R_PORT_PA_SET_, dir3_, v5) << R_PORT_PA_SET__dir3__BITNR) | \
+ (R_PORT_PA_SET__dir2__##f6_##_VAL(R_PORT_PA_SET_, dir2_, v6) << R_PORT_PA_SET__dir2__BITNR) | \
+ (R_PORT_PA_SET__dir1__##f7_##_VAL(R_PORT_PA_SET_, dir1_, v7) << R_PORT_PA_SET__dir1__BITNR) | \
+ (R_PORT_PA_SET__dir0__##f8_##_VAL(R_PORT_PA_SET_, dir0_, v8) << R_PORT_PA_SET__dir0__BITNR) | \
+ (R_PORT_PA_SET__data_out__##f9_##_VAL(R_PORT_PA_SET_, data_out_, v9) << R_PORT_PA_SET__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PB_CONFIG
+ * - type: WO
+ * - addr: 0xb000003a
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_PB_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PORT_PB_CONFIG__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_CONFIG_) \
+ REG_VAL__R_PORT_PB_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_PORT_PB_CONFIG__WRITE(R_PORT_PB_CONFIG__ADDR, *R_PORT_PB_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PORT_PB_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PORT_PB_CONFIG__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_CONFIG_) \
+ REG_VAL__R_PORT_PB_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PB_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PB_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PORT_PB_CONFIG__cs7__##f1##__MASK & REG__##v1) | \
+ (R_PORT_PB_CONFIG__cs6__##f2##__MASK & REG__##v2) | \
+ (R_PORT_PB_CONFIG__cs5__##f3##__MASK & REG__##v3) | \
+ (R_PORT_PB_CONFIG__cs4__##f4##__MASK & REG__##v4) | \
+ (R_PORT_PB_CONFIG__cs3__##f5##__MASK & REG__##v5) | \
+ (R_PORT_PB_CONFIG__cs2__##f6##__MASK & REG__##v6) | \
+ (R_PORT_PB_CONFIG__scsi1__##f7##__MASK & REG__##v7) | \
+ (R_PORT_PB_CONFIG__scsi0__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PORT_PB_CONFIG__cs7__##f1##__VAL(R_PORT_PB_CONFIG_, cs7_, v1) << R_PORT_PB_CONFIG__cs7__BITNR) | \
+ (R_PORT_PB_CONFIG__cs6__##f2##__VAL(R_PORT_PB_CONFIG_, cs6_, v2) << R_PORT_PB_CONFIG__cs6__BITNR) | \
+ (R_PORT_PB_CONFIG__cs5__##f3##__VAL(R_PORT_PB_CONFIG_, cs5_, v3) << R_PORT_PB_CONFIG__cs5__BITNR) | \
+ (R_PORT_PB_CONFIG__cs4__##f4##__VAL(R_PORT_PB_CONFIG_, cs4_, v4) << R_PORT_PB_CONFIG__cs4__BITNR) | \
+ (R_PORT_PB_CONFIG__cs3__##f5##__VAL(R_PORT_PB_CONFIG_, cs3_, v5) << R_PORT_PB_CONFIG__cs3__BITNR) | \
+ (R_PORT_PB_CONFIG__cs2__##f6##__VAL(R_PORT_PB_CONFIG_, cs2_, v6) << R_PORT_PB_CONFIG__cs2__BITNR) | \
+ (R_PORT_PB_CONFIG__scsi1__##f7##__VAL(R_PORT_PB_CONFIG_, scsi1_, v7) << R_PORT_PB_CONFIG__scsi1__BITNR) | \
+ (R_PORT_PB_CONFIG__scsi0__##f8##__VAL(R_PORT_PB_CONFIG_, scsi0_, v8) << R_PORT_PB_CONFIG__scsi0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_PORT_PB_CONFIG__cs7__##f1_##_VAL(R_PORT_PB_CONFIG_, cs7_, v1) << R_PORT_PB_CONFIG__cs7__BITNR) | \
+ (R_PORT_PB_CONFIG__cs6__##f2_##_VAL(R_PORT_PB_CONFIG_, cs6_, v2) << R_PORT_PB_CONFIG__cs6__BITNR) | \
+ (R_PORT_PB_CONFIG__cs5__##f3_##_VAL(R_PORT_PB_CONFIG_, cs5_, v3) << R_PORT_PB_CONFIG__cs5__BITNR) | \
+ (R_PORT_PB_CONFIG__cs4__##f4_##_VAL(R_PORT_PB_CONFIG_, cs4_, v4) << R_PORT_PB_CONFIG__cs4__BITNR) | \
+ (R_PORT_PB_CONFIG__cs3__##f5_##_VAL(R_PORT_PB_CONFIG_, cs3_, v5) << R_PORT_PB_CONFIG__cs3__BITNR) | \
+ (R_PORT_PB_CONFIG__cs2__##f6_##_VAL(R_PORT_PB_CONFIG_, cs2_, v6) << R_PORT_PB_CONFIG__cs2__BITNR) | \
+ (R_PORT_PB_CONFIG__scsi1__##f7_##_VAL(R_PORT_PB_CONFIG_, scsi1_, v7) << R_PORT_PB_CONFIG__scsi1__BITNR) | \
+ (R_PORT_PB_CONFIG__scsi0__##f8_##_VAL(R_PORT_PB_CONFIG_, scsi0_, v8) << R_PORT_PB_CONFIG__scsi0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PB_DATA
+ * - type: WO
+ * - addr: 0xb0000038
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_PB_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_DATA(f1,v1) ( \
+ *R_PORT_PB_DATA__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_DATA_) \
+ REG_VAL__R_PORT_PB_DATA_(f1##_,v1) \
+ ), \
+ R_PORT_PB_DATA__WRITE(R_PORT_PB_DATA__ADDR, *R_PORT_PB_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PORT_PB_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_DATA__SHADOW(f1,v1) ( \
+ *R_PORT_PB_DATA__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_DATA_) \
+ REG_VAL__R_PORT_PB_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PB_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PB_DATA(f1,v1) ( \
+ (R_PORT_PB_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_DATA(f1,v1) ( \
+ (R_PORT_PB_DATA__data_out__##f1##__VAL(R_PORT_PB_DATA_, data_out_, v1) << R_PORT_PB_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_DATA_(f1_,v1) ( \
+ (R_PORT_PB_DATA__data_out__##f1_##_VAL(R_PORT_PB_DATA_, data_out_, v1) << R_PORT_PB_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PB_DIR
+ * - type: WO
+ * - addr: 0xb0000039
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_DIR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_DIR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_PB_DIR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PORT_PB_DIR__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_DIR_) \
+ REG_VAL__R_PORT_PB_DIR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_PORT_PB_DIR__WRITE(R_PORT_PB_DIR__ADDR, *R_PORT_PB_DIR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_DIR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_DIR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PORT_PB_DIR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_DIR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_PORT_PB_DIR__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_DIR_) \
+ REG_VAL__R_PORT_PB_DIR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PB_DIR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PB_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PORT_PB_DIR__dir7__##f1##__MASK & REG__##v1) | \
+ (R_PORT_PB_DIR__dir6__##f2##__MASK & REG__##v2) | \
+ (R_PORT_PB_DIR__dir5__##f3##__MASK & REG__##v3) | \
+ (R_PORT_PB_DIR__dir4__##f4##__MASK & REG__##v4) | \
+ (R_PORT_PB_DIR__dir3__##f5##__MASK & REG__##v5) | \
+ (R_PORT_PB_DIR__dir2__##f6##__MASK & REG__##v6) | \
+ (R_PORT_PB_DIR__dir1__##f7##__MASK & REG__##v7) | \
+ (R_PORT_PB_DIR__dir0__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_DIR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_DIR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_DIR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_PORT_PB_DIR__dir7__##f1##__VAL(R_PORT_PB_DIR_, dir7_, v1) << R_PORT_PB_DIR__dir7__BITNR) | \
+ (R_PORT_PB_DIR__dir6__##f2##__VAL(R_PORT_PB_DIR_, dir6_, v2) << R_PORT_PB_DIR__dir6__BITNR) | \
+ (R_PORT_PB_DIR__dir5__##f3##__VAL(R_PORT_PB_DIR_, dir5_, v3) << R_PORT_PB_DIR__dir5__BITNR) | \
+ (R_PORT_PB_DIR__dir4__##f4##__VAL(R_PORT_PB_DIR_, dir4_, v4) << R_PORT_PB_DIR__dir4__BITNR) | \
+ (R_PORT_PB_DIR__dir3__##f5##__VAL(R_PORT_PB_DIR_, dir3_, v5) << R_PORT_PB_DIR__dir3__BITNR) | \
+ (R_PORT_PB_DIR__dir2__##f6##__VAL(R_PORT_PB_DIR_, dir2_, v6) << R_PORT_PB_DIR__dir2__BITNR) | \
+ (R_PORT_PB_DIR__dir1__##f7##__VAL(R_PORT_PB_DIR_, dir1_, v7) << R_PORT_PB_DIR__dir1__BITNR) | \
+ (R_PORT_PB_DIR__dir0__##f8##__VAL(R_PORT_PB_DIR_, dir0_, v8) << R_PORT_PB_DIR__dir0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_DIR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_DIR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_DIR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_PORT_PB_DIR__dir7__##f1_##_VAL(R_PORT_PB_DIR_, dir7_, v1) << R_PORT_PB_DIR__dir7__BITNR) | \
+ (R_PORT_PB_DIR__dir6__##f2_##_VAL(R_PORT_PB_DIR_, dir6_, v2) << R_PORT_PB_DIR__dir6__BITNR) | \
+ (R_PORT_PB_DIR__dir5__##f3_##_VAL(R_PORT_PB_DIR_, dir5_, v3) << R_PORT_PB_DIR__dir5__BITNR) | \
+ (R_PORT_PB_DIR__dir4__##f4_##_VAL(R_PORT_PB_DIR_, dir4_, v4) << R_PORT_PB_DIR__dir4__BITNR) | \
+ (R_PORT_PB_DIR__dir3__##f5_##_VAL(R_PORT_PB_DIR_, dir3_, v5) << R_PORT_PB_DIR__dir3__BITNR) | \
+ (R_PORT_PB_DIR__dir2__##f6_##_VAL(R_PORT_PB_DIR_, dir2_, v6) << R_PORT_PB_DIR__dir2__BITNR) | \
+ (R_PORT_PB_DIR__dir1__##f7_##_VAL(R_PORT_PB_DIR_, dir1_, v7) << R_PORT_PB_DIR__dir1__BITNR) | \
+ (R_PORT_PB_DIR__dir0__##f8_##_VAL(R_PORT_PB_DIR_, dir0_, v8) << R_PORT_PB_DIR__dir0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PB_I2C
+ * - type: WO
+ * - addr: 0xb000003b
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_I2C
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_I2C.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_PB_I2C.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_I2C(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_PORT_PB_I2C__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_I2C_) \
+ REG_VAL__R_PORT_PB_I2C_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ), \
+ R_PORT_PB_I2C__WRITE(R_PORT_PB_I2C__ADDR, *R_PORT_PB_I2C__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_I2C__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_I2C.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PORT_PB_I2C.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_I2C__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_PORT_PB_I2C__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_I2C_) \
+ REG_VAL__R_PORT_PB_I2C_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PB_I2C
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PB_I2C(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_PORT_PB_I2C__syncser3__##f1##__MASK & REG__##v1) | \
+ (R_PORT_PB_I2C__syncser1__##f2##__MASK & REG__##v2) | \
+ (R_PORT_PB_I2C__i2c_en__##f3##__MASK & REG__##v3) | \
+ (R_PORT_PB_I2C__i2c_d__##f4##__MASK & REG__##v4) | \
+ (R_PORT_PB_I2C__i2c_clk__##f5##__MASK & REG__##v5) | \
+ (R_PORT_PB_I2C__i2c_oe___##f6##__MASK & REG__##v6) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_I2C
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_I2C.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_I2C(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_PORT_PB_I2C__syncser3__##f1##__VAL(R_PORT_PB_I2C_, syncser3_, v1) << R_PORT_PB_I2C__syncser3__BITNR) | \
+ (R_PORT_PB_I2C__syncser1__##f2##__VAL(R_PORT_PB_I2C_, syncser1_, v2) << R_PORT_PB_I2C__syncser1__BITNR) | \
+ (R_PORT_PB_I2C__i2c_en__##f3##__VAL(R_PORT_PB_I2C_, i2c_en_, v3) << R_PORT_PB_I2C__i2c_en__BITNR) | \
+ (R_PORT_PB_I2C__i2c_d__##f4##__VAL(R_PORT_PB_I2C_, i2c_d_, v4) << R_PORT_PB_I2C__i2c_d__BITNR) | \
+ (R_PORT_PB_I2C__i2c_clk__##f5##__VAL(R_PORT_PB_I2C_, i2c_clk_, v5) << R_PORT_PB_I2C__i2c_clk__BITNR) | \
+ (R_PORT_PB_I2C__i2c_oe___##f6##__VAL(R_PORT_PB_I2C_, i2c_oe__, v6) << R_PORT_PB_I2C__i2c_oe___BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_I2C_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_I2C.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_I2C_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \
+ (R_PORT_PB_I2C__syncser3__##f1_##_VAL(R_PORT_PB_I2C_, syncser3_, v1) << R_PORT_PB_I2C__syncser3__BITNR) | \
+ (R_PORT_PB_I2C__syncser1__##f2_##_VAL(R_PORT_PB_I2C_, syncser1_, v2) << R_PORT_PB_I2C__syncser1__BITNR) | \
+ (R_PORT_PB_I2C__i2c_en__##f3_##_VAL(R_PORT_PB_I2C_, i2c_en_, v3) << R_PORT_PB_I2C__i2c_en__BITNR) | \
+ (R_PORT_PB_I2C__i2c_d__##f4_##_VAL(R_PORT_PB_I2C_, i2c_d_, v4) << R_PORT_PB_I2C__i2c_d__BITNR) | \
+ (R_PORT_PB_I2C__i2c_clk__##f5_##_VAL(R_PORT_PB_I2C_, i2c_clk_, v5) << R_PORT_PB_I2C__i2c_clk__BITNR) | \
+ (R_PORT_PB_I2C__i2c_oe___##f6_##_VAL(R_PORT_PB_I2C_, i2c_oe__, v6) << R_PORT_PB_I2C__i2c_oe___BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PB_READ
+ * - type: RO
+ * - addr: 0xb0000038
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PB_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PB_READ(f1,v1) ( \
+ (R_PORT_PB_READ__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_READ(f1,v1) ( \
+ (R_PORT_PB_READ__data_in__##f1##__VAL(R_PORT_PB_READ_, data_in_, v1) << R_PORT_PB_READ__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_READ_(f1_,v1) ( \
+ (R_PORT_PB_READ__data_in__##f1_##_VAL(R_PORT_PB_READ_, data_in_, v1) << R_PORT_PB_READ__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PORT_PB_SET
+ * - type: WO
+ * - addr: 0xb0000038
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_PORT_PB_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ *R_PORT_PB_SET__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_SET_) \
+ REG_VAL__R_PORT_PB_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \
+ ), \
+ R_PORT_PB_SET__WRITE(R_PORT_PB_SET__ADDR, *R_PORT_PB_SET__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_PORT_PB_SET__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_PORT_PB_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_PORT_PB_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_PORT_PB_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ *R_PORT_PB_SET__SADDR = ( \
+ REG_INITIATED(R_PORT_PB_SET_) \
+ REG_VAL__R_PORT_PB_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PORT_PB_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PORT_PB_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ (R_PORT_PB_SET__syncser3__##f1##__MASK & REG__##v1) | \
+ (R_PORT_PB_SET__syncser1__##f2##__MASK & REG__##v2) | \
+ (R_PORT_PB_SET__i2c_en__##f3##__MASK & REG__##v3) | \
+ (R_PORT_PB_SET__i2c_d__##f4##__MASK & REG__##v4) | \
+ (R_PORT_PB_SET__i2c_clk__##f5##__MASK & REG__##v5) | \
+ (R_PORT_PB_SET__i2c_oe___##f6##__MASK & REG__##v6) | \
+ (R_PORT_PB_SET__cs7__##f7##__MASK & REG__##v7) | \
+ (R_PORT_PB_SET__cs6__##f8##__MASK & REG__##v8) | \
+ (R_PORT_PB_SET__cs5__##f9##__MASK & REG__##v9) | \
+ (R_PORT_PB_SET__cs4__##f10##__MASK & REG__##v10) | \
+ (R_PORT_PB_SET__cs3__##f11##__MASK & REG__##v11) | \
+ (R_PORT_PB_SET__cs2__##f12##__MASK & REG__##v12) | \
+ (R_PORT_PB_SET__scsi1__##f13##__MASK & REG__##v13) | \
+ (R_PORT_PB_SET__scsi0__##f14##__MASK & REG__##v14) | \
+ (R_PORT_PB_SET__dir7__##f15##__MASK & REG__##v15) | \
+ (R_PORT_PB_SET__dir6__##f16##__MASK & REG__##v16) | \
+ (R_PORT_PB_SET__dir5__##f17##__MASK & REG__##v17) | \
+ (R_PORT_PB_SET__dir4__##f18##__MASK & REG__##v18) | \
+ (R_PORT_PB_SET__dir3__##f19##__MASK & REG__##v19) | \
+ (R_PORT_PB_SET__dir2__##f20##__MASK & REG__##v20) | \
+ (R_PORT_PB_SET__dir1__##f21##__MASK & REG__##v21) | \
+ (R_PORT_PB_SET__dir0__##f22##__MASK & REG__##v22) | \
+ (R_PORT_PB_SET__data_out__##f23##__MASK & REG__##v23) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_SET.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ (R_PORT_PB_SET__syncser3__##f1##__VAL(R_PORT_PB_SET_, syncser3_, v1) << R_PORT_PB_SET__syncser3__BITNR) | \
+ (R_PORT_PB_SET__syncser1__##f2##__VAL(R_PORT_PB_SET_, syncser1_, v2) << R_PORT_PB_SET__syncser1__BITNR) | \
+ (R_PORT_PB_SET__i2c_en__##f3##__VAL(R_PORT_PB_SET_, i2c_en_, v3) << R_PORT_PB_SET__i2c_en__BITNR) | \
+ (R_PORT_PB_SET__i2c_d__##f4##__VAL(R_PORT_PB_SET_, i2c_d_, v4) << R_PORT_PB_SET__i2c_d__BITNR) | \
+ (R_PORT_PB_SET__i2c_clk__##f5##__VAL(R_PORT_PB_SET_, i2c_clk_, v5) << R_PORT_PB_SET__i2c_clk__BITNR) | \
+ (R_PORT_PB_SET__i2c_oe___##f6##__VAL(R_PORT_PB_SET_, i2c_oe__, v6) << R_PORT_PB_SET__i2c_oe___BITNR) | \
+ (R_PORT_PB_SET__cs7__##f7##__VAL(R_PORT_PB_SET_, cs7_, v7) << R_PORT_PB_SET__cs7__BITNR) | \
+ (R_PORT_PB_SET__cs6__##f8##__VAL(R_PORT_PB_SET_, cs6_, v8) << R_PORT_PB_SET__cs6__BITNR) | \
+ (R_PORT_PB_SET__cs5__##f9##__VAL(R_PORT_PB_SET_, cs5_, v9) << R_PORT_PB_SET__cs5__BITNR) | \
+ (R_PORT_PB_SET__cs4__##f10##__VAL(R_PORT_PB_SET_, cs4_, v10) << R_PORT_PB_SET__cs4__BITNR) | \
+ (R_PORT_PB_SET__cs3__##f11##__VAL(R_PORT_PB_SET_, cs3_, v11) << R_PORT_PB_SET__cs3__BITNR) | \
+ (R_PORT_PB_SET__cs2__##f12##__VAL(R_PORT_PB_SET_, cs2_, v12) << R_PORT_PB_SET__cs2__BITNR) | \
+ (R_PORT_PB_SET__scsi1__##f13##__VAL(R_PORT_PB_SET_, scsi1_, v13) << R_PORT_PB_SET__scsi1__BITNR) | \
+ (R_PORT_PB_SET__scsi0__##f14##__VAL(R_PORT_PB_SET_, scsi0_, v14) << R_PORT_PB_SET__scsi0__BITNR) | \
+ (R_PORT_PB_SET__dir7__##f15##__VAL(R_PORT_PB_SET_, dir7_, v15) << R_PORT_PB_SET__dir7__BITNR) | \
+ (R_PORT_PB_SET__dir6__##f16##__VAL(R_PORT_PB_SET_, dir6_, v16) << R_PORT_PB_SET__dir6__BITNR) | \
+ (R_PORT_PB_SET__dir5__##f17##__VAL(R_PORT_PB_SET_, dir5_, v17) << R_PORT_PB_SET__dir5__BITNR) | \
+ (R_PORT_PB_SET__dir4__##f18##__VAL(R_PORT_PB_SET_, dir4_, v18) << R_PORT_PB_SET__dir4__BITNR) | \
+ (R_PORT_PB_SET__dir3__##f19##__VAL(R_PORT_PB_SET_, dir3_, v19) << R_PORT_PB_SET__dir3__BITNR) | \
+ (R_PORT_PB_SET__dir2__##f20##__VAL(R_PORT_PB_SET_, dir2_, v20) << R_PORT_PB_SET__dir2__BITNR) | \
+ (R_PORT_PB_SET__dir1__##f21##__VAL(R_PORT_PB_SET_, dir1_, v21) << R_PORT_PB_SET__dir1__BITNR) | \
+ (R_PORT_PB_SET__dir0__##f22##__VAL(R_PORT_PB_SET_, dir0_, v22) << R_PORT_PB_SET__dir0__BITNR) | \
+ (R_PORT_PB_SET__data_out__##f23##__VAL(R_PORT_PB_SET_, data_out_, v23) << R_PORT_PB_SET__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PORT_PB_SET_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PORT_PB_SET.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PORT_PB_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23) ( \
+ (R_PORT_PB_SET__syncser3__##f1_##_VAL(R_PORT_PB_SET_, syncser3_, v1) << R_PORT_PB_SET__syncser3__BITNR) | \
+ (R_PORT_PB_SET__syncser1__##f2_##_VAL(R_PORT_PB_SET_, syncser1_, v2) << R_PORT_PB_SET__syncser1__BITNR) | \
+ (R_PORT_PB_SET__i2c_en__##f3_##_VAL(R_PORT_PB_SET_, i2c_en_, v3) << R_PORT_PB_SET__i2c_en__BITNR) | \
+ (R_PORT_PB_SET__i2c_d__##f4_##_VAL(R_PORT_PB_SET_, i2c_d_, v4) << R_PORT_PB_SET__i2c_d__BITNR) | \
+ (R_PORT_PB_SET__i2c_clk__##f5_##_VAL(R_PORT_PB_SET_, i2c_clk_, v5) << R_PORT_PB_SET__i2c_clk__BITNR) | \
+ (R_PORT_PB_SET__i2c_oe___##f6_##_VAL(R_PORT_PB_SET_, i2c_oe__, v6) << R_PORT_PB_SET__i2c_oe___BITNR) | \
+ (R_PORT_PB_SET__cs7__##f7_##_VAL(R_PORT_PB_SET_, cs7_, v7) << R_PORT_PB_SET__cs7__BITNR) | \
+ (R_PORT_PB_SET__cs6__##f8_##_VAL(R_PORT_PB_SET_, cs6_, v8) << R_PORT_PB_SET__cs6__BITNR) | \
+ (R_PORT_PB_SET__cs5__##f9_##_VAL(R_PORT_PB_SET_, cs5_, v9) << R_PORT_PB_SET__cs5__BITNR) | \
+ (R_PORT_PB_SET__cs4__##f10_##_VAL(R_PORT_PB_SET_, cs4_, v10) << R_PORT_PB_SET__cs4__BITNR) | \
+ (R_PORT_PB_SET__cs3__##f11_##_VAL(R_PORT_PB_SET_, cs3_, v11) << R_PORT_PB_SET__cs3__BITNR) | \
+ (R_PORT_PB_SET__cs2__##f12_##_VAL(R_PORT_PB_SET_, cs2_, v12) << R_PORT_PB_SET__cs2__BITNR) | \
+ (R_PORT_PB_SET__scsi1__##f13_##_VAL(R_PORT_PB_SET_, scsi1_, v13) << R_PORT_PB_SET__scsi1__BITNR) | \
+ (R_PORT_PB_SET__scsi0__##f14_##_VAL(R_PORT_PB_SET_, scsi0_, v14) << R_PORT_PB_SET__scsi0__BITNR) | \
+ (R_PORT_PB_SET__dir7__##f15_##_VAL(R_PORT_PB_SET_, dir7_, v15) << R_PORT_PB_SET__dir7__BITNR) | \
+ (R_PORT_PB_SET__dir6__##f16_##_VAL(R_PORT_PB_SET_, dir6_, v16) << R_PORT_PB_SET__dir6__BITNR) | \
+ (R_PORT_PB_SET__dir5__##f17_##_VAL(R_PORT_PB_SET_, dir5_, v17) << R_PORT_PB_SET__dir5__BITNR) | \
+ (R_PORT_PB_SET__dir4__##f18_##_VAL(R_PORT_PB_SET_, dir4_, v18) << R_PORT_PB_SET__dir4__BITNR) | \
+ (R_PORT_PB_SET__dir3__##f19_##_VAL(R_PORT_PB_SET_, dir3_, v19) << R_PORT_PB_SET__dir3__BITNR) | \
+ (R_PORT_PB_SET__dir2__##f20_##_VAL(R_PORT_PB_SET_, dir2_, v20) << R_PORT_PB_SET__dir2__BITNR) | \
+ (R_PORT_PB_SET__dir1__##f21_##_VAL(R_PORT_PB_SET_, dir1_, v21) << R_PORT_PB_SET__dir1__BITNR) | \
+ (R_PORT_PB_SET__dir0__##f22_##_VAL(R_PORT_PB_SET_, dir0_, v22) << R_PORT_PB_SET__dir0__BITNR) | \
+ (R_PORT_PB_SET__data_out__##f23_##_VAL(R_PORT_PB_SET_, data_out_, v23) << R_PORT_PB_SET__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_PRESCALE_STATUS
+ * - type: RO
+ * - addr: 0xb00000f0
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_PRESCALE_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_PRESCALE_STATUS(f1,v1,f2,v2) ( \
+ (R_PRESCALE_STATUS__ser_status__##f1##__MASK & REG__##v1) | \
+ (R_PRESCALE_STATUS__tim_status__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PRESCALE_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PRESCALE_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_PRESCALE_STATUS(f1,v1,f2,v2) ( \
+ (R_PRESCALE_STATUS__ser_status__##f1##__VAL(R_PRESCALE_STATUS_, ser_status_, v1) << R_PRESCALE_STATUS__ser_status__BITNR) | \
+ (R_PRESCALE_STATUS__tim_status__##f2##__VAL(R_PRESCALE_STATUS_, tim_status_, v2) << R_PRESCALE_STATUS__tim_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_PRESCALE_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_PRESCALE_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_PRESCALE_STATUS_(f1_,v1,f2_,v2) ( \
+ (R_PRESCALE_STATUS__ser_status__##f1_##_VAL(R_PRESCALE_STATUS_, ser_status_, v1) << R_PRESCALE_STATUS__ser_status__BITNR) | \
+ (R_PRESCALE_STATUS__tim_status__##f2_##_VAL(R_PRESCALE_STATUS_, tim_status_, v2) << R_PRESCALE_STATUS__tim_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_REC_COUNTERS
+ * - type: RO
+ * - addr: 0xb00000a4
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_REC_COUNTERS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_REC_COUNTERS(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_REC_COUNTERS__congestion__##f1##__MASK & REG__##v1) | \
+ (R_REC_COUNTERS__oversize__##f2##__MASK & REG__##v2) | \
+ (R_REC_COUNTERS__alignment_error__##f3##__MASK & REG__##v3) | \
+ (R_REC_COUNTERS__crc_error__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_REC_COUNTERS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_REC_COUNTERS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_REC_COUNTERS(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_REC_COUNTERS__congestion__##f1##__VAL(R_REC_COUNTERS_, congestion_, v1) << R_REC_COUNTERS__congestion__BITNR) | \
+ (R_REC_COUNTERS__oversize__##f2##__VAL(R_REC_COUNTERS_, oversize_, v2) << R_REC_COUNTERS__oversize__BITNR) | \
+ (R_REC_COUNTERS__alignment_error__##f3##__VAL(R_REC_COUNTERS_, alignment_error_, v3) << R_REC_COUNTERS__alignment_error__BITNR) | \
+ (R_REC_COUNTERS__crc_error__##f4##__VAL(R_REC_COUNTERS_, crc_error_, v4) << R_REC_COUNTERS__crc_error__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_REC_COUNTERS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_REC_COUNTERS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_REC_COUNTERS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_REC_COUNTERS__congestion__##f1_##_VAL(R_REC_COUNTERS_, congestion_, v1) << R_REC_COUNTERS__congestion__BITNR) | \
+ (R_REC_COUNTERS__oversize__##f2_##_VAL(R_REC_COUNTERS_, oversize_, v2) << R_REC_COUNTERS__oversize__BITNR) | \
+ (R_REC_COUNTERS__alignment_error__##f3_##_VAL(R_REC_COUNTERS_, alignment_error_, v3) << R_REC_COUNTERS__alignment_error__BITNR) | \
+ (R_REC_COUNTERS__crc_error__##f4_##_VAL(R_REC_COUNTERS_, crc_error_, v4) << R_REC_COUNTERS__crc_error__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI0_CMD
+ * - type: WO
+ * - addr: 0xb0000042
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_CMD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI0_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_CMD(f1,v1,f2,v2) ( \
+ *R_SCSI0_CMD__SADDR = ( \
+ REG_INITIATED(R_SCSI0_CMD_) \
+ REG_VAL__R_SCSI0_CMD_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_SCSI0_CMD__WRITE(R_SCSI0_CMD__ADDR, *R_SCSI0_CMD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_CMD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_CMD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI0_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_CMD__SHADOW(f1,v1,f2,v2) ( \
+ *R_SCSI0_CMD__SADDR = ( \
+ REG_INITIATED(R_SCSI0_CMD_) \
+ REG_VAL__R_SCSI0_CMD_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI0_CMD(f1,v1,f2,v2) ( \
+ (R_SCSI0_CMD__asynch_setup__##f1##__MASK & REG__##v1) | \
+ (R_SCSI0_CMD__command__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_CMD(f1,v1,f2,v2) ( \
+ (R_SCSI0_CMD__asynch_setup__##f1##__VAL(R_SCSI0_CMD_, asynch_setup_, v1) << R_SCSI0_CMD__asynch_setup__BITNR) | \
+ (R_SCSI0_CMD__command__##f2##__VAL(R_SCSI0_CMD_, command_, v2) << R_SCSI0_CMD__command__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_CMD_(f1_,v1,f2_,v2) ( \
+ (R_SCSI0_CMD__asynch_setup__##f1_##_VAL(R_SCSI0_CMD_, asynch_setup_, v1) << R_SCSI0_CMD__asynch_setup__BITNR) | \
+ (R_SCSI0_CMD__command__##f2_##_VAL(R_SCSI0_CMD_, command_, v2) << R_SCSI0_CMD__command__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI0_CMD_DATA
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_CMD_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_CMD_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI0_CMD_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_SCSI0_CMD_DATA__SADDR = ( \
+ REG_INITIATED(R_SCSI0_CMD_DATA_) \
+ REG_VAL__R_SCSI0_CMD_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ), \
+ R_SCSI0_CMD_DATA__WRITE(R_SCSI0_CMD_DATA__ADDR, *R_SCSI0_CMD_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_CMD_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_CMD_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI0_CMD_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_CMD_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_SCSI0_CMD_DATA__SADDR = ( \
+ REG_INITIATED(R_SCSI0_CMD_DATA_) \
+ REG_VAL__R_SCSI0_CMD_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI0_CMD_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI0_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_SCSI0_CMD_DATA__parity_in__##f1##__MASK & REG__##v1) | \
+ (R_SCSI0_CMD_DATA__skip__##f2##__MASK & REG__##v2) | \
+ (R_SCSI0_CMD_DATA__clr_status__##f3##__MASK & REG__##v3) | \
+ (R_SCSI0_CMD_DATA__asynch_setup__##f4##__MASK & REG__##v4) | \
+ (R_SCSI0_CMD_DATA__command__##f5##__MASK & REG__##v5) | \
+ (R_SCSI0_CMD_DATA__data_out__##f6##__MASK & REG__##v6) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_CMD_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_CMD_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_SCSI0_CMD_DATA__parity_in__##f1##__VAL(R_SCSI0_CMD_DATA_, parity_in_, v1) << R_SCSI0_CMD_DATA__parity_in__BITNR) | \
+ (R_SCSI0_CMD_DATA__skip__##f2##__VAL(R_SCSI0_CMD_DATA_, skip_, v2) << R_SCSI0_CMD_DATA__skip__BITNR) | \
+ (R_SCSI0_CMD_DATA__clr_status__##f3##__VAL(R_SCSI0_CMD_DATA_, clr_status_, v3) << R_SCSI0_CMD_DATA__clr_status__BITNR) | \
+ (R_SCSI0_CMD_DATA__asynch_setup__##f4##__VAL(R_SCSI0_CMD_DATA_, asynch_setup_, v4) << R_SCSI0_CMD_DATA__asynch_setup__BITNR) | \
+ (R_SCSI0_CMD_DATA__command__##f5##__VAL(R_SCSI0_CMD_DATA_, command_, v5) << R_SCSI0_CMD_DATA__command__BITNR) | \
+ (R_SCSI0_CMD_DATA__data_out__##f6##__VAL(R_SCSI0_CMD_DATA_, data_out_, v6) << R_SCSI0_CMD_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_CMD_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_CMD_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_CMD_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \
+ (R_SCSI0_CMD_DATA__parity_in__##f1_##_VAL(R_SCSI0_CMD_DATA_, parity_in_, v1) << R_SCSI0_CMD_DATA__parity_in__BITNR) | \
+ (R_SCSI0_CMD_DATA__skip__##f2_##_VAL(R_SCSI0_CMD_DATA_, skip_, v2) << R_SCSI0_CMD_DATA__skip__BITNR) | \
+ (R_SCSI0_CMD_DATA__clr_status__##f3_##_VAL(R_SCSI0_CMD_DATA_, clr_status_, v3) << R_SCSI0_CMD_DATA__clr_status__BITNR) | \
+ (R_SCSI0_CMD_DATA__asynch_setup__##f4_##_VAL(R_SCSI0_CMD_DATA_, asynch_setup_, v4) << R_SCSI0_CMD_DATA__asynch_setup__BITNR) | \
+ (R_SCSI0_CMD_DATA__command__##f5_##_VAL(R_SCSI0_CMD_DATA_, command_, v5) << R_SCSI0_CMD_DATA__command__BITNR) | \
+ (R_SCSI0_CMD_DATA__data_out__##f6_##_VAL(R_SCSI0_CMD_DATA_, data_out_, v6) << R_SCSI0_CMD_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI0_CTRL
+ * - type: WO
+ * - addr: 0xb0000044
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI0_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ *R_SCSI0_CTRL__SADDR = ( \
+ REG_INITIATED(R_SCSI0_CTRL_) \
+ REG_VAL__R_SCSI0_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \
+ ), \
+ R_SCSI0_CTRL__WRITE(R_SCSI0_CTRL__ADDR, *R_SCSI0_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI0_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ *R_SCSI0_CTRL__SADDR = ( \
+ REG_INITIATED(R_SCSI0_CTRL_) \
+ REG_VAL__R_SCSI0_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ (R_SCSI0_CTRL__id_type__##f1##__MASK & REG__##v1) | \
+ (R_SCSI0_CTRL__sel_timeout__##f2##__MASK & REG__##v2) | \
+ (R_SCSI0_CTRL__synch_per__##f3##__MASK & REG__##v3) | \
+ (R_SCSI0_CTRL__rst__##f4##__MASK & REG__##v4) | \
+ (R_SCSI0_CTRL__atn__##f5##__MASK & REG__##v5) | \
+ (R_SCSI0_CTRL__my_id__##f6##__MASK & REG__##v6) | \
+ (R_SCSI0_CTRL__target_id__##f7##__MASK & REG__##v7) | \
+ (R_SCSI0_CTRL__fast_20__##f8##__MASK & REG__##v8) | \
+ (R_SCSI0_CTRL__bus_width__##f9##__MASK & REG__##v9) | \
+ (R_SCSI0_CTRL__synch__##f10##__MASK & REG__##v10) | \
+ (R_SCSI0_CTRL__enable__##f11##__MASK & REG__##v11) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ (R_SCSI0_CTRL__id_type__##f1##__VAL(R_SCSI0_CTRL_, id_type_, v1) << R_SCSI0_CTRL__id_type__BITNR) | \
+ (R_SCSI0_CTRL__sel_timeout__##f2##__VAL(R_SCSI0_CTRL_, sel_timeout_, v2) << R_SCSI0_CTRL__sel_timeout__BITNR) | \
+ (R_SCSI0_CTRL__synch_per__##f3##__VAL(R_SCSI0_CTRL_, synch_per_, v3) << R_SCSI0_CTRL__synch_per__BITNR) | \
+ (R_SCSI0_CTRL__rst__##f4##__VAL(R_SCSI0_CTRL_, rst_, v4) << R_SCSI0_CTRL__rst__BITNR) | \
+ (R_SCSI0_CTRL__atn__##f5##__VAL(R_SCSI0_CTRL_, atn_, v5) << R_SCSI0_CTRL__atn__BITNR) | \
+ (R_SCSI0_CTRL__my_id__##f6##__VAL(R_SCSI0_CTRL_, my_id_, v6) << R_SCSI0_CTRL__my_id__BITNR) | \
+ (R_SCSI0_CTRL__target_id__##f7##__VAL(R_SCSI0_CTRL_, target_id_, v7) << R_SCSI0_CTRL__target_id__BITNR) | \
+ (R_SCSI0_CTRL__fast_20__##f8##__VAL(R_SCSI0_CTRL_, fast_20_, v8) << R_SCSI0_CTRL__fast_20__BITNR) | \
+ (R_SCSI0_CTRL__bus_width__##f9##__VAL(R_SCSI0_CTRL_, bus_width_, v9) << R_SCSI0_CTRL__bus_width__BITNR) | \
+ (R_SCSI0_CTRL__synch__##f10##__VAL(R_SCSI0_CTRL_, synch_, v10) << R_SCSI0_CTRL__synch__BITNR) | \
+ (R_SCSI0_CTRL__enable__##f11##__VAL(R_SCSI0_CTRL_, enable_, v11) << R_SCSI0_CTRL__enable__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11) ( \
+ (R_SCSI0_CTRL__id_type__##f1_##_VAL(R_SCSI0_CTRL_, id_type_, v1) << R_SCSI0_CTRL__id_type__BITNR) | \
+ (R_SCSI0_CTRL__sel_timeout__##f2_##_VAL(R_SCSI0_CTRL_, sel_timeout_, v2) << R_SCSI0_CTRL__sel_timeout__BITNR) | \
+ (R_SCSI0_CTRL__synch_per__##f3_##_VAL(R_SCSI0_CTRL_, synch_per_, v3) << R_SCSI0_CTRL__synch_per__BITNR) | \
+ (R_SCSI0_CTRL__rst__##f4_##_VAL(R_SCSI0_CTRL_, rst_, v4) << R_SCSI0_CTRL__rst__BITNR) | \
+ (R_SCSI0_CTRL__atn__##f5_##_VAL(R_SCSI0_CTRL_, atn_, v5) << R_SCSI0_CTRL__atn__BITNR) | \
+ (R_SCSI0_CTRL__my_id__##f6_##_VAL(R_SCSI0_CTRL_, my_id_, v6) << R_SCSI0_CTRL__my_id__BITNR) | \
+ (R_SCSI0_CTRL__target_id__##f7_##_VAL(R_SCSI0_CTRL_, target_id_, v7) << R_SCSI0_CTRL__target_id__BITNR) | \
+ (R_SCSI0_CTRL__fast_20__##f8_##_VAL(R_SCSI0_CTRL_, fast_20_, v8) << R_SCSI0_CTRL__fast_20__BITNR) | \
+ (R_SCSI0_CTRL__bus_width__##f9_##_VAL(R_SCSI0_CTRL_, bus_width_, v9) << R_SCSI0_CTRL__bus_width__BITNR) | \
+ (R_SCSI0_CTRL__synch__##f10_##_VAL(R_SCSI0_CTRL_, synch_, v10) << R_SCSI0_CTRL__synch__BITNR) | \
+ (R_SCSI0_CTRL__enable__##f11_##_VAL(R_SCSI0_CTRL_, enable_, v11) << R_SCSI0_CTRL__enable__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI0_DATA
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI0_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_DATA(f1,v1) ( \
+ *R_SCSI0_DATA__SADDR = ( \
+ REG_INITIATED(R_SCSI0_DATA_) \
+ REG_VAL__R_SCSI0_DATA_(f1##_,v1) \
+ ), \
+ R_SCSI0_DATA__WRITE(R_SCSI0_DATA__ADDR, *R_SCSI0_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI0_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_DATA__SHADOW(f1,v1) ( \
+ *R_SCSI0_DATA__SADDR = ( \
+ REG_INITIATED(R_SCSI0_DATA_) \
+ REG_VAL__R_SCSI0_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI0_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI0_DATA(f1,v1) ( \
+ (R_SCSI0_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_DATA(f1,v1) ( \
+ (R_SCSI0_DATA__data_out__##f1##__VAL(R_SCSI0_DATA_, data_out_, v1) << R_SCSI0_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_DATA_(f1_,v1) ( \
+ (R_SCSI0_DATA__data_out__##f1_##_VAL(R_SCSI0_DATA_, data_out_, v1) << R_SCSI0_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI0_DATA_IN
+ * - type: RO
+ * - addr: 0xb0000040
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI0_DATA_IN
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI0_DATA_IN(f1,v1) ( \
+ (R_SCSI0_DATA_IN__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_DATA_IN
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_DATA_IN.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_DATA_IN(f1,v1) ( \
+ (R_SCSI0_DATA_IN__data_in__##f1##__VAL(R_SCSI0_DATA_IN_, data_in_, v1) << R_SCSI0_DATA_IN__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_DATA_IN_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_DATA_IN.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_DATA_IN_(f1_,v1) ( \
+ (R_SCSI0_DATA_IN__data_in__##f1_##_VAL(R_SCSI0_DATA_IN_, data_in_, v1) << R_SCSI0_DATA_IN__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI0_STATUS
+ * - type: RO
+ * - addr: 0xb0000048
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI0_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_SCSI0_STATUS__tst_arb_won__##f1##__MASK & REG__##v1) | \
+ (R_SCSI0_STATUS__tst_resel__##f2##__MASK & REG__##v2) | \
+ (R_SCSI0_STATUS__parity_error__##f3##__MASK & REG__##v3) | \
+ (R_SCSI0_STATUS__bus_reset__##f4##__MASK & REG__##v4) | \
+ (R_SCSI0_STATUS__resel_target__##f5##__MASK & REG__##v5) | \
+ (R_SCSI0_STATUS__resel__##f6##__MASK & REG__##v6) | \
+ (R_SCSI0_STATUS__curr_phase__##f7##__MASK & REG__##v7) | \
+ (R_SCSI0_STATUS__last_seq_step__##f8##__MASK & REG__##v8) | \
+ (R_SCSI0_STATUS__valid_status__##f9##__MASK & REG__##v9) | \
+ (R_SCSI0_STATUS__seq_status__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_SCSI0_STATUS__tst_arb_won__##f1##__VAL(R_SCSI0_STATUS_, tst_arb_won_, v1) << R_SCSI0_STATUS__tst_arb_won__BITNR) | \
+ (R_SCSI0_STATUS__tst_resel__##f2##__VAL(R_SCSI0_STATUS_, tst_resel_, v2) << R_SCSI0_STATUS__tst_resel__BITNR) | \
+ (R_SCSI0_STATUS__parity_error__##f3##__VAL(R_SCSI0_STATUS_, parity_error_, v3) << R_SCSI0_STATUS__parity_error__BITNR) | \
+ (R_SCSI0_STATUS__bus_reset__##f4##__VAL(R_SCSI0_STATUS_, bus_reset_, v4) << R_SCSI0_STATUS__bus_reset__BITNR) | \
+ (R_SCSI0_STATUS__resel_target__##f5##__VAL(R_SCSI0_STATUS_, resel_target_, v5) << R_SCSI0_STATUS__resel_target__BITNR) | \
+ (R_SCSI0_STATUS__resel__##f6##__VAL(R_SCSI0_STATUS_, resel_, v6) << R_SCSI0_STATUS__resel__BITNR) | \
+ (R_SCSI0_STATUS__curr_phase__##f7##__VAL(R_SCSI0_STATUS_, curr_phase_, v7) << R_SCSI0_STATUS__curr_phase__BITNR) | \
+ (R_SCSI0_STATUS__last_seq_step__##f8##__VAL(R_SCSI0_STATUS_, last_seq_step_, v8) << R_SCSI0_STATUS__last_seq_step__BITNR) | \
+ (R_SCSI0_STATUS__valid_status__##f9##__VAL(R_SCSI0_STATUS_, valid_status_, v9) << R_SCSI0_STATUS__valid_status__BITNR) | \
+ (R_SCSI0_STATUS__seq_status__##f10##__VAL(R_SCSI0_STATUS_, seq_status_, v10) << R_SCSI0_STATUS__seq_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_SCSI0_STATUS__tst_arb_won__##f1_##_VAL(R_SCSI0_STATUS_, tst_arb_won_, v1) << R_SCSI0_STATUS__tst_arb_won__BITNR) | \
+ (R_SCSI0_STATUS__tst_resel__##f2_##_VAL(R_SCSI0_STATUS_, tst_resel_, v2) << R_SCSI0_STATUS__tst_resel__BITNR) | \
+ (R_SCSI0_STATUS__parity_error__##f3_##_VAL(R_SCSI0_STATUS_, parity_error_, v3) << R_SCSI0_STATUS__parity_error__BITNR) | \
+ (R_SCSI0_STATUS__bus_reset__##f4_##_VAL(R_SCSI0_STATUS_, bus_reset_, v4) << R_SCSI0_STATUS__bus_reset__BITNR) | \
+ (R_SCSI0_STATUS__resel_target__##f5_##_VAL(R_SCSI0_STATUS_, resel_target_, v5) << R_SCSI0_STATUS__resel_target__BITNR) | \
+ (R_SCSI0_STATUS__resel__##f6_##_VAL(R_SCSI0_STATUS_, resel_, v6) << R_SCSI0_STATUS__resel__BITNR) | \
+ (R_SCSI0_STATUS__curr_phase__##f7_##_VAL(R_SCSI0_STATUS_, curr_phase_, v7) << R_SCSI0_STATUS__curr_phase__BITNR) | \
+ (R_SCSI0_STATUS__last_seq_step__##f8_##_VAL(R_SCSI0_STATUS_, last_seq_step_, v8) << R_SCSI0_STATUS__last_seq_step__BITNR) | \
+ (R_SCSI0_STATUS__valid_status__##f9_##_VAL(R_SCSI0_STATUS_, valid_status_, v9) << R_SCSI0_STATUS__valid_status__BITNR) | \
+ (R_SCSI0_STATUS__seq_status__##f10_##_VAL(R_SCSI0_STATUS_, seq_status_, v10) << R_SCSI0_STATUS__seq_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI0_STATUS_CTRL
+ * - type: WO
+ * - addr: 0xb0000043
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_STATUS_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_STATUS_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI0_STATUS_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ *R_SCSI0_STATUS_CTRL__SADDR = ( \
+ REG_INITIATED(R_SCSI0_STATUS_CTRL_) \
+ REG_VAL__R_SCSI0_STATUS_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ), \
+ R_SCSI0_STATUS_CTRL__WRITE(R_SCSI0_STATUS_CTRL__ADDR, *R_SCSI0_STATUS_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI0_STATUS_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI0_STATUS_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI0_STATUS_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI0_STATUS_CTRL__SHADOW(f1,v1,f2,v2,f3,v3) ( \
+ *R_SCSI0_STATUS_CTRL__SADDR = ( \
+ REG_INITIATED(R_SCSI0_STATUS_CTRL_) \
+ REG_VAL__R_SCSI0_STATUS_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI0_STATUS_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI0_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ (R_SCSI0_STATUS_CTRL__parity_in__##f1##__MASK & REG__##v1) | \
+ (R_SCSI0_STATUS_CTRL__skip__##f2##__MASK & REG__##v2) | \
+ (R_SCSI0_STATUS_CTRL__clr_status__##f3##__MASK & REG__##v3) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_STATUS_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_STATUS_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ (R_SCSI0_STATUS_CTRL__parity_in__##f1##__VAL(R_SCSI0_STATUS_CTRL_, parity_in_, v1) << R_SCSI0_STATUS_CTRL__parity_in__BITNR) | \
+ (R_SCSI0_STATUS_CTRL__skip__##f2##__VAL(R_SCSI0_STATUS_CTRL_, skip_, v2) << R_SCSI0_STATUS_CTRL__skip__BITNR) | \
+ (R_SCSI0_STATUS_CTRL__clr_status__##f3##__VAL(R_SCSI0_STATUS_CTRL_, clr_status_, v3) << R_SCSI0_STATUS_CTRL__clr_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI0_STATUS_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI0_STATUS_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI0_STATUS_CTRL_(f1_,v1,f2_,v2,f3_,v3) ( \
+ (R_SCSI0_STATUS_CTRL__parity_in__##f1_##_VAL(R_SCSI0_STATUS_CTRL_, parity_in_, v1) << R_SCSI0_STATUS_CTRL__parity_in__BITNR) | \
+ (R_SCSI0_STATUS_CTRL__skip__##f2_##_VAL(R_SCSI0_STATUS_CTRL_, skip_, v2) << R_SCSI0_STATUS_CTRL__skip__BITNR) | \
+ (R_SCSI0_STATUS_CTRL__clr_status__##f3_##_VAL(R_SCSI0_STATUS_CTRL_, clr_status_, v3) << R_SCSI0_STATUS_CTRL__clr_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI1_CMD
+ * - type: WO
+ * - addr: 0xb0000052
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_CMD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI1_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_CMD(f1,v1,f2,v2) ( \
+ *R_SCSI1_CMD__SADDR = ( \
+ REG_INITIATED(R_SCSI1_CMD_) \
+ REG_VAL__R_SCSI1_CMD_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_SCSI1_CMD__WRITE(R_SCSI1_CMD__ADDR, *R_SCSI1_CMD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_CMD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_CMD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI1_CMD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_CMD__SHADOW(f1,v1,f2,v2) ( \
+ *R_SCSI1_CMD__SADDR = ( \
+ REG_INITIATED(R_SCSI1_CMD_) \
+ REG_VAL__R_SCSI1_CMD_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI1_CMD(f1,v1,f2,v2) ( \
+ (R_SCSI1_CMD__asynch_setup__##f1##__MASK & REG__##v1) | \
+ (R_SCSI1_CMD__command__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_CMD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_CMD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_CMD(f1,v1,f2,v2) ( \
+ (R_SCSI1_CMD__asynch_setup__##f1##__VAL(R_SCSI1_CMD_, asynch_setup_, v1) << R_SCSI1_CMD__asynch_setup__BITNR) | \
+ (R_SCSI1_CMD__command__##f2##__VAL(R_SCSI1_CMD_, command_, v2) << R_SCSI1_CMD__command__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_CMD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_CMD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_CMD_(f1_,v1,f2_,v2) ( \
+ (R_SCSI1_CMD__asynch_setup__##f1_##_VAL(R_SCSI1_CMD_, asynch_setup_, v1) << R_SCSI1_CMD__asynch_setup__BITNR) | \
+ (R_SCSI1_CMD__command__##f2_##_VAL(R_SCSI1_CMD_, command_, v2) << R_SCSI1_CMD__command__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI1_CMD_DATA
+ * - type: WO
+ * - addr: 0xb0000050
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_CMD_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_CMD_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI1_CMD_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_SCSI1_CMD_DATA__SADDR = ( \
+ REG_INITIATED(R_SCSI1_CMD_DATA_) \
+ REG_VAL__R_SCSI1_CMD_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ), \
+ R_SCSI1_CMD_DATA__WRITE(R_SCSI1_CMD_DATA__ADDR, *R_SCSI1_CMD_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_CMD_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_CMD_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI1_CMD_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_CMD_DATA__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ *R_SCSI1_CMD_DATA__SADDR = ( \
+ REG_INITIATED(R_SCSI1_CMD_DATA_) \
+ REG_VAL__R_SCSI1_CMD_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI1_CMD_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI1_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_SCSI1_CMD_DATA__parity_in__##f1##__MASK & REG__##v1) | \
+ (R_SCSI1_CMD_DATA__skip__##f2##__MASK & REG__##v2) | \
+ (R_SCSI1_CMD_DATA__clr_status__##f3##__MASK & REG__##v3) | \
+ (R_SCSI1_CMD_DATA__asynch_setup__##f4##__MASK & REG__##v4) | \
+ (R_SCSI1_CMD_DATA__command__##f5##__MASK & REG__##v5) | \
+ (R_SCSI1_CMD_DATA__data_out__##f6##__MASK & REG__##v6) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_CMD_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_CMD_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_CMD_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_SCSI1_CMD_DATA__parity_in__##f1##__VAL(R_SCSI1_CMD_DATA_, parity_in_, v1) << R_SCSI1_CMD_DATA__parity_in__BITNR) | \
+ (R_SCSI1_CMD_DATA__skip__##f2##__VAL(R_SCSI1_CMD_DATA_, skip_, v2) << R_SCSI1_CMD_DATA__skip__BITNR) | \
+ (R_SCSI1_CMD_DATA__clr_status__##f3##__VAL(R_SCSI1_CMD_DATA_, clr_status_, v3) << R_SCSI1_CMD_DATA__clr_status__BITNR) | \
+ (R_SCSI1_CMD_DATA__asynch_setup__##f4##__VAL(R_SCSI1_CMD_DATA_, asynch_setup_, v4) << R_SCSI1_CMD_DATA__asynch_setup__BITNR) | \
+ (R_SCSI1_CMD_DATA__command__##f5##__VAL(R_SCSI1_CMD_DATA_, command_, v5) << R_SCSI1_CMD_DATA__command__BITNR) | \
+ (R_SCSI1_CMD_DATA__data_out__##f6##__VAL(R_SCSI1_CMD_DATA_, data_out_, v6) << R_SCSI1_CMD_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_CMD_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_CMD_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_CMD_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \
+ (R_SCSI1_CMD_DATA__parity_in__##f1_##_VAL(R_SCSI1_CMD_DATA_, parity_in_, v1) << R_SCSI1_CMD_DATA__parity_in__BITNR) | \
+ (R_SCSI1_CMD_DATA__skip__##f2_##_VAL(R_SCSI1_CMD_DATA_, skip_, v2) << R_SCSI1_CMD_DATA__skip__BITNR) | \
+ (R_SCSI1_CMD_DATA__clr_status__##f3_##_VAL(R_SCSI1_CMD_DATA_, clr_status_, v3) << R_SCSI1_CMD_DATA__clr_status__BITNR) | \
+ (R_SCSI1_CMD_DATA__asynch_setup__##f4_##_VAL(R_SCSI1_CMD_DATA_, asynch_setup_, v4) << R_SCSI1_CMD_DATA__asynch_setup__BITNR) | \
+ (R_SCSI1_CMD_DATA__command__##f5_##_VAL(R_SCSI1_CMD_DATA_, command_, v5) << R_SCSI1_CMD_DATA__command__BITNR) | \
+ (R_SCSI1_CMD_DATA__data_out__##f6_##_VAL(R_SCSI1_CMD_DATA_, data_out_, v6) << R_SCSI1_CMD_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI1_CTRL
+ * - type: WO
+ * - addr: 0xb0000054
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI1_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ *R_SCSI1_CTRL__SADDR = ( \
+ REG_INITIATED(R_SCSI1_CTRL_) \
+ REG_VAL__R_SCSI1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \
+ ), \
+ R_SCSI1_CTRL__WRITE(R_SCSI1_CTRL__ADDR, *R_SCSI1_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI1_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ *R_SCSI1_CTRL__SADDR = ( \
+ REG_INITIATED(R_SCSI1_CTRL_) \
+ REG_VAL__R_SCSI1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ (R_SCSI1_CTRL__id_type__##f1##__MASK & REG__##v1) | \
+ (R_SCSI1_CTRL__sel_timeout__##f2##__MASK & REG__##v2) | \
+ (R_SCSI1_CTRL__synch_per__##f3##__MASK & REG__##v3) | \
+ (R_SCSI1_CTRL__rst__##f4##__MASK & REG__##v4) | \
+ (R_SCSI1_CTRL__atn__##f5##__MASK & REG__##v5) | \
+ (R_SCSI1_CTRL__my_id__##f6##__MASK & REG__##v6) | \
+ (R_SCSI1_CTRL__target_id__##f7##__MASK & REG__##v7) | \
+ (R_SCSI1_CTRL__fast_20__##f8##__MASK & REG__##v8) | \
+ (R_SCSI1_CTRL__bus_width__##f9##__MASK & REG__##v9) | \
+ (R_SCSI1_CTRL__synch__##f10##__MASK & REG__##v10) | \
+ (R_SCSI1_CTRL__enable__##f11##__MASK & REG__##v11) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11) ( \
+ (R_SCSI1_CTRL__id_type__##f1##__VAL(R_SCSI1_CTRL_, id_type_, v1) << R_SCSI1_CTRL__id_type__BITNR) | \
+ (R_SCSI1_CTRL__sel_timeout__##f2##__VAL(R_SCSI1_CTRL_, sel_timeout_, v2) << R_SCSI1_CTRL__sel_timeout__BITNR) | \
+ (R_SCSI1_CTRL__synch_per__##f3##__VAL(R_SCSI1_CTRL_, synch_per_, v3) << R_SCSI1_CTRL__synch_per__BITNR) | \
+ (R_SCSI1_CTRL__rst__##f4##__VAL(R_SCSI1_CTRL_, rst_, v4) << R_SCSI1_CTRL__rst__BITNR) | \
+ (R_SCSI1_CTRL__atn__##f5##__VAL(R_SCSI1_CTRL_, atn_, v5) << R_SCSI1_CTRL__atn__BITNR) | \
+ (R_SCSI1_CTRL__my_id__##f6##__VAL(R_SCSI1_CTRL_, my_id_, v6) << R_SCSI1_CTRL__my_id__BITNR) | \
+ (R_SCSI1_CTRL__target_id__##f7##__VAL(R_SCSI1_CTRL_, target_id_, v7) << R_SCSI1_CTRL__target_id__BITNR) | \
+ (R_SCSI1_CTRL__fast_20__##f8##__VAL(R_SCSI1_CTRL_, fast_20_, v8) << R_SCSI1_CTRL__fast_20__BITNR) | \
+ (R_SCSI1_CTRL__bus_width__##f9##__VAL(R_SCSI1_CTRL_, bus_width_, v9) << R_SCSI1_CTRL__bus_width__BITNR) | \
+ (R_SCSI1_CTRL__synch__##f10##__VAL(R_SCSI1_CTRL_, synch_, v10) << R_SCSI1_CTRL__synch__BITNR) | \
+ (R_SCSI1_CTRL__enable__##f11##__VAL(R_SCSI1_CTRL_, enable_, v11) << R_SCSI1_CTRL__enable__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11) ( \
+ (R_SCSI1_CTRL__id_type__##f1_##_VAL(R_SCSI1_CTRL_, id_type_, v1) << R_SCSI1_CTRL__id_type__BITNR) | \
+ (R_SCSI1_CTRL__sel_timeout__##f2_##_VAL(R_SCSI1_CTRL_, sel_timeout_, v2) << R_SCSI1_CTRL__sel_timeout__BITNR) | \
+ (R_SCSI1_CTRL__synch_per__##f3_##_VAL(R_SCSI1_CTRL_, synch_per_, v3) << R_SCSI1_CTRL__synch_per__BITNR) | \
+ (R_SCSI1_CTRL__rst__##f4_##_VAL(R_SCSI1_CTRL_, rst_, v4) << R_SCSI1_CTRL__rst__BITNR) | \
+ (R_SCSI1_CTRL__atn__##f5_##_VAL(R_SCSI1_CTRL_, atn_, v5) << R_SCSI1_CTRL__atn__BITNR) | \
+ (R_SCSI1_CTRL__my_id__##f6_##_VAL(R_SCSI1_CTRL_, my_id_, v6) << R_SCSI1_CTRL__my_id__BITNR) | \
+ (R_SCSI1_CTRL__target_id__##f7_##_VAL(R_SCSI1_CTRL_, target_id_, v7) << R_SCSI1_CTRL__target_id__BITNR) | \
+ (R_SCSI1_CTRL__fast_20__##f8_##_VAL(R_SCSI1_CTRL_, fast_20_, v8) << R_SCSI1_CTRL__fast_20__BITNR) | \
+ (R_SCSI1_CTRL__bus_width__##f9_##_VAL(R_SCSI1_CTRL_, bus_width_, v9) << R_SCSI1_CTRL__bus_width__BITNR) | \
+ (R_SCSI1_CTRL__synch__##f10_##_VAL(R_SCSI1_CTRL_, synch_, v10) << R_SCSI1_CTRL__synch__BITNR) | \
+ (R_SCSI1_CTRL__enable__##f11_##_VAL(R_SCSI1_CTRL_, enable_, v11) << R_SCSI1_CTRL__enable__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI1_DATA
+ * - type: WO
+ * - addr: 0xb0000050
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI1_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_DATA(f1,v1) ( \
+ *R_SCSI1_DATA__SADDR = ( \
+ REG_INITIATED(R_SCSI1_DATA_) \
+ REG_VAL__R_SCSI1_DATA_(f1##_,v1) \
+ ), \
+ R_SCSI1_DATA__WRITE(R_SCSI1_DATA__ADDR, *R_SCSI1_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI1_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_DATA__SHADOW(f1,v1) ( \
+ *R_SCSI1_DATA__SADDR = ( \
+ REG_INITIATED(R_SCSI1_DATA_) \
+ REG_VAL__R_SCSI1_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI1_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI1_DATA(f1,v1) ( \
+ (R_SCSI1_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_DATA(f1,v1) ( \
+ (R_SCSI1_DATA__data_out__##f1##__VAL(R_SCSI1_DATA_, data_out_, v1) << R_SCSI1_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_DATA_(f1_,v1) ( \
+ (R_SCSI1_DATA__data_out__##f1_##_VAL(R_SCSI1_DATA_, data_out_, v1) << R_SCSI1_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI1_DATA_IN
+ * - type: RO
+ * - addr: 0xb0000050
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI1_DATA_IN
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI1_DATA_IN(f1,v1) ( \
+ (R_SCSI1_DATA_IN__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_DATA_IN
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_DATA_IN.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_DATA_IN(f1,v1) ( \
+ (R_SCSI1_DATA_IN__data_in__##f1##__VAL(R_SCSI1_DATA_IN_, data_in_, v1) << R_SCSI1_DATA_IN__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_DATA_IN_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_DATA_IN.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_DATA_IN_(f1_,v1) ( \
+ (R_SCSI1_DATA_IN__data_in__##f1_##_VAL(R_SCSI1_DATA_IN_, data_in_, v1) << R_SCSI1_DATA_IN__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI1_STATUS
+ * - type: RO
+ * - addr: 0xb0000058
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_SCSI1_STATUS__tst_arb_won__##f1##__MASK & REG__##v1) | \
+ (R_SCSI1_STATUS__tst_resel__##f2##__MASK & REG__##v2) | \
+ (R_SCSI1_STATUS__parity_error__##f3##__MASK & REG__##v3) | \
+ (R_SCSI1_STATUS__bus_reset__##f4##__MASK & REG__##v4) | \
+ (R_SCSI1_STATUS__resel_target__##f5##__MASK & REG__##v5) | \
+ (R_SCSI1_STATUS__resel__##f6##__MASK & REG__##v6) | \
+ (R_SCSI1_STATUS__curr_phase__##f7##__MASK & REG__##v7) | \
+ (R_SCSI1_STATUS__last_seq_step__##f8##__MASK & REG__##v8) | \
+ (R_SCSI1_STATUS__valid_status__##f9##__MASK & REG__##v9) | \
+ (R_SCSI1_STATUS__seq_status__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_SCSI1_STATUS__tst_arb_won__##f1##__VAL(R_SCSI1_STATUS_, tst_arb_won_, v1) << R_SCSI1_STATUS__tst_arb_won__BITNR) | \
+ (R_SCSI1_STATUS__tst_resel__##f2##__VAL(R_SCSI1_STATUS_, tst_resel_, v2) << R_SCSI1_STATUS__tst_resel__BITNR) | \
+ (R_SCSI1_STATUS__parity_error__##f3##__VAL(R_SCSI1_STATUS_, parity_error_, v3) << R_SCSI1_STATUS__parity_error__BITNR) | \
+ (R_SCSI1_STATUS__bus_reset__##f4##__VAL(R_SCSI1_STATUS_, bus_reset_, v4) << R_SCSI1_STATUS__bus_reset__BITNR) | \
+ (R_SCSI1_STATUS__resel_target__##f5##__VAL(R_SCSI1_STATUS_, resel_target_, v5) << R_SCSI1_STATUS__resel_target__BITNR) | \
+ (R_SCSI1_STATUS__resel__##f6##__VAL(R_SCSI1_STATUS_, resel_, v6) << R_SCSI1_STATUS__resel__BITNR) | \
+ (R_SCSI1_STATUS__curr_phase__##f7##__VAL(R_SCSI1_STATUS_, curr_phase_, v7) << R_SCSI1_STATUS__curr_phase__BITNR) | \
+ (R_SCSI1_STATUS__last_seq_step__##f8##__VAL(R_SCSI1_STATUS_, last_seq_step_, v8) << R_SCSI1_STATUS__last_seq_step__BITNR) | \
+ (R_SCSI1_STATUS__valid_status__##f9##__VAL(R_SCSI1_STATUS_, valid_status_, v9) << R_SCSI1_STATUS__valid_status__BITNR) | \
+ (R_SCSI1_STATUS__seq_status__##f10##__VAL(R_SCSI1_STATUS_, seq_status_, v10) << R_SCSI1_STATUS__seq_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_SCSI1_STATUS__tst_arb_won__##f1_##_VAL(R_SCSI1_STATUS_, tst_arb_won_, v1) << R_SCSI1_STATUS__tst_arb_won__BITNR) | \
+ (R_SCSI1_STATUS__tst_resel__##f2_##_VAL(R_SCSI1_STATUS_, tst_resel_, v2) << R_SCSI1_STATUS__tst_resel__BITNR) | \
+ (R_SCSI1_STATUS__parity_error__##f3_##_VAL(R_SCSI1_STATUS_, parity_error_, v3) << R_SCSI1_STATUS__parity_error__BITNR) | \
+ (R_SCSI1_STATUS__bus_reset__##f4_##_VAL(R_SCSI1_STATUS_, bus_reset_, v4) << R_SCSI1_STATUS__bus_reset__BITNR) | \
+ (R_SCSI1_STATUS__resel_target__##f5_##_VAL(R_SCSI1_STATUS_, resel_target_, v5) << R_SCSI1_STATUS__resel_target__BITNR) | \
+ (R_SCSI1_STATUS__resel__##f6_##_VAL(R_SCSI1_STATUS_, resel_, v6) << R_SCSI1_STATUS__resel__BITNR) | \
+ (R_SCSI1_STATUS__curr_phase__##f7_##_VAL(R_SCSI1_STATUS_, curr_phase_, v7) << R_SCSI1_STATUS__curr_phase__BITNR) | \
+ (R_SCSI1_STATUS__last_seq_step__##f8_##_VAL(R_SCSI1_STATUS_, last_seq_step_, v8) << R_SCSI1_STATUS__last_seq_step__BITNR) | \
+ (R_SCSI1_STATUS__valid_status__##f9_##_VAL(R_SCSI1_STATUS_, valid_status_, v9) << R_SCSI1_STATUS__valid_status__BITNR) | \
+ (R_SCSI1_STATUS__seq_status__##f10_##_VAL(R_SCSI1_STATUS_, seq_status_, v10) << R_SCSI1_STATUS__seq_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SCSI1_STATUS_CTRL
+ * - type: WO
+ * - addr: 0xb0000053
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_STATUS_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_STATUS_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SCSI1_STATUS_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ *R_SCSI1_STATUS_CTRL__SADDR = ( \
+ REG_INITIATED(R_SCSI1_STATUS_CTRL_) \
+ REG_VAL__R_SCSI1_STATUS_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ), \
+ R_SCSI1_STATUS_CTRL__WRITE(R_SCSI1_STATUS_CTRL__ADDR, *R_SCSI1_STATUS_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SCSI1_STATUS_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SCSI1_STATUS_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SCSI1_STATUS_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SCSI1_STATUS_CTRL__SHADOW(f1,v1,f2,v2,f3,v3) ( \
+ *R_SCSI1_STATUS_CTRL__SADDR = ( \
+ REG_INITIATED(R_SCSI1_STATUS_CTRL_) \
+ REG_VAL__R_SCSI1_STATUS_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SCSI1_STATUS_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SCSI1_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ (R_SCSI1_STATUS_CTRL__parity_in__##f1##__MASK & REG__##v1) | \
+ (R_SCSI1_STATUS_CTRL__skip__##f2##__MASK & REG__##v2) | \
+ (R_SCSI1_STATUS_CTRL__clr_status__##f3##__MASK & REG__##v3) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_STATUS_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_STATUS_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_STATUS_CTRL(f1,v1,f2,v2,f3,v3) ( \
+ (R_SCSI1_STATUS_CTRL__parity_in__##f1##__VAL(R_SCSI1_STATUS_CTRL_, parity_in_, v1) << R_SCSI1_STATUS_CTRL__parity_in__BITNR) | \
+ (R_SCSI1_STATUS_CTRL__skip__##f2##__VAL(R_SCSI1_STATUS_CTRL_, skip_, v2) << R_SCSI1_STATUS_CTRL__skip__BITNR) | \
+ (R_SCSI1_STATUS_CTRL__clr_status__##f3##__VAL(R_SCSI1_STATUS_CTRL_, clr_status_, v3) << R_SCSI1_STATUS_CTRL__clr_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SCSI1_STATUS_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SCSI1_STATUS_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SCSI1_STATUS_CTRL_(f1_,v1,f2_,v2,f3_,v3) ( \
+ (R_SCSI1_STATUS_CTRL__parity_in__##f1_##_VAL(R_SCSI1_STATUS_CTRL_, parity_in_, v1) << R_SCSI1_STATUS_CTRL__parity_in__BITNR) | \
+ (R_SCSI1_STATUS_CTRL__skip__##f2_##_VAL(R_SCSI1_STATUS_CTRL_, skip_, v2) << R_SCSI1_STATUS_CTRL__skip__BITNR) | \
+ (R_SCSI1_STATUS_CTRL__clr_status__##f3_##_VAL(R_SCSI1_STATUS_CTRL_, clr_status_, v3) << R_SCSI1_STATUS_CTRL__clr_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SDRAM_CONFIG
+ * - type: WO
+ * - addr: 0xb000000c
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SDRAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SDRAM_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SDRAM_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SDRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ *R_SDRAM_CONFIG__SADDR = ( \
+ REG_INITIATED(R_SDRAM_CONFIG_) \
+ REG_VAL__R_SDRAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \
+ ), \
+ R_SDRAM_CONFIG__WRITE(R_SDRAM_CONFIG__ADDR, *R_SDRAM_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SDRAM_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SDRAM_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SDRAM_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SDRAM_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ *R_SDRAM_CONFIG__SADDR = ( \
+ REG_INITIATED(R_SDRAM_CONFIG_) \
+ REG_VAL__R_SDRAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SDRAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SDRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_SDRAM_CONFIG__wmm1__##f1##__MASK & REG__##v1) | \
+ (R_SDRAM_CONFIG__wmm0__##f2##__MASK & REG__##v2) | \
+ (R_SDRAM_CONFIG__sh1__##f3##__MASK & REG__##v3) | \
+ (R_SDRAM_CONFIG__sh0__##f4##__MASK & REG__##v4) | \
+ (R_SDRAM_CONFIG__w__##f5##__MASK & REG__##v5) | \
+ (R_SDRAM_CONFIG__type1__##f6##__MASK & REG__##v6) | \
+ (R_SDRAM_CONFIG__type0__##f7##__MASK & REG__##v7) | \
+ (R_SDRAM_CONFIG__group_sel__##f8##__MASK & REG__##v8) | \
+ (R_SDRAM_CONFIG__ca1__##f9##__MASK & REG__##v9) | \
+ (R_SDRAM_CONFIG__bank_sel1__##f10##__MASK & REG__##v10) | \
+ (R_SDRAM_CONFIG__ca0__##f11##__MASK & REG__##v11) | \
+ (R_SDRAM_CONFIG__bank_sel0__##f12##__MASK & REG__##v12) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SDRAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SDRAM_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SDRAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_SDRAM_CONFIG__wmm1__##f1##__VAL(R_SDRAM_CONFIG_, wmm1_, v1) << R_SDRAM_CONFIG__wmm1__BITNR) | \
+ (R_SDRAM_CONFIG__wmm0__##f2##__VAL(R_SDRAM_CONFIG_, wmm0_, v2) << R_SDRAM_CONFIG__wmm0__BITNR) | \
+ (R_SDRAM_CONFIG__sh1__##f3##__VAL(R_SDRAM_CONFIG_, sh1_, v3) << R_SDRAM_CONFIG__sh1__BITNR) | \
+ (R_SDRAM_CONFIG__sh0__##f4##__VAL(R_SDRAM_CONFIG_, sh0_, v4) << R_SDRAM_CONFIG__sh0__BITNR) | \
+ (R_SDRAM_CONFIG__w__##f5##__VAL(R_SDRAM_CONFIG_, w_, v5) << R_SDRAM_CONFIG__w__BITNR) | \
+ (R_SDRAM_CONFIG__type1__##f6##__VAL(R_SDRAM_CONFIG_, type1_, v6) << R_SDRAM_CONFIG__type1__BITNR) | \
+ (R_SDRAM_CONFIG__type0__##f7##__VAL(R_SDRAM_CONFIG_, type0_, v7) << R_SDRAM_CONFIG__type0__BITNR) | \
+ (R_SDRAM_CONFIG__group_sel__##f8##__VAL(R_SDRAM_CONFIG_, group_sel_, v8) << R_SDRAM_CONFIG__group_sel__BITNR) | \
+ (R_SDRAM_CONFIG__ca1__##f9##__VAL(R_SDRAM_CONFIG_, ca1_, v9) << R_SDRAM_CONFIG__ca1__BITNR) | \
+ (R_SDRAM_CONFIG__bank_sel1__##f10##__VAL(R_SDRAM_CONFIG_, bank_sel1_, v10) << R_SDRAM_CONFIG__bank_sel1__BITNR) | \
+ (R_SDRAM_CONFIG__ca0__##f11##__VAL(R_SDRAM_CONFIG_, ca0_, v11) << R_SDRAM_CONFIG__ca0__BITNR) | \
+ (R_SDRAM_CONFIG__bank_sel0__##f12##__VAL(R_SDRAM_CONFIG_, bank_sel0_, v12) << R_SDRAM_CONFIG__bank_sel0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SDRAM_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SDRAM_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SDRAM_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \
+ (R_SDRAM_CONFIG__wmm1__##f1_##_VAL(R_SDRAM_CONFIG_, wmm1_, v1) << R_SDRAM_CONFIG__wmm1__BITNR) | \
+ (R_SDRAM_CONFIG__wmm0__##f2_##_VAL(R_SDRAM_CONFIG_, wmm0_, v2) << R_SDRAM_CONFIG__wmm0__BITNR) | \
+ (R_SDRAM_CONFIG__sh1__##f3_##_VAL(R_SDRAM_CONFIG_, sh1_, v3) << R_SDRAM_CONFIG__sh1__BITNR) | \
+ (R_SDRAM_CONFIG__sh0__##f4_##_VAL(R_SDRAM_CONFIG_, sh0_, v4) << R_SDRAM_CONFIG__sh0__BITNR) | \
+ (R_SDRAM_CONFIG__w__##f5_##_VAL(R_SDRAM_CONFIG_, w_, v5) << R_SDRAM_CONFIG__w__BITNR) | \
+ (R_SDRAM_CONFIG__type1__##f6_##_VAL(R_SDRAM_CONFIG_, type1_, v6) << R_SDRAM_CONFIG__type1__BITNR) | \
+ (R_SDRAM_CONFIG__type0__##f7_##_VAL(R_SDRAM_CONFIG_, type0_, v7) << R_SDRAM_CONFIG__type0__BITNR) | \
+ (R_SDRAM_CONFIG__group_sel__##f8_##_VAL(R_SDRAM_CONFIG_, group_sel_, v8) << R_SDRAM_CONFIG__group_sel__BITNR) | \
+ (R_SDRAM_CONFIG__ca1__##f9_##_VAL(R_SDRAM_CONFIG_, ca1_, v9) << R_SDRAM_CONFIG__ca1__BITNR) | \
+ (R_SDRAM_CONFIG__bank_sel1__##f10_##_VAL(R_SDRAM_CONFIG_, bank_sel1_, v10) << R_SDRAM_CONFIG__bank_sel1__BITNR) | \
+ (R_SDRAM_CONFIG__ca0__##f11_##_VAL(R_SDRAM_CONFIG_, ca0_, v11) << R_SDRAM_CONFIG__ca0__BITNR) | \
+ (R_SDRAM_CONFIG__bank_sel0__##f12_##_VAL(R_SDRAM_CONFIG_, bank_sel0_, v12) << R_SDRAM_CONFIG__bank_sel0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SDRAM_TIMING
+ * - type: WO
+ * - addr: 0xb0000008
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SDRAM_TIMING
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SDRAM_TIMING.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SDRAM_TIMING.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SDRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ *R_SDRAM_TIMING__SADDR = ( \
+ REG_INITIATED(R_SDRAM_TIMING_) \
+ REG_VAL__R_SDRAM_TIMING_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \
+ ), \
+ R_SDRAM_TIMING__WRITE(R_SDRAM_TIMING__ADDR, *R_SDRAM_TIMING__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SDRAM_TIMING__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SDRAM_TIMING.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SDRAM_TIMING.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SDRAM_TIMING__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ *R_SDRAM_TIMING__SADDR = ( \
+ REG_INITIATED(R_SDRAM_TIMING_) \
+ REG_VAL__R_SDRAM_TIMING_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SDRAM_TIMING
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SDRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_SDRAM_TIMING__sdram__##f1##__MASK & REG__##v1) | \
+ (R_SDRAM_TIMING__mrs_data__##f2##__MASK & REG__##v2) | \
+ (R_SDRAM_TIMING__ref__##f3##__MASK & REG__##v3) | \
+ (R_SDRAM_TIMING__ddr__##f4##__MASK & REG__##v4) | \
+ (R_SDRAM_TIMING__clk100__##f5##__MASK & REG__##v5) | \
+ (R_SDRAM_TIMING__ps__##f6##__MASK & REG__##v6) | \
+ (R_SDRAM_TIMING__cmd__##f7##__MASK & REG__##v7) | \
+ (R_SDRAM_TIMING__pde__##f8##__MASK & REG__##v8) | \
+ (R_SDRAM_TIMING__rc__##f9##__MASK & REG__##v9) | \
+ (R_SDRAM_TIMING__rp__##f10##__MASK & REG__##v10) | \
+ (R_SDRAM_TIMING__rcd__##f11##__MASK & REG__##v11) | \
+ (R_SDRAM_TIMING__cl__##f12##__MASK & REG__##v12) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SDRAM_TIMING
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SDRAM_TIMING.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SDRAM_TIMING(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_SDRAM_TIMING__sdram__##f1##__VAL(R_SDRAM_TIMING_, sdram_, v1) << R_SDRAM_TIMING__sdram__BITNR) | \
+ (R_SDRAM_TIMING__mrs_data__##f2##__VAL(R_SDRAM_TIMING_, mrs_data_, v2) << R_SDRAM_TIMING__mrs_data__BITNR) | \
+ (R_SDRAM_TIMING__ref__##f3##__VAL(R_SDRAM_TIMING_, ref_, v3) << R_SDRAM_TIMING__ref__BITNR) | \
+ (R_SDRAM_TIMING__ddr__##f4##__VAL(R_SDRAM_TIMING_, ddr_, v4) << R_SDRAM_TIMING__ddr__BITNR) | \
+ (R_SDRAM_TIMING__clk100__##f5##__VAL(R_SDRAM_TIMING_, clk100_, v5) << R_SDRAM_TIMING__clk100__BITNR) | \
+ (R_SDRAM_TIMING__ps__##f6##__VAL(R_SDRAM_TIMING_, ps_, v6) << R_SDRAM_TIMING__ps__BITNR) | \
+ (R_SDRAM_TIMING__cmd__##f7##__VAL(R_SDRAM_TIMING_, cmd_, v7) << R_SDRAM_TIMING__cmd__BITNR) | \
+ (R_SDRAM_TIMING__pde__##f8##__VAL(R_SDRAM_TIMING_, pde_, v8) << R_SDRAM_TIMING__pde__BITNR) | \
+ (R_SDRAM_TIMING__rc__##f9##__VAL(R_SDRAM_TIMING_, rc_, v9) << R_SDRAM_TIMING__rc__BITNR) | \
+ (R_SDRAM_TIMING__rp__##f10##__VAL(R_SDRAM_TIMING_, rp_, v10) << R_SDRAM_TIMING__rp__BITNR) | \
+ (R_SDRAM_TIMING__rcd__##f11##__VAL(R_SDRAM_TIMING_, rcd_, v11) << R_SDRAM_TIMING__rcd__BITNR) | \
+ (R_SDRAM_TIMING__cl__##f12##__VAL(R_SDRAM_TIMING_, cl_, v12) << R_SDRAM_TIMING__cl__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SDRAM_TIMING_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SDRAM_TIMING.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SDRAM_TIMING_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \
+ (R_SDRAM_TIMING__sdram__##f1_##_VAL(R_SDRAM_TIMING_, sdram_, v1) << R_SDRAM_TIMING__sdram__BITNR) | \
+ (R_SDRAM_TIMING__mrs_data__##f2_##_VAL(R_SDRAM_TIMING_, mrs_data_, v2) << R_SDRAM_TIMING__mrs_data__BITNR) | \
+ (R_SDRAM_TIMING__ref__##f3_##_VAL(R_SDRAM_TIMING_, ref_, v3) << R_SDRAM_TIMING__ref__BITNR) | \
+ (R_SDRAM_TIMING__ddr__##f4_##_VAL(R_SDRAM_TIMING_, ddr_, v4) << R_SDRAM_TIMING__ddr__BITNR) | \
+ (R_SDRAM_TIMING__clk100__##f5_##_VAL(R_SDRAM_TIMING_, clk100_, v5) << R_SDRAM_TIMING__clk100__BITNR) | \
+ (R_SDRAM_TIMING__ps__##f6_##_VAL(R_SDRAM_TIMING_, ps_, v6) << R_SDRAM_TIMING__ps__BITNR) | \
+ (R_SDRAM_TIMING__cmd__##f7_##_VAL(R_SDRAM_TIMING_, cmd_, v7) << R_SDRAM_TIMING__cmd__BITNR) | \
+ (R_SDRAM_TIMING__pde__##f8_##_VAL(R_SDRAM_TIMING_, pde_, v8) << R_SDRAM_TIMING__pde__BITNR) | \
+ (R_SDRAM_TIMING__rc__##f9_##_VAL(R_SDRAM_TIMING_, rc_, v9) << R_SDRAM_TIMING__rc__BITNR) | \
+ (R_SDRAM_TIMING__rp__##f10_##_VAL(R_SDRAM_TIMING_, rp_, v10) << R_SDRAM_TIMING__rp__BITNR) | \
+ (R_SDRAM_TIMING__rcd__##f11_##_VAL(R_SDRAM_TIMING_, rcd_, v11) << R_SDRAM_TIMING__rcd__BITNR) | \
+ (R_SDRAM_TIMING__cl__##f12_##_VAL(R_SDRAM_TIMING_, cl_, v12) << R_SDRAM_TIMING__cl__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_BAUD
+ * - type: WO
+ * - addr: 0xb0000063
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_BAUD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL0_BAUD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_BAUD(f1,v1,f2,v2) ( \
+ *R_SERIAL0_BAUD__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_BAUD_) \
+ REG_VAL__R_SERIAL0_BAUD_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_SERIAL0_BAUD__WRITE(R_SERIAL0_BAUD__ADDR, *R_SERIAL0_BAUD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_BAUD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_BAUD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL0_BAUD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_BAUD__SHADOW(f1,v1,f2,v2) ( \
+ *R_SERIAL0_BAUD__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_BAUD_) \
+ REG_VAL__R_SERIAL0_BAUD_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_BAUD(f1,v1,f2,v2) ( \
+ (R_SERIAL0_BAUD__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL0_BAUD__rec_baud__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_BAUD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_BAUD(f1,v1,f2,v2) ( \
+ (R_SERIAL0_BAUD__tr_baud__##f1##__VAL(R_SERIAL0_BAUD_, tr_baud_, v1) << R_SERIAL0_BAUD__tr_baud__BITNR) | \
+ (R_SERIAL0_BAUD__rec_baud__##f2##__VAL(R_SERIAL0_BAUD_, rec_baud_, v2) << R_SERIAL0_BAUD__rec_baud__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_BAUD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_BAUD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_BAUD_(f1_,v1,f2_,v2) ( \
+ (R_SERIAL0_BAUD__tr_baud__##f1_##_VAL(R_SERIAL0_BAUD_, tr_baud_, v1) << R_SERIAL0_BAUD__tr_baud__BITNR) | \
+ (R_SERIAL0_BAUD__rec_baud__##f2_##_VAL(R_SERIAL0_BAUD_, rec_baud_, v2) << R_SERIAL0_BAUD__rec_baud__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_CTRL
+ * - type: WO
+ * - addr: 0xb0000060
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL0_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_SERIAL0_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_CTRL_) \
+ REG_VAL__R_SERIAL0_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ), \
+ R_SERIAL0_CTRL__WRITE(R_SERIAL0_CTRL__ADDR, *R_SERIAL0_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL0_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_SERIAL0_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_CTRL_) \
+ REG_VAL__R_SERIAL0_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_SERIAL0_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL0_CTRL__rec_baud__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL0_CTRL__dma_err__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL0_CTRL__rec_enable__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL0_CTRL__rts___##f5##__MASK & REG__##v5) | \
+ (R_SERIAL0_CTRL__sampling__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL0_CTRL__rec_stick_par__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL0_CTRL__rec_par__##f8##__MASK & REG__##v8) | \
+ (R_SERIAL0_CTRL__rec_par_en__##f9##__MASK & REG__##v9) | \
+ (R_SERIAL0_CTRL__rec_bitnr__##f10##__MASK & REG__##v10) | \
+ (R_SERIAL0_CTRL__txd__##f11##__MASK & REG__##v11) | \
+ (R_SERIAL0_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \
+ (R_SERIAL0_CTRL__auto_cts__##f13##__MASK & REG__##v13) | \
+ (R_SERIAL0_CTRL__stop_bits__##f14##__MASK & REG__##v14) | \
+ (R_SERIAL0_CTRL__tr_stick_par__##f15##__MASK & REG__##v15) | \
+ (R_SERIAL0_CTRL__tr_par__##f16##__MASK & REG__##v16) | \
+ (R_SERIAL0_CTRL__tr_par_en__##f17##__MASK & REG__##v17) | \
+ (R_SERIAL0_CTRL__tr_bitnr__##f18##__MASK & REG__##v18) | \
+ (R_SERIAL0_CTRL__data_out__##f19##__MASK & REG__##v19) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_SERIAL0_CTRL__tr_baud__##f1##__VAL(R_SERIAL0_CTRL_, tr_baud_, v1) << R_SERIAL0_CTRL__tr_baud__BITNR) | \
+ (R_SERIAL0_CTRL__rec_baud__##f2##__VAL(R_SERIAL0_CTRL_, rec_baud_, v2) << R_SERIAL0_CTRL__rec_baud__BITNR) | \
+ (R_SERIAL0_CTRL__dma_err__##f3##__VAL(R_SERIAL0_CTRL_, dma_err_, v3) << R_SERIAL0_CTRL__dma_err__BITNR) | \
+ (R_SERIAL0_CTRL__rec_enable__##f4##__VAL(R_SERIAL0_CTRL_, rec_enable_, v4) << R_SERIAL0_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL0_CTRL__rts___##f5##__VAL(R_SERIAL0_CTRL_, rts__, v5) << R_SERIAL0_CTRL__rts___BITNR) | \
+ (R_SERIAL0_CTRL__sampling__##f6##__VAL(R_SERIAL0_CTRL_, sampling_, v6) << R_SERIAL0_CTRL__sampling__BITNR) | \
+ (R_SERIAL0_CTRL__rec_stick_par__##f7##__VAL(R_SERIAL0_CTRL_, rec_stick_par_, v7) << R_SERIAL0_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL0_CTRL__rec_par__##f8##__VAL(R_SERIAL0_CTRL_, rec_par_, v8) << R_SERIAL0_CTRL__rec_par__BITNR) | \
+ (R_SERIAL0_CTRL__rec_par_en__##f9##__VAL(R_SERIAL0_CTRL_, rec_par_en_, v9) << R_SERIAL0_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL0_CTRL__rec_bitnr__##f10##__VAL(R_SERIAL0_CTRL_, rec_bitnr_, v10) << R_SERIAL0_CTRL__rec_bitnr__BITNR) | \
+ (R_SERIAL0_CTRL__txd__##f11##__VAL(R_SERIAL0_CTRL_, txd_, v11) << R_SERIAL0_CTRL__txd__BITNR) | \
+ (R_SERIAL0_CTRL__tr_enable__##f12##__VAL(R_SERIAL0_CTRL_, tr_enable_, v12) << R_SERIAL0_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL0_CTRL__auto_cts__##f13##__VAL(R_SERIAL0_CTRL_, auto_cts_, v13) << R_SERIAL0_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL0_CTRL__stop_bits__##f14##__VAL(R_SERIAL0_CTRL_, stop_bits_, v14) << R_SERIAL0_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL0_CTRL__tr_stick_par__##f15##__VAL(R_SERIAL0_CTRL_, tr_stick_par_, v15) << R_SERIAL0_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL0_CTRL__tr_par__##f16##__VAL(R_SERIAL0_CTRL_, tr_par_, v16) << R_SERIAL0_CTRL__tr_par__BITNR) | \
+ (R_SERIAL0_CTRL__tr_par_en__##f17##__VAL(R_SERIAL0_CTRL_, tr_par_en_, v17) << R_SERIAL0_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL0_CTRL__tr_bitnr__##f18##__VAL(R_SERIAL0_CTRL_, tr_bitnr_, v18) << R_SERIAL0_CTRL__tr_bitnr__BITNR) | \
+ (R_SERIAL0_CTRL__data_out__##f19##__VAL(R_SERIAL0_CTRL_, data_out_, v19) << R_SERIAL0_CTRL__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \
+ (R_SERIAL0_CTRL__tr_baud__##f1_##_VAL(R_SERIAL0_CTRL_, tr_baud_, v1) << R_SERIAL0_CTRL__tr_baud__BITNR) | \
+ (R_SERIAL0_CTRL__rec_baud__##f2_##_VAL(R_SERIAL0_CTRL_, rec_baud_, v2) << R_SERIAL0_CTRL__rec_baud__BITNR) | \
+ (R_SERIAL0_CTRL__dma_err__##f3_##_VAL(R_SERIAL0_CTRL_, dma_err_, v3) << R_SERIAL0_CTRL__dma_err__BITNR) | \
+ (R_SERIAL0_CTRL__rec_enable__##f4_##_VAL(R_SERIAL0_CTRL_, rec_enable_, v4) << R_SERIAL0_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL0_CTRL__rts___##f5_##_VAL(R_SERIAL0_CTRL_, rts__, v5) << R_SERIAL0_CTRL__rts___BITNR) | \
+ (R_SERIAL0_CTRL__sampling__##f6_##_VAL(R_SERIAL0_CTRL_, sampling_, v6) << R_SERIAL0_CTRL__sampling__BITNR) | \
+ (R_SERIAL0_CTRL__rec_stick_par__##f7_##_VAL(R_SERIAL0_CTRL_, rec_stick_par_, v7) << R_SERIAL0_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL0_CTRL__rec_par__##f8_##_VAL(R_SERIAL0_CTRL_, rec_par_, v8) << R_SERIAL0_CTRL__rec_par__BITNR) | \
+ (R_SERIAL0_CTRL__rec_par_en__##f9_##_VAL(R_SERIAL0_CTRL_, rec_par_en_, v9) << R_SERIAL0_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL0_CTRL__rec_bitnr__##f10_##_VAL(R_SERIAL0_CTRL_, rec_bitnr_, v10) << R_SERIAL0_CTRL__rec_bitnr__BITNR) | \
+ (R_SERIAL0_CTRL__txd__##f11_##_VAL(R_SERIAL0_CTRL_, txd_, v11) << R_SERIAL0_CTRL__txd__BITNR) | \
+ (R_SERIAL0_CTRL__tr_enable__##f12_##_VAL(R_SERIAL0_CTRL_, tr_enable_, v12) << R_SERIAL0_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL0_CTRL__auto_cts__##f13_##_VAL(R_SERIAL0_CTRL_, auto_cts_, v13) << R_SERIAL0_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL0_CTRL__stop_bits__##f14_##_VAL(R_SERIAL0_CTRL_, stop_bits_, v14) << R_SERIAL0_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL0_CTRL__tr_stick_par__##f15_##_VAL(R_SERIAL0_CTRL_, tr_stick_par_, v15) << R_SERIAL0_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL0_CTRL__tr_par__##f16_##_VAL(R_SERIAL0_CTRL_, tr_par_, v16) << R_SERIAL0_CTRL__tr_par__BITNR) | \
+ (R_SERIAL0_CTRL__tr_par_en__##f17_##_VAL(R_SERIAL0_CTRL_, tr_par_en_, v17) << R_SERIAL0_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL0_CTRL__tr_bitnr__##f18_##_VAL(R_SERIAL0_CTRL_, tr_bitnr_, v18) << R_SERIAL0_CTRL__tr_bitnr__BITNR) | \
+ (R_SERIAL0_CTRL__data_out__##f19_##_VAL(R_SERIAL0_CTRL_, data_out_, v19) << R_SERIAL0_CTRL__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_READ
+ * - type: RO
+ * - addr: 0xb0000060
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SERIAL0_READ__xoff_detect__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL0_READ__cts___##f2##__MASK & REG__##v2) | \
+ (R_SERIAL0_READ__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL0_READ__rxd__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL0_READ__overrun__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL0_READ__par_err__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL0_READ__framing_err__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL0_READ__data_avail__##f8##__MASK & REG__##v8) | \
+ (R_SERIAL0_READ__data_in__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SERIAL0_READ__xoff_detect__##f1##__VAL(R_SERIAL0_READ_, xoff_detect_, v1) << R_SERIAL0_READ__xoff_detect__BITNR) | \
+ (R_SERIAL0_READ__cts___##f2##__VAL(R_SERIAL0_READ_, cts__, v2) << R_SERIAL0_READ__cts___BITNR) | \
+ (R_SERIAL0_READ__tr_ready__##f3##__VAL(R_SERIAL0_READ_, tr_ready_, v3) << R_SERIAL0_READ__tr_ready__BITNR) | \
+ (R_SERIAL0_READ__rxd__##f4##__VAL(R_SERIAL0_READ_, rxd_, v4) << R_SERIAL0_READ__rxd__BITNR) | \
+ (R_SERIAL0_READ__overrun__##f5##__VAL(R_SERIAL0_READ_, overrun_, v5) << R_SERIAL0_READ__overrun__BITNR) | \
+ (R_SERIAL0_READ__par_err__##f6##__VAL(R_SERIAL0_READ_, par_err_, v6) << R_SERIAL0_READ__par_err__BITNR) | \
+ (R_SERIAL0_READ__framing_err__##f7##__VAL(R_SERIAL0_READ_, framing_err_, v7) << R_SERIAL0_READ__framing_err__BITNR) | \
+ (R_SERIAL0_READ__data_avail__##f8##__VAL(R_SERIAL0_READ_, data_avail_, v8) << R_SERIAL0_READ__data_avail__BITNR) | \
+ (R_SERIAL0_READ__data_in__##f9##__VAL(R_SERIAL0_READ_, data_in_, v9) << R_SERIAL0_READ__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_SERIAL0_READ__xoff_detect__##f1_##_VAL(R_SERIAL0_READ_, xoff_detect_, v1) << R_SERIAL0_READ__xoff_detect__BITNR) | \
+ (R_SERIAL0_READ__cts___##f2_##_VAL(R_SERIAL0_READ_, cts__, v2) << R_SERIAL0_READ__cts___BITNR) | \
+ (R_SERIAL0_READ__tr_ready__##f3_##_VAL(R_SERIAL0_READ_, tr_ready_, v3) << R_SERIAL0_READ__tr_ready__BITNR) | \
+ (R_SERIAL0_READ__rxd__##f4_##_VAL(R_SERIAL0_READ_, rxd_, v4) << R_SERIAL0_READ__rxd__BITNR) | \
+ (R_SERIAL0_READ__overrun__##f5_##_VAL(R_SERIAL0_READ_, overrun_, v5) << R_SERIAL0_READ__overrun__BITNR) | \
+ (R_SERIAL0_READ__par_err__##f6_##_VAL(R_SERIAL0_READ_, par_err_, v6) << R_SERIAL0_READ__par_err__BITNR) | \
+ (R_SERIAL0_READ__framing_err__##f7_##_VAL(R_SERIAL0_READ_, framing_err_, v7) << R_SERIAL0_READ__framing_err__BITNR) | \
+ (R_SERIAL0_READ__data_avail__##f8_##_VAL(R_SERIAL0_READ_, data_avail_, v8) << R_SERIAL0_READ__data_avail__BITNR) | \
+ (R_SERIAL0_READ__data_in__##f9_##_VAL(R_SERIAL0_READ_, data_in_, v9) << R_SERIAL0_READ__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_REC_CTRL
+ * - type: WO
+ * - addr: 0xb0000062
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_REC_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL0_REC_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL0_REC_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_REC_CTRL_) \
+ REG_VAL__R_SERIAL0_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SERIAL0_REC_CTRL__WRITE(R_SERIAL0_REC_CTRL__ADDR, *R_SERIAL0_REC_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_REC_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_REC_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL0_REC_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_REC_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL0_REC_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_REC_CTRL_) \
+ REG_VAL__R_SERIAL0_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL0_REC_CTRL__dma_err__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL0_REC_CTRL__rec_enable__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL0_REC_CTRL__rts___##f3##__MASK & REG__##v3) | \
+ (R_SERIAL0_REC_CTRL__sampling__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL0_REC_CTRL__rec_stick_par__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL0_REC_CTRL__rec_par__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL0_REC_CTRL__rec_par_en__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL0_REC_CTRL__rec_bitnr__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_REC_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL0_REC_CTRL__dma_err__##f1##__VAL(R_SERIAL0_REC_CTRL_, dma_err_, v1) << R_SERIAL0_REC_CTRL__dma_err__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_enable__##f2##__VAL(R_SERIAL0_REC_CTRL_, rec_enable_, v2) << R_SERIAL0_REC_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rts___##f3##__VAL(R_SERIAL0_REC_CTRL_, rts__, v3) << R_SERIAL0_REC_CTRL__rts___BITNR) | \
+ (R_SERIAL0_REC_CTRL__sampling__##f4##__VAL(R_SERIAL0_REC_CTRL_, sampling_, v4) << R_SERIAL0_REC_CTRL__sampling__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_stick_par__##f5##__VAL(R_SERIAL0_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL0_REC_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_par__##f6##__VAL(R_SERIAL0_REC_CTRL_, rec_par_, v6) << R_SERIAL0_REC_CTRL__rec_par__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_par_en__##f7##__VAL(R_SERIAL0_REC_CTRL_, rec_par_en_, v7) << R_SERIAL0_REC_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_bitnr__##f8##__VAL(R_SERIAL0_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL0_REC_CTRL__rec_bitnr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_REC_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_REC_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_REC_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL0_REC_CTRL__dma_err__##f1_##_VAL(R_SERIAL0_REC_CTRL_, dma_err_, v1) << R_SERIAL0_REC_CTRL__dma_err__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_enable__##f2_##_VAL(R_SERIAL0_REC_CTRL_, rec_enable_, v2) << R_SERIAL0_REC_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rts___##f3_##_VAL(R_SERIAL0_REC_CTRL_, rts__, v3) << R_SERIAL0_REC_CTRL__rts___BITNR) | \
+ (R_SERIAL0_REC_CTRL__sampling__##f4_##_VAL(R_SERIAL0_REC_CTRL_, sampling_, v4) << R_SERIAL0_REC_CTRL__sampling__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_stick_par__##f5_##_VAL(R_SERIAL0_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL0_REC_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_par__##f6_##_VAL(R_SERIAL0_REC_CTRL_, rec_par_, v6) << R_SERIAL0_REC_CTRL__rec_par__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_par_en__##f7_##_VAL(R_SERIAL0_REC_CTRL_, rec_par_en_, v7) << R_SERIAL0_REC_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL0_REC_CTRL__rec_bitnr__##f8_##_VAL(R_SERIAL0_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL0_REC_CTRL__rec_bitnr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_REC_DATA
+ * - type: RO
+ * - addr: 0xb0000060
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_REC_DATA(f1,v1) ( \
+ (R_SERIAL0_REC_DATA__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_REC_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_REC_DATA(f1,v1) ( \
+ (R_SERIAL0_REC_DATA__data_in__##f1##__VAL(R_SERIAL0_REC_DATA_, data_in_, v1) << R_SERIAL0_REC_DATA__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_REC_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_REC_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_REC_DATA_(f1_,v1) ( \
+ (R_SERIAL0_REC_DATA__data_in__##f1_##_VAL(R_SERIAL0_REC_DATA_, data_in_, v1) << R_SERIAL0_REC_DATA__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_STATUS
+ * - type: RO
+ * - addr: 0xb0000061
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL0_STATUS__xoff_detect__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL0_STATUS__cts___##f2##__MASK & REG__##v2) | \
+ (R_SERIAL0_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL0_STATUS__rxd__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL0_STATUS__overrun__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL0_STATUS__par_err__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL0_STATUS__framing_err__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL0_STATUS__data_avail__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL0_STATUS__xoff_detect__##f1##__VAL(R_SERIAL0_STATUS_, xoff_detect_, v1) << R_SERIAL0_STATUS__xoff_detect__BITNR) | \
+ (R_SERIAL0_STATUS__cts___##f2##__VAL(R_SERIAL0_STATUS_, cts__, v2) << R_SERIAL0_STATUS__cts___BITNR) | \
+ (R_SERIAL0_STATUS__tr_ready__##f3##__VAL(R_SERIAL0_STATUS_, tr_ready_, v3) << R_SERIAL0_STATUS__tr_ready__BITNR) | \
+ (R_SERIAL0_STATUS__rxd__##f4##__VAL(R_SERIAL0_STATUS_, rxd_, v4) << R_SERIAL0_STATUS__rxd__BITNR) | \
+ (R_SERIAL0_STATUS__overrun__##f5##__VAL(R_SERIAL0_STATUS_, overrun_, v5) << R_SERIAL0_STATUS__overrun__BITNR) | \
+ (R_SERIAL0_STATUS__par_err__##f6##__VAL(R_SERIAL0_STATUS_, par_err_, v6) << R_SERIAL0_STATUS__par_err__BITNR) | \
+ (R_SERIAL0_STATUS__framing_err__##f7##__VAL(R_SERIAL0_STATUS_, framing_err_, v7) << R_SERIAL0_STATUS__framing_err__BITNR) | \
+ (R_SERIAL0_STATUS__data_avail__##f8##__VAL(R_SERIAL0_STATUS_, data_avail_, v8) << R_SERIAL0_STATUS__data_avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL0_STATUS__xoff_detect__##f1_##_VAL(R_SERIAL0_STATUS_, xoff_detect_, v1) << R_SERIAL0_STATUS__xoff_detect__BITNR) | \
+ (R_SERIAL0_STATUS__cts___##f2_##_VAL(R_SERIAL0_STATUS_, cts__, v2) << R_SERIAL0_STATUS__cts___BITNR) | \
+ (R_SERIAL0_STATUS__tr_ready__##f3_##_VAL(R_SERIAL0_STATUS_, tr_ready_, v3) << R_SERIAL0_STATUS__tr_ready__BITNR) | \
+ (R_SERIAL0_STATUS__rxd__##f4_##_VAL(R_SERIAL0_STATUS_, rxd_, v4) << R_SERIAL0_STATUS__rxd__BITNR) | \
+ (R_SERIAL0_STATUS__overrun__##f5_##_VAL(R_SERIAL0_STATUS_, overrun_, v5) << R_SERIAL0_STATUS__overrun__BITNR) | \
+ (R_SERIAL0_STATUS__par_err__##f6_##_VAL(R_SERIAL0_STATUS_, par_err_, v6) << R_SERIAL0_STATUS__par_err__BITNR) | \
+ (R_SERIAL0_STATUS__framing_err__##f7_##_VAL(R_SERIAL0_STATUS_, framing_err_, v7) << R_SERIAL0_STATUS__framing_err__BITNR) | \
+ (R_SERIAL0_STATUS__data_avail__##f8_##_VAL(R_SERIAL0_STATUS_, data_avail_, v8) << R_SERIAL0_STATUS__data_avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_TR_CTRL
+ * - type: WO
+ * - addr: 0xb0000061
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL0_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL0_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_TR_CTRL_) \
+ REG_VAL__R_SERIAL0_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SERIAL0_TR_CTRL__WRITE(R_SERIAL0_TR_CTRL__ADDR, *R_SERIAL0_TR_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_TR_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL0_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL0_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_TR_CTRL_) \
+ REG_VAL__R_SERIAL0_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL0_TR_CTRL__txd__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL0_TR_CTRL__tr_enable__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL0_TR_CTRL__auto_cts__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL0_TR_CTRL__stop_bits__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL0_TR_CTRL__tr_stick_par__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL0_TR_CTRL__tr_par__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL0_TR_CTRL__tr_par_en__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL0_TR_CTRL__tr_bitnr__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_TR_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL0_TR_CTRL__txd__##f1##__VAL(R_SERIAL0_TR_CTRL_, txd_, v1) << R_SERIAL0_TR_CTRL__txd__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_enable__##f2##__VAL(R_SERIAL0_TR_CTRL_, tr_enable_, v2) << R_SERIAL0_TR_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL0_TR_CTRL__auto_cts__##f3##__VAL(R_SERIAL0_TR_CTRL_, auto_cts_, v3) << R_SERIAL0_TR_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL0_TR_CTRL__stop_bits__##f4##__VAL(R_SERIAL0_TR_CTRL_, stop_bits_, v4) << R_SERIAL0_TR_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_stick_par__##f5##__VAL(R_SERIAL0_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL0_TR_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_par__##f6##__VAL(R_SERIAL0_TR_CTRL_, tr_par_, v6) << R_SERIAL0_TR_CTRL__tr_par__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_par_en__##f7##__VAL(R_SERIAL0_TR_CTRL_, tr_par_en_, v7) << R_SERIAL0_TR_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_bitnr__##f8##__VAL(R_SERIAL0_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL0_TR_CTRL__tr_bitnr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_TR_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_TR_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL0_TR_CTRL__txd__##f1_##_VAL(R_SERIAL0_TR_CTRL_, txd_, v1) << R_SERIAL0_TR_CTRL__txd__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_enable__##f2_##_VAL(R_SERIAL0_TR_CTRL_, tr_enable_, v2) << R_SERIAL0_TR_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL0_TR_CTRL__auto_cts__##f3_##_VAL(R_SERIAL0_TR_CTRL_, auto_cts_, v3) << R_SERIAL0_TR_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL0_TR_CTRL__stop_bits__##f4_##_VAL(R_SERIAL0_TR_CTRL_, stop_bits_, v4) << R_SERIAL0_TR_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_stick_par__##f5_##_VAL(R_SERIAL0_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL0_TR_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_par__##f6_##_VAL(R_SERIAL0_TR_CTRL_, tr_par_, v6) << R_SERIAL0_TR_CTRL__tr_par__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_par_en__##f7_##_VAL(R_SERIAL0_TR_CTRL_, tr_par_en_, v7) << R_SERIAL0_TR_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL0_TR_CTRL__tr_bitnr__##f8_##_VAL(R_SERIAL0_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL0_TR_CTRL__tr_bitnr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_TR_DATA
+ * - type: WO
+ * - addr: 0xb0000060
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL0_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_TR_DATA(f1,v1) ( \
+ *R_SERIAL0_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_TR_DATA_) \
+ REG_VAL__R_SERIAL0_TR_DATA_(f1##_,v1) \
+ ), \
+ R_SERIAL0_TR_DATA__WRITE(R_SERIAL0_TR_DATA__ADDR, *R_SERIAL0_TR_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_TR_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL0_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_TR_DATA__SHADOW(f1,v1) ( \
+ *R_SERIAL0_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_TR_DATA_) \
+ REG_VAL__R_SERIAL0_TR_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_TR_DATA(f1,v1) ( \
+ (R_SERIAL0_TR_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_TR_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_TR_DATA(f1,v1) ( \
+ (R_SERIAL0_TR_DATA__data_out__##f1##__VAL(R_SERIAL0_TR_DATA_, data_out_, v1) << R_SERIAL0_TR_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_TR_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_TR_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_TR_DATA_(f1_,v1) ( \
+ (R_SERIAL0_TR_DATA__data_out__##f1_##_VAL(R_SERIAL0_TR_DATA_, data_out_, v1) << R_SERIAL0_TR_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL0_XOFF
+ * - type: WO
+ * - addr: 0xb0000064
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_XOFF.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL0_XOFF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ *R_SERIAL0_XOFF__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_XOFF_) \
+ REG_VAL__R_SERIAL0_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ), \
+ R_SERIAL0_XOFF__WRITE(R_SERIAL0_XOFF__ADDR, *R_SERIAL0_XOFF__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL0_XOFF__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL0_XOFF.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL0_XOFF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL0_XOFF__SHADOW(f1,v1,f2,v2,f3,v3) ( \
+ *R_SERIAL0_XOFF__SADDR = ( \
+ REG_INITIATED(R_SERIAL0_XOFF_) \
+ REG_VAL__R_SERIAL0_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL0_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL0_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ (R_SERIAL0_XOFF__tx_stop__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL0_XOFF__auto_xoff__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL0_XOFF__xoff_char__##f3##__MASK & REG__##v3) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_XOFF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ (R_SERIAL0_XOFF__tx_stop__##f1##__VAL(R_SERIAL0_XOFF_, tx_stop_, v1) << R_SERIAL0_XOFF__tx_stop__BITNR) | \
+ (R_SERIAL0_XOFF__auto_xoff__##f2##__VAL(R_SERIAL0_XOFF_, auto_xoff_, v2) << R_SERIAL0_XOFF__auto_xoff__BITNR) | \
+ (R_SERIAL0_XOFF__xoff_char__##f3##__VAL(R_SERIAL0_XOFF_, xoff_char_, v3) << R_SERIAL0_XOFF__xoff_char__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL0_XOFF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL0_XOFF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL0_XOFF_(f1_,v1,f2_,v2,f3_,v3) ( \
+ (R_SERIAL0_XOFF__tx_stop__##f1_##_VAL(R_SERIAL0_XOFF_, tx_stop_, v1) << R_SERIAL0_XOFF__tx_stop__BITNR) | \
+ (R_SERIAL0_XOFF__auto_xoff__##f2_##_VAL(R_SERIAL0_XOFF_, auto_xoff_, v2) << R_SERIAL0_XOFF__auto_xoff__BITNR) | \
+ (R_SERIAL0_XOFF__xoff_char__##f3_##_VAL(R_SERIAL0_XOFF_, xoff_char_, v3) << R_SERIAL0_XOFF__xoff_char__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_BAUD
+ * - type: WO
+ * - addr: 0xb000006b
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_BAUD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL1_BAUD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_BAUD(f1,v1,f2,v2) ( \
+ *R_SERIAL1_BAUD__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_BAUD_) \
+ REG_VAL__R_SERIAL1_BAUD_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_SERIAL1_BAUD__WRITE(R_SERIAL1_BAUD__ADDR, *R_SERIAL1_BAUD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_BAUD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_BAUD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL1_BAUD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_BAUD__SHADOW(f1,v1,f2,v2) ( \
+ *R_SERIAL1_BAUD__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_BAUD_) \
+ REG_VAL__R_SERIAL1_BAUD_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_BAUD(f1,v1,f2,v2) ( \
+ (R_SERIAL1_BAUD__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL1_BAUD__rec_baud__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_BAUD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_BAUD(f1,v1,f2,v2) ( \
+ (R_SERIAL1_BAUD__tr_baud__##f1##__VAL(R_SERIAL1_BAUD_, tr_baud_, v1) << R_SERIAL1_BAUD__tr_baud__BITNR) | \
+ (R_SERIAL1_BAUD__rec_baud__##f2##__VAL(R_SERIAL1_BAUD_, rec_baud_, v2) << R_SERIAL1_BAUD__rec_baud__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_BAUD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_BAUD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_BAUD_(f1_,v1,f2_,v2) ( \
+ (R_SERIAL1_BAUD__tr_baud__##f1_##_VAL(R_SERIAL1_BAUD_, tr_baud_, v1) << R_SERIAL1_BAUD__tr_baud__BITNR) | \
+ (R_SERIAL1_BAUD__rec_baud__##f2_##_VAL(R_SERIAL1_BAUD_, rec_baud_, v2) << R_SERIAL1_BAUD__rec_baud__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_CTRL
+ * - type: WO
+ * - addr: 0xb0000068
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL1_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_SERIAL1_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_CTRL_) \
+ REG_VAL__R_SERIAL1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ), \
+ R_SERIAL1_CTRL__WRITE(R_SERIAL1_CTRL__ADDR, *R_SERIAL1_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL1_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_SERIAL1_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_CTRL_) \
+ REG_VAL__R_SERIAL1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_SERIAL1_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL1_CTRL__rec_baud__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL1_CTRL__dma_err__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL1_CTRL__rec_enable__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL1_CTRL__rts___##f5##__MASK & REG__##v5) | \
+ (R_SERIAL1_CTRL__sampling__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL1_CTRL__rec_stick_par__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL1_CTRL__rec_par__##f8##__MASK & REG__##v8) | \
+ (R_SERIAL1_CTRL__rec_par_en__##f9##__MASK & REG__##v9) | \
+ (R_SERIAL1_CTRL__rec_bitnr__##f10##__MASK & REG__##v10) | \
+ (R_SERIAL1_CTRL__txd__##f11##__MASK & REG__##v11) | \
+ (R_SERIAL1_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \
+ (R_SERIAL1_CTRL__auto_cts__##f13##__MASK & REG__##v13) | \
+ (R_SERIAL1_CTRL__stop_bits__##f14##__MASK & REG__##v14) | \
+ (R_SERIAL1_CTRL__tr_stick_par__##f15##__MASK & REG__##v15) | \
+ (R_SERIAL1_CTRL__tr_par__##f16##__MASK & REG__##v16) | \
+ (R_SERIAL1_CTRL__tr_par_en__##f17##__MASK & REG__##v17) | \
+ (R_SERIAL1_CTRL__tr_bitnr__##f18##__MASK & REG__##v18) | \
+ (R_SERIAL1_CTRL__data_out__##f19##__MASK & REG__##v19) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_SERIAL1_CTRL__tr_baud__##f1##__VAL(R_SERIAL1_CTRL_, tr_baud_, v1) << R_SERIAL1_CTRL__tr_baud__BITNR) | \
+ (R_SERIAL1_CTRL__rec_baud__##f2##__VAL(R_SERIAL1_CTRL_, rec_baud_, v2) << R_SERIAL1_CTRL__rec_baud__BITNR) | \
+ (R_SERIAL1_CTRL__dma_err__##f3##__VAL(R_SERIAL1_CTRL_, dma_err_, v3) << R_SERIAL1_CTRL__dma_err__BITNR) | \
+ (R_SERIAL1_CTRL__rec_enable__##f4##__VAL(R_SERIAL1_CTRL_, rec_enable_, v4) << R_SERIAL1_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL1_CTRL__rts___##f5##__VAL(R_SERIAL1_CTRL_, rts__, v5) << R_SERIAL1_CTRL__rts___BITNR) | \
+ (R_SERIAL1_CTRL__sampling__##f6##__VAL(R_SERIAL1_CTRL_, sampling_, v6) << R_SERIAL1_CTRL__sampling__BITNR) | \
+ (R_SERIAL1_CTRL__rec_stick_par__##f7##__VAL(R_SERIAL1_CTRL_, rec_stick_par_, v7) << R_SERIAL1_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL1_CTRL__rec_par__##f8##__VAL(R_SERIAL1_CTRL_, rec_par_, v8) << R_SERIAL1_CTRL__rec_par__BITNR) | \
+ (R_SERIAL1_CTRL__rec_par_en__##f9##__VAL(R_SERIAL1_CTRL_, rec_par_en_, v9) << R_SERIAL1_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL1_CTRL__rec_bitnr__##f10##__VAL(R_SERIAL1_CTRL_, rec_bitnr_, v10) << R_SERIAL1_CTRL__rec_bitnr__BITNR) | \
+ (R_SERIAL1_CTRL__txd__##f11##__VAL(R_SERIAL1_CTRL_, txd_, v11) << R_SERIAL1_CTRL__txd__BITNR) | \
+ (R_SERIAL1_CTRL__tr_enable__##f12##__VAL(R_SERIAL1_CTRL_, tr_enable_, v12) << R_SERIAL1_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL1_CTRL__auto_cts__##f13##__VAL(R_SERIAL1_CTRL_, auto_cts_, v13) << R_SERIAL1_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL1_CTRL__stop_bits__##f14##__VAL(R_SERIAL1_CTRL_, stop_bits_, v14) << R_SERIAL1_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL1_CTRL__tr_stick_par__##f15##__VAL(R_SERIAL1_CTRL_, tr_stick_par_, v15) << R_SERIAL1_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL1_CTRL__tr_par__##f16##__VAL(R_SERIAL1_CTRL_, tr_par_, v16) << R_SERIAL1_CTRL__tr_par__BITNR) | \
+ (R_SERIAL1_CTRL__tr_par_en__##f17##__VAL(R_SERIAL1_CTRL_, tr_par_en_, v17) << R_SERIAL1_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL1_CTRL__tr_bitnr__##f18##__VAL(R_SERIAL1_CTRL_, tr_bitnr_, v18) << R_SERIAL1_CTRL__tr_bitnr__BITNR) | \
+ (R_SERIAL1_CTRL__data_out__##f19##__VAL(R_SERIAL1_CTRL_, data_out_, v19) << R_SERIAL1_CTRL__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \
+ (R_SERIAL1_CTRL__tr_baud__##f1_##_VAL(R_SERIAL1_CTRL_, tr_baud_, v1) << R_SERIAL1_CTRL__tr_baud__BITNR) | \
+ (R_SERIAL1_CTRL__rec_baud__##f2_##_VAL(R_SERIAL1_CTRL_, rec_baud_, v2) << R_SERIAL1_CTRL__rec_baud__BITNR) | \
+ (R_SERIAL1_CTRL__dma_err__##f3_##_VAL(R_SERIAL1_CTRL_, dma_err_, v3) << R_SERIAL1_CTRL__dma_err__BITNR) | \
+ (R_SERIAL1_CTRL__rec_enable__##f4_##_VAL(R_SERIAL1_CTRL_, rec_enable_, v4) << R_SERIAL1_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL1_CTRL__rts___##f5_##_VAL(R_SERIAL1_CTRL_, rts__, v5) << R_SERIAL1_CTRL__rts___BITNR) | \
+ (R_SERIAL1_CTRL__sampling__##f6_##_VAL(R_SERIAL1_CTRL_, sampling_, v6) << R_SERIAL1_CTRL__sampling__BITNR) | \
+ (R_SERIAL1_CTRL__rec_stick_par__##f7_##_VAL(R_SERIAL1_CTRL_, rec_stick_par_, v7) << R_SERIAL1_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL1_CTRL__rec_par__##f8_##_VAL(R_SERIAL1_CTRL_, rec_par_, v8) << R_SERIAL1_CTRL__rec_par__BITNR) | \
+ (R_SERIAL1_CTRL__rec_par_en__##f9_##_VAL(R_SERIAL1_CTRL_, rec_par_en_, v9) << R_SERIAL1_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL1_CTRL__rec_bitnr__##f10_##_VAL(R_SERIAL1_CTRL_, rec_bitnr_, v10) << R_SERIAL1_CTRL__rec_bitnr__BITNR) | \
+ (R_SERIAL1_CTRL__txd__##f11_##_VAL(R_SERIAL1_CTRL_, txd_, v11) << R_SERIAL1_CTRL__txd__BITNR) | \
+ (R_SERIAL1_CTRL__tr_enable__##f12_##_VAL(R_SERIAL1_CTRL_, tr_enable_, v12) << R_SERIAL1_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL1_CTRL__auto_cts__##f13_##_VAL(R_SERIAL1_CTRL_, auto_cts_, v13) << R_SERIAL1_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL1_CTRL__stop_bits__##f14_##_VAL(R_SERIAL1_CTRL_, stop_bits_, v14) << R_SERIAL1_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL1_CTRL__tr_stick_par__##f15_##_VAL(R_SERIAL1_CTRL_, tr_stick_par_, v15) << R_SERIAL1_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL1_CTRL__tr_par__##f16_##_VAL(R_SERIAL1_CTRL_, tr_par_, v16) << R_SERIAL1_CTRL__tr_par__BITNR) | \
+ (R_SERIAL1_CTRL__tr_par_en__##f17_##_VAL(R_SERIAL1_CTRL_, tr_par_en_, v17) << R_SERIAL1_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL1_CTRL__tr_bitnr__##f18_##_VAL(R_SERIAL1_CTRL_, tr_bitnr_, v18) << R_SERIAL1_CTRL__tr_bitnr__BITNR) | \
+ (R_SERIAL1_CTRL__data_out__##f19_##_VAL(R_SERIAL1_CTRL_, data_out_, v19) << R_SERIAL1_CTRL__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_READ
+ * - type: RO
+ * - addr: 0xb0000068
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SERIAL1_READ__xoff_detect__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL1_READ__cts___##f2##__MASK & REG__##v2) | \
+ (R_SERIAL1_READ__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL1_READ__rxd__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL1_READ__overrun__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL1_READ__par_err__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL1_READ__framing_err__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL1_READ__data_avail__##f8##__MASK & REG__##v8) | \
+ (R_SERIAL1_READ__data_in__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SERIAL1_READ__xoff_detect__##f1##__VAL(R_SERIAL1_READ_, xoff_detect_, v1) << R_SERIAL1_READ__xoff_detect__BITNR) | \
+ (R_SERIAL1_READ__cts___##f2##__VAL(R_SERIAL1_READ_, cts__, v2) << R_SERIAL1_READ__cts___BITNR) | \
+ (R_SERIAL1_READ__tr_ready__##f3##__VAL(R_SERIAL1_READ_, tr_ready_, v3) << R_SERIAL1_READ__tr_ready__BITNR) | \
+ (R_SERIAL1_READ__rxd__##f4##__VAL(R_SERIAL1_READ_, rxd_, v4) << R_SERIAL1_READ__rxd__BITNR) | \
+ (R_SERIAL1_READ__overrun__##f5##__VAL(R_SERIAL1_READ_, overrun_, v5) << R_SERIAL1_READ__overrun__BITNR) | \
+ (R_SERIAL1_READ__par_err__##f6##__VAL(R_SERIAL1_READ_, par_err_, v6) << R_SERIAL1_READ__par_err__BITNR) | \
+ (R_SERIAL1_READ__framing_err__##f7##__VAL(R_SERIAL1_READ_, framing_err_, v7) << R_SERIAL1_READ__framing_err__BITNR) | \
+ (R_SERIAL1_READ__data_avail__##f8##__VAL(R_SERIAL1_READ_, data_avail_, v8) << R_SERIAL1_READ__data_avail__BITNR) | \
+ (R_SERIAL1_READ__data_in__##f9##__VAL(R_SERIAL1_READ_, data_in_, v9) << R_SERIAL1_READ__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_SERIAL1_READ__xoff_detect__##f1_##_VAL(R_SERIAL1_READ_, xoff_detect_, v1) << R_SERIAL1_READ__xoff_detect__BITNR) | \
+ (R_SERIAL1_READ__cts___##f2_##_VAL(R_SERIAL1_READ_, cts__, v2) << R_SERIAL1_READ__cts___BITNR) | \
+ (R_SERIAL1_READ__tr_ready__##f3_##_VAL(R_SERIAL1_READ_, tr_ready_, v3) << R_SERIAL1_READ__tr_ready__BITNR) | \
+ (R_SERIAL1_READ__rxd__##f4_##_VAL(R_SERIAL1_READ_, rxd_, v4) << R_SERIAL1_READ__rxd__BITNR) | \
+ (R_SERIAL1_READ__overrun__##f5_##_VAL(R_SERIAL1_READ_, overrun_, v5) << R_SERIAL1_READ__overrun__BITNR) | \
+ (R_SERIAL1_READ__par_err__##f6_##_VAL(R_SERIAL1_READ_, par_err_, v6) << R_SERIAL1_READ__par_err__BITNR) | \
+ (R_SERIAL1_READ__framing_err__##f7_##_VAL(R_SERIAL1_READ_, framing_err_, v7) << R_SERIAL1_READ__framing_err__BITNR) | \
+ (R_SERIAL1_READ__data_avail__##f8_##_VAL(R_SERIAL1_READ_, data_avail_, v8) << R_SERIAL1_READ__data_avail__BITNR) | \
+ (R_SERIAL1_READ__data_in__##f9_##_VAL(R_SERIAL1_READ_, data_in_, v9) << R_SERIAL1_READ__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_REC_CTRL
+ * - type: WO
+ * - addr: 0xb000006a
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_REC_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL1_REC_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL1_REC_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_REC_CTRL_) \
+ REG_VAL__R_SERIAL1_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SERIAL1_REC_CTRL__WRITE(R_SERIAL1_REC_CTRL__ADDR, *R_SERIAL1_REC_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_REC_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_REC_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL1_REC_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_REC_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL1_REC_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_REC_CTRL_) \
+ REG_VAL__R_SERIAL1_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL1_REC_CTRL__dma_err__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL1_REC_CTRL__rec_enable__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL1_REC_CTRL__rts___##f3##__MASK & REG__##v3) | \
+ (R_SERIAL1_REC_CTRL__sampling__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL1_REC_CTRL__rec_stick_par__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL1_REC_CTRL__rec_par__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL1_REC_CTRL__rec_par_en__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL1_REC_CTRL__rec_bitnr__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_REC_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL1_REC_CTRL__dma_err__##f1##__VAL(R_SERIAL1_REC_CTRL_, dma_err_, v1) << R_SERIAL1_REC_CTRL__dma_err__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_enable__##f2##__VAL(R_SERIAL1_REC_CTRL_, rec_enable_, v2) << R_SERIAL1_REC_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rts___##f3##__VAL(R_SERIAL1_REC_CTRL_, rts__, v3) << R_SERIAL1_REC_CTRL__rts___BITNR) | \
+ (R_SERIAL1_REC_CTRL__sampling__##f4##__VAL(R_SERIAL1_REC_CTRL_, sampling_, v4) << R_SERIAL1_REC_CTRL__sampling__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_stick_par__##f5##__VAL(R_SERIAL1_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL1_REC_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_par__##f6##__VAL(R_SERIAL1_REC_CTRL_, rec_par_, v6) << R_SERIAL1_REC_CTRL__rec_par__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_par_en__##f7##__VAL(R_SERIAL1_REC_CTRL_, rec_par_en_, v7) << R_SERIAL1_REC_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_bitnr__##f8##__VAL(R_SERIAL1_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL1_REC_CTRL__rec_bitnr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_REC_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_REC_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_REC_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL1_REC_CTRL__dma_err__##f1_##_VAL(R_SERIAL1_REC_CTRL_, dma_err_, v1) << R_SERIAL1_REC_CTRL__dma_err__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_enable__##f2_##_VAL(R_SERIAL1_REC_CTRL_, rec_enable_, v2) << R_SERIAL1_REC_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rts___##f3_##_VAL(R_SERIAL1_REC_CTRL_, rts__, v3) << R_SERIAL1_REC_CTRL__rts___BITNR) | \
+ (R_SERIAL1_REC_CTRL__sampling__##f4_##_VAL(R_SERIAL1_REC_CTRL_, sampling_, v4) << R_SERIAL1_REC_CTRL__sampling__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_stick_par__##f5_##_VAL(R_SERIAL1_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL1_REC_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_par__##f6_##_VAL(R_SERIAL1_REC_CTRL_, rec_par_, v6) << R_SERIAL1_REC_CTRL__rec_par__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_par_en__##f7_##_VAL(R_SERIAL1_REC_CTRL_, rec_par_en_, v7) << R_SERIAL1_REC_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL1_REC_CTRL__rec_bitnr__##f8_##_VAL(R_SERIAL1_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL1_REC_CTRL__rec_bitnr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_REC_DATA
+ * - type: RO
+ * - addr: 0xb0000068
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_REC_DATA(f1,v1) ( \
+ (R_SERIAL1_REC_DATA__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_REC_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_REC_DATA(f1,v1) ( \
+ (R_SERIAL1_REC_DATA__data_in__##f1##__VAL(R_SERIAL1_REC_DATA_, data_in_, v1) << R_SERIAL1_REC_DATA__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_REC_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_REC_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_REC_DATA_(f1_,v1) ( \
+ (R_SERIAL1_REC_DATA__data_in__##f1_##_VAL(R_SERIAL1_REC_DATA_, data_in_, v1) << R_SERIAL1_REC_DATA__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_STATUS
+ * - type: RO
+ * - addr: 0xb0000069
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL1_STATUS__xoff_detect__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL1_STATUS__cts___##f2##__MASK & REG__##v2) | \
+ (R_SERIAL1_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL1_STATUS__rxd__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL1_STATUS__overrun__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL1_STATUS__par_err__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL1_STATUS__framing_err__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL1_STATUS__data_avail__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL1_STATUS__xoff_detect__##f1##__VAL(R_SERIAL1_STATUS_, xoff_detect_, v1) << R_SERIAL1_STATUS__xoff_detect__BITNR) | \
+ (R_SERIAL1_STATUS__cts___##f2##__VAL(R_SERIAL1_STATUS_, cts__, v2) << R_SERIAL1_STATUS__cts___BITNR) | \
+ (R_SERIAL1_STATUS__tr_ready__##f3##__VAL(R_SERIAL1_STATUS_, tr_ready_, v3) << R_SERIAL1_STATUS__tr_ready__BITNR) | \
+ (R_SERIAL1_STATUS__rxd__##f4##__VAL(R_SERIAL1_STATUS_, rxd_, v4) << R_SERIAL1_STATUS__rxd__BITNR) | \
+ (R_SERIAL1_STATUS__overrun__##f5##__VAL(R_SERIAL1_STATUS_, overrun_, v5) << R_SERIAL1_STATUS__overrun__BITNR) | \
+ (R_SERIAL1_STATUS__par_err__##f6##__VAL(R_SERIAL1_STATUS_, par_err_, v6) << R_SERIAL1_STATUS__par_err__BITNR) | \
+ (R_SERIAL1_STATUS__framing_err__##f7##__VAL(R_SERIAL1_STATUS_, framing_err_, v7) << R_SERIAL1_STATUS__framing_err__BITNR) | \
+ (R_SERIAL1_STATUS__data_avail__##f8##__VAL(R_SERIAL1_STATUS_, data_avail_, v8) << R_SERIAL1_STATUS__data_avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL1_STATUS__xoff_detect__##f1_##_VAL(R_SERIAL1_STATUS_, xoff_detect_, v1) << R_SERIAL1_STATUS__xoff_detect__BITNR) | \
+ (R_SERIAL1_STATUS__cts___##f2_##_VAL(R_SERIAL1_STATUS_, cts__, v2) << R_SERIAL1_STATUS__cts___BITNR) | \
+ (R_SERIAL1_STATUS__tr_ready__##f3_##_VAL(R_SERIAL1_STATUS_, tr_ready_, v3) << R_SERIAL1_STATUS__tr_ready__BITNR) | \
+ (R_SERIAL1_STATUS__rxd__##f4_##_VAL(R_SERIAL1_STATUS_, rxd_, v4) << R_SERIAL1_STATUS__rxd__BITNR) | \
+ (R_SERIAL1_STATUS__overrun__##f5_##_VAL(R_SERIAL1_STATUS_, overrun_, v5) << R_SERIAL1_STATUS__overrun__BITNR) | \
+ (R_SERIAL1_STATUS__par_err__##f6_##_VAL(R_SERIAL1_STATUS_, par_err_, v6) << R_SERIAL1_STATUS__par_err__BITNR) | \
+ (R_SERIAL1_STATUS__framing_err__##f7_##_VAL(R_SERIAL1_STATUS_, framing_err_, v7) << R_SERIAL1_STATUS__framing_err__BITNR) | \
+ (R_SERIAL1_STATUS__data_avail__##f8_##_VAL(R_SERIAL1_STATUS_, data_avail_, v8) << R_SERIAL1_STATUS__data_avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_TR_CTRL
+ * - type: WO
+ * - addr: 0xb0000069
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL1_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL1_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_TR_CTRL_) \
+ REG_VAL__R_SERIAL1_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SERIAL1_TR_CTRL__WRITE(R_SERIAL1_TR_CTRL__ADDR, *R_SERIAL1_TR_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_TR_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL1_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL1_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_TR_CTRL_) \
+ REG_VAL__R_SERIAL1_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL1_TR_CTRL__txd__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL1_TR_CTRL__tr_enable__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL1_TR_CTRL__auto_cts__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL1_TR_CTRL__stop_bits__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL1_TR_CTRL__tr_stick_par__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL1_TR_CTRL__tr_par__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL1_TR_CTRL__tr_par_en__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL1_TR_CTRL__tr_bitnr__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_TR_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL1_TR_CTRL__txd__##f1##__VAL(R_SERIAL1_TR_CTRL_, txd_, v1) << R_SERIAL1_TR_CTRL__txd__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_enable__##f2##__VAL(R_SERIAL1_TR_CTRL_, tr_enable_, v2) << R_SERIAL1_TR_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL1_TR_CTRL__auto_cts__##f3##__VAL(R_SERIAL1_TR_CTRL_, auto_cts_, v3) << R_SERIAL1_TR_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL1_TR_CTRL__stop_bits__##f4##__VAL(R_SERIAL1_TR_CTRL_, stop_bits_, v4) << R_SERIAL1_TR_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_stick_par__##f5##__VAL(R_SERIAL1_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL1_TR_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_par__##f6##__VAL(R_SERIAL1_TR_CTRL_, tr_par_, v6) << R_SERIAL1_TR_CTRL__tr_par__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_par_en__##f7##__VAL(R_SERIAL1_TR_CTRL_, tr_par_en_, v7) << R_SERIAL1_TR_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_bitnr__##f8##__VAL(R_SERIAL1_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL1_TR_CTRL__tr_bitnr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_TR_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_TR_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL1_TR_CTRL__txd__##f1_##_VAL(R_SERIAL1_TR_CTRL_, txd_, v1) << R_SERIAL1_TR_CTRL__txd__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_enable__##f2_##_VAL(R_SERIAL1_TR_CTRL_, tr_enable_, v2) << R_SERIAL1_TR_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL1_TR_CTRL__auto_cts__##f3_##_VAL(R_SERIAL1_TR_CTRL_, auto_cts_, v3) << R_SERIAL1_TR_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL1_TR_CTRL__stop_bits__##f4_##_VAL(R_SERIAL1_TR_CTRL_, stop_bits_, v4) << R_SERIAL1_TR_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_stick_par__##f5_##_VAL(R_SERIAL1_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL1_TR_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_par__##f6_##_VAL(R_SERIAL1_TR_CTRL_, tr_par_, v6) << R_SERIAL1_TR_CTRL__tr_par__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_par_en__##f7_##_VAL(R_SERIAL1_TR_CTRL_, tr_par_en_, v7) << R_SERIAL1_TR_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL1_TR_CTRL__tr_bitnr__##f8_##_VAL(R_SERIAL1_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL1_TR_CTRL__tr_bitnr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_TR_DATA
+ * - type: WO
+ * - addr: 0xb0000068
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL1_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_TR_DATA(f1,v1) ( \
+ *R_SERIAL1_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_TR_DATA_) \
+ REG_VAL__R_SERIAL1_TR_DATA_(f1##_,v1) \
+ ), \
+ R_SERIAL1_TR_DATA__WRITE(R_SERIAL1_TR_DATA__ADDR, *R_SERIAL1_TR_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_TR_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL1_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_TR_DATA__SHADOW(f1,v1) ( \
+ *R_SERIAL1_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_TR_DATA_) \
+ REG_VAL__R_SERIAL1_TR_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_TR_DATA(f1,v1) ( \
+ (R_SERIAL1_TR_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_TR_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_TR_DATA(f1,v1) ( \
+ (R_SERIAL1_TR_DATA__data_out__##f1##__VAL(R_SERIAL1_TR_DATA_, data_out_, v1) << R_SERIAL1_TR_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_TR_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_TR_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_TR_DATA_(f1_,v1) ( \
+ (R_SERIAL1_TR_DATA__data_out__##f1_##_VAL(R_SERIAL1_TR_DATA_, data_out_, v1) << R_SERIAL1_TR_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL1_XOFF
+ * - type: WO
+ * - addr: 0xb000006c
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_XOFF.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL1_XOFF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ *R_SERIAL1_XOFF__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_XOFF_) \
+ REG_VAL__R_SERIAL1_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ), \
+ R_SERIAL1_XOFF__WRITE(R_SERIAL1_XOFF__ADDR, *R_SERIAL1_XOFF__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL1_XOFF__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL1_XOFF.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL1_XOFF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL1_XOFF__SHADOW(f1,v1,f2,v2,f3,v3) ( \
+ *R_SERIAL1_XOFF__SADDR = ( \
+ REG_INITIATED(R_SERIAL1_XOFF_) \
+ REG_VAL__R_SERIAL1_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL1_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL1_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ (R_SERIAL1_XOFF__tx_stop__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL1_XOFF__auto_xoff__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL1_XOFF__xoff_char__##f3##__MASK & REG__##v3) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_XOFF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ (R_SERIAL1_XOFF__tx_stop__##f1##__VAL(R_SERIAL1_XOFF_, tx_stop_, v1) << R_SERIAL1_XOFF__tx_stop__BITNR) | \
+ (R_SERIAL1_XOFF__auto_xoff__##f2##__VAL(R_SERIAL1_XOFF_, auto_xoff_, v2) << R_SERIAL1_XOFF__auto_xoff__BITNR) | \
+ (R_SERIAL1_XOFF__xoff_char__##f3##__VAL(R_SERIAL1_XOFF_, xoff_char_, v3) << R_SERIAL1_XOFF__xoff_char__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL1_XOFF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL1_XOFF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL1_XOFF_(f1_,v1,f2_,v2,f3_,v3) ( \
+ (R_SERIAL1_XOFF__tx_stop__##f1_##_VAL(R_SERIAL1_XOFF_, tx_stop_, v1) << R_SERIAL1_XOFF__tx_stop__BITNR) | \
+ (R_SERIAL1_XOFF__auto_xoff__##f2_##_VAL(R_SERIAL1_XOFF_, auto_xoff_, v2) << R_SERIAL1_XOFF__auto_xoff__BITNR) | \
+ (R_SERIAL1_XOFF__xoff_char__##f3_##_VAL(R_SERIAL1_XOFF_, xoff_char_, v3) << R_SERIAL1_XOFF__xoff_char__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_BAUD
+ * - type: WO
+ * - addr: 0xb0000073
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_BAUD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL2_BAUD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_BAUD(f1,v1,f2,v2) ( \
+ *R_SERIAL2_BAUD__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_BAUD_) \
+ REG_VAL__R_SERIAL2_BAUD_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_SERIAL2_BAUD__WRITE(R_SERIAL2_BAUD__ADDR, *R_SERIAL2_BAUD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_BAUD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_BAUD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL2_BAUD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_BAUD__SHADOW(f1,v1,f2,v2) ( \
+ *R_SERIAL2_BAUD__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_BAUD_) \
+ REG_VAL__R_SERIAL2_BAUD_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_BAUD(f1,v1,f2,v2) ( \
+ (R_SERIAL2_BAUD__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL2_BAUD__rec_baud__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_BAUD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_BAUD(f1,v1,f2,v2) ( \
+ (R_SERIAL2_BAUD__tr_baud__##f1##__VAL(R_SERIAL2_BAUD_, tr_baud_, v1) << R_SERIAL2_BAUD__tr_baud__BITNR) | \
+ (R_SERIAL2_BAUD__rec_baud__##f2##__VAL(R_SERIAL2_BAUD_, rec_baud_, v2) << R_SERIAL2_BAUD__rec_baud__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_BAUD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_BAUD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_BAUD_(f1_,v1,f2_,v2) ( \
+ (R_SERIAL2_BAUD__tr_baud__##f1_##_VAL(R_SERIAL2_BAUD_, tr_baud_, v1) << R_SERIAL2_BAUD__tr_baud__BITNR) | \
+ (R_SERIAL2_BAUD__rec_baud__##f2_##_VAL(R_SERIAL2_BAUD_, rec_baud_, v2) << R_SERIAL2_BAUD__rec_baud__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_CTRL
+ * - type: WO
+ * - addr: 0xb0000070
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL2_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_SERIAL2_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_CTRL_) \
+ REG_VAL__R_SERIAL2_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ), \
+ R_SERIAL2_CTRL__WRITE(R_SERIAL2_CTRL__ADDR, *R_SERIAL2_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL2_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_SERIAL2_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_CTRL_) \
+ REG_VAL__R_SERIAL2_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_SERIAL2_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL2_CTRL__rec_baud__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL2_CTRL__dma_err__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL2_CTRL__rec_enable__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL2_CTRL__rts___##f5##__MASK & REG__##v5) | \
+ (R_SERIAL2_CTRL__sampling__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL2_CTRL__rec_stick_par__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL2_CTRL__rec_par__##f8##__MASK & REG__##v8) | \
+ (R_SERIAL2_CTRL__rec_par_en__##f9##__MASK & REG__##v9) | \
+ (R_SERIAL2_CTRL__rec_bitnr__##f10##__MASK & REG__##v10) | \
+ (R_SERIAL2_CTRL__txd__##f11##__MASK & REG__##v11) | \
+ (R_SERIAL2_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \
+ (R_SERIAL2_CTRL__auto_cts__##f13##__MASK & REG__##v13) | \
+ (R_SERIAL2_CTRL__stop_bits__##f14##__MASK & REG__##v14) | \
+ (R_SERIAL2_CTRL__tr_stick_par__##f15##__MASK & REG__##v15) | \
+ (R_SERIAL2_CTRL__tr_par__##f16##__MASK & REG__##v16) | \
+ (R_SERIAL2_CTRL__tr_par_en__##f17##__MASK & REG__##v17) | \
+ (R_SERIAL2_CTRL__tr_bitnr__##f18##__MASK & REG__##v18) | \
+ (R_SERIAL2_CTRL__data_out__##f19##__MASK & REG__##v19) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_SERIAL2_CTRL__tr_baud__##f1##__VAL(R_SERIAL2_CTRL_, tr_baud_, v1) << R_SERIAL2_CTRL__tr_baud__BITNR) | \
+ (R_SERIAL2_CTRL__rec_baud__##f2##__VAL(R_SERIAL2_CTRL_, rec_baud_, v2) << R_SERIAL2_CTRL__rec_baud__BITNR) | \
+ (R_SERIAL2_CTRL__dma_err__##f3##__VAL(R_SERIAL2_CTRL_, dma_err_, v3) << R_SERIAL2_CTRL__dma_err__BITNR) | \
+ (R_SERIAL2_CTRL__rec_enable__##f4##__VAL(R_SERIAL2_CTRL_, rec_enable_, v4) << R_SERIAL2_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL2_CTRL__rts___##f5##__VAL(R_SERIAL2_CTRL_, rts__, v5) << R_SERIAL2_CTRL__rts___BITNR) | \
+ (R_SERIAL2_CTRL__sampling__##f6##__VAL(R_SERIAL2_CTRL_, sampling_, v6) << R_SERIAL2_CTRL__sampling__BITNR) | \
+ (R_SERIAL2_CTRL__rec_stick_par__##f7##__VAL(R_SERIAL2_CTRL_, rec_stick_par_, v7) << R_SERIAL2_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL2_CTRL__rec_par__##f8##__VAL(R_SERIAL2_CTRL_, rec_par_, v8) << R_SERIAL2_CTRL__rec_par__BITNR) | \
+ (R_SERIAL2_CTRL__rec_par_en__##f9##__VAL(R_SERIAL2_CTRL_, rec_par_en_, v9) << R_SERIAL2_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL2_CTRL__rec_bitnr__##f10##__VAL(R_SERIAL2_CTRL_, rec_bitnr_, v10) << R_SERIAL2_CTRL__rec_bitnr__BITNR) | \
+ (R_SERIAL2_CTRL__txd__##f11##__VAL(R_SERIAL2_CTRL_, txd_, v11) << R_SERIAL2_CTRL__txd__BITNR) | \
+ (R_SERIAL2_CTRL__tr_enable__##f12##__VAL(R_SERIAL2_CTRL_, tr_enable_, v12) << R_SERIAL2_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL2_CTRL__auto_cts__##f13##__VAL(R_SERIAL2_CTRL_, auto_cts_, v13) << R_SERIAL2_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL2_CTRL__stop_bits__##f14##__VAL(R_SERIAL2_CTRL_, stop_bits_, v14) << R_SERIAL2_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL2_CTRL__tr_stick_par__##f15##__VAL(R_SERIAL2_CTRL_, tr_stick_par_, v15) << R_SERIAL2_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL2_CTRL__tr_par__##f16##__VAL(R_SERIAL2_CTRL_, tr_par_, v16) << R_SERIAL2_CTRL__tr_par__BITNR) | \
+ (R_SERIAL2_CTRL__tr_par_en__##f17##__VAL(R_SERIAL2_CTRL_, tr_par_en_, v17) << R_SERIAL2_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL2_CTRL__tr_bitnr__##f18##__VAL(R_SERIAL2_CTRL_, tr_bitnr_, v18) << R_SERIAL2_CTRL__tr_bitnr__BITNR) | \
+ (R_SERIAL2_CTRL__data_out__##f19##__VAL(R_SERIAL2_CTRL_, data_out_, v19) << R_SERIAL2_CTRL__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \
+ (R_SERIAL2_CTRL__tr_baud__##f1_##_VAL(R_SERIAL2_CTRL_, tr_baud_, v1) << R_SERIAL2_CTRL__tr_baud__BITNR) | \
+ (R_SERIAL2_CTRL__rec_baud__##f2_##_VAL(R_SERIAL2_CTRL_, rec_baud_, v2) << R_SERIAL2_CTRL__rec_baud__BITNR) | \
+ (R_SERIAL2_CTRL__dma_err__##f3_##_VAL(R_SERIAL2_CTRL_, dma_err_, v3) << R_SERIAL2_CTRL__dma_err__BITNR) | \
+ (R_SERIAL2_CTRL__rec_enable__##f4_##_VAL(R_SERIAL2_CTRL_, rec_enable_, v4) << R_SERIAL2_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL2_CTRL__rts___##f5_##_VAL(R_SERIAL2_CTRL_, rts__, v5) << R_SERIAL2_CTRL__rts___BITNR) | \
+ (R_SERIAL2_CTRL__sampling__##f6_##_VAL(R_SERIAL2_CTRL_, sampling_, v6) << R_SERIAL2_CTRL__sampling__BITNR) | \
+ (R_SERIAL2_CTRL__rec_stick_par__##f7_##_VAL(R_SERIAL2_CTRL_, rec_stick_par_, v7) << R_SERIAL2_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL2_CTRL__rec_par__##f8_##_VAL(R_SERIAL2_CTRL_, rec_par_, v8) << R_SERIAL2_CTRL__rec_par__BITNR) | \
+ (R_SERIAL2_CTRL__rec_par_en__##f9_##_VAL(R_SERIAL2_CTRL_, rec_par_en_, v9) << R_SERIAL2_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL2_CTRL__rec_bitnr__##f10_##_VAL(R_SERIAL2_CTRL_, rec_bitnr_, v10) << R_SERIAL2_CTRL__rec_bitnr__BITNR) | \
+ (R_SERIAL2_CTRL__txd__##f11_##_VAL(R_SERIAL2_CTRL_, txd_, v11) << R_SERIAL2_CTRL__txd__BITNR) | \
+ (R_SERIAL2_CTRL__tr_enable__##f12_##_VAL(R_SERIAL2_CTRL_, tr_enable_, v12) << R_SERIAL2_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL2_CTRL__auto_cts__##f13_##_VAL(R_SERIAL2_CTRL_, auto_cts_, v13) << R_SERIAL2_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL2_CTRL__stop_bits__##f14_##_VAL(R_SERIAL2_CTRL_, stop_bits_, v14) << R_SERIAL2_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL2_CTRL__tr_stick_par__##f15_##_VAL(R_SERIAL2_CTRL_, tr_stick_par_, v15) << R_SERIAL2_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL2_CTRL__tr_par__##f16_##_VAL(R_SERIAL2_CTRL_, tr_par_, v16) << R_SERIAL2_CTRL__tr_par__BITNR) | \
+ (R_SERIAL2_CTRL__tr_par_en__##f17_##_VAL(R_SERIAL2_CTRL_, tr_par_en_, v17) << R_SERIAL2_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL2_CTRL__tr_bitnr__##f18_##_VAL(R_SERIAL2_CTRL_, tr_bitnr_, v18) << R_SERIAL2_CTRL__tr_bitnr__BITNR) | \
+ (R_SERIAL2_CTRL__data_out__##f19_##_VAL(R_SERIAL2_CTRL_, data_out_, v19) << R_SERIAL2_CTRL__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_READ
+ * - type: RO
+ * - addr: 0xb0000070
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SERIAL2_READ__xoff_detect__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL2_READ__cts___##f2##__MASK & REG__##v2) | \
+ (R_SERIAL2_READ__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL2_READ__rxd__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL2_READ__overrun__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL2_READ__par_err__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL2_READ__framing_err__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL2_READ__data_avail__##f8##__MASK & REG__##v8) | \
+ (R_SERIAL2_READ__data_in__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SERIAL2_READ__xoff_detect__##f1##__VAL(R_SERIAL2_READ_, xoff_detect_, v1) << R_SERIAL2_READ__xoff_detect__BITNR) | \
+ (R_SERIAL2_READ__cts___##f2##__VAL(R_SERIAL2_READ_, cts__, v2) << R_SERIAL2_READ__cts___BITNR) | \
+ (R_SERIAL2_READ__tr_ready__##f3##__VAL(R_SERIAL2_READ_, tr_ready_, v3) << R_SERIAL2_READ__tr_ready__BITNR) | \
+ (R_SERIAL2_READ__rxd__##f4##__VAL(R_SERIAL2_READ_, rxd_, v4) << R_SERIAL2_READ__rxd__BITNR) | \
+ (R_SERIAL2_READ__overrun__##f5##__VAL(R_SERIAL2_READ_, overrun_, v5) << R_SERIAL2_READ__overrun__BITNR) | \
+ (R_SERIAL2_READ__par_err__##f6##__VAL(R_SERIAL2_READ_, par_err_, v6) << R_SERIAL2_READ__par_err__BITNR) | \
+ (R_SERIAL2_READ__framing_err__##f7##__VAL(R_SERIAL2_READ_, framing_err_, v7) << R_SERIAL2_READ__framing_err__BITNR) | \
+ (R_SERIAL2_READ__data_avail__##f8##__VAL(R_SERIAL2_READ_, data_avail_, v8) << R_SERIAL2_READ__data_avail__BITNR) | \
+ (R_SERIAL2_READ__data_in__##f9##__VAL(R_SERIAL2_READ_, data_in_, v9) << R_SERIAL2_READ__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_SERIAL2_READ__xoff_detect__##f1_##_VAL(R_SERIAL2_READ_, xoff_detect_, v1) << R_SERIAL2_READ__xoff_detect__BITNR) | \
+ (R_SERIAL2_READ__cts___##f2_##_VAL(R_SERIAL2_READ_, cts__, v2) << R_SERIAL2_READ__cts___BITNR) | \
+ (R_SERIAL2_READ__tr_ready__##f3_##_VAL(R_SERIAL2_READ_, tr_ready_, v3) << R_SERIAL2_READ__tr_ready__BITNR) | \
+ (R_SERIAL2_READ__rxd__##f4_##_VAL(R_SERIAL2_READ_, rxd_, v4) << R_SERIAL2_READ__rxd__BITNR) | \
+ (R_SERIAL2_READ__overrun__##f5_##_VAL(R_SERIAL2_READ_, overrun_, v5) << R_SERIAL2_READ__overrun__BITNR) | \
+ (R_SERIAL2_READ__par_err__##f6_##_VAL(R_SERIAL2_READ_, par_err_, v6) << R_SERIAL2_READ__par_err__BITNR) | \
+ (R_SERIAL2_READ__framing_err__##f7_##_VAL(R_SERIAL2_READ_, framing_err_, v7) << R_SERIAL2_READ__framing_err__BITNR) | \
+ (R_SERIAL2_READ__data_avail__##f8_##_VAL(R_SERIAL2_READ_, data_avail_, v8) << R_SERIAL2_READ__data_avail__BITNR) | \
+ (R_SERIAL2_READ__data_in__##f9_##_VAL(R_SERIAL2_READ_, data_in_, v9) << R_SERIAL2_READ__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_REC_CTRL
+ * - type: WO
+ * - addr: 0xb0000072
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_REC_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL2_REC_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL2_REC_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_REC_CTRL_) \
+ REG_VAL__R_SERIAL2_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SERIAL2_REC_CTRL__WRITE(R_SERIAL2_REC_CTRL__ADDR, *R_SERIAL2_REC_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_REC_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_REC_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL2_REC_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_REC_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL2_REC_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_REC_CTRL_) \
+ REG_VAL__R_SERIAL2_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL2_REC_CTRL__dma_err__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL2_REC_CTRL__rec_enable__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL2_REC_CTRL__rts___##f3##__MASK & REG__##v3) | \
+ (R_SERIAL2_REC_CTRL__sampling__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL2_REC_CTRL__rec_stick_par__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL2_REC_CTRL__rec_par__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL2_REC_CTRL__rec_par_en__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL2_REC_CTRL__rec_bitnr__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_REC_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL2_REC_CTRL__dma_err__##f1##__VAL(R_SERIAL2_REC_CTRL_, dma_err_, v1) << R_SERIAL2_REC_CTRL__dma_err__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_enable__##f2##__VAL(R_SERIAL2_REC_CTRL_, rec_enable_, v2) << R_SERIAL2_REC_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rts___##f3##__VAL(R_SERIAL2_REC_CTRL_, rts__, v3) << R_SERIAL2_REC_CTRL__rts___BITNR) | \
+ (R_SERIAL2_REC_CTRL__sampling__##f4##__VAL(R_SERIAL2_REC_CTRL_, sampling_, v4) << R_SERIAL2_REC_CTRL__sampling__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_stick_par__##f5##__VAL(R_SERIAL2_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL2_REC_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_par__##f6##__VAL(R_SERIAL2_REC_CTRL_, rec_par_, v6) << R_SERIAL2_REC_CTRL__rec_par__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_par_en__##f7##__VAL(R_SERIAL2_REC_CTRL_, rec_par_en_, v7) << R_SERIAL2_REC_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_bitnr__##f8##__VAL(R_SERIAL2_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL2_REC_CTRL__rec_bitnr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_REC_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_REC_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_REC_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL2_REC_CTRL__dma_err__##f1_##_VAL(R_SERIAL2_REC_CTRL_, dma_err_, v1) << R_SERIAL2_REC_CTRL__dma_err__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_enable__##f2_##_VAL(R_SERIAL2_REC_CTRL_, rec_enable_, v2) << R_SERIAL2_REC_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rts___##f3_##_VAL(R_SERIAL2_REC_CTRL_, rts__, v3) << R_SERIAL2_REC_CTRL__rts___BITNR) | \
+ (R_SERIAL2_REC_CTRL__sampling__##f4_##_VAL(R_SERIAL2_REC_CTRL_, sampling_, v4) << R_SERIAL2_REC_CTRL__sampling__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_stick_par__##f5_##_VAL(R_SERIAL2_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL2_REC_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_par__##f6_##_VAL(R_SERIAL2_REC_CTRL_, rec_par_, v6) << R_SERIAL2_REC_CTRL__rec_par__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_par_en__##f7_##_VAL(R_SERIAL2_REC_CTRL_, rec_par_en_, v7) << R_SERIAL2_REC_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL2_REC_CTRL__rec_bitnr__##f8_##_VAL(R_SERIAL2_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL2_REC_CTRL__rec_bitnr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_REC_DATA
+ * - type: RO
+ * - addr: 0xb0000070
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_REC_DATA(f1,v1) ( \
+ (R_SERIAL2_REC_DATA__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_REC_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_REC_DATA(f1,v1) ( \
+ (R_SERIAL2_REC_DATA__data_in__##f1##__VAL(R_SERIAL2_REC_DATA_, data_in_, v1) << R_SERIAL2_REC_DATA__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_REC_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_REC_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_REC_DATA_(f1_,v1) ( \
+ (R_SERIAL2_REC_DATA__data_in__##f1_##_VAL(R_SERIAL2_REC_DATA_, data_in_, v1) << R_SERIAL2_REC_DATA__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_STATUS
+ * - type: RO
+ * - addr: 0xb0000071
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL2_STATUS__xoff_detect__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL2_STATUS__cts___##f2##__MASK & REG__##v2) | \
+ (R_SERIAL2_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL2_STATUS__rxd__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL2_STATUS__overrun__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL2_STATUS__par_err__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL2_STATUS__framing_err__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL2_STATUS__data_avail__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL2_STATUS__xoff_detect__##f1##__VAL(R_SERIAL2_STATUS_, xoff_detect_, v1) << R_SERIAL2_STATUS__xoff_detect__BITNR) | \
+ (R_SERIAL2_STATUS__cts___##f2##__VAL(R_SERIAL2_STATUS_, cts__, v2) << R_SERIAL2_STATUS__cts___BITNR) | \
+ (R_SERIAL2_STATUS__tr_ready__##f3##__VAL(R_SERIAL2_STATUS_, tr_ready_, v3) << R_SERIAL2_STATUS__tr_ready__BITNR) | \
+ (R_SERIAL2_STATUS__rxd__##f4##__VAL(R_SERIAL2_STATUS_, rxd_, v4) << R_SERIAL2_STATUS__rxd__BITNR) | \
+ (R_SERIAL2_STATUS__overrun__##f5##__VAL(R_SERIAL2_STATUS_, overrun_, v5) << R_SERIAL2_STATUS__overrun__BITNR) | \
+ (R_SERIAL2_STATUS__par_err__##f6##__VAL(R_SERIAL2_STATUS_, par_err_, v6) << R_SERIAL2_STATUS__par_err__BITNR) | \
+ (R_SERIAL2_STATUS__framing_err__##f7##__VAL(R_SERIAL2_STATUS_, framing_err_, v7) << R_SERIAL2_STATUS__framing_err__BITNR) | \
+ (R_SERIAL2_STATUS__data_avail__##f8##__VAL(R_SERIAL2_STATUS_, data_avail_, v8) << R_SERIAL2_STATUS__data_avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL2_STATUS__xoff_detect__##f1_##_VAL(R_SERIAL2_STATUS_, xoff_detect_, v1) << R_SERIAL2_STATUS__xoff_detect__BITNR) | \
+ (R_SERIAL2_STATUS__cts___##f2_##_VAL(R_SERIAL2_STATUS_, cts__, v2) << R_SERIAL2_STATUS__cts___BITNR) | \
+ (R_SERIAL2_STATUS__tr_ready__##f3_##_VAL(R_SERIAL2_STATUS_, tr_ready_, v3) << R_SERIAL2_STATUS__tr_ready__BITNR) | \
+ (R_SERIAL2_STATUS__rxd__##f4_##_VAL(R_SERIAL2_STATUS_, rxd_, v4) << R_SERIAL2_STATUS__rxd__BITNR) | \
+ (R_SERIAL2_STATUS__overrun__##f5_##_VAL(R_SERIAL2_STATUS_, overrun_, v5) << R_SERIAL2_STATUS__overrun__BITNR) | \
+ (R_SERIAL2_STATUS__par_err__##f6_##_VAL(R_SERIAL2_STATUS_, par_err_, v6) << R_SERIAL2_STATUS__par_err__BITNR) | \
+ (R_SERIAL2_STATUS__framing_err__##f7_##_VAL(R_SERIAL2_STATUS_, framing_err_, v7) << R_SERIAL2_STATUS__framing_err__BITNR) | \
+ (R_SERIAL2_STATUS__data_avail__##f8_##_VAL(R_SERIAL2_STATUS_, data_avail_, v8) << R_SERIAL2_STATUS__data_avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_TR_CTRL
+ * - type: WO
+ * - addr: 0xb0000071
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL2_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL2_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_TR_CTRL_) \
+ REG_VAL__R_SERIAL2_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SERIAL2_TR_CTRL__WRITE(R_SERIAL2_TR_CTRL__ADDR, *R_SERIAL2_TR_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_TR_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL2_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL2_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_TR_CTRL_) \
+ REG_VAL__R_SERIAL2_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL2_TR_CTRL__txd__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL2_TR_CTRL__tr_enable__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL2_TR_CTRL__auto_cts__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL2_TR_CTRL__stop_bits__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL2_TR_CTRL__tr_stick_par__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL2_TR_CTRL__tr_par__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL2_TR_CTRL__tr_par_en__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL2_TR_CTRL__tr_bitnr__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_TR_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL2_TR_CTRL__txd__##f1##__VAL(R_SERIAL2_TR_CTRL_, txd_, v1) << R_SERIAL2_TR_CTRL__txd__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_enable__##f2##__VAL(R_SERIAL2_TR_CTRL_, tr_enable_, v2) << R_SERIAL2_TR_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL2_TR_CTRL__auto_cts__##f3##__VAL(R_SERIAL2_TR_CTRL_, auto_cts_, v3) << R_SERIAL2_TR_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL2_TR_CTRL__stop_bits__##f4##__VAL(R_SERIAL2_TR_CTRL_, stop_bits_, v4) << R_SERIAL2_TR_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_stick_par__##f5##__VAL(R_SERIAL2_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL2_TR_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_par__##f6##__VAL(R_SERIAL2_TR_CTRL_, tr_par_, v6) << R_SERIAL2_TR_CTRL__tr_par__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_par_en__##f7##__VAL(R_SERIAL2_TR_CTRL_, tr_par_en_, v7) << R_SERIAL2_TR_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_bitnr__##f8##__VAL(R_SERIAL2_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL2_TR_CTRL__tr_bitnr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_TR_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_TR_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL2_TR_CTRL__txd__##f1_##_VAL(R_SERIAL2_TR_CTRL_, txd_, v1) << R_SERIAL2_TR_CTRL__txd__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_enable__##f2_##_VAL(R_SERIAL2_TR_CTRL_, tr_enable_, v2) << R_SERIAL2_TR_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL2_TR_CTRL__auto_cts__##f3_##_VAL(R_SERIAL2_TR_CTRL_, auto_cts_, v3) << R_SERIAL2_TR_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL2_TR_CTRL__stop_bits__##f4_##_VAL(R_SERIAL2_TR_CTRL_, stop_bits_, v4) << R_SERIAL2_TR_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_stick_par__##f5_##_VAL(R_SERIAL2_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL2_TR_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_par__##f6_##_VAL(R_SERIAL2_TR_CTRL_, tr_par_, v6) << R_SERIAL2_TR_CTRL__tr_par__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_par_en__##f7_##_VAL(R_SERIAL2_TR_CTRL_, tr_par_en_, v7) << R_SERIAL2_TR_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL2_TR_CTRL__tr_bitnr__##f8_##_VAL(R_SERIAL2_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL2_TR_CTRL__tr_bitnr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_TR_DATA
+ * - type: WO
+ * - addr: 0xb0000070
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL2_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_TR_DATA(f1,v1) ( \
+ *R_SERIAL2_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_TR_DATA_) \
+ REG_VAL__R_SERIAL2_TR_DATA_(f1##_,v1) \
+ ), \
+ R_SERIAL2_TR_DATA__WRITE(R_SERIAL2_TR_DATA__ADDR, *R_SERIAL2_TR_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_TR_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL2_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_TR_DATA__SHADOW(f1,v1) ( \
+ *R_SERIAL2_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_TR_DATA_) \
+ REG_VAL__R_SERIAL2_TR_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_TR_DATA(f1,v1) ( \
+ (R_SERIAL2_TR_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_TR_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_TR_DATA(f1,v1) ( \
+ (R_SERIAL2_TR_DATA__data_out__##f1##__VAL(R_SERIAL2_TR_DATA_, data_out_, v1) << R_SERIAL2_TR_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_TR_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_TR_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_TR_DATA_(f1_,v1) ( \
+ (R_SERIAL2_TR_DATA__data_out__##f1_##_VAL(R_SERIAL2_TR_DATA_, data_out_, v1) << R_SERIAL2_TR_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL2_XOFF
+ * - type: WO
+ * - addr: 0xb0000074
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_XOFF.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL2_XOFF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ *R_SERIAL2_XOFF__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_XOFF_) \
+ REG_VAL__R_SERIAL2_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ), \
+ R_SERIAL2_XOFF__WRITE(R_SERIAL2_XOFF__ADDR, *R_SERIAL2_XOFF__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL2_XOFF__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL2_XOFF.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL2_XOFF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL2_XOFF__SHADOW(f1,v1,f2,v2,f3,v3) ( \
+ *R_SERIAL2_XOFF__SADDR = ( \
+ REG_INITIATED(R_SERIAL2_XOFF_) \
+ REG_VAL__R_SERIAL2_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL2_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL2_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ (R_SERIAL2_XOFF__tx_stop__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL2_XOFF__auto_xoff__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL2_XOFF__xoff_char__##f3##__MASK & REG__##v3) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_XOFF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ (R_SERIAL2_XOFF__tx_stop__##f1##__VAL(R_SERIAL2_XOFF_, tx_stop_, v1) << R_SERIAL2_XOFF__tx_stop__BITNR) | \
+ (R_SERIAL2_XOFF__auto_xoff__##f2##__VAL(R_SERIAL2_XOFF_, auto_xoff_, v2) << R_SERIAL2_XOFF__auto_xoff__BITNR) | \
+ (R_SERIAL2_XOFF__xoff_char__##f3##__VAL(R_SERIAL2_XOFF_, xoff_char_, v3) << R_SERIAL2_XOFF__xoff_char__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL2_XOFF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL2_XOFF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL2_XOFF_(f1_,v1,f2_,v2,f3_,v3) ( \
+ (R_SERIAL2_XOFF__tx_stop__##f1_##_VAL(R_SERIAL2_XOFF_, tx_stop_, v1) << R_SERIAL2_XOFF__tx_stop__BITNR) | \
+ (R_SERIAL2_XOFF__auto_xoff__##f2_##_VAL(R_SERIAL2_XOFF_, auto_xoff_, v2) << R_SERIAL2_XOFF__auto_xoff__BITNR) | \
+ (R_SERIAL2_XOFF__xoff_char__##f3_##_VAL(R_SERIAL2_XOFF_, xoff_char_, v3) << R_SERIAL2_XOFF__xoff_char__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_BAUD
+ * - type: WO
+ * - addr: 0xb000007b
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_BAUD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL3_BAUD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_BAUD(f1,v1,f2,v2) ( \
+ *R_SERIAL3_BAUD__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_BAUD_) \
+ REG_VAL__R_SERIAL3_BAUD_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_SERIAL3_BAUD__WRITE(R_SERIAL3_BAUD__ADDR, *R_SERIAL3_BAUD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_BAUD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_BAUD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL3_BAUD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_BAUD__SHADOW(f1,v1,f2,v2) ( \
+ *R_SERIAL3_BAUD__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_BAUD_) \
+ REG_VAL__R_SERIAL3_BAUD_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_BAUD(f1,v1,f2,v2) ( \
+ (R_SERIAL3_BAUD__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL3_BAUD__rec_baud__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_BAUD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_BAUD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_BAUD(f1,v1,f2,v2) ( \
+ (R_SERIAL3_BAUD__tr_baud__##f1##__VAL(R_SERIAL3_BAUD_, tr_baud_, v1) << R_SERIAL3_BAUD__tr_baud__BITNR) | \
+ (R_SERIAL3_BAUD__rec_baud__##f2##__VAL(R_SERIAL3_BAUD_, rec_baud_, v2) << R_SERIAL3_BAUD__rec_baud__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_BAUD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_BAUD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_BAUD_(f1_,v1,f2_,v2) ( \
+ (R_SERIAL3_BAUD__tr_baud__##f1_##_VAL(R_SERIAL3_BAUD_, tr_baud_, v1) << R_SERIAL3_BAUD__tr_baud__BITNR) | \
+ (R_SERIAL3_BAUD__rec_baud__##f2_##_VAL(R_SERIAL3_BAUD_, rec_baud_, v2) << R_SERIAL3_BAUD__rec_baud__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_CTRL
+ * - type: WO
+ * - addr: 0xb0000078
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL3_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_SERIAL3_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_CTRL_) \
+ REG_VAL__R_SERIAL3_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ), \
+ R_SERIAL3_CTRL__WRITE(R_SERIAL3_CTRL__ADDR, *R_SERIAL3_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL3_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ *R_SERIAL3_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_CTRL_) \
+ REG_VAL__R_SERIAL3_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_SERIAL3_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL3_CTRL__rec_baud__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL3_CTRL__dma_err__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL3_CTRL__rec_enable__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL3_CTRL__rts___##f5##__MASK & REG__##v5) | \
+ (R_SERIAL3_CTRL__sampling__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL3_CTRL__rec_stick_par__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL3_CTRL__rec_par__##f8##__MASK & REG__##v8) | \
+ (R_SERIAL3_CTRL__rec_par_en__##f9##__MASK & REG__##v9) | \
+ (R_SERIAL3_CTRL__rec_bitnr__##f10##__MASK & REG__##v10) | \
+ (R_SERIAL3_CTRL__txd__##f11##__MASK & REG__##v11) | \
+ (R_SERIAL3_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \
+ (R_SERIAL3_CTRL__auto_cts__##f13##__MASK & REG__##v13) | \
+ (R_SERIAL3_CTRL__stop_bits__##f14##__MASK & REG__##v14) | \
+ (R_SERIAL3_CTRL__tr_stick_par__##f15##__MASK & REG__##v15) | \
+ (R_SERIAL3_CTRL__tr_par__##f16##__MASK & REG__##v16) | \
+ (R_SERIAL3_CTRL__tr_par_en__##f17##__MASK & REG__##v17) | \
+ (R_SERIAL3_CTRL__tr_bitnr__##f18##__MASK & REG__##v18) | \
+ (R_SERIAL3_CTRL__data_out__##f19##__MASK & REG__##v19) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19) ( \
+ (R_SERIAL3_CTRL__tr_baud__##f1##__VAL(R_SERIAL3_CTRL_, tr_baud_, v1) << R_SERIAL3_CTRL__tr_baud__BITNR) | \
+ (R_SERIAL3_CTRL__rec_baud__##f2##__VAL(R_SERIAL3_CTRL_, rec_baud_, v2) << R_SERIAL3_CTRL__rec_baud__BITNR) | \
+ (R_SERIAL3_CTRL__dma_err__##f3##__VAL(R_SERIAL3_CTRL_, dma_err_, v3) << R_SERIAL3_CTRL__dma_err__BITNR) | \
+ (R_SERIAL3_CTRL__rec_enable__##f4##__VAL(R_SERIAL3_CTRL_, rec_enable_, v4) << R_SERIAL3_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL3_CTRL__rts___##f5##__VAL(R_SERIAL3_CTRL_, rts__, v5) << R_SERIAL3_CTRL__rts___BITNR) | \
+ (R_SERIAL3_CTRL__sampling__##f6##__VAL(R_SERIAL3_CTRL_, sampling_, v6) << R_SERIAL3_CTRL__sampling__BITNR) | \
+ (R_SERIAL3_CTRL__rec_stick_par__##f7##__VAL(R_SERIAL3_CTRL_, rec_stick_par_, v7) << R_SERIAL3_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL3_CTRL__rec_par__##f8##__VAL(R_SERIAL3_CTRL_, rec_par_, v8) << R_SERIAL3_CTRL__rec_par__BITNR) | \
+ (R_SERIAL3_CTRL__rec_par_en__##f9##__VAL(R_SERIAL3_CTRL_, rec_par_en_, v9) << R_SERIAL3_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL3_CTRL__rec_bitnr__##f10##__VAL(R_SERIAL3_CTRL_, rec_bitnr_, v10) << R_SERIAL3_CTRL__rec_bitnr__BITNR) | \
+ (R_SERIAL3_CTRL__txd__##f11##__VAL(R_SERIAL3_CTRL_, txd_, v11) << R_SERIAL3_CTRL__txd__BITNR) | \
+ (R_SERIAL3_CTRL__tr_enable__##f12##__VAL(R_SERIAL3_CTRL_, tr_enable_, v12) << R_SERIAL3_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL3_CTRL__auto_cts__##f13##__VAL(R_SERIAL3_CTRL_, auto_cts_, v13) << R_SERIAL3_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL3_CTRL__stop_bits__##f14##__VAL(R_SERIAL3_CTRL_, stop_bits_, v14) << R_SERIAL3_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL3_CTRL__tr_stick_par__##f15##__VAL(R_SERIAL3_CTRL_, tr_stick_par_, v15) << R_SERIAL3_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL3_CTRL__tr_par__##f16##__VAL(R_SERIAL3_CTRL_, tr_par_, v16) << R_SERIAL3_CTRL__tr_par__BITNR) | \
+ (R_SERIAL3_CTRL__tr_par_en__##f17##__VAL(R_SERIAL3_CTRL_, tr_par_en_, v17) << R_SERIAL3_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL3_CTRL__tr_bitnr__##f18##__VAL(R_SERIAL3_CTRL_, tr_bitnr_, v18) << R_SERIAL3_CTRL__tr_bitnr__BITNR) | \
+ (R_SERIAL3_CTRL__data_out__##f19##__VAL(R_SERIAL3_CTRL_, data_out_, v19) << R_SERIAL3_CTRL__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19) ( \
+ (R_SERIAL3_CTRL__tr_baud__##f1_##_VAL(R_SERIAL3_CTRL_, tr_baud_, v1) << R_SERIAL3_CTRL__tr_baud__BITNR) | \
+ (R_SERIAL3_CTRL__rec_baud__##f2_##_VAL(R_SERIAL3_CTRL_, rec_baud_, v2) << R_SERIAL3_CTRL__rec_baud__BITNR) | \
+ (R_SERIAL3_CTRL__dma_err__##f3_##_VAL(R_SERIAL3_CTRL_, dma_err_, v3) << R_SERIAL3_CTRL__dma_err__BITNR) | \
+ (R_SERIAL3_CTRL__rec_enable__##f4_##_VAL(R_SERIAL3_CTRL_, rec_enable_, v4) << R_SERIAL3_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL3_CTRL__rts___##f5_##_VAL(R_SERIAL3_CTRL_, rts__, v5) << R_SERIAL3_CTRL__rts___BITNR) | \
+ (R_SERIAL3_CTRL__sampling__##f6_##_VAL(R_SERIAL3_CTRL_, sampling_, v6) << R_SERIAL3_CTRL__sampling__BITNR) | \
+ (R_SERIAL3_CTRL__rec_stick_par__##f7_##_VAL(R_SERIAL3_CTRL_, rec_stick_par_, v7) << R_SERIAL3_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL3_CTRL__rec_par__##f8_##_VAL(R_SERIAL3_CTRL_, rec_par_, v8) << R_SERIAL3_CTRL__rec_par__BITNR) | \
+ (R_SERIAL3_CTRL__rec_par_en__##f9_##_VAL(R_SERIAL3_CTRL_, rec_par_en_, v9) << R_SERIAL3_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL3_CTRL__rec_bitnr__##f10_##_VAL(R_SERIAL3_CTRL_, rec_bitnr_, v10) << R_SERIAL3_CTRL__rec_bitnr__BITNR) | \
+ (R_SERIAL3_CTRL__txd__##f11_##_VAL(R_SERIAL3_CTRL_, txd_, v11) << R_SERIAL3_CTRL__txd__BITNR) | \
+ (R_SERIAL3_CTRL__tr_enable__##f12_##_VAL(R_SERIAL3_CTRL_, tr_enable_, v12) << R_SERIAL3_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL3_CTRL__auto_cts__##f13_##_VAL(R_SERIAL3_CTRL_, auto_cts_, v13) << R_SERIAL3_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL3_CTRL__stop_bits__##f14_##_VAL(R_SERIAL3_CTRL_, stop_bits_, v14) << R_SERIAL3_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL3_CTRL__tr_stick_par__##f15_##_VAL(R_SERIAL3_CTRL_, tr_stick_par_, v15) << R_SERIAL3_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL3_CTRL__tr_par__##f16_##_VAL(R_SERIAL3_CTRL_, tr_par_, v16) << R_SERIAL3_CTRL__tr_par__BITNR) | \
+ (R_SERIAL3_CTRL__tr_par_en__##f17_##_VAL(R_SERIAL3_CTRL_, tr_par_en_, v17) << R_SERIAL3_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL3_CTRL__tr_bitnr__##f18_##_VAL(R_SERIAL3_CTRL_, tr_bitnr_, v18) << R_SERIAL3_CTRL__tr_bitnr__BITNR) | \
+ (R_SERIAL3_CTRL__data_out__##f19_##_VAL(R_SERIAL3_CTRL_, data_out_, v19) << R_SERIAL3_CTRL__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_READ
+ * - type: RO
+ * - addr: 0xb0000078
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SERIAL3_READ__xoff_detect__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL3_READ__cts___##f2##__MASK & REG__##v2) | \
+ (R_SERIAL3_READ__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL3_READ__rxd__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL3_READ__overrun__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL3_READ__par_err__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL3_READ__framing_err__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL3_READ__data_avail__##f8##__MASK & REG__##v8) | \
+ (R_SERIAL3_READ__data_in__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SERIAL3_READ__xoff_detect__##f1##__VAL(R_SERIAL3_READ_, xoff_detect_, v1) << R_SERIAL3_READ__xoff_detect__BITNR) | \
+ (R_SERIAL3_READ__cts___##f2##__VAL(R_SERIAL3_READ_, cts__, v2) << R_SERIAL3_READ__cts___BITNR) | \
+ (R_SERIAL3_READ__tr_ready__##f3##__VAL(R_SERIAL3_READ_, tr_ready_, v3) << R_SERIAL3_READ__tr_ready__BITNR) | \
+ (R_SERIAL3_READ__rxd__##f4##__VAL(R_SERIAL3_READ_, rxd_, v4) << R_SERIAL3_READ__rxd__BITNR) | \
+ (R_SERIAL3_READ__overrun__##f5##__VAL(R_SERIAL3_READ_, overrun_, v5) << R_SERIAL3_READ__overrun__BITNR) | \
+ (R_SERIAL3_READ__par_err__##f6##__VAL(R_SERIAL3_READ_, par_err_, v6) << R_SERIAL3_READ__par_err__BITNR) | \
+ (R_SERIAL3_READ__framing_err__##f7##__VAL(R_SERIAL3_READ_, framing_err_, v7) << R_SERIAL3_READ__framing_err__BITNR) | \
+ (R_SERIAL3_READ__data_avail__##f8##__VAL(R_SERIAL3_READ_, data_avail_, v8) << R_SERIAL3_READ__data_avail__BITNR) | \
+ (R_SERIAL3_READ__data_in__##f9##__VAL(R_SERIAL3_READ_, data_in_, v9) << R_SERIAL3_READ__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_SERIAL3_READ__xoff_detect__##f1_##_VAL(R_SERIAL3_READ_, xoff_detect_, v1) << R_SERIAL3_READ__xoff_detect__BITNR) | \
+ (R_SERIAL3_READ__cts___##f2_##_VAL(R_SERIAL3_READ_, cts__, v2) << R_SERIAL3_READ__cts___BITNR) | \
+ (R_SERIAL3_READ__tr_ready__##f3_##_VAL(R_SERIAL3_READ_, tr_ready_, v3) << R_SERIAL3_READ__tr_ready__BITNR) | \
+ (R_SERIAL3_READ__rxd__##f4_##_VAL(R_SERIAL3_READ_, rxd_, v4) << R_SERIAL3_READ__rxd__BITNR) | \
+ (R_SERIAL3_READ__overrun__##f5_##_VAL(R_SERIAL3_READ_, overrun_, v5) << R_SERIAL3_READ__overrun__BITNR) | \
+ (R_SERIAL3_READ__par_err__##f6_##_VAL(R_SERIAL3_READ_, par_err_, v6) << R_SERIAL3_READ__par_err__BITNR) | \
+ (R_SERIAL3_READ__framing_err__##f7_##_VAL(R_SERIAL3_READ_, framing_err_, v7) << R_SERIAL3_READ__framing_err__BITNR) | \
+ (R_SERIAL3_READ__data_avail__##f8_##_VAL(R_SERIAL3_READ_, data_avail_, v8) << R_SERIAL3_READ__data_avail__BITNR) | \
+ (R_SERIAL3_READ__data_in__##f9_##_VAL(R_SERIAL3_READ_, data_in_, v9) << R_SERIAL3_READ__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_REC_CTRL
+ * - type: WO
+ * - addr: 0xb000007a
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_REC_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL3_REC_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL3_REC_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_REC_CTRL_) \
+ REG_VAL__R_SERIAL3_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SERIAL3_REC_CTRL__WRITE(R_SERIAL3_REC_CTRL__ADDR, *R_SERIAL3_REC_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_REC_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_REC_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL3_REC_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_REC_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL3_REC_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_REC_CTRL_) \
+ REG_VAL__R_SERIAL3_REC_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL3_REC_CTRL__dma_err__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL3_REC_CTRL__rec_enable__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL3_REC_CTRL__rts___##f3##__MASK & REG__##v3) | \
+ (R_SERIAL3_REC_CTRL__sampling__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL3_REC_CTRL__rec_stick_par__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL3_REC_CTRL__rec_par__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL3_REC_CTRL__rec_par_en__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL3_REC_CTRL__rec_bitnr__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_REC_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_REC_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_REC_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL3_REC_CTRL__dma_err__##f1##__VAL(R_SERIAL3_REC_CTRL_, dma_err_, v1) << R_SERIAL3_REC_CTRL__dma_err__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_enable__##f2##__VAL(R_SERIAL3_REC_CTRL_, rec_enable_, v2) << R_SERIAL3_REC_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rts___##f3##__VAL(R_SERIAL3_REC_CTRL_, rts__, v3) << R_SERIAL3_REC_CTRL__rts___BITNR) | \
+ (R_SERIAL3_REC_CTRL__sampling__##f4##__VAL(R_SERIAL3_REC_CTRL_, sampling_, v4) << R_SERIAL3_REC_CTRL__sampling__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_stick_par__##f5##__VAL(R_SERIAL3_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL3_REC_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_par__##f6##__VAL(R_SERIAL3_REC_CTRL_, rec_par_, v6) << R_SERIAL3_REC_CTRL__rec_par__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_par_en__##f7##__VAL(R_SERIAL3_REC_CTRL_, rec_par_en_, v7) << R_SERIAL3_REC_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_bitnr__##f8##__VAL(R_SERIAL3_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL3_REC_CTRL__rec_bitnr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_REC_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_REC_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_REC_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL3_REC_CTRL__dma_err__##f1_##_VAL(R_SERIAL3_REC_CTRL_, dma_err_, v1) << R_SERIAL3_REC_CTRL__dma_err__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_enable__##f2_##_VAL(R_SERIAL3_REC_CTRL_, rec_enable_, v2) << R_SERIAL3_REC_CTRL__rec_enable__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rts___##f3_##_VAL(R_SERIAL3_REC_CTRL_, rts__, v3) << R_SERIAL3_REC_CTRL__rts___BITNR) | \
+ (R_SERIAL3_REC_CTRL__sampling__##f4_##_VAL(R_SERIAL3_REC_CTRL_, sampling_, v4) << R_SERIAL3_REC_CTRL__sampling__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_stick_par__##f5_##_VAL(R_SERIAL3_REC_CTRL_, rec_stick_par_, v5) << R_SERIAL3_REC_CTRL__rec_stick_par__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_par__##f6_##_VAL(R_SERIAL3_REC_CTRL_, rec_par_, v6) << R_SERIAL3_REC_CTRL__rec_par__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_par_en__##f7_##_VAL(R_SERIAL3_REC_CTRL_, rec_par_en_, v7) << R_SERIAL3_REC_CTRL__rec_par_en__BITNR) | \
+ (R_SERIAL3_REC_CTRL__rec_bitnr__##f8_##_VAL(R_SERIAL3_REC_CTRL_, rec_bitnr_, v8) << R_SERIAL3_REC_CTRL__rec_bitnr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_REC_DATA
+ * - type: RO
+ * - addr: 0xb0000078
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_REC_DATA(f1,v1) ( \
+ (R_SERIAL3_REC_DATA__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_REC_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_REC_DATA(f1,v1) ( \
+ (R_SERIAL3_REC_DATA__data_in__##f1##__VAL(R_SERIAL3_REC_DATA_, data_in_, v1) << R_SERIAL3_REC_DATA__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_REC_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_REC_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_REC_DATA_(f1_,v1) ( \
+ (R_SERIAL3_REC_DATA__data_in__##f1_##_VAL(R_SERIAL3_REC_DATA_, data_in_, v1) << R_SERIAL3_REC_DATA__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_STATUS
+ * - type: RO
+ * - addr: 0xb0000079
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL3_STATUS__xoff_detect__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL3_STATUS__cts___##f2##__MASK & REG__##v2) | \
+ (R_SERIAL3_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL3_STATUS__rxd__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL3_STATUS__overrun__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL3_STATUS__par_err__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL3_STATUS__framing_err__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL3_STATUS__data_avail__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL3_STATUS__xoff_detect__##f1##__VAL(R_SERIAL3_STATUS_, xoff_detect_, v1) << R_SERIAL3_STATUS__xoff_detect__BITNR) | \
+ (R_SERIAL3_STATUS__cts___##f2##__VAL(R_SERIAL3_STATUS_, cts__, v2) << R_SERIAL3_STATUS__cts___BITNR) | \
+ (R_SERIAL3_STATUS__tr_ready__##f3##__VAL(R_SERIAL3_STATUS_, tr_ready_, v3) << R_SERIAL3_STATUS__tr_ready__BITNR) | \
+ (R_SERIAL3_STATUS__rxd__##f4##__VAL(R_SERIAL3_STATUS_, rxd_, v4) << R_SERIAL3_STATUS__rxd__BITNR) | \
+ (R_SERIAL3_STATUS__overrun__##f5##__VAL(R_SERIAL3_STATUS_, overrun_, v5) << R_SERIAL3_STATUS__overrun__BITNR) | \
+ (R_SERIAL3_STATUS__par_err__##f6##__VAL(R_SERIAL3_STATUS_, par_err_, v6) << R_SERIAL3_STATUS__par_err__BITNR) | \
+ (R_SERIAL3_STATUS__framing_err__##f7##__VAL(R_SERIAL3_STATUS_, framing_err_, v7) << R_SERIAL3_STATUS__framing_err__BITNR) | \
+ (R_SERIAL3_STATUS__data_avail__##f8##__VAL(R_SERIAL3_STATUS_, data_avail_, v8) << R_SERIAL3_STATUS__data_avail__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL3_STATUS__xoff_detect__##f1_##_VAL(R_SERIAL3_STATUS_, xoff_detect_, v1) << R_SERIAL3_STATUS__xoff_detect__BITNR) | \
+ (R_SERIAL3_STATUS__cts___##f2_##_VAL(R_SERIAL3_STATUS_, cts__, v2) << R_SERIAL3_STATUS__cts___BITNR) | \
+ (R_SERIAL3_STATUS__tr_ready__##f3_##_VAL(R_SERIAL3_STATUS_, tr_ready_, v3) << R_SERIAL3_STATUS__tr_ready__BITNR) | \
+ (R_SERIAL3_STATUS__rxd__##f4_##_VAL(R_SERIAL3_STATUS_, rxd_, v4) << R_SERIAL3_STATUS__rxd__BITNR) | \
+ (R_SERIAL3_STATUS__overrun__##f5_##_VAL(R_SERIAL3_STATUS_, overrun_, v5) << R_SERIAL3_STATUS__overrun__BITNR) | \
+ (R_SERIAL3_STATUS__par_err__##f6_##_VAL(R_SERIAL3_STATUS_, par_err_, v6) << R_SERIAL3_STATUS__par_err__BITNR) | \
+ (R_SERIAL3_STATUS__framing_err__##f7_##_VAL(R_SERIAL3_STATUS_, framing_err_, v7) << R_SERIAL3_STATUS__framing_err__BITNR) | \
+ (R_SERIAL3_STATUS__data_avail__##f8_##_VAL(R_SERIAL3_STATUS_, data_avail_, v8) << R_SERIAL3_STATUS__data_avail__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_TR_CTRL
+ * - type: WO
+ * - addr: 0xb0000079
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL3_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL3_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_TR_CTRL_) \
+ REG_VAL__R_SERIAL3_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SERIAL3_TR_CTRL__WRITE(R_SERIAL3_TR_CTRL__ADDR, *R_SERIAL3_TR_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_TR_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_TR_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL3_TR_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_TR_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SERIAL3_TR_CTRL__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_TR_CTRL_) \
+ REG_VAL__R_SERIAL3_TR_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL3_TR_CTRL__txd__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL3_TR_CTRL__tr_enable__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL3_TR_CTRL__auto_cts__##f3##__MASK & REG__##v3) | \
+ (R_SERIAL3_TR_CTRL__stop_bits__##f4##__MASK & REG__##v4) | \
+ (R_SERIAL3_TR_CTRL__tr_stick_par__##f5##__MASK & REG__##v5) | \
+ (R_SERIAL3_TR_CTRL__tr_par__##f6##__MASK & REG__##v6) | \
+ (R_SERIAL3_TR_CTRL__tr_par_en__##f7##__MASK & REG__##v7) | \
+ (R_SERIAL3_TR_CTRL__tr_bitnr__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_TR_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_TR_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_TR_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SERIAL3_TR_CTRL__txd__##f1##__VAL(R_SERIAL3_TR_CTRL_, txd_, v1) << R_SERIAL3_TR_CTRL__txd__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_enable__##f2##__VAL(R_SERIAL3_TR_CTRL_, tr_enable_, v2) << R_SERIAL3_TR_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL3_TR_CTRL__auto_cts__##f3##__VAL(R_SERIAL3_TR_CTRL_, auto_cts_, v3) << R_SERIAL3_TR_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL3_TR_CTRL__stop_bits__##f4##__VAL(R_SERIAL3_TR_CTRL_, stop_bits_, v4) << R_SERIAL3_TR_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_stick_par__##f5##__VAL(R_SERIAL3_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL3_TR_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_par__##f6##__VAL(R_SERIAL3_TR_CTRL_, tr_par_, v6) << R_SERIAL3_TR_CTRL__tr_par__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_par_en__##f7##__VAL(R_SERIAL3_TR_CTRL_, tr_par_en_, v7) << R_SERIAL3_TR_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_bitnr__##f8##__VAL(R_SERIAL3_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL3_TR_CTRL__tr_bitnr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_TR_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_TR_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_TR_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SERIAL3_TR_CTRL__txd__##f1_##_VAL(R_SERIAL3_TR_CTRL_, txd_, v1) << R_SERIAL3_TR_CTRL__txd__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_enable__##f2_##_VAL(R_SERIAL3_TR_CTRL_, tr_enable_, v2) << R_SERIAL3_TR_CTRL__tr_enable__BITNR) | \
+ (R_SERIAL3_TR_CTRL__auto_cts__##f3_##_VAL(R_SERIAL3_TR_CTRL_, auto_cts_, v3) << R_SERIAL3_TR_CTRL__auto_cts__BITNR) | \
+ (R_SERIAL3_TR_CTRL__stop_bits__##f4_##_VAL(R_SERIAL3_TR_CTRL_, stop_bits_, v4) << R_SERIAL3_TR_CTRL__stop_bits__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_stick_par__##f5_##_VAL(R_SERIAL3_TR_CTRL_, tr_stick_par_, v5) << R_SERIAL3_TR_CTRL__tr_stick_par__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_par__##f6_##_VAL(R_SERIAL3_TR_CTRL_, tr_par_, v6) << R_SERIAL3_TR_CTRL__tr_par__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_par_en__##f7_##_VAL(R_SERIAL3_TR_CTRL_, tr_par_en_, v7) << R_SERIAL3_TR_CTRL__tr_par_en__BITNR) | \
+ (R_SERIAL3_TR_CTRL__tr_bitnr__##f8_##_VAL(R_SERIAL3_TR_CTRL_, tr_bitnr_, v8) << R_SERIAL3_TR_CTRL__tr_bitnr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_TR_DATA
+ * - type: WO
+ * - addr: 0xb0000078
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL3_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_TR_DATA(f1,v1) ( \
+ *R_SERIAL3_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_TR_DATA_) \
+ REG_VAL__R_SERIAL3_TR_DATA_(f1##_,v1) \
+ ), \
+ R_SERIAL3_TR_DATA__WRITE(R_SERIAL3_TR_DATA__ADDR, *R_SERIAL3_TR_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_TR_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL3_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_TR_DATA__SHADOW(f1,v1) ( \
+ *R_SERIAL3_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_TR_DATA_) \
+ REG_VAL__R_SERIAL3_TR_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_TR_DATA(f1,v1) ( \
+ (R_SERIAL3_TR_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_TR_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_TR_DATA(f1,v1) ( \
+ (R_SERIAL3_TR_DATA__data_out__##f1##__VAL(R_SERIAL3_TR_DATA_, data_out_, v1) << R_SERIAL3_TR_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_TR_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_TR_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_TR_DATA_(f1_,v1) ( \
+ (R_SERIAL3_TR_DATA__data_out__##f1_##_VAL(R_SERIAL3_TR_DATA_, data_out_, v1) << R_SERIAL3_TR_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL3_XOFF
+ * - type: WO
+ * - addr: 0xb000007c
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_XOFF.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL3_XOFF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ *R_SERIAL3_XOFF__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_XOFF_) \
+ REG_VAL__R_SERIAL3_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ), \
+ R_SERIAL3_XOFF__WRITE(R_SERIAL3_XOFF__ADDR, *R_SERIAL3_XOFF__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL3_XOFF__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL3_XOFF.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL3_XOFF.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL3_XOFF__SHADOW(f1,v1,f2,v2,f3,v3) ( \
+ *R_SERIAL3_XOFF__SADDR = ( \
+ REG_INITIATED(R_SERIAL3_XOFF_) \
+ REG_VAL__R_SERIAL3_XOFF_(f1##_,v1,f2##_,v2,f3##_,v3) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL3_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL3_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ (R_SERIAL3_XOFF__tx_stop__##f1##__MASK & REG__##v1) | \
+ (R_SERIAL3_XOFF__auto_xoff__##f2##__MASK & REG__##v2) | \
+ (R_SERIAL3_XOFF__xoff_char__##f3##__MASK & REG__##v3) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_XOFF
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_XOFF.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_XOFF(f1,v1,f2,v2,f3,v3) ( \
+ (R_SERIAL3_XOFF__tx_stop__##f1##__VAL(R_SERIAL3_XOFF_, tx_stop_, v1) << R_SERIAL3_XOFF__tx_stop__BITNR) | \
+ (R_SERIAL3_XOFF__auto_xoff__##f2##__VAL(R_SERIAL3_XOFF_, auto_xoff_, v2) << R_SERIAL3_XOFF__auto_xoff__BITNR) | \
+ (R_SERIAL3_XOFF__xoff_char__##f3##__VAL(R_SERIAL3_XOFF_, xoff_char_, v3) << R_SERIAL3_XOFF__xoff_char__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL3_XOFF_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL3_XOFF.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL3_XOFF_(f1_,v1,f2_,v2,f3_,v3) ( \
+ (R_SERIAL3_XOFF__tx_stop__##f1_##_VAL(R_SERIAL3_XOFF_, tx_stop_, v1) << R_SERIAL3_XOFF__tx_stop__BITNR) | \
+ (R_SERIAL3_XOFF__auto_xoff__##f2_##_VAL(R_SERIAL3_XOFF_, auto_xoff_, v2) << R_SERIAL3_XOFF__auto_xoff__BITNR) | \
+ (R_SERIAL3_XOFF__xoff_char__##f3_##_VAL(R_SERIAL3_XOFF_, xoff_char_, v3) << R_SERIAL3_XOFF__xoff_char__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SERIAL_PRESCALE
+ * - type: WO
+ * - addr: 0xb00000f2
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL_PRESCALE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SERIAL_PRESCALE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL_PRESCALE(f1,v1) ( \
+ *R_SERIAL_PRESCALE__SADDR = ( \
+ REG_INITIATED(R_SERIAL_PRESCALE_) \
+ REG_VAL__R_SERIAL_PRESCALE_(f1##_,v1) \
+ ), \
+ R_SERIAL_PRESCALE__WRITE(R_SERIAL_PRESCALE__ADDR, *R_SERIAL_PRESCALE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SERIAL_PRESCALE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SERIAL_PRESCALE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SERIAL_PRESCALE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SERIAL_PRESCALE__SHADOW(f1,v1) ( \
+ *R_SERIAL_PRESCALE__SADDR = ( \
+ REG_INITIATED(R_SERIAL_PRESCALE_) \
+ REG_VAL__R_SERIAL_PRESCALE_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SERIAL_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SERIAL_PRESCALE(f1,v1) ( \
+ (R_SERIAL_PRESCALE__ser_presc__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL_PRESCALE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL_PRESCALE(f1,v1) ( \
+ (R_SERIAL_PRESCALE__ser_presc__##f1##__VAL(R_SERIAL_PRESCALE_, ser_presc_, v1) << R_SERIAL_PRESCALE__ser_presc__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SERIAL_PRESCALE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SERIAL_PRESCALE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SERIAL_PRESCALE_(f1_,v1) ( \
+ (R_SERIAL_PRESCALE__ser_presc__##f1_##_VAL(R_SERIAL_PRESCALE_, ser_presc_, v1) << R_SERIAL_PRESCALE__ser_presc__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SER_PRESC_STATUS
+ * - type: RO
+ * - addr: 0xb00000f2
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SER_PRESC_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SER_PRESC_STATUS(f1,v1) ( \
+ (R_SER_PRESC_STATUS__ser_status__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SER_PRESC_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SER_PRESC_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SER_PRESC_STATUS(f1,v1) ( \
+ (R_SER_PRESC_STATUS__ser_status__##f1##__VAL(R_SER_PRESC_STATUS_, ser_status_, v1) << R_SER_PRESC_STATUS__ser_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SER_PRESC_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SER_PRESC_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SER_PRESC_STATUS_(f1_,v1) ( \
+ (R_SER_PRESC_STATUS__ser_status__##f1_##_VAL(R_SER_PRESC_STATUS_, ser_status_, v1) << R_SER_PRESC_STATUS__ser_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SET_EOP
+ * - type: WO
+ * - addr: 0xb000003c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SET_EOP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SET_EOP.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SET_EOP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SET_EOP(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ *R_SET_EOP__SADDR = ( \
+ REG_INITIATED(R_SET_EOP_) \
+ REG_VAL__R_SET_EOP_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \
+ ), \
+ R_SET_EOP__WRITE(R_SET_EOP__ADDR, *R_SET_EOP__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SET_EOP__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SET_EOP.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SET_EOP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SET_EOP__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ *R_SET_EOP__SADDR = ( \
+ REG_INITIATED(R_SET_EOP_) \
+ REG_VAL__R_SET_EOP_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SET_EOP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SET_EOP(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_SET_EOP__ch9_eop__##f1##__MASK & REG__##v1) | \
+ (R_SET_EOP__ch7_eop__##f2##__MASK & REG__##v2) | \
+ (R_SET_EOP__ch5_eop__##f3##__MASK & REG__##v3) | \
+ (R_SET_EOP__ch3_eop__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SET_EOP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SET_EOP.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SET_EOP(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_SET_EOP__ch9_eop__##f1##__VAL(R_SET_EOP_, ch9_eop_, v1) << R_SET_EOP__ch9_eop__BITNR) | \
+ (R_SET_EOP__ch7_eop__##f2##__VAL(R_SET_EOP_, ch7_eop_, v2) << R_SET_EOP__ch7_eop__BITNR) | \
+ (R_SET_EOP__ch5_eop__##f3##__VAL(R_SET_EOP_, ch5_eop_, v3) << R_SET_EOP__ch5_eop__BITNR) | \
+ (R_SET_EOP__ch3_eop__##f4##__VAL(R_SET_EOP_, ch3_eop_, v4) << R_SET_EOP__ch3_eop__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SET_EOP_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SET_EOP.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SET_EOP_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_SET_EOP__ch9_eop__##f1_##_VAL(R_SET_EOP_, ch9_eop_, v1) << R_SET_EOP__ch9_eop__BITNR) | \
+ (R_SET_EOP__ch7_eop__##f2_##_VAL(R_SET_EOP_, ch7_eop_, v2) << R_SET_EOP__ch7_eop__BITNR) | \
+ (R_SET_EOP__ch5_eop__##f3_##_VAL(R_SET_EOP_, ch5_eop_, v3) << R_SET_EOP__ch5_eop__BITNR) | \
+ (R_SET_EOP__ch3_eop__##f4_##_VAL(R_SET_EOP_, ch3_eop_, v4) << R_SET_EOP__ch3_eop__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SHARED_RAM_ADDR
+ * - type: WO
+ * - addr: 0xb0000044
+ * - group: Shared RAM interface registers
+ */
+
+#if USE_GROUP__Shared_RAM_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SHARED_RAM_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SHARED_RAM_ADDR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SHARED_RAM_ADDR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SHARED_RAM_ADDR(f1,v1) ( \
+ *R_SHARED_RAM_ADDR__SADDR = ( \
+ REG_INITIATED(R_SHARED_RAM_ADDR_) \
+ REG_VAL__R_SHARED_RAM_ADDR_(f1##_,v1) \
+ ), \
+ R_SHARED_RAM_ADDR__WRITE(R_SHARED_RAM_ADDR__ADDR, *R_SHARED_RAM_ADDR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SHARED_RAM_ADDR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SHARED_RAM_ADDR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SHARED_RAM_ADDR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SHARED_RAM_ADDR__SHADOW(f1,v1) ( \
+ *R_SHARED_RAM_ADDR__SADDR = ( \
+ REG_INITIATED(R_SHARED_RAM_ADDR_) \
+ REG_VAL__R_SHARED_RAM_ADDR_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SHARED_RAM_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SHARED_RAM_ADDR(f1,v1) ( \
+ (R_SHARED_RAM_ADDR__base_addr__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SHARED_RAM_ADDR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SHARED_RAM_ADDR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SHARED_RAM_ADDR(f1,v1) ( \
+ (R_SHARED_RAM_ADDR__base_addr__##f1##__VAL(R_SHARED_RAM_ADDR_, base_addr_, v1) << R_SHARED_RAM_ADDR__base_addr__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SHARED_RAM_ADDR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SHARED_RAM_ADDR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SHARED_RAM_ADDR_(f1_,v1) ( \
+ (R_SHARED_RAM_ADDR__base_addr__##f1_##_VAL(R_SHARED_RAM_ADDR_, base_addr_, v1) << R_SHARED_RAM_ADDR__base_addr__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SHARED_RAM_CONFIG
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: Shared RAM interface registers
+ */
+
+#if USE_GROUP__Shared_RAM_interface_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SHARED_RAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SHARED_RAM_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SHARED_RAM_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SHARED_RAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ *R_SHARED_RAM_CONFIG__SADDR = ( \
+ REG_INITIATED(R_SHARED_RAM_CONFIG_) \
+ REG_VAL__R_SHARED_RAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \
+ ), \
+ R_SHARED_RAM_CONFIG__WRITE(R_SHARED_RAM_CONFIG__ADDR, *R_SHARED_RAM_CONFIG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SHARED_RAM_CONFIG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SHARED_RAM_CONFIG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SHARED_RAM_CONFIG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SHARED_RAM_CONFIG__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ *R_SHARED_RAM_CONFIG__SADDR = ( \
+ REG_INITIATED(R_SHARED_RAM_CONFIG_) \
+ REG_VAL__R_SHARED_RAM_CONFIG_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SHARED_RAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SHARED_RAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_SHARED_RAM_CONFIG__width__##f1##__MASK & REG__##v1) | \
+ (R_SHARED_RAM_CONFIG__enable__##f2##__MASK & REG__##v2) | \
+ (R_SHARED_RAM_CONFIG__pint__##f3##__MASK & REG__##v3) | \
+ (R_SHARED_RAM_CONFIG__clri__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SHARED_RAM_CONFIG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SHARED_RAM_CONFIG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SHARED_RAM_CONFIG(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_SHARED_RAM_CONFIG__width__##f1##__VAL(R_SHARED_RAM_CONFIG_, width_, v1) << R_SHARED_RAM_CONFIG__width__BITNR) | \
+ (R_SHARED_RAM_CONFIG__enable__##f2##__VAL(R_SHARED_RAM_CONFIG_, enable_, v2) << R_SHARED_RAM_CONFIG__enable__BITNR) | \
+ (R_SHARED_RAM_CONFIG__pint__##f3##__VAL(R_SHARED_RAM_CONFIG_, pint_, v3) << R_SHARED_RAM_CONFIG__pint__BITNR) | \
+ (R_SHARED_RAM_CONFIG__clri__##f4##__VAL(R_SHARED_RAM_CONFIG_, clri_, v4) << R_SHARED_RAM_CONFIG__clri__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SHARED_RAM_CONFIG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SHARED_RAM_CONFIG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SHARED_RAM_CONFIG_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_SHARED_RAM_CONFIG__width__##f1_##_VAL(R_SHARED_RAM_CONFIG_, width_, v1) << R_SHARED_RAM_CONFIG__width__BITNR) | \
+ (R_SHARED_RAM_CONFIG__enable__##f2_##_VAL(R_SHARED_RAM_CONFIG_, enable_, v2) << R_SHARED_RAM_CONFIG__enable__BITNR) | \
+ (R_SHARED_RAM_CONFIG__pint__##f3_##_VAL(R_SHARED_RAM_CONFIG_, pint_, v3) << R_SHARED_RAM_CONFIG__pint__BITNR) | \
+ (R_SHARED_RAM_CONFIG__clri__##f4_##_VAL(R_SHARED_RAM_CONFIG_, clri_, v4) << R_SHARED_RAM_CONFIG__clri__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SINGLE_STEP
+ * - type: WO
+ * - addr: 0xb00000fe
+ * - group: Test mode registers
+ */
+
+#if USE_GROUP__Test_mode_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SINGLE_STEP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SINGLE_STEP.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SINGLE_STEP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SINGLE_STEP(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ *R_SINGLE_STEP__SADDR = ( \
+ REG_INITIATED(R_SINGLE_STEP_) \
+ REG_VAL__R_SINGLE_STEP_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \
+ ), \
+ R_SINGLE_STEP__WRITE(R_SINGLE_STEP__ADDR, *R_SINGLE_STEP__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SINGLE_STEP__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SINGLE_STEP.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SINGLE_STEP.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SINGLE_STEP__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ *R_SINGLE_STEP__SADDR = ( \
+ REG_INITIATED(R_SINGLE_STEP_) \
+ REG_VAL__R_SINGLE_STEP_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SINGLE_STEP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SINGLE_STEP(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_SINGLE_STEP__single_step__##f1##__MASK & REG__##v1) | \
+ (R_SINGLE_STEP__step_wr__##f2##__MASK & REG__##v2) | \
+ (R_SINGLE_STEP__step_rd__##f3##__MASK & REG__##v3) | \
+ (R_SINGLE_STEP__step_fetch__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SINGLE_STEP
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SINGLE_STEP.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SINGLE_STEP(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_SINGLE_STEP__single_step__##f1##__VAL(R_SINGLE_STEP_, single_step_, v1) << R_SINGLE_STEP__single_step__BITNR) | \
+ (R_SINGLE_STEP__step_wr__##f2##__VAL(R_SINGLE_STEP_, step_wr_, v2) << R_SINGLE_STEP__step_wr__BITNR) | \
+ (R_SINGLE_STEP__step_rd__##f3##__VAL(R_SINGLE_STEP_, step_rd_, v3) << R_SINGLE_STEP__step_rd__BITNR) | \
+ (R_SINGLE_STEP__step_fetch__##f4##__VAL(R_SINGLE_STEP_, step_fetch_, v4) << R_SINGLE_STEP__step_fetch__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SINGLE_STEP_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SINGLE_STEP.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SINGLE_STEP_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_SINGLE_STEP__single_step__##f1_##_VAL(R_SINGLE_STEP_, single_step_, v1) << R_SINGLE_STEP__single_step__BITNR) | \
+ (R_SINGLE_STEP__step_wr__##f2_##_VAL(R_SINGLE_STEP_, step_wr_, v2) << R_SINGLE_STEP__step_wr__BITNR) | \
+ (R_SINGLE_STEP__step_rd__##f3_##_VAL(R_SINGLE_STEP_, step_rd_, v3) << R_SINGLE_STEP__step_rd__BITNR) | \
+ (R_SINGLE_STEP__step_fetch__##f4_##_VAL(R_SINGLE_STEP_, step_fetch_, v4) << R_SINGLE_STEP__step_fetch__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_CTRL
+ * - type: WO
+ * - addr: 0xb0000068
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL1_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL1_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ *R_SYNC_SERIAL1_CTRL__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL1_CTRL_) \
+ REG_VAL__R_SYNC_SERIAL1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \
+ ), \
+ R_SYNC_SERIAL1_CTRL__WRITE(R_SYNC_SERIAL1_CTRL__ADDR, *R_SYNC_SERIAL1_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL1_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL1_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL1_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ *R_SYNC_SERIAL1_CTRL__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL1_CTRL_) \
+ REG_VAL__R_SYNC_SERIAL1_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ (R_SYNC_SERIAL1_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SYNC_SERIAL1_CTRL__dma_enable__##f2##__MASK & REG__##v2) | \
+ (R_SYNC_SERIAL1_CTRL__mode__##f3##__MASK & REG__##v3) | \
+ (R_SYNC_SERIAL1_CTRL__error__##f4##__MASK & REG__##v4) | \
+ (R_SYNC_SERIAL1_CTRL__rec_enable__##f5##__MASK & REG__##v5) | \
+ (R_SYNC_SERIAL1_CTRL__f_synctype__##f6##__MASK & REG__##v6) | \
+ (R_SYNC_SERIAL1_CTRL__f_syncsize__##f7##__MASK & REG__##v7) | \
+ (R_SYNC_SERIAL1_CTRL__f_sync__##f8##__MASK & REG__##v8) | \
+ (R_SYNC_SERIAL1_CTRL__clk_mode__##f9##__MASK & REG__##v9) | \
+ (R_SYNC_SERIAL1_CTRL__clk_halt__##f10##__MASK & REG__##v10) | \
+ (R_SYNC_SERIAL1_CTRL__bitorder__##f11##__MASK & REG__##v11) | \
+ (R_SYNC_SERIAL1_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \
+ (R_SYNC_SERIAL1_CTRL__wordsize__##f13##__MASK & REG__##v13) | \
+ (R_SYNC_SERIAL1_CTRL__buf_empty__##f14##__MASK & REG__##v14) | \
+ (R_SYNC_SERIAL1_CTRL__buf_full__##f15##__MASK & REG__##v15) | \
+ (R_SYNC_SERIAL1_CTRL__flow_ctrl__##f16##__MASK & REG__##v16) | \
+ (R_SYNC_SERIAL1_CTRL__clk_polarity__##f17##__MASK & REG__##v17) | \
+ (R_SYNC_SERIAL1_CTRL__frame_polarity__##f18##__MASK & REG__##v18) | \
+ (R_SYNC_SERIAL1_CTRL__status_polarity__##f19##__MASK & REG__##v19) | \
+ (R_SYNC_SERIAL1_CTRL__clk_driver__##f20##__MASK & REG__##v20) | \
+ (R_SYNC_SERIAL1_CTRL__frame_driver__##f21##__MASK & REG__##v21) | \
+ (R_SYNC_SERIAL1_CTRL__status_driver__##f22##__MASK & REG__##v22) | \
+ (R_SYNC_SERIAL1_CTRL__def_out0__##f23##__MASK & REG__##v23) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ (R_SYNC_SERIAL1_CTRL__tr_baud__##f1##__VAL(R_SYNC_SERIAL1_CTRL_, tr_baud_, v1) << R_SYNC_SERIAL1_CTRL__tr_baud__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__dma_enable__##f2##__VAL(R_SYNC_SERIAL1_CTRL_, dma_enable_, v2) << R_SYNC_SERIAL1_CTRL__dma_enable__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__mode__##f3##__VAL(R_SYNC_SERIAL1_CTRL_, mode_, v3) << R_SYNC_SERIAL1_CTRL__mode__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__error__##f4##__VAL(R_SYNC_SERIAL1_CTRL_, error_, v4) << R_SYNC_SERIAL1_CTRL__error__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__rec_enable__##f5##__VAL(R_SYNC_SERIAL1_CTRL_, rec_enable_, v5) << R_SYNC_SERIAL1_CTRL__rec_enable__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__f_synctype__##f6##__VAL(R_SYNC_SERIAL1_CTRL_, f_synctype_, v6) << R_SYNC_SERIAL1_CTRL__f_synctype__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__f_syncsize__##f7##__VAL(R_SYNC_SERIAL1_CTRL_, f_syncsize_, v7) << R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__f_sync__##f8##__VAL(R_SYNC_SERIAL1_CTRL_, f_sync_, v8) << R_SYNC_SERIAL1_CTRL__f_sync__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__clk_mode__##f9##__VAL(R_SYNC_SERIAL1_CTRL_, clk_mode_, v9) << R_SYNC_SERIAL1_CTRL__clk_mode__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__clk_halt__##f10##__VAL(R_SYNC_SERIAL1_CTRL_, clk_halt_, v10) << R_SYNC_SERIAL1_CTRL__clk_halt__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__bitorder__##f11##__VAL(R_SYNC_SERIAL1_CTRL_, bitorder_, v11) << R_SYNC_SERIAL1_CTRL__bitorder__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__tr_enable__##f12##__VAL(R_SYNC_SERIAL1_CTRL_, tr_enable_, v12) << R_SYNC_SERIAL1_CTRL__tr_enable__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__wordsize__##f13##__VAL(R_SYNC_SERIAL1_CTRL_, wordsize_, v13) << R_SYNC_SERIAL1_CTRL__wordsize__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__buf_empty__##f14##__VAL(R_SYNC_SERIAL1_CTRL_, buf_empty_, v14) << R_SYNC_SERIAL1_CTRL__buf_empty__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__buf_full__##f15##__VAL(R_SYNC_SERIAL1_CTRL_, buf_full_, v15) << R_SYNC_SERIAL1_CTRL__buf_full__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__flow_ctrl__##f16##__VAL(R_SYNC_SERIAL1_CTRL_, flow_ctrl_, v16) << R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__clk_polarity__##f17##__VAL(R_SYNC_SERIAL1_CTRL_, clk_polarity_, v17) << R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__frame_polarity__##f18##__VAL(R_SYNC_SERIAL1_CTRL_, frame_polarity_, v18) << R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__status_polarity__##f19##__VAL(R_SYNC_SERIAL1_CTRL_, status_polarity_, v19) << R_SYNC_SERIAL1_CTRL__status_polarity__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__clk_driver__##f20##__VAL(R_SYNC_SERIAL1_CTRL_, clk_driver_, v20) << R_SYNC_SERIAL1_CTRL__clk_driver__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__frame_driver__##f21##__VAL(R_SYNC_SERIAL1_CTRL_, frame_driver_, v21) << R_SYNC_SERIAL1_CTRL__frame_driver__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__status_driver__##f22##__VAL(R_SYNC_SERIAL1_CTRL_, status_driver_, v22) << R_SYNC_SERIAL1_CTRL__status_driver__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__def_out0__##f23##__VAL(R_SYNC_SERIAL1_CTRL_, def_out0_, v23) << R_SYNC_SERIAL1_CTRL__def_out0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23) ( \
+ (R_SYNC_SERIAL1_CTRL__tr_baud__##f1_##_VAL(R_SYNC_SERIAL1_CTRL_, tr_baud_, v1) << R_SYNC_SERIAL1_CTRL__tr_baud__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__dma_enable__##f2_##_VAL(R_SYNC_SERIAL1_CTRL_, dma_enable_, v2) << R_SYNC_SERIAL1_CTRL__dma_enable__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__mode__##f3_##_VAL(R_SYNC_SERIAL1_CTRL_, mode_, v3) << R_SYNC_SERIAL1_CTRL__mode__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__error__##f4_##_VAL(R_SYNC_SERIAL1_CTRL_, error_, v4) << R_SYNC_SERIAL1_CTRL__error__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__rec_enable__##f5_##_VAL(R_SYNC_SERIAL1_CTRL_, rec_enable_, v5) << R_SYNC_SERIAL1_CTRL__rec_enable__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__f_synctype__##f6_##_VAL(R_SYNC_SERIAL1_CTRL_, f_synctype_, v6) << R_SYNC_SERIAL1_CTRL__f_synctype__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__f_syncsize__##f7_##_VAL(R_SYNC_SERIAL1_CTRL_, f_syncsize_, v7) << R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__f_sync__##f8_##_VAL(R_SYNC_SERIAL1_CTRL_, f_sync_, v8) << R_SYNC_SERIAL1_CTRL__f_sync__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__clk_mode__##f9_##_VAL(R_SYNC_SERIAL1_CTRL_, clk_mode_, v9) << R_SYNC_SERIAL1_CTRL__clk_mode__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__clk_halt__##f10_##_VAL(R_SYNC_SERIAL1_CTRL_, clk_halt_, v10) << R_SYNC_SERIAL1_CTRL__clk_halt__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__bitorder__##f11_##_VAL(R_SYNC_SERIAL1_CTRL_, bitorder_, v11) << R_SYNC_SERIAL1_CTRL__bitorder__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__tr_enable__##f12_##_VAL(R_SYNC_SERIAL1_CTRL_, tr_enable_, v12) << R_SYNC_SERIAL1_CTRL__tr_enable__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__wordsize__##f13_##_VAL(R_SYNC_SERIAL1_CTRL_, wordsize_, v13) << R_SYNC_SERIAL1_CTRL__wordsize__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__buf_empty__##f14_##_VAL(R_SYNC_SERIAL1_CTRL_, buf_empty_, v14) << R_SYNC_SERIAL1_CTRL__buf_empty__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__buf_full__##f15_##_VAL(R_SYNC_SERIAL1_CTRL_, buf_full_, v15) << R_SYNC_SERIAL1_CTRL__buf_full__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__flow_ctrl__##f16_##_VAL(R_SYNC_SERIAL1_CTRL_, flow_ctrl_, v16) << R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__clk_polarity__##f17_##_VAL(R_SYNC_SERIAL1_CTRL_, clk_polarity_, v17) << R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__frame_polarity__##f18_##_VAL(R_SYNC_SERIAL1_CTRL_, frame_polarity_, v18) << R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__status_polarity__##f19_##_VAL(R_SYNC_SERIAL1_CTRL_, status_polarity_, v19) << R_SYNC_SERIAL1_CTRL__status_polarity__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__clk_driver__##f20_##_VAL(R_SYNC_SERIAL1_CTRL_, clk_driver_, v20) << R_SYNC_SERIAL1_CTRL__clk_driver__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__frame_driver__##f21_##_VAL(R_SYNC_SERIAL1_CTRL_, frame_driver_, v21) << R_SYNC_SERIAL1_CTRL__frame_driver__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__status_driver__##f22_##_VAL(R_SYNC_SERIAL1_CTRL_, status_driver_, v22) << R_SYNC_SERIAL1_CTRL__status_driver__BITNR) | \
+ (R_SYNC_SERIAL1_CTRL__def_out0__##f23_##_VAL(R_SYNC_SERIAL1_CTRL_, def_out0_, v23) << R_SYNC_SERIAL1_CTRL__def_out0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_REC_BYTE
+ * - type: RO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_REC_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL1_REC_BYTE(f1,v1) ( \
+ (R_SYNC_SERIAL1_REC_BYTE__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_REC_BYTE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_REC_BYTE(f1,v1) ( \
+ (R_SYNC_SERIAL1_REC_BYTE__data_in__##f1##__VAL(R_SYNC_SERIAL1_REC_BYTE_, data_in_, v1) << R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_BYTE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_REC_BYTE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_REC_BYTE_(f1_,v1) ( \
+ (R_SYNC_SERIAL1_REC_BYTE__data_in__##f1_##_VAL(R_SYNC_SERIAL1_REC_BYTE_, data_in_, v1) << R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_REC_DATA
+ * - type: RO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL1_REC_DATA(f1,v1) ( \
+ (R_SYNC_SERIAL1_REC_DATA__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_REC_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_REC_DATA(f1,v1) ( \
+ (R_SYNC_SERIAL1_REC_DATA__data_in__##f1##__VAL(R_SYNC_SERIAL1_REC_DATA_, data_in_, v1) << R_SYNC_SERIAL1_REC_DATA__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_REC_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_REC_DATA_(f1_,v1) ( \
+ (R_SYNC_SERIAL1_REC_DATA__data_in__##f1_##_VAL(R_SYNC_SERIAL1_REC_DATA_, data_in_, v1) << R_SYNC_SERIAL1_REC_DATA__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_REC_WORD
+ * - type: RO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_REC_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL1_REC_WORD(f1,v1) ( \
+ (R_SYNC_SERIAL1_REC_WORD__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_REC_WORD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_REC_WORD(f1,v1) ( \
+ (R_SYNC_SERIAL1_REC_WORD__data_in__##f1##__VAL(R_SYNC_SERIAL1_REC_WORD_, data_in_, v1) << R_SYNC_SERIAL1_REC_WORD__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_REC_WORD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_REC_WORD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_REC_WORD_(f1_,v1) ( \
+ (R_SYNC_SERIAL1_REC_WORD__data_in__##f1_##_VAL(R_SYNC_SERIAL1_REC_WORD_, data_in_, v1) << R_SYNC_SERIAL1_REC_WORD__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_STATUS
+ * - type: RO
+ * - addr: 0xb0000068
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SYNC_SERIAL1_STATUS__rec_status__##f1##__MASK & REG__##v1) | \
+ (R_SYNC_SERIAL1_STATUS__tr_empty__##f2##__MASK & REG__##v2) | \
+ (R_SYNC_SERIAL1_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SYNC_SERIAL1_STATUS__pin_1__##f4##__MASK & REG__##v4) | \
+ (R_SYNC_SERIAL1_STATUS__pin_0__##f5##__MASK & REG__##v5) | \
+ (R_SYNC_SERIAL1_STATUS__underflow__##f6##__MASK & REG__##v6) | \
+ (R_SYNC_SERIAL1_STATUS__overrun__##f7##__MASK & REG__##v7) | \
+ (R_SYNC_SERIAL1_STATUS__data_avail__##f8##__MASK & REG__##v8) | \
+ (R_SYNC_SERIAL1_STATUS__data__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SYNC_SERIAL1_STATUS__rec_status__##f1##__VAL(R_SYNC_SERIAL1_STATUS_, rec_status_, v1) << R_SYNC_SERIAL1_STATUS__rec_status__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__tr_empty__##f2##__VAL(R_SYNC_SERIAL1_STATUS_, tr_empty_, v2) << R_SYNC_SERIAL1_STATUS__tr_empty__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__tr_ready__##f3##__VAL(R_SYNC_SERIAL1_STATUS_, tr_ready_, v3) << R_SYNC_SERIAL1_STATUS__tr_ready__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__pin_1__##f4##__VAL(R_SYNC_SERIAL1_STATUS_, pin_1_, v4) << R_SYNC_SERIAL1_STATUS__pin_1__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__pin_0__##f5##__VAL(R_SYNC_SERIAL1_STATUS_, pin_0_, v5) << R_SYNC_SERIAL1_STATUS__pin_0__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__underflow__##f6##__VAL(R_SYNC_SERIAL1_STATUS_, underflow_, v6) << R_SYNC_SERIAL1_STATUS__underflow__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__overrun__##f7##__VAL(R_SYNC_SERIAL1_STATUS_, overrun_, v7) << R_SYNC_SERIAL1_STATUS__overrun__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__data_avail__##f8##__VAL(R_SYNC_SERIAL1_STATUS_, data_avail_, v8) << R_SYNC_SERIAL1_STATUS__data_avail__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__data__##f9##__VAL(R_SYNC_SERIAL1_STATUS_, data_, v9) << R_SYNC_SERIAL1_STATUS__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_SYNC_SERIAL1_STATUS__rec_status__##f1_##_VAL(R_SYNC_SERIAL1_STATUS_, rec_status_, v1) << R_SYNC_SERIAL1_STATUS__rec_status__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__tr_empty__##f2_##_VAL(R_SYNC_SERIAL1_STATUS_, tr_empty_, v2) << R_SYNC_SERIAL1_STATUS__tr_empty__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__tr_ready__##f3_##_VAL(R_SYNC_SERIAL1_STATUS_, tr_ready_, v3) << R_SYNC_SERIAL1_STATUS__tr_ready__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__pin_1__##f4_##_VAL(R_SYNC_SERIAL1_STATUS_, pin_1_, v4) << R_SYNC_SERIAL1_STATUS__pin_1__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__pin_0__##f5_##_VAL(R_SYNC_SERIAL1_STATUS_, pin_0_, v5) << R_SYNC_SERIAL1_STATUS__pin_0__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__underflow__##f6_##_VAL(R_SYNC_SERIAL1_STATUS_, underflow_, v6) << R_SYNC_SERIAL1_STATUS__underflow__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__overrun__##f7_##_VAL(R_SYNC_SERIAL1_STATUS_, overrun_, v7) << R_SYNC_SERIAL1_STATUS__overrun__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__data_avail__##f8_##_VAL(R_SYNC_SERIAL1_STATUS_, data_avail_, v8) << R_SYNC_SERIAL1_STATUS__data_avail__BITNR) | \
+ (R_SYNC_SERIAL1_STATUS__data__##f9_##_VAL(R_SYNC_SERIAL1_STATUS_, data_, v9) << R_SYNC_SERIAL1_STATUS__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_TR_BYTE
+ * - type: WO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_BYTE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL1_TR_BYTE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL1_TR_BYTE(f1,v1) ( \
+ *R_SYNC_SERIAL1_TR_BYTE__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL1_TR_BYTE_) \
+ REG_VAL__R_SYNC_SERIAL1_TR_BYTE_(f1##_,v1) \
+ ), \
+ R_SYNC_SERIAL1_TR_BYTE__WRITE(R_SYNC_SERIAL1_TR_BYTE__ADDR, *R_SYNC_SERIAL1_TR_BYTE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_BYTE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_BYTE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL1_TR_BYTE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL1_TR_BYTE__SHADOW(f1,v1) ( \
+ *R_SYNC_SERIAL1_TR_BYTE__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL1_TR_BYTE_) \
+ REG_VAL__R_SYNC_SERIAL1_TR_BYTE_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_TR_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL1_TR_BYTE(f1,v1) ( \
+ (R_SYNC_SERIAL1_TR_BYTE__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_TR_BYTE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_TR_BYTE(f1,v1) ( \
+ (R_SYNC_SERIAL1_TR_BYTE__data_out__##f1##__VAL(R_SYNC_SERIAL1_TR_BYTE_, data_out_, v1) << R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_BYTE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_TR_BYTE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_TR_BYTE_(f1_,v1) ( \
+ (R_SYNC_SERIAL1_TR_BYTE__data_out__##f1_##_VAL(R_SYNC_SERIAL1_TR_BYTE_, data_out_, v1) << R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_TR_DATA
+ * - type: WO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL1_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL1_TR_DATA(f1,v1) ( \
+ *R_SYNC_SERIAL1_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL1_TR_DATA_) \
+ REG_VAL__R_SYNC_SERIAL1_TR_DATA_(f1##_,v1) \
+ ), \
+ R_SYNC_SERIAL1_TR_DATA__WRITE(R_SYNC_SERIAL1_TR_DATA__ADDR, *R_SYNC_SERIAL1_TR_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL1_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL1_TR_DATA__SHADOW(f1,v1) ( \
+ *R_SYNC_SERIAL1_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL1_TR_DATA_) \
+ REG_VAL__R_SYNC_SERIAL1_TR_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL1_TR_DATA(f1,v1) ( \
+ (R_SYNC_SERIAL1_TR_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_TR_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_TR_DATA(f1,v1) ( \
+ (R_SYNC_SERIAL1_TR_DATA__data_out__##f1##__VAL(R_SYNC_SERIAL1_TR_DATA_, data_out_, v1) << R_SYNC_SERIAL1_TR_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_TR_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_TR_DATA_(f1_,v1) ( \
+ (R_SYNC_SERIAL1_TR_DATA__data_out__##f1_##_VAL(R_SYNC_SERIAL1_TR_DATA_, data_out_, v1) << R_SYNC_SERIAL1_TR_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_TR_WORD
+ * - type: WO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_WORD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL1_TR_WORD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL1_TR_WORD(f1,v1) ( \
+ *R_SYNC_SERIAL1_TR_WORD__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL1_TR_WORD_) \
+ REG_VAL__R_SYNC_SERIAL1_TR_WORD_(f1##_,v1) \
+ ), \
+ R_SYNC_SERIAL1_TR_WORD__WRITE(R_SYNC_SERIAL1_TR_WORD__ADDR, *R_SYNC_SERIAL1_TR_WORD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL1_TR_WORD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL1_TR_WORD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL1_TR_WORD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL1_TR_WORD__SHADOW(f1,v1) ( \
+ *R_SYNC_SERIAL1_TR_WORD__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL1_TR_WORD_) \
+ REG_VAL__R_SYNC_SERIAL1_TR_WORD_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL1_TR_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL1_TR_WORD(f1,v1) ( \
+ (R_SYNC_SERIAL1_TR_WORD__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_TR_WORD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_TR_WORD(f1,v1) ( \
+ (R_SYNC_SERIAL1_TR_WORD__data_out__##f1##__VAL(R_SYNC_SERIAL1_TR_WORD_, data_out_, v1) << R_SYNC_SERIAL1_TR_WORD__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL1_TR_WORD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL1_TR_WORD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL1_TR_WORD_(f1_,v1) ( \
+ (R_SYNC_SERIAL1_TR_WORD__data_out__##f1_##_VAL(R_SYNC_SERIAL1_TR_WORD_, data_out_, v1) << R_SYNC_SERIAL1_TR_WORD__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_CTRL
+ * - type: WO
+ * - addr: 0xb0000078
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL3_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL3_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ *R_SYNC_SERIAL3_CTRL__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL3_CTRL_) \
+ REG_VAL__R_SYNC_SERIAL3_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \
+ ), \
+ R_SYNC_SERIAL3_CTRL__WRITE(R_SYNC_SERIAL3_CTRL__ADDR, *R_SYNC_SERIAL3_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL3_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL3_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL3_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ *R_SYNC_SERIAL3_CTRL__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL3_CTRL_) \
+ REG_VAL__R_SYNC_SERIAL3_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ (R_SYNC_SERIAL3_CTRL__tr_baud__##f1##__MASK & REG__##v1) | \
+ (R_SYNC_SERIAL3_CTRL__dma_enable__##f2##__MASK & REG__##v2) | \
+ (R_SYNC_SERIAL3_CTRL__mode__##f3##__MASK & REG__##v3) | \
+ (R_SYNC_SERIAL3_CTRL__error__##f4##__MASK & REG__##v4) | \
+ (R_SYNC_SERIAL3_CTRL__rec_enable__##f5##__MASK & REG__##v5) | \
+ (R_SYNC_SERIAL3_CTRL__f_synctype__##f6##__MASK & REG__##v6) | \
+ (R_SYNC_SERIAL3_CTRL__f_syncsize__##f7##__MASK & REG__##v7) | \
+ (R_SYNC_SERIAL3_CTRL__f_sync__##f8##__MASK & REG__##v8) | \
+ (R_SYNC_SERIAL3_CTRL__clk_mode__##f9##__MASK & REG__##v9) | \
+ (R_SYNC_SERIAL3_CTRL__clk_halt__##f10##__MASK & REG__##v10) | \
+ (R_SYNC_SERIAL3_CTRL__bitorder__##f11##__MASK & REG__##v11) | \
+ (R_SYNC_SERIAL3_CTRL__tr_enable__##f12##__MASK & REG__##v12) | \
+ (R_SYNC_SERIAL3_CTRL__wordsize__##f13##__MASK & REG__##v13) | \
+ (R_SYNC_SERIAL3_CTRL__buf_empty__##f14##__MASK & REG__##v14) | \
+ (R_SYNC_SERIAL3_CTRL__buf_full__##f15##__MASK & REG__##v15) | \
+ (R_SYNC_SERIAL3_CTRL__flow_ctrl__##f16##__MASK & REG__##v16) | \
+ (R_SYNC_SERIAL3_CTRL__clk_polarity__##f17##__MASK & REG__##v17) | \
+ (R_SYNC_SERIAL3_CTRL__frame_polarity__##f18##__MASK & REG__##v18) | \
+ (R_SYNC_SERIAL3_CTRL__status_polarity__##f19##__MASK & REG__##v19) | \
+ (R_SYNC_SERIAL3_CTRL__clk_driver__##f20##__MASK & REG__##v20) | \
+ (R_SYNC_SERIAL3_CTRL__frame_driver__##f21##__MASK & REG__##v21) | \
+ (R_SYNC_SERIAL3_CTRL__status_driver__##f22##__MASK & REG__##v22) | \
+ (R_SYNC_SERIAL3_CTRL__def_out0__##f23##__MASK & REG__##v23) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23) ( \
+ (R_SYNC_SERIAL3_CTRL__tr_baud__##f1##__VAL(R_SYNC_SERIAL3_CTRL_, tr_baud_, v1) << R_SYNC_SERIAL3_CTRL__tr_baud__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__dma_enable__##f2##__VAL(R_SYNC_SERIAL3_CTRL_, dma_enable_, v2) << R_SYNC_SERIAL3_CTRL__dma_enable__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__mode__##f3##__VAL(R_SYNC_SERIAL3_CTRL_, mode_, v3) << R_SYNC_SERIAL3_CTRL__mode__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__error__##f4##__VAL(R_SYNC_SERIAL3_CTRL_, error_, v4) << R_SYNC_SERIAL3_CTRL__error__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__rec_enable__##f5##__VAL(R_SYNC_SERIAL3_CTRL_, rec_enable_, v5) << R_SYNC_SERIAL3_CTRL__rec_enable__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__f_synctype__##f6##__VAL(R_SYNC_SERIAL3_CTRL_, f_synctype_, v6) << R_SYNC_SERIAL3_CTRL__f_synctype__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__f_syncsize__##f7##__VAL(R_SYNC_SERIAL3_CTRL_, f_syncsize_, v7) << R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__f_sync__##f8##__VAL(R_SYNC_SERIAL3_CTRL_, f_sync_, v8) << R_SYNC_SERIAL3_CTRL__f_sync__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__clk_mode__##f9##__VAL(R_SYNC_SERIAL3_CTRL_, clk_mode_, v9) << R_SYNC_SERIAL3_CTRL__clk_mode__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__clk_halt__##f10##__VAL(R_SYNC_SERIAL3_CTRL_, clk_halt_, v10) << R_SYNC_SERIAL3_CTRL__clk_halt__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__bitorder__##f11##__VAL(R_SYNC_SERIAL3_CTRL_, bitorder_, v11) << R_SYNC_SERIAL3_CTRL__bitorder__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__tr_enable__##f12##__VAL(R_SYNC_SERIAL3_CTRL_, tr_enable_, v12) << R_SYNC_SERIAL3_CTRL__tr_enable__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__wordsize__##f13##__VAL(R_SYNC_SERIAL3_CTRL_, wordsize_, v13) << R_SYNC_SERIAL3_CTRL__wordsize__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__buf_empty__##f14##__VAL(R_SYNC_SERIAL3_CTRL_, buf_empty_, v14) << R_SYNC_SERIAL3_CTRL__buf_empty__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__buf_full__##f15##__VAL(R_SYNC_SERIAL3_CTRL_, buf_full_, v15) << R_SYNC_SERIAL3_CTRL__buf_full__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__flow_ctrl__##f16##__VAL(R_SYNC_SERIAL3_CTRL_, flow_ctrl_, v16) << R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__clk_polarity__##f17##__VAL(R_SYNC_SERIAL3_CTRL_, clk_polarity_, v17) << R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__frame_polarity__##f18##__VAL(R_SYNC_SERIAL3_CTRL_, frame_polarity_, v18) << R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__status_polarity__##f19##__VAL(R_SYNC_SERIAL3_CTRL_, status_polarity_, v19) << R_SYNC_SERIAL3_CTRL__status_polarity__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__clk_driver__##f20##__VAL(R_SYNC_SERIAL3_CTRL_, clk_driver_, v20) << R_SYNC_SERIAL3_CTRL__clk_driver__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__frame_driver__##f21##__VAL(R_SYNC_SERIAL3_CTRL_, frame_driver_, v21) << R_SYNC_SERIAL3_CTRL__frame_driver__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__status_driver__##f22##__VAL(R_SYNC_SERIAL3_CTRL_, status_driver_, v22) << R_SYNC_SERIAL3_CTRL__status_driver__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__def_out0__##f23##__VAL(R_SYNC_SERIAL3_CTRL_, def_out0_, v23) << R_SYNC_SERIAL3_CTRL__def_out0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23) ( \
+ (R_SYNC_SERIAL3_CTRL__tr_baud__##f1_##_VAL(R_SYNC_SERIAL3_CTRL_, tr_baud_, v1) << R_SYNC_SERIAL3_CTRL__tr_baud__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__dma_enable__##f2_##_VAL(R_SYNC_SERIAL3_CTRL_, dma_enable_, v2) << R_SYNC_SERIAL3_CTRL__dma_enable__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__mode__##f3_##_VAL(R_SYNC_SERIAL3_CTRL_, mode_, v3) << R_SYNC_SERIAL3_CTRL__mode__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__error__##f4_##_VAL(R_SYNC_SERIAL3_CTRL_, error_, v4) << R_SYNC_SERIAL3_CTRL__error__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__rec_enable__##f5_##_VAL(R_SYNC_SERIAL3_CTRL_, rec_enable_, v5) << R_SYNC_SERIAL3_CTRL__rec_enable__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__f_synctype__##f6_##_VAL(R_SYNC_SERIAL3_CTRL_, f_synctype_, v6) << R_SYNC_SERIAL3_CTRL__f_synctype__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__f_syncsize__##f7_##_VAL(R_SYNC_SERIAL3_CTRL_, f_syncsize_, v7) << R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__f_sync__##f8_##_VAL(R_SYNC_SERIAL3_CTRL_, f_sync_, v8) << R_SYNC_SERIAL3_CTRL__f_sync__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__clk_mode__##f9_##_VAL(R_SYNC_SERIAL3_CTRL_, clk_mode_, v9) << R_SYNC_SERIAL3_CTRL__clk_mode__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__clk_halt__##f10_##_VAL(R_SYNC_SERIAL3_CTRL_, clk_halt_, v10) << R_SYNC_SERIAL3_CTRL__clk_halt__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__bitorder__##f11_##_VAL(R_SYNC_SERIAL3_CTRL_, bitorder_, v11) << R_SYNC_SERIAL3_CTRL__bitorder__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__tr_enable__##f12_##_VAL(R_SYNC_SERIAL3_CTRL_, tr_enable_, v12) << R_SYNC_SERIAL3_CTRL__tr_enable__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__wordsize__##f13_##_VAL(R_SYNC_SERIAL3_CTRL_, wordsize_, v13) << R_SYNC_SERIAL3_CTRL__wordsize__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__buf_empty__##f14_##_VAL(R_SYNC_SERIAL3_CTRL_, buf_empty_, v14) << R_SYNC_SERIAL3_CTRL__buf_empty__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__buf_full__##f15_##_VAL(R_SYNC_SERIAL3_CTRL_, buf_full_, v15) << R_SYNC_SERIAL3_CTRL__buf_full__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__flow_ctrl__##f16_##_VAL(R_SYNC_SERIAL3_CTRL_, flow_ctrl_, v16) << R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__clk_polarity__##f17_##_VAL(R_SYNC_SERIAL3_CTRL_, clk_polarity_, v17) << R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__frame_polarity__##f18_##_VAL(R_SYNC_SERIAL3_CTRL_, frame_polarity_, v18) << R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__status_polarity__##f19_##_VAL(R_SYNC_SERIAL3_CTRL_, status_polarity_, v19) << R_SYNC_SERIAL3_CTRL__status_polarity__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__clk_driver__##f20_##_VAL(R_SYNC_SERIAL3_CTRL_, clk_driver_, v20) << R_SYNC_SERIAL3_CTRL__clk_driver__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__frame_driver__##f21_##_VAL(R_SYNC_SERIAL3_CTRL_, frame_driver_, v21) << R_SYNC_SERIAL3_CTRL__frame_driver__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__status_driver__##f22_##_VAL(R_SYNC_SERIAL3_CTRL_, status_driver_, v22) << R_SYNC_SERIAL3_CTRL__status_driver__BITNR) | \
+ (R_SYNC_SERIAL3_CTRL__def_out0__##f23_##_VAL(R_SYNC_SERIAL3_CTRL_, def_out0_, v23) << R_SYNC_SERIAL3_CTRL__def_out0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_REC_BYTE
+ * - type: RO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_REC_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL3_REC_BYTE(f1,v1) ( \
+ (R_SYNC_SERIAL3_REC_BYTE__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_REC_BYTE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_REC_BYTE(f1,v1) ( \
+ (R_SYNC_SERIAL3_REC_BYTE__data_in__##f1##__VAL(R_SYNC_SERIAL3_REC_BYTE_, data_in_, v1) << R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_BYTE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_REC_BYTE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_REC_BYTE_(f1_,v1) ( \
+ (R_SYNC_SERIAL3_REC_BYTE__data_in__##f1_##_VAL(R_SYNC_SERIAL3_REC_BYTE_, data_in_, v1) << R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_REC_DATA
+ * - type: RO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL3_REC_DATA(f1,v1) ( \
+ (R_SYNC_SERIAL3_REC_DATA__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_REC_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_REC_DATA(f1,v1) ( \
+ (R_SYNC_SERIAL3_REC_DATA__data_in__##f1##__VAL(R_SYNC_SERIAL3_REC_DATA_, data_in_, v1) << R_SYNC_SERIAL3_REC_DATA__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_REC_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_REC_DATA_(f1_,v1) ( \
+ (R_SYNC_SERIAL3_REC_DATA__data_in__##f1_##_VAL(R_SYNC_SERIAL3_REC_DATA_, data_in_, v1) << R_SYNC_SERIAL3_REC_DATA__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_REC_WORD
+ * - type: RO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_REC_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL3_REC_WORD(f1,v1) ( \
+ (R_SYNC_SERIAL3_REC_WORD__data_in__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_REC_WORD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_REC_WORD(f1,v1) ( \
+ (R_SYNC_SERIAL3_REC_WORD__data_in__##f1##__VAL(R_SYNC_SERIAL3_REC_WORD_, data_in_, v1) << R_SYNC_SERIAL3_REC_WORD__data_in__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_REC_WORD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_REC_WORD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_REC_WORD_(f1_,v1) ( \
+ (R_SYNC_SERIAL3_REC_WORD__data_in__##f1_##_VAL(R_SYNC_SERIAL3_REC_WORD_, data_in_, v1) << R_SYNC_SERIAL3_REC_WORD__data_in__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_STATUS
+ * - type: RO
+ * - addr: 0xb0000078
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL3_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SYNC_SERIAL3_STATUS__rec_status__##f1##__MASK & REG__##v1) | \
+ (R_SYNC_SERIAL3_STATUS__tr_empty__##f2##__MASK & REG__##v2) | \
+ (R_SYNC_SERIAL3_STATUS__tr_ready__##f3##__MASK & REG__##v3) | \
+ (R_SYNC_SERIAL3_STATUS__pin_1__##f4##__MASK & REG__##v4) | \
+ (R_SYNC_SERIAL3_STATUS__pin_0__##f5##__MASK & REG__##v5) | \
+ (R_SYNC_SERIAL3_STATUS__underflow__##f6##__MASK & REG__##v6) | \
+ (R_SYNC_SERIAL3_STATUS__overrun__##f7##__MASK & REG__##v7) | \
+ (R_SYNC_SERIAL3_STATUS__data_avail__##f8##__MASK & REG__##v8) | \
+ (R_SYNC_SERIAL3_STATUS__data__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_SYNC_SERIAL3_STATUS__rec_status__##f1##__VAL(R_SYNC_SERIAL3_STATUS_, rec_status_, v1) << R_SYNC_SERIAL3_STATUS__rec_status__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__tr_empty__##f2##__VAL(R_SYNC_SERIAL3_STATUS_, tr_empty_, v2) << R_SYNC_SERIAL3_STATUS__tr_empty__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__tr_ready__##f3##__VAL(R_SYNC_SERIAL3_STATUS_, tr_ready_, v3) << R_SYNC_SERIAL3_STATUS__tr_ready__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__pin_1__##f4##__VAL(R_SYNC_SERIAL3_STATUS_, pin_1_, v4) << R_SYNC_SERIAL3_STATUS__pin_1__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__pin_0__##f5##__VAL(R_SYNC_SERIAL3_STATUS_, pin_0_, v5) << R_SYNC_SERIAL3_STATUS__pin_0__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__underflow__##f6##__VAL(R_SYNC_SERIAL3_STATUS_, underflow_, v6) << R_SYNC_SERIAL3_STATUS__underflow__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__overrun__##f7##__VAL(R_SYNC_SERIAL3_STATUS_, overrun_, v7) << R_SYNC_SERIAL3_STATUS__overrun__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__data_avail__##f8##__VAL(R_SYNC_SERIAL3_STATUS_, data_avail_, v8) << R_SYNC_SERIAL3_STATUS__data_avail__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__data__##f9##__VAL(R_SYNC_SERIAL3_STATUS_, data_, v9) << R_SYNC_SERIAL3_STATUS__data__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_SYNC_SERIAL3_STATUS__rec_status__##f1_##_VAL(R_SYNC_SERIAL3_STATUS_, rec_status_, v1) << R_SYNC_SERIAL3_STATUS__rec_status__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__tr_empty__##f2_##_VAL(R_SYNC_SERIAL3_STATUS_, tr_empty_, v2) << R_SYNC_SERIAL3_STATUS__tr_empty__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__tr_ready__##f3_##_VAL(R_SYNC_SERIAL3_STATUS_, tr_ready_, v3) << R_SYNC_SERIAL3_STATUS__tr_ready__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__pin_1__##f4_##_VAL(R_SYNC_SERIAL3_STATUS_, pin_1_, v4) << R_SYNC_SERIAL3_STATUS__pin_1__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__pin_0__##f5_##_VAL(R_SYNC_SERIAL3_STATUS_, pin_0_, v5) << R_SYNC_SERIAL3_STATUS__pin_0__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__underflow__##f6_##_VAL(R_SYNC_SERIAL3_STATUS_, underflow_, v6) << R_SYNC_SERIAL3_STATUS__underflow__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__overrun__##f7_##_VAL(R_SYNC_SERIAL3_STATUS_, overrun_, v7) << R_SYNC_SERIAL3_STATUS__overrun__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__data_avail__##f8_##_VAL(R_SYNC_SERIAL3_STATUS_, data_avail_, v8) << R_SYNC_SERIAL3_STATUS__data_avail__BITNR) | \
+ (R_SYNC_SERIAL3_STATUS__data__##f9_##_VAL(R_SYNC_SERIAL3_STATUS_, data_, v9) << R_SYNC_SERIAL3_STATUS__data__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_TR_BYTE
+ * - type: WO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_BYTE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL3_TR_BYTE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL3_TR_BYTE(f1,v1) ( \
+ *R_SYNC_SERIAL3_TR_BYTE__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL3_TR_BYTE_) \
+ REG_VAL__R_SYNC_SERIAL3_TR_BYTE_(f1##_,v1) \
+ ), \
+ R_SYNC_SERIAL3_TR_BYTE__WRITE(R_SYNC_SERIAL3_TR_BYTE__ADDR, *R_SYNC_SERIAL3_TR_BYTE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_BYTE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_BYTE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL3_TR_BYTE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL3_TR_BYTE__SHADOW(f1,v1) ( \
+ *R_SYNC_SERIAL3_TR_BYTE__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL3_TR_BYTE_) \
+ REG_VAL__R_SYNC_SERIAL3_TR_BYTE_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_TR_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL3_TR_BYTE(f1,v1) ( \
+ (R_SYNC_SERIAL3_TR_BYTE__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_BYTE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_TR_BYTE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_TR_BYTE(f1,v1) ( \
+ (R_SYNC_SERIAL3_TR_BYTE__data_out__##f1##__VAL(R_SYNC_SERIAL3_TR_BYTE_, data_out_, v1) << R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_BYTE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_TR_BYTE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_TR_BYTE_(f1_,v1) ( \
+ (R_SYNC_SERIAL3_TR_BYTE__data_out__##f1_##_VAL(R_SYNC_SERIAL3_TR_BYTE_, data_out_, v1) << R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_TR_DATA
+ * - type: WO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL3_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL3_TR_DATA(f1,v1) ( \
+ *R_SYNC_SERIAL3_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL3_TR_DATA_) \
+ REG_VAL__R_SYNC_SERIAL3_TR_DATA_(f1##_,v1) \
+ ), \
+ R_SYNC_SERIAL3_TR_DATA__WRITE(R_SYNC_SERIAL3_TR_DATA__ADDR, *R_SYNC_SERIAL3_TR_DATA__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_DATA__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_DATA.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL3_TR_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL3_TR_DATA__SHADOW(f1,v1) ( \
+ *R_SYNC_SERIAL3_TR_DATA__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL3_TR_DATA_) \
+ REG_VAL__R_SYNC_SERIAL3_TR_DATA_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL3_TR_DATA(f1,v1) ( \
+ (R_SYNC_SERIAL3_TR_DATA__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_TR_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_TR_DATA(f1,v1) ( \
+ (R_SYNC_SERIAL3_TR_DATA__data_out__##f1##__VAL(R_SYNC_SERIAL3_TR_DATA_, data_out_, v1) << R_SYNC_SERIAL3_TR_DATA__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_TR_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_TR_DATA_(f1_,v1) ( \
+ (R_SYNC_SERIAL3_TR_DATA__data_out__##f1_##_VAL(R_SYNC_SERIAL3_TR_DATA_, data_out_, v1) << R_SYNC_SERIAL3_TR_DATA__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_TR_WORD
+ * - type: WO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_WORD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL3_TR_WORD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL3_TR_WORD(f1,v1) ( \
+ *R_SYNC_SERIAL3_TR_WORD__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL3_TR_WORD_) \
+ REG_VAL__R_SYNC_SERIAL3_TR_WORD_(f1##_,v1) \
+ ), \
+ R_SYNC_SERIAL3_TR_WORD__WRITE(R_SYNC_SERIAL3_TR_WORD__ADDR, *R_SYNC_SERIAL3_TR_WORD__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL3_TR_WORD__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL3_TR_WORD.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL3_TR_WORD.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL3_TR_WORD__SHADOW(f1,v1) ( \
+ *R_SYNC_SERIAL3_TR_WORD__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL3_TR_WORD_) \
+ REG_VAL__R_SYNC_SERIAL3_TR_WORD_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL3_TR_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL3_TR_WORD(f1,v1) ( \
+ (R_SYNC_SERIAL3_TR_WORD__data_out__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_WORD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_TR_WORD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_TR_WORD(f1,v1) ( \
+ (R_SYNC_SERIAL3_TR_WORD__data_out__##f1##__VAL(R_SYNC_SERIAL3_TR_WORD_, data_out_, v1) << R_SYNC_SERIAL3_TR_WORD__data_out__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL3_TR_WORD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL3_TR_WORD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL3_TR_WORD_(f1_,v1) ( \
+ (R_SYNC_SERIAL3_TR_WORD__data_out__##f1_##_VAL(R_SYNC_SERIAL3_TR_WORD_, data_out_, v1) << R_SYNC_SERIAL3_TR_WORD__data_out__BITNR) \
+)
+
+#endif
+
+/*
+ * R_SYNC_SERIAL_PRESCALE
+ * - type: WO
+ * - addr: 0xb00000f4
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL_PRESCALE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_SYNC_SERIAL_PRESCALE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL_PRESCALE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SYNC_SERIAL_PRESCALE__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL_PRESCALE_) \
+ REG_VAL__R_SYNC_SERIAL_PRESCALE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ), \
+ R_SYNC_SERIAL_PRESCALE__WRITE(R_SYNC_SERIAL_PRESCALE__ADDR, *R_SYNC_SERIAL_PRESCALE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_SYNC_SERIAL_PRESCALE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_SYNC_SERIAL_PRESCALE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_SYNC_SERIAL_PRESCALE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_SYNC_SERIAL_PRESCALE__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ *R_SYNC_SERIAL_PRESCALE__SADDR = ( \
+ REG_INITIATED(R_SYNC_SERIAL_PRESCALE_) \
+ REG_VAL__R_SYNC_SERIAL_PRESCALE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_SYNC_SERIAL_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_SYNC_SERIAL_PRESCALE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SYNC_SERIAL_PRESCALE__clk_sel_u3__##f1##__MASK & REG__##v1) | \
+ (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__##f2##__MASK & REG__##v2) | \
+ (R_SYNC_SERIAL_PRESCALE__clk_sel_u1__##f3##__MASK & REG__##v3) | \
+ (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__##f4##__MASK & REG__##v4) | \
+ (R_SYNC_SERIAL_PRESCALE__prescaler__##f5##__MASK & REG__##v5) | \
+ (R_SYNC_SERIAL_PRESCALE__warp_mode__##f6##__MASK & REG__##v6) | \
+ (R_SYNC_SERIAL_PRESCALE__frame_rate__##f7##__MASK & REG__##v7) | \
+ (R_SYNC_SERIAL_PRESCALE__word_rate__##f8##__MASK & REG__##v8) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL_PRESCALE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL_PRESCALE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8) ( \
+ (R_SYNC_SERIAL_PRESCALE__clk_sel_u3__##f1##__VAL(R_SYNC_SERIAL_PRESCALE_, clk_sel_u3_, v1) << R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__##f2##__VAL(R_SYNC_SERIAL_PRESCALE_, word_stb_sel_u3_, v2) << R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__clk_sel_u1__##f3##__VAL(R_SYNC_SERIAL_PRESCALE_, clk_sel_u1_, v3) << R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__##f4##__VAL(R_SYNC_SERIAL_PRESCALE_, word_stb_sel_u1_, v4) << R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__prescaler__##f5##__VAL(R_SYNC_SERIAL_PRESCALE_, prescaler_, v5) << R_SYNC_SERIAL_PRESCALE__prescaler__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__warp_mode__##f6##__VAL(R_SYNC_SERIAL_PRESCALE_, warp_mode_, v6) << R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__frame_rate__##f7##__VAL(R_SYNC_SERIAL_PRESCALE_, frame_rate_, v7) << R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__word_rate__##f8##__VAL(R_SYNC_SERIAL_PRESCALE_, word_rate_, v8) << R_SYNC_SERIAL_PRESCALE__word_rate__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_SYNC_SERIAL_PRESCALE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_SYNC_SERIAL_PRESCALE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_SYNC_SERIAL_PRESCALE_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8) ( \
+ (R_SYNC_SERIAL_PRESCALE__clk_sel_u3__##f1_##_VAL(R_SYNC_SERIAL_PRESCALE_, clk_sel_u3_, v1) << R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__##f2_##_VAL(R_SYNC_SERIAL_PRESCALE_, word_stb_sel_u3_, v2) << R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__clk_sel_u1__##f3_##_VAL(R_SYNC_SERIAL_PRESCALE_, clk_sel_u1_, v3) << R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__##f4_##_VAL(R_SYNC_SERIAL_PRESCALE_, word_stb_sel_u1_, v4) << R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__prescaler__##f5_##_VAL(R_SYNC_SERIAL_PRESCALE_, prescaler_, v5) << R_SYNC_SERIAL_PRESCALE__prescaler__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__warp_mode__##f6_##_VAL(R_SYNC_SERIAL_PRESCALE_, warp_mode_, v6) << R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__frame_rate__##f7_##_VAL(R_SYNC_SERIAL_PRESCALE_, frame_rate_, v7) << R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR) | \
+ (R_SYNC_SERIAL_PRESCALE__word_rate__##f8_##_VAL(R_SYNC_SERIAL_PRESCALE_, word_rate_, v8) << R_SYNC_SERIAL_PRESCALE__word_rate__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TEST_MODE
+ * - type: WO
+ * - addr: 0xb00000fc
+ * - group: Test mode registers
+ */
+
+#if USE_GROUP__Test_mode_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TEST_MODE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TEST_MODE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_TEST_MODE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TEST_MODE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \
+ *R_TEST_MODE__SADDR = ( \
+ REG_INITIATED(R_TEST_MODE_) \
+ REG_VAL__R_TEST_MODE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16) \
+ ), \
+ R_TEST_MODE__WRITE(R_TEST_MODE__ADDR, *R_TEST_MODE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TEST_MODE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TEST_MODE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_TEST_MODE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TEST_MODE__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \
+ *R_TEST_MODE__SADDR = ( \
+ REG_INITIATED(R_TEST_MODE_) \
+ REG_VAL__R_TEST_MODE_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TEST_MODE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TEST_MODE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \
+ (R_TEST_MODE__single_step__##f1##__MASK & REG__##v1) | \
+ (R_TEST_MODE__step_wr__##f2##__MASK & REG__##v2) | \
+ (R_TEST_MODE__step_rd__##f3##__MASK & REG__##v3) | \
+ (R_TEST_MODE__step_fetch__##f4##__MASK & REG__##v4) | \
+ (R_TEST_MODE__mmu_test__##f5##__MASK & REG__##v5) | \
+ (R_TEST_MODE__usb_test__##f6##__MASK & REG__##v6) | \
+ (R_TEST_MODE__scsi_timer_test__##f7##__MASK & REG__##v7) | \
+ (R_TEST_MODE__backoff__##f8##__MASK & REG__##v8) | \
+ (R_TEST_MODE__snmp_test__##f9##__MASK & REG__##v9) | \
+ (R_TEST_MODE__snmp_inc__##f10##__MASK & REG__##v10) | \
+ (R_TEST_MODE__ser_loop__##f11##__MASK & REG__##v11) | \
+ (R_TEST_MODE__baudrate__##f12##__MASK & REG__##v12) | \
+ (R_TEST_MODE__timer__##f13##__MASK & REG__##v13) | \
+ (R_TEST_MODE__cache_test__##f14##__MASK & REG__##v14) | \
+ (R_TEST_MODE__tag_test__##f15##__MASK & REG__##v15) | \
+ (R_TEST_MODE__cache_enable__##f16##__MASK & REG__##v16) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TEST_MODE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TEST_MODE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TEST_MODE(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16) ( \
+ (R_TEST_MODE__single_step__##f1##__VAL(R_TEST_MODE_, single_step_, v1) << R_TEST_MODE__single_step__BITNR) | \
+ (R_TEST_MODE__step_wr__##f2##__VAL(R_TEST_MODE_, step_wr_, v2) << R_TEST_MODE__step_wr__BITNR) | \
+ (R_TEST_MODE__step_rd__##f3##__VAL(R_TEST_MODE_, step_rd_, v3) << R_TEST_MODE__step_rd__BITNR) | \
+ (R_TEST_MODE__step_fetch__##f4##__VAL(R_TEST_MODE_, step_fetch_, v4) << R_TEST_MODE__step_fetch__BITNR) | \
+ (R_TEST_MODE__mmu_test__##f5##__VAL(R_TEST_MODE_, mmu_test_, v5) << R_TEST_MODE__mmu_test__BITNR) | \
+ (R_TEST_MODE__usb_test__##f6##__VAL(R_TEST_MODE_, usb_test_, v6) << R_TEST_MODE__usb_test__BITNR) | \
+ (R_TEST_MODE__scsi_timer_test__##f7##__VAL(R_TEST_MODE_, scsi_timer_test_, v7) << R_TEST_MODE__scsi_timer_test__BITNR) | \
+ (R_TEST_MODE__backoff__##f8##__VAL(R_TEST_MODE_, backoff_, v8) << R_TEST_MODE__backoff__BITNR) | \
+ (R_TEST_MODE__snmp_test__##f9##__VAL(R_TEST_MODE_, snmp_test_, v9) << R_TEST_MODE__snmp_test__BITNR) | \
+ (R_TEST_MODE__snmp_inc__##f10##__VAL(R_TEST_MODE_, snmp_inc_, v10) << R_TEST_MODE__snmp_inc__BITNR) | \
+ (R_TEST_MODE__ser_loop__##f11##__VAL(R_TEST_MODE_, ser_loop_, v11) << R_TEST_MODE__ser_loop__BITNR) | \
+ (R_TEST_MODE__baudrate__##f12##__VAL(R_TEST_MODE_, baudrate_, v12) << R_TEST_MODE__baudrate__BITNR) | \
+ (R_TEST_MODE__timer__##f13##__VAL(R_TEST_MODE_, timer_, v13) << R_TEST_MODE__timer__BITNR) | \
+ (R_TEST_MODE__cache_test__##f14##__VAL(R_TEST_MODE_, cache_test_, v14) << R_TEST_MODE__cache_test__BITNR) | \
+ (R_TEST_MODE__tag_test__##f15##__VAL(R_TEST_MODE_, tag_test_, v15) << R_TEST_MODE__tag_test__BITNR) | \
+ (R_TEST_MODE__cache_enable__##f16##__VAL(R_TEST_MODE_, cache_enable_, v16) << R_TEST_MODE__cache_enable__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TEST_MODE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TEST_MODE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TEST_MODE_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16) ( \
+ (R_TEST_MODE__single_step__##f1_##_VAL(R_TEST_MODE_, single_step_, v1) << R_TEST_MODE__single_step__BITNR) | \
+ (R_TEST_MODE__step_wr__##f2_##_VAL(R_TEST_MODE_, step_wr_, v2) << R_TEST_MODE__step_wr__BITNR) | \
+ (R_TEST_MODE__step_rd__##f3_##_VAL(R_TEST_MODE_, step_rd_, v3) << R_TEST_MODE__step_rd__BITNR) | \
+ (R_TEST_MODE__step_fetch__##f4_##_VAL(R_TEST_MODE_, step_fetch_, v4) << R_TEST_MODE__step_fetch__BITNR) | \
+ (R_TEST_MODE__mmu_test__##f5_##_VAL(R_TEST_MODE_, mmu_test_, v5) << R_TEST_MODE__mmu_test__BITNR) | \
+ (R_TEST_MODE__usb_test__##f6_##_VAL(R_TEST_MODE_, usb_test_, v6) << R_TEST_MODE__usb_test__BITNR) | \
+ (R_TEST_MODE__scsi_timer_test__##f7_##_VAL(R_TEST_MODE_, scsi_timer_test_, v7) << R_TEST_MODE__scsi_timer_test__BITNR) | \
+ (R_TEST_MODE__backoff__##f8_##_VAL(R_TEST_MODE_, backoff_, v8) << R_TEST_MODE__backoff__BITNR) | \
+ (R_TEST_MODE__snmp_test__##f9_##_VAL(R_TEST_MODE_, snmp_test_, v9) << R_TEST_MODE__snmp_test__BITNR) | \
+ (R_TEST_MODE__snmp_inc__##f10_##_VAL(R_TEST_MODE_, snmp_inc_, v10) << R_TEST_MODE__snmp_inc__BITNR) | \
+ (R_TEST_MODE__ser_loop__##f11_##_VAL(R_TEST_MODE_, ser_loop_, v11) << R_TEST_MODE__ser_loop__BITNR) | \
+ (R_TEST_MODE__baudrate__##f12_##_VAL(R_TEST_MODE_, baudrate_, v12) << R_TEST_MODE__baudrate__BITNR) | \
+ (R_TEST_MODE__timer__##f13_##_VAL(R_TEST_MODE_, timer_, v13) << R_TEST_MODE__timer__BITNR) | \
+ (R_TEST_MODE__cache_test__##f14_##_VAL(R_TEST_MODE_, cache_test_, v14) << R_TEST_MODE__cache_test__BITNR) | \
+ (R_TEST_MODE__tag_test__##f15_##_VAL(R_TEST_MODE_, tag_test_, v15) << R_TEST_MODE__tag_test__BITNR) | \
+ (R_TEST_MODE__cache_enable__##f16_##_VAL(R_TEST_MODE_, cache_enable_, v16) << R_TEST_MODE__cache_enable__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TIMER01_DATA
+ * - type: RO
+ * - addr: 0xb0000022
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TIMER01_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TIMER01_DATA(f1,v1) ( \
+ (R_TIMER01_DATA__count__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER01_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER01_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER01_DATA(f1,v1) ( \
+ (R_TIMER01_DATA__count__##f1##__VAL(R_TIMER01_DATA_, count_, v1) << R_TIMER01_DATA__count__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER01_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER01_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER01_DATA_(f1_,v1) ( \
+ (R_TIMER01_DATA__count__##f1_##_VAL(R_TIMER01_DATA_, count_, v1) << R_TIMER01_DATA__count__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TIMER0_DATA
+ * - type: RO
+ * - addr: 0xb0000022
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TIMER0_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TIMER0_DATA(f1,v1) ( \
+ (R_TIMER0_DATA__count__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER0_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER0_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER0_DATA(f1,v1) ( \
+ (R_TIMER0_DATA__count__##f1##__VAL(R_TIMER0_DATA_, count_, v1) << R_TIMER0_DATA__count__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER0_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER0_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER0_DATA_(f1_,v1) ( \
+ (R_TIMER0_DATA__count__##f1_##_VAL(R_TIMER0_DATA_, count_, v1) << R_TIMER0_DATA__count__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TIMER1_DATA
+ * - type: RO
+ * - addr: 0xb0000023
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TIMER1_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TIMER1_DATA(f1,v1) ( \
+ (R_TIMER1_DATA__count__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER1_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER1_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER1_DATA(f1,v1) ( \
+ (R_TIMER1_DATA__count__##f1##__VAL(R_TIMER1_DATA_, count_, v1) << R_TIMER1_DATA__count__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER1_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER1_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER1_DATA_(f1_,v1) ( \
+ (R_TIMER1_DATA__count__##f1_##_VAL(R_TIMER1_DATA_, count_, v1) << R_TIMER1_DATA__count__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TIMER_CTRL
+ * - type: WO
+ * - addr: 0xb0000020
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TIMER_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TIMER_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_TIMER_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TIMER_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_TIMER_CTRL__SADDR = ( \
+ REG_INITIATED(R_TIMER_CTRL_) \
+ REG_VAL__R_TIMER_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ), \
+ R_TIMER_CTRL__WRITE(R_TIMER_CTRL__ADDR, *R_TIMER_CTRL__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TIMER_CTRL__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TIMER_CTRL.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_TIMER_CTRL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TIMER_CTRL__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_TIMER_CTRL__SADDR = ( \
+ REG_INITIATED(R_TIMER_CTRL_) \
+ REG_VAL__R_TIMER_CTRL_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TIMER_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TIMER_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_TIMER_CTRL__timerdiv1__##f1##__MASK & REG__##v1) | \
+ (R_TIMER_CTRL__timerdiv0__##f2##__MASK & REG__##v2) | \
+ (R_TIMER_CTRL__presc_timer1__##f3##__MASK & REG__##v3) | \
+ (R_TIMER_CTRL__i1__##f4##__MASK & REG__##v4) | \
+ (R_TIMER_CTRL__tm1__##f5##__MASK & REG__##v5) | \
+ (R_TIMER_CTRL__clksel1__##f6##__MASK & REG__##v6) | \
+ (R_TIMER_CTRL__presc_ext__##f7##__MASK & REG__##v7) | \
+ (R_TIMER_CTRL__i0__##f8##__MASK & REG__##v8) | \
+ (R_TIMER_CTRL__tm0__##f9##__MASK & REG__##v9) | \
+ (R_TIMER_CTRL__clksel0__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER_CTRL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER_CTRL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER_CTRL(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_TIMER_CTRL__timerdiv1__##f1##__VAL(R_TIMER_CTRL_, timerdiv1_, v1) << R_TIMER_CTRL__timerdiv1__BITNR) | \
+ (R_TIMER_CTRL__timerdiv0__##f2##__VAL(R_TIMER_CTRL_, timerdiv0_, v2) << R_TIMER_CTRL__timerdiv0__BITNR) | \
+ (R_TIMER_CTRL__presc_timer1__##f3##__VAL(R_TIMER_CTRL_, presc_timer1_, v3) << R_TIMER_CTRL__presc_timer1__BITNR) | \
+ (R_TIMER_CTRL__i1__##f4##__VAL(R_TIMER_CTRL_, i1_, v4) << R_TIMER_CTRL__i1__BITNR) | \
+ (R_TIMER_CTRL__tm1__##f5##__VAL(R_TIMER_CTRL_, tm1_, v5) << R_TIMER_CTRL__tm1__BITNR) | \
+ (R_TIMER_CTRL__clksel1__##f6##__VAL(R_TIMER_CTRL_, clksel1_, v6) << R_TIMER_CTRL__clksel1__BITNR) | \
+ (R_TIMER_CTRL__presc_ext__##f7##__VAL(R_TIMER_CTRL_, presc_ext_, v7) << R_TIMER_CTRL__presc_ext__BITNR) | \
+ (R_TIMER_CTRL__i0__##f8##__VAL(R_TIMER_CTRL_, i0_, v8) << R_TIMER_CTRL__i0__BITNR) | \
+ (R_TIMER_CTRL__tm0__##f9##__VAL(R_TIMER_CTRL_, tm0_, v9) << R_TIMER_CTRL__tm0__BITNR) | \
+ (R_TIMER_CTRL__clksel0__##f10##__VAL(R_TIMER_CTRL_, clksel0_, v10) << R_TIMER_CTRL__clksel0__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER_CTRL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER_CTRL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER_CTRL_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_TIMER_CTRL__timerdiv1__##f1_##_VAL(R_TIMER_CTRL_, timerdiv1_, v1) << R_TIMER_CTRL__timerdiv1__BITNR) | \
+ (R_TIMER_CTRL__timerdiv0__##f2_##_VAL(R_TIMER_CTRL_, timerdiv0_, v2) << R_TIMER_CTRL__timerdiv0__BITNR) | \
+ (R_TIMER_CTRL__presc_timer1__##f3_##_VAL(R_TIMER_CTRL_, presc_timer1_, v3) << R_TIMER_CTRL__presc_timer1__BITNR) | \
+ (R_TIMER_CTRL__i1__##f4_##_VAL(R_TIMER_CTRL_, i1_, v4) << R_TIMER_CTRL__i1__BITNR) | \
+ (R_TIMER_CTRL__tm1__##f5_##_VAL(R_TIMER_CTRL_, tm1_, v5) << R_TIMER_CTRL__tm1__BITNR) | \
+ (R_TIMER_CTRL__clksel1__##f6_##_VAL(R_TIMER_CTRL_, clksel1_, v6) << R_TIMER_CTRL__clksel1__BITNR) | \
+ (R_TIMER_CTRL__presc_ext__##f7_##_VAL(R_TIMER_CTRL_, presc_ext_, v7) << R_TIMER_CTRL__presc_ext__BITNR) | \
+ (R_TIMER_CTRL__i0__##f8_##_VAL(R_TIMER_CTRL_, i0_, v8) << R_TIMER_CTRL__i0__BITNR) | \
+ (R_TIMER_CTRL__tm0__##f9_##_VAL(R_TIMER_CTRL_, tm0_, v9) << R_TIMER_CTRL__tm0__BITNR) | \
+ (R_TIMER_CTRL__clksel0__##f10_##_VAL(R_TIMER_CTRL_, clksel0_, v10) << R_TIMER_CTRL__clksel0__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TIMER_DATA
+ * - type: RO
+ * - addr: 0xb0000020
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TIMER_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TIMER_DATA(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_TIMER_DATA__timer1__##f1##__MASK & REG__##v1) | \
+ (R_TIMER_DATA__timer0__##f2##__MASK & REG__##v2) | \
+ (R_TIMER_DATA__clkdiv_high__##f3##__MASK & REG__##v3) | \
+ (R_TIMER_DATA__clkdiv_low__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER_DATA(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_TIMER_DATA__timer1__##f1##__VAL(R_TIMER_DATA_, timer1_, v1) << R_TIMER_DATA__timer1__BITNR) | \
+ (R_TIMER_DATA__timer0__##f2##__VAL(R_TIMER_DATA_, timer0_, v2) << R_TIMER_DATA__timer0__BITNR) | \
+ (R_TIMER_DATA__clkdiv_high__##f3##__VAL(R_TIMER_DATA_, clkdiv_high_, v3) << R_TIMER_DATA__clkdiv_high__BITNR) | \
+ (R_TIMER_DATA__clkdiv_low__##f4##__VAL(R_TIMER_DATA_, clkdiv_low_, v4) << R_TIMER_DATA__clkdiv_low__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_TIMER_DATA__timer1__##f1_##_VAL(R_TIMER_DATA_, timer1_, v1) << R_TIMER_DATA__timer1__BITNR) | \
+ (R_TIMER_DATA__timer0__##f2_##_VAL(R_TIMER_DATA_, timer0_, v2) << R_TIMER_DATA__timer0__BITNR) | \
+ (R_TIMER_DATA__clkdiv_high__##f3_##_VAL(R_TIMER_DATA_, clkdiv_high_, v3) << R_TIMER_DATA__clkdiv_high__BITNR) | \
+ (R_TIMER_DATA__clkdiv_low__##f4_##_VAL(R_TIMER_DATA_, clkdiv_low_, v4) << R_TIMER_DATA__clkdiv_low__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TIMER_PRESCALE
+ * - type: WO
+ * - addr: 0xb00000f0
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TIMER_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TIMER_PRESCALE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_TIMER_PRESCALE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TIMER_PRESCALE(f1,v1) ( \
+ *R_TIMER_PRESCALE__SADDR = ( \
+ REG_INITIATED(R_TIMER_PRESCALE_) \
+ REG_VAL__R_TIMER_PRESCALE_(f1##_,v1) \
+ ), \
+ R_TIMER_PRESCALE__WRITE(R_TIMER_PRESCALE__ADDR, *R_TIMER_PRESCALE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TIMER_PRESCALE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TIMER_PRESCALE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_TIMER_PRESCALE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TIMER_PRESCALE__SHADOW(f1,v1) ( \
+ *R_TIMER_PRESCALE__SADDR = ( \
+ REG_INITIATED(R_TIMER_PRESCALE_) \
+ REG_VAL__R_TIMER_PRESCALE_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TIMER_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TIMER_PRESCALE(f1,v1) ( \
+ (R_TIMER_PRESCALE__tim_presc__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER_PRESCALE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER_PRESCALE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER_PRESCALE(f1,v1) ( \
+ (R_TIMER_PRESCALE__tim_presc__##f1##__VAL(R_TIMER_PRESCALE_, tim_presc_, v1) << R_TIMER_PRESCALE__tim_presc__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIMER_PRESCALE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIMER_PRESCALE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TIMER_PRESCALE_(f1_,v1) ( \
+ (R_TIMER_PRESCALE__tim_presc__##f1_##_VAL(R_TIMER_PRESCALE_, tim_presc_, v1) << R_TIMER_PRESCALE__tim_presc__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TIM_PRESC_STATUS
+ * - type: RO
+ * - addr: 0xb00000f0
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TIM_PRESC_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TIM_PRESC_STATUS(f1,v1) ( \
+ (R_TIM_PRESC_STATUS__tim_status__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIM_PRESC_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIM_PRESC_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TIM_PRESC_STATUS(f1,v1) ( \
+ (R_TIM_PRESC_STATUS__tim_status__##f1##__VAL(R_TIM_PRESC_STATUS_, tim_status_, v1) << R_TIM_PRESC_STATUS__tim_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TIM_PRESC_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TIM_PRESC_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TIM_PRESC_STATUS_(f1_,v1) ( \
+ (R_TIM_PRESC_STATUS__tim_status__##f1_##_VAL(R_TIM_PRESC_STATUS_, tim_status_, v1) << R_TIM_PRESC_STATUS__tim_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TLB_HI
+ * - type: RW
+ * - addr: 0xb000025c
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TLB_HI
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TLB_HI.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_TLB_HI.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TLB_HI(f1,v1,f2,v2) ( \
+ R_TLB_HI__WRITE(R_TLB_HI__ADDR, ( \
+ REG_VAL__R_TLB_HI_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TLB_HI
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TLB_HI(f1,v1,f2,v2) ( \
+ (R_TLB_HI__vpn__##f1##__MASK & REG__##v1) | \
+ (R_TLB_HI__page_id__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TLB_HI
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TLB_HI.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TLB_HI(f1,v1,f2,v2) ( \
+ (R_TLB_HI__vpn__##f1##__VAL(R_TLB_HI_, vpn_, v1) << R_TLB_HI__vpn__BITNR) | \
+ (R_TLB_HI__page_id__##f2##__VAL(R_TLB_HI_, page_id_, v2) << R_TLB_HI__page_id__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TLB_HI_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TLB_HI.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TLB_HI_(f1_,v1,f2_,v2) ( \
+ (R_TLB_HI__vpn__##f1_##_VAL(R_TLB_HI_, vpn_, v1) << R_TLB_HI__vpn__BITNR) | \
+ (R_TLB_HI__page_id__##f2_##_VAL(R_TLB_HI_, page_id_, v2) << R_TLB_HI__page_id__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TLB_LO
+ * - type: RW
+ * - addr: 0xb0000258
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TLB_LO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TLB_LO.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_TLB_LO.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TLB_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ R_TLB_LO__WRITE(R_TLB_LO__ADDR, ( \
+ REG_VAL__R_TLB_LO_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TLB_LO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TLB_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_TLB_LO__pfn__##f1##__MASK & REG__##v1) | \
+ (R_TLB_LO__global__##f2##__MASK & REG__##v2) | \
+ (R_TLB_LO__valid__##f3##__MASK & REG__##v3) | \
+ (R_TLB_LO__kernel__##f4##__MASK & REG__##v4) | \
+ (R_TLB_LO__we__##f5##__MASK & REG__##v5) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TLB_LO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TLB_LO.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TLB_LO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_TLB_LO__pfn__##f1##__VAL(R_TLB_LO_, pfn_, v1) << R_TLB_LO__pfn__BITNR) | \
+ (R_TLB_LO__global__##f2##__VAL(R_TLB_LO_, global_, v2) << R_TLB_LO__global__BITNR) | \
+ (R_TLB_LO__valid__##f3##__VAL(R_TLB_LO_, valid_, v3) << R_TLB_LO__valid__BITNR) | \
+ (R_TLB_LO__kernel__##f4##__VAL(R_TLB_LO_, kernel_, v4) << R_TLB_LO__kernel__BITNR) | \
+ (R_TLB_LO__we__##f5##__VAL(R_TLB_LO_, we_, v5) << R_TLB_LO__we__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TLB_LO_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TLB_LO.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TLB_LO_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \
+ (R_TLB_LO__pfn__##f1_##_VAL(R_TLB_LO_, pfn_, v1) << R_TLB_LO__pfn__BITNR) | \
+ (R_TLB_LO__global__##f2_##_VAL(R_TLB_LO_, global_, v2) << R_TLB_LO__global__BITNR) | \
+ (R_TLB_LO__valid__##f3_##_VAL(R_TLB_LO_, valid_, v3) << R_TLB_LO__valid__BITNR) | \
+ (R_TLB_LO__kernel__##f4_##_VAL(R_TLB_LO_, kernel_, v4) << R_TLB_LO__kernel__BITNR) | \
+ (R_TLB_LO__we__##f5_##_VAL(R_TLB_LO_, we_, v5) << R_TLB_LO__we__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TLB_SELECT
+ * - type: RW
+ * - addr: 0xb0000254
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_TLB_SELECT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_TLB_SELECT.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_TLB_SELECT.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_TLB_SELECT(f1,v1) ( \
+ R_TLB_SELECT__WRITE(R_TLB_SELECT__ADDR, ( \
+ REG_VAL__R_TLB_SELECT_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TLB_SELECT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TLB_SELECT(f1,v1) ( \
+ (R_TLB_SELECT__index__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TLB_SELECT
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TLB_SELECT.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TLB_SELECT(f1,v1) ( \
+ (R_TLB_SELECT__index__##f1##__VAL(R_TLB_SELECT_, index_, v1) << R_TLB_SELECT__index__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TLB_SELECT_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TLB_SELECT.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TLB_SELECT_(f1_,v1) ( \
+ (R_TLB_SELECT__index__##f1_##_VAL(R_TLB_SELECT_, index_, v1) << R_TLB_SELECT__index__BITNR) \
+)
+
+#endif
+
+/*
+ * R_TR_COUNTERS
+ * - type: RO
+ * - addr: 0xb00000a8
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_TR_COUNTERS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_TR_COUNTERS(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_TR_COUNTERS__deferred__##f1##__MASK & REG__##v1) | \
+ (R_TR_COUNTERS__late_col__##f2##__MASK & REG__##v2) | \
+ (R_TR_COUNTERS__multiple_col__##f3##__MASK & REG__##v3) | \
+ (R_TR_COUNTERS__single_col__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TR_COUNTERS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TR_COUNTERS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_TR_COUNTERS(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_TR_COUNTERS__deferred__##f1##__VAL(R_TR_COUNTERS_, deferred_, v1) << R_TR_COUNTERS__deferred__BITNR) | \
+ (R_TR_COUNTERS__late_col__##f2##__VAL(R_TR_COUNTERS_, late_col_, v2) << R_TR_COUNTERS__late_col__BITNR) | \
+ (R_TR_COUNTERS__multiple_col__##f3##__VAL(R_TR_COUNTERS_, multiple_col_, v3) << R_TR_COUNTERS__multiple_col__BITNR) | \
+ (R_TR_COUNTERS__single_col__##f4##__VAL(R_TR_COUNTERS_, single_col_, v4) << R_TR_COUNTERS__single_col__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_TR_COUNTERS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_TR_COUNTERS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_TR_COUNTERS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_TR_COUNTERS__deferred__##f1_##_VAL(R_TR_COUNTERS_, deferred_, v1) << R_TR_COUNTERS__deferred__BITNR) | \
+ (R_TR_COUNTERS__late_col__##f2_##_VAL(R_TR_COUNTERS_, late_col_, v2) << R_TR_COUNTERS__late_col__BITNR) | \
+ (R_TR_COUNTERS__multiple_col__##f3_##_VAL(R_TR_COUNTERS_, multiple_col_, v3) << R_TR_COUNTERS__multiple_col__BITNR) | \
+ (R_TR_COUNTERS__single_col__##f4_##_VAL(R_TR_COUNTERS_, single_col_, v4) << R_TR_COUNTERS__single_col__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_COMMAND
+ * - type: RW
+ * - addr: 0xb0000201
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_COMMAND
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_COMMAND.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_COMMAND.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_COMMAND(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ R_USB_COMMAND__WRITE(R_USB_COMMAND__ADDR, ( \
+ REG_VAL__R_USB_COMMAND_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_COMMAND
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_COMMAND(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_USB_COMMAND__port_sel__##f1##__MASK & REG__##v1) | \
+ (R_USB_COMMAND__port_cmd__##f2##__MASK & REG__##v2) | \
+ (R_USB_COMMAND__busy__##f3##__MASK & REG__##v3) | \
+ (R_USB_COMMAND__ctrl_cmd__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_COMMAND
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_COMMAND.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_COMMAND(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_USB_COMMAND__port_sel__##f1##__VAL(R_USB_COMMAND_, port_sel_, v1) << R_USB_COMMAND__port_sel__BITNR) | \
+ (R_USB_COMMAND__port_cmd__##f2##__VAL(R_USB_COMMAND_, port_cmd_, v2) << R_USB_COMMAND__port_cmd__BITNR) | \
+ (R_USB_COMMAND__busy__##f3##__VAL(R_USB_COMMAND_, busy_, v3) << R_USB_COMMAND__busy__BITNR) | \
+ (R_USB_COMMAND__ctrl_cmd__##f4##__VAL(R_USB_COMMAND_, ctrl_cmd_, v4) << R_USB_COMMAND__ctrl_cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_COMMAND_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_COMMAND.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_COMMAND_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_USB_COMMAND__port_sel__##f1_##_VAL(R_USB_COMMAND_, port_sel_, v1) << R_USB_COMMAND__port_sel__BITNR) | \
+ (R_USB_COMMAND__port_cmd__##f2_##_VAL(R_USB_COMMAND_, port_cmd_, v2) << R_USB_COMMAND__port_cmd__BITNR) | \
+ (R_USB_COMMAND__busy__##f3_##_VAL(R_USB_COMMAND_, busy_, v3) << R_USB_COMMAND__busy__BITNR) | \
+ (R_USB_COMMAND__ctrl_cmd__##f4_##_VAL(R_USB_COMMAND_, ctrl_cmd_, v4) << R_USB_COMMAND__ctrl_cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_COMMAND_DEV
+ * - type: RW
+ * - addr: 0xb0000201
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_COMMAND_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_COMMAND_DEV.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_COMMAND_DEV.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_COMMAND_DEV(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ R_USB_COMMAND_DEV__WRITE(R_USB_COMMAND_DEV__ADDR, ( \
+ REG_VAL__R_USB_COMMAND_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_COMMAND_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_COMMAND_DEV(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_USB_COMMAND_DEV__port_sel__##f1##__MASK & REG__##v1) | \
+ (R_USB_COMMAND_DEV__port_cmd__##f2##__MASK & REG__##v2) | \
+ (R_USB_COMMAND_DEV__busy__##f3##__MASK & REG__##v3) | \
+ (R_USB_COMMAND_DEV__ctrl_cmd__##f4##__MASK & REG__##v4) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_COMMAND_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_COMMAND_DEV.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_COMMAND_DEV(f1,v1,f2,v2,f3,v3,f4,v4) ( \
+ (R_USB_COMMAND_DEV__port_sel__##f1##__VAL(R_USB_COMMAND_DEV_, port_sel_, v1) << R_USB_COMMAND_DEV__port_sel__BITNR) | \
+ (R_USB_COMMAND_DEV__port_cmd__##f2##__VAL(R_USB_COMMAND_DEV_, port_cmd_, v2) << R_USB_COMMAND_DEV__port_cmd__BITNR) | \
+ (R_USB_COMMAND_DEV__busy__##f3##__VAL(R_USB_COMMAND_DEV_, busy_, v3) << R_USB_COMMAND_DEV__busy__BITNR) | \
+ (R_USB_COMMAND_DEV__ctrl_cmd__##f4##__VAL(R_USB_COMMAND_DEV_, ctrl_cmd_, v4) << R_USB_COMMAND_DEV__ctrl_cmd__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_COMMAND_DEV_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_COMMAND_DEV.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_COMMAND_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4) ( \
+ (R_USB_COMMAND_DEV__port_sel__##f1_##_VAL(R_USB_COMMAND_DEV_, port_sel_, v1) << R_USB_COMMAND_DEV__port_sel__BITNR) | \
+ (R_USB_COMMAND_DEV__port_cmd__##f2_##_VAL(R_USB_COMMAND_DEV_, port_cmd_, v2) << R_USB_COMMAND_DEV__port_cmd__BITNR) | \
+ (R_USB_COMMAND_DEV__busy__##f3_##_VAL(R_USB_COMMAND_DEV_, busy_, v3) << R_USB_COMMAND_DEV__busy__BITNR) | \
+ (R_USB_COMMAND_DEV__ctrl_cmd__##f4_##_VAL(R_USB_COMMAND_DEV_, ctrl_cmd_, v4) << R_USB_COMMAND_DEV__ctrl_cmd__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_EPID_ATTN
+ * - type: RO
+ * - addr: 0xb0000224
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_EPID_ATTN
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_EPID_ATTN(f1,v1) ( \
+ (R_USB_EPID_ATTN__value__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPID_ATTN
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPID_ATTN.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPID_ATTN(f1,v1) ( \
+ (R_USB_EPID_ATTN__value__##f1##__VAL(R_USB_EPID_ATTN_, value_, v1) << R_USB_EPID_ATTN__value__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPID_ATTN_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPID_ATTN.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPID_ATTN_(f1_,v1) ( \
+ (R_USB_EPID_ATTN__value__##f1_##_VAL(R_USB_EPID_ATTN_, value_, v1) << R_USB_EPID_ATTN__value__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_EPT_DATA
+ * - type: RW
+ * - addr: 0xb000021c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_EPT_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_EPT_DATA.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_EPT_DATA.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_EPT_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ R_USB_EPT_DATA__WRITE(R_USB_EPT_DATA__ADDR, ( \
+ REG_VAL__R_USB_EPT_DATA_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_EPT_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_EPT_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_USB_EPT_DATA__valid__##f1##__MASK & REG__##v1) | \
+ (R_USB_EPT_DATA__hold__##f2##__MASK & REG__##v2) | \
+ (R_USB_EPT_DATA__error_count_in__##f3##__MASK & REG__##v3) | \
+ (R_USB_EPT_DATA__t_in__##f4##__MASK & REG__##v4) | \
+ (R_USB_EPT_DATA__low_speed__##f5##__MASK & REG__##v5) | \
+ (R_USB_EPT_DATA__port__##f6##__MASK & REG__##v6) | \
+ (R_USB_EPT_DATA__error_code__##f7##__MASK & REG__##v7) | \
+ (R_USB_EPT_DATA__t_out__##f8##__MASK & REG__##v8) | \
+ (R_USB_EPT_DATA__error_count_out__##f9##__MASK & REG__##v9) | \
+ (R_USB_EPT_DATA__max_len__##f10##__MASK & REG__##v10) | \
+ (R_USB_EPT_DATA__ep__##f11##__MASK & REG__##v11) | \
+ (R_USB_EPT_DATA__dev__##f12##__MASK & REG__##v12) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPT_DATA
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPT_DATA.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPT_DATA(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_USB_EPT_DATA__valid__##f1##__VAL(R_USB_EPT_DATA_, valid_, v1) << R_USB_EPT_DATA__valid__BITNR) | \
+ (R_USB_EPT_DATA__hold__##f2##__VAL(R_USB_EPT_DATA_, hold_, v2) << R_USB_EPT_DATA__hold__BITNR) | \
+ (R_USB_EPT_DATA__error_count_in__##f3##__VAL(R_USB_EPT_DATA_, error_count_in_, v3) << R_USB_EPT_DATA__error_count_in__BITNR) | \
+ (R_USB_EPT_DATA__t_in__##f4##__VAL(R_USB_EPT_DATA_, t_in_, v4) << R_USB_EPT_DATA__t_in__BITNR) | \
+ (R_USB_EPT_DATA__low_speed__##f5##__VAL(R_USB_EPT_DATA_, low_speed_, v5) << R_USB_EPT_DATA__low_speed__BITNR) | \
+ (R_USB_EPT_DATA__port__##f6##__VAL(R_USB_EPT_DATA_, port_, v6) << R_USB_EPT_DATA__port__BITNR) | \
+ (R_USB_EPT_DATA__error_code__##f7##__VAL(R_USB_EPT_DATA_, error_code_, v7) << R_USB_EPT_DATA__error_code__BITNR) | \
+ (R_USB_EPT_DATA__t_out__##f8##__VAL(R_USB_EPT_DATA_, t_out_, v8) << R_USB_EPT_DATA__t_out__BITNR) | \
+ (R_USB_EPT_DATA__error_count_out__##f9##__VAL(R_USB_EPT_DATA_, error_count_out_, v9) << R_USB_EPT_DATA__error_count_out__BITNR) | \
+ (R_USB_EPT_DATA__max_len__##f10##__VAL(R_USB_EPT_DATA_, max_len_, v10) << R_USB_EPT_DATA__max_len__BITNR) | \
+ (R_USB_EPT_DATA__ep__##f11##__VAL(R_USB_EPT_DATA_, ep_, v11) << R_USB_EPT_DATA__ep__BITNR) | \
+ (R_USB_EPT_DATA__dev__##f12##__VAL(R_USB_EPT_DATA_, dev_, v12) << R_USB_EPT_DATA__dev__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPT_DATA.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPT_DATA_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \
+ (R_USB_EPT_DATA__valid__##f1_##_VAL(R_USB_EPT_DATA_, valid_, v1) << R_USB_EPT_DATA__valid__BITNR) | \
+ (R_USB_EPT_DATA__hold__##f2_##_VAL(R_USB_EPT_DATA_, hold_, v2) << R_USB_EPT_DATA__hold__BITNR) | \
+ (R_USB_EPT_DATA__error_count_in__##f3_##_VAL(R_USB_EPT_DATA_, error_count_in_, v3) << R_USB_EPT_DATA__error_count_in__BITNR) | \
+ (R_USB_EPT_DATA__t_in__##f4_##_VAL(R_USB_EPT_DATA_, t_in_, v4) << R_USB_EPT_DATA__t_in__BITNR) | \
+ (R_USB_EPT_DATA__low_speed__##f5_##_VAL(R_USB_EPT_DATA_, low_speed_, v5) << R_USB_EPT_DATA__low_speed__BITNR) | \
+ (R_USB_EPT_DATA__port__##f6_##_VAL(R_USB_EPT_DATA_, port_, v6) << R_USB_EPT_DATA__port__BITNR) | \
+ (R_USB_EPT_DATA__error_code__##f7_##_VAL(R_USB_EPT_DATA_, error_code_, v7) << R_USB_EPT_DATA__error_code__BITNR) | \
+ (R_USB_EPT_DATA__t_out__##f8_##_VAL(R_USB_EPT_DATA_, t_out_, v8) << R_USB_EPT_DATA__t_out__BITNR) | \
+ (R_USB_EPT_DATA__error_count_out__##f9_##_VAL(R_USB_EPT_DATA_, error_count_out_, v9) << R_USB_EPT_DATA__error_count_out__BITNR) | \
+ (R_USB_EPT_DATA__max_len__##f10_##_VAL(R_USB_EPT_DATA_, max_len_, v10) << R_USB_EPT_DATA__max_len__BITNR) | \
+ (R_USB_EPT_DATA__ep__##f11_##_VAL(R_USB_EPT_DATA_, ep_, v11) << R_USB_EPT_DATA__ep__BITNR) | \
+ (R_USB_EPT_DATA__dev__##f12_##_VAL(R_USB_EPT_DATA_, dev_, v12) << R_USB_EPT_DATA__dev__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_EPT_DATA_DEV
+ * - type: RW
+ * - addr: 0xb000021c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_EPT_DATA_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_EPT_DATA_DEV.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_EPT_DATA_DEV.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_EPT_DATA_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ R_USB_EPT_DATA_DEV__WRITE(R_USB_EPT_DATA_DEV__ADDR, ( \
+ REG_VAL__R_USB_EPT_DATA_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_EPT_DATA_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_EPT_DATA_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_USB_EPT_DATA_DEV__valid__##f1##__MASK & REG__##v1) | \
+ (R_USB_EPT_DATA_DEV__hold__##f2##__MASK & REG__##v2) | \
+ (R_USB_EPT_DATA_DEV__stall__##f3##__MASK & REG__##v3) | \
+ (R_USB_EPT_DATA_DEV__iso_resp__##f4##__MASK & REG__##v4) | \
+ (R_USB_EPT_DATA_DEV__ctrl__##f5##__MASK & REG__##v5) | \
+ (R_USB_EPT_DATA_DEV__iso__##f6##__MASK & REG__##v6) | \
+ (R_USB_EPT_DATA_DEV__port__##f7##__MASK & REG__##v7) | \
+ (R_USB_EPT_DATA_DEV__control_phase__##f8##__MASK & REG__##v8) | \
+ (R_USB_EPT_DATA_DEV__t__##f9##__MASK & REG__##v9) | \
+ (R_USB_EPT_DATA_DEV__max_len__##f10##__MASK & REG__##v10) | \
+ (R_USB_EPT_DATA_DEV__ep__##f11##__MASK & REG__##v11) | \
+ (R_USB_EPT_DATA_DEV__dev__##f12##__MASK & REG__##v12) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPT_DATA_DEV.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPT_DATA_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_USB_EPT_DATA_DEV__valid__##f1##__VAL(R_USB_EPT_DATA_DEV_, valid_, v1) << R_USB_EPT_DATA_DEV__valid__BITNR) | \
+ (R_USB_EPT_DATA_DEV__hold__##f2##__VAL(R_USB_EPT_DATA_DEV_, hold_, v2) << R_USB_EPT_DATA_DEV__hold__BITNR) | \
+ (R_USB_EPT_DATA_DEV__stall__##f3##__VAL(R_USB_EPT_DATA_DEV_, stall_, v3) << R_USB_EPT_DATA_DEV__stall__BITNR) | \
+ (R_USB_EPT_DATA_DEV__iso_resp__##f4##__VAL(R_USB_EPT_DATA_DEV_, iso_resp_, v4) << R_USB_EPT_DATA_DEV__iso_resp__BITNR) | \
+ (R_USB_EPT_DATA_DEV__ctrl__##f5##__VAL(R_USB_EPT_DATA_DEV_, ctrl_, v5) << R_USB_EPT_DATA_DEV__ctrl__BITNR) | \
+ (R_USB_EPT_DATA_DEV__iso__##f6##__VAL(R_USB_EPT_DATA_DEV_, iso_, v6) << R_USB_EPT_DATA_DEV__iso__BITNR) | \
+ (R_USB_EPT_DATA_DEV__port__##f7##__VAL(R_USB_EPT_DATA_DEV_, port_, v7) << R_USB_EPT_DATA_DEV__port__BITNR) | \
+ (R_USB_EPT_DATA_DEV__control_phase__##f8##__VAL(R_USB_EPT_DATA_DEV_, control_phase_, v8) << R_USB_EPT_DATA_DEV__control_phase__BITNR) | \
+ (R_USB_EPT_DATA_DEV__t__##f9##__VAL(R_USB_EPT_DATA_DEV_, t_, v9) << R_USB_EPT_DATA_DEV__t__BITNR) | \
+ (R_USB_EPT_DATA_DEV__max_len__##f10##__VAL(R_USB_EPT_DATA_DEV_, max_len_, v10) << R_USB_EPT_DATA_DEV__max_len__BITNR) | \
+ (R_USB_EPT_DATA_DEV__ep__##f11##__VAL(R_USB_EPT_DATA_DEV_, ep_, v11) << R_USB_EPT_DATA_DEV__ep__BITNR) | \
+ (R_USB_EPT_DATA_DEV__dev__##f12##__VAL(R_USB_EPT_DATA_DEV_, dev_, v12) << R_USB_EPT_DATA_DEV__dev__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_DEV_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPT_DATA_DEV.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPT_DATA_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \
+ (R_USB_EPT_DATA_DEV__valid__##f1_##_VAL(R_USB_EPT_DATA_DEV_, valid_, v1) << R_USB_EPT_DATA_DEV__valid__BITNR) | \
+ (R_USB_EPT_DATA_DEV__hold__##f2_##_VAL(R_USB_EPT_DATA_DEV_, hold_, v2) << R_USB_EPT_DATA_DEV__hold__BITNR) | \
+ (R_USB_EPT_DATA_DEV__stall__##f3_##_VAL(R_USB_EPT_DATA_DEV_, stall_, v3) << R_USB_EPT_DATA_DEV__stall__BITNR) | \
+ (R_USB_EPT_DATA_DEV__iso_resp__##f4_##_VAL(R_USB_EPT_DATA_DEV_, iso_resp_, v4) << R_USB_EPT_DATA_DEV__iso_resp__BITNR) | \
+ (R_USB_EPT_DATA_DEV__ctrl__##f5_##_VAL(R_USB_EPT_DATA_DEV_, ctrl_, v5) << R_USB_EPT_DATA_DEV__ctrl__BITNR) | \
+ (R_USB_EPT_DATA_DEV__iso__##f6_##_VAL(R_USB_EPT_DATA_DEV_, iso_, v6) << R_USB_EPT_DATA_DEV__iso__BITNR) | \
+ (R_USB_EPT_DATA_DEV__port__##f7_##_VAL(R_USB_EPT_DATA_DEV_, port_, v7) << R_USB_EPT_DATA_DEV__port__BITNR) | \
+ (R_USB_EPT_DATA_DEV__control_phase__##f8_##_VAL(R_USB_EPT_DATA_DEV_, control_phase_, v8) << R_USB_EPT_DATA_DEV__control_phase__BITNR) | \
+ (R_USB_EPT_DATA_DEV__t__##f9_##_VAL(R_USB_EPT_DATA_DEV_, t_, v9) << R_USB_EPT_DATA_DEV__t__BITNR) | \
+ (R_USB_EPT_DATA_DEV__max_len__##f10_##_VAL(R_USB_EPT_DATA_DEV_, max_len_, v10) << R_USB_EPT_DATA_DEV__max_len__BITNR) | \
+ (R_USB_EPT_DATA_DEV__ep__##f11_##_VAL(R_USB_EPT_DATA_DEV_, ep_, v11) << R_USB_EPT_DATA_DEV__ep__BITNR) | \
+ (R_USB_EPT_DATA_DEV__dev__##f12_##_VAL(R_USB_EPT_DATA_DEV_, dev_, v12) << R_USB_EPT_DATA_DEV__dev__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_EPT_DATA_ISO
+ * - type: RW
+ * - addr: 0xb000021c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_EPT_DATA_ISO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_EPT_DATA_ISO.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_EPT_DATA_ISO.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_EPT_DATA_ISO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ R_USB_EPT_DATA_ISO__WRITE(R_USB_EPT_DATA_ISO__ADDR, ( \
+ REG_VAL__R_USB_EPT_DATA_ISO_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_EPT_DATA_ISO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_EPT_DATA_ISO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_USB_EPT_DATA_ISO__valid__##f1##__MASK & REG__##v1) | \
+ (R_USB_EPT_DATA_ISO__port__##f2##__MASK & REG__##v2) | \
+ (R_USB_EPT_DATA_ISO__error_code__##f3##__MASK & REG__##v3) | \
+ (R_USB_EPT_DATA_ISO__max_len__##f4##__MASK & REG__##v4) | \
+ (R_USB_EPT_DATA_ISO__ep__##f5##__MASK & REG__##v5) | \
+ (R_USB_EPT_DATA_ISO__dev__##f6##__MASK & REG__##v6) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_ISO
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPT_DATA_ISO.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPT_DATA_ISO(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_USB_EPT_DATA_ISO__valid__##f1##__VAL(R_USB_EPT_DATA_ISO_, valid_, v1) << R_USB_EPT_DATA_ISO__valid__BITNR) | \
+ (R_USB_EPT_DATA_ISO__port__##f2##__VAL(R_USB_EPT_DATA_ISO_, port_, v2) << R_USB_EPT_DATA_ISO__port__BITNR) | \
+ (R_USB_EPT_DATA_ISO__error_code__##f3##__VAL(R_USB_EPT_DATA_ISO_, error_code_, v3) << R_USB_EPT_DATA_ISO__error_code__BITNR) | \
+ (R_USB_EPT_DATA_ISO__max_len__##f4##__VAL(R_USB_EPT_DATA_ISO_, max_len_, v4) << R_USB_EPT_DATA_ISO__max_len__BITNR) | \
+ (R_USB_EPT_DATA_ISO__ep__##f5##__VAL(R_USB_EPT_DATA_ISO_, ep_, v5) << R_USB_EPT_DATA_ISO__ep__BITNR) | \
+ (R_USB_EPT_DATA_ISO__dev__##f6##__VAL(R_USB_EPT_DATA_ISO_, dev_, v6) << R_USB_EPT_DATA_ISO__dev__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPT_DATA_ISO_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPT_DATA_ISO.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPT_DATA_ISO_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \
+ (R_USB_EPT_DATA_ISO__valid__##f1_##_VAL(R_USB_EPT_DATA_ISO_, valid_, v1) << R_USB_EPT_DATA_ISO__valid__BITNR) | \
+ (R_USB_EPT_DATA_ISO__port__##f2_##_VAL(R_USB_EPT_DATA_ISO_, port_, v2) << R_USB_EPT_DATA_ISO__port__BITNR) | \
+ (R_USB_EPT_DATA_ISO__error_code__##f3_##_VAL(R_USB_EPT_DATA_ISO_, error_code_, v3) << R_USB_EPT_DATA_ISO__error_code__BITNR) | \
+ (R_USB_EPT_DATA_ISO__max_len__##f4_##_VAL(R_USB_EPT_DATA_ISO_, max_len_, v4) << R_USB_EPT_DATA_ISO__max_len__BITNR) | \
+ (R_USB_EPT_DATA_ISO__ep__##f5_##_VAL(R_USB_EPT_DATA_ISO_, ep_, v5) << R_USB_EPT_DATA_ISO__ep__BITNR) | \
+ (R_USB_EPT_DATA_ISO__dev__##f6_##_VAL(R_USB_EPT_DATA_ISO_, dev_, v6) << R_USB_EPT_DATA_ISO__dev__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_EPT_INDEX
+ * - type: RW
+ * - addr: 0xb0000208
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_EPT_INDEX
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_EPT_INDEX.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_EPT_INDEX.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_EPT_INDEX(f1,v1) ( \
+ R_USB_EPT_INDEX__WRITE(R_USB_EPT_INDEX__ADDR, ( \
+ REG_VAL__R_USB_EPT_INDEX_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_EPT_INDEX
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_EPT_INDEX(f1,v1) ( \
+ (R_USB_EPT_INDEX__value__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPT_INDEX
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPT_INDEX.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPT_INDEX(f1,v1) ( \
+ (R_USB_EPT_INDEX__value__##f1##__VAL(R_USB_EPT_INDEX_, value_, v1) << R_USB_EPT_INDEX__value__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_EPT_INDEX_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_EPT_INDEX.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_EPT_INDEX_(f1_,v1) ( \
+ (R_USB_EPT_INDEX__value__##f1_##_VAL(R_USB_EPT_INDEX_, value_, v1) << R_USB_EPT_INDEX__value__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_FM_INTERVAL
+ * - type: RW
+ * - addr: 0xb0000210
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_FM_INTERVAL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_FM_INTERVAL.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_FM_INTERVAL.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_FM_INTERVAL(f1,v1,f2,v2) ( \
+ R_USB_FM_INTERVAL__WRITE(R_USB_FM_INTERVAL__ADDR, ( \
+ REG_VAL__R_USB_FM_INTERVAL_(f1##_,v1,f2##_,v2) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_FM_INTERVAL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_FM_INTERVAL(f1,v1,f2,v2) ( \
+ (R_USB_FM_INTERVAL__fixed__##f1##__MASK & REG__##v1) | \
+ (R_USB_FM_INTERVAL__adj__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_INTERVAL
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_INTERVAL.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_INTERVAL(f1,v1,f2,v2) ( \
+ (R_USB_FM_INTERVAL__fixed__##f1##__VAL(R_USB_FM_INTERVAL_, fixed_, v1) << R_USB_FM_INTERVAL__fixed__BITNR) | \
+ (R_USB_FM_INTERVAL__adj__##f2##__VAL(R_USB_FM_INTERVAL_, adj_, v2) << R_USB_FM_INTERVAL__adj__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_INTERVAL_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_INTERVAL.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_INTERVAL_(f1_,v1,f2_,v2) ( \
+ (R_USB_FM_INTERVAL__fixed__##f1_##_VAL(R_USB_FM_INTERVAL_, fixed_, v1) << R_USB_FM_INTERVAL__fixed__BITNR) | \
+ (R_USB_FM_INTERVAL__adj__##f2_##_VAL(R_USB_FM_INTERVAL_, adj_, v2) << R_USB_FM_INTERVAL__adj__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_FM_NUMBER
+ * - type: RW
+ * - addr: 0xb000020c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_FM_NUMBER
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_FM_NUMBER.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_FM_NUMBER.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_FM_NUMBER(f1,v1) ( \
+ R_USB_FM_NUMBER__WRITE(R_USB_FM_NUMBER__ADDR, ( \
+ REG_VAL__R_USB_FM_NUMBER_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_FM_NUMBER
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_FM_NUMBER(f1,v1) ( \
+ (R_USB_FM_NUMBER__value__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_NUMBER
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_NUMBER.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_NUMBER(f1,v1) ( \
+ (R_USB_FM_NUMBER__value__##f1##__VAL(R_USB_FM_NUMBER_, value_, v1) << R_USB_FM_NUMBER__value__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_NUMBER_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_NUMBER.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_NUMBER_(f1_,v1) ( \
+ (R_USB_FM_NUMBER__value__##f1_##_VAL(R_USB_FM_NUMBER_, value_, v1) << R_USB_FM_NUMBER__value__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_FM_NUMBER_DEV
+ * - type: RW
+ * - addr: 0xb000020c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_FM_NUMBER_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_FM_NUMBER_DEV.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_FM_NUMBER_DEV.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_FM_NUMBER_DEV(f1,v1,f2,v2,f3,v3) ( \
+ R_USB_FM_NUMBER_DEV__WRITE(R_USB_FM_NUMBER_DEV__ADDR, ( \
+ REG_VAL__R_USB_FM_NUMBER_DEV_(f1##_,v1,f2##_,v2,f3##_,v3) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_FM_NUMBER_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_FM_NUMBER_DEV(f1,v1,f2,v2,f3,v3) ( \
+ (R_USB_FM_NUMBER_DEV__sign__##f1##__MASK & REG__##v1) | \
+ (R_USB_FM_NUMBER_DEV__deviation__##f2##__MASK & REG__##v2) | \
+ (R_USB_FM_NUMBER_DEV__fm_number__##f3##__MASK & REG__##v3) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_NUMBER_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_NUMBER_DEV.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_NUMBER_DEV(f1,v1,f2,v2,f3,v3) ( \
+ (R_USB_FM_NUMBER_DEV__sign__##f1##__VAL(R_USB_FM_NUMBER_DEV_, sign_, v1) << R_USB_FM_NUMBER_DEV__sign__BITNR) | \
+ (R_USB_FM_NUMBER_DEV__deviation__##f2##__VAL(R_USB_FM_NUMBER_DEV_, deviation_, v2) << R_USB_FM_NUMBER_DEV__deviation__BITNR) | \
+ (R_USB_FM_NUMBER_DEV__fm_number__##f3##__VAL(R_USB_FM_NUMBER_DEV_, fm_number_, v3) << R_USB_FM_NUMBER_DEV__fm_number__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_NUMBER_DEV_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_NUMBER_DEV.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_NUMBER_DEV_(f1_,v1,f2_,v2,f3_,v3) ( \
+ (R_USB_FM_NUMBER_DEV__sign__##f1_##_VAL(R_USB_FM_NUMBER_DEV_, sign_, v1) << R_USB_FM_NUMBER_DEV__sign__BITNR) | \
+ (R_USB_FM_NUMBER_DEV__deviation__##f2_##_VAL(R_USB_FM_NUMBER_DEV_, deviation_, v2) << R_USB_FM_NUMBER_DEV__deviation__BITNR) | \
+ (R_USB_FM_NUMBER_DEV__fm_number__##f3_##_VAL(R_USB_FM_NUMBER_DEV_, fm_number_, v3) << R_USB_FM_NUMBER_DEV__fm_number__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_FM_PSTART
+ * - type: RW
+ * - addr: 0xb0000214
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_FM_PSTART
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_FM_PSTART.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_FM_PSTART.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_FM_PSTART(f1,v1) ( \
+ R_USB_FM_PSTART__WRITE(R_USB_FM_PSTART__ADDR, ( \
+ REG_VAL__R_USB_FM_PSTART_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_FM_PSTART
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_FM_PSTART(f1,v1) ( \
+ (R_USB_FM_PSTART__value__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_PSTART
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_PSTART.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_PSTART(f1,v1) ( \
+ (R_USB_FM_PSTART__value__##f1##__VAL(R_USB_FM_PSTART_, value_, v1) << R_USB_FM_PSTART__value__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_PSTART_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_PSTART.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_PSTART_(f1_,v1) ( \
+ (R_USB_FM_PSTART__value__##f1_##_VAL(R_USB_FM_PSTART_, value_, v1) << R_USB_FM_PSTART__value__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_FM_REMAINING
+ * - type: RO
+ * - addr: 0xb0000212
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_FM_REMAINING
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_FM_REMAINING(f1,v1) ( \
+ (R_USB_FM_REMAINING__value__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_REMAINING
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_REMAINING.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_REMAINING(f1,v1) ( \
+ (R_USB_FM_REMAINING__value__##f1##__VAL(R_USB_FM_REMAINING_, value_, v1) << R_USB_FM_REMAINING__value__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_FM_REMAINING_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_FM_REMAINING.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_FM_REMAINING_(f1_,v1) ( \
+ (R_USB_FM_REMAINING__value__##f1_##_VAL(R_USB_FM_REMAINING_, value_, v1) << R_USB_FM_REMAINING__value__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_CLR
+ * - type: WO
+ * - addr: 0xb0000206
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_IRQ_MASK_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_IRQ_MASK_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_IRQ_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_USB_IRQ_MASK_CLR__SADDR = ( \
+ REG_INITIATED(R_USB_IRQ_MASK_CLR_) \
+ REG_VAL__R_USB_IRQ_MASK_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ), \
+ R_USB_IRQ_MASK_CLR__WRITE(R_USB_IRQ_MASK_CLR__ADDR, *R_USB_IRQ_MASK_CLR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_CLR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_IRQ_MASK_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_USB_IRQ_MASK_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_IRQ_MASK_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_USB_IRQ_MASK_CLR__SADDR = ( \
+ REG_INITIATED(R_USB_IRQ_MASK_CLR_) \
+ REG_VAL__R_USB_IRQ_MASK_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_IRQ_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_USB_IRQ_MASK_CLR__iso_eof__##f1##__MASK & REG__##v1) | \
+ (R_USB_IRQ_MASK_CLR__intr_eof__##f2##__MASK & REG__##v2) | \
+ (R_USB_IRQ_MASK_CLR__iso_eot__##f3##__MASK & REG__##v3) | \
+ (R_USB_IRQ_MASK_CLR__intr_eot__##f4##__MASK & REG__##v4) | \
+ (R_USB_IRQ_MASK_CLR__ctl_eot__##f5##__MASK & REG__##v5) | \
+ (R_USB_IRQ_MASK_CLR__bulk_eot__##f6##__MASK & REG__##v6) | \
+ (R_USB_IRQ_MASK_CLR__epid_attn__##f7##__MASK & REG__##v7) | \
+ (R_USB_IRQ_MASK_CLR__sof__##f8##__MASK & REG__##v8) | \
+ (R_USB_IRQ_MASK_CLR__port_status__##f9##__MASK & REG__##v9) | \
+ (R_USB_IRQ_MASK_CLR__ctl_status__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_CLR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_USB_IRQ_MASK_CLR__iso_eof__##f1##__VAL(R_USB_IRQ_MASK_CLR_, iso_eof_, v1) << R_USB_IRQ_MASK_CLR__iso_eof__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__intr_eof__##f2##__VAL(R_USB_IRQ_MASK_CLR_, intr_eof_, v2) << R_USB_IRQ_MASK_CLR__intr_eof__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__iso_eot__##f3##__VAL(R_USB_IRQ_MASK_CLR_, iso_eot_, v3) << R_USB_IRQ_MASK_CLR__iso_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__intr_eot__##f4##__VAL(R_USB_IRQ_MASK_CLR_, intr_eot_, v4) << R_USB_IRQ_MASK_CLR__intr_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__ctl_eot__##f5##__VAL(R_USB_IRQ_MASK_CLR_, ctl_eot_, v5) << R_USB_IRQ_MASK_CLR__ctl_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__bulk_eot__##f6##__VAL(R_USB_IRQ_MASK_CLR_, bulk_eot_, v6) << R_USB_IRQ_MASK_CLR__bulk_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__epid_attn__##f7##__VAL(R_USB_IRQ_MASK_CLR_, epid_attn_, v7) << R_USB_IRQ_MASK_CLR__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__sof__##f8##__VAL(R_USB_IRQ_MASK_CLR_, sof_, v8) << R_USB_IRQ_MASK_CLR__sof__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__port_status__##f9##__VAL(R_USB_IRQ_MASK_CLR_, port_status_, v9) << R_USB_IRQ_MASK_CLR__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__ctl_status__##f10##__VAL(R_USB_IRQ_MASK_CLR_, ctl_status_, v10) << R_USB_IRQ_MASK_CLR__ctl_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_CLR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_CLR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_USB_IRQ_MASK_CLR__iso_eof__##f1_##_VAL(R_USB_IRQ_MASK_CLR_, iso_eof_, v1) << R_USB_IRQ_MASK_CLR__iso_eof__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__intr_eof__##f2_##_VAL(R_USB_IRQ_MASK_CLR_, intr_eof_, v2) << R_USB_IRQ_MASK_CLR__intr_eof__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__iso_eot__##f3_##_VAL(R_USB_IRQ_MASK_CLR_, iso_eot_, v3) << R_USB_IRQ_MASK_CLR__iso_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__intr_eot__##f4_##_VAL(R_USB_IRQ_MASK_CLR_, intr_eot_, v4) << R_USB_IRQ_MASK_CLR__intr_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__ctl_eot__##f5_##_VAL(R_USB_IRQ_MASK_CLR_, ctl_eot_, v5) << R_USB_IRQ_MASK_CLR__ctl_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__bulk_eot__##f6_##_VAL(R_USB_IRQ_MASK_CLR_, bulk_eot_, v6) << R_USB_IRQ_MASK_CLR__bulk_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__epid_attn__##f7_##_VAL(R_USB_IRQ_MASK_CLR_, epid_attn_, v7) << R_USB_IRQ_MASK_CLR__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__sof__##f8_##_VAL(R_USB_IRQ_MASK_CLR_, sof_, v8) << R_USB_IRQ_MASK_CLR__sof__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__port_status__##f9_##_VAL(R_USB_IRQ_MASK_CLR_, port_status_, v9) << R_USB_IRQ_MASK_CLR__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_CLR__ctl_status__##f10_##_VAL(R_USB_IRQ_MASK_CLR_, ctl_status_, v10) << R_USB_IRQ_MASK_CLR__ctl_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_CLR_DEV
+ * - type: WO
+ * - addr: 0xb0000206
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_CLR_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_IRQ_MASK_CLR_DEV.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_IRQ_MASK_CLR_DEV.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_IRQ_MASK_CLR_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ *R_USB_IRQ_MASK_CLR_DEV__SADDR = ( \
+ REG_INITIATED(R_USB_IRQ_MASK_CLR_DEV_) \
+ REG_VAL__R_USB_IRQ_MASK_CLR_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \
+ ), \
+ R_USB_IRQ_MASK_CLR_DEV__WRITE(R_USB_IRQ_MASK_CLR_DEV__ADDR, *R_USB_IRQ_MASK_CLR_DEV__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_CLR_DEV__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_IRQ_MASK_CLR_DEV.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_USB_IRQ_MASK_CLR_DEV.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_IRQ_MASK_CLR_DEV__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ *R_USB_IRQ_MASK_CLR_DEV__SADDR = ( \
+ REG_INITIATED(R_USB_IRQ_MASK_CLR_DEV_) \
+ REG_VAL__R_USB_IRQ_MASK_CLR_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_CLR_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_IRQ_MASK_CLR_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_USB_IRQ_MASK_CLR_DEV__out_eot__##f1##__MASK & REG__##v1) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__##f2##__MASK & REG__##v2) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__##f3##__MASK & REG__##v3) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__##f4##__MASK & REG__##v4) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__##f5##__MASK & REG__##v5) | \
+ (R_USB_IRQ_MASK_CLR_DEV__epid_attn__##f6##__MASK & REG__##v6) | \
+ (R_USB_IRQ_MASK_CLR_DEV__sof__##f7##__MASK & REG__##v7) | \
+ (R_USB_IRQ_MASK_CLR_DEV__port_status__##f8##__MASK & REG__##v8) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ctl_status__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_CLR_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_CLR_DEV.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_CLR_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_USB_IRQ_MASK_CLR_DEV__out_eot__##f1##__VAL(R_USB_IRQ_MASK_CLR_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__##f2##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__##f3##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__##f4##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__##f5##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__epid_attn__##f6##__VAL(R_USB_IRQ_MASK_CLR_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__sof__##f7##__VAL(R_USB_IRQ_MASK_CLR_DEV_, sof_, v7) << R_USB_IRQ_MASK_CLR_DEV__sof__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__port_status__##f8##__VAL(R_USB_IRQ_MASK_CLR_DEV_, port_status_, v8) << R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ctl_status__##f9##__VAL(R_USB_IRQ_MASK_CLR_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_CLR_DEV_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_CLR_DEV.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_CLR_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_USB_IRQ_MASK_CLR_DEV__out_eot__##f1_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__##f2_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__##f3_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__##f4_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__##f5_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__epid_attn__##f6_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__sof__##f7_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, sof_, v7) << R_USB_IRQ_MASK_CLR_DEV__sof__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__port_status__##f8_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, port_status_, v8) << R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_CLR_DEV__ctl_status__##f9_##_VAL(R_USB_IRQ_MASK_CLR_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_READ
+ * - type: RO
+ * - addr: 0xb0000204
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_IRQ_MASK_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_USB_IRQ_MASK_READ__iso_eof__##f1##__MASK & REG__##v1) | \
+ (R_USB_IRQ_MASK_READ__intr_eof__##f2##__MASK & REG__##v2) | \
+ (R_USB_IRQ_MASK_READ__iso_eot__##f3##__MASK & REG__##v3) | \
+ (R_USB_IRQ_MASK_READ__intr_eot__##f4##__MASK & REG__##v4) | \
+ (R_USB_IRQ_MASK_READ__ctl_eot__##f5##__MASK & REG__##v5) | \
+ (R_USB_IRQ_MASK_READ__bulk_eot__##f6##__MASK & REG__##v6) | \
+ (R_USB_IRQ_MASK_READ__epid_attn__##f7##__MASK & REG__##v7) | \
+ (R_USB_IRQ_MASK_READ__sof__##f8##__MASK & REG__##v8) | \
+ (R_USB_IRQ_MASK_READ__port_status__##f9##__MASK & REG__##v9) | \
+ (R_USB_IRQ_MASK_READ__ctl_status__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_USB_IRQ_MASK_READ__iso_eof__##f1##__VAL(R_USB_IRQ_MASK_READ_, iso_eof_, v1) << R_USB_IRQ_MASK_READ__iso_eof__BITNR) | \
+ (R_USB_IRQ_MASK_READ__intr_eof__##f2##__VAL(R_USB_IRQ_MASK_READ_, intr_eof_, v2) << R_USB_IRQ_MASK_READ__intr_eof__BITNR) | \
+ (R_USB_IRQ_MASK_READ__iso_eot__##f3##__VAL(R_USB_IRQ_MASK_READ_, iso_eot_, v3) << R_USB_IRQ_MASK_READ__iso_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ__intr_eot__##f4##__VAL(R_USB_IRQ_MASK_READ_, intr_eot_, v4) << R_USB_IRQ_MASK_READ__intr_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ__ctl_eot__##f5##__VAL(R_USB_IRQ_MASK_READ_, ctl_eot_, v5) << R_USB_IRQ_MASK_READ__ctl_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ__bulk_eot__##f6##__VAL(R_USB_IRQ_MASK_READ_, bulk_eot_, v6) << R_USB_IRQ_MASK_READ__bulk_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ__epid_attn__##f7##__VAL(R_USB_IRQ_MASK_READ_, epid_attn_, v7) << R_USB_IRQ_MASK_READ__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_READ__sof__##f8##__VAL(R_USB_IRQ_MASK_READ_, sof_, v8) << R_USB_IRQ_MASK_READ__sof__BITNR) | \
+ (R_USB_IRQ_MASK_READ__port_status__##f9##__VAL(R_USB_IRQ_MASK_READ_, port_status_, v9) << R_USB_IRQ_MASK_READ__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_READ__ctl_status__##f10##__VAL(R_USB_IRQ_MASK_READ_, ctl_status_, v10) << R_USB_IRQ_MASK_READ__ctl_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_USB_IRQ_MASK_READ__iso_eof__##f1_##_VAL(R_USB_IRQ_MASK_READ_, iso_eof_, v1) << R_USB_IRQ_MASK_READ__iso_eof__BITNR) | \
+ (R_USB_IRQ_MASK_READ__intr_eof__##f2_##_VAL(R_USB_IRQ_MASK_READ_, intr_eof_, v2) << R_USB_IRQ_MASK_READ__intr_eof__BITNR) | \
+ (R_USB_IRQ_MASK_READ__iso_eot__##f3_##_VAL(R_USB_IRQ_MASK_READ_, iso_eot_, v3) << R_USB_IRQ_MASK_READ__iso_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ__intr_eot__##f4_##_VAL(R_USB_IRQ_MASK_READ_, intr_eot_, v4) << R_USB_IRQ_MASK_READ__intr_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ__ctl_eot__##f5_##_VAL(R_USB_IRQ_MASK_READ_, ctl_eot_, v5) << R_USB_IRQ_MASK_READ__ctl_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ__bulk_eot__##f6_##_VAL(R_USB_IRQ_MASK_READ_, bulk_eot_, v6) << R_USB_IRQ_MASK_READ__bulk_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ__epid_attn__##f7_##_VAL(R_USB_IRQ_MASK_READ_, epid_attn_, v7) << R_USB_IRQ_MASK_READ__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_READ__sof__##f8_##_VAL(R_USB_IRQ_MASK_READ_, sof_, v8) << R_USB_IRQ_MASK_READ__sof__BITNR) | \
+ (R_USB_IRQ_MASK_READ__port_status__##f9_##_VAL(R_USB_IRQ_MASK_READ_, port_status_, v9) << R_USB_IRQ_MASK_READ__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_READ__ctl_status__##f10_##_VAL(R_USB_IRQ_MASK_READ_, ctl_status_, v10) << R_USB_IRQ_MASK_READ__ctl_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_READ_DEV
+ * - type: RO
+ * - addr: 0xb0000204
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_READ_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_IRQ_MASK_READ_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_USB_IRQ_MASK_READ_DEV__out_eot__##f1##__MASK & REG__##v1) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__##f2##__MASK & REG__##v2) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__##f3##__MASK & REG__##v3) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__##f4##__MASK & REG__##v4) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__##f5##__MASK & REG__##v5) | \
+ (R_USB_IRQ_MASK_READ_DEV__epid_attn__##f6##__MASK & REG__##v6) | \
+ (R_USB_IRQ_MASK_READ_DEV__sof__##f7##__MASK & REG__##v7) | \
+ (R_USB_IRQ_MASK_READ_DEV__port_status__##f8##__MASK & REG__##v8) | \
+ (R_USB_IRQ_MASK_READ_DEV__ctl_status__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_READ_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_READ_DEV.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_READ_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_USB_IRQ_MASK_READ_DEV__out_eot__##f1##__VAL(R_USB_IRQ_MASK_READ_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__##f2##__VAL(R_USB_IRQ_MASK_READ_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__##f3##__VAL(R_USB_IRQ_MASK_READ_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__##f4##__VAL(R_USB_IRQ_MASK_READ_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__##f5##__VAL(R_USB_IRQ_MASK_READ_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__epid_attn__##f6##__VAL(R_USB_IRQ_MASK_READ_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__sof__##f7##__VAL(R_USB_IRQ_MASK_READ_DEV_, sof_, v7) << R_USB_IRQ_MASK_READ_DEV__sof__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__port_status__##f8##__VAL(R_USB_IRQ_MASK_READ_DEV_, port_status_, v8) << R_USB_IRQ_MASK_READ_DEV__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ctl_status__##f9##__VAL(R_USB_IRQ_MASK_READ_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_READ_DEV_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_READ_DEV.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_READ_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_USB_IRQ_MASK_READ_DEV__out_eot__##f1_##_VAL(R_USB_IRQ_MASK_READ_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__##f2_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__##f3_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__##f4_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__##f5_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__epid_attn__##f6_##_VAL(R_USB_IRQ_MASK_READ_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__sof__##f7_##_VAL(R_USB_IRQ_MASK_READ_DEV_, sof_, v7) << R_USB_IRQ_MASK_READ_DEV__sof__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__port_status__##f8_##_VAL(R_USB_IRQ_MASK_READ_DEV_, port_status_, v8) << R_USB_IRQ_MASK_READ_DEV__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_READ_DEV__ctl_status__##f9_##_VAL(R_USB_IRQ_MASK_READ_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_SET
+ * - type: WO
+ * - addr: 0xb0000204
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_IRQ_MASK_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_IRQ_MASK_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_IRQ_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_USB_IRQ_MASK_SET__SADDR = ( \
+ REG_INITIATED(R_USB_IRQ_MASK_SET_) \
+ REG_VAL__R_USB_IRQ_MASK_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ), \
+ R_USB_IRQ_MASK_SET__WRITE(R_USB_IRQ_MASK_SET__ADDR, *R_USB_IRQ_MASK_SET__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_SET__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_IRQ_MASK_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_USB_IRQ_MASK_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_IRQ_MASK_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ *R_USB_IRQ_MASK_SET__SADDR = ( \
+ REG_INITIATED(R_USB_IRQ_MASK_SET_) \
+ REG_VAL__R_USB_IRQ_MASK_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_IRQ_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_USB_IRQ_MASK_SET__iso_eof__##f1##__MASK & REG__##v1) | \
+ (R_USB_IRQ_MASK_SET__intr_eof__##f2##__MASK & REG__##v2) | \
+ (R_USB_IRQ_MASK_SET__iso_eot__##f3##__MASK & REG__##v3) | \
+ (R_USB_IRQ_MASK_SET__intr_eot__##f4##__MASK & REG__##v4) | \
+ (R_USB_IRQ_MASK_SET__ctl_eot__##f5##__MASK & REG__##v5) | \
+ (R_USB_IRQ_MASK_SET__bulk_eot__##f6##__MASK & REG__##v6) | \
+ (R_USB_IRQ_MASK_SET__epid_attn__##f7##__MASK & REG__##v7) | \
+ (R_USB_IRQ_MASK_SET__sof__##f8##__MASK & REG__##v8) | \
+ (R_USB_IRQ_MASK_SET__port_status__##f9##__MASK & REG__##v9) | \
+ (R_USB_IRQ_MASK_SET__ctl_status__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_SET.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_USB_IRQ_MASK_SET__iso_eof__##f1##__VAL(R_USB_IRQ_MASK_SET_, iso_eof_, v1) << R_USB_IRQ_MASK_SET__iso_eof__BITNR) | \
+ (R_USB_IRQ_MASK_SET__intr_eof__##f2##__VAL(R_USB_IRQ_MASK_SET_, intr_eof_, v2) << R_USB_IRQ_MASK_SET__intr_eof__BITNR) | \
+ (R_USB_IRQ_MASK_SET__iso_eot__##f3##__VAL(R_USB_IRQ_MASK_SET_, iso_eot_, v3) << R_USB_IRQ_MASK_SET__iso_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET__intr_eot__##f4##__VAL(R_USB_IRQ_MASK_SET_, intr_eot_, v4) << R_USB_IRQ_MASK_SET__intr_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET__ctl_eot__##f5##__VAL(R_USB_IRQ_MASK_SET_, ctl_eot_, v5) << R_USB_IRQ_MASK_SET__ctl_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET__bulk_eot__##f6##__VAL(R_USB_IRQ_MASK_SET_, bulk_eot_, v6) << R_USB_IRQ_MASK_SET__bulk_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET__epid_attn__##f7##__VAL(R_USB_IRQ_MASK_SET_, epid_attn_, v7) << R_USB_IRQ_MASK_SET__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_SET__sof__##f8##__VAL(R_USB_IRQ_MASK_SET_, sof_, v8) << R_USB_IRQ_MASK_SET__sof__BITNR) | \
+ (R_USB_IRQ_MASK_SET__port_status__##f9##__VAL(R_USB_IRQ_MASK_SET_, port_status_, v9) << R_USB_IRQ_MASK_SET__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_SET__ctl_status__##f10##__VAL(R_USB_IRQ_MASK_SET_, ctl_status_, v10) << R_USB_IRQ_MASK_SET__ctl_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_SET_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_SET.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_USB_IRQ_MASK_SET__iso_eof__##f1_##_VAL(R_USB_IRQ_MASK_SET_, iso_eof_, v1) << R_USB_IRQ_MASK_SET__iso_eof__BITNR) | \
+ (R_USB_IRQ_MASK_SET__intr_eof__##f2_##_VAL(R_USB_IRQ_MASK_SET_, intr_eof_, v2) << R_USB_IRQ_MASK_SET__intr_eof__BITNR) | \
+ (R_USB_IRQ_MASK_SET__iso_eot__##f3_##_VAL(R_USB_IRQ_MASK_SET_, iso_eot_, v3) << R_USB_IRQ_MASK_SET__iso_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET__intr_eot__##f4_##_VAL(R_USB_IRQ_MASK_SET_, intr_eot_, v4) << R_USB_IRQ_MASK_SET__intr_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET__ctl_eot__##f5_##_VAL(R_USB_IRQ_MASK_SET_, ctl_eot_, v5) << R_USB_IRQ_MASK_SET__ctl_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET__bulk_eot__##f6_##_VAL(R_USB_IRQ_MASK_SET_, bulk_eot_, v6) << R_USB_IRQ_MASK_SET__bulk_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET__epid_attn__##f7_##_VAL(R_USB_IRQ_MASK_SET_, epid_attn_, v7) << R_USB_IRQ_MASK_SET__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_SET__sof__##f8_##_VAL(R_USB_IRQ_MASK_SET_, sof_, v8) << R_USB_IRQ_MASK_SET__sof__BITNR) | \
+ (R_USB_IRQ_MASK_SET__port_status__##f9_##_VAL(R_USB_IRQ_MASK_SET_, port_status_, v9) << R_USB_IRQ_MASK_SET__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_SET__ctl_status__##f10_##_VAL(R_USB_IRQ_MASK_SET_, ctl_status_, v10) << R_USB_IRQ_MASK_SET__ctl_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_SET_DEV
+ * - type: WO
+ * - addr: 0xb0000204
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_SET_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_IRQ_MASK_SET_DEV.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_IRQ_MASK_SET_DEV.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_IRQ_MASK_SET_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ *R_USB_IRQ_MASK_SET_DEV__SADDR = ( \
+ REG_INITIATED(R_USB_IRQ_MASK_SET_DEV_) \
+ REG_VAL__R_USB_IRQ_MASK_SET_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \
+ ), \
+ R_USB_IRQ_MASK_SET_DEV__WRITE(R_USB_IRQ_MASK_SET_DEV__ADDR, *R_USB_IRQ_MASK_SET_DEV__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_IRQ_MASK_SET_DEV__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_IRQ_MASK_SET_DEV.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_USB_IRQ_MASK_SET_DEV.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_IRQ_MASK_SET_DEV__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ *R_USB_IRQ_MASK_SET_DEV__SADDR = ( \
+ REG_INITIATED(R_USB_IRQ_MASK_SET_DEV_) \
+ REG_VAL__R_USB_IRQ_MASK_SET_DEV_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_IRQ_MASK_SET_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_IRQ_MASK_SET_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_USB_IRQ_MASK_SET_DEV__out_eot__##f1##__MASK & REG__##v1) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__##f2##__MASK & REG__##v2) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__##f3##__MASK & REG__##v3) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__##f4##__MASK & REG__##v4) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__##f5##__MASK & REG__##v5) | \
+ (R_USB_IRQ_MASK_SET_DEV__epid_attn__##f6##__MASK & REG__##v6) | \
+ (R_USB_IRQ_MASK_SET_DEV__sof__##f7##__MASK & REG__##v7) | \
+ (R_USB_IRQ_MASK_SET_DEV__port_status__##f8##__MASK & REG__##v8) | \
+ (R_USB_IRQ_MASK_SET_DEV__ctl_status__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_SET_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_SET_DEV.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_SET_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_USB_IRQ_MASK_SET_DEV__out_eot__##f1##__VAL(R_USB_IRQ_MASK_SET_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__##f2##__VAL(R_USB_IRQ_MASK_SET_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__##f3##__VAL(R_USB_IRQ_MASK_SET_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__##f4##__VAL(R_USB_IRQ_MASK_SET_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__##f5##__VAL(R_USB_IRQ_MASK_SET_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__epid_attn__##f6##__VAL(R_USB_IRQ_MASK_SET_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__sof__##f7##__VAL(R_USB_IRQ_MASK_SET_DEV_, sof_, v7) << R_USB_IRQ_MASK_SET_DEV__sof__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__port_status__##f8##__VAL(R_USB_IRQ_MASK_SET_DEV_, port_status_, v8) << R_USB_IRQ_MASK_SET_DEV__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ctl_status__##f9##__VAL(R_USB_IRQ_MASK_SET_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_MASK_SET_DEV_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_MASK_SET_DEV.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_MASK_SET_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_USB_IRQ_MASK_SET_DEV__out_eot__##f1_##_VAL(R_USB_IRQ_MASK_SET_DEV_, out_eot_, v1) << R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__##f2_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__##f3_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__##f4_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__##f5_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__epid_attn__##f6_##_VAL(R_USB_IRQ_MASK_SET_DEV_, epid_attn_, v6) << R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__sof__##f7_##_VAL(R_USB_IRQ_MASK_SET_DEV_, sof_, v7) << R_USB_IRQ_MASK_SET_DEV__sof__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__port_status__##f8_##_VAL(R_USB_IRQ_MASK_SET_DEV_, port_status_, v8) << R_USB_IRQ_MASK_SET_DEV__port_status__BITNR) | \
+ (R_USB_IRQ_MASK_SET_DEV__ctl_status__##f9_##_VAL(R_USB_IRQ_MASK_SET_DEV_, ctl_status_, v9) << R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_IRQ_READ
+ * - type: RO
+ * - addr: 0xb0000206
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_IRQ_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_IRQ_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_USB_IRQ_READ__iso_eof__##f1##__MASK & REG__##v1) | \
+ (R_USB_IRQ_READ__intr_eof__##f2##__MASK & REG__##v2) | \
+ (R_USB_IRQ_READ__iso_eot__##f3##__MASK & REG__##v3) | \
+ (R_USB_IRQ_READ__intr_eot__##f4##__MASK & REG__##v4) | \
+ (R_USB_IRQ_READ__ctl_eot__##f5##__MASK & REG__##v5) | \
+ (R_USB_IRQ_READ__bulk_eot__##f6##__MASK & REG__##v6) | \
+ (R_USB_IRQ_READ__epid_attn__##f7##__MASK & REG__##v7) | \
+ (R_USB_IRQ_READ__sof__##f8##__MASK & REG__##v8) | \
+ (R_USB_IRQ_READ__port_status__##f9##__MASK & REG__##v9) | \
+ (R_USB_IRQ_READ__ctl_status__##f10##__MASK & REG__##v10) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10) ( \
+ (R_USB_IRQ_READ__iso_eof__##f1##__VAL(R_USB_IRQ_READ_, iso_eof_, v1) << R_USB_IRQ_READ__iso_eof__BITNR) | \
+ (R_USB_IRQ_READ__intr_eof__##f2##__VAL(R_USB_IRQ_READ_, intr_eof_, v2) << R_USB_IRQ_READ__intr_eof__BITNR) | \
+ (R_USB_IRQ_READ__iso_eot__##f3##__VAL(R_USB_IRQ_READ_, iso_eot_, v3) << R_USB_IRQ_READ__iso_eot__BITNR) | \
+ (R_USB_IRQ_READ__intr_eot__##f4##__VAL(R_USB_IRQ_READ_, intr_eot_, v4) << R_USB_IRQ_READ__intr_eot__BITNR) | \
+ (R_USB_IRQ_READ__ctl_eot__##f5##__VAL(R_USB_IRQ_READ_, ctl_eot_, v5) << R_USB_IRQ_READ__ctl_eot__BITNR) | \
+ (R_USB_IRQ_READ__bulk_eot__##f6##__VAL(R_USB_IRQ_READ_, bulk_eot_, v6) << R_USB_IRQ_READ__bulk_eot__BITNR) | \
+ (R_USB_IRQ_READ__epid_attn__##f7##__VAL(R_USB_IRQ_READ_, epid_attn_, v7) << R_USB_IRQ_READ__epid_attn__BITNR) | \
+ (R_USB_IRQ_READ__sof__##f8##__VAL(R_USB_IRQ_READ_, sof_, v8) << R_USB_IRQ_READ__sof__BITNR) | \
+ (R_USB_IRQ_READ__port_status__##f9##__VAL(R_USB_IRQ_READ_, port_status_, v9) << R_USB_IRQ_READ__port_status__BITNR) | \
+ (R_USB_IRQ_READ__ctl_status__##f10##__VAL(R_USB_IRQ_READ_, ctl_status_, v10) << R_USB_IRQ_READ__ctl_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10) ( \
+ (R_USB_IRQ_READ__iso_eof__##f1_##_VAL(R_USB_IRQ_READ_, iso_eof_, v1) << R_USB_IRQ_READ__iso_eof__BITNR) | \
+ (R_USB_IRQ_READ__intr_eof__##f2_##_VAL(R_USB_IRQ_READ_, intr_eof_, v2) << R_USB_IRQ_READ__intr_eof__BITNR) | \
+ (R_USB_IRQ_READ__iso_eot__##f3_##_VAL(R_USB_IRQ_READ_, iso_eot_, v3) << R_USB_IRQ_READ__iso_eot__BITNR) | \
+ (R_USB_IRQ_READ__intr_eot__##f4_##_VAL(R_USB_IRQ_READ_, intr_eot_, v4) << R_USB_IRQ_READ__intr_eot__BITNR) | \
+ (R_USB_IRQ_READ__ctl_eot__##f5_##_VAL(R_USB_IRQ_READ_, ctl_eot_, v5) << R_USB_IRQ_READ__ctl_eot__BITNR) | \
+ (R_USB_IRQ_READ__bulk_eot__##f6_##_VAL(R_USB_IRQ_READ_, bulk_eot_, v6) << R_USB_IRQ_READ__bulk_eot__BITNR) | \
+ (R_USB_IRQ_READ__epid_attn__##f7_##_VAL(R_USB_IRQ_READ_, epid_attn_, v7) << R_USB_IRQ_READ__epid_attn__BITNR) | \
+ (R_USB_IRQ_READ__sof__##f8_##_VAL(R_USB_IRQ_READ_, sof_, v8) << R_USB_IRQ_READ__sof__BITNR) | \
+ (R_USB_IRQ_READ__port_status__##f9_##_VAL(R_USB_IRQ_READ_, port_status_, v9) << R_USB_IRQ_READ__port_status__BITNR) | \
+ (R_USB_IRQ_READ__ctl_status__##f10_##_VAL(R_USB_IRQ_READ_, ctl_status_, v10) << R_USB_IRQ_READ__ctl_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_IRQ_READ_DEV
+ * - type: RO
+ * - addr: 0xb0000206
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_IRQ_READ_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_IRQ_READ_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_USB_IRQ_READ_DEV__out_eot__##f1##__MASK & REG__##v1) | \
+ (R_USB_IRQ_READ_DEV__ep3_in_eot__##f2##__MASK & REG__##v2) | \
+ (R_USB_IRQ_READ_DEV__ep2_in_eot__##f3##__MASK & REG__##v3) | \
+ (R_USB_IRQ_READ_DEV__ep1_in_eot__##f4##__MASK & REG__##v4) | \
+ (R_USB_IRQ_READ_DEV__ep0_in_eot__##f5##__MASK & REG__##v5) | \
+ (R_USB_IRQ_READ_DEV__epid_attn__##f6##__MASK & REG__##v6) | \
+ (R_USB_IRQ_READ_DEV__sof__##f7##__MASK & REG__##v7) | \
+ (R_USB_IRQ_READ_DEV__port_status__##f8##__MASK & REG__##v8) | \
+ (R_USB_IRQ_READ_DEV__ctl_status__##f9##__MASK & REG__##v9) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_READ_DEV
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_READ_DEV.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_READ_DEV(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9) ( \
+ (R_USB_IRQ_READ_DEV__out_eot__##f1##__VAL(R_USB_IRQ_READ_DEV_, out_eot_, v1) << R_USB_IRQ_READ_DEV__out_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ep3_in_eot__##f2##__VAL(R_USB_IRQ_READ_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ep2_in_eot__##f3##__VAL(R_USB_IRQ_READ_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ep1_in_eot__##f4##__VAL(R_USB_IRQ_READ_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ep0_in_eot__##f5##__VAL(R_USB_IRQ_READ_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__epid_attn__##f6##__VAL(R_USB_IRQ_READ_DEV_, epid_attn_, v6) << R_USB_IRQ_READ_DEV__epid_attn__BITNR) | \
+ (R_USB_IRQ_READ_DEV__sof__##f7##__VAL(R_USB_IRQ_READ_DEV_, sof_, v7) << R_USB_IRQ_READ_DEV__sof__BITNR) | \
+ (R_USB_IRQ_READ_DEV__port_status__##f8##__VAL(R_USB_IRQ_READ_DEV_, port_status_, v8) << R_USB_IRQ_READ_DEV__port_status__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ctl_status__##f9##__VAL(R_USB_IRQ_READ_DEV_, ctl_status_, v9) << R_USB_IRQ_READ_DEV__ctl_status__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_IRQ_READ_DEV_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_IRQ_READ_DEV.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_IRQ_READ_DEV_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9) ( \
+ (R_USB_IRQ_READ_DEV__out_eot__##f1_##_VAL(R_USB_IRQ_READ_DEV_, out_eot_, v1) << R_USB_IRQ_READ_DEV__out_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ep3_in_eot__##f2_##_VAL(R_USB_IRQ_READ_DEV_, ep3_in_eot_, v2) << R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ep2_in_eot__##f3_##_VAL(R_USB_IRQ_READ_DEV_, ep2_in_eot_, v3) << R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ep1_in_eot__##f4_##_VAL(R_USB_IRQ_READ_DEV_, ep1_in_eot_, v4) << R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ep0_in_eot__##f5_##_VAL(R_USB_IRQ_READ_DEV_, ep0_in_eot_, v5) << R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR) | \
+ (R_USB_IRQ_READ_DEV__epid_attn__##f6_##_VAL(R_USB_IRQ_READ_DEV_, epid_attn_, v6) << R_USB_IRQ_READ_DEV__epid_attn__BITNR) | \
+ (R_USB_IRQ_READ_DEV__sof__##f7_##_VAL(R_USB_IRQ_READ_DEV_, sof_, v7) << R_USB_IRQ_READ_DEV__sof__BITNR) | \
+ (R_USB_IRQ_READ_DEV__port_status__##f8_##_VAL(R_USB_IRQ_READ_DEV_, port_status_, v8) << R_USB_IRQ_READ_DEV__port_status__BITNR) | \
+ (R_USB_IRQ_READ_DEV__ctl_status__##f9_##_VAL(R_USB_IRQ_READ_DEV_, ctl_status_, v9) << R_USB_IRQ_READ_DEV__ctl_status__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_PORT1_DISABLE
+ * - type: WO
+ * - addr: 0xb000006a
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_PORT1_DISABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_PORT1_DISABLE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_PORT1_DISABLE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_PORT1_DISABLE(f1,v1) ( \
+ *R_USB_PORT1_DISABLE__SADDR = ( \
+ REG_INITIATED(R_USB_PORT1_DISABLE_) \
+ REG_VAL__R_USB_PORT1_DISABLE_(f1##_,v1) \
+ ), \
+ R_USB_PORT1_DISABLE__WRITE(R_USB_PORT1_DISABLE__ADDR, *R_USB_PORT1_DISABLE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_PORT1_DISABLE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_PORT1_DISABLE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_USB_PORT1_DISABLE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_PORT1_DISABLE__SHADOW(f1,v1) ( \
+ *R_USB_PORT1_DISABLE__SADDR = ( \
+ REG_INITIATED(R_USB_PORT1_DISABLE_) \
+ REG_VAL__R_USB_PORT1_DISABLE_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_PORT1_DISABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_PORT1_DISABLE(f1,v1) ( \
+ (R_USB_PORT1_DISABLE__disable__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_PORT1_DISABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_PORT1_DISABLE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_PORT1_DISABLE(f1,v1) ( \
+ (R_USB_PORT1_DISABLE__disable__##f1##__VAL(R_USB_PORT1_DISABLE_, disable_, v1) << R_USB_PORT1_DISABLE__disable__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_PORT1_DISABLE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_PORT1_DISABLE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_PORT1_DISABLE_(f1_,v1) ( \
+ (R_USB_PORT1_DISABLE__disable__##f1_##_VAL(R_USB_PORT1_DISABLE_, disable_, v1) << R_USB_PORT1_DISABLE__disable__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_PORT2_DISABLE
+ * - type: WO
+ * - addr: 0xb0000052
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_PORT2_DISABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_PORT2_DISABLE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_PORT2_DISABLE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_PORT2_DISABLE(f1,v1) ( \
+ *R_USB_PORT2_DISABLE__SADDR = ( \
+ REG_INITIATED(R_USB_PORT2_DISABLE_) \
+ REG_VAL__R_USB_PORT2_DISABLE_(f1##_,v1) \
+ ), \
+ R_USB_PORT2_DISABLE__WRITE(R_USB_PORT2_DISABLE__ADDR, *R_USB_PORT2_DISABLE__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_PORT2_DISABLE__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_PORT2_DISABLE.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_USB_PORT2_DISABLE.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_PORT2_DISABLE__SHADOW(f1,v1) ( \
+ *R_USB_PORT2_DISABLE__SADDR = ( \
+ REG_INITIATED(R_USB_PORT2_DISABLE_) \
+ REG_VAL__R_USB_PORT2_DISABLE_(f1##_,v1) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_PORT2_DISABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_PORT2_DISABLE(f1,v1) ( \
+ (R_USB_PORT2_DISABLE__disable__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_PORT2_DISABLE
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_PORT2_DISABLE.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_PORT2_DISABLE(f1,v1) ( \
+ (R_USB_PORT2_DISABLE__disable__##f1##__VAL(R_USB_PORT2_DISABLE_, disable_, v1) << R_USB_PORT2_DISABLE__disable__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_PORT2_DISABLE_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_PORT2_DISABLE.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_PORT2_DISABLE_(f1_,v1) ( \
+ (R_USB_PORT2_DISABLE__disable__##f1_##_VAL(R_USB_PORT2_DISABLE_, disable_, v1) << R_USB_PORT2_DISABLE__disable__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_REVISION
+ * - type: RO
+ * - addr: 0xb0000200
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_REVISION
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_REVISION(f1,v1,f2,v2) ( \
+ (R_USB_REVISION__major__##f1##__MASK & REG__##v1) | \
+ (R_USB_REVISION__minor__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_REVISION
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_REVISION.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_REVISION(f1,v1,f2,v2) ( \
+ (R_USB_REVISION__major__##f1##__VAL(R_USB_REVISION_, major_, v1) << R_USB_REVISION__major__BITNR) | \
+ (R_USB_REVISION__minor__##f2##__VAL(R_USB_REVISION_, minor_, v2) << R_USB_REVISION__minor__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_REVISION_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_REVISION.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_REVISION_(f1_,v1,f2_,v2) ( \
+ (R_USB_REVISION__major__##f1_##_VAL(R_USB_REVISION_, major_, v1) << R_USB_REVISION__major__BITNR) | \
+ (R_USB_REVISION__minor__##f2_##_VAL(R_USB_REVISION_, minor_, v2) << R_USB_REVISION__minor__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_RH_PORT_STATUS_1
+ * - type: RO
+ * - addr: 0xb0000218
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_RH_PORT_STATUS_1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_RH_PORT_STATUS_1(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ (R_USB_RH_PORT_STATUS_1__speed__##f1##__MASK & REG__##v1) | \
+ (R_USB_RH_PORT_STATUS_1__power__##f2##__MASK & REG__##v2) | \
+ (R_USB_RH_PORT_STATUS_1__reset__##f3##__MASK & REG__##v3) | \
+ (R_USB_RH_PORT_STATUS_1__overcurrent__##f4##__MASK & REG__##v4) | \
+ (R_USB_RH_PORT_STATUS_1__suspended__##f5##__MASK & REG__##v5) | \
+ (R_USB_RH_PORT_STATUS_1__enabled__##f6##__MASK & REG__##v6) | \
+ (R_USB_RH_PORT_STATUS_1__connected__##f7##__MASK & REG__##v7) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_RH_PORT_STATUS_1
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_RH_PORT_STATUS_1.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_RH_PORT_STATUS_1(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ (R_USB_RH_PORT_STATUS_1__speed__##f1##__VAL(R_USB_RH_PORT_STATUS_1_, speed_, v1) << R_USB_RH_PORT_STATUS_1__speed__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__power__##f2##__VAL(R_USB_RH_PORT_STATUS_1_, power_, v2) << R_USB_RH_PORT_STATUS_1__power__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__reset__##f3##__VAL(R_USB_RH_PORT_STATUS_1_, reset_, v3) << R_USB_RH_PORT_STATUS_1__reset__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__overcurrent__##f4##__VAL(R_USB_RH_PORT_STATUS_1_, overcurrent_, v4) << R_USB_RH_PORT_STATUS_1__overcurrent__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__suspended__##f5##__VAL(R_USB_RH_PORT_STATUS_1_, suspended_, v5) << R_USB_RH_PORT_STATUS_1__suspended__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__enabled__##f6##__VAL(R_USB_RH_PORT_STATUS_1_, enabled_, v6) << R_USB_RH_PORT_STATUS_1__enabled__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__connected__##f7##__VAL(R_USB_RH_PORT_STATUS_1_, connected_, v7) << R_USB_RH_PORT_STATUS_1__connected__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_RH_PORT_STATUS_1_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_RH_PORT_STATUS_1.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_RH_PORT_STATUS_1_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7) ( \
+ (R_USB_RH_PORT_STATUS_1__speed__##f1_##_VAL(R_USB_RH_PORT_STATUS_1_, speed_, v1) << R_USB_RH_PORT_STATUS_1__speed__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__power__##f2_##_VAL(R_USB_RH_PORT_STATUS_1_, power_, v2) << R_USB_RH_PORT_STATUS_1__power__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__reset__##f3_##_VAL(R_USB_RH_PORT_STATUS_1_, reset_, v3) << R_USB_RH_PORT_STATUS_1__reset__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__overcurrent__##f4_##_VAL(R_USB_RH_PORT_STATUS_1_, overcurrent_, v4) << R_USB_RH_PORT_STATUS_1__overcurrent__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__suspended__##f5_##_VAL(R_USB_RH_PORT_STATUS_1_, suspended_, v5) << R_USB_RH_PORT_STATUS_1__suspended__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__enabled__##f6_##_VAL(R_USB_RH_PORT_STATUS_1_, enabled_, v6) << R_USB_RH_PORT_STATUS_1__enabled__BITNR) | \
+ (R_USB_RH_PORT_STATUS_1__connected__##f7_##_VAL(R_USB_RH_PORT_STATUS_1_, connected_, v7) << R_USB_RH_PORT_STATUS_1__connected__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_RH_PORT_STATUS_2
+ * - type: RO
+ * - addr: 0xb000021a
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_RH_PORT_STATUS_2
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_RH_PORT_STATUS_2(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ (R_USB_RH_PORT_STATUS_2__speed__##f1##__MASK & REG__##v1) | \
+ (R_USB_RH_PORT_STATUS_2__power__##f2##__MASK & REG__##v2) | \
+ (R_USB_RH_PORT_STATUS_2__reset__##f3##__MASK & REG__##v3) | \
+ (R_USB_RH_PORT_STATUS_2__overcurrent__##f4##__MASK & REG__##v4) | \
+ (R_USB_RH_PORT_STATUS_2__suspended__##f5##__MASK & REG__##v5) | \
+ (R_USB_RH_PORT_STATUS_2__enabled__##f6##__MASK & REG__##v6) | \
+ (R_USB_RH_PORT_STATUS_2__connected__##f7##__MASK & REG__##v7) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_RH_PORT_STATUS_2
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_RH_PORT_STATUS_2.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_RH_PORT_STATUS_2(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7) ( \
+ (R_USB_RH_PORT_STATUS_2__speed__##f1##__VAL(R_USB_RH_PORT_STATUS_2_, speed_, v1) << R_USB_RH_PORT_STATUS_2__speed__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__power__##f2##__VAL(R_USB_RH_PORT_STATUS_2_, power_, v2) << R_USB_RH_PORT_STATUS_2__power__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__reset__##f3##__VAL(R_USB_RH_PORT_STATUS_2_, reset_, v3) << R_USB_RH_PORT_STATUS_2__reset__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__overcurrent__##f4##__VAL(R_USB_RH_PORT_STATUS_2_, overcurrent_, v4) << R_USB_RH_PORT_STATUS_2__overcurrent__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__suspended__##f5##__VAL(R_USB_RH_PORT_STATUS_2_, suspended_, v5) << R_USB_RH_PORT_STATUS_2__suspended__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__enabled__##f6##__VAL(R_USB_RH_PORT_STATUS_2_, enabled_, v6) << R_USB_RH_PORT_STATUS_2__enabled__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__connected__##f7##__VAL(R_USB_RH_PORT_STATUS_2_, connected_, v7) << R_USB_RH_PORT_STATUS_2__connected__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_RH_PORT_STATUS_2_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_RH_PORT_STATUS_2.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_RH_PORT_STATUS_2_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7) ( \
+ (R_USB_RH_PORT_STATUS_2__speed__##f1_##_VAL(R_USB_RH_PORT_STATUS_2_, speed_, v1) << R_USB_RH_PORT_STATUS_2__speed__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__power__##f2_##_VAL(R_USB_RH_PORT_STATUS_2_, power_, v2) << R_USB_RH_PORT_STATUS_2__power__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__reset__##f3_##_VAL(R_USB_RH_PORT_STATUS_2_, reset_, v3) << R_USB_RH_PORT_STATUS_2__reset__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__overcurrent__##f4_##_VAL(R_USB_RH_PORT_STATUS_2_, overcurrent_, v4) << R_USB_RH_PORT_STATUS_2__overcurrent__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__suspended__##f5_##_VAL(R_USB_RH_PORT_STATUS_2_, suspended_, v5) << R_USB_RH_PORT_STATUS_2__suspended__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__enabled__##f6_##_VAL(R_USB_RH_PORT_STATUS_2_, enabled_, v6) << R_USB_RH_PORT_STATUS_2__enabled__BITNR) | \
+ (R_USB_RH_PORT_STATUS_2__connected__##f7_##_VAL(R_USB_RH_PORT_STATUS_2_, connected_, v7) << R_USB_RH_PORT_STATUS_2__connected__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_RH_STATUS
+ * - type: RO
+ * - addr: 0xb0000203
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_RH_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_RH_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_USB_RH_STATUS__babble2__##f1##__MASK & REG__##v1) | \
+ (R_USB_RH_STATUS__babble1__##f2##__MASK & REG__##v2) | \
+ (R_USB_RH_STATUS__bus1__##f3##__MASK & REG__##v3) | \
+ (R_USB_RH_STATUS__bus2__##f4##__MASK & REG__##v4) | \
+ (R_USB_RH_STATUS__nports__##f5##__MASK & REG__##v5) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_RH_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_RH_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_RH_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5) ( \
+ (R_USB_RH_STATUS__babble2__##f1##__VAL(R_USB_RH_STATUS_, babble2_, v1) << R_USB_RH_STATUS__babble2__BITNR) | \
+ (R_USB_RH_STATUS__babble1__##f2##__VAL(R_USB_RH_STATUS_, babble1_, v2) << R_USB_RH_STATUS__babble1__BITNR) | \
+ (R_USB_RH_STATUS__bus1__##f3##__VAL(R_USB_RH_STATUS_, bus1_, v3) << R_USB_RH_STATUS__bus1__BITNR) | \
+ (R_USB_RH_STATUS__bus2__##f4##__VAL(R_USB_RH_STATUS_, bus2_, v4) << R_USB_RH_STATUS__bus2__BITNR) | \
+ (R_USB_RH_STATUS__nports__##f5##__VAL(R_USB_RH_STATUS_, nports_, v5) << R_USB_RH_STATUS__nports__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_RH_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_RH_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_RH_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5) ( \
+ (R_USB_RH_STATUS__babble2__##f1_##_VAL(R_USB_RH_STATUS_, babble2_, v1) << R_USB_RH_STATUS__babble2__BITNR) | \
+ (R_USB_RH_STATUS__babble1__##f2_##_VAL(R_USB_RH_STATUS_, babble1_, v2) << R_USB_RH_STATUS__babble1__BITNR) | \
+ (R_USB_RH_STATUS__bus1__##f3_##_VAL(R_USB_RH_STATUS_, bus1_, v3) << R_USB_RH_STATUS__bus1__BITNR) | \
+ (R_USB_RH_STATUS__bus2__##f4_##_VAL(R_USB_RH_STATUS_, bus2_, v4) << R_USB_RH_STATUS__bus2__BITNR) | \
+ (R_USB_RH_STATUS__nports__##f5_##_VAL(R_USB_RH_STATUS_, nports_, v5) << R_USB_RH_STATUS__nports__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_SNMP_TERROR
+ * - type: RW
+ * - addr: 0xb0000220
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_USB_SNMP_TERROR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_USB_SNMP_TERROR.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_USB_SNMP_TERROR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_USB_SNMP_TERROR(f1,v1) ( \
+ R_USB_SNMP_TERROR__WRITE(R_USB_SNMP_TERROR__ADDR, ( \
+ REG_VAL__R_USB_SNMP_TERROR_(f1##_,v1) ) \
+ ) \
+)
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_SNMP_TERROR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_SNMP_TERROR(f1,v1) ( \
+ (R_USB_SNMP_TERROR__value__##f1##__MASK & REG__##v1) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_SNMP_TERROR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_SNMP_TERROR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_SNMP_TERROR(f1,v1) ( \
+ (R_USB_SNMP_TERROR__value__##f1##__VAL(R_USB_SNMP_TERROR_, value_, v1) << R_USB_SNMP_TERROR__value__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_SNMP_TERROR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_SNMP_TERROR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_SNMP_TERROR_(f1_,v1) ( \
+ (R_USB_SNMP_TERROR__value__##f1_##_VAL(R_USB_SNMP_TERROR_, value_, v1) << R_USB_SNMP_TERROR__value__BITNR) \
+)
+
+#endif
+
+/*
+ * R_USB_STATUS
+ * - type: RO
+ * - addr: 0xb0000202
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_USB_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_USB_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_USB_STATUS__ourun__##f1##__MASK & REG__##v1) | \
+ (R_USB_STATUS__perror__##f2##__MASK & REG__##v2) | \
+ (R_USB_STATUS__device_mode__##f3##__MASK & REG__##v3) | \
+ (R_USB_STATUS__host_mode__##f4##__MASK & REG__##v4) | \
+ (R_USB_STATUS__started__##f5##__MASK & REG__##v5) | \
+ (R_USB_STATUS__running__##f6##__MASK & REG__##v6) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_STATUS
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_STATUS.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_STATUS(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6) ( \
+ (R_USB_STATUS__ourun__##f1##__VAL(R_USB_STATUS_, ourun_, v1) << R_USB_STATUS__ourun__BITNR) | \
+ (R_USB_STATUS__perror__##f2##__VAL(R_USB_STATUS_, perror_, v2) << R_USB_STATUS__perror__BITNR) | \
+ (R_USB_STATUS__device_mode__##f3##__VAL(R_USB_STATUS_, device_mode_, v3) << R_USB_STATUS__device_mode__BITNR) | \
+ (R_USB_STATUS__host_mode__##f4##__VAL(R_USB_STATUS_, host_mode_, v4) << R_USB_STATUS__host_mode__BITNR) | \
+ (R_USB_STATUS__started__##f5##__VAL(R_USB_STATUS_, started_, v5) << R_USB_STATUS__started__BITNR) | \
+ (R_USB_STATUS__running__##f6##__VAL(R_USB_STATUS_, running_, v6) << R_USB_STATUS__running__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_USB_STATUS_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_USB_STATUS.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_USB_STATUS_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6) ( \
+ (R_USB_STATUS__ourun__##f1_##_VAL(R_USB_STATUS_, ourun_, v1) << R_USB_STATUS__ourun__BITNR) | \
+ (R_USB_STATUS__perror__##f2_##_VAL(R_USB_STATUS_, perror_, v2) << R_USB_STATUS__perror__BITNR) | \
+ (R_USB_STATUS__device_mode__##f3_##_VAL(R_USB_STATUS_, device_mode_, v3) << R_USB_STATUS__device_mode__BITNR) | \
+ (R_USB_STATUS__host_mode__##f4_##_VAL(R_USB_STATUS_, host_mode_, v4) << R_USB_STATUS__host_mode__BITNR) | \
+ (R_USB_STATUS__started__##f5_##_VAL(R_USB_STATUS_, started_, v5) << R_USB_STATUS__started__BITNR) | \
+ (R_USB_STATUS__running__##f6_##_VAL(R_USB_STATUS_, running_, v6) << R_USB_STATUS__running__BITNR) \
+)
+
+#endif
+
+/*
+ * R_VECT_MASK_CLR
+ * - type: WO
+ * - addr: 0xb00000d8
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_VECT_MASK_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_VECT_MASK_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_VECT_MASK_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_VECT_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ *R_VECT_MASK_CLR__SADDR = ( \
+ REG_INITIATED(R_VECT_MASK_CLR_) \
+ REG_VAL__R_VECT_MASK_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \
+ ), \
+ R_VECT_MASK_CLR__WRITE(R_VECT_MASK_CLR__ADDR, *R_VECT_MASK_CLR__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_VECT_MASK_CLR__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_VECT_MASK_CLR.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_VECT_MASK_CLR.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_VECT_MASK_CLR__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ *R_VECT_MASK_CLR__SADDR = ( \
+ REG_INITIATED(R_VECT_MASK_CLR_) \
+ REG_VAL__R_VECT_MASK_CLR_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_VECT_MASK_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_VECT_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_VECT_MASK_CLR__usb__##f1##__MASK & REG__##v1) | \
+ (R_VECT_MASK_CLR__dma9__##f2##__MASK & REG__##v2) | \
+ (R_VECT_MASK_CLR__dma8__##f3##__MASK & REG__##v3) | \
+ (R_VECT_MASK_CLR__dma7__##f4##__MASK & REG__##v4) | \
+ (R_VECT_MASK_CLR__dma6__##f5##__MASK & REG__##v5) | \
+ (R_VECT_MASK_CLR__dma5__##f6##__MASK & REG__##v6) | \
+ (R_VECT_MASK_CLR__dma4__##f7##__MASK & REG__##v7) | \
+ (R_VECT_MASK_CLR__dma3__##f8##__MASK & REG__##v8) | \
+ (R_VECT_MASK_CLR__dma2__##f9##__MASK & REG__##v9) | \
+ (R_VECT_MASK_CLR__dma1__##f10##__MASK & REG__##v10) | \
+ (R_VECT_MASK_CLR__dma0__##f11##__MASK & REG__##v11) | \
+ (R_VECT_MASK_CLR__ext_dma1__##f12##__MASK & REG__##v12) | \
+ (R_VECT_MASK_CLR__ext_dma0__##f13##__MASK & REG__##v13) | \
+ (R_VECT_MASK_CLR__pa__##f14##__MASK & REG__##v14) | \
+ (R_VECT_MASK_CLR__irq_intnr__##f15##__MASK & REG__##v15) | \
+ (R_VECT_MASK_CLR__sw__##f16##__MASK & REG__##v16) | \
+ (R_VECT_MASK_CLR__serial__##f17##__MASK & REG__##v17) | \
+ (R_VECT_MASK_CLR__snmp__##f18##__MASK & REG__##v18) | \
+ (R_VECT_MASK_CLR__network__##f19##__MASK & REG__##v19) | \
+ (R_VECT_MASK_CLR__scsi1__##f20##__MASK & REG__##v20) | \
+ (R_VECT_MASK_CLR__scsi0__##f21##__MASK & REG__##v21) | \
+ (R_VECT_MASK_CLR__timer1__##f22##__MASK & REG__##v22) | \
+ (R_VECT_MASK_CLR__timer0__##f23##__MASK & REG__##v23) | \
+ (R_VECT_MASK_CLR__nmi__##f24##__MASK & REG__##v24) | \
+ (R_VECT_MASK_CLR__some__##f25##__MASK & REG__##v25) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_VECT_MASK_CLR
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_VECT_MASK_CLR.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_VECT_MASK_CLR(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_VECT_MASK_CLR__usb__##f1##__VAL(R_VECT_MASK_CLR_, usb_, v1) << R_VECT_MASK_CLR__usb__BITNR) | \
+ (R_VECT_MASK_CLR__dma9__##f2##__VAL(R_VECT_MASK_CLR_, dma9_, v2) << R_VECT_MASK_CLR__dma9__BITNR) | \
+ (R_VECT_MASK_CLR__dma8__##f3##__VAL(R_VECT_MASK_CLR_, dma8_, v3) << R_VECT_MASK_CLR__dma8__BITNR) | \
+ (R_VECT_MASK_CLR__dma7__##f4##__VAL(R_VECT_MASK_CLR_, dma7_, v4) << R_VECT_MASK_CLR__dma7__BITNR) | \
+ (R_VECT_MASK_CLR__dma6__##f5##__VAL(R_VECT_MASK_CLR_, dma6_, v5) << R_VECT_MASK_CLR__dma6__BITNR) | \
+ (R_VECT_MASK_CLR__dma5__##f6##__VAL(R_VECT_MASK_CLR_, dma5_, v6) << R_VECT_MASK_CLR__dma5__BITNR) | \
+ (R_VECT_MASK_CLR__dma4__##f7##__VAL(R_VECT_MASK_CLR_, dma4_, v7) << R_VECT_MASK_CLR__dma4__BITNR) | \
+ (R_VECT_MASK_CLR__dma3__##f8##__VAL(R_VECT_MASK_CLR_, dma3_, v8) << R_VECT_MASK_CLR__dma3__BITNR) | \
+ (R_VECT_MASK_CLR__dma2__##f9##__VAL(R_VECT_MASK_CLR_, dma2_, v9) << R_VECT_MASK_CLR__dma2__BITNR) | \
+ (R_VECT_MASK_CLR__dma1__##f10##__VAL(R_VECT_MASK_CLR_, dma1_, v10) << R_VECT_MASK_CLR__dma1__BITNR) | \
+ (R_VECT_MASK_CLR__dma0__##f11##__VAL(R_VECT_MASK_CLR_, dma0_, v11) << R_VECT_MASK_CLR__dma0__BITNR) | \
+ (R_VECT_MASK_CLR__ext_dma1__##f12##__VAL(R_VECT_MASK_CLR_, ext_dma1_, v12) << R_VECT_MASK_CLR__ext_dma1__BITNR) | \
+ (R_VECT_MASK_CLR__ext_dma0__##f13##__VAL(R_VECT_MASK_CLR_, ext_dma0_, v13) << R_VECT_MASK_CLR__ext_dma0__BITNR) | \
+ (R_VECT_MASK_CLR__pa__##f14##__VAL(R_VECT_MASK_CLR_, pa_, v14) << R_VECT_MASK_CLR__pa__BITNR) | \
+ (R_VECT_MASK_CLR__irq_intnr__##f15##__VAL(R_VECT_MASK_CLR_, irq_intnr_, v15) << R_VECT_MASK_CLR__irq_intnr__BITNR) | \
+ (R_VECT_MASK_CLR__sw__##f16##__VAL(R_VECT_MASK_CLR_, sw_, v16) << R_VECT_MASK_CLR__sw__BITNR) | \
+ (R_VECT_MASK_CLR__serial__##f17##__VAL(R_VECT_MASK_CLR_, serial_, v17) << R_VECT_MASK_CLR__serial__BITNR) | \
+ (R_VECT_MASK_CLR__snmp__##f18##__VAL(R_VECT_MASK_CLR_, snmp_, v18) << R_VECT_MASK_CLR__snmp__BITNR) | \
+ (R_VECT_MASK_CLR__network__##f19##__VAL(R_VECT_MASK_CLR_, network_, v19) << R_VECT_MASK_CLR__network__BITNR) | \
+ (R_VECT_MASK_CLR__scsi1__##f20##__VAL(R_VECT_MASK_CLR_, scsi1_, v20) << R_VECT_MASK_CLR__scsi1__BITNR) | \
+ (R_VECT_MASK_CLR__scsi0__##f21##__VAL(R_VECT_MASK_CLR_, scsi0_, v21) << R_VECT_MASK_CLR__scsi0__BITNR) | \
+ (R_VECT_MASK_CLR__timer1__##f22##__VAL(R_VECT_MASK_CLR_, timer1_, v22) << R_VECT_MASK_CLR__timer1__BITNR) | \
+ (R_VECT_MASK_CLR__timer0__##f23##__VAL(R_VECT_MASK_CLR_, timer0_, v23) << R_VECT_MASK_CLR__timer0__BITNR) | \
+ (R_VECT_MASK_CLR__nmi__##f24##__VAL(R_VECT_MASK_CLR_, nmi_, v24) << R_VECT_MASK_CLR__nmi__BITNR) | \
+ (R_VECT_MASK_CLR__some__##f25##__VAL(R_VECT_MASK_CLR_, some_, v25) << R_VECT_MASK_CLR__some__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_VECT_MASK_CLR_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_VECT_MASK_CLR.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_VECT_MASK_CLR_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \
+ (R_VECT_MASK_CLR__usb__##f1_##_VAL(R_VECT_MASK_CLR_, usb_, v1) << R_VECT_MASK_CLR__usb__BITNR) | \
+ (R_VECT_MASK_CLR__dma9__##f2_##_VAL(R_VECT_MASK_CLR_, dma9_, v2) << R_VECT_MASK_CLR__dma9__BITNR) | \
+ (R_VECT_MASK_CLR__dma8__##f3_##_VAL(R_VECT_MASK_CLR_, dma8_, v3) << R_VECT_MASK_CLR__dma8__BITNR) | \
+ (R_VECT_MASK_CLR__dma7__##f4_##_VAL(R_VECT_MASK_CLR_, dma7_, v4) << R_VECT_MASK_CLR__dma7__BITNR) | \
+ (R_VECT_MASK_CLR__dma6__##f5_##_VAL(R_VECT_MASK_CLR_, dma6_, v5) << R_VECT_MASK_CLR__dma6__BITNR) | \
+ (R_VECT_MASK_CLR__dma5__##f6_##_VAL(R_VECT_MASK_CLR_, dma5_, v6) << R_VECT_MASK_CLR__dma5__BITNR) | \
+ (R_VECT_MASK_CLR__dma4__##f7_##_VAL(R_VECT_MASK_CLR_, dma4_, v7) << R_VECT_MASK_CLR__dma4__BITNR) | \
+ (R_VECT_MASK_CLR__dma3__##f8_##_VAL(R_VECT_MASK_CLR_, dma3_, v8) << R_VECT_MASK_CLR__dma3__BITNR) | \
+ (R_VECT_MASK_CLR__dma2__##f9_##_VAL(R_VECT_MASK_CLR_, dma2_, v9) << R_VECT_MASK_CLR__dma2__BITNR) | \
+ (R_VECT_MASK_CLR__dma1__##f10_##_VAL(R_VECT_MASK_CLR_, dma1_, v10) << R_VECT_MASK_CLR__dma1__BITNR) | \
+ (R_VECT_MASK_CLR__dma0__##f11_##_VAL(R_VECT_MASK_CLR_, dma0_, v11) << R_VECT_MASK_CLR__dma0__BITNR) | \
+ (R_VECT_MASK_CLR__ext_dma1__##f12_##_VAL(R_VECT_MASK_CLR_, ext_dma1_, v12) << R_VECT_MASK_CLR__ext_dma1__BITNR) | \
+ (R_VECT_MASK_CLR__ext_dma0__##f13_##_VAL(R_VECT_MASK_CLR_, ext_dma0_, v13) << R_VECT_MASK_CLR__ext_dma0__BITNR) | \
+ (R_VECT_MASK_CLR__pa__##f14_##_VAL(R_VECT_MASK_CLR_, pa_, v14) << R_VECT_MASK_CLR__pa__BITNR) | \
+ (R_VECT_MASK_CLR__irq_intnr__##f15_##_VAL(R_VECT_MASK_CLR_, irq_intnr_, v15) << R_VECT_MASK_CLR__irq_intnr__BITNR) | \
+ (R_VECT_MASK_CLR__sw__##f16_##_VAL(R_VECT_MASK_CLR_, sw_, v16) << R_VECT_MASK_CLR__sw__BITNR) | \
+ (R_VECT_MASK_CLR__serial__##f17_##_VAL(R_VECT_MASK_CLR_, serial_, v17) << R_VECT_MASK_CLR__serial__BITNR) | \
+ (R_VECT_MASK_CLR__snmp__##f18_##_VAL(R_VECT_MASK_CLR_, snmp_, v18) << R_VECT_MASK_CLR__snmp__BITNR) | \
+ (R_VECT_MASK_CLR__network__##f19_##_VAL(R_VECT_MASK_CLR_, network_, v19) << R_VECT_MASK_CLR__network__BITNR) | \
+ (R_VECT_MASK_CLR__scsi1__##f20_##_VAL(R_VECT_MASK_CLR_, scsi1_, v20) << R_VECT_MASK_CLR__scsi1__BITNR) | \
+ (R_VECT_MASK_CLR__scsi0__##f21_##_VAL(R_VECT_MASK_CLR_, scsi0_, v21) << R_VECT_MASK_CLR__scsi0__BITNR) | \
+ (R_VECT_MASK_CLR__timer1__##f22_##_VAL(R_VECT_MASK_CLR_, timer1_, v22) << R_VECT_MASK_CLR__timer1__BITNR) | \
+ (R_VECT_MASK_CLR__timer0__##f23_##_VAL(R_VECT_MASK_CLR_, timer0_, v23) << R_VECT_MASK_CLR__timer0__BITNR) | \
+ (R_VECT_MASK_CLR__nmi__##f24_##_VAL(R_VECT_MASK_CLR_, nmi_, v24) << R_VECT_MASK_CLR__nmi__BITNR) | \
+ (R_VECT_MASK_CLR__some__##f25_##_VAL(R_VECT_MASK_CLR_, some_, v25) << R_VECT_MASK_CLR__some__BITNR) \
+)
+
+#endif
+
+/*
+ * R_VECT_MASK_RD
+ * - type: RO
+ * - addr: 0xb00000d8
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_VECT_MASK_RD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_VECT_MASK_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_VECT_MASK_RD__usb__##f1##__MASK & REG__##v1) | \
+ (R_VECT_MASK_RD__dma9__##f2##__MASK & REG__##v2) | \
+ (R_VECT_MASK_RD__dma8__##f3##__MASK & REG__##v3) | \
+ (R_VECT_MASK_RD__dma7__##f4##__MASK & REG__##v4) | \
+ (R_VECT_MASK_RD__dma6__##f5##__MASK & REG__##v5) | \
+ (R_VECT_MASK_RD__dma5__##f6##__MASK & REG__##v6) | \
+ (R_VECT_MASK_RD__dma4__##f7##__MASK & REG__##v7) | \
+ (R_VECT_MASK_RD__dma3__##f8##__MASK & REG__##v8) | \
+ (R_VECT_MASK_RD__dma2__##f9##__MASK & REG__##v9) | \
+ (R_VECT_MASK_RD__dma1__##f10##__MASK & REG__##v10) | \
+ (R_VECT_MASK_RD__dma0__##f11##__MASK & REG__##v11) | \
+ (R_VECT_MASK_RD__ext_dma1__##f12##__MASK & REG__##v12) | \
+ (R_VECT_MASK_RD__ext_dma0__##f13##__MASK & REG__##v13) | \
+ (R_VECT_MASK_RD__pa__##f14##__MASK & REG__##v14) | \
+ (R_VECT_MASK_RD__irq_intnr__##f15##__MASK & REG__##v15) | \
+ (R_VECT_MASK_RD__sw__##f16##__MASK & REG__##v16) | \
+ (R_VECT_MASK_RD__serial__##f17##__MASK & REG__##v17) | \
+ (R_VECT_MASK_RD__snmp__##f18##__MASK & REG__##v18) | \
+ (R_VECT_MASK_RD__network__##f19##__MASK & REG__##v19) | \
+ (R_VECT_MASK_RD__scsi1__##f20##__MASK & REG__##v20) | \
+ (R_VECT_MASK_RD__scsi0__##f21##__MASK & REG__##v21) | \
+ (R_VECT_MASK_RD__timer1__##f22##__MASK & REG__##v22) | \
+ (R_VECT_MASK_RD__timer0__##f23##__MASK & REG__##v23) | \
+ (R_VECT_MASK_RD__nmi__##f24##__MASK & REG__##v24) | \
+ (R_VECT_MASK_RD__some__##f25##__MASK & REG__##v25) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_VECT_MASK_RD
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_VECT_MASK_RD.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_VECT_MASK_RD(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_VECT_MASK_RD__usb__##f1##__VAL(R_VECT_MASK_RD_, usb_, v1) << R_VECT_MASK_RD__usb__BITNR) | \
+ (R_VECT_MASK_RD__dma9__##f2##__VAL(R_VECT_MASK_RD_, dma9_, v2) << R_VECT_MASK_RD__dma9__BITNR) | \
+ (R_VECT_MASK_RD__dma8__##f3##__VAL(R_VECT_MASK_RD_, dma8_, v3) << R_VECT_MASK_RD__dma8__BITNR) | \
+ (R_VECT_MASK_RD__dma7__##f4##__VAL(R_VECT_MASK_RD_, dma7_, v4) << R_VECT_MASK_RD__dma7__BITNR) | \
+ (R_VECT_MASK_RD__dma6__##f5##__VAL(R_VECT_MASK_RD_, dma6_, v5) << R_VECT_MASK_RD__dma6__BITNR) | \
+ (R_VECT_MASK_RD__dma5__##f6##__VAL(R_VECT_MASK_RD_, dma5_, v6) << R_VECT_MASK_RD__dma5__BITNR) | \
+ (R_VECT_MASK_RD__dma4__##f7##__VAL(R_VECT_MASK_RD_, dma4_, v7) << R_VECT_MASK_RD__dma4__BITNR) | \
+ (R_VECT_MASK_RD__dma3__##f8##__VAL(R_VECT_MASK_RD_, dma3_, v8) << R_VECT_MASK_RD__dma3__BITNR) | \
+ (R_VECT_MASK_RD__dma2__##f9##__VAL(R_VECT_MASK_RD_, dma2_, v9) << R_VECT_MASK_RD__dma2__BITNR) | \
+ (R_VECT_MASK_RD__dma1__##f10##__VAL(R_VECT_MASK_RD_, dma1_, v10) << R_VECT_MASK_RD__dma1__BITNR) | \
+ (R_VECT_MASK_RD__dma0__##f11##__VAL(R_VECT_MASK_RD_, dma0_, v11) << R_VECT_MASK_RD__dma0__BITNR) | \
+ (R_VECT_MASK_RD__ext_dma1__##f12##__VAL(R_VECT_MASK_RD_, ext_dma1_, v12) << R_VECT_MASK_RD__ext_dma1__BITNR) | \
+ (R_VECT_MASK_RD__ext_dma0__##f13##__VAL(R_VECT_MASK_RD_, ext_dma0_, v13) << R_VECT_MASK_RD__ext_dma0__BITNR) | \
+ (R_VECT_MASK_RD__pa__##f14##__VAL(R_VECT_MASK_RD_, pa_, v14) << R_VECT_MASK_RD__pa__BITNR) | \
+ (R_VECT_MASK_RD__irq_intnr__##f15##__VAL(R_VECT_MASK_RD_, irq_intnr_, v15) << R_VECT_MASK_RD__irq_intnr__BITNR) | \
+ (R_VECT_MASK_RD__sw__##f16##__VAL(R_VECT_MASK_RD_, sw_, v16) << R_VECT_MASK_RD__sw__BITNR) | \
+ (R_VECT_MASK_RD__serial__##f17##__VAL(R_VECT_MASK_RD_, serial_, v17) << R_VECT_MASK_RD__serial__BITNR) | \
+ (R_VECT_MASK_RD__snmp__##f18##__VAL(R_VECT_MASK_RD_, snmp_, v18) << R_VECT_MASK_RD__snmp__BITNR) | \
+ (R_VECT_MASK_RD__network__##f19##__VAL(R_VECT_MASK_RD_, network_, v19) << R_VECT_MASK_RD__network__BITNR) | \
+ (R_VECT_MASK_RD__scsi1__##f20##__VAL(R_VECT_MASK_RD_, scsi1_, v20) << R_VECT_MASK_RD__scsi1__BITNR) | \
+ (R_VECT_MASK_RD__scsi0__##f21##__VAL(R_VECT_MASK_RD_, scsi0_, v21) << R_VECT_MASK_RD__scsi0__BITNR) | \
+ (R_VECT_MASK_RD__timer1__##f22##__VAL(R_VECT_MASK_RD_, timer1_, v22) << R_VECT_MASK_RD__timer1__BITNR) | \
+ (R_VECT_MASK_RD__timer0__##f23##__VAL(R_VECT_MASK_RD_, timer0_, v23) << R_VECT_MASK_RD__timer0__BITNR) | \
+ (R_VECT_MASK_RD__nmi__##f24##__VAL(R_VECT_MASK_RD_, nmi_, v24) << R_VECT_MASK_RD__nmi__BITNR) | \
+ (R_VECT_MASK_RD__some__##f25##__VAL(R_VECT_MASK_RD_, some_, v25) << R_VECT_MASK_RD__some__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_VECT_MASK_RD_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_VECT_MASK_RD.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_VECT_MASK_RD_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \
+ (R_VECT_MASK_RD__usb__##f1_##_VAL(R_VECT_MASK_RD_, usb_, v1) << R_VECT_MASK_RD__usb__BITNR) | \
+ (R_VECT_MASK_RD__dma9__##f2_##_VAL(R_VECT_MASK_RD_, dma9_, v2) << R_VECT_MASK_RD__dma9__BITNR) | \
+ (R_VECT_MASK_RD__dma8__##f3_##_VAL(R_VECT_MASK_RD_, dma8_, v3) << R_VECT_MASK_RD__dma8__BITNR) | \
+ (R_VECT_MASK_RD__dma7__##f4_##_VAL(R_VECT_MASK_RD_, dma7_, v4) << R_VECT_MASK_RD__dma7__BITNR) | \
+ (R_VECT_MASK_RD__dma6__##f5_##_VAL(R_VECT_MASK_RD_, dma6_, v5) << R_VECT_MASK_RD__dma6__BITNR) | \
+ (R_VECT_MASK_RD__dma5__##f6_##_VAL(R_VECT_MASK_RD_, dma5_, v6) << R_VECT_MASK_RD__dma5__BITNR) | \
+ (R_VECT_MASK_RD__dma4__##f7_##_VAL(R_VECT_MASK_RD_, dma4_, v7) << R_VECT_MASK_RD__dma4__BITNR) | \
+ (R_VECT_MASK_RD__dma3__##f8_##_VAL(R_VECT_MASK_RD_, dma3_, v8) << R_VECT_MASK_RD__dma3__BITNR) | \
+ (R_VECT_MASK_RD__dma2__##f9_##_VAL(R_VECT_MASK_RD_, dma2_, v9) << R_VECT_MASK_RD__dma2__BITNR) | \
+ (R_VECT_MASK_RD__dma1__##f10_##_VAL(R_VECT_MASK_RD_, dma1_, v10) << R_VECT_MASK_RD__dma1__BITNR) | \
+ (R_VECT_MASK_RD__dma0__##f11_##_VAL(R_VECT_MASK_RD_, dma0_, v11) << R_VECT_MASK_RD__dma0__BITNR) | \
+ (R_VECT_MASK_RD__ext_dma1__##f12_##_VAL(R_VECT_MASK_RD_, ext_dma1_, v12) << R_VECT_MASK_RD__ext_dma1__BITNR) | \
+ (R_VECT_MASK_RD__ext_dma0__##f13_##_VAL(R_VECT_MASK_RD_, ext_dma0_, v13) << R_VECT_MASK_RD__ext_dma0__BITNR) | \
+ (R_VECT_MASK_RD__pa__##f14_##_VAL(R_VECT_MASK_RD_, pa_, v14) << R_VECT_MASK_RD__pa__BITNR) | \
+ (R_VECT_MASK_RD__irq_intnr__##f15_##_VAL(R_VECT_MASK_RD_, irq_intnr_, v15) << R_VECT_MASK_RD__irq_intnr__BITNR) | \
+ (R_VECT_MASK_RD__sw__##f16_##_VAL(R_VECT_MASK_RD_, sw_, v16) << R_VECT_MASK_RD__sw__BITNR) | \
+ (R_VECT_MASK_RD__serial__##f17_##_VAL(R_VECT_MASK_RD_, serial_, v17) << R_VECT_MASK_RD__serial__BITNR) | \
+ (R_VECT_MASK_RD__snmp__##f18_##_VAL(R_VECT_MASK_RD_, snmp_, v18) << R_VECT_MASK_RD__snmp__BITNR) | \
+ (R_VECT_MASK_RD__network__##f19_##_VAL(R_VECT_MASK_RD_, network_, v19) << R_VECT_MASK_RD__network__BITNR) | \
+ (R_VECT_MASK_RD__scsi1__##f20_##_VAL(R_VECT_MASK_RD_, scsi1_, v20) << R_VECT_MASK_RD__scsi1__BITNR) | \
+ (R_VECT_MASK_RD__scsi0__##f21_##_VAL(R_VECT_MASK_RD_, scsi0_, v21) << R_VECT_MASK_RD__scsi0__BITNR) | \
+ (R_VECT_MASK_RD__timer1__##f22_##_VAL(R_VECT_MASK_RD_, timer1_, v22) << R_VECT_MASK_RD__timer1__BITNR) | \
+ (R_VECT_MASK_RD__timer0__##f23_##_VAL(R_VECT_MASK_RD_, timer0_, v23) << R_VECT_MASK_RD__timer0__BITNR) | \
+ (R_VECT_MASK_RD__nmi__##f24_##_VAL(R_VECT_MASK_RD_, nmi_, v24) << R_VECT_MASK_RD__nmi__BITNR) | \
+ (R_VECT_MASK_RD__some__##f25_##_VAL(R_VECT_MASK_RD_, some_, v25) << R_VECT_MASK_RD__some__BITNR) \
+)
+
+#endif
+
+/*
+ * R_VECT_MASK_SET
+ * - type: WO
+ * - addr: 0xb00000dc
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_VECT_MASK_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_VECT_MASK_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_VECT_MASK_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_VECT_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ *R_VECT_MASK_SET__SADDR = ( \
+ REG_INITIATED(R_VECT_MASK_SET_) \
+ REG_VAL__R_VECT_MASK_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \
+ ), \
+ R_VECT_MASK_SET__WRITE(R_VECT_MASK_SET__ADDR, *R_VECT_MASK_SET__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_VECT_MASK_SET__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_VECT_MASK_SET.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_VECT_MASK_SET.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_VECT_MASK_SET__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ *R_VECT_MASK_SET__SADDR = ( \
+ REG_INITIATED(R_VECT_MASK_SET_) \
+ REG_VAL__R_VECT_MASK_SET_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12,f13##_,v13,f14##_,v14,f15##_,v15,f16##_,v16,f17##_,v17,f18##_,v18,f19##_,v19,f20##_,v20,f21##_,v21,f22##_,v22,f23##_,v23,f24##_,v24,f25##_,v25) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_VECT_MASK_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_VECT_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_VECT_MASK_SET__usb__##f1##__MASK & REG__##v1) | \
+ (R_VECT_MASK_SET__dma9__##f2##__MASK & REG__##v2) | \
+ (R_VECT_MASK_SET__dma8__##f3##__MASK & REG__##v3) | \
+ (R_VECT_MASK_SET__dma7__##f4##__MASK & REG__##v4) | \
+ (R_VECT_MASK_SET__dma6__##f5##__MASK & REG__##v5) | \
+ (R_VECT_MASK_SET__dma5__##f6##__MASK & REG__##v6) | \
+ (R_VECT_MASK_SET__dma4__##f7##__MASK & REG__##v7) | \
+ (R_VECT_MASK_SET__dma3__##f8##__MASK & REG__##v8) | \
+ (R_VECT_MASK_SET__dma2__##f9##__MASK & REG__##v9) | \
+ (R_VECT_MASK_SET__dma1__##f10##__MASK & REG__##v10) | \
+ (R_VECT_MASK_SET__dma0__##f11##__MASK & REG__##v11) | \
+ (R_VECT_MASK_SET__ext_dma1__##f12##__MASK & REG__##v12) | \
+ (R_VECT_MASK_SET__ext_dma0__##f13##__MASK & REG__##v13) | \
+ (R_VECT_MASK_SET__pa__##f14##__MASK & REG__##v14) | \
+ (R_VECT_MASK_SET__irq_intnr__##f15##__MASK & REG__##v15) | \
+ (R_VECT_MASK_SET__sw__##f16##__MASK & REG__##v16) | \
+ (R_VECT_MASK_SET__serial__##f17##__MASK & REG__##v17) | \
+ (R_VECT_MASK_SET__snmp__##f18##__MASK & REG__##v18) | \
+ (R_VECT_MASK_SET__network__##f19##__MASK & REG__##v19) | \
+ (R_VECT_MASK_SET__scsi1__##f20##__MASK & REG__##v20) | \
+ (R_VECT_MASK_SET__scsi0__##f21##__MASK & REG__##v21) | \
+ (R_VECT_MASK_SET__timer1__##f22##__MASK & REG__##v22) | \
+ (R_VECT_MASK_SET__timer0__##f23##__MASK & REG__##v23) | \
+ (R_VECT_MASK_SET__nmi__##f24##__MASK & REG__##v24) | \
+ (R_VECT_MASK_SET__some__##f25##__MASK & REG__##v25) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_VECT_MASK_SET
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_VECT_MASK_SET.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_VECT_MASK_SET(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_VECT_MASK_SET__usb__##f1##__VAL(R_VECT_MASK_SET_, usb_, v1) << R_VECT_MASK_SET__usb__BITNR) | \
+ (R_VECT_MASK_SET__dma9__##f2##__VAL(R_VECT_MASK_SET_, dma9_, v2) << R_VECT_MASK_SET__dma9__BITNR) | \
+ (R_VECT_MASK_SET__dma8__##f3##__VAL(R_VECT_MASK_SET_, dma8_, v3) << R_VECT_MASK_SET__dma8__BITNR) | \
+ (R_VECT_MASK_SET__dma7__##f4##__VAL(R_VECT_MASK_SET_, dma7_, v4) << R_VECT_MASK_SET__dma7__BITNR) | \
+ (R_VECT_MASK_SET__dma6__##f5##__VAL(R_VECT_MASK_SET_, dma6_, v5) << R_VECT_MASK_SET__dma6__BITNR) | \
+ (R_VECT_MASK_SET__dma5__##f6##__VAL(R_VECT_MASK_SET_, dma5_, v6) << R_VECT_MASK_SET__dma5__BITNR) | \
+ (R_VECT_MASK_SET__dma4__##f7##__VAL(R_VECT_MASK_SET_, dma4_, v7) << R_VECT_MASK_SET__dma4__BITNR) | \
+ (R_VECT_MASK_SET__dma3__##f8##__VAL(R_VECT_MASK_SET_, dma3_, v8) << R_VECT_MASK_SET__dma3__BITNR) | \
+ (R_VECT_MASK_SET__dma2__##f9##__VAL(R_VECT_MASK_SET_, dma2_, v9) << R_VECT_MASK_SET__dma2__BITNR) | \
+ (R_VECT_MASK_SET__dma1__##f10##__VAL(R_VECT_MASK_SET_, dma1_, v10) << R_VECT_MASK_SET__dma1__BITNR) | \
+ (R_VECT_MASK_SET__dma0__##f11##__VAL(R_VECT_MASK_SET_, dma0_, v11) << R_VECT_MASK_SET__dma0__BITNR) | \
+ (R_VECT_MASK_SET__ext_dma1__##f12##__VAL(R_VECT_MASK_SET_, ext_dma1_, v12) << R_VECT_MASK_SET__ext_dma1__BITNR) | \
+ (R_VECT_MASK_SET__ext_dma0__##f13##__VAL(R_VECT_MASK_SET_, ext_dma0_, v13) << R_VECT_MASK_SET__ext_dma0__BITNR) | \
+ (R_VECT_MASK_SET__pa__##f14##__VAL(R_VECT_MASK_SET_, pa_, v14) << R_VECT_MASK_SET__pa__BITNR) | \
+ (R_VECT_MASK_SET__irq_intnr__##f15##__VAL(R_VECT_MASK_SET_, irq_intnr_, v15) << R_VECT_MASK_SET__irq_intnr__BITNR) | \
+ (R_VECT_MASK_SET__sw__##f16##__VAL(R_VECT_MASK_SET_, sw_, v16) << R_VECT_MASK_SET__sw__BITNR) | \
+ (R_VECT_MASK_SET__serial__##f17##__VAL(R_VECT_MASK_SET_, serial_, v17) << R_VECT_MASK_SET__serial__BITNR) | \
+ (R_VECT_MASK_SET__snmp__##f18##__VAL(R_VECT_MASK_SET_, snmp_, v18) << R_VECT_MASK_SET__snmp__BITNR) | \
+ (R_VECT_MASK_SET__network__##f19##__VAL(R_VECT_MASK_SET_, network_, v19) << R_VECT_MASK_SET__network__BITNR) | \
+ (R_VECT_MASK_SET__scsi1__##f20##__VAL(R_VECT_MASK_SET_, scsi1_, v20) << R_VECT_MASK_SET__scsi1__BITNR) | \
+ (R_VECT_MASK_SET__scsi0__##f21##__VAL(R_VECT_MASK_SET_, scsi0_, v21) << R_VECT_MASK_SET__scsi0__BITNR) | \
+ (R_VECT_MASK_SET__timer1__##f22##__VAL(R_VECT_MASK_SET_, timer1_, v22) << R_VECT_MASK_SET__timer1__BITNR) | \
+ (R_VECT_MASK_SET__timer0__##f23##__VAL(R_VECT_MASK_SET_, timer0_, v23) << R_VECT_MASK_SET__timer0__BITNR) | \
+ (R_VECT_MASK_SET__nmi__##f24##__VAL(R_VECT_MASK_SET_, nmi_, v24) << R_VECT_MASK_SET__nmi__BITNR) | \
+ (R_VECT_MASK_SET__some__##f25##__VAL(R_VECT_MASK_SET_, some_, v25) << R_VECT_MASK_SET__some__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_VECT_MASK_SET_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_VECT_MASK_SET.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_VECT_MASK_SET_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \
+ (R_VECT_MASK_SET__usb__##f1_##_VAL(R_VECT_MASK_SET_, usb_, v1) << R_VECT_MASK_SET__usb__BITNR) | \
+ (R_VECT_MASK_SET__dma9__##f2_##_VAL(R_VECT_MASK_SET_, dma9_, v2) << R_VECT_MASK_SET__dma9__BITNR) | \
+ (R_VECT_MASK_SET__dma8__##f3_##_VAL(R_VECT_MASK_SET_, dma8_, v3) << R_VECT_MASK_SET__dma8__BITNR) | \
+ (R_VECT_MASK_SET__dma7__##f4_##_VAL(R_VECT_MASK_SET_, dma7_, v4) << R_VECT_MASK_SET__dma7__BITNR) | \
+ (R_VECT_MASK_SET__dma6__##f5_##_VAL(R_VECT_MASK_SET_, dma6_, v5) << R_VECT_MASK_SET__dma6__BITNR) | \
+ (R_VECT_MASK_SET__dma5__##f6_##_VAL(R_VECT_MASK_SET_, dma5_, v6) << R_VECT_MASK_SET__dma5__BITNR) | \
+ (R_VECT_MASK_SET__dma4__##f7_##_VAL(R_VECT_MASK_SET_, dma4_, v7) << R_VECT_MASK_SET__dma4__BITNR) | \
+ (R_VECT_MASK_SET__dma3__##f8_##_VAL(R_VECT_MASK_SET_, dma3_, v8) << R_VECT_MASK_SET__dma3__BITNR) | \
+ (R_VECT_MASK_SET__dma2__##f9_##_VAL(R_VECT_MASK_SET_, dma2_, v9) << R_VECT_MASK_SET__dma2__BITNR) | \
+ (R_VECT_MASK_SET__dma1__##f10_##_VAL(R_VECT_MASK_SET_, dma1_, v10) << R_VECT_MASK_SET__dma1__BITNR) | \
+ (R_VECT_MASK_SET__dma0__##f11_##_VAL(R_VECT_MASK_SET_, dma0_, v11) << R_VECT_MASK_SET__dma0__BITNR) | \
+ (R_VECT_MASK_SET__ext_dma1__##f12_##_VAL(R_VECT_MASK_SET_, ext_dma1_, v12) << R_VECT_MASK_SET__ext_dma1__BITNR) | \
+ (R_VECT_MASK_SET__ext_dma0__##f13_##_VAL(R_VECT_MASK_SET_, ext_dma0_, v13) << R_VECT_MASK_SET__ext_dma0__BITNR) | \
+ (R_VECT_MASK_SET__pa__##f14_##_VAL(R_VECT_MASK_SET_, pa_, v14) << R_VECT_MASK_SET__pa__BITNR) | \
+ (R_VECT_MASK_SET__irq_intnr__##f15_##_VAL(R_VECT_MASK_SET_, irq_intnr_, v15) << R_VECT_MASK_SET__irq_intnr__BITNR) | \
+ (R_VECT_MASK_SET__sw__##f16_##_VAL(R_VECT_MASK_SET_, sw_, v16) << R_VECT_MASK_SET__sw__BITNR) | \
+ (R_VECT_MASK_SET__serial__##f17_##_VAL(R_VECT_MASK_SET_, serial_, v17) << R_VECT_MASK_SET__serial__BITNR) | \
+ (R_VECT_MASK_SET__snmp__##f18_##_VAL(R_VECT_MASK_SET_, snmp_, v18) << R_VECT_MASK_SET__snmp__BITNR) | \
+ (R_VECT_MASK_SET__network__##f19_##_VAL(R_VECT_MASK_SET_, network_, v19) << R_VECT_MASK_SET__network__BITNR) | \
+ (R_VECT_MASK_SET__scsi1__##f20_##_VAL(R_VECT_MASK_SET_, scsi1_, v20) << R_VECT_MASK_SET__scsi1__BITNR) | \
+ (R_VECT_MASK_SET__scsi0__##f21_##_VAL(R_VECT_MASK_SET_, scsi0_, v21) << R_VECT_MASK_SET__scsi0__BITNR) | \
+ (R_VECT_MASK_SET__timer1__##f22_##_VAL(R_VECT_MASK_SET_, timer1_, v22) << R_VECT_MASK_SET__timer1__BITNR) | \
+ (R_VECT_MASK_SET__timer0__##f23_##_VAL(R_VECT_MASK_SET_, timer0_, v23) << R_VECT_MASK_SET__timer0__BITNR) | \
+ (R_VECT_MASK_SET__nmi__##f24_##_VAL(R_VECT_MASK_SET_, nmi_, v24) << R_VECT_MASK_SET__nmi__BITNR) | \
+ (R_VECT_MASK_SET__some__##f25_##_VAL(R_VECT_MASK_SET_, some_, v25) << R_VECT_MASK_SET__some__BITNR) \
+)
+
+#endif
+
+/*
+ * R_VECT_READ
+ * - type: RO
+ * - addr: 0xb00000dc
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+/* No REG_SET__register-name for read only registers. */
+
+/* No REG_SET__register-name__SHADOW for read only and read write registers. */
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_VECT_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_VECT_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_VECT_READ__usb__##f1##__MASK & REG__##v1) | \
+ (R_VECT_READ__dma9__##f2##__MASK & REG__##v2) | \
+ (R_VECT_READ__dma8__##f3##__MASK & REG__##v3) | \
+ (R_VECT_READ__dma7__##f4##__MASK & REG__##v4) | \
+ (R_VECT_READ__dma6__##f5##__MASK & REG__##v5) | \
+ (R_VECT_READ__dma5__##f6##__MASK & REG__##v6) | \
+ (R_VECT_READ__dma4__##f7##__MASK & REG__##v7) | \
+ (R_VECT_READ__dma3__##f8##__MASK & REG__##v8) | \
+ (R_VECT_READ__dma2__##f9##__MASK & REG__##v9) | \
+ (R_VECT_READ__dma1__##f10##__MASK & REG__##v10) | \
+ (R_VECT_READ__dma0__##f11##__MASK & REG__##v11) | \
+ (R_VECT_READ__ext_dma1__##f12##__MASK & REG__##v12) | \
+ (R_VECT_READ__ext_dma0__##f13##__MASK & REG__##v13) | \
+ (R_VECT_READ__pa__##f14##__MASK & REG__##v14) | \
+ (R_VECT_READ__irq_intnr__##f15##__MASK & REG__##v15) | \
+ (R_VECT_READ__sw__##f16##__MASK & REG__##v16) | \
+ (R_VECT_READ__serial__##f17##__MASK & REG__##v17) | \
+ (R_VECT_READ__snmp__##f18##__MASK & REG__##v18) | \
+ (R_VECT_READ__network__##f19##__MASK & REG__##v19) | \
+ (R_VECT_READ__scsi1__##f20##__MASK & REG__##v20) | \
+ (R_VECT_READ__scsi0__##f21##__MASK & REG__##v21) | \
+ (R_VECT_READ__timer1__##f22##__MASK & REG__##v22) | \
+ (R_VECT_READ__timer0__##f23##__MASK & REG__##v23) | \
+ (R_VECT_READ__nmi__##f24##__MASK & REG__##v24) | \
+ (R_VECT_READ__some__##f25##__MASK & REG__##v25) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_VECT_READ
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_VECT_READ.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_VECT_READ(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12,f13,v13,f14,v14,f15,v15,f16,v16,f17,v17,f18,v18,f19,v19,f20,v20,f21,v21,f22,v22,f23,v23,f24,v24,f25,v25) ( \
+ (R_VECT_READ__usb__##f1##__VAL(R_VECT_READ_, usb_, v1) << R_VECT_READ__usb__BITNR) | \
+ (R_VECT_READ__dma9__##f2##__VAL(R_VECT_READ_, dma9_, v2) << R_VECT_READ__dma9__BITNR) | \
+ (R_VECT_READ__dma8__##f3##__VAL(R_VECT_READ_, dma8_, v3) << R_VECT_READ__dma8__BITNR) | \
+ (R_VECT_READ__dma7__##f4##__VAL(R_VECT_READ_, dma7_, v4) << R_VECT_READ__dma7__BITNR) | \
+ (R_VECT_READ__dma6__##f5##__VAL(R_VECT_READ_, dma6_, v5) << R_VECT_READ__dma6__BITNR) | \
+ (R_VECT_READ__dma5__##f6##__VAL(R_VECT_READ_, dma5_, v6) << R_VECT_READ__dma5__BITNR) | \
+ (R_VECT_READ__dma4__##f7##__VAL(R_VECT_READ_, dma4_, v7) << R_VECT_READ__dma4__BITNR) | \
+ (R_VECT_READ__dma3__##f8##__VAL(R_VECT_READ_, dma3_, v8) << R_VECT_READ__dma3__BITNR) | \
+ (R_VECT_READ__dma2__##f9##__VAL(R_VECT_READ_, dma2_, v9) << R_VECT_READ__dma2__BITNR) | \
+ (R_VECT_READ__dma1__##f10##__VAL(R_VECT_READ_, dma1_, v10) << R_VECT_READ__dma1__BITNR) | \
+ (R_VECT_READ__dma0__##f11##__VAL(R_VECT_READ_, dma0_, v11) << R_VECT_READ__dma0__BITNR) | \
+ (R_VECT_READ__ext_dma1__##f12##__VAL(R_VECT_READ_, ext_dma1_, v12) << R_VECT_READ__ext_dma1__BITNR) | \
+ (R_VECT_READ__ext_dma0__##f13##__VAL(R_VECT_READ_, ext_dma0_, v13) << R_VECT_READ__ext_dma0__BITNR) | \
+ (R_VECT_READ__pa__##f14##__VAL(R_VECT_READ_, pa_, v14) << R_VECT_READ__pa__BITNR) | \
+ (R_VECT_READ__irq_intnr__##f15##__VAL(R_VECT_READ_, irq_intnr_, v15) << R_VECT_READ__irq_intnr__BITNR) | \
+ (R_VECT_READ__sw__##f16##__VAL(R_VECT_READ_, sw_, v16) << R_VECT_READ__sw__BITNR) | \
+ (R_VECT_READ__serial__##f17##__VAL(R_VECT_READ_, serial_, v17) << R_VECT_READ__serial__BITNR) | \
+ (R_VECT_READ__snmp__##f18##__VAL(R_VECT_READ_, snmp_, v18) << R_VECT_READ__snmp__BITNR) | \
+ (R_VECT_READ__network__##f19##__VAL(R_VECT_READ_, network_, v19) << R_VECT_READ__network__BITNR) | \
+ (R_VECT_READ__scsi1__##f20##__VAL(R_VECT_READ_, scsi1_, v20) << R_VECT_READ__scsi1__BITNR) | \
+ (R_VECT_READ__scsi0__##f21##__VAL(R_VECT_READ_, scsi0_, v21) << R_VECT_READ__scsi0__BITNR) | \
+ (R_VECT_READ__timer1__##f22##__VAL(R_VECT_READ_, timer1_, v22) << R_VECT_READ__timer1__BITNR) | \
+ (R_VECT_READ__timer0__##f23##__VAL(R_VECT_READ_, timer0_, v23) << R_VECT_READ__timer0__BITNR) | \
+ (R_VECT_READ__nmi__##f24##__VAL(R_VECT_READ_, nmi_, v24) << R_VECT_READ__nmi__BITNR) | \
+ (R_VECT_READ__some__##f25##__VAL(R_VECT_READ_, some_, v25) << R_VECT_READ__some__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_VECT_READ_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_VECT_READ.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_VECT_READ_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12,f13_,v13,f14_,v14,f15_,v15,f16_,v16,f17_,v17,f18_,v18,f19_,v19,f20_,v20,f21_,v21,f22_,v22,f23_,v23,f24_,v24,f25_,v25) ( \
+ (R_VECT_READ__usb__##f1_##_VAL(R_VECT_READ_, usb_, v1) << R_VECT_READ__usb__BITNR) | \
+ (R_VECT_READ__dma9__##f2_##_VAL(R_VECT_READ_, dma9_, v2) << R_VECT_READ__dma9__BITNR) | \
+ (R_VECT_READ__dma8__##f3_##_VAL(R_VECT_READ_, dma8_, v3) << R_VECT_READ__dma8__BITNR) | \
+ (R_VECT_READ__dma7__##f4_##_VAL(R_VECT_READ_, dma7_, v4) << R_VECT_READ__dma7__BITNR) | \
+ (R_VECT_READ__dma6__##f5_##_VAL(R_VECT_READ_, dma6_, v5) << R_VECT_READ__dma6__BITNR) | \
+ (R_VECT_READ__dma5__##f6_##_VAL(R_VECT_READ_, dma5_, v6) << R_VECT_READ__dma5__BITNR) | \
+ (R_VECT_READ__dma4__##f7_##_VAL(R_VECT_READ_, dma4_, v7) << R_VECT_READ__dma4__BITNR) | \
+ (R_VECT_READ__dma3__##f8_##_VAL(R_VECT_READ_, dma3_, v8) << R_VECT_READ__dma3__BITNR) | \
+ (R_VECT_READ__dma2__##f9_##_VAL(R_VECT_READ_, dma2_, v9) << R_VECT_READ__dma2__BITNR) | \
+ (R_VECT_READ__dma1__##f10_##_VAL(R_VECT_READ_, dma1_, v10) << R_VECT_READ__dma1__BITNR) | \
+ (R_VECT_READ__dma0__##f11_##_VAL(R_VECT_READ_, dma0_, v11) << R_VECT_READ__dma0__BITNR) | \
+ (R_VECT_READ__ext_dma1__##f12_##_VAL(R_VECT_READ_, ext_dma1_, v12) << R_VECT_READ__ext_dma1__BITNR) | \
+ (R_VECT_READ__ext_dma0__##f13_##_VAL(R_VECT_READ_, ext_dma0_, v13) << R_VECT_READ__ext_dma0__BITNR) | \
+ (R_VECT_READ__pa__##f14_##_VAL(R_VECT_READ_, pa_, v14) << R_VECT_READ__pa__BITNR) | \
+ (R_VECT_READ__irq_intnr__##f15_##_VAL(R_VECT_READ_, irq_intnr_, v15) << R_VECT_READ__irq_intnr__BITNR) | \
+ (R_VECT_READ__sw__##f16_##_VAL(R_VECT_READ_, sw_, v16) << R_VECT_READ__sw__BITNR) | \
+ (R_VECT_READ__serial__##f17_##_VAL(R_VECT_READ_, serial_, v17) << R_VECT_READ__serial__BITNR) | \
+ (R_VECT_READ__snmp__##f18_##_VAL(R_VECT_READ_, snmp_, v18) << R_VECT_READ__snmp__BITNR) | \
+ (R_VECT_READ__network__##f19_##_VAL(R_VECT_READ_, network_, v19) << R_VECT_READ__network__BITNR) | \
+ (R_VECT_READ__scsi1__##f20_##_VAL(R_VECT_READ_, scsi1_, v20) << R_VECT_READ__scsi1__BITNR) | \
+ (R_VECT_READ__scsi0__##f21_##_VAL(R_VECT_READ_, scsi0_, v21) << R_VECT_READ__scsi0__BITNR) | \
+ (R_VECT_READ__timer1__##f22_##_VAL(R_VECT_READ_, timer1_, v22) << R_VECT_READ__timer1__BITNR) | \
+ (R_VECT_READ__timer0__##f23_##_VAL(R_VECT_READ_, timer0_, v23) << R_VECT_READ__timer0__BITNR) | \
+ (R_VECT_READ__nmi__##f24_##_VAL(R_VECT_READ_, nmi_, v24) << R_VECT_READ__nmi__BITNR) | \
+ (R_VECT_READ__some__##f25_##_VAL(R_VECT_READ_, some_, v25) << R_VECT_READ__some__BITNR) \
+)
+
+#endif
+
+/*
+ * R_WAITSTATES
+ * - type: WO
+ * - addr: 0xb0000000
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_WAITSTATES
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_WAITSTATES.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_WAITSTATES.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_WAITSTATES(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ *R_WAITSTATES__SADDR = ( \
+ REG_INITIATED(R_WAITSTATES_) \
+ REG_VAL__R_WAITSTATES_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \
+ ), \
+ R_WAITSTATES__WRITE(R_WAITSTATES__ADDR, *R_WAITSTATES__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_WAITSTATES__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_WAITSTATES.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_WAITSTATES.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_WAITSTATES__SHADOW(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ *R_WAITSTATES__SADDR = ( \
+ REG_INITIATED(R_WAITSTATES_) \
+ REG_VAL__R_WAITSTATES_(f1##_,v1,f2##_,v2,f3##_,v3,f4##_,v4,f5##_,v5,f6##_,v6,f7##_,v7,f8##_,v8,f9##_,v9,f10##_,v10,f11##_,v11,f12##_,v12) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_WAITSTATES
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_WAITSTATES(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_WAITSTATES__pcs4_7_zw__##f1##__MASK & REG__##v1) | \
+ (R_WAITSTATES__pcs4_7_ew__##f2##__MASK & REG__##v2) | \
+ (R_WAITSTATES__pcs4_7_lw__##f3##__MASK & REG__##v3) | \
+ (R_WAITSTATES__pcs0_3_zw__##f4##__MASK & REG__##v4) | \
+ (R_WAITSTATES__pcs0_3_ew__##f5##__MASK & REG__##v5) | \
+ (R_WAITSTATES__pcs0_3_lw__##f6##__MASK & REG__##v6) | \
+ (R_WAITSTATES__sram_zw__##f7##__MASK & REG__##v7) | \
+ (R_WAITSTATES__sram_ew__##f8##__MASK & REG__##v8) | \
+ (R_WAITSTATES__sram_lw__##f9##__MASK & REG__##v9) | \
+ (R_WAITSTATES__flash_zw__##f10##__MASK & REG__##v10) | \
+ (R_WAITSTATES__flash_ew__##f11##__MASK & REG__##v11) | \
+ (R_WAITSTATES__flash_lw__##f12##__MASK & REG__##v12) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_WAITSTATES
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_WAITSTATES.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_WAITSTATES(f1,v1,f2,v2,f3,v3,f4,v4,f5,v5,f6,v6,f7,v7,f8,v8,f9,v9,f10,v10,f11,v11,f12,v12) ( \
+ (R_WAITSTATES__pcs4_7_zw__##f1##__VAL(R_WAITSTATES_, pcs4_7_zw_, v1) << R_WAITSTATES__pcs4_7_zw__BITNR) | \
+ (R_WAITSTATES__pcs4_7_ew__##f2##__VAL(R_WAITSTATES_, pcs4_7_ew_, v2) << R_WAITSTATES__pcs4_7_ew__BITNR) | \
+ (R_WAITSTATES__pcs4_7_lw__##f3##__VAL(R_WAITSTATES_, pcs4_7_lw_, v3) << R_WAITSTATES__pcs4_7_lw__BITNR) | \
+ (R_WAITSTATES__pcs0_3_zw__##f4##__VAL(R_WAITSTATES_, pcs0_3_zw_, v4) << R_WAITSTATES__pcs0_3_zw__BITNR) | \
+ (R_WAITSTATES__pcs0_3_ew__##f5##__VAL(R_WAITSTATES_, pcs0_3_ew_, v5) << R_WAITSTATES__pcs0_3_ew__BITNR) | \
+ (R_WAITSTATES__pcs0_3_lw__##f6##__VAL(R_WAITSTATES_, pcs0_3_lw_, v6) << R_WAITSTATES__pcs0_3_lw__BITNR) | \
+ (R_WAITSTATES__sram_zw__##f7##__VAL(R_WAITSTATES_, sram_zw_, v7) << R_WAITSTATES__sram_zw__BITNR) | \
+ (R_WAITSTATES__sram_ew__##f8##__VAL(R_WAITSTATES_, sram_ew_, v8) << R_WAITSTATES__sram_ew__BITNR) | \
+ (R_WAITSTATES__sram_lw__##f9##__VAL(R_WAITSTATES_, sram_lw_, v9) << R_WAITSTATES__sram_lw__BITNR) | \
+ (R_WAITSTATES__flash_zw__##f10##__VAL(R_WAITSTATES_, flash_zw_, v10) << R_WAITSTATES__flash_zw__BITNR) | \
+ (R_WAITSTATES__flash_ew__##f11##__VAL(R_WAITSTATES_, flash_ew_, v11) << R_WAITSTATES__flash_ew__BITNR) | \
+ (R_WAITSTATES__flash_lw__##f12##__VAL(R_WAITSTATES_, flash_lw_, v12) << R_WAITSTATES__flash_lw__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_WAITSTATES_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_WAITSTATES.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_WAITSTATES_(f1_,v1,f2_,v2,f3_,v3,f4_,v4,f5_,v5,f6_,v6,f7_,v7,f8_,v8,f9_,v9,f10_,v10,f11_,v11,f12_,v12) ( \
+ (R_WAITSTATES__pcs4_7_zw__##f1_##_VAL(R_WAITSTATES_, pcs4_7_zw_, v1) << R_WAITSTATES__pcs4_7_zw__BITNR) | \
+ (R_WAITSTATES__pcs4_7_ew__##f2_##_VAL(R_WAITSTATES_, pcs4_7_ew_, v2) << R_WAITSTATES__pcs4_7_ew__BITNR) | \
+ (R_WAITSTATES__pcs4_7_lw__##f3_##_VAL(R_WAITSTATES_, pcs4_7_lw_, v3) << R_WAITSTATES__pcs4_7_lw__BITNR) | \
+ (R_WAITSTATES__pcs0_3_zw__##f4_##_VAL(R_WAITSTATES_, pcs0_3_zw_, v4) << R_WAITSTATES__pcs0_3_zw__BITNR) | \
+ (R_WAITSTATES__pcs0_3_ew__##f5_##_VAL(R_WAITSTATES_, pcs0_3_ew_, v5) << R_WAITSTATES__pcs0_3_ew__BITNR) | \
+ (R_WAITSTATES__pcs0_3_lw__##f6_##_VAL(R_WAITSTATES_, pcs0_3_lw_, v6) << R_WAITSTATES__pcs0_3_lw__BITNR) | \
+ (R_WAITSTATES__sram_zw__##f7_##_VAL(R_WAITSTATES_, sram_zw_, v7) << R_WAITSTATES__sram_zw__BITNR) | \
+ (R_WAITSTATES__sram_ew__##f8_##_VAL(R_WAITSTATES_, sram_ew_, v8) << R_WAITSTATES__sram_ew__BITNR) | \
+ (R_WAITSTATES__sram_lw__##f9_##_VAL(R_WAITSTATES_, sram_lw_, v9) << R_WAITSTATES__sram_lw__BITNR) | \
+ (R_WAITSTATES__flash_zw__##f10_##_VAL(R_WAITSTATES_, flash_zw_, v10) << R_WAITSTATES__flash_zw__BITNR) | \
+ (R_WAITSTATES__flash_ew__##f11_##_VAL(R_WAITSTATES_, flash_ew_, v11) << R_WAITSTATES__flash_ew__BITNR) | \
+ (R_WAITSTATES__flash_lw__##f12_##_VAL(R_WAITSTATES_, flash_lw_, v12) << R_WAITSTATES__flash_lw__BITNR) \
+)
+
+#endif
+
+/*
+ * R_WATCHDOG
+ * - type: WO
+ * - addr: 0xb0000024
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_WATCHDOG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_WATCHDOG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in register
+*# R_WATCHDOG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_WATCHDOG(f1,v1,f2,v2) ( \
+ *R_WATCHDOG__SADDR = ( \
+ REG_INITIATED(R_WATCHDOG_) \
+ REG_VAL__R_WATCHDOG_(f1##_,v1,f2##_,v2) \
+ ), \
+ R_WATCHDOG__WRITE(R_WATCHDOG__ADDR, *R_WATCHDOG__SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET__R_WATCHDOG__SHADOW
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Integer value to write to field N.
+*#
+*# RETURNS : integer value written to register R_WATCHDOG.
+*#
+*# SIDE EFFECTS: REG_INITIATED evaluated.
+*#
+*# DESCRIPTION : Write value of vn parameters to fields fn in the
+*# shadow register for R_WATCHDOG.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_SET__R_WATCHDOG__SHADOW(f1,v1,f2,v2) ( \
+ *R_WATCHDOG__SADDR = ( \
+ REG_INITIATED(R_WATCHDOG_) \
+ REG_VAL__R_WATCHDOG_(f1##_,v1,f2##_,v2) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_MASK__R_WATCHDOG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : REG__on, or REG__off
+*#
+*# RETURNS : Integer value with 1s in all on-fields,
+*# and 0s in all off-fields.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Create a mask with 1s in all fields with vn == REG__on,
+*# and 0s in fields with vn == REG_off.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Only put ## where necessary to stop
+*# premature macro evaluation.
+*#**********************************************************************/
+
+#define REG_MASK__R_WATCHDOG(f1,v1,f2,v2) ( \
+ (R_WATCHDOG__key__##f1##__MASK & REG__##v1) | \
+ (R_WATCHDOG__enable__##f2##__MASK & REG__##v2) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_WATCHDOG
+*#
+*# PARAMETERS : fn : Name of field N.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_WATCHDOG.
+*# Parameters vn are checked for validity.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson To stop premature evaluation, append
+*# _ to fn parameters when passing
+*# on to other macros.
+*#**********************************************************************/
+
+#define REG_VAL__R_WATCHDOG(f1,v1,f2,v2) ( \
+ (R_WATCHDOG__key__##f1##__VAL(R_WATCHDOG_, key_, v1) << R_WATCHDOG__key__BITNR) | \
+ (R_WATCHDOG__enable__##f2##__VAL(R_WATCHDOG_, enable_, v2) << R_WATCHDOG__enable__BITNR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL__R_WATCHDOG_
+*#
+*# PARAMETERS : fn_ : Name of field N, with "_" appended.
+*# vn : Value in field N.
+*#
+*# RETURNS : Integer value.
+*#
+*# SIDE EFFECTS: REG_VERROR may be evaluated.
+*#
+*# DESCRIPTION : Create a value by combining the vn parameters according
+*# to the fields in register R_WATCHDOG.
+*# Parameters vn are checked for validity.
+*# INTERNAL: for use by other macros in this file only.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Sep 30 2002 Hans-Peter Nilsson Initial version
+*#**********************************************************************/
+
+#define REG_VAL__R_WATCHDOG_(f1_,v1,f2_,v2) ( \
+ (R_WATCHDOG__key__##f1_##_VAL(R_WATCHDOG_, key_, v1) << R_WATCHDOG__key__BITNR) | \
+ (R_WATCHDOG__enable__##f2_##_VAL(R_WATCHDOG_, enable_, v2) << R_WATCHDOG__enable__BITNR) \
+)
+
+#endif
+
+#endif
diff --git a/package/etrax-tools/src/e100boot/cbl/src/hwregs_def.h b/package/etrax-tools/src/e100boot/cbl/src/hwregs_def.h
new file mode 100644
index 000000000..75077cfa8
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/hwregs_def.h
@@ -0,0 +1,5435 @@
+/*!**********************************************************************
+*!
+*! FILE NAME: hwregs_def.h
+*!
+*! DESCRIPTION: Template file for register field default values used by
+*! the init_shadow() function defined in hwregs.c
+*! For each field in each register select a default value
+*! from the listed set of valid values.
+*! Only write only registers need default values.
+*! This file is included in hwregs.h
+*!
+*! FUNCTIONS: none
+*!
+*! NOTE: This file is automatically generated, do _not_ edit.
+*! Created: Thu Oct 3 01:21:27 2002
+*! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp
+*! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168
+*! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3
+*!
+*! NOTE: There are default constants for all write only registers described
+*! in /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd.
+*! Since one physical register may have several logical names you
+*! only need default constants for those registers that are
+*! initiated in init_shadow(). This is done by the
+*! 'USE_GROUP__group-name' macros in this file.
+*!
+*! As an example, in Etrax100 the following logical registers are
+*! all the same physical register at address 0xb0000044:
+*!
+*! R_ATA_CONFIG
+*! R_PAR0_CONFIG
+*! R_SCSI0_CTRL
+*! R_SHARED_RAM_ADDR
+*!
+*!----------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! Apr 01 1998 Jan Bengtsson Initial version
+*!----------------------------------------------------------------------
+*!
+*! (C) Copyright 1998, Axis Communications AB, LUND, SWEDEN
+*!
+*!**********************************************************************/
+/* %Z% %M% %I% %G% */
+
+#ifndef __HWREGS_DEF_H__
+#define __HWREGS_DEF_H__
+
+/********************** INCLUDE FILES SECTION **************************/
+
+/********************** CONSTANT AND MACRO SECTION *********************/
+
+/*
+** To use shadow registers for a register_group, define the following
+** macros to TRUE in a project specific file.
+*/
+
+#ifndef USE_GROUP__Serial_port_registers
+#define USE_GROUP__Serial_port_registers 1
+#endif
+
+#ifndef USE_GROUP__ATA_interface_registers
+#define USE_GROUP__ATA_interface_registers 1
+#endif
+
+#ifndef USE_GROUP__Bus_interface_configuration_registers
+#define USE_GROUP__Bus_interface_configuration_registers 1
+#endif
+
+#ifndef USE_GROUP__Timer_registers
+#define USE_GROUP__Timer_registers 1
+#endif
+
+#ifndef USE_GROUP__DMA_registers
+#define USE_GROUP__DMA_registers 1
+#endif
+
+#ifndef USE_GROUP__External_DMA_registers
+#define USE_GROUP__External_DMA_registers 1
+#endif
+
+#ifndef USE_GROUP__General_config_registers
+#define USE_GROUP__General_config_registers 1
+#endif
+
+#ifndef USE_GROUP__Interrupt_mask_and_status_registers
+#define USE_GROUP__Interrupt_mask_and_status_registers 1
+#endif
+
+#ifndef USE_GROUP__MMU_registers
+#define USE_GROUP__MMU_registers 1
+#endif
+
+#ifndef USE_GROUP__Network_interface_registers
+#define USE_GROUP__Network_interface_registers 1
+#endif
+
+#ifndef USE_GROUP__Parallel_printer_port_registers
+#define USE_GROUP__Parallel_printer_port_registers 1
+#endif
+
+#ifndef USE_GROUP__General_port_configuration_registers
+#define USE_GROUP__General_port_configuration_registers 1
+#endif
+
+#ifndef USE_GROUP__SCSI_registers
+#define USE_GROUP__SCSI_registers 1
+#endif
+
+#ifndef USE_GROUP__Shared_RAM_interface_registers
+#define USE_GROUP__Shared_RAM_interface_registers 1
+#endif
+
+#ifndef USE_GROUP__Test_mode_registers
+#define USE_GROUP__Test_mode_registers 1
+#endif
+
+#ifndef USE_GROUP__Syncrounous_serial_port_registers
+#define USE_GROUP__Syncrounous_serial_port_registers 1
+#endif
+
+#ifndef USE_GROUP__USB_interface_control_registers
+#define USE_GROUP__USB_interface_control_registers 1
+#endif
+
+
+/*
+** Default values for register R_ALT_SER_BAUDRATE
+*/
+
+/* timer normal extern prescale */
+#ifndef R_ALT_SER_BAUDRATE__ser3_tr__DEFAULT
+#define R_ALT_SER_BAUDRATE__ser3_tr__DEFAULT timer
+#endif
+
+/* timer normal extern prescale */
+#ifndef R_ALT_SER_BAUDRATE__ser3_rec__DEFAULT
+#define R_ALT_SER_BAUDRATE__ser3_rec__DEFAULT timer
+#endif
+
+/* timer normal extern prescale */
+#ifndef R_ALT_SER_BAUDRATE__ser2_tr__DEFAULT
+#define R_ALT_SER_BAUDRATE__ser2_tr__DEFAULT timer
+#endif
+
+/* timer normal extern prescale */
+#ifndef R_ALT_SER_BAUDRATE__ser2_rec__DEFAULT
+#define R_ALT_SER_BAUDRATE__ser2_rec__DEFAULT timer
+#endif
+
+/* timer normal extern prescale */
+#ifndef R_ALT_SER_BAUDRATE__ser1_tr__DEFAULT
+#define R_ALT_SER_BAUDRATE__ser1_tr__DEFAULT timer
+#endif
+
+/* timer normal extern prescale */
+#ifndef R_ALT_SER_BAUDRATE__ser1_rec__DEFAULT
+#define R_ALT_SER_BAUDRATE__ser1_rec__DEFAULT timer
+#endif
+
+/* timer normal extern prescale */
+#ifndef R_ALT_SER_BAUDRATE__ser0_tr__DEFAULT
+#define R_ALT_SER_BAUDRATE__ser0_tr__DEFAULT timer
+#endif
+
+/* timer normal extern prescale */
+#ifndef R_ALT_SER_BAUDRATE__ser0_rec__DEFAULT
+#define R_ALT_SER_BAUDRATE__ser0_rec__DEFAULT timer
+#endif
+
+/*
+** Default values for register R_ATA_CONFIG
+*/
+
+/* off on */
+#ifndef R_ATA_CONFIG__enable__DEFAULT
+#define R_ATA_CONFIG__enable__DEFAULT off
+#endif
+
+/* 0 - 31 */
+#ifndef R_ATA_CONFIG__dma_strobe__DEFAULT
+#define R_ATA_CONFIG__dma_strobe__DEFAULT 0
+#endif
+
+/* 0 - 31 */
+#ifndef R_ATA_CONFIG__dma_hold__DEFAULT
+#define R_ATA_CONFIG__dma_hold__DEFAULT 0
+#endif
+
+/* 0 - 31 */
+#ifndef R_ATA_CONFIG__pio_setup__DEFAULT
+#define R_ATA_CONFIG__pio_setup__DEFAULT 0
+#endif
+
+/* 0 - 31 */
+#ifndef R_ATA_CONFIG__pio_strobe__DEFAULT
+#define R_ATA_CONFIG__pio_strobe__DEFAULT 0
+#endif
+
+/* 0 - 31 */
+#ifndef R_ATA_CONFIG__pio_hold__DEFAULT
+#define R_ATA_CONFIG__pio_hold__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_ATA_CTRL_DATA
+*/
+
+/* 0 - 3 */
+#ifndef R_ATA_CTRL_DATA__sel__DEFAULT
+#define R_ATA_CTRL_DATA__sel__DEFAULT 0
+#endif
+
+/* inactive active */
+#ifndef R_ATA_CTRL_DATA__cs1__DEFAULT
+#define R_ATA_CTRL_DATA__cs1__DEFAULT inactive
+#endif
+
+/* inactive active */
+#ifndef R_ATA_CTRL_DATA__cs0__DEFAULT
+#define R_ATA_CTRL_DATA__cs0__DEFAULT inactive
+#endif
+
+/* 0 - 7 */
+#ifndef R_ATA_CTRL_DATA__addr__DEFAULT
+#define R_ATA_CTRL_DATA__addr__DEFAULT 0
+#endif
+
+/* write read */
+#ifndef R_ATA_CTRL_DATA__rw__DEFAULT
+#define R_ATA_CTRL_DATA__rw__DEFAULT write
+#endif
+
+/* dma register */
+#ifndef R_ATA_CTRL_DATA__src_dst__DEFAULT
+#define R_ATA_CTRL_DATA__src_dst__DEFAULT dma
+#endif
+
+/* pio dma */
+#ifndef R_ATA_CTRL_DATA__handsh__DEFAULT
+#define R_ATA_CTRL_DATA__handsh__DEFAULT pio
+#endif
+
+/* off on */
+#ifndef R_ATA_CTRL_DATA__multi__DEFAULT
+#define R_ATA_CTRL_DATA__multi__DEFAULT off
+#endif
+
+/* word byte */
+#ifndef R_ATA_CTRL_DATA__dma_size__DEFAULT
+#define R_ATA_CTRL_DATA__dma_size__DEFAULT word
+#endif
+
+/* 0 - 0xffff */
+#ifndef R_ATA_CTRL_DATA__data__DEFAULT
+#define R_ATA_CTRL_DATA__data__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_BUS_CONFIG
+*/
+
+/* bwe cwe */
+#ifndef R_BUS_CONFIG__sram_type__DEFAULT
+#define R_BUS_CONFIG__sram_type__DEFAULT bwe
+#endif
+
+/* burst32 burst16 */
+#ifndef R_BUS_CONFIG__dma_burst__DEFAULT
+#define R_BUS_CONFIG__dma_burst__DEFAULT burst32
+#endif
+
+/* ext norm */
+#ifndef R_BUS_CONFIG__pcs4_7_wr__DEFAULT
+#define R_BUS_CONFIG__pcs4_7_wr__DEFAULT ext
+#endif
+
+/* ext norm */
+#ifndef R_BUS_CONFIG__pcs0_3_wr__DEFAULT
+#define R_BUS_CONFIG__pcs0_3_wr__DEFAULT ext
+#endif
+
+/* ext norm */
+#ifndef R_BUS_CONFIG__sram_wr__DEFAULT
+#define R_BUS_CONFIG__sram_wr__DEFAULT ext
+#endif
+
+/* ext norm */
+#ifndef R_BUS_CONFIG__flash_wr__DEFAULT
+#define R_BUS_CONFIG__flash_wr__DEFAULT ext
+#endif
+
+/* bw16 bw32 */
+#ifndef R_BUS_CONFIG__pcs4_7_bw__DEFAULT
+#define R_BUS_CONFIG__pcs4_7_bw__DEFAULT bw16
+#endif
+
+/* bw16 bw32 */
+#ifndef R_BUS_CONFIG__pcs0_3_bw__DEFAULT
+#define R_BUS_CONFIG__pcs0_3_bw__DEFAULT bw16
+#endif
+
+/* bw16 bw32 */
+#ifndef R_BUS_CONFIG__sram_bw__DEFAULT
+#define R_BUS_CONFIG__sram_bw__DEFAULT bw16
+#endif
+
+/* bw16 bw32 */
+#ifndef R_BUS_CONFIG__flash_bw__DEFAULT
+#define R_BUS_CONFIG__flash_bw__DEFAULT bw16
+#endif
+
+/*
+** Default values for register R_CLOCK_PRESCALE
+*/
+
+/* 0 - 0xffff */
+#ifndef R_CLOCK_PRESCALE__ser_presc__DEFAULT
+#define R_CLOCK_PRESCALE__ser_presc__DEFAULT 0
+#endif
+
+/* 0 - 0xffff */
+#ifndef R_CLOCK_PRESCALE__tim_presc__DEFAULT
+#define R_CLOCK_PRESCALE__tim_presc__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_DMA_CH0_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH0_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH0_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH0_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH0_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH1_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH1_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH1_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH1_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH1_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH2_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH2_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH2_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH2_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH2_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH3_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH3_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH3_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH3_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH3_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH4_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH4_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH4_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH4_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH4_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH5_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH5_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH5_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH5_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH5_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH6_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH6_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH6_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH6_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH6_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH7_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH7_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH7_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH7_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH7_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH8_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH8_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH8_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH8_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH8_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH8_SUB0_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH8_SUB0_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH8_SUB1_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH8_SUB1_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH8_SUB2_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH8_SUB2_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH8_SUB3_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH8_SUB3_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DMA_CH9_CLR_INTR
+*/
+
+/* do dont */
+#ifndef R_DMA_CH9_CLR_INTR__clr_eop__DEFAULT
+#define R_DMA_CH9_CLR_INTR__clr_eop__DEFAULT do
+#endif
+
+/* do dont */
+#ifndef R_DMA_CH9_CLR_INTR__clr_descr__DEFAULT
+#define R_DMA_CH9_CLR_INTR__clr_descr__DEFAULT do
+#endif
+
+/*
+** Default values for register R_DRAM_CONFIG
+*/
+
+/* wmm norm */
+#ifndef R_DRAM_CONFIG__wmm1__DEFAULT
+#define R_DRAM_CONFIG__wmm1__DEFAULT wmm
+#endif
+
+/* wmm norm */
+#ifndef R_DRAM_CONFIG__wmm0__DEFAULT
+#define R_DRAM_CONFIG__wmm0__DEFAULT wmm
+#endif
+
+/* 0 - 7 */
+#ifndef R_DRAM_CONFIG__sh1__DEFAULT
+#define R_DRAM_CONFIG__sh1__DEFAULT 0
+#endif
+
+/* 0 - 7 */
+#ifndef R_DRAM_CONFIG__sh0__DEFAULT
+#define R_DRAM_CONFIG__sh0__DEFAULT 0
+#endif
+
+/* bw16 bw32 */
+#ifndef R_DRAM_CONFIG__w__DEFAULT
+#define R_DRAM_CONFIG__w__DEFAULT bw16
+#endif
+
+/* bank byte */
+#ifndef R_DRAM_CONFIG__c__DEFAULT
+#define R_DRAM_CONFIG__c__DEFAULT bank
+#endif
+
+/* edo fast */
+#ifndef R_DRAM_CONFIG__e__DEFAULT
+#define R_DRAM_CONFIG__e__DEFAULT edo
+#endif
+
+/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit9 bit28 bit19 grp0 bit29 grp1 */
+#ifndef R_DRAM_CONFIG__group_sel__DEFAULT
+#define R_DRAM_CONFIG__group_sel__DEFAULT bit10
+#endif
+
+/* 0 - 7 */
+#ifndef R_DRAM_CONFIG__ca1__DEFAULT
+#define R_DRAM_CONFIG__ca1__DEFAULT 0
+#endif
+
+/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit28 bit19 bit29 bank0 bank1 bit9 */
+#ifndef R_DRAM_CONFIG__bank23sel__DEFAULT
+#define R_DRAM_CONFIG__bank23sel__DEFAULT bit10
+#endif
+
+/* 0 - 7 */
+#ifndef R_DRAM_CONFIG__ca0__DEFAULT
+#define R_DRAM_CONFIG__ca0__DEFAULT 0
+#endif
+
+/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit28 bit19 bit29 bank0 bank1 bit9 */
+#ifndef R_DRAM_CONFIG__bank01sel__DEFAULT
+#define R_DRAM_CONFIG__bank01sel__DEFAULT bit10
+#endif
+
+/*
+** Default values for register R_DRAM_TIMING
+*/
+
+/* disable enable */
+#ifndef R_DRAM_TIMING__sdram__DEFAULT
+#define R_DRAM_TIMING__sdram__DEFAULT disable
+#endif
+
+/* e13us disable e52us e8700ns */
+#ifndef R_DRAM_TIMING__ref__DEFAULT
+#define R_DRAM_TIMING__ref__DEFAULT e13us
+#endif
+
+/* 0 - 3 */
+#ifndef R_DRAM_TIMING__rp__DEFAULT
+#define R_DRAM_TIMING__rp__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_DRAM_TIMING__rs__DEFAULT
+#define R_DRAM_TIMING__rs__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_DRAM_TIMING__rh__DEFAULT
+#define R_DRAM_TIMING__rh__DEFAULT 0
+#endif
+
+/* ext norm */
+#ifndef R_DRAM_TIMING__w__DEFAULT
+#define R_DRAM_TIMING__w__DEFAULT ext
+#endif
+
+/* ext norm */
+#ifndef R_DRAM_TIMING__c__DEFAULT
+#define R_DRAM_TIMING__c__DEFAULT ext
+#endif
+
+/* 0 - 3 */
+#ifndef R_DRAM_TIMING__cz__DEFAULT
+#define R_DRAM_TIMING__cz__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_DRAM_TIMING__cp__DEFAULT
+#define R_DRAM_TIMING__cp__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_DRAM_TIMING__cw__DEFAULT
+#define R_DRAM_TIMING__cw__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_EXT_DMA_0_ADDR
+*/
+
+/* 0 - 0xfffffff */
+#ifndef R_EXT_DMA_0_ADDR__ext0_addr__DEFAULT
+#define R_EXT_DMA_0_ADDR__ext0_addr__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_EXT_DMA_0_CMD
+*/
+
+/* disable enable */
+#ifndef R_EXT_DMA_0_CMD__cnt__DEFAULT
+#define R_EXT_DMA_0_CMD__cnt__DEFAULT disable
+#endif
+
+/* ahigh alow */
+#ifndef R_EXT_DMA_0_CMD__rqpol__DEFAULT
+#define R_EXT_DMA_0_CMD__rqpol__DEFAULT ahigh
+#endif
+
+/* ahigh alow */
+#ifndef R_EXT_DMA_0_CMD__apol__DEFAULT
+#define R_EXT_DMA_0_CMD__apol__DEFAULT ahigh
+#endif
+
+/* burst handsh */
+#ifndef R_EXT_DMA_0_CMD__rq_ack__DEFAULT
+#define R_EXT_DMA_0_CMD__rq_ack__DEFAULT burst
+#endif
+
+/* dword word byte */
+#ifndef R_EXT_DMA_0_CMD__wid__DEFAULT
+#define R_EXT_DMA_0_CMD__wid__DEFAULT dword
+#endif
+
+/* input output */
+#ifndef R_EXT_DMA_0_CMD__dir__DEFAULT
+#define R_EXT_DMA_0_CMD__dir__DEFAULT input
+#endif
+
+/* stop start */
+#ifndef R_EXT_DMA_0_CMD__run__DEFAULT
+#define R_EXT_DMA_0_CMD__run__DEFAULT stop
+#endif
+
+/* 0 - 0xffff */
+#ifndef R_EXT_DMA_0_CMD__trf_count__DEFAULT
+#define R_EXT_DMA_0_CMD__trf_count__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_EXT_DMA_1_ADDR
+*/
+
+/* 0 - 0xfffffff */
+#ifndef R_EXT_DMA_1_ADDR__ext0_addr__DEFAULT
+#define R_EXT_DMA_1_ADDR__ext0_addr__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_EXT_DMA_1_CMD
+*/
+
+/* disable enable */
+#ifndef R_EXT_DMA_1_CMD__cnt__DEFAULT
+#define R_EXT_DMA_1_CMD__cnt__DEFAULT disable
+#endif
+
+/* ahigh alow */
+#ifndef R_EXT_DMA_1_CMD__rqpol__DEFAULT
+#define R_EXT_DMA_1_CMD__rqpol__DEFAULT ahigh
+#endif
+
+/* ahigh alow */
+#ifndef R_EXT_DMA_1_CMD__apol__DEFAULT
+#define R_EXT_DMA_1_CMD__apol__DEFAULT ahigh
+#endif
+
+/* burst handsh */
+#ifndef R_EXT_DMA_1_CMD__rq_ack__DEFAULT
+#define R_EXT_DMA_1_CMD__rq_ack__DEFAULT burst
+#endif
+
+/* dword word byte */
+#ifndef R_EXT_DMA_1_CMD__wid__DEFAULT
+#define R_EXT_DMA_1_CMD__wid__DEFAULT dword
+#endif
+
+/* input output */
+#ifndef R_EXT_DMA_1_CMD__dir__DEFAULT
+#define R_EXT_DMA_1_CMD__dir__DEFAULT input
+#endif
+
+/* stop start */
+#ifndef R_EXT_DMA_1_CMD__run__DEFAULT
+#define R_EXT_DMA_1_CMD__run__DEFAULT stop
+#endif
+
+/* 0 - 0xffff */
+#ifndef R_EXT_DMA_1_CMD__trf_count__DEFAULT
+#define R_EXT_DMA_1_CMD__trf_count__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_GEN_CONFIG
+*/
+
+/* select disable */
+#ifndef R_GEN_CONFIG__par_w__DEFAULT
+#define R_GEN_CONFIG__par_w__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__usb2__DEFAULT
+#define R_GEN_CONFIG__usb2__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__usb1__DEFAULT
+#define R_GEN_CONFIG__usb1__DEFAULT select
+#endif
+
+/* out in */
+#ifndef R_GEN_CONFIG__g24dir__DEFAULT
+#define R_GEN_CONFIG__g24dir__DEFAULT out
+#endif
+
+/* out in */
+#ifndef R_GEN_CONFIG__g16_23dir__DEFAULT
+#define R_GEN_CONFIG__g16_23dir__DEFAULT out
+#endif
+
+/* out in */
+#ifndef R_GEN_CONFIG__g8_15dir__DEFAULT
+#define R_GEN_CONFIG__g8_15dir__DEFAULT out
+#endif
+
+/* out in */
+#ifndef R_GEN_CONFIG__g0dir__DEFAULT
+#define R_GEN_CONFIG__g0dir__DEFAULT out
+#endif
+
+/* serial1 usb */
+#ifndef R_GEN_CONFIG__dma9__DEFAULT
+#define R_GEN_CONFIG__dma9__DEFAULT serial1
+#endif
+
+/* serial1 usb */
+#ifndef R_GEN_CONFIG__dma8__DEFAULT
+#define R_GEN_CONFIG__dma8__DEFAULT serial1
+#endif
+
+/* serial0 intdma6 extdma1 unused */
+#ifndef R_GEN_CONFIG__dma7__DEFAULT
+#define R_GEN_CONFIG__dma7__DEFAULT serial0
+#endif
+
+/* serial0 intdma7 extdma1 unused */
+#ifndef R_GEN_CONFIG__dma6__DEFAULT
+#define R_GEN_CONFIG__dma6__DEFAULT serial0
+#endif
+
+/* extdma0 serial3 scsi1 par1 */
+#ifndef R_GEN_CONFIG__dma5__DEFAULT
+#define R_GEN_CONFIG__dma5__DEFAULT extdma0
+#endif
+
+/* extdma0 serial3 scsi1 par1 */
+#ifndef R_GEN_CONFIG__dma4__DEFAULT
+#define R_GEN_CONFIG__dma4__DEFAULT extdma0
+#endif
+
+/* serial2 scsi0 par0 ata */
+#ifndef R_GEN_CONFIG__dma3__DEFAULT
+#define R_GEN_CONFIG__dma3__DEFAULT serial2
+#endif
+
+/* serial2 scsi0 par0 ata */
+#ifndef R_GEN_CONFIG__dma2__DEFAULT
+#define R_GEN_CONFIG__dma2__DEFAULT serial2
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__mio_w__DEFAULT
+#define R_GEN_CONFIG__mio_w__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__ser3__DEFAULT
+#define R_GEN_CONFIG__ser3__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__par1__DEFAULT
+#define R_GEN_CONFIG__par1__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__scsi0w__DEFAULT
+#define R_GEN_CONFIG__scsi0w__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__scsi1__DEFAULT
+#define R_GEN_CONFIG__scsi1__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__mio__DEFAULT
+#define R_GEN_CONFIG__mio__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__ser2__DEFAULT
+#define R_GEN_CONFIG__ser2__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__par0__DEFAULT
+#define R_GEN_CONFIG__par0__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__ata__DEFAULT
+#define R_GEN_CONFIG__ata__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG__scsi0__DEFAULT
+#define R_GEN_CONFIG__scsi0__DEFAULT select
+#endif
+
+/*
+** Default values for register R_GEN_CONFIG_II
+*/
+
+/* sync async */
+#ifndef R_GEN_CONFIG_II__sermode3__DEFAULT
+#define R_GEN_CONFIG_II__sermode3__DEFAULT sync
+#endif
+
+/* sync async */
+#ifndef R_GEN_CONFIG_II__sermode1__DEFAULT
+#define R_GEN_CONFIG_II__sermode1__DEFAULT sync
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG_II__ext_clk__DEFAULT
+#define R_GEN_CONFIG_II__ext_clk__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG_II__ser3__DEFAULT
+#define R_GEN_CONFIG_II__ser3__DEFAULT select
+#endif
+
+/* select disable */
+#ifndef R_GEN_CONFIG_II__ser2__DEFAULT
+#define R_GEN_CONFIG_II__ser2__DEFAULT select
+#endif
+
+/*
+** Default values for register R_IRQ_MASK0_CLR
+*/
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__nmi_pin__DEFAULT
+#define R_IRQ_MASK0_CLR__nmi_pin__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__watchdog_nmi__DEFAULT
+#define R_IRQ_MASK0_CLR__watchdog_nmi__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__sqe_test_error__DEFAULT
+#define R_IRQ_MASK0_CLR__sqe_test_error__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__carrier_loss__DEFAULT
+#define R_IRQ_MASK0_CLR__carrier_loss__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__deferred__DEFAULT
+#define R_IRQ_MASK0_CLR__deferred__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__late_col__DEFAULT
+#define R_IRQ_MASK0_CLR__late_col__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__multiple_col__DEFAULT
+#define R_IRQ_MASK0_CLR__multiple_col__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__single_col__DEFAULT
+#define R_IRQ_MASK0_CLR__single_col__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__congestion__DEFAULT
+#define R_IRQ_MASK0_CLR__congestion__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__oversize__DEFAULT
+#define R_IRQ_MASK0_CLR__oversize__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__alignment_error__DEFAULT
+#define R_IRQ_MASK0_CLR__alignment_error__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__crc_error__DEFAULT
+#define R_IRQ_MASK0_CLR__crc_error__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__overrun__DEFAULT
+#define R_IRQ_MASK0_CLR__overrun__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__underrun__DEFAULT
+#define R_IRQ_MASK0_CLR__underrun__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__excessive_col__DEFAULT
+#define R_IRQ_MASK0_CLR__excessive_col__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__mdio__DEFAULT
+#define R_IRQ_MASK0_CLR__mdio__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__ata_drq3__DEFAULT
+#define R_IRQ_MASK0_CLR__ata_drq3__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__ata_drq2__DEFAULT
+#define R_IRQ_MASK0_CLR__ata_drq2__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__ata_drq1__DEFAULT
+#define R_IRQ_MASK0_CLR__ata_drq1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__ata_drq0__DEFAULT
+#define R_IRQ_MASK0_CLR__ata_drq0__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__par0_ecp_cmd__DEFAULT
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__par0_peri__DEFAULT
+#define R_IRQ_MASK0_CLR__par0_peri__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__par0_data__DEFAULT
+#define R_IRQ_MASK0_CLR__par0_data__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__par0_ready__DEFAULT
+#define R_IRQ_MASK0_CLR__par0_ready__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__ata_dmaend__DEFAULT
+#define R_IRQ_MASK0_CLR__ata_dmaend__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__irq_ext_vector_nr__DEFAULT
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__irq_int_vector_nr__DEFAULT
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__ext_dma1__DEFAULT
+#define R_IRQ_MASK0_CLR__ext_dma1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__ext_dma0__DEFAULT
+#define R_IRQ_MASK0_CLR__ext_dma0__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__timer1__DEFAULT
+#define R_IRQ_MASK0_CLR__timer1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK0_CLR__timer0__DEFAULT
+#define R_IRQ_MASK0_CLR__timer0__DEFAULT clr
+#endif
+
+/*
+** Default values for register R_IRQ_MASK0_SET
+*/
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__nmi_pin__DEFAULT
+#define R_IRQ_MASK0_SET__nmi_pin__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__watchdog_nmi__DEFAULT
+#define R_IRQ_MASK0_SET__watchdog_nmi__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__sqe_test_error__DEFAULT
+#define R_IRQ_MASK0_SET__sqe_test_error__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__carrier_loss__DEFAULT
+#define R_IRQ_MASK0_SET__carrier_loss__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__deferred__DEFAULT
+#define R_IRQ_MASK0_SET__deferred__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__late_col__DEFAULT
+#define R_IRQ_MASK0_SET__late_col__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__multiple_col__DEFAULT
+#define R_IRQ_MASK0_SET__multiple_col__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__single_col__DEFAULT
+#define R_IRQ_MASK0_SET__single_col__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__congestion__DEFAULT
+#define R_IRQ_MASK0_SET__congestion__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__oversize__DEFAULT
+#define R_IRQ_MASK0_SET__oversize__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__alignment_error__DEFAULT
+#define R_IRQ_MASK0_SET__alignment_error__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__crc_error__DEFAULT
+#define R_IRQ_MASK0_SET__crc_error__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__overrun__DEFAULT
+#define R_IRQ_MASK0_SET__overrun__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__underrun__DEFAULT
+#define R_IRQ_MASK0_SET__underrun__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__excessive_col__DEFAULT
+#define R_IRQ_MASK0_SET__excessive_col__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__mdio__DEFAULT
+#define R_IRQ_MASK0_SET__mdio__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__ata_drq3__DEFAULT
+#define R_IRQ_MASK0_SET__ata_drq3__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__ata_drq2__DEFAULT
+#define R_IRQ_MASK0_SET__ata_drq2__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__ata_drq1__DEFAULT
+#define R_IRQ_MASK0_SET__ata_drq1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__ata_drq0__DEFAULT
+#define R_IRQ_MASK0_SET__ata_drq0__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__par0_ecp_cmd__DEFAULT
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__par0_peri__DEFAULT
+#define R_IRQ_MASK0_SET__par0_peri__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__par0_data__DEFAULT
+#define R_IRQ_MASK0_SET__par0_data__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__par0_ready__DEFAULT
+#define R_IRQ_MASK0_SET__par0_ready__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__ata_dmaend__DEFAULT
+#define R_IRQ_MASK0_SET__ata_dmaend__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__irq_ext_vector_nr__DEFAULT
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__irq_int_vector_nr__DEFAULT
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__ext_dma1__DEFAULT
+#define R_IRQ_MASK0_SET__ext_dma1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__ext_dma0__DEFAULT
+#define R_IRQ_MASK0_SET__ext_dma0__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__timer1__DEFAULT
+#define R_IRQ_MASK0_SET__timer1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK0_SET__timer0__DEFAULT
+#define R_IRQ_MASK0_SET__timer0__DEFAULT set
+#endif
+
+/*
+** Default values for register R_IRQ_MASK1_CLR
+*/
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__sw_int7__DEFAULT
+#define R_IRQ_MASK1_CLR__sw_int7__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__sw_int6__DEFAULT
+#define R_IRQ_MASK1_CLR__sw_int6__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__sw_int5__DEFAULT
+#define R_IRQ_MASK1_CLR__sw_int5__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__sw_int4__DEFAULT
+#define R_IRQ_MASK1_CLR__sw_int4__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__sw_int3__DEFAULT
+#define R_IRQ_MASK1_CLR__sw_int3__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__sw_int2__DEFAULT
+#define R_IRQ_MASK1_CLR__sw_int2__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__sw_int1__DEFAULT
+#define R_IRQ_MASK1_CLR__sw_int1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__sw_int0__DEFAULT
+#define R_IRQ_MASK1_CLR__sw_int0__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__par1_ecp_cmd__DEFAULT
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__par1_peri__DEFAULT
+#define R_IRQ_MASK1_CLR__par1_peri__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__par1_data__DEFAULT
+#define R_IRQ_MASK1_CLR__par1_data__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__par1_ready__DEFAULT
+#define R_IRQ_MASK1_CLR__par1_ready__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__ser3_ready__DEFAULT
+#define R_IRQ_MASK1_CLR__ser3_ready__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__ser3_data__DEFAULT
+#define R_IRQ_MASK1_CLR__ser3_data__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__ser2_ready__DEFAULT
+#define R_IRQ_MASK1_CLR__ser2_ready__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__ser2_data__DEFAULT
+#define R_IRQ_MASK1_CLR__ser2_data__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__ser1_ready__DEFAULT
+#define R_IRQ_MASK1_CLR__ser1_ready__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__ser1_data__DEFAULT
+#define R_IRQ_MASK1_CLR__ser1_data__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__ser0_ready__DEFAULT
+#define R_IRQ_MASK1_CLR__ser0_ready__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__ser0_data__DEFAULT
+#define R_IRQ_MASK1_CLR__ser0_data__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__pa7__DEFAULT
+#define R_IRQ_MASK1_CLR__pa7__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__pa6__DEFAULT
+#define R_IRQ_MASK1_CLR__pa6__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__pa5__DEFAULT
+#define R_IRQ_MASK1_CLR__pa5__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__pa4__DEFAULT
+#define R_IRQ_MASK1_CLR__pa4__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__pa3__DEFAULT
+#define R_IRQ_MASK1_CLR__pa3__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__pa2__DEFAULT
+#define R_IRQ_MASK1_CLR__pa2__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__pa1__DEFAULT
+#define R_IRQ_MASK1_CLR__pa1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK1_CLR__pa0__DEFAULT
+#define R_IRQ_MASK1_CLR__pa0__DEFAULT clr
+#endif
+
+/*
+** Default values for register R_IRQ_MASK1_SET
+*/
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__sw_int7__DEFAULT
+#define R_IRQ_MASK1_SET__sw_int7__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__sw_int6__DEFAULT
+#define R_IRQ_MASK1_SET__sw_int6__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__sw_int5__DEFAULT
+#define R_IRQ_MASK1_SET__sw_int5__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__sw_int4__DEFAULT
+#define R_IRQ_MASK1_SET__sw_int4__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__sw_int3__DEFAULT
+#define R_IRQ_MASK1_SET__sw_int3__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__sw_int2__DEFAULT
+#define R_IRQ_MASK1_SET__sw_int2__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__sw_int1__DEFAULT
+#define R_IRQ_MASK1_SET__sw_int1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__sw_int0__DEFAULT
+#define R_IRQ_MASK1_SET__sw_int0__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__par1_ecp_cmd__DEFAULT
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__par1_peri__DEFAULT
+#define R_IRQ_MASK1_SET__par1_peri__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__par1_data__DEFAULT
+#define R_IRQ_MASK1_SET__par1_data__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__par1_ready__DEFAULT
+#define R_IRQ_MASK1_SET__par1_ready__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__ser3_ready__DEFAULT
+#define R_IRQ_MASK1_SET__ser3_ready__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__ser3_data__DEFAULT
+#define R_IRQ_MASK1_SET__ser3_data__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__ser2_ready__DEFAULT
+#define R_IRQ_MASK1_SET__ser2_ready__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__ser2_data__DEFAULT
+#define R_IRQ_MASK1_SET__ser2_data__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__ser1_ready__DEFAULT
+#define R_IRQ_MASK1_SET__ser1_ready__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__ser1_data__DEFAULT
+#define R_IRQ_MASK1_SET__ser1_data__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__ser0_ready__DEFAULT
+#define R_IRQ_MASK1_SET__ser0_ready__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__ser0_data__DEFAULT
+#define R_IRQ_MASK1_SET__ser0_data__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__pa7__DEFAULT
+#define R_IRQ_MASK1_SET__pa7__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__pa6__DEFAULT
+#define R_IRQ_MASK1_SET__pa6__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__pa5__DEFAULT
+#define R_IRQ_MASK1_SET__pa5__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__pa4__DEFAULT
+#define R_IRQ_MASK1_SET__pa4__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__pa3__DEFAULT
+#define R_IRQ_MASK1_SET__pa3__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__pa2__DEFAULT
+#define R_IRQ_MASK1_SET__pa2__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__pa1__DEFAULT
+#define R_IRQ_MASK1_SET__pa1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK1_SET__pa0__DEFAULT
+#define R_IRQ_MASK1_SET__pa0__DEFAULT set
+#endif
+
+/*
+** Default values for register R_IRQ_MASK2_CLR
+*/
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma8_sub3_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma8_sub2_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma8_sub1_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma8_sub0_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma9_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma9_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma9_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma9_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma8_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma8_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma8_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma8_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma7_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma7_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma7_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma7_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma6_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma6_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma6_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma6_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma5_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma5_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma5_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma5_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma4_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma4_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma4_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma4_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma3_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma3_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma3_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma3_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma2_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma2_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma2_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma2_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma1_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma1_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma1_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma1_descr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma0_eop__DEFAULT
+#define R_IRQ_MASK2_CLR__dma0_eop__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_IRQ_MASK2_CLR__dma0_descr__DEFAULT
+#define R_IRQ_MASK2_CLR__dma0_descr__DEFAULT clr
+#endif
+
+/*
+** Default values for register R_IRQ_MASK2_SET
+*/
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma8_sub3_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma8_sub2_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma8_sub1_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma8_sub0_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma9_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma9_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma9_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma9_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma8_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma8_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma8_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma8_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma7_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma7_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma7_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma7_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma6_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma6_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma6_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma6_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma5_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma5_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma5_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma5_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma4_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma4_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma4_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma4_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma3_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma3_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma3_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma3_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma2_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma2_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma2_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma2_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma1_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma1_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma1_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma1_descr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma0_eop__DEFAULT
+#define R_IRQ_MASK2_SET__dma0_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_IRQ_MASK2_SET__dma0_descr__DEFAULT
+#define R_IRQ_MASK2_SET__dma0_descr__DEFAULT set
+#endif
+
+/*
+** Default values for register R_MMU_CONFIG
+*/
+
+/* disable enable */
+#ifndef R_MMU_CONFIG__mmu_enable__DEFAULT
+#define R_MMU_CONFIG__mmu_enable__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_MMU_CONFIG__inv_excp__DEFAULT
+#define R_MMU_CONFIG__inv_excp__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_MMU_CONFIG__acc_excp__DEFAULT
+#define R_MMU_CONFIG__acc_excp__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_MMU_CONFIG__we_excp__DEFAULT
+#define R_MMU_CONFIG__we_excp__DEFAULT disable
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_f__DEFAULT
+#define R_MMU_CONFIG__seg_f__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_e__DEFAULT
+#define R_MMU_CONFIG__seg_e__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_d__DEFAULT
+#define R_MMU_CONFIG__seg_d__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_c__DEFAULT
+#define R_MMU_CONFIG__seg_c__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_b__DEFAULT
+#define R_MMU_CONFIG__seg_b__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_a__DEFAULT
+#define R_MMU_CONFIG__seg_a__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_9__DEFAULT
+#define R_MMU_CONFIG__seg_9__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_8__DEFAULT
+#define R_MMU_CONFIG__seg_8__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_7__DEFAULT
+#define R_MMU_CONFIG__seg_7__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_6__DEFAULT
+#define R_MMU_CONFIG__seg_6__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_5__DEFAULT
+#define R_MMU_CONFIG__seg_5__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_4__DEFAULT
+#define R_MMU_CONFIG__seg_4__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_3__DEFAULT
+#define R_MMU_CONFIG__seg_3__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_2__DEFAULT
+#define R_MMU_CONFIG__seg_2__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_1__DEFAULT
+#define R_MMU_CONFIG__seg_1__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_CONFIG__seg_0__DEFAULT
+#define R_MMU_CONFIG__seg_0__DEFAULT page
+#endif
+
+/*
+** Default values for register R_MMU_CTRL
+*/
+
+/* disable enable */
+#ifndef R_MMU_CTRL__inv_excp__DEFAULT
+#define R_MMU_CTRL__inv_excp__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_MMU_CTRL__acc_excp__DEFAULT
+#define R_MMU_CTRL__acc_excp__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_MMU_CTRL__we_excp__DEFAULT
+#define R_MMU_CTRL__we_excp__DEFAULT disable
+#endif
+
+/*
+** Default values for register R_MMU_ENABLE
+*/
+
+/* disable enable */
+#ifndef R_MMU_ENABLE__mmu_enable__DEFAULT
+#define R_MMU_ENABLE__mmu_enable__DEFAULT disable
+#endif
+
+/*
+** Default values for register R_MMU_KBASE_HI
+*/
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_HI__base_f__DEFAULT
+#define R_MMU_KBASE_HI__base_f__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_HI__base_e__DEFAULT
+#define R_MMU_KBASE_HI__base_e__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_HI__base_d__DEFAULT
+#define R_MMU_KBASE_HI__base_d__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_HI__base_c__DEFAULT
+#define R_MMU_KBASE_HI__base_c__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_HI__base_b__DEFAULT
+#define R_MMU_KBASE_HI__base_b__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_HI__base_a__DEFAULT
+#define R_MMU_KBASE_HI__base_a__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_HI__base_9__DEFAULT
+#define R_MMU_KBASE_HI__base_9__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_HI__base_8__DEFAULT
+#define R_MMU_KBASE_HI__base_8__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_MMU_KBASE_LO
+*/
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_LO__base_7__DEFAULT
+#define R_MMU_KBASE_LO__base_7__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_LO__base_6__DEFAULT
+#define R_MMU_KBASE_LO__base_6__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_LO__base_5__DEFAULT
+#define R_MMU_KBASE_LO__base_5__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_LO__base_4__DEFAULT
+#define R_MMU_KBASE_LO__base_4__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_LO__base_3__DEFAULT
+#define R_MMU_KBASE_LO__base_3__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_LO__base_2__DEFAULT
+#define R_MMU_KBASE_LO__base_2__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_LO__base_1__DEFAULT
+#define R_MMU_KBASE_LO__base_1__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_MMU_KBASE_LO__base_0__DEFAULT
+#define R_MMU_KBASE_LO__base_0__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_MMU_KSEG
+*/
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_f__DEFAULT
+#define R_MMU_KSEG__seg_f__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_e__DEFAULT
+#define R_MMU_KSEG__seg_e__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_d__DEFAULT
+#define R_MMU_KSEG__seg_d__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_c__DEFAULT
+#define R_MMU_KSEG__seg_c__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_b__DEFAULT
+#define R_MMU_KSEG__seg_b__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_a__DEFAULT
+#define R_MMU_KSEG__seg_a__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_9__DEFAULT
+#define R_MMU_KSEG__seg_9__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_8__DEFAULT
+#define R_MMU_KSEG__seg_8__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_7__DEFAULT
+#define R_MMU_KSEG__seg_7__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_6__DEFAULT
+#define R_MMU_KSEG__seg_6__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_5__DEFAULT
+#define R_MMU_KSEG__seg_5__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_4__DEFAULT
+#define R_MMU_KSEG__seg_4__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_3__DEFAULT
+#define R_MMU_KSEG__seg_3__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_2__DEFAULT
+#define R_MMU_KSEG__seg_2__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_1__DEFAULT
+#define R_MMU_KSEG__seg_1__DEFAULT page
+#endif
+
+/* page seg */
+#ifndef R_MMU_KSEG__seg_0__DEFAULT
+#define R_MMU_KSEG__seg_0__DEFAULT page
+#endif
+
+/*
+** Default values for register R_NETWORK_GA_0
+*/
+
+/* 0 - 0xffffffff */
+#ifndef R_NETWORK_GA_0__ga_low__DEFAULT
+#define R_NETWORK_GA_0__ga_low__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_NETWORK_GA_1
+*/
+
+/* 0 - 0xffffffff */
+#ifndef R_NETWORK_GA_1__ga_high__DEFAULT
+#define R_NETWORK_GA_1__ga_high__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_NETWORK_GEN_CONFIG
+*/
+
+/* off on */
+#ifndef R_NETWORK_GEN_CONFIG__loopback__DEFAULT
+#define R_NETWORK_GEN_CONFIG__loopback__DEFAULT off
+#endif
+
+/* ether tokenr */
+#ifndef R_NETWORK_GEN_CONFIG__frame__DEFAULT
+#define R_NETWORK_GEN_CONFIG__frame__DEFAULT ether
+#endif
+
+/* off on */
+#ifndef R_NETWORK_GEN_CONFIG__vg__DEFAULT
+#define R_NETWORK_GEN_CONFIG__vg__DEFAULT off
+#endif
+
+/* mii_clk sni mii_req mii_err */
+#ifndef R_NETWORK_GEN_CONFIG__phy__DEFAULT
+#define R_NETWORK_GEN_CONFIG__phy__DEFAULT mii_clk
+#endif
+
+/* off on */
+#ifndef R_NETWORK_GEN_CONFIG__enable__DEFAULT
+#define R_NETWORK_GEN_CONFIG__enable__DEFAULT off
+#endif
+
+/*
+** Default values for register R_NETWORK_MGM_CTRL
+*/
+
+/* 0 - 0xf */
+#ifndef R_NETWORK_MGM_CTRL__txd_pins__DEFAULT
+#define R_NETWORK_MGM_CTRL__txd_pins__DEFAULT 0
+#endif
+
+/* 0 - 0x1 */
+#ifndef R_NETWORK_MGM_CTRL__txer_pin__DEFAULT
+#define R_NETWORK_MGM_CTRL__txer_pin__DEFAULT 0
+#endif
+
+/* 0 - 0x1 */
+#ifndef R_NETWORK_MGM_CTRL__mdck__DEFAULT
+#define R_NETWORK_MGM_CTRL__mdck__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_NETWORK_MGM_CTRL__mdoe__DEFAULT
+#define R_NETWORK_MGM_CTRL__mdoe__DEFAULT disable
+#endif
+
+/* 0 - 0x1 */
+#ifndef R_NETWORK_MGM_CTRL__mdio__DEFAULT
+#define R_NETWORK_MGM_CTRL__mdio__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_NETWORK_REC_CONFIG
+*/
+
+/* size1518 size1522 */
+#ifndef R_NETWORK_REC_CONFIG__max_size__DEFAULT
+#define R_NETWORK_REC_CONFIG__max_size__DEFAULT size1518
+#endif
+
+/* half full */
+#ifndef R_NETWORK_REC_CONFIG__duplex__DEFAULT
+#define R_NETWORK_REC_CONFIG__duplex__DEFAULT half
+#endif
+
+/* discard receive */
+#ifndef R_NETWORK_REC_CONFIG__bad_crc__DEFAULT
+#define R_NETWORK_REC_CONFIG__bad_crc__DEFAULT discard
+#endif
+
+/* discard receive */
+#ifndef R_NETWORK_REC_CONFIG__oversize__DEFAULT
+#define R_NETWORK_REC_CONFIG__oversize__DEFAULT discard
+#endif
+
+/* discard receive */
+#ifndef R_NETWORK_REC_CONFIG__undersize__DEFAULT
+#define R_NETWORK_REC_CONFIG__undersize__DEFAULT discard
+#endif
+
+/* discard receive */
+#ifndef R_NETWORK_REC_CONFIG__all_roots__DEFAULT
+#define R_NETWORK_REC_CONFIG__all_roots__DEFAULT discard
+#endif
+
+/* discard receive */
+#ifndef R_NETWORK_REC_CONFIG__tr_broadcast__DEFAULT
+#define R_NETWORK_REC_CONFIG__tr_broadcast__DEFAULT discard
+#endif
+
+/* discard receive */
+#ifndef R_NETWORK_REC_CONFIG__broadcast__DEFAULT
+#define R_NETWORK_REC_CONFIG__broadcast__DEFAULT discard
+#endif
+
+/* discard receive */
+#ifndef R_NETWORK_REC_CONFIG__individual__DEFAULT
+#define R_NETWORK_REC_CONFIG__individual__DEFAULT discard
+#endif
+
+/* disable enable */
+#ifndef R_NETWORK_REC_CONFIG__ma1__DEFAULT
+#define R_NETWORK_REC_CONFIG__ma1__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_NETWORK_REC_CONFIG__ma0__DEFAULT
+#define R_NETWORK_REC_CONFIG__ma0__DEFAULT disable
+#endif
+
+/*
+** Default values for register R_NETWORK_SA_0
+*/
+
+/* 0 - 0xffffffff */
+#ifndef R_NETWORK_SA_0__ma0_low__DEFAULT
+#define R_NETWORK_SA_0__ma0_low__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_NETWORK_SA_1
+*/
+
+/* 0 - 0xffff */
+#ifndef R_NETWORK_SA_1__ma1_low__DEFAULT
+#define R_NETWORK_SA_1__ma1_low__DEFAULT 0
+#endif
+
+/* 0 - 0xffff */
+#ifndef R_NETWORK_SA_1__ma0_high__DEFAULT
+#define R_NETWORK_SA_1__ma0_high__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_NETWORK_SA_2
+*/
+
+/* 0 - 0xffffffff */
+#ifndef R_NETWORK_SA_2__ma1_high__DEFAULT
+#define R_NETWORK_SA_2__ma1_high__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_NETWORK_TR_CTRL
+*/
+
+/* clr nop */
+#ifndef R_NETWORK_TR_CTRL__clr_error__DEFAULT
+#define R_NETWORK_TR_CTRL__clr_error__DEFAULT clr
+#endif
+
+/* none d2us */
+#ifndef R_NETWORK_TR_CTRL__delay__DEFAULT
+#define R_NETWORK_TR_CTRL__delay__DEFAULT none
+#endif
+
+/* do dont */
+#ifndef R_NETWORK_TR_CTRL__cancel__DEFAULT
+#define R_NETWORK_TR_CTRL__cancel__DEFAULT do
+#endif
+
+/* ack_col disable ack_crs enable */
+#ifndef R_NETWORK_TR_CTRL__cd__DEFAULT
+#define R_NETWORK_TR_CTRL__cd__DEFAULT ack_col
+#endif
+
+/* disable enable */
+#ifndef R_NETWORK_TR_CTRL__retry__DEFAULT
+#define R_NETWORK_TR_CTRL__retry__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_NETWORK_TR_CTRL__pad__DEFAULT
+#define R_NETWORK_TR_CTRL__pad__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_NETWORK_TR_CTRL__crc__DEFAULT
+#define R_NETWORK_TR_CTRL__crc__DEFAULT disable
+#endif
+
+/*
+** Default values for register R_PAR0_CONFIG
+*/
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__ioe__DEFAULT
+#define R_PAR0_CONFIG__ioe__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__iseli__DEFAULT
+#define R_PAR0_CONFIG__iseli__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__iautofd__DEFAULT
+#define R_PAR0_CONFIG__iautofd__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__istrb__DEFAULT
+#define R_PAR0_CONFIG__istrb__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__iinit__DEFAULT
+#define R_PAR0_CONFIG__iinit__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__iperr__DEFAULT
+#define R_PAR0_CONFIG__iperr__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__iack__DEFAULT
+#define R_PAR0_CONFIG__iack__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__ibusy__DEFAULT
+#define R_PAR0_CONFIG__ibusy__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__ifault__DEFAULT
+#define R_PAR0_CONFIG__ifault__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR0_CONFIG__isel__DEFAULT
+#define R_PAR0_CONFIG__isel__DEFAULT noninv
+#endif
+
+/* disable enable */
+#ifndef R_PAR0_CONFIG__ext_mode__DEFAULT
+#define R_PAR0_CONFIG__ext_mode__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_PAR0_CONFIG__wide__DEFAULT
+#define R_PAR0_CONFIG__wide__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_PAR0_CONFIG__dma__DEFAULT
+#define R_PAR0_CONFIG__dma__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_PAR0_CONFIG__rle_in__DEFAULT
+#define R_PAR0_CONFIG__rle_in__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_PAR0_CONFIG__rle_out__DEFAULT
+#define R_PAR0_CONFIG__rle_out__DEFAULT disable
+#endif
+
+/* reset on */
+#ifndef R_PAR0_CONFIG__enable__DEFAULT
+#define R_PAR0_CONFIG__enable__DEFAULT reset
+#endif
+
+/* off on */
+#ifndef R_PAR0_CONFIG__force__DEFAULT
+#define R_PAR0_CONFIG__force__DEFAULT off
+#endif
+
+/* ignore wait */
+#ifndef R_PAR0_CONFIG__ign_ack__DEFAULT
+#define R_PAR0_CONFIG__ign_ack__DEFAULT ignore
+#endif
+
+/* wait_oe dont_wait epp_data epp_addr */
+#ifndef R_PAR0_CONFIG__oe_ack__DEFAULT
+#define R_PAR0_CONFIG__oe_ack__DEFAULT wait_oe
+#endif
+
+/* epp_wr3 fastbyte ecp_rev byte centronics ecp_fwd epp_rd off nibble epp_wr1 manual epp_wr2 */
+#ifndef R_PAR0_CONFIG__mode__DEFAULT
+#define R_PAR0_CONFIG__mode__DEFAULT epp_wr3
+#endif
+
+/*
+** Default values for register R_PAR0_CTRL
+*/
+
+/* 0 - 31 */
+#ifndef R_PAR0_CTRL__ctrl__DEFAULT
+#define R_PAR0_CTRL__ctrl__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PAR0_CTRL_DATA
+*/
+
+/* nop ack */
+#ifndef R_PAR0_CTRL_DATA__peri_int__DEFAULT
+#define R_PAR0_CTRL_DATA__peri_int__DEFAULT nop
+#endif
+
+/* disable enable */
+#ifndef R_PAR0_CTRL_DATA__oe__DEFAULT
+#define R_PAR0_CTRL_DATA__oe__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_PAR0_CTRL_DATA__seli__DEFAULT
+#define R_PAR0_CTRL_DATA__seli__DEFAULT inactive
+#endif
+
+/* inactive active */
+#ifndef R_PAR0_CTRL_DATA__autofd__DEFAULT
+#define R_PAR0_CTRL_DATA__autofd__DEFAULT inactive
+#endif
+
+/* inactive active */
+#ifndef R_PAR0_CTRL_DATA__strb__DEFAULT
+#define R_PAR0_CTRL_DATA__strb__DEFAULT inactive
+#endif
+
+/* inactive active */
+#ifndef R_PAR0_CTRL_DATA__init__DEFAULT
+#define R_PAR0_CTRL_DATA__init__DEFAULT inactive
+#endif
+
+/* data command */
+#ifndef R_PAR0_CTRL_DATA__ecp_cmd__DEFAULT
+#define R_PAR0_CTRL_DATA__ecp_cmd__DEFAULT data
+#endif
+
+/* 0 - 0xff */
+#ifndef R_PAR0_CTRL_DATA__data__DEFAULT
+#define R_PAR0_CTRL_DATA__data__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PAR0_DELAY
+*/
+
+/* 0 - 0x7 */
+#ifndef R_PAR0_DELAY__fine_hold__DEFAULT
+#define R_PAR0_DELAY__fine_hold__DEFAULT 0
+#endif
+
+/* 0 - 0x1f */
+#ifndef R_PAR0_DELAY__hold__DEFAULT
+#define R_PAR0_DELAY__hold__DEFAULT 0
+#endif
+
+/* 0 - 0x7 */
+#ifndef R_PAR0_DELAY__fine_strb__DEFAULT
+#define R_PAR0_DELAY__fine_strb__DEFAULT 0
+#endif
+
+/* 0 - 0x1f */
+#ifndef R_PAR0_DELAY__strobe__DEFAULT
+#define R_PAR0_DELAY__strobe__DEFAULT 0
+#endif
+
+/* 0 - 0x7 */
+#ifndef R_PAR0_DELAY__fine_setup__DEFAULT
+#define R_PAR0_DELAY__fine_setup__DEFAULT 0
+#endif
+
+/* 0 - 0x1f */
+#ifndef R_PAR0_DELAY__setup__DEFAULT
+#define R_PAR0_DELAY__setup__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PAR1_CONFIG
+*/
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__ioe__DEFAULT
+#define R_PAR1_CONFIG__ioe__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__iseli__DEFAULT
+#define R_PAR1_CONFIG__iseli__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__iautofd__DEFAULT
+#define R_PAR1_CONFIG__iautofd__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__istrb__DEFAULT
+#define R_PAR1_CONFIG__istrb__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__iinit__DEFAULT
+#define R_PAR1_CONFIG__iinit__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__iperr__DEFAULT
+#define R_PAR1_CONFIG__iperr__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__iack__DEFAULT
+#define R_PAR1_CONFIG__iack__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__ibusy__DEFAULT
+#define R_PAR1_CONFIG__ibusy__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__ifault__DEFAULT
+#define R_PAR1_CONFIG__ifault__DEFAULT noninv
+#endif
+
+/* noninv inv */
+#ifndef R_PAR1_CONFIG__isel__DEFAULT
+#define R_PAR1_CONFIG__isel__DEFAULT noninv
+#endif
+
+/* disable enable */
+#ifndef R_PAR1_CONFIG__ext_mode__DEFAULT
+#define R_PAR1_CONFIG__ext_mode__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_PAR1_CONFIG__dma__DEFAULT
+#define R_PAR1_CONFIG__dma__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_PAR1_CONFIG__rle_in__DEFAULT
+#define R_PAR1_CONFIG__rle_in__DEFAULT disable
+#endif
+
+/* disable enable */
+#ifndef R_PAR1_CONFIG__rle_out__DEFAULT
+#define R_PAR1_CONFIG__rle_out__DEFAULT disable
+#endif
+
+/* reset on */
+#ifndef R_PAR1_CONFIG__enable__DEFAULT
+#define R_PAR1_CONFIG__enable__DEFAULT reset
+#endif
+
+/* off on */
+#ifndef R_PAR1_CONFIG__force__DEFAULT
+#define R_PAR1_CONFIG__force__DEFAULT off
+#endif
+
+/* ignore wait */
+#ifndef R_PAR1_CONFIG__ign_ack__DEFAULT
+#define R_PAR1_CONFIG__ign_ack__DEFAULT ignore
+#endif
+
+/* wait_oe dont_wait epp_data epp_addr */
+#ifndef R_PAR1_CONFIG__oe_ack__DEFAULT
+#define R_PAR1_CONFIG__oe_ack__DEFAULT wait_oe
+#endif
+
+/* epp_wr3 fastbyte ecp_rev byte centronics ecp_fwd epp_rd off nibble epp_wr1 manual epp_wr2 */
+#ifndef R_PAR1_CONFIG__mode__DEFAULT
+#define R_PAR1_CONFIG__mode__DEFAULT epp_wr3
+#endif
+
+/*
+** Default values for register R_PAR1_CTRL
+*/
+
+/* 0 - 31 */
+#ifndef R_PAR1_CTRL__ctrl__DEFAULT
+#define R_PAR1_CTRL__ctrl__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PAR1_CTRL_DATA
+*/
+
+/* nop ack */
+#ifndef R_PAR1_CTRL_DATA__peri_int__DEFAULT
+#define R_PAR1_CTRL_DATA__peri_int__DEFAULT nop
+#endif
+
+/* disable enable */
+#ifndef R_PAR1_CTRL_DATA__oe__DEFAULT
+#define R_PAR1_CTRL_DATA__oe__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_PAR1_CTRL_DATA__seli__DEFAULT
+#define R_PAR1_CTRL_DATA__seli__DEFAULT inactive
+#endif
+
+/* inactive active */
+#ifndef R_PAR1_CTRL_DATA__autofd__DEFAULT
+#define R_PAR1_CTRL_DATA__autofd__DEFAULT inactive
+#endif
+
+/* inactive active */
+#ifndef R_PAR1_CTRL_DATA__strb__DEFAULT
+#define R_PAR1_CTRL_DATA__strb__DEFAULT inactive
+#endif
+
+/* inactive active */
+#ifndef R_PAR1_CTRL_DATA__init__DEFAULT
+#define R_PAR1_CTRL_DATA__init__DEFAULT inactive
+#endif
+
+/* data command */
+#ifndef R_PAR1_CTRL_DATA__ecp_cmd__DEFAULT
+#define R_PAR1_CTRL_DATA__ecp_cmd__DEFAULT data
+#endif
+
+/* 0 - 0xff */
+#ifndef R_PAR1_CTRL_DATA__data__DEFAULT
+#define R_PAR1_CTRL_DATA__data__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PAR1_DELAY
+*/
+
+/* 0 - 0x7 */
+#ifndef R_PAR1_DELAY__fine_hold__DEFAULT
+#define R_PAR1_DELAY__fine_hold__DEFAULT 0
+#endif
+
+/* 0 - 0x1f */
+#ifndef R_PAR1_DELAY__hold__DEFAULT
+#define R_PAR1_DELAY__hold__DEFAULT 0
+#endif
+
+/* 0 - 0x7 */
+#ifndef R_PAR1_DELAY__fine_strb__DEFAULT
+#define R_PAR1_DELAY__fine_strb__DEFAULT 0
+#endif
+
+/* 0 - 0x1f */
+#ifndef R_PAR1_DELAY__strobe__DEFAULT
+#define R_PAR1_DELAY__strobe__DEFAULT 0
+#endif
+
+/* 0 - 0x7 */
+#ifndef R_PAR1_DELAY__fine_setup__DEFAULT
+#define R_PAR1_DELAY__fine_setup__DEFAULT 0
+#endif
+
+/* 0 - 0x1f */
+#ifndef R_PAR1_DELAY__setup__DEFAULT
+#define R_PAR1_DELAY__setup__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PORT_PA_DATA
+*/
+
+/* 0 - 255 */
+#ifndef R_PORT_PA_DATA__data_out__DEFAULT
+#define R_PORT_PA_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PORT_PA_DIR
+*/
+
+/* input output */
+#ifndef R_PORT_PA_DIR__dir7__DEFAULT
+#define R_PORT_PA_DIR__dir7__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_DIR__dir6__DEFAULT
+#define R_PORT_PA_DIR__dir6__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_DIR__dir5__DEFAULT
+#define R_PORT_PA_DIR__dir5__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_DIR__dir4__DEFAULT
+#define R_PORT_PA_DIR__dir4__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_DIR__dir3__DEFAULT
+#define R_PORT_PA_DIR__dir3__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_DIR__dir2__DEFAULT
+#define R_PORT_PA_DIR__dir2__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_DIR__dir1__DEFAULT
+#define R_PORT_PA_DIR__dir1__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_DIR__dir0__DEFAULT
+#define R_PORT_PA_DIR__dir0__DEFAULT input
+#endif
+
+/*
+** Default values for register R_PORT_PA_SET
+*/
+
+/* input output */
+#ifndef R_PORT_PA_SET__dir7__DEFAULT
+#define R_PORT_PA_SET__dir7__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_SET__dir6__DEFAULT
+#define R_PORT_PA_SET__dir6__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_SET__dir5__DEFAULT
+#define R_PORT_PA_SET__dir5__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_SET__dir4__DEFAULT
+#define R_PORT_PA_SET__dir4__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_SET__dir3__DEFAULT
+#define R_PORT_PA_SET__dir3__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_SET__dir2__DEFAULT
+#define R_PORT_PA_SET__dir2__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_SET__dir1__DEFAULT
+#define R_PORT_PA_SET__dir1__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PA_SET__dir0__DEFAULT
+#define R_PORT_PA_SET__dir0__DEFAULT input
+#endif
+
+/* 0 - 255 */
+#ifndef R_PORT_PA_SET__data_out__DEFAULT
+#define R_PORT_PA_SET__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PORT_PB_CONFIG
+*/
+
+/* port cs */
+#ifndef R_PORT_PB_CONFIG__cs7__DEFAULT
+#define R_PORT_PB_CONFIG__cs7__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_CONFIG__cs6__DEFAULT
+#define R_PORT_PB_CONFIG__cs6__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_CONFIG__cs5__DEFAULT
+#define R_PORT_PB_CONFIG__cs5__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_CONFIG__cs4__DEFAULT
+#define R_PORT_PB_CONFIG__cs4__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_CONFIG__cs3__DEFAULT
+#define R_PORT_PB_CONFIG__cs3__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_CONFIG__cs2__DEFAULT
+#define R_PORT_PB_CONFIG__cs2__DEFAULT port
+#endif
+
+/* port_cs enph */
+#ifndef R_PORT_PB_CONFIG__scsi1__DEFAULT
+#define R_PORT_PB_CONFIG__scsi1__DEFAULT port_cs
+#endif
+
+/* port_cs enph */
+#ifndef R_PORT_PB_CONFIG__scsi0__DEFAULT
+#define R_PORT_PB_CONFIG__scsi0__DEFAULT port_cs
+#endif
+
+/*
+** Default values for register R_PORT_PB_DATA
+*/
+
+/* 0 - 255 */
+#ifndef R_PORT_PB_DATA__data_out__DEFAULT
+#define R_PORT_PB_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_PORT_PB_DIR
+*/
+
+/* input output */
+#ifndef R_PORT_PB_DIR__dir7__DEFAULT
+#define R_PORT_PB_DIR__dir7__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_DIR__dir6__DEFAULT
+#define R_PORT_PB_DIR__dir6__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_DIR__dir5__DEFAULT
+#define R_PORT_PB_DIR__dir5__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_DIR__dir4__DEFAULT
+#define R_PORT_PB_DIR__dir4__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_DIR__dir3__DEFAULT
+#define R_PORT_PB_DIR__dir3__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_DIR__dir2__DEFAULT
+#define R_PORT_PB_DIR__dir2__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_DIR__dir1__DEFAULT
+#define R_PORT_PB_DIR__dir1__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_DIR__dir0__DEFAULT
+#define R_PORT_PB_DIR__dir0__DEFAULT input
+#endif
+
+/*
+** Default values for register R_PORT_PB_I2C
+*/
+
+/* port_cs ss3extra */
+#ifndef R_PORT_PB_I2C__syncser3__DEFAULT
+#define R_PORT_PB_I2C__syncser3__DEFAULT port_cs
+#endif
+
+/* port_cs ss1extra */
+#ifndef R_PORT_PB_I2C__syncser1__DEFAULT
+#define R_PORT_PB_I2C__syncser1__DEFAULT port_cs
+#endif
+
+/* off on */
+#ifndef R_PORT_PB_I2C__i2c_en__DEFAULT
+#define R_PORT_PB_I2C__i2c_en__DEFAULT off
+#endif
+
+/* 0 - 1 */
+#ifndef R_PORT_PB_I2C__i2c_d__DEFAULT
+#define R_PORT_PB_I2C__i2c_d__DEFAULT 0
+#endif
+
+/* 0 - 1 */
+#ifndef R_PORT_PB_I2C__i2c_clk__DEFAULT
+#define R_PORT_PB_I2C__i2c_clk__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_PORT_PB_I2C__i2c_oe___DEFAULT
+#define R_PORT_PB_I2C__i2c_oe___DEFAULT disable
+#endif
+
+/*
+** Default values for register R_PORT_PB_SET
+*/
+
+/* port_cs ss3extra */
+#ifndef R_PORT_PB_SET__syncser3__DEFAULT
+#define R_PORT_PB_SET__syncser3__DEFAULT port_cs
+#endif
+
+/* port_cs ss1extra */
+#ifndef R_PORT_PB_SET__syncser1__DEFAULT
+#define R_PORT_PB_SET__syncser1__DEFAULT port_cs
+#endif
+
+/* off on */
+#ifndef R_PORT_PB_SET__i2c_en__DEFAULT
+#define R_PORT_PB_SET__i2c_en__DEFAULT off
+#endif
+
+/* 0 - 1 */
+#ifndef R_PORT_PB_SET__i2c_d__DEFAULT
+#define R_PORT_PB_SET__i2c_d__DEFAULT 0
+#endif
+
+/* 0 - 1 */
+#ifndef R_PORT_PB_SET__i2c_clk__DEFAULT
+#define R_PORT_PB_SET__i2c_clk__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_PORT_PB_SET__i2c_oe___DEFAULT
+#define R_PORT_PB_SET__i2c_oe___DEFAULT disable
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_SET__cs7__DEFAULT
+#define R_PORT_PB_SET__cs7__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_SET__cs6__DEFAULT
+#define R_PORT_PB_SET__cs6__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_SET__cs5__DEFAULT
+#define R_PORT_PB_SET__cs5__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_SET__cs4__DEFAULT
+#define R_PORT_PB_SET__cs4__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_SET__cs3__DEFAULT
+#define R_PORT_PB_SET__cs3__DEFAULT port
+#endif
+
+/* port cs */
+#ifndef R_PORT_PB_SET__cs2__DEFAULT
+#define R_PORT_PB_SET__cs2__DEFAULT port
+#endif
+
+/* port_cs enph */
+#ifndef R_PORT_PB_SET__scsi1__DEFAULT
+#define R_PORT_PB_SET__scsi1__DEFAULT port_cs
+#endif
+
+/* port_cs enph */
+#ifndef R_PORT_PB_SET__scsi0__DEFAULT
+#define R_PORT_PB_SET__scsi0__DEFAULT port_cs
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_SET__dir7__DEFAULT
+#define R_PORT_PB_SET__dir7__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_SET__dir6__DEFAULT
+#define R_PORT_PB_SET__dir6__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_SET__dir5__DEFAULT
+#define R_PORT_PB_SET__dir5__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_SET__dir4__DEFAULT
+#define R_PORT_PB_SET__dir4__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_SET__dir3__DEFAULT
+#define R_PORT_PB_SET__dir3__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_SET__dir2__DEFAULT
+#define R_PORT_PB_SET__dir2__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_SET__dir1__DEFAULT
+#define R_PORT_PB_SET__dir1__DEFAULT input
+#endif
+
+/* input output */
+#ifndef R_PORT_PB_SET__dir0__DEFAULT
+#define R_PORT_PB_SET__dir0__DEFAULT input
+#endif
+
+/* 0 - 255 */
+#ifndef R_PORT_PB_SET__data_out__DEFAULT
+#define R_PORT_PB_SET__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SCSI0_CMD
+*/
+
+/* 0 - 0xf */
+#ifndef R_SCSI0_CMD__asynch_setup__DEFAULT
+#define R_SCSI0_CMD__asynch_setup__DEFAULT 0
+#endif
+
+/* full_stat_3 full_dout_3 man_rat resel_din arb_only resel_stat resel_dout man_data_in man_data_out full_din_1 full_dout_1 full_stat_1 full_din_3 */
+#ifndef R_SCSI0_CMD__command__DEFAULT
+#define R_SCSI0_CMD__command__DEFAULT full_stat_3
+#endif
+
+/*
+** Default values for register R_SCSI0_CMD_DATA
+*/
+
+/* off on */
+#ifndef R_SCSI0_CMD_DATA__parity_in__DEFAULT
+#define R_SCSI0_CMD_DATA__parity_in__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SCSI0_CMD_DATA__skip__DEFAULT
+#define R_SCSI0_CMD_DATA__skip__DEFAULT off
+#endif
+
+/* yes nop */
+#ifndef R_SCSI0_CMD_DATA__clr_status__DEFAULT
+#define R_SCSI0_CMD_DATA__clr_status__DEFAULT yes
+#endif
+
+/* 0 - 0xf */
+#ifndef R_SCSI0_CMD_DATA__asynch_setup__DEFAULT
+#define R_SCSI0_CMD_DATA__asynch_setup__DEFAULT 0
+#endif
+
+/* full_stat_3 full_dout_3 man_rat resel_din arb_only resel_stat resel_dout man_data_in man_data_out full_din_1 full_dout_1 full_stat_1 full_din_3 */
+#ifndef R_SCSI0_CMD_DATA__command__DEFAULT
+#define R_SCSI0_CMD_DATA__command__DEFAULT full_stat_3
+#endif
+
+/* 0 - 0xffff */
+#ifndef R_SCSI0_CMD_DATA__data_out__DEFAULT
+#define R_SCSI0_CMD_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SCSI0_CTRL
+*/
+
+/* software hardware */
+#ifndef R_SCSI0_CTRL__id_type__DEFAULT
+#define R_SCSI0_CTRL__id_type__DEFAULT software
+#endif
+
+/* 0 - 0x7f */
+#ifndef R_SCSI0_CTRL__sel_timeout__DEFAULT
+#define R_SCSI0_CTRL__sel_timeout__DEFAULT 0
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SCSI0_CTRL__synch_per__DEFAULT
+#define R_SCSI0_CTRL__synch_per__DEFAULT 0
+#endif
+
+/* yes no */
+#ifndef R_SCSI0_CTRL__rst__DEFAULT
+#define R_SCSI0_CTRL__rst__DEFAULT yes
+#endif
+
+/* yes no */
+#ifndef R_SCSI0_CTRL__atn__DEFAULT
+#define R_SCSI0_CTRL__atn__DEFAULT yes
+#endif
+
+/* 0 - 0xf */
+#ifndef R_SCSI0_CTRL__my_id__DEFAULT
+#define R_SCSI0_CTRL__my_id__DEFAULT 0
+#endif
+
+/* 0 - 0xf */
+#ifndef R_SCSI0_CTRL__target_id__DEFAULT
+#define R_SCSI0_CTRL__target_id__DEFAULT 0
+#endif
+
+/* yes no */
+#ifndef R_SCSI0_CTRL__fast_20__DEFAULT
+#define R_SCSI0_CTRL__fast_20__DEFAULT yes
+#endif
+
+/* narrow wide */
+#ifndef R_SCSI0_CTRL__bus_width__DEFAULT
+#define R_SCSI0_CTRL__bus_width__DEFAULT narrow
+#endif
+
+/* synch asynch */
+#ifndef R_SCSI0_CTRL__synch__DEFAULT
+#define R_SCSI0_CTRL__synch__DEFAULT synch
+#endif
+
+/* off on */
+#ifndef R_SCSI0_CTRL__enable__DEFAULT
+#define R_SCSI0_CTRL__enable__DEFAULT off
+#endif
+
+/*
+** Default values for register R_SCSI0_DATA
+*/
+
+/* 0 - 0xffff */
+#ifndef R_SCSI0_DATA__data_out__DEFAULT
+#define R_SCSI0_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SCSI0_STATUS_CTRL
+*/
+
+/* off on */
+#ifndef R_SCSI0_STATUS_CTRL__parity_in__DEFAULT
+#define R_SCSI0_STATUS_CTRL__parity_in__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SCSI0_STATUS_CTRL__skip__DEFAULT
+#define R_SCSI0_STATUS_CTRL__skip__DEFAULT off
+#endif
+
+/* yes nop */
+#ifndef R_SCSI0_STATUS_CTRL__clr_status__DEFAULT
+#define R_SCSI0_STATUS_CTRL__clr_status__DEFAULT yes
+#endif
+
+/*
+** Default values for register R_SCSI1_CMD
+*/
+
+/* 0 - 0xf */
+#ifndef R_SCSI1_CMD__asynch_setup__DEFAULT
+#define R_SCSI1_CMD__asynch_setup__DEFAULT 0
+#endif
+
+/* full_stat_3 full_dout_3 man_rat resel_din arb_only resel_stat resel_dout man_data_in man_data_out full_din_1 full_dout_1 full_stat_1 full_din_3 */
+#ifndef R_SCSI1_CMD__command__DEFAULT
+#define R_SCSI1_CMD__command__DEFAULT full_stat_3
+#endif
+
+/*
+** Default values for register R_SCSI1_CMD_DATA
+*/
+
+/* off on */
+#ifndef R_SCSI1_CMD_DATA__parity_in__DEFAULT
+#define R_SCSI1_CMD_DATA__parity_in__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SCSI1_CMD_DATA__skip__DEFAULT
+#define R_SCSI1_CMD_DATA__skip__DEFAULT off
+#endif
+
+/* yes nop */
+#ifndef R_SCSI1_CMD_DATA__clr_status__DEFAULT
+#define R_SCSI1_CMD_DATA__clr_status__DEFAULT yes
+#endif
+
+/* 0 - 0xf */
+#ifndef R_SCSI1_CMD_DATA__asynch_setup__DEFAULT
+#define R_SCSI1_CMD_DATA__asynch_setup__DEFAULT 0
+#endif
+
+/* full_stat_3 full_dout_3 man_rat resel_din arb_only resel_stat resel_dout man_data_in man_data_out full_din_1 full_dout_1 full_stat_1 full_din_3 */
+#ifndef R_SCSI1_CMD_DATA__command__DEFAULT
+#define R_SCSI1_CMD_DATA__command__DEFAULT full_stat_3
+#endif
+
+/* 0 - 0xffff */
+#ifndef R_SCSI1_CMD_DATA__data_out__DEFAULT
+#define R_SCSI1_CMD_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SCSI1_CTRL
+*/
+
+/* software hardware */
+#ifndef R_SCSI1_CTRL__id_type__DEFAULT
+#define R_SCSI1_CTRL__id_type__DEFAULT software
+#endif
+
+/* 0 - 0x7f */
+#ifndef R_SCSI1_CTRL__sel_timeout__DEFAULT
+#define R_SCSI1_CTRL__sel_timeout__DEFAULT 0
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SCSI1_CTRL__synch_per__DEFAULT
+#define R_SCSI1_CTRL__synch_per__DEFAULT 0
+#endif
+
+/* yes no */
+#ifndef R_SCSI1_CTRL__rst__DEFAULT
+#define R_SCSI1_CTRL__rst__DEFAULT yes
+#endif
+
+/* yes no */
+#ifndef R_SCSI1_CTRL__atn__DEFAULT
+#define R_SCSI1_CTRL__atn__DEFAULT yes
+#endif
+
+/* 0 - 0xf */
+#ifndef R_SCSI1_CTRL__my_id__DEFAULT
+#define R_SCSI1_CTRL__my_id__DEFAULT 0
+#endif
+
+/* 0 - 0xf */
+#ifndef R_SCSI1_CTRL__target_id__DEFAULT
+#define R_SCSI1_CTRL__target_id__DEFAULT 0
+#endif
+
+/* yes no */
+#ifndef R_SCSI1_CTRL__fast_20__DEFAULT
+#define R_SCSI1_CTRL__fast_20__DEFAULT yes
+#endif
+
+/* narrow wide */
+#ifndef R_SCSI1_CTRL__bus_width__DEFAULT
+#define R_SCSI1_CTRL__bus_width__DEFAULT narrow
+#endif
+
+/* synch asynch */
+#ifndef R_SCSI1_CTRL__synch__DEFAULT
+#define R_SCSI1_CTRL__synch__DEFAULT synch
+#endif
+
+/* off on */
+#ifndef R_SCSI1_CTRL__enable__DEFAULT
+#define R_SCSI1_CTRL__enable__DEFAULT off
+#endif
+
+/*
+** Default values for register R_SCSI1_DATA
+*/
+
+/* 0 - 0xffff */
+#ifndef R_SCSI1_DATA__data_out__DEFAULT
+#define R_SCSI1_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SCSI1_STATUS_CTRL
+*/
+
+/* off on */
+#ifndef R_SCSI1_STATUS_CTRL__parity_in__DEFAULT
+#define R_SCSI1_STATUS_CTRL__parity_in__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SCSI1_STATUS_CTRL__skip__DEFAULT
+#define R_SCSI1_STATUS_CTRL__skip__DEFAULT off
+#endif
+
+/* yes nop */
+#ifndef R_SCSI1_STATUS_CTRL__clr_status__DEFAULT
+#define R_SCSI1_STATUS_CTRL__clr_status__DEFAULT yes
+#endif
+
+/*
+** Default values for register R_SDRAM_CONFIG
+*/
+
+/* wmm norm */
+#ifndef R_SDRAM_CONFIG__wmm1__DEFAULT
+#define R_SDRAM_CONFIG__wmm1__DEFAULT wmm
+#endif
+
+/* wmm norm */
+#ifndef R_SDRAM_CONFIG__wmm0__DEFAULT
+#define R_SDRAM_CONFIG__wmm0__DEFAULT wmm
+#endif
+
+/* 0 - 7 */
+#ifndef R_SDRAM_CONFIG__sh1__DEFAULT
+#define R_SDRAM_CONFIG__sh1__DEFAULT 0
+#endif
+
+/* 0 - 7 */
+#ifndef R_SDRAM_CONFIG__sh0__DEFAULT
+#define R_SDRAM_CONFIG__sh0__DEFAULT 0
+#endif
+
+/* bw16 bw32 */
+#ifndef R_SDRAM_CONFIG__w__DEFAULT
+#define R_SDRAM_CONFIG__w__DEFAULT bw16
+#endif
+
+/* bank4 bank2 */
+#ifndef R_SDRAM_CONFIG__type1__DEFAULT
+#define R_SDRAM_CONFIG__type1__DEFAULT bank4
+#endif
+
+/* bank4 bank2 */
+#ifndef R_SDRAM_CONFIG__type0__DEFAULT
+#define R_SDRAM_CONFIG__type0__DEFAULT bank4
+#endif
+
+/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit9 bit28 bit19 grp0 bit29 grp1 */
+#ifndef R_SDRAM_CONFIG__group_sel__DEFAULT
+#define R_SDRAM_CONFIG__group_sel__DEFAULT bit10
+#endif
+
+/* 0 - 7 */
+#ifndef R_SDRAM_CONFIG__ca1__DEFAULT
+#define R_SDRAM_CONFIG__ca1__DEFAULT 0
+#endif
+
+/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit28 bit19 bit29 bit9 */
+#ifndef R_SDRAM_CONFIG__bank_sel1__DEFAULT
+#define R_SDRAM_CONFIG__bank_sel1__DEFAULT bit10
+#endif
+
+/* 0 - 7 */
+#ifndef R_SDRAM_CONFIG__ca0__DEFAULT
+#define R_SDRAM_CONFIG__ca0__DEFAULT 0
+#endif
+
+/* bit10 bit20 bit11 bit21 bit12 bit22 bit13 bit23 bit14 bit24 bit15 bit25 bit16 bit26 bit17 bit27 bit18 bit28 bit19 bit29 bit9 */
+#ifndef R_SDRAM_CONFIG__bank_sel0__DEFAULT
+#define R_SDRAM_CONFIG__bank_sel0__DEFAULT bit10
+#endif
+
+/*
+** Default values for register R_SDRAM_TIMING
+*/
+
+/* disable enable */
+#ifndef R_SDRAM_TIMING__sdram__DEFAULT
+#define R_SDRAM_TIMING__sdram__DEFAULT disable
+#endif
+
+/* 0 - 0x7fff */
+#ifndef R_SDRAM_TIMING__mrs_data__DEFAULT
+#define R_SDRAM_TIMING__mrs_data__DEFAULT 0
+#endif
+
+/* e6500ns e13us disable e52us */
+#ifndef R_SDRAM_TIMING__ref__DEFAULT
+#define R_SDRAM_TIMING__ref__DEFAULT e6500ns
+#endif
+
+/* off on */
+#ifndef R_SDRAM_TIMING__ddr__DEFAULT
+#define R_SDRAM_TIMING__ddr__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SDRAM_TIMING__clk100__DEFAULT
+#define R_SDRAM_TIMING__clk100__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SDRAM_TIMING__ps__DEFAULT
+#define R_SDRAM_TIMING__ps__DEFAULT off
+#endif
+
+/* mrs nop ref pre */
+#ifndef R_SDRAM_TIMING__cmd__DEFAULT
+#define R_SDRAM_TIMING__cmd__DEFAULT mrs
+#endif
+
+/* 0 - 1 */
+#ifndef R_SDRAM_TIMING__pde__DEFAULT
+#define R_SDRAM_TIMING__pde__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_SDRAM_TIMING__rc__DEFAULT
+#define R_SDRAM_TIMING__rc__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_SDRAM_TIMING__rp__DEFAULT
+#define R_SDRAM_TIMING__rp__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_SDRAM_TIMING__rcd__DEFAULT
+#define R_SDRAM_TIMING__rcd__DEFAULT 0
+#endif
+
+/* 0 - 2 */
+#ifndef R_SDRAM_TIMING__cl__DEFAULT
+#define R_SDRAM_TIMING__cl__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL0_BAUD
+*/
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL0_BAUD__tr_baud__DEFAULT
+#define R_SERIAL0_BAUD__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL0_BAUD__rec_baud__DEFAULT
+#define R_SERIAL0_BAUD__rec_baud__DEFAULT c4800Hz
+#endif
+
+/*
+** Default values for register R_SERIAL0_CTRL
+*/
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL0_CTRL__tr_baud__DEFAULT
+#define R_SERIAL0_CTRL__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL0_CTRL__rec_baud__DEFAULT
+#define R_SERIAL0_CTRL__rec_baud__DEFAULT c4800Hz
+#endif
+
+/* ignore stop */
+#ifndef R_SERIAL0_CTRL__dma_err__DEFAULT
+#define R_SERIAL0_CTRL__dma_err__DEFAULT ignore
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_CTRL__rec_enable__DEFAULT
+#define R_SERIAL0_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_SERIAL0_CTRL__rts___DEFAULT
+#define R_SERIAL0_CTRL__rts___DEFAULT inactive
+#endif
+
+/* majority middle */
+#ifndef R_SERIAL0_CTRL__sampling__DEFAULT
+#define R_SERIAL0_CTRL__sampling__DEFAULT majority
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL0_CTRL__rec_stick_par__DEFAULT
+#define R_SERIAL0_CTRL__rec_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL0_CTRL__rec_par__DEFAULT
+#define R_SERIAL0_CTRL__rec_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_CTRL__rec_par_en__DEFAULT
+#define R_SERIAL0_CTRL__rec_par_en__DEFAULT disable
+#endif
+
+/* rec_8bit rec_7bit */
+#ifndef R_SERIAL0_CTRL__rec_bitnr__DEFAULT
+#define R_SERIAL0_CTRL__rec_bitnr__DEFAULT rec_8bit
+#endif
+
+/* 0 - 0x1 */
+#ifndef R_SERIAL0_CTRL__txd__DEFAULT
+#define R_SERIAL0_CTRL__txd__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_CTRL__tr_enable__DEFAULT
+#define R_SERIAL0_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* disabled active */
+#ifndef R_SERIAL0_CTRL__auto_cts__DEFAULT
+#define R_SERIAL0_CTRL__auto_cts__DEFAULT disabled
+#endif
+
+/* one_bit two_bits */
+#ifndef R_SERIAL0_CTRL__stop_bits__DEFAULT
+#define R_SERIAL0_CTRL__stop_bits__DEFAULT one_bit
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL0_CTRL__tr_stick_par__DEFAULT
+#define R_SERIAL0_CTRL__tr_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL0_CTRL__tr_par__DEFAULT
+#define R_SERIAL0_CTRL__tr_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_CTRL__tr_par_en__DEFAULT
+#define R_SERIAL0_CTRL__tr_par_en__DEFAULT disable
+#endif
+
+/* tr_7bit tr_8bit */
+#ifndef R_SERIAL0_CTRL__tr_bitnr__DEFAULT
+#define R_SERIAL0_CTRL__tr_bitnr__DEFAULT tr_7bit
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SERIAL0_CTRL__data_out__DEFAULT
+#define R_SERIAL0_CTRL__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL0_REC_CTRL
+*/
+
+/* ignore stop */
+#ifndef R_SERIAL0_REC_CTRL__dma_err__DEFAULT
+#define R_SERIAL0_REC_CTRL__dma_err__DEFAULT ignore
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_REC_CTRL__rec_enable__DEFAULT
+#define R_SERIAL0_REC_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_SERIAL0_REC_CTRL__rts___DEFAULT
+#define R_SERIAL0_REC_CTRL__rts___DEFAULT inactive
+#endif
+
+/* majority middle */
+#ifndef R_SERIAL0_REC_CTRL__sampling__DEFAULT
+#define R_SERIAL0_REC_CTRL__sampling__DEFAULT majority
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL0_REC_CTRL__rec_stick_par__DEFAULT
+#define R_SERIAL0_REC_CTRL__rec_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL0_REC_CTRL__rec_par__DEFAULT
+#define R_SERIAL0_REC_CTRL__rec_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_REC_CTRL__rec_par_en__DEFAULT
+#define R_SERIAL0_REC_CTRL__rec_par_en__DEFAULT disable
+#endif
+
+/* rec_8bit rec_7bit */
+#ifndef R_SERIAL0_REC_CTRL__rec_bitnr__DEFAULT
+#define R_SERIAL0_REC_CTRL__rec_bitnr__DEFAULT rec_8bit
+#endif
+
+/*
+** Default values for register R_SERIAL0_TR_CTRL
+*/
+
+/* 0 - 0x1 */
+#ifndef R_SERIAL0_TR_CTRL__txd__DEFAULT
+#define R_SERIAL0_TR_CTRL__txd__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_TR_CTRL__tr_enable__DEFAULT
+#define R_SERIAL0_TR_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* disabled active */
+#ifndef R_SERIAL0_TR_CTRL__auto_cts__DEFAULT
+#define R_SERIAL0_TR_CTRL__auto_cts__DEFAULT disabled
+#endif
+
+/* one_bit two_bits */
+#ifndef R_SERIAL0_TR_CTRL__stop_bits__DEFAULT
+#define R_SERIAL0_TR_CTRL__stop_bits__DEFAULT one_bit
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL0_TR_CTRL__tr_stick_par__DEFAULT
+#define R_SERIAL0_TR_CTRL__tr_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL0_TR_CTRL__tr_par__DEFAULT
+#define R_SERIAL0_TR_CTRL__tr_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_TR_CTRL__tr_par_en__DEFAULT
+#define R_SERIAL0_TR_CTRL__tr_par_en__DEFAULT disable
+#endif
+
+/* tr_7bit tr_8bit */
+#ifndef R_SERIAL0_TR_CTRL__tr_bitnr__DEFAULT
+#define R_SERIAL0_TR_CTRL__tr_bitnr__DEFAULT tr_7bit
+#endif
+
+/*
+** Default values for register R_SERIAL0_TR_DATA
+*/
+
+/* 0 - 0xff */
+#ifndef R_SERIAL0_TR_DATA__data_out__DEFAULT
+#define R_SERIAL0_TR_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL0_XOFF
+*/
+
+/* stop enable */
+#ifndef R_SERIAL0_XOFF__tx_stop__DEFAULT
+#define R_SERIAL0_XOFF__tx_stop__DEFAULT stop
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL0_XOFF__auto_xoff__DEFAULT
+#define R_SERIAL0_XOFF__auto_xoff__DEFAULT disable
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SERIAL0_XOFF__xoff_char__DEFAULT
+#define R_SERIAL0_XOFF__xoff_char__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL1_BAUD
+*/
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL1_BAUD__tr_baud__DEFAULT
+#define R_SERIAL1_BAUD__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL1_BAUD__rec_baud__DEFAULT
+#define R_SERIAL1_BAUD__rec_baud__DEFAULT c4800Hz
+#endif
+
+/*
+** Default values for register R_SERIAL1_CTRL
+*/
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL1_CTRL__tr_baud__DEFAULT
+#define R_SERIAL1_CTRL__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL1_CTRL__rec_baud__DEFAULT
+#define R_SERIAL1_CTRL__rec_baud__DEFAULT c4800Hz
+#endif
+
+/* ignore stop */
+#ifndef R_SERIAL1_CTRL__dma_err__DEFAULT
+#define R_SERIAL1_CTRL__dma_err__DEFAULT ignore
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_CTRL__rec_enable__DEFAULT
+#define R_SERIAL1_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_SERIAL1_CTRL__rts___DEFAULT
+#define R_SERIAL1_CTRL__rts___DEFAULT inactive
+#endif
+
+/* majority middle */
+#ifndef R_SERIAL1_CTRL__sampling__DEFAULT
+#define R_SERIAL1_CTRL__sampling__DEFAULT majority
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL1_CTRL__rec_stick_par__DEFAULT
+#define R_SERIAL1_CTRL__rec_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL1_CTRL__rec_par__DEFAULT
+#define R_SERIAL1_CTRL__rec_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_CTRL__rec_par_en__DEFAULT
+#define R_SERIAL1_CTRL__rec_par_en__DEFAULT disable
+#endif
+
+/* rec_8bit rec_7bit */
+#ifndef R_SERIAL1_CTRL__rec_bitnr__DEFAULT
+#define R_SERIAL1_CTRL__rec_bitnr__DEFAULT rec_8bit
+#endif
+
+/* 0 - 0x1 */
+#ifndef R_SERIAL1_CTRL__txd__DEFAULT
+#define R_SERIAL1_CTRL__txd__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_CTRL__tr_enable__DEFAULT
+#define R_SERIAL1_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* disabled active */
+#ifndef R_SERIAL1_CTRL__auto_cts__DEFAULT
+#define R_SERIAL1_CTRL__auto_cts__DEFAULT disabled
+#endif
+
+/* one_bit two_bits */
+#ifndef R_SERIAL1_CTRL__stop_bits__DEFAULT
+#define R_SERIAL1_CTRL__stop_bits__DEFAULT one_bit
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL1_CTRL__tr_stick_par__DEFAULT
+#define R_SERIAL1_CTRL__tr_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL1_CTRL__tr_par__DEFAULT
+#define R_SERIAL1_CTRL__tr_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_CTRL__tr_par_en__DEFAULT
+#define R_SERIAL1_CTRL__tr_par_en__DEFAULT disable
+#endif
+
+/* tr_7bit tr_8bit */
+#ifndef R_SERIAL1_CTRL__tr_bitnr__DEFAULT
+#define R_SERIAL1_CTRL__tr_bitnr__DEFAULT tr_7bit
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SERIAL1_CTRL__data_out__DEFAULT
+#define R_SERIAL1_CTRL__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL1_REC_CTRL
+*/
+
+/* ignore stop */
+#ifndef R_SERIAL1_REC_CTRL__dma_err__DEFAULT
+#define R_SERIAL1_REC_CTRL__dma_err__DEFAULT ignore
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_REC_CTRL__rec_enable__DEFAULT
+#define R_SERIAL1_REC_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_SERIAL1_REC_CTRL__rts___DEFAULT
+#define R_SERIAL1_REC_CTRL__rts___DEFAULT inactive
+#endif
+
+/* majority middle */
+#ifndef R_SERIAL1_REC_CTRL__sampling__DEFAULT
+#define R_SERIAL1_REC_CTRL__sampling__DEFAULT majority
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL1_REC_CTRL__rec_stick_par__DEFAULT
+#define R_SERIAL1_REC_CTRL__rec_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL1_REC_CTRL__rec_par__DEFAULT
+#define R_SERIAL1_REC_CTRL__rec_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_REC_CTRL__rec_par_en__DEFAULT
+#define R_SERIAL1_REC_CTRL__rec_par_en__DEFAULT disable
+#endif
+
+/* rec_8bit rec_7bit */
+#ifndef R_SERIAL1_REC_CTRL__rec_bitnr__DEFAULT
+#define R_SERIAL1_REC_CTRL__rec_bitnr__DEFAULT rec_8bit
+#endif
+
+/*
+** Default values for register R_SERIAL1_TR_CTRL
+*/
+
+/* 0 - 0x1 */
+#ifndef R_SERIAL1_TR_CTRL__txd__DEFAULT
+#define R_SERIAL1_TR_CTRL__txd__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_TR_CTRL__tr_enable__DEFAULT
+#define R_SERIAL1_TR_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* disabled active */
+#ifndef R_SERIAL1_TR_CTRL__auto_cts__DEFAULT
+#define R_SERIAL1_TR_CTRL__auto_cts__DEFAULT disabled
+#endif
+
+/* one_bit two_bits */
+#ifndef R_SERIAL1_TR_CTRL__stop_bits__DEFAULT
+#define R_SERIAL1_TR_CTRL__stop_bits__DEFAULT one_bit
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL1_TR_CTRL__tr_stick_par__DEFAULT
+#define R_SERIAL1_TR_CTRL__tr_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL1_TR_CTRL__tr_par__DEFAULT
+#define R_SERIAL1_TR_CTRL__tr_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_TR_CTRL__tr_par_en__DEFAULT
+#define R_SERIAL1_TR_CTRL__tr_par_en__DEFAULT disable
+#endif
+
+/* tr_7bit tr_8bit */
+#ifndef R_SERIAL1_TR_CTRL__tr_bitnr__DEFAULT
+#define R_SERIAL1_TR_CTRL__tr_bitnr__DEFAULT tr_7bit
+#endif
+
+/*
+** Default values for register R_SERIAL1_TR_DATA
+*/
+
+/* 0 - 0xff */
+#ifndef R_SERIAL1_TR_DATA__data_out__DEFAULT
+#define R_SERIAL1_TR_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL1_XOFF
+*/
+
+/* stop enable */
+#ifndef R_SERIAL1_XOFF__tx_stop__DEFAULT
+#define R_SERIAL1_XOFF__tx_stop__DEFAULT stop
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL1_XOFF__auto_xoff__DEFAULT
+#define R_SERIAL1_XOFF__auto_xoff__DEFAULT disable
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SERIAL1_XOFF__xoff_char__DEFAULT
+#define R_SERIAL1_XOFF__xoff_char__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL2_BAUD
+*/
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL2_BAUD__tr_baud__DEFAULT
+#define R_SERIAL2_BAUD__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL2_BAUD__rec_baud__DEFAULT
+#define R_SERIAL2_BAUD__rec_baud__DEFAULT c4800Hz
+#endif
+
+/*
+** Default values for register R_SERIAL2_CTRL
+*/
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL2_CTRL__tr_baud__DEFAULT
+#define R_SERIAL2_CTRL__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL2_CTRL__rec_baud__DEFAULT
+#define R_SERIAL2_CTRL__rec_baud__DEFAULT c4800Hz
+#endif
+
+/* ignore stop */
+#ifndef R_SERIAL2_CTRL__dma_err__DEFAULT
+#define R_SERIAL2_CTRL__dma_err__DEFAULT ignore
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_CTRL__rec_enable__DEFAULT
+#define R_SERIAL2_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_SERIAL2_CTRL__rts___DEFAULT
+#define R_SERIAL2_CTRL__rts___DEFAULT inactive
+#endif
+
+/* majority middle */
+#ifndef R_SERIAL2_CTRL__sampling__DEFAULT
+#define R_SERIAL2_CTRL__sampling__DEFAULT majority
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL2_CTRL__rec_stick_par__DEFAULT
+#define R_SERIAL2_CTRL__rec_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL2_CTRL__rec_par__DEFAULT
+#define R_SERIAL2_CTRL__rec_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_CTRL__rec_par_en__DEFAULT
+#define R_SERIAL2_CTRL__rec_par_en__DEFAULT disable
+#endif
+
+/* rec_8bit rec_7bit */
+#ifndef R_SERIAL2_CTRL__rec_bitnr__DEFAULT
+#define R_SERIAL2_CTRL__rec_bitnr__DEFAULT rec_8bit
+#endif
+
+/* 0 - 0x1 */
+#ifndef R_SERIAL2_CTRL__txd__DEFAULT
+#define R_SERIAL2_CTRL__txd__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_CTRL__tr_enable__DEFAULT
+#define R_SERIAL2_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* disabled active */
+#ifndef R_SERIAL2_CTRL__auto_cts__DEFAULT
+#define R_SERIAL2_CTRL__auto_cts__DEFAULT disabled
+#endif
+
+/* one_bit two_bits */
+#ifndef R_SERIAL2_CTRL__stop_bits__DEFAULT
+#define R_SERIAL2_CTRL__stop_bits__DEFAULT one_bit
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL2_CTRL__tr_stick_par__DEFAULT
+#define R_SERIAL2_CTRL__tr_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL2_CTRL__tr_par__DEFAULT
+#define R_SERIAL2_CTRL__tr_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_CTRL__tr_par_en__DEFAULT
+#define R_SERIAL2_CTRL__tr_par_en__DEFAULT disable
+#endif
+
+/* tr_7bit tr_8bit */
+#ifndef R_SERIAL2_CTRL__tr_bitnr__DEFAULT
+#define R_SERIAL2_CTRL__tr_bitnr__DEFAULT tr_7bit
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SERIAL2_CTRL__data_out__DEFAULT
+#define R_SERIAL2_CTRL__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL2_REC_CTRL
+*/
+
+/* ignore stop */
+#ifndef R_SERIAL2_REC_CTRL__dma_err__DEFAULT
+#define R_SERIAL2_REC_CTRL__dma_err__DEFAULT ignore
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_REC_CTRL__rec_enable__DEFAULT
+#define R_SERIAL2_REC_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_SERIAL2_REC_CTRL__rts___DEFAULT
+#define R_SERIAL2_REC_CTRL__rts___DEFAULT inactive
+#endif
+
+/* majority middle */
+#ifndef R_SERIAL2_REC_CTRL__sampling__DEFAULT
+#define R_SERIAL2_REC_CTRL__sampling__DEFAULT majority
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL2_REC_CTRL__rec_stick_par__DEFAULT
+#define R_SERIAL2_REC_CTRL__rec_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL2_REC_CTRL__rec_par__DEFAULT
+#define R_SERIAL2_REC_CTRL__rec_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_REC_CTRL__rec_par_en__DEFAULT
+#define R_SERIAL2_REC_CTRL__rec_par_en__DEFAULT disable
+#endif
+
+/* rec_8bit rec_7bit */
+#ifndef R_SERIAL2_REC_CTRL__rec_bitnr__DEFAULT
+#define R_SERIAL2_REC_CTRL__rec_bitnr__DEFAULT rec_8bit
+#endif
+
+/*
+** Default values for register R_SERIAL2_TR_CTRL
+*/
+
+/* 0 - 0x1 */
+#ifndef R_SERIAL2_TR_CTRL__txd__DEFAULT
+#define R_SERIAL2_TR_CTRL__txd__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_TR_CTRL__tr_enable__DEFAULT
+#define R_SERIAL2_TR_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* disabled active */
+#ifndef R_SERIAL2_TR_CTRL__auto_cts__DEFAULT
+#define R_SERIAL2_TR_CTRL__auto_cts__DEFAULT disabled
+#endif
+
+/* one_bit two_bits */
+#ifndef R_SERIAL2_TR_CTRL__stop_bits__DEFAULT
+#define R_SERIAL2_TR_CTRL__stop_bits__DEFAULT one_bit
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL2_TR_CTRL__tr_stick_par__DEFAULT
+#define R_SERIAL2_TR_CTRL__tr_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL2_TR_CTRL__tr_par__DEFAULT
+#define R_SERIAL2_TR_CTRL__tr_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_TR_CTRL__tr_par_en__DEFAULT
+#define R_SERIAL2_TR_CTRL__tr_par_en__DEFAULT disable
+#endif
+
+/* tr_7bit tr_8bit */
+#ifndef R_SERIAL2_TR_CTRL__tr_bitnr__DEFAULT
+#define R_SERIAL2_TR_CTRL__tr_bitnr__DEFAULT tr_7bit
+#endif
+
+/*
+** Default values for register R_SERIAL2_TR_DATA
+*/
+
+/* 0 - 0xff */
+#ifndef R_SERIAL2_TR_DATA__data_out__DEFAULT
+#define R_SERIAL2_TR_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL2_XOFF
+*/
+
+/* stop enable */
+#ifndef R_SERIAL2_XOFF__tx_stop__DEFAULT
+#define R_SERIAL2_XOFF__tx_stop__DEFAULT stop
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL2_XOFF__auto_xoff__DEFAULT
+#define R_SERIAL2_XOFF__auto_xoff__DEFAULT disable
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SERIAL2_XOFF__xoff_char__DEFAULT
+#define R_SERIAL2_XOFF__xoff_char__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL3_BAUD
+*/
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL3_BAUD__tr_baud__DEFAULT
+#define R_SERIAL3_BAUD__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL3_BAUD__rec_baud__DEFAULT
+#define R_SERIAL3_BAUD__rec_baud__DEFAULT c4800Hz
+#endif
+
+/*
+** Default values for register R_SERIAL3_CTRL
+*/
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL3_CTRL__tr_baud__DEFAULT
+#define R_SERIAL3_CTRL__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_SERIAL3_CTRL__rec_baud__DEFAULT
+#define R_SERIAL3_CTRL__rec_baud__DEFAULT c4800Hz
+#endif
+
+/* ignore stop */
+#ifndef R_SERIAL3_CTRL__dma_err__DEFAULT
+#define R_SERIAL3_CTRL__dma_err__DEFAULT ignore
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_CTRL__rec_enable__DEFAULT
+#define R_SERIAL3_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_SERIAL3_CTRL__rts___DEFAULT
+#define R_SERIAL3_CTRL__rts___DEFAULT inactive
+#endif
+
+/* majority middle */
+#ifndef R_SERIAL3_CTRL__sampling__DEFAULT
+#define R_SERIAL3_CTRL__sampling__DEFAULT majority
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL3_CTRL__rec_stick_par__DEFAULT
+#define R_SERIAL3_CTRL__rec_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL3_CTRL__rec_par__DEFAULT
+#define R_SERIAL3_CTRL__rec_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_CTRL__rec_par_en__DEFAULT
+#define R_SERIAL3_CTRL__rec_par_en__DEFAULT disable
+#endif
+
+/* rec_8bit rec_7bit */
+#ifndef R_SERIAL3_CTRL__rec_bitnr__DEFAULT
+#define R_SERIAL3_CTRL__rec_bitnr__DEFAULT rec_8bit
+#endif
+
+/* 0 - 0x1 */
+#ifndef R_SERIAL3_CTRL__txd__DEFAULT
+#define R_SERIAL3_CTRL__txd__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_CTRL__tr_enable__DEFAULT
+#define R_SERIAL3_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* disabled active */
+#ifndef R_SERIAL3_CTRL__auto_cts__DEFAULT
+#define R_SERIAL3_CTRL__auto_cts__DEFAULT disabled
+#endif
+
+/* one_bit two_bits */
+#ifndef R_SERIAL3_CTRL__stop_bits__DEFAULT
+#define R_SERIAL3_CTRL__stop_bits__DEFAULT one_bit
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL3_CTRL__tr_stick_par__DEFAULT
+#define R_SERIAL3_CTRL__tr_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL3_CTRL__tr_par__DEFAULT
+#define R_SERIAL3_CTRL__tr_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_CTRL__tr_par_en__DEFAULT
+#define R_SERIAL3_CTRL__tr_par_en__DEFAULT disable
+#endif
+
+/* tr_7bit tr_8bit */
+#ifndef R_SERIAL3_CTRL__tr_bitnr__DEFAULT
+#define R_SERIAL3_CTRL__tr_bitnr__DEFAULT tr_7bit
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SERIAL3_CTRL__data_out__DEFAULT
+#define R_SERIAL3_CTRL__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL3_REC_CTRL
+*/
+
+/* ignore stop */
+#ifndef R_SERIAL3_REC_CTRL__dma_err__DEFAULT
+#define R_SERIAL3_REC_CTRL__dma_err__DEFAULT ignore
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_REC_CTRL__rec_enable__DEFAULT
+#define R_SERIAL3_REC_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* inactive active */
+#ifndef R_SERIAL3_REC_CTRL__rts___DEFAULT
+#define R_SERIAL3_REC_CTRL__rts___DEFAULT inactive
+#endif
+
+/* majority middle */
+#ifndef R_SERIAL3_REC_CTRL__sampling__DEFAULT
+#define R_SERIAL3_REC_CTRL__sampling__DEFAULT majority
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL3_REC_CTRL__rec_stick_par__DEFAULT
+#define R_SERIAL3_REC_CTRL__rec_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL3_REC_CTRL__rec_par__DEFAULT
+#define R_SERIAL3_REC_CTRL__rec_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_REC_CTRL__rec_par_en__DEFAULT
+#define R_SERIAL3_REC_CTRL__rec_par_en__DEFAULT disable
+#endif
+
+/* rec_8bit rec_7bit */
+#ifndef R_SERIAL3_REC_CTRL__rec_bitnr__DEFAULT
+#define R_SERIAL3_REC_CTRL__rec_bitnr__DEFAULT rec_8bit
+#endif
+
+/*
+** Default values for register R_SERIAL3_TR_CTRL
+*/
+
+/* 0 - 0x1 */
+#ifndef R_SERIAL3_TR_CTRL__txd__DEFAULT
+#define R_SERIAL3_TR_CTRL__txd__DEFAULT 0
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_TR_CTRL__tr_enable__DEFAULT
+#define R_SERIAL3_TR_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* disabled active */
+#ifndef R_SERIAL3_TR_CTRL__auto_cts__DEFAULT
+#define R_SERIAL3_TR_CTRL__auto_cts__DEFAULT disabled
+#endif
+
+/* one_bit two_bits */
+#ifndef R_SERIAL3_TR_CTRL__stop_bits__DEFAULT
+#define R_SERIAL3_TR_CTRL__stop_bits__DEFAULT one_bit
+#endif
+
+/* normal stick */
+#ifndef R_SERIAL3_TR_CTRL__tr_stick_par__DEFAULT
+#define R_SERIAL3_TR_CTRL__tr_stick_par__DEFAULT normal
+#endif
+
+/* even odd */
+#ifndef R_SERIAL3_TR_CTRL__tr_par__DEFAULT
+#define R_SERIAL3_TR_CTRL__tr_par__DEFAULT even
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_TR_CTRL__tr_par_en__DEFAULT
+#define R_SERIAL3_TR_CTRL__tr_par_en__DEFAULT disable
+#endif
+
+/* tr_7bit tr_8bit */
+#ifndef R_SERIAL3_TR_CTRL__tr_bitnr__DEFAULT
+#define R_SERIAL3_TR_CTRL__tr_bitnr__DEFAULT tr_7bit
+#endif
+
+/*
+** Default values for register R_SERIAL3_TR_DATA
+*/
+
+/* 0 - 0xff */
+#ifndef R_SERIAL3_TR_DATA__data_out__DEFAULT
+#define R_SERIAL3_TR_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL3_XOFF
+*/
+
+/* stop enable */
+#ifndef R_SERIAL3_XOFF__tx_stop__DEFAULT
+#define R_SERIAL3_XOFF__tx_stop__DEFAULT stop
+#endif
+
+/* disable enable */
+#ifndef R_SERIAL3_XOFF__auto_xoff__DEFAULT
+#define R_SERIAL3_XOFF__auto_xoff__DEFAULT disable
+#endif
+
+/* 0 - 0xff */
+#ifndef R_SERIAL3_XOFF__xoff_char__DEFAULT
+#define R_SERIAL3_XOFF__xoff_char__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SERIAL_PRESCALE
+*/
+
+/* 0 - 0xffff */
+#ifndef R_SERIAL_PRESCALE__ser_presc__DEFAULT
+#define R_SERIAL_PRESCALE__ser_presc__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SET_EOP
+*/
+
+/* set nop */
+#ifndef R_SET_EOP__ch9_eop__DEFAULT
+#define R_SET_EOP__ch9_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_SET_EOP__ch7_eop__DEFAULT
+#define R_SET_EOP__ch7_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_SET_EOP__ch5_eop__DEFAULT
+#define R_SET_EOP__ch5_eop__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_SET_EOP__ch3_eop__DEFAULT
+#define R_SET_EOP__ch3_eop__DEFAULT set
+#endif
+
+/*
+** Default values for register R_SHARED_RAM_ADDR
+*/
+
+/* 0 - 0x3fffff */
+#ifndef R_SHARED_RAM_ADDR__base_addr__DEFAULT
+#define R_SHARED_RAM_ADDR__base_addr__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SHARED_RAM_CONFIG
+*/
+
+/* word byte */
+#ifndef R_SHARED_RAM_CONFIG__width__DEFAULT
+#define R_SHARED_RAM_CONFIG__width__DEFAULT word
+#endif
+
+/* yes no */
+#ifndef R_SHARED_RAM_CONFIG__enable__DEFAULT
+#define R_SHARED_RAM_CONFIG__enable__DEFAULT yes
+#endif
+
+/* int nop */
+#ifndef R_SHARED_RAM_CONFIG__pint__DEFAULT
+#define R_SHARED_RAM_CONFIG__pint__DEFAULT int
+#endif
+
+/* clr nop */
+#ifndef R_SHARED_RAM_CONFIG__clri__DEFAULT
+#define R_SHARED_RAM_CONFIG__clri__DEFAULT clr
+#endif
+
+/*
+** Default values for register R_SINGLE_STEP
+*/
+
+/* off on */
+#ifndef R_SINGLE_STEP__single_step__DEFAULT
+#define R_SINGLE_STEP__single_step__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SINGLE_STEP__step_wr__DEFAULT
+#define R_SINGLE_STEP__step_wr__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SINGLE_STEP__step_rd__DEFAULT
+#define R_SINGLE_STEP__step_rd__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_SINGLE_STEP__step_fetch__DEFAULT
+#define R_SINGLE_STEP__step_fetch__DEFAULT off
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL1_CTRL
+*/
+
+/* c4800Hz c921k6Hz c460k8Hz c57k6Hz c28k8Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c3125kHz c150Hz c600Hz c2400Hz c19k2Hz */
+#ifndef R_SYNC_SERIAL1_CTRL__tr_baud__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* off on */
+#ifndef R_SYNC_SERIAL1_CTRL__dma_enable__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__dma_enable__DEFAULT off
+#endif
+
+/* slave_input master_input slave_output slave_bidir master_output master_bidir */
+#ifndef R_SYNC_SERIAL1_CTRL__mode__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__mode__DEFAULT slave_input
+#endif
+
+/* normal ignore */
+#ifndef R_SYNC_SERIAL1_CTRL__error__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__error__DEFAULT normal
+#endif
+
+/* disable enable */
+#ifndef R_SYNC_SERIAL1_CTRL__rec_enable__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* normal early */
+#ifndef R_SYNC_SERIAL1_CTRL__f_synctype__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__f_synctype__DEFAULT normal
+#endif
+
+/* extended word bit */
+#ifndef R_SYNC_SERIAL1_CTRL__f_syncsize__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__DEFAULT extended
+#endif
+
+/* off on */
+#ifndef R_SYNC_SERIAL1_CTRL__f_sync__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__f_sync__DEFAULT off
+#endif
+
+/* normal gated */
+#ifndef R_SYNC_SERIAL1_CTRL__clk_mode__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__clk_mode__DEFAULT normal
+#endif
+
+/* running stopped */
+#ifndef R_SYNC_SERIAL1_CTRL__clk_halt__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__clk_halt__DEFAULT running
+#endif
+
+/* lsb msb */
+#ifndef R_SYNC_SERIAL1_CTRL__bitorder__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__bitorder__DEFAULT lsb
+#endif
+
+/* disable enable */
+#ifndef R_SYNC_SERIAL1_CTRL__tr_enable__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* size24bit size16bit size8bit size12bit size32bit */
+#ifndef R_SYNC_SERIAL1_CTRL__wordsize__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__wordsize__DEFAULT size24bit
+#endif
+
+/* lmt_0 lmt_8 */
+#ifndef R_SYNC_SERIAL1_CTRL__buf_empty__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__buf_empty__DEFAULT lmt_0
+#endif
+
+/* lmt_32 lmt_8 */
+#ifndef R_SYNC_SERIAL1_CTRL__buf_full__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__buf_full__DEFAULT lmt_32
+#endif
+
+/* disabled enabled */
+#ifndef R_SYNC_SERIAL1_CTRL__flow_ctrl__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__DEFAULT disabled
+#endif
+
+/* neg pos */
+#ifndef R_SYNC_SERIAL1_CTRL__clk_polarity__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__DEFAULT neg
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL1_CTRL__frame_polarity__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__DEFAULT inverted
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL1_CTRL__status_polarity__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__status_polarity__DEFAULT inverted
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL1_CTRL__clk_driver__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__clk_driver__DEFAULT inverted
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL1_CTRL__frame_driver__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__frame_driver__DEFAULT inverted
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL1_CTRL__status_driver__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__status_driver__DEFAULT inverted
+#endif
+
+/* high low */
+#ifndef R_SYNC_SERIAL1_CTRL__def_out0__DEFAULT
+#define R_SYNC_SERIAL1_CTRL__def_out0__DEFAULT high
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL1_TR_BYTE
+*/
+
+/* 0 - 0xff */
+#ifndef R_SYNC_SERIAL1_TR_BYTE__data_out__DEFAULT
+#define R_SYNC_SERIAL1_TR_BYTE__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL1_TR_DATA
+*/
+
+/* 0 - 0xffffffff */
+#ifndef R_SYNC_SERIAL1_TR_DATA__data_out__DEFAULT
+#define R_SYNC_SERIAL1_TR_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL1_TR_WORD
+*/
+
+/* 0 - 0xffff */
+#ifndef R_SYNC_SERIAL1_TR_WORD__data_out__DEFAULT
+#define R_SYNC_SERIAL1_TR_WORD__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL3_CTRL
+*/
+
+/* c4800Hz c921k6Hz c460k8Hz c57k6Hz c28k8Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c3125kHz c150Hz c600Hz c2400Hz c19k2Hz */
+#ifndef R_SYNC_SERIAL3_CTRL__tr_baud__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__tr_baud__DEFAULT c4800Hz
+#endif
+
+/* off on */
+#ifndef R_SYNC_SERIAL3_CTRL__dma_enable__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__dma_enable__DEFAULT off
+#endif
+
+/* slave_input master_input slave_output slave_bidir master_output master_bidir */
+#ifndef R_SYNC_SERIAL3_CTRL__mode__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__mode__DEFAULT slave_input
+#endif
+
+/* normal ignore */
+#ifndef R_SYNC_SERIAL3_CTRL__error__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__error__DEFAULT normal
+#endif
+
+/* disable enable */
+#ifndef R_SYNC_SERIAL3_CTRL__rec_enable__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__rec_enable__DEFAULT disable
+#endif
+
+/* normal early */
+#ifndef R_SYNC_SERIAL3_CTRL__f_synctype__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__f_synctype__DEFAULT normal
+#endif
+
+/* extended word bit */
+#ifndef R_SYNC_SERIAL3_CTRL__f_syncsize__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__DEFAULT extended
+#endif
+
+/* off on */
+#ifndef R_SYNC_SERIAL3_CTRL__f_sync__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__f_sync__DEFAULT off
+#endif
+
+/* normal gated */
+#ifndef R_SYNC_SERIAL3_CTRL__clk_mode__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__clk_mode__DEFAULT normal
+#endif
+
+/* running stopped */
+#ifndef R_SYNC_SERIAL3_CTRL__clk_halt__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__clk_halt__DEFAULT running
+#endif
+
+/* lsb msb */
+#ifndef R_SYNC_SERIAL3_CTRL__bitorder__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__bitorder__DEFAULT lsb
+#endif
+
+/* disable enable */
+#ifndef R_SYNC_SERIAL3_CTRL__tr_enable__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__tr_enable__DEFAULT disable
+#endif
+
+/* size24bit size16bit size8bit size12bit size32bit */
+#ifndef R_SYNC_SERIAL3_CTRL__wordsize__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__wordsize__DEFAULT size24bit
+#endif
+
+/* lmt_0 lmt_8 */
+#ifndef R_SYNC_SERIAL3_CTRL__buf_empty__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__buf_empty__DEFAULT lmt_0
+#endif
+
+/* lmt_32 lmt_8 */
+#ifndef R_SYNC_SERIAL3_CTRL__buf_full__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__buf_full__DEFAULT lmt_32
+#endif
+
+/* disabled enabled */
+#ifndef R_SYNC_SERIAL3_CTRL__flow_ctrl__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__DEFAULT disabled
+#endif
+
+/* neg pos */
+#ifndef R_SYNC_SERIAL3_CTRL__clk_polarity__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__DEFAULT neg
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL3_CTRL__frame_polarity__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__DEFAULT inverted
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL3_CTRL__status_polarity__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__status_polarity__DEFAULT inverted
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL3_CTRL__clk_driver__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__clk_driver__DEFAULT inverted
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL3_CTRL__frame_driver__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__frame_driver__DEFAULT inverted
+#endif
+
+/* inverted normal */
+#ifndef R_SYNC_SERIAL3_CTRL__status_driver__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__status_driver__DEFAULT inverted
+#endif
+
+/* high low */
+#ifndef R_SYNC_SERIAL3_CTRL__def_out0__DEFAULT
+#define R_SYNC_SERIAL3_CTRL__def_out0__DEFAULT high
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL3_TR_BYTE
+*/
+
+/* 0 - 0xff */
+#ifndef R_SYNC_SERIAL3_TR_BYTE__data_out__DEFAULT
+#define R_SYNC_SERIAL3_TR_BYTE__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL3_TR_DATA
+*/
+
+/* 0 - 0xffffffff */
+#ifndef R_SYNC_SERIAL3_TR_DATA__data_out__DEFAULT
+#define R_SYNC_SERIAL3_TR_DATA__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL3_TR_WORD
+*/
+
+/* 0 - 0xffff */
+#ifndef R_SYNC_SERIAL3_TR_WORD__data_out__DEFAULT
+#define R_SYNC_SERIAL3_TR_WORD__data_out__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_SYNC_SERIAL_PRESCALE
+*/
+
+/* baudrate codec */
+#ifndef R_SYNC_SERIAL_PRESCALE__clk_sel_u3__DEFAULT
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__DEFAULT baudrate
+#endif
+
+/* external internal */
+#ifndef R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__DEFAULT
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__DEFAULT external
+#endif
+
+/* baudrate codec */
+#ifndef R_SYNC_SERIAL_PRESCALE__clk_sel_u1__DEFAULT
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__DEFAULT baudrate
+#endif
+
+/* external internal */
+#ifndef R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__DEFAULT
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__DEFAULT external
+#endif
+
+/* div1 div2 div4 div32 div16 div8 div64 div128 */
+#ifndef R_SYNC_SERIAL_PRESCALE__prescaler__DEFAULT
+#define R_SYNC_SERIAL_PRESCALE__prescaler__DEFAULT div1
+#endif
+
+/* normal enabled */
+#ifndef R_SYNC_SERIAL_PRESCALE__warp_mode__DEFAULT
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__DEFAULT normal
+#endif
+
+/* 0 - 0xf */
+#ifndef R_SYNC_SERIAL_PRESCALE__frame_rate__DEFAULT
+#define R_SYNC_SERIAL_PRESCALE__frame_rate__DEFAULT 0
+#endif
+
+/* 0 - 0x3ff */
+#ifndef R_SYNC_SERIAL_PRESCALE__word_rate__DEFAULT
+#define R_SYNC_SERIAL_PRESCALE__word_rate__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_TEST_MODE
+*/
+
+/* off on */
+#ifndef R_TEST_MODE__single_step__DEFAULT
+#define R_TEST_MODE__single_step__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__step_wr__DEFAULT
+#define R_TEST_MODE__step_wr__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__step_rd__DEFAULT
+#define R_TEST_MODE__step_rd__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__step_fetch__DEFAULT
+#define R_TEST_MODE__step_fetch__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__mmu_test__DEFAULT
+#define R_TEST_MODE__mmu_test__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__usb_test__DEFAULT
+#define R_TEST_MODE__usb_test__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__scsi_timer_test__DEFAULT
+#define R_TEST_MODE__scsi_timer_test__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__backoff__DEFAULT
+#define R_TEST_MODE__backoff__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__snmp_test__DEFAULT
+#define R_TEST_MODE__snmp_test__DEFAULT off
+#endif
+
+/* do dont */
+#ifndef R_TEST_MODE__snmp_inc__DEFAULT
+#define R_TEST_MODE__snmp_inc__DEFAULT do
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__ser_loop__DEFAULT
+#define R_TEST_MODE__ser_loop__DEFAULT off
+#endif
+
+/* off on */
+#ifndef R_TEST_MODE__baudrate__DEFAULT
+#define R_TEST_MODE__baudrate__DEFAULT off
+#endif
+
+/* all off even odd */
+#ifndef R_TEST_MODE__timer__DEFAULT
+#define R_TEST_MODE__timer__DEFAULT all
+#endif
+
+/* test normal */
+#ifndef R_TEST_MODE__cache_test__DEFAULT
+#define R_TEST_MODE__cache_test__DEFAULT test
+#endif
+
+/* test normal */
+#ifndef R_TEST_MODE__tag_test__DEFAULT
+#define R_TEST_MODE__tag_test__DEFAULT test
+#endif
+
+/* disable enable */
+#ifndef R_TEST_MODE__cache_enable__DEFAULT
+#define R_TEST_MODE__cache_enable__DEFAULT disable
+#endif
+
+/*
+** Default values for register R_TIMER_CTRL
+*/
+
+/* 0 - 0xff */
+#ifndef R_TIMER_CTRL__timerdiv1__DEFAULT
+#define R_TIMER_CTRL__timerdiv1__DEFAULT 0
+#endif
+
+/* 0 - 0xff */
+#ifndef R_TIMER_CTRL__timerdiv0__DEFAULT
+#define R_TIMER_CTRL__timerdiv0__DEFAULT 0
+#endif
+
+/* normal prescale */
+#ifndef R_TIMER_CTRL__presc_timer1__DEFAULT
+#define R_TIMER_CTRL__presc_timer1__DEFAULT normal
+#endif
+
+/* clr nop */
+#ifndef R_TIMER_CTRL__i1__DEFAULT
+#define R_TIMER_CTRL__i1__DEFAULT clr
+#endif
+
+/* freeze run stop_ld */
+#ifndef R_TIMER_CTRL__tm1__DEFAULT
+#define R_TIMER_CTRL__tm1__DEFAULT freeze
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz cascade0 c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_TIMER_CTRL__clksel1__DEFAULT
+#define R_TIMER_CTRL__clksel1__DEFAULT c4800Hz
+#endif
+
+/* external prescale */
+#ifndef R_TIMER_CTRL__presc_ext__DEFAULT
+#define R_TIMER_CTRL__presc_ext__DEFAULT external
+#endif
+
+/* clr nop */
+#ifndef R_TIMER_CTRL__i0__DEFAULT
+#define R_TIMER_CTRL__i0__DEFAULT clr
+#endif
+
+/* freeze run stop_ld */
+#ifndef R_TIMER_CTRL__tm0__DEFAULT
+#define R_TIMER_CTRL__tm0__DEFAULT freeze
+#endif
+
+/* c4800Hz c1843k2Hz c921k6Hz c460k8Hz c57k6Hz c9600Hz c300Hz c1200Hz c230k4Hz c115k2Hz flexible c600Hz c2400Hz c19k2Hz c6250kHz c38k4Hz */
+#ifndef R_TIMER_CTRL__clksel0__DEFAULT
+#define R_TIMER_CTRL__clksel0__DEFAULT c4800Hz
+#endif
+
+/*
+** Default values for register R_TIMER_PRESCALE
+*/
+
+/* 0 - 0xffff */
+#ifndef R_TIMER_PRESCALE__tim_presc__DEFAULT
+#define R_TIMER_PRESCALE__tim_presc__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_USB_IRQ_MASK_CLR
+*/
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__iso_eof__DEFAULT
+#define R_USB_IRQ_MASK_CLR__iso_eof__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__intr_eof__DEFAULT
+#define R_USB_IRQ_MASK_CLR__intr_eof__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__iso_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR__iso_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__intr_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR__intr_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__ctl_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR__ctl_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__bulk_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR__bulk_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__epid_attn__DEFAULT
+#define R_USB_IRQ_MASK_CLR__epid_attn__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__sof__DEFAULT
+#define R_USB_IRQ_MASK_CLR__sof__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__port_status__DEFAULT
+#define R_USB_IRQ_MASK_CLR__port_status__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR__ctl_status__DEFAULT
+#define R_USB_IRQ_MASK_CLR__ctl_status__DEFAULT clr
+#endif
+
+/*
+** Default values for register R_USB_IRQ_MASK_CLR_DEV
+*/
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__out_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__epid_attn__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__sof__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__sof__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__port_status__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_USB_IRQ_MASK_CLR_DEV__ctl_status__DEFAULT
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__DEFAULT clr
+#endif
+
+/*
+** Default values for register R_USB_IRQ_MASK_SET
+*/
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__iso_eof__DEFAULT
+#define R_USB_IRQ_MASK_SET__iso_eof__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__intr_eof__DEFAULT
+#define R_USB_IRQ_MASK_SET__intr_eof__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__iso_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET__iso_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__intr_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET__intr_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__ctl_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET__ctl_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__bulk_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET__bulk_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__epid_attn__DEFAULT
+#define R_USB_IRQ_MASK_SET__epid_attn__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__sof__DEFAULT
+#define R_USB_IRQ_MASK_SET__sof__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__port_status__DEFAULT
+#define R_USB_IRQ_MASK_SET__port_status__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET__ctl_status__DEFAULT
+#define R_USB_IRQ_MASK_SET__ctl_status__DEFAULT set
+#endif
+
+/*
+** Default values for register R_USB_IRQ_MASK_SET_DEV
+*/
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__out_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__epid_attn__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__sof__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__sof__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__port_status__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__port_status__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_USB_IRQ_MASK_SET_DEV__ctl_status__DEFAULT
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__DEFAULT set
+#endif
+
+/*
+** Default values for register R_USB_PORT1_DISABLE
+*/
+
+/* yes no */
+#ifndef R_USB_PORT1_DISABLE__disable__DEFAULT
+#define R_USB_PORT1_DISABLE__disable__DEFAULT yes
+#endif
+
+/*
+** Default values for register R_USB_PORT2_DISABLE
+*/
+
+/* yes no */
+#ifndef R_USB_PORT2_DISABLE__disable__DEFAULT
+#define R_USB_PORT2_DISABLE__disable__DEFAULT yes
+#endif
+
+/*
+** Default values for register R_VECT_MASK_CLR
+*/
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__usb__DEFAULT
+#define R_VECT_MASK_CLR__usb__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma9__DEFAULT
+#define R_VECT_MASK_CLR__dma9__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma8__DEFAULT
+#define R_VECT_MASK_CLR__dma8__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma7__DEFAULT
+#define R_VECT_MASK_CLR__dma7__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma6__DEFAULT
+#define R_VECT_MASK_CLR__dma6__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma5__DEFAULT
+#define R_VECT_MASK_CLR__dma5__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma4__DEFAULT
+#define R_VECT_MASK_CLR__dma4__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma3__DEFAULT
+#define R_VECT_MASK_CLR__dma3__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma2__DEFAULT
+#define R_VECT_MASK_CLR__dma2__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma1__DEFAULT
+#define R_VECT_MASK_CLR__dma1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__dma0__DEFAULT
+#define R_VECT_MASK_CLR__dma0__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__ext_dma1__DEFAULT
+#define R_VECT_MASK_CLR__ext_dma1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__ext_dma0__DEFAULT
+#define R_VECT_MASK_CLR__ext_dma0__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__pa__DEFAULT
+#define R_VECT_MASK_CLR__pa__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__irq_intnr__DEFAULT
+#define R_VECT_MASK_CLR__irq_intnr__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__sw__DEFAULT
+#define R_VECT_MASK_CLR__sw__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__serial__DEFAULT
+#define R_VECT_MASK_CLR__serial__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__snmp__DEFAULT
+#define R_VECT_MASK_CLR__snmp__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__network__DEFAULT
+#define R_VECT_MASK_CLR__network__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__scsi1__DEFAULT
+#define R_VECT_MASK_CLR__scsi1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__scsi0__DEFAULT
+#define R_VECT_MASK_CLR__scsi0__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__timer1__DEFAULT
+#define R_VECT_MASK_CLR__timer1__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__timer0__DEFAULT
+#define R_VECT_MASK_CLR__timer0__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__nmi__DEFAULT
+#define R_VECT_MASK_CLR__nmi__DEFAULT clr
+#endif
+
+/* clr nop */
+#ifndef R_VECT_MASK_CLR__some__DEFAULT
+#define R_VECT_MASK_CLR__some__DEFAULT clr
+#endif
+
+/*
+** Default values for register R_VECT_MASK_SET
+*/
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__usb__DEFAULT
+#define R_VECT_MASK_SET__usb__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma9__DEFAULT
+#define R_VECT_MASK_SET__dma9__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma8__DEFAULT
+#define R_VECT_MASK_SET__dma8__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma7__DEFAULT
+#define R_VECT_MASK_SET__dma7__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma6__DEFAULT
+#define R_VECT_MASK_SET__dma6__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma5__DEFAULT
+#define R_VECT_MASK_SET__dma5__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma4__DEFAULT
+#define R_VECT_MASK_SET__dma4__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma3__DEFAULT
+#define R_VECT_MASK_SET__dma3__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma2__DEFAULT
+#define R_VECT_MASK_SET__dma2__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma1__DEFAULT
+#define R_VECT_MASK_SET__dma1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__dma0__DEFAULT
+#define R_VECT_MASK_SET__dma0__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__ext_dma1__DEFAULT
+#define R_VECT_MASK_SET__ext_dma1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__ext_dma0__DEFAULT
+#define R_VECT_MASK_SET__ext_dma0__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__pa__DEFAULT
+#define R_VECT_MASK_SET__pa__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__irq_intnr__DEFAULT
+#define R_VECT_MASK_SET__irq_intnr__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__sw__DEFAULT
+#define R_VECT_MASK_SET__sw__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__serial__DEFAULT
+#define R_VECT_MASK_SET__serial__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__snmp__DEFAULT
+#define R_VECT_MASK_SET__snmp__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__network__DEFAULT
+#define R_VECT_MASK_SET__network__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__scsi1__DEFAULT
+#define R_VECT_MASK_SET__scsi1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__scsi0__DEFAULT
+#define R_VECT_MASK_SET__scsi0__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__timer1__DEFAULT
+#define R_VECT_MASK_SET__timer1__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__timer0__DEFAULT
+#define R_VECT_MASK_SET__timer0__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__nmi__DEFAULT
+#define R_VECT_MASK_SET__nmi__DEFAULT set
+#endif
+
+/* set nop */
+#ifndef R_VECT_MASK_SET__some__DEFAULT
+#define R_VECT_MASK_SET__some__DEFAULT set
+#endif
+
+/*
+** Default values for register R_WAITSTATES
+*/
+
+/* 0 - 3 */
+#ifndef R_WAITSTATES__pcs4_7_zw__DEFAULT
+#define R_WAITSTATES__pcs4_7_zw__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_WAITSTATES__pcs4_7_ew__DEFAULT
+#define R_WAITSTATES__pcs4_7_ew__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_WAITSTATES__pcs4_7_lw__DEFAULT
+#define R_WAITSTATES__pcs4_7_lw__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_WAITSTATES__pcs0_3_zw__DEFAULT
+#define R_WAITSTATES__pcs0_3_zw__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_WAITSTATES__pcs0_3_ew__DEFAULT
+#define R_WAITSTATES__pcs0_3_ew__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_WAITSTATES__pcs0_3_lw__DEFAULT
+#define R_WAITSTATES__pcs0_3_lw__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_WAITSTATES__sram_zw__DEFAULT
+#define R_WAITSTATES__sram_zw__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_WAITSTATES__sram_ew__DEFAULT
+#define R_WAITSTATES__sram_ew__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_WAITSTATES__sram_lw__DEFAULT
+#define R_WAITSTATES__sram_lw__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_WAITSTATES__flash_zw__DEFAULT
+#define R_WAITSTATES__flash_zw__DEFAULT 0
+#endif
+
+/* 0 - 3 */
+#ifndef R_WAITSTATES__flash_ew__DEFAULT
+#define R_WAITSTATES__flash_ew__DEFAULT 0
+#endif
+
+/* 0 - 15 */
+#ifndef R_WAITSTATES__flash_lw__DEFAULT
+#define R_WAITSTATES__flash_lw__DEFAULT 0
+#endif
+
+/*
+** Default values for register R_WATCHDOG
+*/
+
+/* 0 - 7 */
+#ifndef R_WATCHDOG__key__DEFAULT
+#define R_WATCHDOG__key__DEFAULT 0
+#endif
+
+/* start stop */
+#ifndef R_WATCHDOG__enable__DEFAULT
+#define R_WATCHDOG__enable__DEFAULT start
+#endif
+
+/********************** TYPE DEFINITION SECTION ************************/
+
+/********************** LOCAL FUNCTION DECLARATION SECTION *************/
+
+/********************** GLOBAL VARIABLE DECLARATION SECTION ************/
+
+/********************** FUNCTION DEFINITION SECTION ********************/
+
+#endif
diff --git a/package/etrax-tools/src/e100boot/cbl/src/hwregs_int.h b/package/etrax-tools/src/e100boot/cbl/src/hwregs_int.h
new file mode 100644
index 000000000..5688a76a8
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/hwregs_int.h
@@ -0,0 +1,25386 @@
+/*!**********************************************************************
+*!
+*! FILE NAME: hwregs_int.h
+*!
+*! DESCRIPTION: Internal shadow register implementation.
+*! Not intended for general use.
+*! This file is include in hwregs.h
+*!
+*! FUNCTIONS: none
+*!
+*! NOTE: This file is automatically generated, do _not_ edit.
+*! Created: Thu Oct 3 01:21:27 2002
+*! By: Id: shadow_gen,v 1.14 2002/10/02 20:31:22 hp Exp
+*! From: /n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd 1.168
+*! /n/asic/projects/etrax_ng/include//hwregs.ctrl 1.3
+*!
+*! MACROS: REG_INITIATED
+*! REG_CHECK_INIT
+*! REG_ICHECK_INIT
+*! REG_CHECK_INR
+*! REG_VAL_VAL
+*! REG_SVAL
+*! REG_SVAL_ZERO
+*! REG_SVAL_SHADOW
+*! REG_SVAL_I
+*! REG_SVAL_I_ZERO
+*! REG_SVAL_I_SHADOW
+*!
+*! REG_IMASK
+*! REG_ADDR_I
+*! REG_SADDR_I
+*! REG_IADDR_I
+*! REG_VAL_ENUM
+*! REG_GET_WO
+*! REG_GET_RO
+*! REG_GET_RW
+*! REG_IGET_WO
+*! REG_IGET_RO
+*! REG_IGET_RW
+*! REG_SET_WO
+*! REG_ISET_WO
+*! REG_SET_VAL_WO
+*! REG_SET_RW
+*! REG_ISET_RW
+*! REG_SET_VAL_RW
+*! REG_EQL_WO
+*! REG_EQL_RO
+*! REG_EQL_RW
+*! REG_IEQL_WO
+*! REG_IEQL_RO
+*! REG_IEQL_RW
+*! REG_RD_WO
+*! REG_RD_RO
+*! REG_RD_RW
+*! REG_IRD_WO
+*! REG_IRD_RO
+*! REG_IRD_RW
+*! REG_WR_WO
+*! REG_WR_RW
+*! REG_IWR_WO
+*! REG_IWR_RW
+*!
+*!----------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! Apr 01 1998 Jan Bengtsson Initial version
+*! Oct 01 2002 Hans-Peter Nilsson Large mechanical changes to correct
+*! use of the ## operator.
+*!----------------------------------------------------------------------
+*!
+*! (C) Copyright 1998, 2002 Axis Communications AB, LUND, SWEDEN
+*!
+*!**********************************************************************/
+/* %Z% %M% %I% %G% */
+
+#ifndef __HWREGS_INT_H__
+#define __HWREGS_INT_H__
+
+/********************** INCLUDE FILES SECTION **************************/
+
+/********************** CONSTANT AND MACRO SECTION *********************/
+#ifndef __REG_GENERAL_INT_H__
+#define __REG_GENERAL_INT_H__
+
+/*
+** The first part of hwregs_int.h is common to all shadow
+** register modules, and should therefore only be included once to
+** avoid macro redefinitions.
+*/
+
+#if REG_DEBUG && !defined(__ASSEMBLER__)
+
+#ifndef REG_SERROR
+#define REG_SERROR(ok,reg) \
+ assert( ok ),
+#endif
+
+#ifndef REG_VERROR
+#define REG_VERROR(ok,val) \
+ assert( ok ),
+#endif
+
+#ifndef REG_IERROR
+#define REG_IERROR(ok,i,reg) \
+ assert( ok ),
+#endif
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_INITIATED
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : 0
+*#
+*# SIDE EFFECTS: Clears initiated flag in reg_initiated_type struct.
+*#
+*# DESCRIPTION : Clears initiated flag in reg_initiated_type struct.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_INITIATED(reg_) \
+ *reg_##_IADDR = 0,
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_CHECK_INIT
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Value of REG_SERROR macro.
+*#
+*# SIDE EFFECTS: Evaluates REG_SERROR macro.
+*#
+*# DESCRIPTION : Check that shadow is initiated, by
+*# evaluating REG_SERROR macro.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Parameter now has "_" appended.
+*# Correct stringization.
+*#**********************************************************************/
+
+#define REG_CHECK_INIT(reg_) \
+ REG_SERROR(*reg_##_IADDR == 0, #reg_)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_ICHECK_INIT
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_: Name of a register, with "_" appended.
+*#
+*# RETURNS : Value of REG_SERROR macro.
+*#
+*# SIDE EFFECTS: Evaluates REG_SERROR macro.
+*#
+*# DESCRIPTION : Check that shadow is initiated, by
+*# evaluating REG_SERROR macro.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*# Correct stringization.
+*#**********************************************************************/
+
+#define REG_ICHECK_INIT(i, reg_) \
+ REG_SERROR(*REG_IADDR_I(i, reg_) == 0, #reg_)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_CHECK_INR
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_: Name of a register, with "_" appended.
+*#
+*# RETURNS : Value of REG_IERROR macro.
+*#
+*# SIDE EFFECTS: Evaluates REG_IERROR macro.
+*#
+*# DESCRIPTION : Check that interface number is valid.
+*# If an invalid interface number is found at compile
+*# time gcc report the following warning:
+*# 'warning: right shift count >= width of type'
+*# If an invalid interface number is found at run time
+*# the REG_IERROR macro is evaluated.
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*# Correct stringization.
+*#**********************************************************************/
+
+#define REG_CHECK_INR(i, reg_) \
+ REG_IERROR( \
+ 1 >> ( \
+ ( \
+ (udword)(~(i)) > (udword)(~(reg_##_FIRST)) || \
+ (udword)(i) > (udword)(reg_##_LAST) \
+ ) ? 32 : 0 \
+ ), \
+ i, #reg_ \
+ )
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL_VAL
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Integer value
+*#
+*# RETURNS : val
+*#
+*# SIDE EFFECTS: Evaluate REG_VERROR macro.
+*#
+*# DESCRIPTION : Check that an integer value is within field range.
+*# If val parameter is found to be out of range at compile
+*# time gcc report the following warning:
+*# 'left shift count >= width of type'
+*# If an invalid integer value is found at run time
+*# the REG_VERROR macro is evaluated.
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_VAL_VAL(reg_, field_, val) ( \
+ REG_VERROR( \
+ 1 << ( \
+ ( \
+ (udword)(~(val)) > (udword)(~(reg_##_##field_##_MIN)) || \
+ (udword)(val) > (udword)(reg_##_##field_##_MAX) \
+ ) ? 32 : 0 \
+ ), \
+ val \
+ ) \
+ val \
+)
+
+#else /* ! REG_DEBUG || __ASSEMBER__ */
+
+/* Checks only done in debug mode. */
+/* No need for REG_VERROR, REG_SERROR, and REG_IERROR. */
+
+#define REG_INITIATED(reg)
+#define REG_CHECK_INIT(reg)
+#define REG_ICHECK_INIT(i,reg)
+#define REG_CHECK_INR(i,reg)
+#define REG_VAL_VAL(reg,field,val) (val)
+
+#endif
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SVAL
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Value of shadow register associated with a WO register,
+*# or 0.
+*#
+*# SIDE EFFECTS: None
+*#
+*# DESCRIPTION : Read contents of a shadow register. By using this macro
+*# it's possible to force special values for some registers,
+*# e.g. zero for set/clr registers.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+#define REG_SVAL(reg_) ( \
+ reg_##_SVAL(reg_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SVAL_ZERO
+*#
+*# PARAMETERS : reg : Name of a register.
+*#
+*# RETURNS : Zero.
+*#
+*# SIDE EFFECTS: None
+*#
+*# DESCRIPTION : Force contents of shadow register to zero, used by
+*# the set/clr registers.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*#**********************************************************************/
+#define REG_SVAL_ZERO(reg) ( \
+ 0 \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SVAL_SHADOW
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Value of shadow register associated with a WO register.
+*#
+*# SIDE EFFECTS: None
+*#
+*# DESCRIPTION : Read shadow register contents.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+#define REG_SVAL_SHADOW(reg_) ( \
+ *reg_##_SADDR \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SVAL_I
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# i : Interface number.
+*#
+*# RETURNS : Value of shadow register associated with a WO register,
+*# or 0, for interface i.
+*#
+*# SIDE EFFECTS: None
+*#
+*# DESCRIPTION : Read contents of a shadow register. By using this macro
+*# it's possible to force special values for some registers,
+*# e.g. zero for set/clr registers.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+#define REG_SVAL_I(i, reg_) ( \
+ reg_##_SVAL_I(i, reg_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SVAL_I_ZERO
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# i : Interface number.
+*#
+*# RETURNS : Zero.
+*#
+*# SIDE EFFECTS: None
+*#
+*# DESCRIPTION : Force contents of shadow register to zero, used by
+*# the set/clr registers, for interface i.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+#define REG_SVAL_I_ZERO(i,reg) ( \
+ 0 \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SVAL_I_SHADOW
+*#
+*# PARAMETERS : reg_ : Name of a register.
+*# i : Interface number.
+*#
+*# RETURNS : Value of shadow register associated with a WO register,
+*# for interface i.
+*#
+*# SIDE EFFECTS: None
+*#
+*# DESCRIPTION : Read shadow register contents, of interface i.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+#define REG_SVAL_I_SHADOW(i, reg_) ( \
+ *REG_SADDR_I(i, reg_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IMASK
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_ : Name of a field, with "_" appended.
+*#
+*# RETURNS : Inverse of field mask.
+*#
+*# SIDE EFFECTS: none
+*#
+*# DESCRIPTION : Create a mask with zeros matching the field,
+*# and ones matching the rest.
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_IMASK(reg_, field_) ( \
+ ~reg_##_##field_##_##field_##_MASK \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_ADDR_I
+*#
+*# PARAMETERS : i : interface number.
+*# reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Address to reg for interface i.
+*#
+*# SIDE EFFECTS: May evaluate REG_IERROR.
+*#
+*# DESCRIPTION : Calculate address to reg for interface i.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_ADDR_I(i, reg_) ( \
+ reg_##_TYPECAST ( \
+ REG_CHECK_INR(i, reg_) \
+ ((udword) reg_##_ADDR) + reg_##_OFFSET * (i) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SADDR_I
+*#
+*# PARAMETERS : i : interface number.
+*# reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Address to shadow register for interface i.
+*#
+*# SIDE EFFECTS: May evaluate REG_IERROR.
+*#
+*# DESCRIPTION : Calculate address to shadow register for interface i.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_SADDR_I(i, reg_) ( \
+ reg_##_STYPECAST ( \
+ REG_CHECK_INR(i, reg_) \
+ ((udword) reg_##_SADDR) + reg_##_SOFFSET * (i) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IADDR_I
+*#
+*# PARAMETERS : i : interface number.
+*# reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Address to initiated flag for interface i.
+*#
+*# SIDE EFFECTS: May evaluate REG_IERROR.
+*#
+*# DESCRIPTION : Calculate address to initiated flag for interface i.
+*# The reg_initiated_type struct has the same layout as
+*# the reg_shadow_type struct, i.e. it's possible to use
+*# <reg>__SOFFSET here to.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_IADDR_I(i, reg_) ( \
+ reg_##_STYPECAST ( \
+ REG_CHECK_INR(i, reg_) \
+ ((udword) reg_##_IADDR) + reg_##_SOFFSET * (i) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_VAL_ENUM
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# sym : Symbolic value.
+*#
+*# RETURNS : Integer value for sym.
+*#
+*# SIDE EFFECTS: none
+*#
+*# DESCRIPTION : Convert symbolic value to an integer value.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_VAL_ENUM(reg_, field_, sym) ( \
+ reg_##_##field_##_##field_##_##sym \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_GET_WO
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_ : Name of a field, with "_" appended.
+*#
+*# RETURNS : Value of field field in register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR.
+*#
+*# DESCRIPTION : Read a field in a write only shadow register,
+*# i.e. from the shadow register. If the shadow register
+*# isn't initiated the REG_SERROR macro is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_GET_WO(reg_, field_) ( \
+ REG_CHECK_INIT(reg_) \
+ (REG_SVAL(reg_) & reg_##_##field_##_##field_##_MASK) >> \
+ reg_##_##field_##_BITNR \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_GET_RO, REG_GET_RW
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_ : Name of a field, with "_" appended.
+*#
+*# RETURNS : Value of field field in register reg.
+*#
+*# SIDE EFFECTS: none
+*#
+*# DESCRIPTION : Read a field in a read only or read write shadow register.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_GET_RO(reg_, field_) ( \
+ (reg_##_READ(reg_##_ADDR) & reg_##_##field_##_##field_##_MASK) >> \
+ reg_##_##field_##_BITNR \
+)
+
+#define REG_GET_RW REG_GET_RO
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IGET_WO
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*#
+*# RETURNS : Value of field field in register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR, and REG_IERROR.
+*#
+*# DESCRIPTION : Read a field in a write only register for interface i,
+*# i.e. from the shadow register. If the shadow register
+*# isn't initiated the REG_SERROR macro is evaluated,
+*# and if i is out of range REG_IERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_IGET_WO(i, reg_, field_) ( \
+ REG_ICHECK_INIT(i, reg_) \
+ (REG_SVAL_I(i, reg_) & reg_##_##field_##_##field_##_MASK) >> \
+ reg_##_##field_##_BITNR \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IGET_RO, REG_IGET_RW
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*#
+*# RETURNS : Value of field field in register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_IERROR.
+*#
+*# DESCRIPTION : Read a field in a read only or read write register for
+*# interface i. If i is out of range REG_IERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_IGET_RO(i, reg_, field_) ( \
+ (reg_##_READ(REG_ADDR_I(i, reg_) ) & \
+ reg_##_##field_##_##field_##_MASK) >> reg_##_##field_##_BITNR \
+)
+
+#define REG_IGET_RW REG_IGET_RO
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET_WO
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Value to write to field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in write only register
+*# reg and in the shadow register. If the shadow register
+*# isn't initiated REG_SERROR is evaluated, and if the
+*# val parameter is out of range REG_VERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_SET_WO(reg_, field_, val) ( \
+ *reg_##_SADDR = ( \
+ REG_CHECK_INIT(reg_) \
+ (REG_SVAL(reg_) & REG_IMASK(reg_, field_)) | \
+ (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \
+ reg_##_##field_##_BITNR) \
+ ), \
+ reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_ISET_WO
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Value to write to field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_IERROR, REG_SERROR, and REG_VERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in write only register
+*# reg of interface i and in the shadow register. If the
+*# shadow register isn't initiated REG_SERROR is evaluated,
+*# and if the val parameter is out of range REG_VERROR is
+*# evaluated, and if the interface number is out of range
+*# REG_IERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_ISET_WO(i, reg_, field_, val) ( \
+ *REG_SADDR_I(i, reg_) = ( \
+ REG_ICHECK_INIT(i, reg_) \
+ (REG_SVAL_I(i, reg_) & REG_IMASK(reg_, field_)) | \
+ (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \
+ reg_##_##field_##_BITNR) \
+ ), \
+ reg_##_WRITE(REG_ADDR_I(i, reg_), *REG_SADDR_I(i, reg_)) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET_VAL_WO
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Integer value to write to symbolic field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in write only register
+*# reg and in the shadow register. If the shadow register
+*# isn't initiated REG_SERROR is evaluated, and if the
+*# val parameter is out of range REG_VERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_SET_VAL_WO(reg_, field_, val) ( \
+ *reg_##_SADDR = ( \
+ REG_CHECK_INIT(reg_) \
+ (REG_SVAL(reg_) & REG_IMASK(reg_, field_)) | \
+ (REG_VAL_VAL(reg_, field_, val) << reg_##_##field_##_BITNR) \
+ ), \
+ reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \
+)
+
+/*#**********************************************************************
+*# Can't write to a read only register, i.e. NO REG_SET_RO, REG_ISET_RO,
+*# and REG_SET_VAL_RO macros.
+*#**********************************************************************/
+
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET_RW
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Value to write to field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in read write register
+*# reg. If the val parameter is out of range REG_VERROR is
+*# evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_SET_RW(reg_, field_, val) ( \
+ reg_##_WRITE(reg_##_ADDR, ( \
+ (reg_##_READ(reg_##_ADDR) & REG_IMASK(reg_, field_)) | \
+ (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \
+ reg_##_##field_##_BITNR) ) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_ISET_RW
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Value to write to field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR and REG_IERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in read write register
+*# reg of interface i. If the val parameter is out of range
+*# REG_VERROR is evaluated, and if the interface number is
+*# out of range REG_IERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_ISET_RW(i, reg_, field_, val) ( \
+ reg_##_WRITE(REG_ADDR_I(i, reg_), ( \
+ (reg_##_READ(REG_ADDR_I(i, reg_)) & REG_IMASK(reg_, field_))\
+ | (reg_##_##field_##_##field_##_VAL(reg_, field_, val) << \
+ reg_##_##field_##_BITNR) ) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_SET_VAL_RW
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Integer value to write to symbolic field.
+*#
+*# RETURNS : Integer value written to complete register.
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR.
+*#
+*# DESCRIPTION : Write val parameter to field field in read write register
+*# reg. If the val parameter is out of range REG_VERROR is
+*# evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_SET_VAL_RW(reg_, field_, val) ( \
+ reg_##_WRITE(reg_##_ADDR, ( \
+ (reg_##_READ(reg_##_ADDR) & REG_IMASK(reg_, field_)) | \
+ (REG_VAL_VAL(reg_, field_, val) << reg_##_##field_##_BITNR) ) \
+ ) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_EQL_WO
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Value to compare with field.
+*#
+*# RETURNS : TRUE, FALSE
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR and REG_VERROR.
+*#
+*# DESCRIPTION : Compare val parameter with field field in write only
+*# register reg. If the val parameter is out of range
+*# REG_VERROR is evaluated, and if the shadow register
+*# isn't initiated REG_SERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_EQL_WO(reg_, field_, val) ( \
+ REG_CHECK_INIT(reg_) \
+ ( (REG_SVAL(reg_) & reg_##_##field_##_##field_##_MASK) >> \
+ reg_##_##field_##_BITNR \
+ ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_EQL_RO, REG_EQL_RW
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Value to compare with field.
+*#
+*# RETURNS : TRUE, FALSE
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR.
+*#
+*# DESCRIPTION : Compare val parameter with field field in read only
+*# or read write register reg. If the val parameter is
+*# out of range REG_VERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_EQL_RO(reg_, field_, val) ( \
+ ( (reg_##_READ(reg_##_ADDR) & reg_##_##field_##_##field_##_MASK) >> \
+ reg_##_##field_##_BITNR \
+ ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \
+)
+
+#define REG_EQL_RW REG_EQL_RO
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IEQL_WO
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register, with "_" appended.
+*# field_: Name of a field, with "_" appended.
+*# val : Value to compare with field.
+*#
+*# RETURNS : TRUE, FALSE
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR, REG_IERROR, and REG_SERROR.
+*#
+*# DESCRIPTION : Compare val parameter with field field in write only
+*# register reg of interface i. If the val parameter is
+*# out of range REG_VERROR is evaluated, and if the
+*# interface number is out of range REG_IERROR is evaluated,
+*# and if the shadow register isn't initiated REG_SERROR
+*# is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_IEQL_WO(i, reg_, field_, val) ( \
+ REG_ICHECK_INIT(i, reg_) \
+ ( (REG_SVAL_I(i, reg_) & reg_##_##field_##_##field_##_MASK) >> \
+ reg_##_##field_##_BITNR \
+ ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IEQL_RO, REG_IEQL_RW
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register.
+*# field_: Name of a field.
+*# val : Value to compare with field.
+*#
+*# RETURNS : TRUE, FALSE
+*#
+*# SIDE EFFECTS: May evaluate REG_VERROR and REG_IERROR.
+*#
+*# DESCRIPTION : Compare val parameter with field field in read only
+*# or read write register reg of interface i. If the val
+*# parameter is out of range REG_VERROR is evaluated, and
+*# if the interface number is out of range REG_IERROR is
+*# evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg and field name parameters now
+*# have "_" appended.
+*#**********************************************************************/
+
+#define REG_IEQL_RO(i, reg_, field_, val) ( \
+ ( (reg_##_READ(REG_ADDR_I(i, reg_)) & \
+ reg_##_##field_##_##field_##_MASK) >> reg_##_##field_##_BITNR \
+ ) == reg_##_##field_##_##field_##_VAL(reg_, field_, val) \
+)
+
+#define REG_IEQL_RW REG_IEQL_RO
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_RD_WO
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Contents of register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR.
+*#
+*# DESCRIPTION : Read contents of write only register reg, i.e. read
+*# the shadow register. If the shadow register isn't
+*# initiated REG_SERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_RD_WO(reg_) ( \
+ REG_CHECK_INIT(reg_) \
+ REG_SVAL(reg_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_RD_RO, REG_RD_RW
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Contents of register reg.
+*#
+*# SIDE EFFECTS: none
+*#
+*# DESCRIPTION : Read contents of read only or read write register reg.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_RD_RO(reg_) ( \
+ reg_##_READ(reg_##_ADDR) \
+)
+
+#define REG_RD_RW REG_RD_RO
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IRD_WO
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register, with "_" appended.
+*#
+*# RETURNS : Contents of register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR and REG_IERROR.
+*#
+*# DESCRIPTION : Read contents of write only register reg, i.e. read
+*# the shadow register of interface i. If the shadow register
+*# isn't initiated REG_SERROR is evaluated, and if the
+*# interface number is out of range REG_IERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_IRD_WO(i, reg_) ( \
+ REG_ICHECK_INIT(i, reg_) \
+ REG_SVAL_I(i, reg_) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IRD_RO, REG_IRD_RW
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register.
+*#
+*# RETURNS : Contents of register reg.
+*#
+*# SIDE EFFECTS: none
+*#
+*# DESCRIPTION : Read contents of read only or read write register reg
+*# of interface i.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_IRD_RO(i, reg_) ( \
+ reg_##_READ(REG_ADDR_I(i, reg_)) \
+)
+
+#define REG_IRD_RW REG_IRD_RO
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_WR_WO
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# var : Variable (or value) to write to reg.
+*#
+*# RETURNS : integer value written to register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR.
+*#
+*# DESCRIPTION : Write value of var parameter to register reg and to
+*# the shadow register. If the shadow register
+*# isn't initiated REG_SERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_WR_WO(reg_, var) ( \
+ *reg_##_SADDR = ( \
+ REG_CHECK_INIT(reg_) \
+ (reg_##_TYPE var) \
+ ), \
+ reg_##_WRITE(reg_##_ADDR, *reg_##_SADDR) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_WR_RW
+*#
+*# PARAMETERS : reg_ : Name of a register, with "_" appended.
+*# var : Variable (or value) to write to reg.
+*#
+*# RETURNS : integer value written to register reg.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of var parameter to register reg.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_WR_RW(reg_, var) ( \
+ reg_##_WRITE(reg_##_ADDR, (reg_##_TYPE (var))) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IWR_WO
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register, with "_" appended.
+*# var : Variable (or value) to write to reg.
+*#
+*# RETURNS : integer value written to register reg.
+*#
+*# SIDE EFFECTS: May evaluate REG_SERROR.
+*#
+*# DESCRIPTION : Write value of var parameter to register reg and to
+*# the shadow register of interface i. If the shadow
+*# register isn't initiated REG_SERROR is evaluated.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_IWR_WO(i, reg_, var) ( \
+ *REG_SADDR_I(i, reg_) = ( \
+ REG_ICHECK_INIT(i, reg_) \
+ reg_##_TYPE (var) \
+ ), \
+ reg_##_WRITE(REG_ADDR_I(i, reg_), *REG_SADDR_I(i, reg_)) \
+)
+
+/*#**********************************************************************
+*#
+*# MACRO NAME : REG_IWR_RW
+*#
+*# PARAMETERS : i : Interface number.
+*# reg_ : Name of a register.
+*# var : Variable (or value) to write to reg.
+*#
+*# RETURNS : integer value written to register reg.
+*#
+*# SIDE EFFECTS: None.
+*#
+*# DESCRIPTION : Write value of var parameter to register reg of
+*# interface i.
+*#
+*#----------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# Apr 01 1998 Jan Bengtsson Initial version
+*# Oct 01 2002 Hans-Peter Nilsson Reg parameter now has "_" appended.
+*#**********************************************************************/
+
+#define REG_IWR_RW(i, reg_, var) ( \
+ reg_##_WRITE(REG_ADDR_I(i, reg_), (reg_##_TYPE (var))) \
+)
+
+/*
+ * Can't write to a read only register, i.e. NO REG_WR_RO, REG_IWR_RO
+ * macros.
+ */
+
+#endif /* __REG_GENERAL_INT_H__ */
+
+/*
+ * R_ALT_SER_BAUDRATE
+ * - type: WO
+ * - addr: 0xb000005c
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_ALT_SER_BAUDRATE__ADDR (REG_TYPECAST_UDWORD 0xb000005c)
+
+#ifndef REG_NO_SHADOW
+#define R_ALT_SER_BAUDRATE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ALT_SER_BAUDRATE + 0))
+#define R_ALT_SER_BAUDRATE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ALT_SER_BAUDRATE + 0))
+#else /* REG_NO_SHADOW */
+#define R_ALT_SER_BAUDRATE__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_ALT_SER_BAUDRATE__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_ALT_SER_BAUDRATE__STYPECAST REG_STYPECAST_UDWORD
+#define R_ALT_SER_BAUDRATE__SVAL REG_SVAL_SHADOW
+#define R_ALT_SER_BAUDRATE__SVAL_I REG_SVAL_I_SHADOW
+#define R_ALT_SER_BAUDRATE__TYPECAST REG_TYPECAST_UDWORD
+#define R_ALT_SER_BAUDRATE__TYPE (REG_UDWORD)
+#define R_ALT_SER_BAUDRATE__GET REG_GET_WO
+#define R_ALT_SER_BAUDRATE__IGET REG_IGET_WO
+#define R_ALT_SER_BAUDRATE__SET REG_SET_WO
+#define R_ALT_SER_BAUDRATE__ISET REG_ISET_WO
+#define R_ALT_SER_BAUDRATE__SET_VAL REG_SET_VAL_WO
+#define R_ALT_SER_BAUDRATE__EQL REG_EQL_WO
+#define R_ALT_SER_BAUDRATE__IEQL REG_IEQL_WO
+#define R_ALT_SER_BAUDRATE__RD REG_RD_WO
+#define R_ALT_SER_BAUDRATE__IRD REG_IRD_WO
+#define R_ALT_SER_BAUDRATE__WR REG_WR_WO
+#define R_ALT_SER_BAUDRATE__IWR REG_IWR_WO
+
+#define R_ALT_SER_BAUDRATE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__MASK 0x30000000U
+#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__MASK 0x03000000U
+#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__MASK 0x00300000U
+#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__MASK 0x00030000U
+#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__MASK 0x00003000U
+#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__MASK 0x00000300U
+#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__MASK 0x00000030U
+#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__MASK 0x00000003U
+
+#define R_ALT_SER_BAUDRATE__ser3_tr__MAX 0x3
+#define R_ALT_SER_BAUDRATE__ser3_rec__MAX 0x3
+#define R_ALT_SER_BAUDRATE__ser2_tr__MAX 0x3
+#define R_ALT_SER_BAUDRATE__ser2_rec__MAX 0x3
+#define R_ALT_SER_BAUDRATE__ser1_tr__MAX 0x3
+#define R_ALT_SER_BAUDRATE__ser1_rec__MAX 0x3
+#define R_ALT_SER_BAUDRATE__ser0_tr__MAX 0x3
+#define R_ALT_SER_BAUDRATE__ser0_rec__MAX 0x3
+
+#define R_ALT_SER_BAUDRATE__ser3_tr__MIN 0
+#define R_ALT_SER_BAUDRATE__ser3_rec__MIN 0
+#define R_ALT_SER_BAUDRATE__ser2_tr__MIN 0
+#define R_ALT_SER_BAUDRATE__ser2_rec__MIN 0
+#define R_ALT_SER_BAUDRATE__ser1_tr__MIN 0
+#define R_ALT_SER_BAUDRATE__ser1_rec__MIN 0
+#define R_ALT_SER_BAUDRATE__ser0_tr__MIN 0
+#define R_ALT_SER_BAUDRATE__ser0_rec__MIN 0
+
+#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28
+#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24
+#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20
+#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16
+#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12
+#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8
+#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4
+#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0
+
+#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__VAL REG_VAL_ENUM
+#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__VAL REG_VAL_ENUM
+#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__VAL REG_VAL_ENUM
+#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__VAL REG_VAL_ENUM
+#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__VAL REG_VAL_ENUM
+#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__VAL REG_VAL_ENUM
+#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__VAL REG_VAL_ENUM
+#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__VAL REG_VAL_ENUM
+
+#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__extern 2
+#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__normal 0
+#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__prescale 1
+#define R_ALT_SER_BAUDRATE__ser3_tr__ser3_tr__timer 3
+#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__extern 2
+#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__normal 0
+#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__prescale 1
+#define R_ALT_SER_BAUDRATE__ser3_rec__ser3_rec__timer 3
+#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__extern 2
+#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__normal 0
+#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__prescale 1
+#define R_ALT_SER_BAUDRATE__ser2_tr__ser2_tr__timer 3
+#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__extern 2
+#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__normal 0
+#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__prescale 1
+#define R_ALT_SER_BAUDRATE__ser2_rec__ser2_rec__timer 3
+#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__extern 2
+#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__normal 0
+#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__prescale 1
+#define R_ALT_SER_BAUDRATE__ser1_tr__ser1_tr__timer 3
+#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__extern 2
+#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__normal 0
+#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__prescale 1
+#define R_ALT_SER_BAUDRATE__ser1_rec__ser1_rec__timer 3
+#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__extern 2
+#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__normal 0
+#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__prescale 1
+#define R_ALT_SER_BAUDRATE__ser0_tr__ser0_tr__timer 3
+#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__extern 2
+#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__normal 0
+#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__prescale 1
+#define R_ALT_SER_BAUDRATE__ser0_rec__ser0_rec__timer 3
+
+#endif
+
+/*
+ * R_ATA_CONFIG
+ * - type: WO
+ * - addr: 0xb0000044
+ * - group: ATA interface registers
+ */
+
+#if USE_GROUP__ATA_interface_registers
+
+#define R_ATA_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000044)
+
+#ifndef REG_NO_SHADOW
+#define R_ATA_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0))
+#define R_ATA_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_ATA_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_ATA_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_ATA_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_ATA_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_ATA_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_ATA_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_ATA_CONFIG__TYPE (REG_UDWORD)
+#define R_ATA_CONFIG__GET REG_GET_WO
+#define R_ATA_CONFIG__IGET REG_IGET_WO
+#define R_ATA_CONFIG__SET REG_SET_WO
+#define R_ATA_CONFIG__ISET REG_ISET_WO
+#define R_ATA_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_ATA_CONFIG__EQL REG_EQL_WO
+#define R_ATA_CONFIG__IEQL REG_IEQL_WO
+#define R_ATA_CONFIG__RD REG_RD_WO
+#define R_ATA_CONFIG__IRD REG_IRD_WO
+#define R_ATA_CONFIG__WR REG_WR_WO
+#define R_ATA_CONFIG__IWR REG_IWR_WO
+
+#define R_ATA_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_ATA_CONFIG__enable__enable__MASK 0x02000000U
+#define R_ATA_CONFIG__dma_strobe__dma_strobe__MASK 0x01f00000U
+#define R_ATA_CONFIG__dma_hold__dma_hold__MASK 0x000f8000U
+#define R_ATA_CONFIG__pio_setup__pio_setup__MASK 0x00007c00U
+#define R_ATA_CONFIG__pio_strobe__pio_strobe__MASK 0x000003e0U
+#define R_ATA_CONFIG__pio_hold__pio_hold__MASK 0x0000001fU
+
+#define R_ATA_CONFIG__enable__MAX 0x1
+#define R_ATA_CONFIG__dma_strobe__MAX 31
+#define R_ATA_CONFIG__dma_hold__MAX 31
+#define R_ATA_CONFIG__pio_setup__MAX 31
+#define R_ATA_CONFIG__pio_strobe__MAX 31
+#define R_ATA_CONFIG__pio_hold__MAX 31
+
+#define R_ATA_CONFIG__enable__MIN 0
+#define R_ATA_CONFIG__dma_strobe__MIN 0
+#define R_ATA_CONFIG__dma_hold__MIN 0
+#define R_ATA_CONFIG__pio_setup__MIN 0
+#define R_ATA_CONFIG__pio_strobe__MIN 0
+#define R_ATA_CONFIG__pio_hold__MIN 0
+
+#define R_ATA_CONFIG__enable__BITNR 25
+#define R_ATA_CONFIG__dma_strobe__BITNR 20
+#define R_ATA_CONFIG__dma_hold__BITNR 15
+#define R_ATA_CONFIG__pio_setup__BITNR 10
+#define R_ATA_CONFIG__pio_strobe__BITNR 5
+#define R_ATA_CONFIG__pio_hold__BITNR 0
+
+#define R_ATA_CONFIG__enable__enable__VAL REG_VAL_ENUM
+#define R_ATA_CONFIG__dma_strobe__dma_strobe__VAL REG_VAL_VAL
+#define R_ATA_CONFIG__dma_hold__dma_hold__VAL REG_VAL_VAL
+#define R_ATA_CONFIG__pio_setup__pio_setup__VAL REG_VAL_VAL
+#define R_ATA_CONFIG__pio_strobe__pio_strobe__VAL REG_VAL_VAL
+#define R_ATA_CONFIG__pio_hold__pio_hold__VAL REG_VAL_VAL
+
+#define R_ATA_CONFIG__enable__enable__off 0
+#define R_ATA_CONFIG__enable__enable__on 1
+
+#endif
+
+/*
+ * R_ATA_CTRL_DATA
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: ATA interface registers
+ */
+
+#if USE_GROUP__ATA_interface_registers
+
+#define R_ATA_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
+
+#ifndef REG_NO_SHADOW
+#define R_ATA_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
+#define R_ATA_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
+#else /* REG_NO_SHADOW */
+#define R_ATA_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_ATA_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_ATA_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD
+#define R_ATA_CTRL_DATA__SVAL REG_SVAL_SHADOW
+#define R_ATA_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_ATA_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_ATA_CTRL_DATA__TYPE (REG_UDWORD)
+#define R_ATA_CTRL_DATA__GET REG_GET_WO
+#define R_ATA_CTRL_DATA__IGET REG_IGET_WO
+#define R_ATA_CTRL_DATA__SET REG_SET_WO
+#define R_ATA_CTRL_DATA__ISET REG_ISET_WO
+#define R_ATA_CTRL_DATA__SET_VAL REG_SET_VAL_WO
+#define R_ATA_CTRL_DATA__EQL REG_EQL_WO
+#define R_ATA_CTRL_DATA__IEQL REG_IEQL_WO
+#define R_ATA_CTRL_DATA__RD REG_RD_WO
+#define R_ATA_CTRL_DATA__IRD REG_IRD_WO
+#define R_ATA_CTRL_DATA__WR REG_WR_WO
+#define R_ATA_CTRL_DATA__IWR REG_IWR_WO
+
+#define R_ATA_CTRL_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_ATA_CTRL_DATA__sel__sel__MASK 0xc0000000U
+#define R_ATA_CTRL_DATA__cs1__cs1__MASK 0x20000000U
+#define R_ATA_CTRL_DATA__cs0__cs0__MASK 0x10000000U
+#define R_ATA_CTRL_DATA__addr__addr__MASK 0x0e000000U
+#define R_ATA_CTRL_DATA__rw__rw__MASK 0x01000000U
+#define R_ATA_CTRL_DATA__src_dst__src_dst__MASK 0x00800000U
+#define R_ATA_CTRL_DATA__handsh__handsh__MASK 0x00400000U
+#define R_ATA_CTRL_DATA__multi__multi__MASK 0x00200000U
+#define R_ATA_CTRL_DATA__dma_size__dma_size__MASK 0x00100000U
+#define R_ATA_CTRL_DATA__data__data__MASK 0x0000ffffU
+
+#define R_ATA_CTRL_DATA__sel__MAX 3
+#define R_ATA_CTRL_DATA__cs1__MAX 0x1
+#define R_ATA_CTRL_DATA__cs0__MAX 0x1
+#define R_ATA_CTRL_DATA__addr__MAX 7
+#define R_ATA_CTRL_DATA__rw__MAX 0x1
+#define R_ATA_CTRL_DATA__src_dst__MAX 0x1
+#define R_ATA_CTRL_DATA__handsh__MAX 0x1
+#define R_ATA_CTRL_DATA__multi__MAX 0x1
+#define R_ATA_CTRL_DATA__dma_size__MAX 0x1
+#define R_ATA_CTRL_DATA__data__MAX 0xffff
+
+#define R_ATA_CTRL_DATA__sel__MIN 0
+#define R_ATA_CTRL_DATA__cs1__MIN 0
+#define R_ATA_CTRL_DATA__cs0__MIN 0
+#define R_ATA_CTRL_DATA__addr__MIN 0
+#define R_ATA_CTRL_DATA__rw__MIN 0
+#define R_ATA_CTRL_DATA__src_dst__MIN 0
+#define R_ATA_CTRL_DATA__handsh__MIN 0
+#define R_ATA_CTRL_DATA__multi__MIN 0
+#define R_ATA_CTRL_DATA__dma_size__MIN 0
+#define R_ATA_CTRL_DATA__data__MIN 0
+
+#define R_ATA_CTRL_DATA__sel__BITNR 30
+#define R_ATA_CTRL_DATA__cs1__BITNR 29
+#define R_ATA_CTRL_DATA__cs0__BITNR 28
+#define R_ATA_CTRL_DATA__addr__BITNR 25
+#define R_ATA_CTRL_DATA__rw__BITNR 24
+#define R_ATA_CTRL_DATA__src_dst__BITNR 23
+#define R_ATA_CTRL_DATA__handsh__BITNR 22
+#define R_ATA_CTRL_DATA__multi__BITNR 21
+#define R_ATA_CTRL_DATA__dma_size__BITNR 20
+#define R_ATA_CTRL_DATA__data__BITNR 0
+
+#define R_ATA_CTRL_DATA__sel__sel__VAL REG_VAL_VAL
+#define R_ATA_CTRL_DATA__cs1__cs1__VAL REG_VAL_ENUM
+#define R_ATA_CTRL_DATA__cs0__cs0__VAL REG_VAL_ENUM
+#define R_ATA_CTRL_DATA__addr__addr__VAL REG_VAL_VAL
+#define R_ATA_CTRL_DATA__rw__rw__VAL REG_VAL_ENUM
+#define R_ATA_CTRL_DATA__src_dst__src_dst__VAL REG_VAL_ENUM
+#define R_ATA_CTRL_DATA__handsh__handsh__VAL REG_VAL_ENUM
+#define R_ATA_CTRL_DATA__multi__multi__VAL REG_VAL_ENUM
+#define R_ATA_CTRL_DATA__dma_size__dma_size__VAL REG_VAL_ENUM
+#define R_ATA_CTRL_DATA__data__data__VAL REG_VAL_VAL
+
+#define R_ATA_CTRL_DATA__cs1__cs1__active 1
+#define R_ATA_CTRL_DATA__cs1__cs1__inactive 0
+#define R_ATA_CTRL_DATA__cs0__cs0__active 1
+#define R_ATA_CTRL_DATA__cs0__cs0__inactive 0
+#define R_ATA_CTRL_DATA__rw__rw__read 1
+#define R_ATA_CTRL_DATA__rw__rw__write 0
+#define R_ATA_CTRL_DATA__src_dst__src_dst__dma 1
+#define R_ATA_CTRL_DATA__src_dst__src_dst__register 0
+#define R_ATA_CTRL_DATA__handsh__handsh__dma 1
+#define R_ATA_CTRL_DATA__handsh__handsh__pio 0
+#define R_ATA_CTRL_DATA__multi__multi__off 0
+#define R_ATA_CTRL_DATA__multi__multi__on 1
+#define R_ATA_CTRL_DATA__dma_size__dma_size__byte 1
+#define R_ATA_CTRL_DATA__dma_size__dma_size__word 0
+
+#endif
+
+/*
+ * R_ATA_STATUS_DATA
+ * - type: RO
+ * - addr: 0xb0000040
+ * - group: ATA interface registers
+ */
+
+#if USE_GROUP__ATA_interface_registers
+
+#define R_ATA_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
+#define R_ATA_STATUS_DATA__SVAL REG_SVAL_SHADOW
+#define R_ATA_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_ATA_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_ATA_STATUS_DATA__TYPE (REG_UDWORD)
+#define R_ATA_STATUS_DATA__GET REG_GET_RO
+#define R_ATA_STATUS_DATA__IGET REG_IGET_RO
+#define R_ATA_STATUS_DATA__SET REG_SET_RO
+#define R_ATA_STATUS_DATA__ISET REG_ISET_RO
+#define R_ATA_STATUS_DATA__SET_VAL REG_SET_VAL_RO
+#define R_ATA_STATUS_DATA__EQL REG_EQL_RO
+#define R_ATA_STATUS_DATA__IEQL REG_IEQL_RO
+#define R_ATA_STATUS_DATA__RD REG_RD_RO
+#define R_ATA_STATUS_DATA__IRD REG_IRD_RO
+#define R_ATA_STATUS_DATA__WR REG_WR_RO
+#define R_ATA_STATUS_DATA__IWR REG_IWR_RO
+
+#define R_ATA_STATUS_DATA__READ(addr) \
+ (*(addr))
+
+#define R_ATA_STATUS_DATA__busy__busy__MASK 0x00040000U
+#define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U
+#define R_ATA_STATUS_DATA__dav__dav__MASK 0x00010000U
+#define R_ATA_STATUS_DATA__data__data__MASK 0x0000ffffU
+
+#define R_ATA_STATUS_DATA__busy__MAX 0x1
+#define R_ATA_STATUS_DATA__tr_rdy__MAX 0x1
+#define R_ATA_STATUS_DATA__dav__MAX 0x1
+#define R_ATA_STATUS_DATA__data__MAX 0xffff
+
+#define R_ATA_STATUS_DATA__busy__MIN 0
+#define R_ATA_STATUS_DATA__tr_rdy__MIN 0
+#define R_ATA_STATUS_DATA__dav__MIN 0
+#define R_ATA_STATUS_DATA__data__MIN 0
+
+#define R_ATA_STATUS_DATA__busy__BITNR 18
+#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17
+#define R_ATA_STATUS_DATA__dav__BITNR 16
+#define R_ATA_STATUS_DATA__data__BITNR 0
+
+#define R_ATA_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM
+#define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
+#define R_ATA_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM
+#define R_ATA_STATUS_DATA__data__data__VAL REG_VAL_VAL
+
+#define R_ATA_STATUS_DATA__busy__busy__no 0
+#define R_ATA_STATUS_DATA__busy__busy__yes 1
+#define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__busy 0
+#define R_ATA_STATUS_DATA__tr_rdy__tr_rdy__ready 1
+#define R_ATA_STATUS_DATA__dav__dav__data 1
+#define R_ATA_STATUS_DATA__dav__dav__nodata 0
+
+#endif
+
+/*
+ * R_ATA_TRANSFER_CNT
+ * - type: RW
+ * - addr: 0xb0000048
+ * - group: ATA interface registers
+ */
+
+#if USE_GROUP__ATA_interface_registers
+
+#define R_ATA_TRANSFER_CNT__ADDR (REG_TYPECAST_UDWORD 0xb0000048)
+#define R_ATA_TRANSFER_CNT__SVAL REG_SVAL_SHADOW
+#define R_ATA_TRANSFER_CNT__SVAL_I REG_SVAL_I_SHADOW
+#define R_ATA_TRANSFER_CNT__TYPECAST REG_TYPECAST_UDWORD
+#define R_ATA_TRANSFER_CNT__TYPE (REG_UDWORD)
+#define R_ATA_TRANSFER_CNT__GET REG_GET_RW
+#define R_ATA_TRANSFER_CNT__IGET REG_IGET_RW
+#define R_ATA_TRANSFER_CNT__SET REG_SET_RW
+#define R_ATA_TRANSFER_CNT__ISET REG_ISET_RW
+#define R_ATA_TRANSFER_CNT__SET_VAL REG_SET_VAL_RW
+#define R_ATA_TRANSFER_CNT__EQL REG_EQL_RW
+#define R_ATA_TRANSFER_CNT__IEQL REG_IEQL_RW
+#define R_ATA_TRANSFER_CNT__RD REG_RD_RW
+#define R_ATA_TRANSFER_CNT__IRD REG_IRD_RW
+#define R_ATA_TRANSFER_CNT__WR REG_WR_RW
+#define R_ATA_TRANSFER_CNT__IWR REG_IWR_RW
+
+#define R_ATA_TRANSFER_CNT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_ATA_TRANSFER_CNT__READ(addr) \
+ (*(addr))
+
+#define R_ATA_TRANSFER_CNT__count__count__MASK 0x0001ffffU
+
+#define R_ATA_TRANSFER_CNT__count__MAX 0x1ffff
+
+#define R_ATA_TRANSFER_CNT__count__MIN 0
+
+#define R_ATA_TRANSFER_CNT__count__BITNR 0
+
+#define R_ATA_TRANSFER_CNT__count__count__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_BUS_CONFIG
+ * - type: WO
+ * - addr: 0xb0000004
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+#define R_BUS_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000004)
+
+#ifndef REG_NO_SHADOW
+#define R_BUS_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_BUS_CONFIG + 0))
+#define R_BUS_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_BUS_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_BUS_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_BUS_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_BUS_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_BUS_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_BUS_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_BUS_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_BUS_CONFIG__TYPE (REG_UDWORD)
+#define R_BUS_CONFIG__GET REG_GET_WO
+#define R_BUS_CONFIG__IGET REG_IGET_WO
+#define R_BUS_CONFIG__SET REG_SET_WO
+#define R_BUS_CONFIG__ISET REG_ISET_WO
+#define R_BUS_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_BUS_CONFIG__EQL REG_EQL_WO
+#define R_BUS_CONFIG__IEQL REG_IEQL_WO
+#define R_BUS_CONFIG__RD REG_RD_WO
+#define R_BUS_CONFIG__IRD REG_IRD_WO
+#define R_BUS_CONFIG__WR REG_WR_WO
+#define R_BUS_CONFIG__IWR REG_IWR_WO
+
+#define R_BUS_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_BUS_CONFIG__sram_type__sram_type__MASK 0x00000200U
+#define R_BUS_CONFIG__dma_burst__dma_burst__MASK 0x00000100U
+#define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__MASK 0x00000080U
+#define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__MASK 0x00000040U
+#define R_BUS_CONFIG__sram_wr__sram_wr__MASK 0x00000020U
+#define R_BUS_CONFIG__flash_wr__flash_wr__MASK 0x00000010U
+#define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__MASK 0x00000008U
+#define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__MASK 0x00000004U
+#define R_BUS_CONFIG__sram_bw__sram_bw__MASK 0x00000002U
+#define R_BUS_CONFIG__flash_bw__flash_bw__MASK 0x00000001U
+
+#define R_BUS_CONFIG__sram_type__MAX 0x1
+#define R_BUS_CONFIG__dma_burst__MAX 0x1
+#define R_BUS_CONFIG__pcs4_7_wr__MAX 0x1
+#define R_BUS_CONFIG__pcs0_3_wr__MAX 0x1
+#define R_BUS_CONFIG__sram_wr__MAX 0x1
+#define R_BUS_CONFIG__flash_wr__MAX 0x1
+#define R_BUS_CONFIG__pcs4_7_bw__MAX 0x1
+#define R_BUS_CONFIG__pcs0_3_bw__MAX 0x1
+#define R_BUS_CONFIG__sram_bw__MAX 0x1
+#define R_BUS_CONFIG__flash_bw__MAX 0x1
+
+#define R_BUS_CONFIG__sram_type__MIN 0
+#define R_BUS_CONFIG__dma_burst__MIN 0
+#define R_BUS_CONFIG__pcs4_7_wr__MIN 0
+#define R_BUS_CONFIG__pcs0_3_wr__MIN 0
+#define R_BUS_CONFIG__sram_wr__MIN 0
+#define R_BUS_CONFIG__flash_wr__MIN 0
+#define R_BUS_CONFIG__pcs4_7_bw__MIN 0
+#define R_BUS_CONFIG__pcs0_3_bw__MIN 0
+#define R_BUS_CONFIG__sram_bw__MIN 0
+#define R_BUS_CONFIG__flash_bw__MIN 0
+
+#define R_BUS_CONFIG__sram_type__BITNR 9
+#define R_BUS_CONFIG__dma_burst__BITNR 8
+#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7
+#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6
+#define R_BUS_CONFIG__sram_wr__BITNR 5
+#define R_BUS_CONFIG__flash_wr__BITNR 4
+#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3
+#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2
+#define R_BUS_CONFIG__sram_bw__BITNR 1
+#define R_BUS_CONFIG__flash_bw__BITNR 0
+
+#define R_BUS_CONFIG__sram_type__sram_type__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__dma_burst__dma_burst__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__sram_wr__sram_wr__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__flash_wr__flash_wr__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__sram_bw__sram_bw__VAL REG_VAL_ENUM
+#define R_BUS_CONFIG__flash_bw__flash_bw__VAL REG_VAL_ENUM
+
+#define R_BUS_CONFIG__sram_type__sram_type__bwe 0
+#define R_BUS_CONFIG__sram_type__sram_type__cwe 1
+#define R_BUS_CONFIG__dma_burst__dma_burst__burst16 1
+#define R_BUS_CONFIG__dma_burst__dma_burst__burst32 0
+#define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__ext 1
+#define R_BUS_CONFIG__pcs4_7_wr__pcs4_7_wr__norm 0
+#define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__ext 1
+#define R_BUS_CONFIG__pcs0_3_wr__pcs0_3_wr__norm 0
+#define R_BUS_CONFIG__sram_wr__sram_wr__ext 1
+#define R_BUS_CONFIG__sram_wr__sram_wr__norm 0
+#define R_BUS_CONFIG__flash_wr__flash_wr__ext 1
+#define R_BUS_CONFIG__flash_wr__flash_wr__norm 0
+#define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__bw16 0
+#define R_BUS_CONFIG__pcs4_7_bw__pcs4_7_bw__bw32 1
+#define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__bw16 0
+#define R_BUS_CONFIG__pcs0_3_bw__pcs0_3_bw__bw32 1
+#define R_BUS_CONFIG__sram_bw__sram_bw__bw16 0
+#define R_BUS_CONFIG__sram_bw__sram_bw__bw32 1
+#define R_BUS_CONFIG__flash_bw__flash_bw__bw16 0
+#define R_BUS_CONFIG__flash_bw__flash_bw__bw32 1
+
+#endif
+
+/*
+ * R_BUS_STATUS
+ * - type: RO
+ * - addr: 0xb0000004
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+#define R_BUS_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000004)
+#define R_BUS_STATUS__SVAL REG_SVAL_SHADOW
+#define R_BUS_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_BUS_STATUS__TYPECAST REG_TYPECAST_UDWORD
+#define R_BUS_STATUS__TYPE (REG_UDWORD)
+#define R_BUS_STATUS__GET REG_GET_RO
+#define R_BUS_STATUS__IGET REG_IGET_RO
+#define R_BUS_STATUS__SET REG_SET_RO
+#define R_BUS_STATUS__ISET REG_ISET_RO
+#define R_BUS_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_BUS_STATUS__EQL REG_EQL_RO
+#define R_BUS_STATUS__IEQL REG_IEQL_RO
+#define R_BUS_STATUS__RD REG_RD_RO
+#define R_BUS_STATUS__IRD REG_IRD_RO
+#define R_BUS_STATUS__WR REG_WR_RO
+#define R_BUS_STATUS__IWR REG_IWR_RO
+
+#define R_BUS_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__MASK 0x00000020U
+#define R_BUS_STATUS__both_faults__both_faults__MASK 0x00000010U
+#define R_BUS_STATUS__bsen___bsen___MASK 0x00000008U
+#define R_BUS_STATUS__boot__boot__MASK 0x00000006U
+#define R_BUS_STATUS__flashw__flashw__MASK 0x00000001U
+
+#define R_BUS_STATUS__pll_lock_tm__MAX 0x1
+#define R_BUS_STATUS__both_faults__MAX 0x1
+#define R_BUS_STATUS__bsen___MAX 0x1
+#define R_BUS_STATUS__boot__MAX 0x3
+#define R_BUS_STATUS__flashw__MAX 0x1
+
+#define R_BUS_STATUS__pll_lock_tm__MIN 0
+#define R_BUS_STATUS__both_faults__MIN 0
+#define R_BUS_STATUS__bsen___MIN 0
+#define R_BUS_STATUS__boot__MIN 0
+#define R_BUS_STATUS__flashw__MIN 0
+
+#define R_BUS_STATUS__pll_lock_tm__BITNR 5
+#define R_BUS_STATUS__both_faults__BITNR 4
+#define R_BUS_STATUS__bsen___BITNR 3
+#define R_BUS_STATUS__boot__BITNR 1
+#define R_BUS_STATUS__flashw__BITNR 0
+
+#define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__VAL REG_VAL_ENUM
+#define R_BUS_STATUS__both_faults__both_faults__VAL REG_VAL_ENUM
+#define R_BUS_STATUS__bsen___bsen___VAL REG_VAL_ENUM
+#define R_BUS_STATUS__boot__boot__VAL REG_VAL_ENUM
+#define R_BUS_STATUS__flashw__flashw__VAL REG_VAL_ENUM
+
+#define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__counting 1
+#define R_BUS_STATUS__pll_lock_tm__pll_lock_tm__expired 0
+#define R_BUS_STATUS__both_faults__both_faults__no 0
+#define R_BUS_STATUS__both_faults__both_faults__yes 1
+#define R_BUS_STATUS__bsen___bsen___disable 1
+#define R_BUS_STATUS__bsen___bsen___enable 0
+#define R_BUS_STATUS__boot__boot__network 2
+#define R_BUS_STATUS__boot__boot__parallel 3
+#define R_BUS_STATUS__boot__boot__serial 1
+#define R_BUS_STATUS__boot__boot__uncached 0
+#define R_BUS_STATUS__flashw__flashw__bw16 0
+#define R_BUS_STATUS__flashw__flashw__bw32 1
+
+#endif
+
+/*
+ * R_CLOCK_PRESCALE
+ * - type: WO
+ * - addr: 0xb00000f0
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_CLOCK_PRESCALE__ADDR (REG_TYPECAST_UDWORD 0xb00000f0)
+
+#ifndef REG_NO_SHADOW
+#define R_CLOCK_PRESCALE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 0))
+#define R_CLOCK_PRESCALE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 0))
+#else /* REG_NO_SHADOW */
+#define R_CLOCK_PRESCALE__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_CLOCK_PRESCALE__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_CLOCK_PRESCALE__STYPECAST REG_STYPECAST_UDWORD
+#define R_CLOCK_PRESCALE__SVAL REG_SVAL_SHADOW
+#define R_CLOCK_PRESCALE__SVAL_I REG_SVAL_I_SHADOW
+#define R_CLOCK_PRESCALE__TYPECAST REG_TYPECAST_UDWORD
+#define R_CLOCK_PRESCALE__TYPE (REG_UDWORD)
+#define R_CLOCK_PRESCALE__GET REG_GET_WO
+#define R_CLOCK_PRESCALE__IGET REG_IGET_WO
+#define R_CLOCK_PRESCALE__SET REG_SET_WO
+#define R_CLOCK_PRESCALE__ISET REG_ISET_WO
+#define R_CLOCK_PRESCALE__SET_VAL REG_SET_VAL_WO
+#define R_CLOCK_PRESCALE__EQL REG_EQL_WO
+#define R_CLOCK_PRESCALE__IEQL REG_IEQL_WO
+#define R_CLOCK_PRESCALE__RD REG_RD_WO
+#define R_CLOCK_PRESCALE__IRD REG_IRD_WO
+#define R_CLOCK_PRESCALE__WR REG_WR_WO
+#define R_CLOCK_PRESCALE__IWR REG_IWR_WO
+
+#define R_CLOCK_PRESCALE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_CLOCK_PRESCALE__ser_presc__ser_presc__MASK 0xffff0000U
+#define R_CLOCK_PRESCALE__tim_presc__tim_presc__MASK 0x0000ffffU
+
+#define R_CLOCK_PRESCALE__ser_presc__MAX 0xffff
+#define R_CLOCK_PRESCALE__tim_presc__MAX 0xffff
+
+#define R_CLOCK_PRESCALE__ser_presc__MIN 0
+#define R_CLOCK_PRESCALE__tim_presc__MIN 0
+
+#define R_CLOCK_PRESCALE__ser_presc__BITNR 16
+#define R_CLOCK_PRESCALE__tim_presc__BITNR 0
+
+#define R_CLOCK_PRESCALE__ser_presc__ser_presc__VAL REG_VAL_VAL
+#define R_CLOCK_PRESCALE__tim_presc__tim_presc__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH0_BUF
+ * - type: RW
+ * - addr: 0xb0000108
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH0_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000108)
+#define R_DMA_CH0_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH0_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH0_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH0_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH0_BUF__GET REG_GET_RW
+#define R_DMA_CH0_BUF__IGET REG_IGET_RW
+#define R_DMA_CH0_BUF__SET REG_SET_RW
+#define R_DMA_CH0_BUF__ISET REG_ISET_RW
+#define R_DMA_CH0_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH0_BUF__EQL REG_EQL_RW
+#define R_DMA_CH0_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH0_BUF__RD REG_RD_RW
+#define R_DMA_CH0_BUF__IRD REG_IRD_RW
+#define R_DMA_CH0_BUF__WR REG_WR_RW
+#define R_DMA_CH0_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH0_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH0_BUF__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_DMA_CH0_BUF__FIRST 0
+#define R_DMA_CH0_BUF__LAST 9
+#define R_DMA_CH0_BUF__OFFSET 16
+/* end */
+
+#define R_DMA_CH0_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH0_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH0_BUF__buf__MIN 0
+
+#define R_DMA_CH0_BUF__buf__BITNR 0
+
+#define R_DMA_CH0_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH0_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001d1
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH0_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d1)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH0_CLR_INTR + 0))
+#define R_DMA_CH0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH0_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH0_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH0_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH0_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH0_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH0_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH0_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH0_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH0_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH0_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH0_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH0_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH0_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH0_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH0_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH0_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH0_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH0_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_DMA_CH0_CLR_INTR__FIRST 0
+#define R_DMA_CH0_CLR_INTR__IOFFSET 0
+#define R_DMA_CH0_CLR_INTR__LAST 9
+#define R_DMA_CH0_CLR_INTR__OFFSET 4
+#define R_DMA_CH0_CLR_INTR__SOFFSET 0
+/* end */
+
+#define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH0_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH0_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH0_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH0_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH0_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH0_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH0_CMD
+ * - type: RW
+ * - addr: 0xb00001d0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH0_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d0)
+#define R_DMA_CH0_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH0_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH0_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH0_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH0_CMD__GET REG_GET_RW
+#define R_DMA_CH0_CMD__IGET REG_IGET_RW
+#define R_DMA_CH0_CMD__SET REG_SET_RW
+#define R_DMA_CH0_CMD__ISET REG_ISET_RW
+#define R_DMA_CH0_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH0_CMD__EQL REG_EQL_RW
+#define R_DMA_CH0_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH0_CMD__RD REG_RD_RW
+#define R_DMA_CH0_CMD__IRD REG_IRD_RW
+#define R_DMA_CH0_CMD__WR REG_WR_RW
+#define R_DMA_CH0_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH0_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH0_CMD__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_DMA_CH0_CMD__FIRST 0
+#define R_DMA_CH0_CMD__LAST 9
+#define R_DMA_CH0_CMD__OFFSET 4
+/* end */
+
+#define R_DMA_CH0_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH0_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH0_CMD__cmd__MIN 0
+
+#define R_DMA_CH0_CMD__cmd__BITNR 0
+
+#define R_DMA_CH0_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH0_CMD__cmd__cmd__continue 3
+#define R_DMA_CH0_CMD__cmd__cmd__hold 0
+#define R_DMA_CH0_CMD__cmd__cmd__reset 4
+#define R_DMA_CH0_CMD__cmd__cmd__restart 3
+#define R_DMA_CH0_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH0_DESCR
+ * - type: RW
+ * - addr: 0xb000010c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH0_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000010c)
+#define R_DMA_CH0_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH0_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH0_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH0_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH0_DESCR__GET REG_GET_RW
+#define R_DMA_CH0_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH0_DESCR__SET REG_SET_RW
+#define R_DMA_CH0_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH0_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH0_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH0_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH0_DESCR__RD REG_RD_RW
+#define R_DMA_CH0_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH0_DESCR__WR REG_WR_RW
+#define R_DMA_CH0_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH0_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH0_DESCR__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_DMA_CH0_DESCR__FIRST 0
+#define R_DMA_CH0_DESCR__LAST 9
+#define R_DMA_CH0_DESCR__OFFSET 16
+/* end */
+
+#define R_DMA_CH0_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH0_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH0_DESCR__descr__MIN 0
+
+#define R_DMA_CH0_DESCR__descr__BITNR 0
+
+#define R_DMA_CH0_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH0_FIRST
+ * - type: RW
+ * - addr: 0xb00001a0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH0_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a0)
+#define R_DMA_CH0_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH0_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH0_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH0_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH0_FIRST__GET REG_GET_RW
+#define R_DMA_CH0_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH0_FIRST__SET REG_SET_RW
+#define R_DMA_CH0_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH0_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH0_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH0_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH0_FIRST__RD REG_RD_RW
+#define R_DMA_CH0_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH0_FIRST__WR REG_WR_RW
+#define R_DMA_CH0_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH0_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH0_FIRST__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_DMA_CH0_FIRST__FIRST 0
+#define R_DMA_CH0_FIRST__LAST 9
+#define R_DMA_CH0_FIRST__OFFSET 4
+/* end */
+
+#define R_DMA_CH0_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH0_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH0_FIRST__first__MIN 0
+
+#define R_DMA_CH0_FIRST__first__BITNR 0
+
+#define R_DMA_CH0_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH0_HWSW
+ * - type: RW
+ * - addr: 0xb0000100
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH0_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000100)
+#define R_DMA_CH0_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH0_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH0_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH0_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH0_HWSW__GET REG_GET_RW
+#define R_DMA_CH0_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH0_HWSW__SET REG_SET_RW
+#define R_DMA_CH0_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH0_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH0_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH0_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH0_HWSW__RD REG_RD_RW
+#define R_DMA_CH0_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH0_HWSW__WR REG_WR_RW
+#define R_DMA_CH0_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH0_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH0_HWSW__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_DMA_CH0_HWSW__FIRST 0
+#define R_DMA_CH0_HWSW__LAST 9
+#define R_DMA_CH0_HWSW__OFFSET 16
+/* end */
+
+#define R_DMA_CH0_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH0_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH0_HWSW__hw__MAX 0xffff
+#define R_DMA_CH0_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH0_HWSW__hw__MIN 0
+#define R_DMA_CH0_HWSW__sw__MIN 0
+
+#define R_DMA_CH0_HWSW__hw__BITNR 16
+#define R_DMA_CH0_HWSW__sw__BITNR 0
+
+#define R_DMA_CH0_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH0_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH0_NEXT
+ * - type: RW
+ * - addr: 0xb0000104
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH0_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000104)
+#define R_DMA_CH0_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH0_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH0_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH0_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH0_NEXT__GET REG_GET_RW
+#define R_DMA_CH0_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH0_NEXT__SET REG_SET_RW
+#define R_DMA_CH0_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH0_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH0_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH0_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH0_NEXT__RD REG_RD_RW
+#define R_DMA_CH0_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH0_NEXT__WR REG_WR_RW
+#define R_DMA_CH0_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH0_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH0_NEXT__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_DMA_CH0_NEXT__FIRST 0
+#define R_DMA_CH0_NEXT__LAST 9
+#define R_DMA_CH0_NEXT__OFFSET 16
+/* end */
+
+#define R_DMA_CH0_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH0_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH0_NEXT__next__MIN 0
+
+#define R_DMA_CH0_NEXT__next__BITNR 0
+
+#define R_DMA_CH0_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH0_STATUS
+ * - type: RO
+ * - addr: 0xb00001d2
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH0_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001d2)
+#define R_DMA_CH0_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH0_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH0_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH0_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH0_STATUS__GET REG_GET_RO
+#define R_DMA_CH0_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH0_STATUS__SET REG_SET_RO
+#define R_DMA_CH0_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH0_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH0_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH0_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH0_STATUS__RD REG_RD_RO
+#define R_DMA_CH0_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH0_STATUS__WR REG_WR_RO
+#define R_DMA_CH0_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH0_STATUS__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_DMA_CH0_STATUS__FIRST 0
+#define R_DMA_CH0_STATUS__LAST 9
+#define R_DMA_CH0_STATUS__OFFSET 4
+/* end */
+
+#define R_DMA_CH0_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH0_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH0_STATUS__avail__MIN 0
+
+#define R_DMA_CH0_STATUS__avail__BITNR 0
+
+#define R_DMA_CH0_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH1_BUF
+ * - type: RW
+ * - addr: 0xb0000118
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH1_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000118)
+#define R_DMA_CH1_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH1_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH1_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH1_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH1_BUF__GET REG_GET_RW
+#define R_DMA_CH1_BUF__IGET REG_IGET_RW
+#define R_DMA_CH1_BUF__SET REG_SET_RW
+#define R_DMA_CH1_BUF__ISET REG_ISET_RW
+#define R_DMA_CH1_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH1_BUF__EQL REG_EQL_RW
+#define R_DMA_CH1_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH1_BUF__RD REG_RD_RW
+#define R_DMA_CH1_BUF__IRD REG_IRD_RW
+#define R_DMA_CH1_BUF__WR REG_WR_RW
+#define R_DMA_CH1_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH1_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH1_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH1_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH1_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH1_BUF__buf__MIN 0
+
+#define R_DMA_CH1_BUF__buf__BITNR 0
+
+#define R_DMA_CH1_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH1_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001d5
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH1_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d5)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH1_CLR_INTR + 0))
+#define R_DMA_CH1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH1_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH1_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH1_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH1_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH1_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH1_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH1_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH1_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH1_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH1_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH1_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH1_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH1_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH1_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH1_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH1_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH1_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH1_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH1_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH1_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH1_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH1_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH1_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH1_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH1_CMD
+ * - type: RW
+ * - addr: 0xb00001d4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH1_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d4)
+#define R_DMA_CH1_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH1_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH1_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH1_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH1_CMD__GET REG_GET_RW
+#define R_DMA_CH1_CMD__IGET REG_IGET_RW
+#define R_DMA_CH1_CMD__SET REG_SET_RW
+#define R_DMA_CH1_CMD__ISET REG_ISET_RW
+#define R_DMA_CH1_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH1_CMD__EQL REG_EQL_RW
+#define R_DMA_CH1_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH1_CMD__RD REG_RD_RW
+#define R_DMA_CH1_CMD__IRD REG_IRD_RW
+#define R_DMA_CH1_CMD__WR REG_WR_RW
+#define R_DMA_CH1_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH1_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH1_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH1_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH1_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH1_CMD__cmd__MIN 0
+
+#define R_DMA_CH1_CMD__cmd__BITNR 0
+
+#define R_DMA_CH1_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH1_CMD__cmd__cmd__continue 3
+#define R_DMA_CH1_CMD__cmd__cmd__hold 0
+#define R_DMA_CH1_CMD__cmd__cmd__reset 4
+#define R_DMA_CH1_CMD__cmd__cmd__restart 3
+#define R_DMA_CH1_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH1_DESCR
+ * - type: RW
+ * - addr: 0xb000011c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH1_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000011c)
+#define R_DMA_CH1_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH1_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH1_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH1_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH1_DESCR__GET REG_GET_RW
+#define R_DMA_CH1_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH1_DESCR__SET REG_SET_RW
+#define R_DMA_CH1_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH1_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH1_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH1_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH1_DESCR__RD REG_RD_RW
+#define R_DMA_CH1_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH1_DESCR__WR REG_WR_RW
+#define R_DMA_CH1_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH1_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH1_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH1_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH1_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH1_DESCR__descr__MIN 0
+
+#define R_DMA_CH1_DESCR__descr__BITNR 0
+
+#define R_DMA_CH1_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH1_FIRST
+ * - type: RW
+ * - addr: 0xb00001a4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH1_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a4)
+#define R_DMA_CH1_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH1_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH1_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH1_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH1_FIRST__GET REG_GET_RW
+#define R_DMA_CH1_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH1_FIRST__SET REG_SET_RW
+#define R_DMA_CH1_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH1_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH1_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH1_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH1_FIRST__RD REG_RD_RW
+#define R_DMA_CH1_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH1_FIRST__WR REG_WR_RW
+#define R_DMA_CH1_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH1_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH1_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH1_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH1_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH1_FIRST__first__MIN 0
+
+#define R_DMA_CH1_FIRST__first__BITNR 0
+
+#define R_DMA_CH1_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH1_HWSW
+ * - type: RW
+ * - addr: 0xb0000110
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH1_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000110)
+#define R_DMA_CH1_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH1_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH1_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH1_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH1_HWSW__GET REG_GET_RW
+#define R_DMA_CH1_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH1_HWSW__SET REG_SET_RW
+#define R_DMA_CH1_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH1_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH1_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH1_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH1_HWSW__RD REG_RD_RW
+#define R_DMA_CH1_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH1_HWSW__WR REG_WR_RW
+#define R_DMA_CH1_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH1_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH1_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH1_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH1_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH1_HWSW__hw__MAX 0xffff
+#define R_DMA_CH1_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH1_HWSW__hw__MIN 0
+#define R_DMA_CH1_HWSW__sw__MIN 0
+
+#define R_DMA_CH1_HWSW__hw__BITNR 16
+#define R_DMA_CH1_HWSW__sw__BITNR 0
+
+#define R_DMA_CH1_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH1_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH1_NEXT
+ * - type: RW
+ * - addr: 0xb0000114
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH1_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000114)
+#define R_DMA_CH1_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH1_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH1_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH1_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH1_NEXT__GET REG_GET_RW
+#define R_DMA_CH1_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH1_NEXT__SET REG_SET_RW
+#define R_DMA_CH1_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH1_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH1_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH1_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH1_NEXT__RD REG_RD_RW
+#define R_DMA_CH1_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH1_NEXT__WR REG_WR_RW
+#define R_DMA_CH1_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH1_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH1_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH1_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH1_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH1_NEXT__next__MIN 0
+
+#define R_DMA_CH1_NEXT__next__BITNR 0
+
+#define R_DMA_CH1_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH1_STATUS
+ * - type: RO
+ * - addr: 0xb00001d6
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH1_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001d6)
+#define R_DMA_CH1_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH1_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH1_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH1_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH1_STATUS__GET REG_GET_RO
+#define R_DMA_CH1_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH1_STATUS__SET REG_SET_RO
+#define R_DMA_CH1_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH1_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH1_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH1_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH1_STATUS__RD REG_RD_RO
+#define R_DMA_CH1_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH1_STATUS__WR REG_WR_RO
+#define R_DMA_CH1_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH1_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH1_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH1_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH1_STATUS__avail__MIN 0
+
+#define R_DMA_CH1_STATUS__avail__BITNR 0
+
+#define R_DMA_CH1_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH2_BUF
+ * - type: RW
+ * - addr: 0xb0000128
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH2_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000128)
+#define R_DMA_CH2_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH2_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH2_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH2_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH2_BUF__GET REG_GET_RW
+#define R_DMA_CH2_BUF__IGET REG_IGET_RW
+#define R_DMA_CH2_BUF__SET REG_SET_RW
+#define R_DMA_CH2_BUF__ISET REG_ISET_RW
+#define R_DMA_CH2_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH2_BUF__EQL REG_EQL_RW
+#define R_DMA_CH2_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH2_BUF__RD REG_RD_RW
+#define R_DMA_CH2_BUF__IRD REG_IRD_RW
+#define R_DMA_CH2_BUF__WR REG_WR_RW
+#define R_DMA_CH2_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH2_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH2_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH2_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH2_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH2_BUF__buf__MIN 0
+
+#define R_DMA_CH2_BUF__buf__BITNR 0
+
+#define R_DMA_CH2_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH2_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001d9
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH2_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001d9)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH2_CLR_INTR + 0))
+#define R_DMA_CH2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH2_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH2_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH2_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH2_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH2_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH2_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH2_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH2_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH2_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH2_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH2_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH2_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH2_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH2_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH2_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH2_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH2_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH2_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH2_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH2_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH2_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH2_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH2_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH2_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH2_CMD
+ * - type: RW
+ * - addr: 0xb00001d8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH2_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d8)
+#define R_DMA_CH2_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH2_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH2_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH2_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH2_CMD__GET REG_GET_RW
+#define R_DMA_CH2_CMD__IGET REG_IGET_RW
+#define R_DMA_CH2_CMD__SET REG_SET_RW
+#define R_DMA_CH2_CMD__ISET REG_ISET_RW
+#define R_DMA_CH2_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH2_CMD__EQL REG_EQL_RW
+#define R_DMA_CH2_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH2_CMD__RD REG_RD_RW
+#define R_DMA_CH2_CMD__IRD REG_IRD_RW
+#define R_DMA_CH2_CMD__WR REG_WR_RW
+#define R_DMA_CH2_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH2_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH2_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH2_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH2_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH2_CMD__cmd__MIN 0
+
+#define R_DMA_CH2_CMD__cmd__BITNR 0
+
+#define R_DMA_CH2_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH2_CMD__cmd__cmd__continue 3
+#define R_DMA_CH2_CMD__cmd__cmd__hold 0
+#define R_DMA_CH2_CMD__cmd__cmd__reset 4
+#define R_DMA_CH2_CMD__cmd__cmd__restart 3
+#define R_DMA_CH2_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH2_DESCR
+ * - type: RW
+ * - addr: 0xb000012c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH2_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000012c)
+#define R_DMA_CH2_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH2_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH2_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH2_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH2_DESCR__GET REG_GET_RW
+#define R_DMA_CH2_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH2_DESCR__SET REG_SET_RW
+#define R_DMA_CH2_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH2_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH2_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH2_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH2_DESCR__RD REG_RD_RW
+#define R_DMA_CH2_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH2_DESCR__WR REG_WR_RW
+#define R_DMA_CH2_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH2_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH2_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH2_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH2_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH2_DESCR__descr__MIN 0
+
+#define R_DMA_CH2_DESCR__descr__BITNR 0
+
+#define R_DMA_CH2_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH2_FIRST
+ * - type: RW
+ * - addr: 0xb00001a8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH2_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001a8)
+#define R_DMA_CH2_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH2_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH2_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH2_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH2_FIRST__GET REG_GET_RW
+#define R_DMA_CH2_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH2_FIRST__SET REG_SET_RW
+#define R_DMA_CH2_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH2_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH2_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH2_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH2_FIRST__RD REG_RD_RW
+#define R_DMA_CH2_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH2_FIRST__WR REG_WR_RW
+#define R_DMA_CH2_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH2_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH2_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH2_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH2_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH2_FIRST__first__MIN 0
+
+#define R_DMA_CH2_FIRST__first__BITNR 0
+
+#define R_DMA_CH2_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH2_HWSW
+ * - type: RW
+ * - addr: 0xb0000120
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH2_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000120)
+#define R_DMA_CH2_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH2_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH2_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH2_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH2_HWSW__GET REG_GET_RW
+#define R_DMA_CH2_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH2_HWSW__SET REG_SET_RW
+#define R_DMA_CH2_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH2_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH2_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH2_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH2_HWSW__RD REG_RD_RW
+#define R_DMA_CH2_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH2_HWSW__WR REG_WR_RW
+#define R_DMA_CH2_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH2_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH2_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH2_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH2_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH2_HWSW__hw__MAX 0xffff
+#define R_DMA_CH2_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH2_HWSW__hw__MIN 0
+#define R_DMA_CH2_HWSW__sw__MIN 0
+
+#define R_DMA_CH2_HWSW__hw__BITNR 16
+#define R_DMA_CH2_HWSW__sw__BITNR 0
+
+#define R_DMA_CH2_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH2_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH2_NEXT
+ * - type: RW
+ * - addr: 0xb0000124
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH2_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000124)
+#define R_DMA_CH2_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH2_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH2_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH2_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH2_NEXT__GET REG_GET_RW
+#define R_DMA_CH2_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH2_NEXT__SET REG_SET_RW
+#define R_DMA_CH2_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH2_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH2_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH2_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH2_NEXT__RD REG_RD_RW
+#define R_DMA_CH2_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH2_NEXT__WR REG_WR_RW
+#define R_DMA_CH2_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH2_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH2_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH2_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH2_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH2_NEXT__next__MIN 0
+
+#define R_DMA_CH2_NEXT__next__BITNR 0
+
+#define R_DMA_CH2_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH2_STATUS
+ * - type: RO
+ * - addr: 0xb00001da
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH2_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001da)
+#define R_DMA_CH2_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH2_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH2_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH2_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH2_STATUS__GET REG_GET_RO
+#define R_DMA_CH2_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH2_STATUS__SET REG_SET_RO
+#define R_DMA_CH2_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH2_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH2_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH2_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH2_STATUS__RD REG_RD_RO
+#define R_DMA_CH2_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH2_STATUS__WR REG_WR_RO
+#define R_DMA_CH2_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH2_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH2_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH2_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH2_STATUS__avail__MIN 0
+
+#define R_DMA_CH2_STATUS__avail__BITNR 0
+
+#define R_DMA_CH2_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH3_BUF
+ * - type: RW
+ * - addr: 0xb0000138
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH3_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000138)
+#define R_DMA_CH3_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH3_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH3_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH3_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH3_BUF__GET REG_GET_RW
+#define R_DMA_CH3_BUF__IGET REG_IGET_RW
+#define R_DMA_CH3_BUF__SET REG_SET_RW
+#define R_DMA_CH3_BUF__ISET REG_ISET_RW
+#define R_DMA_CH3_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH3_BUF__EQL REG_EQL_RW
+#define R_DMA_CH3_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH3_BUF__RD REG_RD_RW
+#define R_DMA_CH3_BUF__IRD REG_IRD_RW
+#define R_DMA_CH3_BUF__WR REG_WR_RW
+#define R_DMA_CH3_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH3_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH3_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH3_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH3_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH3_BUF__buf__MIN 0
+
+#define R_DMA_CH3_BUF__buf__BITNR 0
+
+#define R_DMA_CH3_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH3_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001dd
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH3_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001dd)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH3_CLR_INTR + 0))
+#define R_DMA_CH3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH3_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH3_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH3_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH3_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH3_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH3_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH3_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH3_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH3_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH3_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH3_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH3_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH3_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH3_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH3_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH3_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH3_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH3_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH3_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH3_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH3_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH3_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH3_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH3_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH3_CMD
+ * - type: RW
+ * - addr: 0xb00001dc
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH3_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001dc)
+#define R_DMA_CH3_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH3_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH3_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH3_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH3_CMD__GET REG_GET_RW
+#define R_DMA_CH3_CMD__IGET REG_IGET_RW
+#define R_DMA_CH3_CMD__SET REG_SET_RW
+#define R_DMA_CH3_CMD__ISET REG_ISET_RW
+#define R_DMA_CH3_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH3_CMD__EQL REG_EQL_RW
+#define R_DMA_CH3_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH3_CMD__RD REG_RD_RW
+#define R_DMA_CH3_CMD__IRD REG_IRD_RW
+#define R_DMA_CH3_CMD__WR REG_WR_RW
+#define R_DMA_CH3_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH3_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH3_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH3_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH3_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH3_CMD__cmd__MIN 0
+
+#define R_DMA_CH3_CMD__cmd__BITNR 0
+
+#define R_DMA_CH3_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH3_CMD__cmd__cmd__continue 3
+#define R_DMA_CH3_CMD__cmd__cmd__hold 0
+#define R_DMA_CH3_CMD__cmd__cmd__reset 4
+#define R_DMA_CH3_CMD__cmd__cmd__restart 3
+#define R_DMA_CH3_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH3_DESCR
+ * - type: RW
+ * - addr: 0xb000013c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH3_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000013c)
+#define R_DMA_CH3_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH3_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH3_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH3_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH3_DESCR__GET REG_GET_RW
+#define R_DMA_CH3_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH3_DESCR__SET REG_SET_RW
+#define R_DMA_CH3_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH3_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH3_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH3_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH3_DESCR__RD REG_RD_RW
+#define R_DMA_CH3_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH3_DESCR__WR REG_WR_RW
+#define R_DMA_CH3_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH3_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH3_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH3_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH3_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH3_DESCR__descr__MIN 0
+
+#define R_DMA_CH3_DESCR__descr__BITNR 0
+
+#define R_DMA_CH3_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH3_FIRST
+ * - type: RW
+ * - addr: 0xb00001ac
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH3_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001ac)
+#define R_DMA_CH3_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH3_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH3_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH3_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH3_FIRST__GET REG_GET_RW
+#define R_DMA_CH3_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH3_FIRST__SET REG_SET_RW
+#define R_DMA_CH3_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH3_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH3_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH3_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH3_FIRST__RD REG_RD_RW
+#define R_DMA_CH3_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH3_FIRST__WR REG_WR_RW
+#define R_DMA_CH3_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH3_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH3_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH3_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH3_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH3_FIRST__first__MIN 0
+
+#define R_DMA_CH3_FIRST__first__BITNR 0
+
+#define R_DMA_CH3_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH3_HWSW
+ * - type: RW
+ * - addr: 0xb0000130
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH3_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000130)
+#define R_DMA_CH3_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH3_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH3_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH3_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH3_HWSW__GET REG_GET_RW
+#define R_DMA_CH3_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH3_HWSW__SET REG_SET_RW
+#define R_DMA_CH3_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH3_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH3_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH3_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH3_HWSW__RD REG_RD_RW
+#define R_DMA_CH3_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH3_HWSW__WR REG_WR_RW
+#define R_DMA_CH3_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH3_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH3_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH3_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH3_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH3_HWSW__hw__MAX 0xffff
+#define R_DMA_CH3_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH3_HWSW__hw__MIN 0
+#define R_DMA_CH3_HWSW__sw__MIN 0
+
+#define R_DMA_CH3_HWSW__hw__BITNR 16
+#define R_DMA_CH3_HWSW__sw__BITNR 0
+
+#define R_DMA_CH3_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH3_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH3_NEXT
+ * - type: RW
+ * - addr: 0xb0000134
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH3_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000134)
+#define R_DMA_CH3_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH3_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH3_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH3_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH3_NEXT__GET REG_GET_RW
+#define R_DMA_CH3_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH3_NEXT__SET REG_SET_RW
+#define R_DMA_CH3_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH3_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH3_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH3_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH3_NEXT__RD REG_RD_RW
+#define R_DMA_CH3_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH3_NEXT__WR REG_WR_RW
+#define R_DMA_CH3_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH3_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH3_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH3_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH3_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH3_NEXT__next__MIN 0
+
+#define R_DMA_CH3_NEXT__next__BITNR 0
+
+#define R_DMA_CH3_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH3_STATUS
+ * - type: RO
+ * - addr: 0xb00001de
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH3_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001de)
+#define R_DMA_CH3_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH3_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH3_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH3_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH3_STATUS__GET REG_GET_RO
+#define R_DMA_CH3_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH3_STATUS__SET REG_SET_RO
+#define R_DMA_CH3_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH3_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH3_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH3_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH3_STATUS__RD REG_RD_RO
+#define R_DMA_CH3_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH3_STATUS__WR REG_WR_RO
+#define R_DMA_CH3_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH3_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH3_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH3_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH3_STATUS__avail__MIN 0
+
+#define R_DMA_CH3_STATUS__avail__BITNR 0
+
+#define R_DMA_CH3_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH4_BUF
+ * - type: RW
+ * - addr: 0xb0000148
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH4_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000148)
+#define R_DMA_CH4_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH4_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH4_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH4_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH4_BUF__GET REG_GET_RW
+#define R_DMA_CH4_BUF__IGET REG_IGET_RW
+#define R_DMA_CH4_BUF__SET REG_SET_RW
+#define R_DMA_CH4_BUF__ISET REG_ISET_RW
+#define R_DMA_CH4_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH4_BUF__EQL REG_EQL_RW
+#define R_DMA_CH4_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH4_BUF__RD REG_RD_RW
+#define R_DMA_CH4_BUF__IRD REG_IRD_RW
+#define R_DMA_CH4_BUF__WR REG_WR_RW
+#define R_DMA_CH4_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH4_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH4_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH4_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH4_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH4_BUF__buf__MIN 0
+
+#define R_DMA_CH4_BUF__buf__BITNR 0
+
+#define R_DMA_CH4_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH4_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e1
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH4_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e1)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH4_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH4_CLR_INTR + 0))
+#define R_DMA_CH4_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH4_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH4_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH4_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH4_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH4_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH4_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH4_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH4_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH4_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH4_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH4_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH4_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH4_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH4_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH4_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH4_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH4_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH4_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH4_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH4_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH4_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH4_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH4_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH4_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH4_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH4_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH4_CMD
+ * - type: RW
+ * - addr: 0xb00001e0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH4_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e0)
+#define R_DMA_CH4_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH4_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH4_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH4_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH4_CMD__GET REG_GET_RW
+#define R_DMA_CH4_CMD__IGET REG_IGET_RW
+#define R_DMA_CH4_CMD__SET REG_SET_RW
+#define R_DMA_CH4_CMD__ISET REG_ISET_RW
+#define R_DMA_CH4_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH4_CMD__EQL REG_EQL_RW
+#define R_DMA_CH4_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH4_CMD__RD REG_RD_RW
+#define R_DMA_CH4_CMD__IRD REG_IRD_RW
+#define R_DMA_CH4_CMD__WR REG_WR_RW
+#define R_DMA_CH4_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH4_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH4_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH4_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH4_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH4_CMD__cmd__MIN 0
+
+#define R_DMA_CH4_CMD__cmd__BITNR 0
+
+#define R_DMA_CH4_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH4_CMD__cmd__cmd__continue 3
+#define R_DMA_CH4_CMD__cmd__cmd__hold 0
+#define R_DMA_CH4_CMD__cmd__cmd__reset 4
+#define R_DMA_CH4_CMD__cmd__cmd__restart 3
+#define R_DMA_CH4_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH4_DESCR
+ * - type: RW
+ * - addr: 0xb000014c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH4_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000014c)
+#define R_DMA_CH4_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH4_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH4_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH4_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH4_DESCR__GET REG_GET_RW
+#define R_DMA_CH4_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH4_DESCR__SET REG_SET_RW
+#define R_DMA_CH4_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH4_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH4_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH4_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH4_DESCR__RD REG_RD_RW
+#define R_DMA_CH4_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH4_DESCR__WR REG_WR_RW
+#define R_DMA_CH4_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH4_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH4_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH4_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH4_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH4_DESCR__descr__MIN 0
+
+#define R_DMA_CH4_DESCR__descr__BITNR 0
+
+#define R_DMA_CH4_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH4_FIRST
+ * - type: RW
+ * - addr: 0xb00001b0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH4_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b0)
+#define R_DMA_CH4_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH4_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH4_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH4_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH4_FIRST__GET REG_GET_RW
+#define R_DMA_CH4_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH4_FIRST__SET REG_SET_RW
+#define R_DMA_CH4_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH4_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH4_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH4_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH4_FIRST__RD REG_RD_RW
+#define R_DMA_CH4_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH4_FIRST__WR REG_WR_RW
+#define R_DMA_CH4_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH4_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH4_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH4_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH4_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH4_FIRST__first__MIN 0
+
+#define R_DMA_CH4_FIRST__first__BITNR 0
+
+#define R_DMA_CH4_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH4_HWSW
+ * - type: RW
+ * - addr: 0xb0000140
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH4_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000140)
+#define R_DMA_CH4_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH4_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH4_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH4_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH4_HWSW__GET REG_GET_RW
+#define R_DMA_CH4_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH4_HWSW__SET REG_SET_RW
+#define R_DMA_CH4_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH4_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH4_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH4_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH4_HWSW__RD REG_RD_RW
+#define R_DMA_CH4_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH4_HWSW__WR REG_WR_RW
+#define R_DMA_CH4_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH4_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH4_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH4_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH4_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH4_HWSW__hw__MAX 0xffff
+#define R_DMA_CH4_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH4_HWSW__hw__MIN 0
+#define R_DMA_CH4_HWSW__sw__MIN 0
+
+#define R_DMA_CH4_HWSW__hw__BITNR 16
+#define R_DMA_CH4_HWSW__sw__BITNR 0
+
+#define R_DMA_CH4_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH4_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH4_NEXT
+ * - type: RW
+ * - addr: 0xb0000144
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH4_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000144)
+#define R_DMA_CH4_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH4_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH4_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH4_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH4_NEXT__GET REG_GET_RW
+#define R_DMA_CH4_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH4_NEXT__SET REG_SET_RW
+#define R_DMA_CH4_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH4_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH4_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH4_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH4_NEXT__RD REG_RD_RW
+#define R_DMA_CH4_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH4_NEXT__WR REG_WR_RW
+#define R_DMA_CH4_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH4_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH4_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH4_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH4_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH4_NEXT__next__MIN 0
+
+#define R_DMA_CH4_NEXT__next__BITNR 0
+
+#define R_DMA_CH4_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH4_STATUS
+ * - type: RO
+ * - addr: 0xb00001e2
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH4_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001e2)
+#define R_DMA_CH4_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH4_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH4_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH4_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH4_STATUS__GET REG_GET_RO
+#define R_DMA_CH4_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH4_STATUS__SET REG_SET_RO
+#define R_DMA_CH4_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH4_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH4_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH4_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH4_STATUS__RD REG_RD_RO
+#define R_DMA_CH4_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH4_STATUS__WR REG_WR_RO
+#define R_DMA_CH4_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH4_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH4_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH4_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH4_STATUS__avail__MIN 0
+
+#define R_DMA_CH4_STATUS__avail__BITNR 0
+
+#define R_DMA_CH4_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH5_BUF
+ * - type: RW
+ * - addr: 0xb0000158
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH5_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000158)
+#define R_DMA_CH5_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH5_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH5_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH5_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH5_BUF__GET REG_GET_RW
+#define R_DMA_CH5_BUF__IGET REG_IGET_RW
+#define R_DMA_CH5_BUF__SET REG_SET_RW
+#define R_DMA_CH5_BUF__ISET REG_ISET_RW
+#define R_DMA_CH5_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH5_BUF__EQL REG_EQL_RW
+#define R_DMA_CH5_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH5_BUF__RD REG_RD_RW
+#define R_DMA_CH5_BUF__IRD REG_IRD_RW
+#define R_DMA_CH5_BUF__WR REG_WR_RW
+#define R_DMA_CH5_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH5_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH5_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH5_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH5_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH5_BUF__buf__MIN 0
+
+#define R_DMA_CH5_BUF__buf__BITNR 0
+
+#define R_DMA_CH5_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH5_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e5
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH5_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e5)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH5_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH5_CLR_INTR + 0))
+#define R_DMA_CH5_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH5_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH5_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH5_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH5_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH5_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH5_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH5_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH5_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH5_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH5_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH5_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH5_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH5_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH5_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH5_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH5_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH5_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH5_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH5_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH5_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH5_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH5_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH5_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH5_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH5_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH5_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH5_CMD
+ * - type: RW
+ * - addr: 0xb00001e4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH5_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e4)
+#define R_DMA_CH5_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH5_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH5_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH5_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH5_CMD__GET REG_GET_RW
+#define R_DMA_CH5_CMD__IGET REG_IGET_RW
+#define R_DMA_CH5_CMD__SET REG_SET_RW
+#define R_DMA_CH5_CMD__ISET REG_ISET_RW
+#define R_DMA_CH5_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH5_CMD__EQL REG_EQL_RW
+#define R_DMA_CH5_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH5_CMD__RD REG_RD_RW
+#define R_DMA_CH5_CMD__IRD REG_IRD_RW
+#define R_DMA_CH5_CMD__WR REG_WR_RW
+#define R_DMA_CH5_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH5_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH5_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH5_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH5_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH5_CMD__cmd__MIN 0
+
+#define R_DMA_CH5_CMD__cmd__BITNR 0
+
+#define R_DMA_CH5_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH5_CMD__cmd__cmd__continue 3
+#define R_DMA_CH5_CMD__cmd__cmd__hold 0
+#define R_DMA_CH5_CMD__cmd__cmd__reset 4
+#define R_DMA_CH5_CMD__cmd__cmd__restart 3
+#define R_DMA_CH5_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH5_DESCR
+ * - type: RW
+ * - addr: 0xb000015c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH5_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000015c)
+#define R_DMA_CH5_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH5_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH5_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH5_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH5_DESCR__GET REG_GET_RW
+#define R_DMA_CH5_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH5_DESCR__SET REG_SET_RW
+#define R_DMA_CH5_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH5_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH5_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH5_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH5_DESCR__RD REG_RD_RW
+#define R_DMA_CH5_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH5_DESCR__WR REG_WR_RW
+#define R_DMA_CH5_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH5_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH5_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH5_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH5_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH5_DESCR__descr__MIN 0
+
+#define R_DMA_CH5_DESCR__descr__BITNR 0
+
+#define R_DMA_CH5_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH5_FIRST
+ * - type: RW
+ * - addr: 0xb00001b4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH5_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b4)
+#define R_DMA_CH5_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH5_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH5_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH5_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH5_FIRST__GET REG_GET_RW
+#define R_DMA_CH5_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH5_FIRST__SET REG_SET_RW
+#define R_DMA_CH5_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH5_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH5_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH5_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH5_FIRST__RD REG_RD_RW
+#define R_DMA_CH5_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH5_FIRST__WR REG_WR_RW
+#define R_DMA_CH5_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH5_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH5_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH5_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH5_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH5_FIRST__first__MIN 0
+
+#define R_DMA_CH5_FIRST__first__BITNR 0
+
+#define R_DMA_CH5_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH5_HWSW
+ * - type: RW
+ * - addr: 0xb0000150
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH5_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000150)
+#define R_DMA_CH5_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH5_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH5_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH5_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH5_HWSW__GET REG_GET_RW
+#define R_DMA_CH5_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH5_HWSW__SET REG_SET_RW
+#define R_DMA_CH5_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH5_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH5_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH5_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH5_HWSW__RD REG_RD_RW
+#define R_DMA_CH5_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH5_HWSW__WR REG_WR_RW
+#define R_DMA_CH5_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH5_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH5_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH5_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH5_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH5_HWSW__hw__MAX 0xffff
+#define R_DMA_CH5_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH5_HWSW__hw__MIN 0
+#define R_DMA_CH5_HWSW__sw__MIN 0
+
+#define R_DMA_CH5_HWSW__hw__BITNR 16
+#define R_DMA_CH5_HWSW__sw__BITNR 0
+
+#define R_DMA_CH5_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH5_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH5_NEXT
+ * - type: RW
+ * - addr: 0xb0000154
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH5_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000154)
+#define R_DMA_CH5_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH5_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH5_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH5_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH5_NEXT__GET REG_GET_RW
+#define R_DMA_CH5_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH5_NEXT__SET REG_SET_RW
+#define R_DMA_CH5_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH5_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH5_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH5_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH5_NEXT__RD REG_RD_RW
+#define R_DMA_CH5_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH5_NEXT__WR REG_WR_RW
+#define R_DMA_CH5_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH5_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH5_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH5_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH5_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH5_NEXT__next__MIN 0
+
+#define R_DMA_CH5_NEXT__next__BITNR 0
+
+#define R_DMA_CH5_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH5_STATUS
+ * - type: RO
+ * - addr: 0xb00001e6
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH5_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001e6)
+#define R_DMA_CH5_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH5_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH5_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH5_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH5_STATUS__GET REG_GET_RO
+#define R_DMA_CH5_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH5_STATUS__SET REG_SET_RO
+#define R_DMA_CH5_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH5_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH5_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH5_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH5_STATUS__RD REG_RD_RO
+#define R_DMA_CH5_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH5_STATUS__WR REG_WR_RO
+#define R_DMA_CH5_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH5_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH5_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH5_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH5_STATUS__avail__MIN 0
+
+#define R_DMA_CH5_STATUS__avail__BITNR 0
+
+#define R_DMA_CH5_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH6_BUF
+ * - type: RW
+ * - addr: 0xb0000168
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH6_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000168)
+#define R_DMA_CH6_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH6_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH6_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH6_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH6_BUF__GET REG_GET_RW
+#define R_DMA_CH6_BUF__IGET REG_IGET_RW
+#define R_DMA_CH6_BUF__SET REG_SET_RW
+#define R_DMA_CH6_BUF__ISET REG_ISET_RW
+#define R_DMA_CH6_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH6_BUF__EQL REG_EQL_RW
+#define R_DMA_CH6_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH6_BUF__RD REG_RD_RW
+#define R_DMA_CH6_BUF__IRD REG_IRD_RW
+#define R_DMA_CH6_BUF__WR REG_WR_RW
+#define R_DMA_CH6_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH6_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH6_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH6_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH6_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH6_BUF__buf__MIN 0
+
+#define R_DMA_CH6_BUF__buf__BITNR 0
+
+#define R_DMA_CH6_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH6_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e9
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH6_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e9)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH6_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH6_CLR_INTR + 0))
+#define R_DMA_CH6_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH6_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH6_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH6_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH6_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH6_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH6_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH6_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH6_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH6_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH6_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH6_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH6_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH6_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH6_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH6_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH6_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH6_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH6_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH6_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH6_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH6_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH6_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH6_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH6_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH6_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH6_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH6_CMD
+ * - type: RW
+ * - addr: 0xb00001e8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH6_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001e8)
+#define R_DMA_CH6_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH6_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH6_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH6_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH6_CMD__GET REG_GET_RW
+#define R_DMA_CH6_CMD__IGET REG_IGET_RW
+#define R_DMA_CH6_CMD__SET REG_SET_RW
+#define R_DMA_CH6_CMD__ISET REG_ISET_RW
+#define R_DMA_CH6_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH6_CMD__EQL REG_EQL_RW
+#define R_DMA_CH6_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH6_CMD__RD REG_RD_RW
+#define R_DMA_CH6_CMD__IRD REG_IRD_RW
+#define R_DMA_CH6_CMD__WR REG_WR_RW
+#define R_DMA_CH6_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH6_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH6_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH6_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH6_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH6_CMD__cmd__MIN 0
+
+#define R_DMA_CH6_CMD__cmd__BITNR 0
+
+#define R_DMA_CH6_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH6_CMD__cmd__cmd__continue 3
+#define R_DMA_CH6_CMD__cmd__cmd__hold 0
+#define R_DMA_CH6_CMD__cmd__cmd__reset 4
+#define R_DMA_CH6_CMD__cmd__cmd__restart 3
+#define R_DMA_CH6_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH6_DESCR
+ * - type: RW
+ * - addr: 0xb000016c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH6_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000016c)
+#define R_DMA_CH6_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH6_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH6_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH6_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH6_DESCR__GET REG_GET_RW
+#define R_DMA_CH6_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH6_DESCR__SET REG_SET_RW
+#define R_DMA_CH6_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH6_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH6_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH6_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH6_DESCR__RD REG_RD_RW
+#define R_DMA_CH6_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH6_DESCR__WR REG_WR_RW
+#define R_DMA_CH6_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH6_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH6_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH6_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH6_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH6_DESCR__descr__MIN 0
+
+#define R_DMA_CH6_DESCR__descr__BITNR 0
+
+#define R_DMA_CH6_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH6_FIRST
+ * - type: RW
+ * - addr: 0xb00001b8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH6_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001b8)
+#define R_DMA_CH6_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH6_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH6_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH6_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH6_FIRST__GET REG_GET_RW
+#define R_DMA_CH6_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH6_FIRST__SET REG_SET_RW
+#define R_DMA_CH6_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH6_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH6_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH6_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH6_FIRST__RD REG_RD_RW
+#define R_DMA_CH6_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH6_FIRST__WR REG_WR_RW
+#define R_DMA_CH6_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH6_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH6_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH6_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH6_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH6_FIRST__first__MIN 0
+
+#define R_DMA_CH6_FIRST__first__BITNR 0
+
+#define R_DMA_CH6_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH6_HWSW
+ * - type: RW
+ * - addr: 0xb0000160
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH6_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000160)
+#define R_DMA_CH6_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH6_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH6_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH6_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH6_HWSW__GET REG_GET_RW
+#define R_DMA_CH6_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH6_HWSW__SET REG_SET_RW
+#define R_DMA_CH6_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH6_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH6_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH6_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH6_HWSW__RD REG_RD_RW
+#define R_DMA_CH6_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH6_HWSW__WR REG_WR_RW
+#define R_DMA_CH6_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH6_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH6_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH6_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH6_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH6_HWSW__hw__MAX 0xffff
+#define R_DMA_CH6_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH6_HWSW__hw__MIN 0
+#define R_DMA_CH6_HWSW__sw__MIN 0
+
+#define R_DMA_CH6_HWSW__hw__BITNR 16
+#define R_DMA_CH6_HWSW__sw__BITNR 0
+
+#define R_DMA_CH6_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH6_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH6_NEXT
+ * - type: RW
+ * - addr: 0xb0000164
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH6_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000164)
+#define R_DMA_CH6_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH6_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH6_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH6_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH6_NEXT__GET REG_GET_RW
+#define R_DMA_CH6_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH6_NEXT__SET REG_SET_RW
+#define R_DMA_CH6_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH6_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH6_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH6_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH6_NEXT__RD REG_RD_RW
+#define R_DMA_CH6_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH6_NEXT__WR REG_WR_RW
+#define R_DMA_CH6_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH6_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH6_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH6_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH6_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH6_NEXT__next__MIN 0
+
+#define R_DMA_CH6_NEXT__next__BITNR 0
+
+#define R_DMA_CH6_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH6_STATUS
+ * - type: RO
+ * - addr: 0xb00001ea
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH6_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001ea)
+#define R_DMA_CH6_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH6_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH6_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH6_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH6_STATUS__GET REG_GET_RO
+#define R_DMA_CH6_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH6_STATUS__SET REG_SET_RO
+#define R_DMA_CH6_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH6_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH6_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH6_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH6_STATUS__RD REG_RD_RO
+#define R_DMA_CH6_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH6_STATUS__WR REG_WR_RO
+#define R_DMA_CH6_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH6_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH6_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH6_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH6_STATUS__avail__MIN 0
+
+#define R_DMA_CH6_STATUS__avail__BITNR 0
+
+#define R_DMA_CH6_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH7_BUF
+ * - type: RW
+ * - addr: 0xb0000178
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH7_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000178)
+#define R_DMA_CH7_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH7_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH7_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH7_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH7_BUF__GET REG_GET_RW
+#define R_DMA_CH7_BUF__IGET REG_IGET_RW
+#define R_DMA_CH7_BUF__SET REG_SET_RW
+#define R_DMA_CH7_BUF__ISET REG_ISET_RW
+#define R_DMA_CH7_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH7_BUF__EQL REG_EQL_RW
+#define R_DMA_CH7_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH7_BUF__RD REG_RD_RW
+#define R_DMA_CH7_BUF__IRD REG_IRD_RW
+#define R_DMA_CH7_BUF__WR REG_WR_RW
+#define R_DMA_CH7_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH7_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH7_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH7_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH7_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH7_BUF__buf__MIN 0
+
+#define R_DMA_CH7_BUF__buf__BITNR 0
+
+#define R_DMA_CH7_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH7_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001ed
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH7_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001ed)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH7_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH7_CLR_INTR + 0))
+#define R_DMA_CH7_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH7_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH7_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH7_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH7_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH7_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH7_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH7_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH7_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH7_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH7_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH7_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH7_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH7_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH7_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH7_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH7_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH7_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH7_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH7_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH7_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH7_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH7_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH7_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH7_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH7_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH7_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH7_CMD
+ * - type: RW
+ * - addr: 0xb00001ec
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH7_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001ec)
+#define R_DMA_CH7_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH7_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH7_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH7_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH7_CMD__GET REG_GET_RW
+#define R_DMA_CH7_CMD__IGET REG_IGET_RW
+#define R_DMA_CH7_CMD__SET REG_SET_RW
+#define R_DMA_CH7_CMD__ISET REG_ISET_RW
+#define R_DMA_CH7_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH7_CMD__EQL REG_EQL_RW
+#define R_DMA_CH7_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH7_CMD__RD REG_RD_RW
+#define R_DMA_CH7_CMD__IRD REG_IRD_RW
+#define R_DMA_CH7_CMD__WR REG_WR_RW
+#define R_DMA_CH7_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH7_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH7_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH7_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH7_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH7_CMD__cmd__MIN 0
+
+#define R_DMA_CH7_CMD__cmd__BITNR 0
+
+#define R_DMA_CH7_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH7_CMD__cmd__cmd__continue 3
+#define R_DMA_CH7_CMD__cmd__cmd__hold 0
+#define R_DMA_CH7_CMD__cmd__cmd__reset 4
+#define R_DMA_CH7_CMD__cmd__cmd__restart 3
+#define R_DMA_CH7_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH7_DESCR
+ * - type: RW
+ * - addr: 0xb000017c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH7_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000017c)
+#define R_DMA_CH7_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH7_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH7_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH7_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH7_DESCR__GET REG_GET_RW
+#define R_DMA_CH7_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH7_DESCR__SET REG_SET_RW
+#define R_DMA_CH7_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH7_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH7_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH7_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH7_DESCR__RD REG_RD_RW
+#define R_DMA_CH7_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH7_DESCR__WR REG_WR_RW
+#define R_DMA_CH7_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH7_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH7_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH7_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH7_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH7_DESCR__descr__MIN 0
+
+#define R_DMA_CH7_DESCR__descr__BITNR 0
+
+#define R_DMA_CH7_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH7_FIRST
+ * - type: RW
+ * - addr: 0xb00001bc
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH7_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001bc)
+#define R_DMA_CH7_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH7_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH7_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH7_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH7_FIRST__GET REG_GET_RW
+#define R_DMA_CH7_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH7_FIRST__SET REG_SET_RW
+#define R_DMA_CH7_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH7_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH7_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH7_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH7_FIRST__RD REG_RD_RW
+#define R_DMA_CH7_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH7_FIRST__WR REG_WR_RW
+#define R_DMA_CH7_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH7_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH7_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH7_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH7_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH7_FIRST__first__MIN 0
+
+#define R_DMA_CH7_FIRST__first__BITNR 0
+
+#define R_DMA_CH7_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH7_HWSW
+ * - type: RW
+ * - addr: 0xb0000170
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH7_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000170)
+#define R_DMA_CH7_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH7_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH7_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH7_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH7_HWSW__GET REG_GET_RW
+#define R_DMA_CH7_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH7_HWSW__SET REG_SET_RW
+#define R_DMA_CH7_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH7_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH7_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH7_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH7_HWSW__RD REG_RD_RW
+#define R_DMA_CH7_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH7_HWSW__WR REG_WR_RW
+#define R_DMA_CH7_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH7_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH7_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH7_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH7_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH7_HWSW__hw__MAX 0xffff
+#define R_DMA_CH7_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH7_HWSW__hw__MIN 0
+#define R_DMA_CH7_HWSW__sw__MIN 0
+
+#define R_DMA_CH7_HWSW__hw__BITNR 16
+#define R_DMA_CH7_HWSW__sw__BITNR 0
+
+#define R_DMA_CH7_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH7_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH7_NEXT
+ * - type: RW
+ * - addr: 0xb0000174
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH7_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000174)
+#define R_DMA_CH7_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH7_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH7_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH7_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH7_NEXT__GET REG_GET_RW
+#define R_DMA_CH7_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH7_NEXT__SET REG_SET_RW
+#define R_DMA_CH7_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH7_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH7_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH7_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH7_NEXT__RD REG_RD_RW
+#define R_DMA_CH7_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH7_NEXT__WR REG_WR_RW
+#define R_DMA_CH7_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH7_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH7_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH7_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH7_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH7_NEXT__next__MIN 0
+
+#define R_DMA_CH7_NEXT__next__BITNR 0
+
+#define R_DMA_CH7_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH7_STATUS
+ * - type: RO
+ * - addr: 0xb00001ee
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH7_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001ee)
+#define R_DMA_CH7_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH7_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH7_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH7_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH7_STATUS__GET REG_GET_RO
+#define R_DMA_CH7_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH7_STATUS__SET REG_SET_RO
+#define R_DMA_CH7_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH7_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH7_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH7_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH7_STATUS__RD REG_RD_RO
+#define R_DMA_CH7_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH7_STATUS__WR REG_WR_RO
+#define R_DMA_CH7_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH7_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH7_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH7_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH7_STATUS__avail__MIN 0
+
+#define R_DMA_CH7_STATUS__avail__BITNR 0
+
+#define R_DMA_CH7_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_BUF
+ * - type: RW
+ * - addr: 0xb0000188
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000188)
+#define R_DMA_CH8_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH8_BUF__GET REG_GET_RW
+#define R_DMA_CH8_BUF__IGET REG_IGET_RW
+#define R_DMA_CH8_BUF__SET REG_SET_RW
+#define R_DMA_CH8_BUF__ISET REG_ISET_RW
+#define R_DMA_CH8_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_BUF__EQL REG_EQL_RW
+#define R_DMA_CH8_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH8_BUF__RD REG_RD_RW
+#define R_DMA_CH8_BUF__IRD REG_IRD_RW
+#define R_DMA_CH8_BUF__WR REG_WR_RW
+#define R_DMA_CH8_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH8_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH8_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH8_BUF__buf__MIN 0
+
+#define R_DMA_CH8_BUF__buf__BITNR 0
+
+#define R_DMA_CH8_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001f1
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001f1)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH8_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_CLR_INTR + 0))
+#define R_DMA_CH8_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH8_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH8_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH8_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH8_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH8_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH8_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH8_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH8_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH8_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH8_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH8_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH8_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH8_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH8_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH8_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH8_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH8_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH8_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH8_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH8_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH8_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH8_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH8_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH8_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH8_CMD
+ * - type: RW
+ * - addr: 0xb00001f0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001f0)
+#define R_DMA_CH8_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH8_CMD__GET REG_GET_RW
+#define R_DMA_CH8_CMD__IGET REG_IGET_RW
+#define R_DMA_CH8_CMD__SET REG_SET_RW
+#define R_DMA_CH8_CMD__ISET REG_ISET_RW
+#define R_DMA_CH8_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_CMD__EQL REG_EQL_RW
+#define R_DMA_CH8_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH8_CMD__RD REG_RD_RW
+#define R_DMA_CH8_CMD__IRD REG_IRD_RW
+#define R_DMA_CH8_CMD__WR REG_WR_RW
+#define R_DMA_CH8_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH8_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH8_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH8_CMD__cmd__MIN 0
+
+#define R_DMA_CH8_CMD__cmd__BITNR 0
+
+#define R_DMA_CH8_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_CMD__cmd__cmd__continue 3
+#define R_DMA_CH8_CMD__cmd__cmd__hold 0
+#define R_DMA_CH8_CMD__cmd__cmd__reset 4
+#define R_DMA_CH8_CMD__cmd__cmd__restart 3
+#define R_DMA_CH8_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH8_DESCR
+ * - type: RW
+ * - addr: 0xb000018c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000018c)
+#define R_DMA_CH8_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH8_DESCR__GET REG_GET_RW
+#define R_DMA_CH8_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH8_DESCR__SET REG_SET_RW
+#define R_DMA_CH8_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH8_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH8_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH8_DESCR__RD REG_RD_RW
+#define R_DMA_CH8_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH8_DESCR__WR REG_WR_RW
+#define R_DMA_CH8_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH8_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH8_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH8_DESCR__descr__MIN 0
+
+#define R_DMA_CH8_DESCR__descr__BITNR 0
+
+#define R_DMA_CH8_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_FIRST
+ * - type: RW
+ * - addr: 0xb00001c0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001c0)
+#define R_DMA_CH8_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH8_FIRST__GET REG_GET_RW
+#define R_DMA_CH8_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH8_FIRST__SET REG_SET_RW
+#define R_DMA_CH8_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH8_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH8_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH8_FIRST__RD REG_RD_RW
+#define R_DMA_CH8_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH8_FIRST__WR REG_WR_RW
+#define R_DMA_CH8_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH8_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH8_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH8_FIRST__first__MIN 0
+
+#define R_DMA_CH8_FIRST__first__BITNR 0
+
+#define R_DMA_CH8_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_HWSW
+ * - type: RW
+ * - addr: 0xb0000180
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000180)
+#define R_DMA_CH8_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH8_HWSW__GET REG_GET_RW
+#define R_DMA_CH8_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH8_HWSW__SET REG_SET_RW
+#define R_DMA_CH8_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH8_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH8_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH8_HWSW__RD REG_RD_RW
+#define R_DMA_CH8_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH8_HWSW__WR REG_WR_RW
+#define R_DMA_CH8_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH8_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH8_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH8_HWSW__hw__MAX 0xffff
+#define R_DMA_CH8_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH8_HWSW__hw__MIN 0
+#define R_DMA_CH8_HWSW__sw__MIN 0
+
+#define R_DMA_CH8_HWSW__hw__BITNR 16
+#define R_DMA_CH8_HWSW__sw__BITNR 0
+
+#define R_DMA_CH8_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH8_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_NEP
+ * - type: RW
+ * - addr: 0xb00001c0
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_NEP__ADDR (REG_TYPECAST_UDWORD 0xb00001c0)
+#define R_DMA_CH8_NEP__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_NEP__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_NEP__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_NEP__TYPE (REG_UDWORD)
+#define R_DMA_CH8_NEP__GET REG_GET_RW
+#define R_DMA_CH8_NEP__IGET REG_IGET_RW
+#define R_DMA_CH8_NEP__SET REG_SET_RW
+#define R_DMA_CH8_NEP__ISET REG_ISET_RW
+#define R_DMA_CH8_NEP__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_NEP__EQL REG_EQL_RW
+#define R_DMA_CH8_NEP__IEQL REG_IEQL_RW
+#define R_DMA_CH8_NEP__RD REG_RD_RW
+#define R_DMA_CH8_NEP__IRD REG_IRD_RW
+#define R_DMA_CH8_NEP__WR REG_WR_RW
+#define R_DMA_CH8_NEP__IWR REG_IWR_RW
+
+#define R_DMA_CH8_NEP__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_NEP__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_NEP__nep__nep__MASK 0xffffffffU
+
+#define R_DMA_CH8_NEP__nep__MAX 0xffffffff
+
+#define R_DMA_CH8_NEP__nep__MIN 0
+
+#define R_DMA_CH8_NEP__nep__BITNR 0
+
+#define R_DMA_CH8_NEP__nep__nep__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_NEXT
+ * - type: RW
+ * - addr: 0xb0000184
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000184)
+#define R_DMA_CH8_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH8_NEXT__GET REG_GET_RW
+#define R_DMA_CH8_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH8_NEXT__SET REG_SET_RW
+#define R_DMA_CH8_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH8_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH8_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH8_NEXT__RD REG_RD_RW
+#define R_DMA_CH8_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH8_NEXT__WR REG_WR_RW
+#define R_DMA_CH8_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH8_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH8_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH8_NEXT__next__MIN 0
+
+#define R_DMA_CH8_NEXT__next__BITNR 0
+
+#define R_DMA_CH8_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_STATUS
+ * - type: RO
+ * - addr: 0xb00001f2
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001f2)
+#define R_DMA_CH8_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH8_STATUS__GET REG_GET_RO
+#define R_DMA_CH8_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH8_STATUS__SET REG_SET_RO
+#define R_DMA_CH8_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH8_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH8_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH8_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH8_STATUS__RD REG_RD_RO
+#define R_DMA_CH8_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH8_STATUS__WR REG_WR_RO
+#define R_DMA_CH8_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH8_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH8_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH8_STATUS__avail__MIN 0
+
+#define R_DMA_CH8_STATUS__avail__BITNR 0
+
+#define R_DMA_CH8_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB
+ * - type: RW
+ * - addr: 0xb000018c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB__ADDR (REG_TYPECAST_UDWORD 0xb000018c)
+#define R_DMA_CH8_SUB__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_SUB__TYPE (REG_UDWORD)
+#define R_DMA_CH8_SUB__GET REG_GET_RW
+#define R_DMA_CH8_SUB__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB__SET REG_SET_RW
+#define R_DMA_CH8_SUB__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB__RD REG_RD_RW
+#define R_DMA_CH8_SUB__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB__WR REG_WR_RW
+#define R_DMA_CH8_SUB__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB__sub__sub__MASK 0xffffffffU
+
+#define R_DMA_CH8_SUB__sub__MAX 0xffffffff
+
+#define R_DMA_CH8_SUB__sub__MIN 0
+
+#define R_DMA_CH8_SUB__sub__BITNR 0
+
+#define R_DMA_CH8_SUB__sub__sub__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB0_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e3
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB0_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e3)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH8_SUB0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB0_CLR_INTR + 0))
+#define R_DMA_CH8_SUB0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB0_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH8_SUB0_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH8_SUB0_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH8_SUB0_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH8_SUB0_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH8_SUB0_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH8_SUB0_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_SUB0_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH8_SUB0_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH8_SUB0_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH8_SUB0_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB0_CMD
+ * - type: RW
+ * - addr: 0xb00001d3
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB0_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d3)
+#define R_DMA_CH8_SUB0_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB0_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB0_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_SUB0_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH8_SUB0_CMD__GET REG_GET_RW
+#define R_DMA_CH8_SUB0_CMD__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB0_CMD__SET REG_SET_RW
+#define R_DMA_CH8_SUB0_CMD__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB0_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB0_CMD__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB0_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB0_CMD__RD REG_RD_RW
+#define R_DMA_CH8_SUB0_CMD__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB0_CMD__WR REG_WR_RW
+#define R_DMA_CH8_SUB0_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB0_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB0_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB0_CMD__cmd__cmd__MASK 0x00000001U
+
+#define R_DMA_CH8_SUB0_CMD__cmd__MAX 0x1
+
+#define R_DMA_CH8_SUB0_CMD__cmd__MIN 0
+
+#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0
+
+#define R_DMA_CH8_SUB0_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_SUB0_CMD__cmd__cmd__start 1
+#define R_DMA_CH8_SUB0_CMD__cmd__cmd__stop 0
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB0_EP
+ * - type: RW
+ * - addr: 0xb00001c8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB0_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001c8)
+#define R_DMA_CH8_SUB0_EP__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB0_EP__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB0_EP__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_SUB0_EP__TYPE (REG_UDWORD)
+#define R_DMA_CH8_SUB0_EP__GET REG_GET_RW
+#define R_DMA_CH8_SUB0_EP__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB0_EP__SET REG_SET_RW
+#define R_DMA_CH8_SUB0_EP__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB0_EP__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB0_EP__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB0_EP__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB0_EP__RD REG_RD_RW
+#define R_DMA_CH8_SUB0_EP__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB0_EP__WR REG_WR_RW
+#define R_DMA_CH8_SUB0_EP__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB0_EP__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB0_EP__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB0_EP__ep__ep__MASK 0xffffffffU
+
+#define R_DMA_CH8_SUB0_EP__ep__MAX 0xffffffff
+
+#define R_DMA_CH8_SUB0_EP__ep__MIN 0
+
+#define R_DMA_CH8_SUB0_EP__ep__BITNR 0
+
+#define R_DMA_CH8_SUB0_EP__ep__ep__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB1_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001e7
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB1_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001e7)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH8_SUB1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB1_CLR_INTR + 0))
+#define R_DMA_CH8_SUB1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB1_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH8_SUB1_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH8_SUB1_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH8_SUB1_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH8_SUB1_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH8_SUB1_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH8_SUB1_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_SUB1_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH8_SUB1_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH8_SUB1_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH8_SUB1_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB1_CMD
+ * - type: RW
+ * - addr: 0xb00001d7
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB1_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001d7)
+#define R_DMA_CH8_SUB1_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB1_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB1_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_SUB1_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH8_SUB1_CMD__GET REG_GET_RW
+#define R_DMA_CH8_SUB1_CMD__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB1_CMD__SET REG_SET_RW
+#define R_DMA_CH8_SUB1_CMD__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB1_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB1_CMD__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB1_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB1_CMD__RD REG_RD_RW
+#define R_DMA_CH8_SUB1_CMD__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB1_CMD__WR REG_WR_RW
+#define R_DMA_CH8_SUB1_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB1_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB1_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB1_CMD__cmd__cmd__MASK 0x00000001U
+
+#define R_DMA_CH8_SUB1_CMD__cmd__MAX 0x1
+
+#define R_DMA_CH8_SUB1_CMD__cmd__MIN 0
+
+#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0
+
+#define R_DMA_CH8_SUB1_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_SUB1_CMD__cmd__cmd__start 1
+#define R_DMA_CH8_SUB1_CMD__cmd__cmd__stop 0
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB1_EP
+ * - type: RW
+ * - addr: 0xb00001cc
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB1_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001cc)
+#define R_DMA_CH8_SUB1_EP__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB1_EP__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB1_EP__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_SUB1_EP__TYPE (REG_UDWORD)
+#define R_DMA_CH8_SUB1_EP__GET REG_GET_RW
+#define R_DMA_CH8_SUB1_EP__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB1_EP__SET REG_SET_RW
+#define R_DMA_CH8_SUB1_EP__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB1_EP__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB1_EP__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB1_EP__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB1_EP__RD REG_RD_RW
+#define R_DMA_CH8_SUB1_EP__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB1_EP__WR REG_WR_RW
+#define R_DMA_CH8_SUB1_EP__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB1_EP__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB1_EP__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB1_EP__ep__ep__MASK 0xffffffffU
+
+#define R_DMA_CH8_SUB1_EP__ep__MAX 0xffffffff
+
+#define R_DMA_CH8_SUB1_EP__ep__MIN 0
+
+#define R_DMA_CH8_SUB1_EP__ep__BITNR 0
+
+#define R_DMA_CH8_SUB1_EP__ep__ep__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB2_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001eb
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB2_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001eb)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH8_SUB2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB2_CLR_INTR + 0))
+#define R_DMA_CH8_SUB2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB2_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH8_SUB2_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH8_SUB2_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH8_SUB2_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH8_SUB2_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH8_SUB2_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH8_SUB2_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_SUB2_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH8_SUB2_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH8_SUB2_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH8_SUB2_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB2_CMD
+ * - type: RW
+ * - addr: 0xb00001db
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB2_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001db)
+#define R_DMA_CH8_SUB2_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB2_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB2_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_SUB2_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH8_SUB2_CMD__GET REG_GET_RW
+#define R_DMA_CH8_SUB2_CMD__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB2_CMD__SET REG_SET_RW
+#define R_DMA_CH8_SUB2_CMD__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB2_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB2_CMD__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB2_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB2_CMD__RD REG_RD_RW
+#define R_DMA_CH8_SUB2_CMD__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB2_CMD__WR REG_WR_RW
+#define R_DMA_CH8_SUB2_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB2_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB2_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB2_CMD__cmd__cmd__MASK 0x00000001U
+
+#define R_DMA_CH8_SUB2_CMD__cmd__MAX 0x1
+
+#define R_DMA_CH8_SUB2_CMD__cmd__MIN 0
+
+#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0
+
+#define R_DMA_CH8_SUB2_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_SUB2_CMD__cmd__cmd__start 1
+#define R_DMA_CH8_SUB2_CMD__cmd__cmd__stop 0
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB2_EP
+ * - type: RW
+ * - addr: 0xb00001f8
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB2_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001f8)
+#define R_DMA_CH8_SUB2_EP__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB2_EP__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB2_EP__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_SUB2_EP__TYPE (REG_UDWORD)
+#define R_DMA_CH8_SUB2_EP__GET REG_GET_RW
+#define R_DMA_CH8_SUB2_EP__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB2_EP__SET REG_SET_RW
+#define R_DMA_CH8_SUB2_EP__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB2_EP__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB2_EP__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB2_EP__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB2_EP__RD REG_RD_RW
+#define R_DMA_CH8_SUB2_EP__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB2_EP__WR REG_WR_RW
+#define R_DMA_CH8_SUB2_EP__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB2_EP__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB2_EP__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB2_EP__ep__ep__MASK 0xffffffffU
+
+#define R_DMA_CH8_SUB2_EP__ep__MAX 0xffffffff
+
+#define R_DMA_CH8_SUB2_EP__ep__MIN 0
+
+#define R_DMA_CH8_SUB2_EP__ep__BITNR 0
+
+#define R_DMA_CH8_SUB2_EP__ep__ep__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB3_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001ef
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB3_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001ef)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH8_SUB3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH8_SUB3_CLR_INTR + 0))
+#define R_DMA_CH8_SUB3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH8_SUB3_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH8_SUB3_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH8_SUB3_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH8_SUB3_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH8_SUB3_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH8_SUB3_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH8_SUB3_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_SUB3_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH8_SUB3_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH8_SUB3_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH8_SUB3_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB3_CMD
+ * - type: RW
+ * - addr: 0xb00001df
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB3_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001df)
+#define R_DMA_CH8_SUB3_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB3_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB3_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH8_SUB3_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH8_SUB3_CMD__GET REG_GET_RW
+#define R_DMA_CH8_SUB3_CMD__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB3_CMD__SET REG_SET_RW
+#define R_DMA_CH8_SUB3_CMD__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB3_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB3_CMD__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB3_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB3_CMD__RD REG_RD_RW
+#define R_DMA_CH8_SUB3_CMD__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB3_CMD__WR REG_WR_RW
+#define R_DMA_CH8_SUB3_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB3_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB3_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB3_CMD__cmd__cmd__MASK 0x00000001U
+
+#define R_DMA_CH8_SUB3_CMD__cmd__MAX 0x1
+
+#define R_DMA_CH8_SUB3_CMD__cmd__MIN 0
+
+#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0
+
+#define R_DMA_CH8_SUB3_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH8_SUB3_CMD__cmd__cmd__start 1
+#define R_DMA_CH8_SUB3_CMD__cmd__cmd__stop 0
+
+#endif
+
+/*
+ * R_DMA_CH8_SUB3_EP
+ * - type: RW
+ * - addr: 0xb00001fc
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH8_SUB3_EP__ADDR (REG_TYPECAST_UDWORD 0xb00001fc)
+#define R_DMA_CH8_SUB3_EP__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH8_SUB3_EP__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH8_SUB3_EP__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH8_SUB3_EP__TYPE (REG_UDWORD)
+#define R_DMA_CH8_SUB3_EP__GET REG_GET_RW
+#define R_DMA_CH8_SUB3_EP__IGET REG_IGET_RW
+#define R_DMA_CH8_SUB3_EP__SET REG_SET_RW
+#define R_DMA_CH8_SUB3_EP__ISET REG_ISET_RW
+#define R_DMA_CH8_SUB3_EP__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH8_SUB3_EP__EQL REG_EQL_RW
+#define R_DMA_CH8_SUB3_EP__IEQL REG_IEQL_RW
+#define R_DMA_CH8_SUB3_EP__RD REG_RD_RW
+#define R_DMA_CH8_SUB3_EP__IRD REG_IRD_RW
+#define R_DMA_CH8_SUB3_EP__WR REG_WR_RW
+#define R_DMA_CH8_SUB3_EP__IWR REG_IWR_RW
+
+#define R_DMA_CH8_SUB3_EP__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH8_SUB3_EP__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH8_SUB3_EP__ep__ep__MASK 0xffffffffU
+
+#define R_DMA_CH8_SUB3_EP__ep__MAX 0xffffffff
+
+#define R_DMA_CH8_SUB3_EP__ep__MIN 0
+
+#define R_DMA_CH8_SUB3_EP__ep__BITNR 0
+
+#define R_DMA_CH8_SUB3_EP__ep__ep__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH9_BUF
+ * - type: RW
+ * - addr: 0xb0000198
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH9_BUF__ADDR (REG_TYPECAST_UDWORD 0xb0000198)
+#define R_DMA_CH9_BUF__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH9_BUF__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH9_BUF__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH9_BUF__TYPE (REG_UDWORD)
+#define R_DMA_CH9_BUF__GET REG_GET_RW
+#define R_DMA_CH9_BUF__IGET REG_IGET_RW
+#define R_DMA_CH9_BUF__SET REG_SET_RW
+#define R_DMA_CH9_BUF__ISET REG_ISET_RW
+#define R_DMA_CH9_BUF__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH9_BUF__EQL REG_EQL_RW
+#define R_DMA_CH9_BUF__IEQL REG_IEQL_RW
+#define R_DMA_CH9_BUF__RD REG_RD_RW
+#define R_DMA_CH9_BUF__IRD REG_IRD_RW
+#define R_DMA_CH9_BUF__WR REG_WR_RW
+#define R_DMA_CH9_BUF__IWR REG_IWR_RW
+
+#define R_DMA_CH9_BUF__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH9_BUF__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH9_BUF__buf__buf__MASK 0xffffffffU
+
+#define R_DMA_CH9_BUF__buf__MAX 0xffffffff
+
+#define R_DMA_CH9_BUF__buf__MIN 0
+
+#define R_DMA_CH9_BUF__buf__BITNR 0
+
+#define R_DMA_CH9_BUF__buf__buf__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH9_CLR_INTR
+ * - type: WO
+ * - addr: 0xb00001f5
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH9_CLR_INTR__ADDR (REG_TYPECAST_BYTE 0xb00001f5)
+
+#ifndef REG_NO_SHADOW
+#define R_DMA_CH9_CLR_INTR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_DMA_CH9_CLR_INTR + 0))
+#define R_DMA_CH9_CLR_INTR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_DMA_CH9_CLR_INTR + 0))
+#else /* REG_NO_SHADOW */
+#define R_DMA_CH9_CLR_INTR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_DMA_CH9_CLR_INTR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DMA_CH9_CLR_INTR__STYPECAST REG_STYPECAST_BYTE
+#define R_DMA_CH9_CLR_INTR__SVAL REG_SVAL_ZERO
+#define R_DMA_CH9_CLR_INTR__SVAL_I REG_SVAL_I_ZERO
+#define R_DMA_CH9_CLR_INTR__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH9_CLR_INTR__TYPE (REG_BYTE)
+#define R_DMA_CH9_CLR_INTR__GET REG_GET_WO
+#define R_DMA_CH9_CLR_INTR__IGET REG_IGET_WO
+#define R_DMA_CH9_CLR_INTR__SET REG_SET_WO
+#define R_DMA_CH9_CLR_INTR__ISET REG_ISET_WO
+#define R_DMA_CH9_CLR_INTR__SET_VAL REG_SET_VAL_WO
+#define R_DMA_CH9_CLR_INTR__EQL REG_EQL_WO
+#define R_DMA_CH9_CLR_INTR__IEQL REG_IEQL_WO
+#define R_DMA_CH9_CLR_INTR__RD REG_RD_WO
+#define R_DMA_CH9_CLR_INTR__IRD REG_IRD_WO
+#define R_DMA_CH9_CLR_INTR__WR REG_WR_WO
+#define R_DMA_CH9_CLR_INTR__IWR REG_IWR_WO
+
+#define R_DMA_CH9_CLR_INTR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__MASK 0x00000002U
+#define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__MASK 0x00000001U
+
+#define R_DMA_CH9_CLR_INTR__clr_eop__MAX 0x1
+#define R_DMA_CH9_CLR_INTR__clr_descr__MAX 0x1
+
+#define R_DMA_CH9_CLR_INTR__clr_eop__MIN 0
+#define R_DMA_CH9_CLR_INTR__clr_descr__MIN 0
+
+#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0
+
+#define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__VAL REG_VAL_ENUM
+#define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__VAL REG_VAL_ENUM
+
+#define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__do 1
+#define R_DMA_CH9_CLR_INTR__clr_eop__clr_eop__dont 0
+#define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__do 1
+#define R_DMA_CH9_CLR_INTR__clr_descr__clr_descr__dont 0
+
+#endif
+
+/*
+ * R_DMA_CH9_CMD
+ * - type: RW
+ * - addr: 0xb00001f4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH9_CMD__ADDR (REG_TYPECAST_BYTE 0xb00001f4)
+#define R_DMA_CH9_CMD__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH9_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH9_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH9_CMD__TYPE (REG_BYTE)
+#define R_DMA_CH9_CMD__GET REG_GET_RW
+#define R_DMA_CH9_CMD__IGET REG_IGET_RW
+#define R_DMA_CH9_CMD__SET REG_SET_RW
+#define R_DMA_CH9_CMD__ISET REG_ISET_RW
+#define R_DMA_CH9_CMD__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH9_CMD__EQL REG_EQL_RW
+#define R_DMA_CH9_CMD__IEQL REG_IEQL_RW
+#define R_DMA_CH9_CMD__RD REG_RD_RW
+#define R_DMA_CH9_CMD__IRD REG_IRD_RW
+#define R_DMA_CH9_CMD__WR REG_WR_RW
+#define R_DMA_CH9_CMD__IWR REG_IWR_RW
+
+#define R_DMA_CH9_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH9_CMD__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH9_CMD__cmd__cmd__MASK 0x00000007U
+
+#define R_DMA_CH9_CMD__cmd__MAX 0x7
+
+#define R_DMA_CH9_CMD__cmd__MIN 0
+
+#define R_DMA_CH9_CMD__cmd__BITNR 0
+
+#define R_DMA_CH9_CMD__cmd__cmd__VAL REG_VAL_ENUM
+
+#define R_DMA_CH9_CMD__cmd__cmd__continue 3
+#define R_DMA_CH9_CMD__cmd__cmd__hold 0
+#define R_DMA_CH9_CMD__cmd__cmd__reset 4
+#define R_DMA_CH9_CMD__cmd__cmd__restart 3
+#define R_DMA_CH9_CMD__cmd__cmd__start 1
+
+#endif
+
+/*
+ * R_DMA_CH9_DESCR
+ * - type: RW
+ * - addr: 0xb000019c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH9_DESCR__ADDR (REG_TYPECAST_UDWORD 0xb000019c)
+#define R_DMA_CH9_DESCR__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH9_DESCR__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH9_DESCR__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH9_DESCR__TYPE (REG_UDWORD)
+#define R_DMA_CH9_DESCR__GET REG_GET_RW
+#define R_DMA_CH9_DESCR__IGET REG_IGET_RW
+#define R_DMA_CH9_DESCR__SET REG_SET_RW
+#define R_DMA_CH9_DESCR__ISET REG_ISET_RW
+#define R_DMA_CH9_DESCR__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH9_DESCR__EQL REG_EQL_RW
+#define R_DMA_CH9_DESCR__IEQL REG_IEQL_RW
+#define R_DMA_CH9_DESCR__RD REG_RD_RW
+#define R_DMA_CH9_DESCR__IRD REG_IRD_RW
+#define R_DMA_CH9_DESCR__WR REG_WR_RW
+#define R_DMA_CH9_DESCR__IWR REG_IWR_RW
+
+#define R_DMA_CH9_DESCR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH9_DESCR__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH9_DESCR__descr__descr__MASK 0xffffffffU
+
+#define R_DMA_CH9_DESCR__descr__MAX 0xffffffff
+
+#define R_DMA_CH9_DESCR__descr__MIN 0
+
+#define R_DMA_CH9_DESCR__descr__BITNR 0
+
+#define R_DMA_CH9_DESCR__descr__descr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH9_FIRST
+ * - type: RW
+ * - addr: 0xb00001c4
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH9_FIRST__ADDR (REG_TYPECAST_UDWORD 0xb00001c4)
+#define R_DMA_CH9_FIRST__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH9_FIRST__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH9_FIRST__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH9_FIRST__TYPE (REG_UDWORD)
+#define R_DMA_CH9_FIRST__GET REG_GET_RW
+#define R_DMA_CH9_FIRST__IGET REG_IGET_RW
+#define R_DMA_CH9_FIRST__SET REG_SET_RW
+#define R_DMA_CH9_FIRST__ISET REG_ISET_RW
+#define R_DMA_CH9_FIRST__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH9_FIRST__EQL REG_EQL_RW
+#define R_DMA_CH9_FIRST__IEQL REG_IEQL_RW
+#define R_DMA_CH9_FIRST__RD REG_RD_RW
+#define R_DMA_CH9_FIRST__IRD REG_IRD_RW
+#define R_DMA_CH9_FIRST__WR REG_WR_RW
+#define R_DMA_CH9_FIRST__IWR REG_IWR_RW
+
+#define R_DMA_CH9_FIRST__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH9_FIRST__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH9_FIRST__first__first__MASK 0xffffffffU
+
+#define R_DMA_CH9_FIRST__first__MAX 0xffffffff
+
+#define R_DMA_CH9_FIRST__first__MIN 0
+
+#define R_DMA_CH9_FIRST__first__BITNR 0
+
+#define R_DMA_CH9_FIRST__first__first__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH9_HWSW
+ * - type: RW
+ * - addr: 0xb0000190
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH9_HWSW__ADDR (REG_TYPECAST_UDWORD 0xb0000190)
+#define R_DMA_CH9_HWSW__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH9_HWSW__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH9_HWSW__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH9_HWSW__TYPE (REG_UDWORD)
+#define R_DMA_CH9_HWSW__GET REG_GET_RW
+#define R_DMA_CH9_HWSW__IGET REG_IGET_RW
+#define R_DMA_CH9_HWSW__SET REG_SET_RW
+#define R_DMA_CH9_HWSW__ISET REG_ISET_RW
+#define R_DMA_CH9_HWSW__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH9_HWSW__EQL REG_EQL_RW
+#define R_DMA_CH9_HWSW__IEQL REG_IEQL_RW
+#define R_DMA_CH9_HWSW__RD REG_RD_RW
+#define R_DMA_CH9_HWSW__IRD REG_IRD_RW
+#define R_DMA_CH9_HWSW__WR REG_WR_RW
+#define R_DMA_CH9_HWSW__IWR REG_IWR_RW
+
+#define R_DMA_CH9_HWSW__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH9_HWSW__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH9_HWSW__hw__hw__MASK 0xffff0000U
+#define R_DMA_CH9_HWSW__sw__sw__MASK 0x0000ffffU
+
+#define R_DMA_CH9_HWSW__hw__MAX 0xffff
+#define R_DMA_CH9_HWSW__sw__MAX 0xffff
+
+#define R_DMA_CH9_HWSW__hw__MIN 0
+#define R_DMA_CH9_HWSW__sw__MIN 0
+
+#define R_DMA_CH9_HWSW__hw__BITNR 16
+#define R_DMA_CH9_HWSW__sw__BITNR 0
+
+#define R_DMA_CH9_HWSW__hw__hw__VAL REG_VAL_VAL
+#define R_DMA_CH9_HWSW__sw__sw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH9_NEXT
+ * - type: RW
+ * - addr: 0xb0000194
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH9_NEXT__ADDR (REG_TYPECAST_UDWORD 0xb0000194)
+#define R_DMA_CH9_NEXT__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH9_NEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH9_NEXT__TYPECAST REG_TYPECAST_UDWORD
+#define R_DMA_CH9_NEXT__TYPE (REG_UDWORD)
+#define R_DMA_CH9_NEXT__GET REG_GET_RW
+#define R_DMA_CH9_NEXT__IGET REG_IGET_RW
+#define R_DMA_CH9_NEXT__SET REG_SET_RW
+#define R_DMA_CH9_NEXT__ISET REG_ISET_RW
+#define R_DMA_CH9_NEXT__SET_VAL REG_SET_VAL_RW
+#define R_DMA_CH9_NEXT__EQL REG_EQL_RW
+#define R_DMA_CH9_NEXT__IEQL REG_IEQL_RW
+#define R_DMA_CH9_NEXT__RD REG_RD_RW
+#define R_DMA_CH9_NEXT__IRD REG_IRD_RW
+#define R_DMA_CH9_NEXT__WR REG_WR_RW
+#define R_DMA_CH9_NEXT__IWR REG_IWR_RW
+
+#define R_DMA_CH9_NEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_DMA_CH9_NEXT__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH9_NEXT__next__next__MASK 0xffffffffU
+
+#define R_DMA_CH9_NEXT__next__MAX 0xffffffff
+
+#define R_DMA_CH9_NEXT__next__MIN 0
+
+#define R_DMA_CH9_NEXT__next__BITNR 0
+
+#define R_DMA_CH9_NEXT__next__next__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DMA_CH9_STATUS
+ * - type: RO
+ * - addr: 0xb00001f6
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_DMA_CH9_STATUS__ADDR (REG_TYPECAST_BYTE 0xb00001f6)
+#define R_DMA_CH9_STATUS__SVAL REG_SVAL_SHADOW
+#define R_DMA_CH9_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_DMA_CH9_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_DMA_CH9_STATUS__TYPE (REG_BYTE)
+#define R_DMA_CH9_STATUS__GET REG_GET_RO
+#define R_DMA_CH9_STATUS__IGET REG_IGET_RO
+#define R_DMA_CH9_STATUS__SET REG_SET_RO
+#define R_DMA_CH9_STATUS__ISET REG_ISET_RO
+#define R_DMA_CH9_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_DMA_CH9_STATUS__EQL REG_EQL_RO
+#define R_DMA_CH9_STATUS__IEQL REG_IEQL_RO
+#define R_DMA_CH9_STATUS__RD REG_RD_RO
+#define R_DMA_CH9_STATUS__IRD REG_IRD_RO
+#define R_DMA_CH9_STATUS__WR REG_WR_RO
+#define R_DMA_CH9_STATUS__IWR REG_IWR_RO
+
+#define R_DMA_CH9_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_DMA_CH9_STATUS__avail__avail__MASK 0x0000007fU
+
+#define R_DMA_CH9_STATUS__avail__MAX 0x7f
+
+#define R_DMA_CH9_STATUS__avail__MIN 0
+
+#define R_DMA_CH9_STATUS__avail__BITNR 0
+
+#define R_DMA_CH9_STATUS__avail__avail__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_DRAM_CONFIG
+ * - type: WO
+ * - addr: 0xb000000c
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+#define R_DRAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000000c)
+
+#ifndef REG_NO_SHADOW
+#define R_DRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_CONFIG + 0))
+#define R_DRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_DRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_DRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DRAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_DRAM_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_DRAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_DRAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_DRAM_CONFIG__TYPE (REG_UDWORD)
+#define R_DRAM_CONFIG__GET REG_GET_WO
+#define R_DRAM_CONFIG__IGET REG_IGET_WO
+#define R_DRAM_CONFIG__SET REG_SET_WO
+#define R_DRAM_CONFIG__ISET REG_ISET_WO
+#define R_DRAM_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_DRAM_CONFIG__EQL REG_EQL_WO
+#define R_DRAM_CONFIG__IEQL REG_IEQL_WO
+#define R_DRAM_CONFIG__RD REG_RD_WO
+#define R_DRAM_CONFIG__IRD REG_IRD_WO
+#define R_DRAM_CONFIG__WR REG_WR_WO
+#define R_DRAM_CONFIG__IWR REG_IWR_WO
+
+#define R_DRAM_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DRAM_CONFIG__wmm1__wmm1__MASK 0x80000000U
+#define R_DRAM_CONFIG__wmm0__wmm0__MASK 0x40000000U
+#define R_DRAM_CONFIG__sh1__sh1__MASK 0x38000000U
+#define R_DRAM_CONFIG__sh0__sh0__MASK 0x07000000U
+#define R_DRAM_CONFIG__w__w__MASK 0x00800000U
+#define R_DRAM_CONFIG__c__c__MASK 0x00400000U
+#define R_DRAM_CONFIG__e__e__MASK 0x00200000U
+#define R_DRAM_CONFIG__group_sel__group_sel__MASK 0x001f0000U
+#define R_DRAM_CONFIG__ca1__ca1__MASK 0x0000e000U
+#define R_DRAM_CONFIG__bank23sel__bank23sel__MASK 0x00001f00U
+#define R_DRAM_CONFIG__ca0__ca0__MASK 0x000000e0U
+#define R_DRAM_CONFIG__bank01sel__bank01sel__MASK 0x0000001fU
+
+#define R_DRAM_CONFIG__wmm1__MAX 0x1
+#define R_DRAM_CONFIG__wmm0__MAX 0x1
+#define R_DRAM_CONFIG__sh1__MAX 7
+#define R_DRAM_CONFIG__sh0__MAX 7
+#define R_DRAM_CONFIG__w__MAX 0x1
+#define R_DRAM_CONFIG__c__MAX 0x1
+#define R_DRAM_CONFIG__e__MAX 0x1
+#define R_DRAM_CONFIG__group_sel__MAX 0x1f
+#define R_DRAM_CONFIG__ca1__MAX 7
+#define R_DRAM_CONFIG__bank23sel__MAX 0x1f
+#define R_DRAM_CONFIG__ca0__MAX 7
+#define R_DRAM_CONFIG__bank01sel__MAX 0x1f
+
+#define R_DRAM_CONFIG__wmm1__MIN 0
+#define R_DRAM_CONFIG__wmm0__MIN 0
+#define R_DRAM_CONFIG__sh1__MIN 0
+#define R_DRAM_CONFIG__sh0__MIN 0
+#define R_DRAM_CONFIG__w__MIN 0
+#define R_DRAM_CONFIG__c__MIN 0
+#define R_DRAM_CONFIG__e__MIN 0
+#define R_DRAM_CONFIG__group_sel__MIN 0
+#define R_DRAM_CONFIG__ca1__MIN 0
+#define R_DRAM_CONFIG__bank23sel__MIN 0
+#define R_DRAM_CONFIG__ca0__MIN 0
+#define R_DRAM_CONFIG__bank01sel__MIN 0
+
+#define R_DRAM_CONFIG__wmm1__BITNR 31
+#define R_DRAM_CONFIG__wmm0__BITNR 30
+#define R_DRAM_CONFIG__sh1__BITNR 27
+#define R_DRAM_CONFIG__sh0__BITNR 24
+#define R_DRAM_CONFIG__w__BITNR 23
+#define R_DRAM_CONFIG__c__BITNR 22
+#define R_DRAM_CONFIG__e__BITNR 21
+#define R_DRAM_CONFIG__group_sel__BITNR 16
+#define R_DRAM_CONFIG__ca1__BITNR 13
+#define R_DRAM_CONFIG__bank23sel__BITNR 8
+#define R_DRAM_CONFIG__ca0__BITNR 5
+#define R_DRAM_CONFIG__bank01sel__BITNR 0
+
+#define R_DRAM_CONFIG__wmm1__wmm1__VAL REG_VAL_ENUM
+#define R_DRAM_CONFIG__wmm0__wmm0__VAL REG_VAL_ENUM
+#define R_DRAM_CONFIG__sh1__sh1__VAL REG_VAL_VAL
+#define R_DRAM_CONFIG__sh0__sh0__VAL REG_VAL_VAL
+#define R_DRAM_CONFIG__w__w__VAL REG_VAL_ENUM
+#define R_DRAM_CONFIG__c__c__VAL REG_VAL_ENUM
+#define R_DRAM_CONFIG__e__e__VAL REG_VAL_ENUM
+#define R_DRAM_CONFIG__group_sel__group_sel__VAL REG_VAL_ENUM
+#define R_DRAM_CONFIG__ca1__ca1__VAL REG_VAL_VAL
+#define R_DRAM_CONFIG__bank23sel__bank23sel__VAL REG_VAL_ENUM
+#define R_DRAM_CONFIG__ca0__ca0__VAL REG_VAL_VAL
+#define R_DRAM_CONFIG__bank01sel__bank01sel__VAL REG_VAL_ENUM
+
+#define R_DRAM_CONFIG__wmm1__wmm1__norm 0
+#define R_DRAM_CONFIG__wmm1__wmm1__wmm 1
+#define R_DRAM_CONFIG__wmm0__wmm0__norm 0
+#define R_DRAM_CONFIG__wmm0__wmm0__wmm 1
+#define R_DRAM_CONFIG__w__w__bw16 0
+#define R_DRAM_CONFIG__w__w__bw32 1
+#define R_DRAM_CONFIG__c__c__bank 1
+#define R_DRAM_CONFIG__c__c__byte 0
+#define R_DRAM_CONFIG__e__e__edo 1
+#define R_DRAM_CONFIG__e__e__fast 0
+#define R_DRAM_CONFIG__group_sel__group_sel__bit10 10
+#define R_DRAM_CONFIG__group_sel__group_sel__bit11 11
+#define R_DRAM_CONFIG__group_sel__group_sel__bit12 12
+#define R_DRAM_CONFIG__group_sel__group_sel__bit13 13
+#define R_DRAM_CONFIG__group_sel__group_sel__bit14 14
+#define R_DRAM_CONFIG__group_sel__group_sel__bit15 15
+#define R_DRAM_CONFIG__group_sel__group_sel__bit16 16
+#define R_DRAM_CONFIG__group_sel__group_sel__bit17 17
+#define R_DRAM_CONFIG__group_sel__group_sel__bit18 18
+#define R_DRAM_CONFIG__group_sel__group_sel__bit19 19
+#define R_DRAM_CONFIG__group_sel__group_sel__bit20 20
+#define R_DRAM_CONFIG__group_sel__group_sel__bit21 21
+#define R_DRAM_CONFIG__group_sel__group_sel__bit22 22
+#define R_DRAM_CONFIG__group_sel__group_sel__bit23 23
+#define R_DRAM_CONFIG__group_sel__group_sel__bit24 24
+#define R_DRAM_CONFIG__group_sel__group_sel__bit25 25
+#define R_DRAM_CONFIG__group_sel__group_sel__bit26 26
+#define R_DRAM_CONFIG__group_sel__group_sel__bit27 27
+#define R_DRAM_CONFIG__group_sel__group_sel__bit28 28
+#define R_DRAM_CONFIG__group_sel__group_sel__bit29 29
+#define R_DRAM_CONFIG__group_sel__group_sel__bit9 9
+#define R_DRAM_CONFIG__group_sel__group_sel__grp0 0
+#define R_DRAM_CONFIG__group_sel__group_sel__grp1 1
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bank0 0
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bank1 1
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit10 10
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit11 11
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit12 12
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit13 13
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit14 14
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit15 15
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit16 16
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit17 17
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit18 18
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit19 19
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit20 20
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit21 21
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit22 22
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit23 23
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit24 24
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit25 25
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit26 26
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit27 27
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit28 28
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit29 29
+#define R_DRAM_CONFIG__bank23sel__bank23sel__bit9 9
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bank0 0
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bank1 1
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit10 10
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit11 11
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit12 12
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit13 13
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit14 14
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit15 15
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit16 16
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit17 17
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit18 18
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit19 19
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit20 20
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit21 21
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit22 22
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit23 23
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit24 24
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit25 25
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit26 26
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit27 27
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit28 28
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit29 29
+#define R_DRAM_CONFIG__bank01sel__bank01sel__bit9 9
+
+#endif
+
+/*
+ * R_DRAM_TIMING
+ * - type: WO
+ * - addr: 0xb0000008
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+#define R_DRAM_TIMING__ADDR (REG_TYPECAST_UDWORD 0xb0000008)
+
+#ifndef REG_NO_SHADOW
+#define R_DRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_TIMING + 0))
+#define R_DRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_TIMING + 0))
+#else /* REG_NO_SHADOW */
+#define R_DRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_DRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_DRAM_TIMING__STYPECAST REG_STYPECAST_UDWORD
+#define R_DRAM_TIMING__SVAL REG_SVAL_SHADOW
+#define R_DRAM_TIMING__SVAL_I REG_SVAL_I_SHADOW
+#define R_DRAM_TIMING__TYPECAST REG_TYPECAST_UDWORD
+#define R_DRAM_TIMING__TYPE (REG_UDWORD)
+#define R_DRAM_TIMING__GET REG_GET_WO
+#define R_DRAM_TIMING__IGET REG_IGET_WO
+#define R_DRAM_TIMING__SET REG_SET_WO
+#define R_DRAM_TIMING__ISET REG_ISET_WO
+#define R_DRAM_TIMING__SET_VAL REG_SET_VAL_WO
+#define R_DRAM_TIMING__EQL REG_EQL_WO
+#define R_DRAM_TIMING__IEQL REG_IEQL_WO
+#define R_DRAM_TIMING__RD REG_RD_WO
+#define R_DRAM_TIMING__IRD REG_IRD_WO
+#define R_DRAM_TIMING__WR REG_WR_WO
+#define R_DRAM_TIMING__IWR REG_IWR_WO
+
+#define R_DRAM_TIMING__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_DRAM_TIMING__sdram__sdram__MASK 0x80000000U
+#define R_DRAM_TIMING__ref__ref__MASK 0x0000c000U
+#define R_DRAM_TIMING__rp__rp__MASK 0x00003000U
+#define R_DRAM_TIMING__rs__rs__MASK 0x00000c00U
+#define R_DRAM_TIMING__rh__rh__MASK 0x00000300U
+#define R_DRAM_TIMING__w__w__MASK 0x00000080U
+#define R_DRAM_TIMING__c__c__MASK 0x00000040U
+#define R_DRAM_TIMING__cz__cz__MASK 0x00000030U
+#define R_DRAM_TIMING__cp__cp__MASK 0x0000000cU
+#define R_DRAM_TIMING__cw__cw__MASK 0x00000003U
+
+#define R_DRAM_TIMING__sdram__MAX 0x1
+#define R_DRAM_TIMING__ref__MAX 0x3
+#define R_DRAM_TIMING__rp__MAX 3
+#define R_DRAM_TIMING__rs__MAX 3
+#define R_DRAM_TIMING__rh__MAX 3
+#define R_DRAM_TIMING__w__MAX 0x1
+#define R_DRAM_TIMING__c__MAX 0x1
+#define R_DRAM_TIMING__cz__MAX 3
+#define R_DRAM_TIMING__cp__MAX 3
+#define R_DRAM_TIMING__cw__MAX 3
+
+#define R_DRAM_TIMING__sdram__MIN 0
+#define R_DRAM_TIMING__ref__MIN 0
+#define R_DRAM_TIMING__rp__MIN 0
+#define R_DRAM_TIMING__rs__MIN 0
+#define R_DRAM_TIMING__rh__MIN 0
+#define R_DRAM_TIMING__w__MIN 0
+#define R_DRAM_TIMING__c__MIN 0
+#define R_DRAM_TIMING__cz__MIN 0
+#define R_DRAM_TIMING__cp__MIN 0
+#define R_DRAM_TIMING__cw__MIN 0
+
+#define R_DRAM_TIMING__sdram__BITNR 31
+#define R_DRAM_TIMING__ref__BITNR 14
+#define R_DRAM_TIMING__rp__BITNR 12
+#define R_DRAM_TIMING__rs__BITNR 10
+#define R_DRAM_TIMING__rh__BITNR 8
+#define R_DRAM_TIMING__w__BITNR 7
+#define R_DRAM_TIMING__c__BITNR 6
+#define R_DRAM_TIMING__cz__BITNR 4
+#define R_DRAM_TIMING__cp__BITNR 2
+#define R_DRAM_TIMING__cw__BITNR 0
+
+#define R_DRAM_TIMING__sdram__sdram__VAL REG_VAL_ENUM
+#define R_DRAM_TIMING__ref__ref__VAL REG_VAL_ENUM
+#define R_DRAM_TIMING__rp__rp__VAL REG_VAL_VAL
+#define R_DRAM_TIMING__rs__rs__VAL REG_VAL_VAL
+#define R_DRAM_TIMING__rh__rh__VAL REG_VAL_VAL
+#define R_DRAM_TIMING__w__w__VAL REG_VAL_ENUM
+#define R_DRAM_TIMING__c__c__VAL REG_VAL_ENUM
+#define R_DRAM_TIMING__cz__cz__VAL REG_VAL_VAL
+#define R_DRAM_TIMING__cp__cp__VAL REG_VAL_VAL
+#define R_DRAM_TIMING__cw__cw__VAL REG_VAL_VAL
+
+#define R_DRAM_TIMING__sdram__sdram__disable 0
+#define R_DRAM_TIMING__sdram__sdram__enable 1
+#define R_DRAM_TIMING__ref__ref__disable 3
+#define R_DRAM_TIMING__ref__ref__e13us 1
+#define R_DRAM_TIMING__ref__ref__e52us 0
+#define R_DRAM_TIMING__ref__ref__e8700ns 2
+#define R_DRAM_TIMING__w__w__ext 1
+#define R_DRAM_TIMING__w__w__norm 0
+#define R_DRAM_TIMING__c__c__ext 1
+#define R_DRAM_TIMING__c__c__norm 0
+
+#endif
+
+/*
+ * R_EXT_DMA_0_ADDR
+ * - type: WO
+ * - addr: 0xb0000014
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+#define R_EXT_DMA_0_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb0000014)
+
+#ifndef REG_NO_SHADOW
+#define R_EXT_DMA_0_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_0_ADDR + 0))
+#define R_EXT_DMA_0_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_0_ADDR + 0))
+#else /* REG_NO_SHADOW */
+#define R_EXT_DMA_0_ADDR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_EXT_DMA_0_ADDR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_EXT_DMA_0_ADDR__STYPECAST REG_STYPECAST_UDWORD
+#define R_EXT_DMA_0_ADDR__SVAL REG_SVAL_SHADOW
+#define R_EXT_DMA_0_ADDR__SVAL_I REG_SVAL_I_SHADOW
+#define R_EXT_DMA_0_ADDR__TYPECAST REG_TYPECAST_UDWORD
+#define R_EXT_DMA_0_ADDR__TYPE (REG_UDWORD)
+#define R_EXT_DMA_0_ADDR__GET REG_GET_WO
+#define R_EXT_DMA_0_ADDR__IGET REG_IGET_WO
+#define R_EXT_DMA_0_ADDR__SET REG_SET_WO
+#define R_EXT_DMA_0_ADDR__ISET REG_ISET_WO
+#define R_EXT_DMA_0_ADDR__SET_VAL REG_SET_VAL_WO
+#define R_EXT_DMA_0_ADDR__EQL REG_EQL_WO
+#define R_EXT_DMA_0_ADDR__IEQL REG_IEQL_WO
+#define R_EXT_DMA_0_ADDR__RD REG_RD_WO
+#define R_EXT_DMA_0_ADDR__IRD REG_IRD_WO
+#define R_EXT_DMA_0_ADDR__WR REG_WR_WO
+#define R_EXT_DMA_0_ADDR__IWR REG_IWR_WO
+
+#define R_EXT_DMA_0_ADDR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_EXT_DMA_0_ADDR__FIRST 0
+#define R_EXT_DMA_0_ADDR__IOFFSET 8
+#define R_EXT_DMA_0_ADDR__LAST 1
+#define R_EXT_DMA_0_ADDR__OFFSET 8
+#define R_EXT_DMA_0_ADDR__SOFFSET 8
+/* end */
+
+#define R_EXT_DMA_0_ADDR__ext0_addr__ext0_addr__MASK 0x3ffffffcU
+
+#define R_EXT_DMA_0_ADDR__ext0_addr__MAX 0xfffffff
+
+#define R_EXT_DMA_0_ADDR__ext0_addr__MIN 0
+
+#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2
+
+#define R_EXT_DMA_0_ADDR__ext0_addr__ext0_addr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_EXT_DMA_0_CMD
+ * - type: WO
+ * - addr: 0xb0000010
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+#define R_EXT_DMA_0_CMD__ADDR (REG_TYPECAST_UDWORD 0xb0000010)
+
+#ifndef REG_NO_SHADOW
+#define R_EXT_DMA_0_CMD__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_0_CMD + 0))
+#define R_EXT_DMA_0_CMD__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_0_CMD + 0))
+#else /* REG_NO_SHADOW */
+#define R_EXT_DMA_0_CMD__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_EXT_DMA_0_CMD__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_EXT_DMA_0_CMD__STYPECAST REG_STYPECAST_UDWORD
+#define R_EXT_DMA_0_CMD__SVAL REG_SVAL_SHADOW
+#define R_EXT_DMA_0_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_EXT_DMA_0_CMD__TYPECAST REG_TYPECAST_UDWORD
+#define R_EXT_DMA_0_CMD__TYPE (REG_UDWORD)
+#define R_EXT_DMA_0_CMD__GET REG_GET_WO
+#define R_EXT_DMA_0_CMD__IGET REG_IGET_WO
+#define R_EXT_DMA_0_CMD__SET REG_SET_WO
+#define R_EXT_DMA_0_CMD__ISET REG_ISET_WO
+#define R_EXT_DMA_0_CMD__SET_VAL REG_SET_VAL_WO
+#define R_EXT_DMA_0_CMD__EQL REG_EQL_WO
+#define R_EXT_DMA_0_CMD__IEQL REG_IEQL_WO
+#define R_EXT_DMA_0_CMD__RD REG_RD_WO
+#define R_EXT_DMA_0_CMD__IRD REG_IRD_WO
+#define R_EXT_DMA_0_CMD__WR REG_WR_WO
+#define R_EXT_DMA_0_CMD__IWR REG_IWR_WO
+
+#define R_EXT_DMA_0_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_EXT_DMA_0_CMD__FIRST 0
+#define R_EXT_DMA_0_CMD__IOFFSET 8
+#define R_EXT_DMA_0_CMD__LAST 1
+#define R_EXT_DMA_0_CMD__OFFSET 8
+#define R_EXT_DMA_0_CMD__SOFFSET 8
+/* end */
+
+#define R_EXT_DMA_0_CMD__cnt__cnt__MASK 0x00800000U
+#define R_EXT_DMA_0_CMD__rqpol__rqpol__MASK 0x00400000U
+#define R_EXT_DMA_0_CMD__apol__apol__MASK 0x00200000U
+#define R_EXT_DMA_0_CMD__rq_ack__rq_ack__MASK 0x00100000U
+#define R_EXT_DMA_0_CMD__wid__wid__MASK 0x000c0000U
+#define R_EXT_DMA_0_CMD__dir__dir__MASK 0x00020000U
+#define R_EXT_DMA_0_CMD__run__run__MASK 0x00010000U
+#define R_EXT_DMA_0_CMD__trf_count__trf_count__MASK 0x0000ffffU
+
+#define R_EXT_DMA_0_CMD__cnt__MAX 0x1
+#define R_EXT_DMA_0_CMD__rqpol__MAX 0x1
+#define R_EXT_DMA_0_CMD__apol__MAX 0x1
+#define R_EXT_DMA_0_CMD__rq_ack__MAX 0x1
+#define R_EXT_DMA_0_CMD__wid__MAX 0x3
+#define R_EXT_DMA_0_CMD__dir__MAX 0x1
+#define R_EXT_DMA_0_CMD__run__MAX 0x1
+#define R_EXT_DMA_0_CMD__trf_count__MAX 0xffff
+
+#define R_EXT_DMA_0_CMD__cnt__MIN 0
+#define R_EXT_DMA_0_CMD__rqpol__MIN 0
+#define R_EXT_DMA_0_CMD__apol__MIN 0
+#define R_EXT_DMA_0_CMD__rq_ack__MIN 0
+#define R_EXT_DMA_0_CMD__wid__MIN 0
+#define R_EXT_DMA_0_CMD__dir__MIN 0
+#define R_EXT_DMA_0_CMD__run__MIN 0
+#define R_EXT_DMA_0_CMD__trf_count__MIN 0
+
+#define R_EXT_DMA_0_CMD__cnt__BITNR 23
+#define R_EXT_DMA_0_CMD__rqpol__BITNR 22
+#define R_EXT_DMA_0_CMD__apol__BITNR 21
+#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20
+#define R_EXT_DMA_0_CMD__wid__BITNR 18
+#define R_EXT_DMA_0_CMD__dir__BITNR 17
+#define R_EXT_DMA_0_CMD__run__BITNR 16
+#define R_EXT_DMA_0_CMD__trf_count__BITNR 0
+
+#define R_EXT_DMA_0_CMD__cnt__cnt__VAL REG_VAL_ENUM
+#define R_EXT_DMA_0_CMD__rqpol__rqpol__VAL REG_VAL_ENUM
+#define R_EXT_DMA_0_CMD__apol__apol__VAL REG_VAL_ENUM
+#define R_EXT_DMA_0_CMD__rq_ack__rq_ack__VAL REG_VAL_ENUM
+#define R_EXT_DMA_0_CMD__wid__wid__VAL REG_VAL_ENUM
+#define R_EXT_DMA_0_CMD__dir__dir__VAL REG_VAL_ENUM
+#define R_EXT_DMA_0_CMD__run__run__VAL REG_VAL_ENUM
+#define R_EXT_DMA_0_CMD__trf_count__trf_count__VAL REG_VAL_VAL
+
+#define R_EXT_DMA_0_CMD__cnt__cnt__disable 0
+#define R_EXT_DMA_0_CMD__cnt__cnt__enable 1
+#define R_EXT_DMA_0_CMD__rqpol__rqpol__ahigh 0
+#define R_EXT_DMA_0_CMD__rqpol__rqpol__alow 1
+#define R_EXT_DMA_0_CMD__apol__apol__ahigh 0
+#define R_EXT_DMA_0_CMD__apol__apol__alow 1
+#define R_EXT_DMA_0_CMD__rq_ack__rq_ack__burst 0
+#define R_EXT_DMA_0_CMD__rq_ack__rq_ack__handsh 1
+#define R_EXT_DMA_0_CMD__wid__wid__byte 0
+#define R_EXT_DMA_0_CMD__wid__wid__dword 2
+#define R_EXT_DMA_0_CMD__wid__wid__word 1
+#define R_EXT_DMA_0_CMD__dir__dir__input 0
+#define R_EXT_DMA_0_CMD__dir__dir__output 1
+#define R_EXT_DMA_0_CMD__run__run__start 1
+#define R_EXT_DMA_0_CMD__run__run__stop 0
+
+#endif
+
+/*
+ * R_EXT_DMA_0_STAT
+ * - type: RO
+ * - addr: 0xb0000010
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+#define R_EXT_DMA_0_STAT__ADDR (REG_TYPECAST_UDWORD 0xb0000010)
+#define R_EXT_DMA_0_STAT__SVAL REG_SVAL_SHADOW
+#define R_EXT_DMA_0_STAT__SVAL_I REG_SVAL_I_SHADOW
+#define R_EXT_DMA_0_STAT__TYPECAST REG_TYPECAST_UDWORD
+#define R_EXT_DMA_0_STAT__TYPE (REG_UDWORD)
+#define R_EXT_DMA_0_STAT__GET REG_GET_RO
+#define R_EXT_DMA_0_STAT__IGET REG_IGET_RO
+#define R_EXT_DMA_0_STAT__SET REG_SET_RO
+#define R_EXT_DMA_0_STAT__ISET REG_ISET_RO
+#define R_EXT_DMA_0_STAT__SET_VAL REG_SET_VAL_RO
+#define R_EXT_DMA_0_STAT__EQL REG_EQL_RO
+#define R_EXT_DMA_0_STAT__IEQL REG_IEQL_RO
+#define R_EXT_DMA_0_STAT__RD REG_RD_RO
+#define R_EXT_DMA_0_STAT__IRD REG_IRD_RO
+#define R_EXT_DMA_0_STAT__WR REG_WR_RO
+#define R_EXT_DMA_0_STAT__IWR REG_IWR_RO
+
+#define R_EXT_DMA_0_STAT__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_EXT_DMA_0_STAT__FIRST 0
+#define R_EXT_DMA_0_STAT__LAST 1
+#define R_EXT_DMA_0_STAT__OFFSET 8
+/* end */
+
+#define R_EXT_DMA_0_STAT__run__run__MASK 0x00010000U
+#define R_EXT_DMA_0_STAT__trf_count__trf_count__MASK 0x0000ffffU
+
+#define R_EXT_DMA_0_STAT__run__MAX 0x1
+#define R_EXT_DMA_0_STAT__trf_count__MAX 0xffff
+
+#define R_EXT_DMA_0_STAT__run__MIN 0
+#define R_EXT_DMA_0_STAT__trf_count__MIN 0
+
+#define R_EXT_DMA_0_STAT__run__BITNR 16
+#define R_EXT_DMA_0_STAT__trf_count__BITNR 0
+
+#define R_EXT_DMA_0_STAT__run__run__VAL REG_VAL_ENUM
+#define R_EXT_DMA_0_STAT__trf_count__trf_count__VAL REG_VAL_VAL
+
+#define R_EXT_DMA_0_STAT__run__run__start 1
+#define R_EXT_DMA_0_STAT__run__run__stop 0
+
+#endif
+
+/*
+ * R_EXT_DMA_1_ADDR
+ * - type: WO
+ * - addr: 0xb000001c
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+#define R_EXT_DMA_1_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb000001c)
+
+#ifndef REG_NO_SHADOW
+#define R_EXT_DMA_1_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_1_ADDR + 0))
+#define R_EXT_DMA_1_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_1_ADDR + 0))
+#else /* REG_NO_SHADOW */
+#define R_EXT_DMA_1_ADDR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_EXT_DMA_1_ADDR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_EXT_DMA_1_ADDR__STYPECAST REG_STYPECAST_UDWORD
+#define R_EXT_DMA_1_ADDR__SVAL REG_SVAL_SHADOW
+#define R_EXT_DMA_1_ADDR__SVAL_I REG_SVAL_I_SHADOW
+#define R_EXT_DMA_1_ADDR__TYPECAST REG_TYPECAST_UDWORD
+#define R_EXT_DMA_1_ADDR__TYPE (REG_UDWORD)
+#define R_EXT_DMA_1_ADDR__GET REG_GET_WO
+#define R_EXT_DMA_1_ADDR__IGET REG_IGET_WO
+#define R_EXT_DMA_1_ADDR__SET REG_SET_WO
+#define R_EXT_DMA_1_ADDR__ISET REG_ISET_WO
+#define R_EXT_DMA_1_ADDR__SET_VAL REG_SET_VAL_WO
+#define R_EXT_DMA_1_ADDR__EQL REG_EQL_WO
+#define R_EXT_DMA_1_ADDR__IEQL REG_IEQL_WO
+#define R_EXT_DMA_1_ADDR__RD REG_RD_WO
+#define R_EXT_DMA_1_ADDR__IRD REG_IRD_WO
+#define R_EXT_DMA_1_ADDR__WR REG_WR_WO
+#define R_EXT_DMA_1_ADDR__IWR REG_IWR_WO
+
+#define R_EXT_DMA_1_ADDR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_EXT_DMA_1_ADDR__ext0_addr__ext0_addr__MASK 0x3ffffffcU
+
+#define R_EXT_DMA_1_ADDR__ext0_addr__MAX 0xfffffff
+
+#define R_EXT_DMA_1_ADDR__ext0_addr__MIN 0
+
+#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2
+
+#define R_EXT_DMA_1_ADDR__ext0_addr__ext0_addr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_EXT_DMA_1_CMD
+ * - type: WO
+ * - addr: 0xb0000018
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+#define R_EXT_DMA_1_CMD__ADDR (REG_TYPECAST_UDWORD 0xb0000018)
+
+#ifndef REG_NO_SHADOW
+#define R_EXT_DMA_1_CMD__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_EXT_DMA_1_CMD + 0))
+#define R_EXT_DMA_1_CMD__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_EXT_DMA_1_CMD + 0))
+#else /* REG_NO_SHADOW */
+#define R_EXT_DMA_1_CMD__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_EXT_DMA_1_CMD__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_EXT_DMA_1_CMD__STYPECAST REG_STYPECAST_UDWORD
+#define R_EXT_DMA_1_CMD__SVAL REG_SVAL_SHADOW
+#define R_EXT_DMA_1_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_EXT_DMA_1_CMD__TYPECAST REG_TYPECAST_UDWORD
+#define R_EXT_DMA_1_CMD__TYPE (REG_UDWORD)
+#define R_EXT_DMA_1_CMD__GET REG_GET_WO
+#define R_EXT_DMA_1_CMD__IGET REG_IGET_WO
+#define R_EXT_DMA_1_CMD__SET REG_SET_WO
+#define R_EXT_DMA_1_CMD__ISET REG_ISET_WO
+#define R_EXT_DMA_1_CMD__SET_VAL REG_SET_VAL_WO
+#define R_EXT_DMA_1_CMD__EQL REG_EQL_WO
+#define R_EXT_DMA_1_CMD__IEQL REG_IEQL_WO
+#define R_EXT_DMA_1_CMD__RD REG_RD_WO
+#define R_EXT_DMA_1_CMD__IRD REG_IRD_WO
+#define R_EXT_DMA_1_CMD__WR REG_WR_WO
+#define R_EXT_DMA_1_CMD__IWR REG_IWR_WO
+
+#define R_EXT_DMA_1_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_EXT_DMA_1_CMD__cnt__cnt__MASK 0x00800000U
+#define R_EXT_DMA_1_CMD__rqpol__rqpol__MASK 0x00400000U
+#define R_EXT_DMA_1_CMD__apol__apol__MASK 0x00200000U
+#define R_EXT_DMA_1_CMD__rq_ack__rq_ack__MASK 0x00100000U
+#define R_EXT_DMA_1_CMD__wid__wid__MASK 0x000c0000U
+#define R_EXT_DMA_1_CMD__dir__dir__MASK 0x00020000U
+#define R_EXT_DMA_1_CMD__run__run__MASK 0x00010000U
+#define R_EXT_DMA_1_CMD__trf_count__trf_count__MASK 0x0000ffffU
+
+#define R_EXT_DMA_1_CMD__cnt__MAX 0x1
+#define R_EXT_DMA_1_CMD__rqpol__MAX 0x1
+#define R_EXT_DMA_1_CMD__apol__MAX 0x1
+#define R_EXT_DMA_1_CMD__rq_ack__MAX 0x1
+#define R_EXT_DMA_1_CMD__wid__MAX 0x3
+#define R_EXT_DMA_1_CMD__dir__MAX 0x1
+#define R_EXT_DMA_1_CMD__run__MAX 0x1
+#define R_EXT_DMA_1_CMD__trf_count__MAX 0xffff
+
+#define R_EXT_DMA_1_CMD__cnt__MIN 0
+#define R_EXT_DMA_1_CMD__rqpol__MIN 0
+#define R_EXT_DMA_1_CMD__apol__MIN 0
+#define R_EXT_DMA_1_CMD__rq_ack__MIN 0
+#define R_EXT_DMA_1_CMD__wid__MIN 0
+#define R_EXT_DMA_1_CMD__dir__MIN 0
+#define R_EXT_DMA_1_CMD__run__MIN 0
+#define R_EXT_DMA_1_CMD__trf_count__MIN 0
+
+#define R_EXT_DMA_1_CMD__cnt__BITNR 23
+#define R_EXT_DMA_1_CMD__rqpol__BITNR 22
+#define R_EXT_DMA_1_CMD__apol__BITNR 21
+#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20
+#define R_EXT_DMA_1_CMD__wid__BITNR 18
+#define R_EXT_DMA_1_CMD__dir__BITNR 17
+#define R_EXT_DMA_1_CMD__run__BITNR 16
+#define R_EXT_DMA_1_CMD__trf_count__BITNR 0
+
+#define R_EXT_DMA_1_CMD__cnt__cnt__VAL REG_VAL_ENUM
+#define R_EXT_DMA_1_CMD__rqpol__rqpol__VAL REG_VAL_ENUM
+#define R_EXT_DMA_1_CMD__apol__apol__VAL REG_VAL_ENUM
+#define R_EXT_DMA_1_CMD__rq_ack__rq_ack__VAL REG_VAL_ENUM
+#define R_EXT_DMA_1_CMD__wid__wid__VAL REG_VAL_ENUM
+#define R_EXT_DMA_1_CMD__dir__dir__VAL REG_VAL_ENUM
+#define R_EXT_DMA_1_CMD__run__run__VAL REG_VAL_ENUM
+#define R_EXT_DMA_1_CMD__trf_count__trf_count__VAL REG_VAL_VAL
+
+#define R_EXT_DMA_1_CMD__cnt__cnt__disable 0
+#define R_EXT_DMA_1_CMD__cnt__cnt__enable 1
+#define R_EXT_DMA_1_CMD__rqpol__rqpol__ahigh 0
+#define R_EXT_DMA_1_CMD__rqpol__rqpol__alow 1
+#define R_EXT_DMA_1_CMD__apol__apol__ahigh 0
+#define R_EXT_DMA_1_CMD__apol__apol__alow 1
+#define R_EXT_DMA_1_CMD__rq_ack__rq_ack__burst 0
+#define R_EXT_DMA_1_CMD__rq_ack__rq_ack__handsh 1
+#define R_EXT_DMA_1_CMD__wid__wid__byte 0
+#define R_EXT_DMA_1_CMD__wid__wid__dword 2
+#define R_EXT_DMA_1_CMD__wid__wid__word 1
+#define R_EXT_DMA_1_CMD__dir__dir__input 0
+#define R_EXT_DMA_1_CMD__dir__dir__output 1
+#define R_EXT_DMA_1_CMD__run__run__start 1
+#define R_EXT_DMA_1_CMD__run__run__stop 0
+
+#endif
+
+/*
+ * R_EXT_DMA_1_STAT
+ * - type: RO
+ * - addr: 0xb0000018
+ * - group: External DMA registers
+ */
+
+#if USE_GROUP__External_DMA_registers
+
+#define R_EXT_DMA_1_STAT__ADDR (REG_TYPECAST_UDWORD 0xb0000018)
+#define R_EXT_DMA_1_STAT__SVAL REG_SVAL_SHADOW
+#define R_EXT_DMA_1_STAT__SVAL_I REG_SVAL_I_SHADOW
+#define R_EXT_DMA_1_STAT__TYPECAST REG_TYPECAST_UDWORD
+#define R_EXT_DMA_1_STAT__TYPE (REG_UDWORD)
+#define R_EXT_DMA_1_STAT__GET REG_GET_RO
+#define R_EXT_DMA_1_STAT__IGET REG_IGET_RO
+#define R_EXT_DMA_1_STAT__SET REG_SET_RO
+#define R_EXT_DMA_1_STAT__ISET REG_ISET_RO
+#define R_EXT_DMA_1_STAT__SET_VAL REG_SET_VAL_RO
+#define R_EXT_DMA_1_STAT__EQL REG_EQL_RO
+#define R_EXT_DMA_1_STAT__IEQL REG_IEQL_RO
+#define R_EXT_DMA_1_STAT__RD REG_RD_RO
+#define R_EXT_DMA_1_STAT__IRD REG_IRD_RO
+#define R_EXT_DMA_1_STAT__WR REG_WR_RO
+#define R_EXT_DMA_1_STAT__IWR REG_IWR_RO
+
+#define R_EXT_DMA_1_STAT__READ(addr) \
+ (*(addr))
+
+#define R_EXT_DMA_1_STAT__run__run__MASK 0x00010000U
+#define R_EXT_DMA_1_STAT__trf_count__trf_count__MASK 0x0000ffffU
+
+#define R_EXT_DMA_1_STAT__run__MAX 0x1
+#define R_EXT_DMA_1_STAT__trf_count__MAX 0xffff
+
+#define R_EXT_DMA_1_STAT__run__MIN 0
+#define R_EXT_DMA_1_STAT__trf_count__MIN 0
+
+#define R_EXT_DMA_1_STAT__run__BITNR 16
+#define R_EXT_DMA_1_STAT__trf_count__BITNR 0
+
+#define R_EXT_DMA_1_STAT__run__run__VAL REG_VAL_ENUM
+#define R_EXT_DMA_1_STAT__trf_count__trf_count__VAL REG_VAL_VAL
+
+#define R_EXT_DMA_1_STAT__run__run__start 1
+#define R_EXT_DMA_1_STAT__run__run__stop 0
+
+#endif
+
+/*
+ * R_GEN_CONFIG
+ * - type: WO
+ * - addr: 0xb000002c
+ * - group: General config registers
+ */
+
+#if USE_GROUP__General_config_registers
+
+#define R_GEN_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000002c)
+
+#ifndef REG_NO_SHADOW
+#define R_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_GEN_CONFIG + 0))
+#define R_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_GEN_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_GEN_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_GEN_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_GEN_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_GEN_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_GEN_CONFIG__TYPE (REG_UDWORD)
+#define R_GEN_CONFIG__GET REG_GET_WO
+#define R_GEN_CONFIG__IGET REG_IGET_WO
+#define R_GEN_CONFIG__SET REG_SET_WO
+#define R_GEN_CONFIG__ISET REG_ISET_WO
+#define R_GEN_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_GEN_CONFIG__EQL REG_EQL_WO
+#define R_GEN_CONFIG__IEQL REG_IEQL_WO
+#define R_GEN_CONFIG__RD REG_RD_WO
+#define R_GEN_CONFIG__IRD REG_IRD_WO
+#define R_GEN_CONFIG__WR REG_WR_WO
+#define R_GEN_CONFIG__IWR REG_IWR_WO
+
+#define R_GEN_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_GEN_CONFIG__par_w__par_w__MASK 0x80000000U
+#define R_GEN_CONFIG__usb2__usb2__MASK 0x40000000U
+#define R_GEN_CONFIG__usb1__usb1__MASK 0x20000000U
+#define R_GEN_CONFIG__g24dir__g24dir__MASK 0x08000000U
+#define R_GEN_CONFIG__g16_23dir__g16_23dir__MASK 0x04000000U
+#define R_GEN_CONFIG__g16_20dir__g16_20dir__MASK 0x04000000U
+#define R_GEN_CONFIG__g16_23dir__g16_20dir__MASK 0x04000000U
+#define R_GEN_CONFIG__g8_15dir__g8_15dir__MASK 0x02000000U
+#define R_GEN_CONFIG__g0dir__g0dir__MASK 0x01000000U
+#define R_GEN_CONFIG__dma9__dma9__MASK 0x00800000U
+#define R_GEN_CONFIG__dma8__dma8__MASK 0x00400000U
+#define R_GEN_CONFIG__dma7__dma7__MASK 0x00300000U
+#define R_GEN_CONFIG__dma6__dma6__MASK 0x000c0000U
+#define R_GEN_CONFIG__dma5__dma5__MASK 0x00030000U
+#define R_GEN_CONFIG__dma4__dma4__MASK 0x0000c000U
+#define R_GEN_CONFIG__dma3__dma3__MASK 0x00003000U
+#define R_GEN_CONFIG__dma2__dma2__MASK 0x00000c00U
+#define R_GEN_CONFIG__mio_w__mio_w__MASK 0x00000200U
+#define R_GEN_CONFIG__ser3__ser3__MASK 0x00000100U
+#define R_GEN_CONFIG__par1__par1__MASK 0x00000080U
+#define R_GEN_CONFIG__scsi0w__scsi0w__MASK 0x00000040U
+#define R_GEN_CONFIG__scsi1__scsi1__MASK 0x00000020U
+#define R_GEN_CONFIG__mio__mio__MASK 0x00000010U
+#define R_GEN_CONFIG__ser2__ser2__MASK 0x00000008U
+#define R_GEN_CONFIG__par0__par0__MASK 0x00000004U
+#define R_GEN_CONFIG__ata__ata__MASK 0x00000002U
+#define R_GEN_CONFIG__scsi0__scsi0__MASK 0x00000001U
+
+#define R_GEN_CONFIG__par_w__MAX 0x1
+#define R_GEN_CONFIG__usb2__MAX 0x1
+#define R_GEN_CONFIG__usb1__MAX 0x1
+#define R_GEN_CONFIG__g24dir__MAX 0x1
+#define R_GEN_CONFIG__g16_23dir__MAX 0x1
+#define R_GEN_CONFIG__g16_20dir__MAX 0x1
+#define R_GEN_CONFIG__g8_15dir__MAX 0x1
+#define R_GEN_CONFIG__g0dir__MAX 0x1
+#define R_GEN_CONFIG__dma9__MAX 0x1
+#define R_GEN_CONFIG__dma8__MAX 0x1
+#define R_GEN_CONFIG__dma7__MAX 0x3
+#define R_GEN_CONFIG__dma6__MAX 0x3
+#define R_GEN_CONFIG__dma5__MAX 0x3
+#define R_GEN_CONFIG__dma4__MAX 0x3
+#define R_GEN_CONFIG__dma3__MAX 0x3
+#define R_GEN_CONFIG__dma2__MAX 0x3
+#define R_GEN_CONFIG__mio_w__MAX 0x1
+#define R_GEN_CONFIG__ser3__MAX 0x1
+#define R_GEN_CONFIG__par1__MAX 0x1
+#define R_GEN_CONFIG__scsi0w__MAX 0x1
+#define R_GEN_CONFIG__scsi1__MAX 0x1
+#define R_GEN_CONFIG__mio__MAX 0x1
+#define R_GEN_CONFIG__ser2__MAX 0x1
+#define R_GEN_CONFIG__par0__MAX 0x1
+#define R_GEN_CONFIG__ata__MAX 0x1
+#define R_GEN_CONFIG__scsi0__MAX 0x1
+
+#define R_GEN_CONFIG__par_w__MIN 0
+#define R_GEN_CONFIG__usb2__MIN 0
+#define R_GEN_CONFIG__usb1__MIN 0
+#define R_GEN_CONFIG__g24dir__MIN 0
+#define R_GEN_CONFIG__g16_23dir__MIN 0
+#define R_GEN_CONFIG__g16_20dir__MIN 0
+#define R_GEN_CONFIG__g8_15dir__MIN 0
+#define R_GEN_CONFIG__g0dir__MIN 0
+#define R_GEN_CONFIG__dma9__MIN 0
+#define R_GEN_CONFIG__dma8__MIN 0
+#define R_GEN_CONFIG__dma7__MIN 0
+#define R_GEN_CONFIG__dma6__MIN 0
+#define R_GEN_CONFIG__dma5__MIN 0
+#define R_GEN_CONFIG__dma4__MIN 0
+#define R_GEN_CONFIG__dma3__MIN 0
+#define R_GEN_CONFIG__dma2__MIN 0
+#define R_GEN_CONFIG__mio_w__MIN 0
+#define R_GEN_CONFIG__ser3__MIN 0
+#define R_GEN_CONFIG__par1__MIN 0
+#define R_GEN_CONFIG__scsi0w__MIN 0
+#define R_GEN_CONFIG__scsi1__MIN 0
+#define R_GEN_CONFIG__mio__MIN 0
+#define R_GEN_CONFIG__ser2__MIN 0
+#define R_GEN_CONFIG__par0__MIN 0
+#define R_GEN_CONFIG__ata__MIN 0
+#define R_GEN_CONFIG__scsi0__MIN 0
+
+#define R_GEN_CONFIG__par_w__BITNR 31
+#define R_GEN_CONFIG__usb2__BITNR 30
+#define R_GEN_CONFIG__usb1__BITNR 29
+#define R_GEN_CONFIG__g24dir__BITNR 27
+#define R_GEN_CONFIG__g16_23dir__BITNR 26
+#define R_GEN_CONFIG__g16_20dir__BITNR 26
+#define R_GEN_CONFIG__g8_15dir__BITNR 25
+#define R_GEN_CONFIG__g0dir__BITNR 24
+#define R_GEN_CONFIG__dma9__BITNR 23
+#define R_GEN_CONFIG__dma8__BITNR 22
+#define R_GEN_CONFIG__dma7__BITNR 20
+#define R_GEN_CONFIG__dma6__BITNR 18
+#define R_GEN_CONFIG__dma5__BITNR 16
+#define R_GEN_CONFIG__dma4__BITNR 14
+#define R_GEN_CONFIG__dma3__BITNR 12
+#define R_GEN_CONFIG__dma2__BITNR 10
+#define R_GEN_CONFIG__mio_w__BITNR 9
+#define R_GEN_CONFIG__ser3__BITNR 8
+#define R_GEN_CONFIG__par1__BITNR 7
+#define R_GEN_CONFIG__scsi0w__BITNR 6
+#define R_GEN_CONFIG__scsi1__BITNR 5
+#define R_GEN_CONFIG__mio__BITNR 4
+#define R_GEN_CONFIG__ser2__BITNR 3
+#define R_GEN_CONFIG__par0__BITNR 2
+#define R_GEN_CONFIG__ata__BITNR 1
+#define R_GEN_CONFIG__scsi0__BITNR 0
+
+#define R_GEN_CONFIG__par_w__par_w__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__usb2__usb2__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__usb1__usb1__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__g24dir__g24dir__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__g16_23dir__g16_23dir__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__g16_20dir__g16_20dir__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__g16_23dir__g16_20dir__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__g8_15dir__g8_15dir__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__g0dir__g0dir__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__dma9__dma9__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__dma8__dma8__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__dma7__dma7__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__dma6__dma6__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__dma5__dma5__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__dma4__dma4__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__dma3__dma3__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__dma2__dma2__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__mio_w__mio_w__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__ser3__ser3__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__par1__par1__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__scsi0w__scsi0w__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__mio__mio__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__ser2__ser2__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__par0__par0__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__ata__ata__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG__scsi0__scsi0__VAL REG_VAL_ENUM
+
+#define R_GEN_CONFIG__par_w__par_w__disable 0
+#define R_GEN_CONFIG__par_w__par_w__select 1
+#define R_GEN_CONFIG__usb2__usb2__disable 0
+#define R_GEN_CONFIG__usb2__usb2__select 1
+#define R_GEN_CONFIG__usb1__usb1__disable 0
+#define R_GEN_CONFIG__usb1__usb1__select 1
+#define R_GEN_CONFIG__g24dir__g24dir__in 0
+#define R_GEN_CONFIG__g24dir__g24dir__out 1
+#define R_GEN_CONFIG__g16_23dir__g16_23dir__in 0
+#define R_GEN_CONFIG__g16_23dir__g16_23dir__out 1
+#define R_GEN_CONFIG__g16_20dir__g16_20dir__in 0
+#define R_GEN_CONFIG__g16_20dir__g16_20dir__out 1
+#define R_GEN_CONFIG__g8_15dir__g8_15dir__in 0
+#define R_GEN_CONFIG__g8_15dir__g8_15dir__out 1
+#define R_GEN_CONFIG__g0dir__g0dir__in 0
+#define R_GEN_CONFIG__g0dir__g0dir__out 1
+#define R_GEN_CONFIG__dma9__dma9__serial1 1
+#define R_GEN_CONFIG__dma9__dma9__usb 0
+#define R_GEN_CONFIG__dma8__dma8__serial1 1
+#define R_GEN_CONFIG__dma8__dma8__usb 0
+#define R_GEN_CONFIG__dma7__dma7__extdma1 2
+#define R_GEN_CONFIG__dma7__dma7__intdma6 3
+#define R_GEN_CONFIG__dma7__dma7__serial0 1
+#define R_GEN_CONFIG__dma7__dma7__unused 0
+#define R_GEN_CONFIG__dma6__dma6__extdma1 2
+#define R_GEN_CONFIG__dma6__dma6__intdma7 3
+#define R_GEN_CONFIG__dma6__dma6__serial0 1
+#define R_GEN_CONFIG__dma6__dma6__unused 0
+#define R_GEN_CONFIG__dma5__dma5__extdma0 3
+#define R_GEN_CONFIG__dma5__dma5__par1 0
+#define R_GEN_CONFIG__dma5__dma5__scsi1 1
+#define R_GEN_CONFIG__dma5__dma5__serial3 2
+#define R_GEN_CONFIG__dma4__dma4__extdma0 3
+#define R_GEN_CONFIG__dma4__dma4__par1 0
+#define R_GEN_CONFIG__dma4__dma4__scsi1 1
+#define R_GEN_CONFIG__dma4__dma4__serial3 2
+#define R_GEN_CONFIG__dma3__dma3__ata 3
+#define R_GEN_CONFIG__dma3__dma3__par0 0
+#define R_GEN_CONFIG__dma3__dma3__scsi0 1
+#define R_GEN_CONFIG__dma3__dma3__serial2 2
+#define R_GEN_CONFIG__dma2__dma2__ata 3
+#define R_GEN_CONFIG__dma2__dma2__par0 0
+#define R_GEN_CONFIG__dma2__dma2__scsi0 1
+#define R_GEN_CONFIG__dma2__dma2__serial2 2
+#define R_GEN_CONFIG__mio_w__mio_w__disable 0
+#define R_GEN_CONFIG__mio_w__mio_w__select 1
+#define R_GEN_CONFIG__ser3__ser3__disable 0
+#define R_GEN_CONFIG__ser3__ser3__select 1
+#define R_GEN_CONFIG__par1__par1__disable 0
+#define R_GEN_CONFIG__par1__par1__select 1
+#define R_GEN_CONFIG__scsi0w__scsi0w__disable 0
+#define R_GEN_CONFIG__scsi0w__scsi0w__select 1
+#define R_GEN_CONFIG__scsi1__scsi1__disable 0
+#define R_GEN_CONFIG__scsi1__scsi1__select 1
+#define R_GEN_CONFIG__mio__mio__disable 0
+#define R_GEN_CONFIG__mio__mio__select 1
+#define R_GEN_CONFIG__ser2__ser2__disable 0
+#define R_GEN_CONFIG__ser2__ser2__select 1
+#define R_GEN_CONFIG__par0__par0__disable 0
+#define R_GEN_CONFIG__par0__par0__select 1
+#define R_GEN_CONFIG__ata__ata__disable 0
+#define R_GEN_CONFIG__ata__ata__select 1
+#define R_GEN_CONFIG__scsi0__scsi0__disable 0
+#define R_GEN_CONFIG__scsi0__scsi0__select 1
+
+#endif
+
+/*
+ * R_GEN_CONFIG_II
+ * - type: WO
+ * - addr: 0xb0000034
+ * - group: General config registers
+ */
+
+#if USE_GROUP__General_config_registers
+
+#define R_GEN_CONFIG_II__ADDR (REG_TYPECAST_UDWORD 0xb0000034)
+
+#ifndef REG_NO_SHADOW
+#define R_GEN_CONFIG_II__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_GEN_CONFIG_II + 0))
+#define R_GEN_CONFIG_II__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_GEN_CONFIG_II + 0))
+#else /* REG_NO_SHADOW */
+#define R_GEN_CONFIG_II__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_GEN_CONFIG_II__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_GEN_CONFIG_II__STYPECAST REG_STYPECAST_UDWORD
+#define R_GEN_CONFIG_II__SVAL REG_SVAL_SHADOW
+#define R_GEN_CONFIG_II__SVAL_I REG_SVAL_I_SHADOW
+#define R_GEN_CONFIG_II__TYPECAST REG_TYPECAST_UDWORD
+#define R_GEN_CONFIG_II__TYPE (REG_UDWORD)
+#define R_GEN_CONFIG_II__GET REG_GET_WO
+#define R_GEN_CONFIG_II__IGET REG_IGET_WO
+#define R_GEN_CONFIG_II__SET REG_SET_WO
+#define R_GEN_CONFIG_II__ISET REG_ISET_WO
+#define R_GEN_CONFIG_II__SET_VAL REG_SET_VAL_WO
+#define R_GEN_CONFIG_II__EQL REG_EQL_WO
+#define R_GEN_CONFIG_II__IEQL REG_IEQL_WO
+#define R_GEN_CONFIG_II__RD REG_RD_WO
+#define R_GEN_CONFIG_II__IRD REG_IRD_WO
+#define R_GEN_CONFIG_II__WR REG_WR_WO
+#define R_GEN_CONFIG_II__IWR REG_IWR_WO
+
+#define R_GEN_CONFIG_II__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_GEN_CONFIG_II__sermode3__sermode3__MASK 0x00000040U
+#define R_GEN_CONFIG_II__sermode1__sermode1__MASK 0x00000010U
+#define R_GEN_CONFIG_II__ext_clk__ext_clk__MASK 0x00000004U
+#define R_GEN_CONFIG_II__ser3__ser3__MASK 0x00000002U
+#define R_GEN_CONFIG_II__ser2__ser2__MASK 0x00000001U
+
+#define R_GEN_CONFIG_II__sermode3__MAX 0x1
+#define R_GEN_CONFIG_II__sermode1__MAX 0x1
+#define R_GEN_CONFIG_II__ext_clk__MAX 0x1
+#define R_GEN_CONFIG_II__ser3__MAX 0x1
+#define R_GEN_CONFIG_II__ser2__MAX 0x1
+
+#define R_GEN_CONFIG_II__sermode3__MIN 0
+#define R_GEN_CONFIG_II__sermode1__MIN 0
+#define R_GEN_CONFIG_II__ext_clk__MIN 0
+#define R_GEN_CONFIG_II__ser3__MIN 0
+#define R_GEN_CONFIG_II__ser2__MIN 0
+
+#define R_GEN_CONFIG_II__sermode3__BITNR 6
+#define R_GEN_CONFIG_II__sermode1__BITNR 4
+#define R_GEN_CONFIG_II__ext_clk__BITNR 2
+#define R_GEN_CONFIG_II__ser3__BITNR 1
+#define R_GEN_CONFIG_II__ser2__BITNR 0
+
+#define R_GEN_CONFIG_II__sermode3__sermode3__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG_II__sermode1__sermode1__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG_II__ext_clk__ext_clk__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG_II__ser3__ser3__VAL REG_VAL_ENUM
+#define R_GEN_CONFIG_II__ser2__ser2__VAL REG_VAL_ENUM
+
+#define R_GEN_CONFIG_II__sermode3__sermode3__async 0
+#define R_GEN_CONFIG_II__sermode3__sermode3__sync 1
+#define R_GEN_CONFIG_II__sermode1__sermode1__async 0
+#define R_GEN_CONFIG_II__sermode1__sermode1__sync 1
+#define R_GEN_CONFIG_II__ext_clk__ext_clk__disable 0
+#define R_GEN_CONFIG_II__ext_clk__ext_clk__select 1
+#define R_GEN_CONFIG_II__ser3__ser3__disable 0
+#define R_GEN_CONFIG_II__ser3__ser3__select 1
+#define R_GEN_CONFIG_II__ser2__ser2__disable 0
+#define R_GEN_CONFIG_II__ser2__ser2__select 1
+
+#endif
+
+/*
+ * R_IRQ_MASK0_CLR
+ * - type: WO
+ * - addr: 0xb00000c0
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK0_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000c0)
+
+#ifndef REG_NO_SHADOW
+#define R_IRQ_MASK0_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK0_CLR + 0))
+#define R_IRQ_MASK0_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK0_CLR + 0))
+#else /* REG_NO_SHADOW */
+#define R_IRQ_MASK0_CLR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_IRQ_MASK0_CLR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_IRQ_MASK0_CLR__STYPECAST REG_STYPECAST_UDWORD
+#define R_IRQ_MASK0_CLR__SVAL REG_SVAL_ZERO
+#define R_IRQ_MASK0_CLR__SVAL_I REG_SVAL_I_ZERO
+#define R_IRQ_MASK0_CLR__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK0_CLR__TYPE (REG_UDWORD)
+#define R_IRQ_MASK0_CLR__GET REG_GET_WO
+#define R_IRQ_MASK0_CLR__IGET REG_IGET_WO
+#define R_IRQ_MASK0_CLR__SET REG_SET_WO
+#define R_IRQ_MASK0_CLR__ISET REG_ISET_WO
+#define R_IRQ_MASK0_CLR__SET_VAL REG_SET_VAL_WO
+#define R_IRQ_MASK0_CLR__EQL REG_EQL_WO
+#define R_IRQ_MASK0_CLR__IEQL REG_IEQL_WO
+#define R_IRQ_MASK0_CLR__RD REG_RD_WO
+#define R_IRQ_MASK0_CLR__IRD REG_IRD_WO
+#define R_IRQ_MASK0_CLR__WR REG_WR_WO
+#define R_IRQ_MASK0_CLR__IWR REG_IWR_WO
+
+#define R_IRQ_MASK0_CLR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__MASK 0x80000000U
+#define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__MASK 0x40000000U
+#define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__MASK 0x20000000U
+#define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__MASK 0x10000000U
+#define R_IRQ_MASK0_CLR__deferred__deferred__MASK 0x08000000U
+#define R_IRQ_MASK0_CLR__late_col__late_col__MASK 0x04000000U
+#define R_IRQ_MASK0_CLR__multiple_col__multiple_col__MASK 0x02000000U
+#define R_IRQ_MASK0_CLR__single_col__single_col__MASK 0x01000000U
+#define R_IRQ_MASK0_CLR__congestion__congestion__MASK 0x00800000U
+#define R_IRQ_MASK0_CLR__oversize__oversize__MASK 0x00400000U
+#define R_IRQ_MASK0_CLR__alignment_error__alignment_error__MASK 0x00200000U
+#define R_IRQ_MASK0_CLR__crc_error__crc_error__MASK 0x00100000U
+#define R_IRQ_MASK0_CLR__overrun__overrun__MASK 0x00080000U
+#define R_IRQ_MASK0_CLR__underrun__underrun__MASK 0x00040000U
+#define R_IRQ_MASK0_CLR__excessive_col__excessive_col__MASK 0x00020000U
+#define R_IRQ_MASK0_CLR__mdio__mdio__MASK 0x00010000U
+#define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__MASK 0x00008000U
+#define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__MASK 0x00004000U
+#define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__MASK 0x00002000U
+#define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__MASK 0x00001000U
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U
+#define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__MASK 0x00000800U
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__ata_irq3__MASK 0x00000800U
+#define R_IRQ_MASK0_CLR__par0_peri__par0_peri__MASK 0x00000400U
+#define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__MASK 0x00000400U
+#define R_IRQ_MASK0_CLR__par0_peri__ata_irq2__MASK 0x00000400U
+#define R_IRQ_MASK0_CLR__par0_data__par0_data__MASK 0x00000200U
+#define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__MASK 0x00000200U
+#define R_IRQ_MASK0_CLR__par0_data__ata_irq1__MASK 0x00000200U
+#define R_IRQ_MASK0_CLR__par0_ready__par0_ready__MASK 0x00000100U
+#define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__MASK 0x00000100U
+#define R_IRQ_MASK0_CLR__par0_ready__ata_irq0__MASK 0x00000100U
+#define R_IRQ_MASK0_CLR__mio__mio__MASK 0x00000100U
+#define R_IRQ_MASK0_CLR__par0_ready__mio__MASK 0x00000100U
+#define R_IRQ_MASK0_CLR__scsi0__scsi0__MASK 0x00000100U
+#define R_IRQ_MASK0_CLR__par0_ready__scsi0__MASK 0x00000100U
+#define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__MASK 0x00000080U
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U
+#define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__MASK 0x00000008U
+#define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__MASK 0x00000004U
+#define R_IRQ_MASK0_CLR__timer1__timer1__MASK 0x00000002U
+#define R_IRQ_MASK0_CLR__timer0__timer0__MASK 0x00000001U
+
+#define R_IRQ_MASK0_CLR__nmi_pin__MAX 0x1
+#define R_IRQ_MASK0_CLR__watchdog_nmi__MAX 0x1
+#define R_IRQ_MASK0_CLR__sqe_test_error__MAX 0x1
+#define R_IRQ_MASK0_CLR__carrier_loss__MAX 0x1
+#define R_IRQ_MASK0_CLR__deferred__MAX 0x1
+#define R_IRQ_MASK0_CLR__late_col__MAX 0x1
+#define R_IRQ_MASK0_CLR__multiple_col__MAX 0x1
+#define R_IRQ_MASK0_CLR__single_col__MAX 0x1
+#define R_IRQ_MASK0_CLR__congestion__MAX 0x1
+#define R_IRQ_MASK0_CLR__oversize__MAX 0x1
+#define R_IRQ_MASK0_CLR__alignment_error__MAX 0x1
+#define R_IRQ_MASK0_CLR__crc_error__MAX 0x1
+#define R_IRQ_MASK0_CLR__overrun__MAX 0x1
+#define R_IRQ_MASK0_CLR__underrun__MAX 0x1
+#define R_IRQ_MASK0_CLR__excessive_col__MAX 0x1
+#define R_IRQ_MASK0_CLR__mdio__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_drq3__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_drq2__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_drq1__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_drq0__MAX 0x1
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_irq3__MAX 0x1
+#define R_IRQ_MASK0_CLR__par0_peri__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_irq2__MAX 0x1
+#define R_IRQ_MASK0_CLR__par0_data__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_irq1__MAX 0x1
+#define R_IRQ_MASK0_CLR__par0_ready__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_irq0__MAX 0x1
+#define R_IRQ_MASK0_CLR__mio__MAX 0x1
+#define R_IRQ_MASK0_CLR__scsi0__MAX 0x1
+#define R_IRQ_MASK0_CLR__ata_dmaend__MAX 0x1
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__MAX 0x1
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__MAX 0x1
+#define R_IRQ_MASK0_CLR__ext_dma1__MAX 0x1
+#define R_IRQ_MASK0_CLR__ext_dma0__MAX 0x1
+#define R_IRQ_MASK0_CLR__timer1__MAX 0x1
+#define R_IRQ_MASK0_CLR__timer0__MAX 0x1
+
+#define R_IRQ_MASK0_CLR__nmi_pin__MIN 0
+#define R_IRQ_MASK0_CLR__watchdog_nmi__MIN 0
+#define R_IRQ_MASK0_CLR__sqe_test_error__MIN 0
+#define R_IRQ_MASK0_CLR__carrier_loss__MIN 0
+#define R_IRQ_MASK0_CLR__deferred__MIN 0
+#define R_IRQ_MASK0_CLR__late_col__MIN 0
+#define R_IRQ_MASK0_CLR__multiple_col__MIN 0
+#define R_IRQ_MASK0_CLR__single_col__MIN 0
+#define R_IRQ_MASK0_CLR__congestion__MIN 0
+#define R_IRQ_MASK0_CLR__oversize__MIN 0
+#define R_IRQ_MASK0_CLR__alignment_error__MIN 0
+#define R_IRQ_MASK0_CLR__crc_error__MIN 0
+#define R_IRQ_MASK0_CLR__overrun__MIN 0
+#define R_IRQ_MASK0_CLR__underrun__MIN 0
+#define R_IRQ_MASK0_CLR__excessive_col__MIN 0
+#define R_IRQ_MASK0_CLR__mdio__MIN 0
+#define R_IRQ_MASK0_CLR__ata_drq3__MIN 0
+#define R_IRQ_MASK0_CLR__ata_drq2__MIN 0
+#define R_IRQ_MASK0_CLR__ata_drq1__MIN 0
+#define R_IRQ_MASK0_CLR__ata_drq0__MIN 0
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__MIN 0
+#define R_IRQ_MASK0_CLR__ata_irq3__MIN 0
+#define R_IRQ_MASK0_CLR__par0_peri__MIN 0
+#define R_IRQ_MASK0_CLR__ata_irq2__MIN 0
+#define R_IRQ_MASK0_CLR__par0_data__MIN 0
+#define R_IRQ_MASK0_CLR__ata_irq1__MIN 0
+#define R_IRQ_MASK0_CLR__par0_ready__MIN 0
+#define R_IRQ_MASK0_CLR__ata_irq0__MIN 0
+#define R_IRQ_MASK0_CLR__mio__MIN 0
+#define R_IRQ_MASK0_CLR__scsi0__MIN 0
+#define R_IRQ_MASK0_CLR__ata_dmaend__MIN 0
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__MIN 0
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__MIN 0
+#define R_IRQ_MASK0_CLR__ext_dma1__MIN 0
+#define R_IRQ_MASK0_CLR__ext_dma0__MIN 0
+#define R_IRQ_MASK0_CLR__timer1__MIN 0
+#define R_IRQ_MASK0_CLR__timer0__MIN 0
+
+#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31
+#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30
+#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29
+#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28
+#define R_IRQ_MASK0_CLR__deferred__BITNR 27
+#define R_IRQ_MASK0_CLR__late_col__BITNR 26
+#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25
+#define R_IRQ_MASK0_CLR__single_col__BITNR 24
+#define R_IRQ_MASK0_CLR__congestion__BITNR 23
+#define R_IRQ_MASK0_CLR__oversize__BITNR 22
+#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21
+#define R_IRQ_MASK0_CLR__crc_error__BITNR 20
+#define R_IRQ_MASK0_CLR__overrun__BITNR 19
+#define R_IRQ_MASK0_CLR__underrun__BITNR 18
+#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17
+#define R_IRQ_MASK0_CLR__mdio__BITNR 16
+#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15
+#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14
+#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13
+#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11
+#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11
+#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10
+#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10
+#define R_IRQ_MASK0_CLR__par0_data__BITNR 9
+#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9
+#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8
+#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8
+#define R_IRQ_MASK0_CLR__mio__BITNR 8
+#define R_IRQ_MASK0_CLR__scsi0__BITNR 8
+#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4
+#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3
+#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2
+#define R_IRQ_MASK0_CLR__timer1__BITNR 1
+#define R_IRQ_MASK0_CLR__timer0__BITNR 0
+
+#define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__deferred__deferred__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__late_col__late_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__multiple_col__multiple_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__single_col__single_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__congestion__congestion__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__oversize__oversize__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__alignment_error__alignment_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__crc_error__crc_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__overrun__overrun__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__underrun__underrun__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__excessive_col__excessive_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__mdio__mdio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_peri__par0_peri__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_peri__ata_irq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_data__par0_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_data__ata_irq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_ready__par0_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_ready__ata_irq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__mio__mio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_ready__mio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__par0_ready__scsi0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__timer1__timer1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_CLR__timer0__timer0__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__clr 1
+#define R_IRQ_MASK0_CLR__nmi_pin__nmi_pin__nop 0
+#define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__clr 1
+#define R_IRQ_MASK0_CLR__watchdog_nmi__watchdog_nmi__nop 0
+#define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__clr 1
+#define R_IRQ_MASK0_CLR__sqe_test_error__sqe_test_error__nop 0
+#define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__clr 1
+#define R_IRQ_MASK0_CLR__carrier_loss__carrier_loss__nop 0
+#define R_IRQ_MASK0_CLR__deferred__deferred__clr 1
+#define R_IRQ_MASK0_CLR__deferred__deferred__nop 0
+#define R_IRQ_MASK0_CLR__late_col__late_col__clr 1
+#define R_IRQ_MASK0_CLR__late_col__late_col__nop 0
+#define R_IRQ_MASK0_CLR__multiple_col__multiple_col__clr 1
+#define R_IRQ_MASK0_CLR__multiple_col__multiple_col__nop 0
+#define R_IRQ_MASK0_CLR__single_col__single_col__clr 1
+#define R_IRQ_MASK0_CLR__single_col__single_col__nop 0
+#define R_IRQ_MASK0_CLR__congestion__congestion__clr 1
+#define R_IRQ_MASK0_CLR__congestion__congestion__nop 0
+#define R_IRQ_MASK0_CLR__oversize__oversize__clr 1
+#define R_IRQ_MASK0_CLR__oversize__oversize__nop 0
+#define R_IRQ_MASK0_CLR__alignment_error__alignment_error__clr 1
+#define R_IRQ_MASK0_CLR__alignment_error__alignment_error__nop 0
+#define R_IRQ_MASK0_CLR__crc_error__crc_error__clr 1
+#define R_IRQ_MASK0_CLR__crc_error__crc_error__nop 0
+#define R_IRQ_MASK0_CLR__overrun__overrun__clr 1
+#define R_IRQ_MASK0_CLR__overrun__overrun__nop 0
+#define R_IRQ_MASK0_CLR__underrun__underrun__clr 1
+#define R_IRQ_MASK0_CLR__underrun__underrun__nop 0
+#define R_IRQ_MASK0_CLR__excessive_col__excessive_col__clr 1
+#define R_IRQ_MASK0_CLR__excessive_col__excessive_col__nop 0
+#define R_IRQ_MASK0_CLR__mdio__mdio__clr 1
+#define R_IRQ_MASK0_CLR__mdio__mdio__nop 0
+#define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__clr 1
+#define R_IRQ_MASK0_CLR__ata_drq3__ata_drq3__nop 0
+#define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__clr 1
+#define R_IRQ_MASK0_CLR__ata_drq2__ata_drq2__nop 0
+#define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__clr 1
+#define R_IRQ_MASK0_CLR__ata_drq1__ata_drq1__nop 0
+#define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__clr 1
+#define R_IRQ_MASK0_CLR__ata_drq0__ata_drq0__nop 0
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__clr 1
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__par0_ecp_cmd__nop 0
+#define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__clr 1
+#define R_IRQ_MASK0_CLR__ata_irq3__ata_irq3__nop 0
+#define R_IRQ_MASK0_CLR__par0_peri__par0_peri__clr 1
+#define R_IRQ_MASK0_CLR__par0_peri__par0_peri__nop 0
+#define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__clr 1
+#define R_IRQ_MASK0_CLR__ata_irq2__ata_irq2__nop 0
+#define R_IRQ_MASK0_CLR__par0_data__par0_data__clr 1
+#define R_IRQ_MASK0_CLR__par0_data__par0_data__nop 0
+#define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__clr 1
+#define R_IRQ_MASK0_CLR__ata_irq1__ata_irq1__nop 0
+#define R_IRQ_MASK0_CLR__par0_ready__par0_ready__clr 1
+#define R_IRQ_MASK0_CLR__par0_ready__par0_ready__nop 0
+#define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__clr 1
+#define R_IRQ_MASK0_CLR__ata_irq0__ata_irq0__nop 0
+#define R_IRQ_MASK0_CLR__mio__mio__clr 1
+#define R_IRQ_MASK0_CLR__mio__mio__nop 0
+#define R_IRQ_MASK0_CLR__scsi0__scsi0__clr 1
+#define R_IRQ_MASK0_CLR__scsi0__scsi0__nop 0
+#define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__clr 1
+#define R_IRQ_MASK0_CLR__ata_dmaend__ata_dmaend__nop 0
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__clr 1
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__irq_ext_vector_nr__nop 0
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__clr 1
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__irq_int_vector_nr__nop 0
+#define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__clr 1
+#define R_IRQ_MASK0_CLR__ext_dma1__ext_dma1__nop 0
+#define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__clr 1
+#define R_IRQ_MASK0_CLR__ext_dma0__ext_dma0__nop 0
+#define R_IRQ_MASK0_CLR__timer1__timer1__clr 1
+#define R_IRQ_MASK0_CLR__timer1__timer1__nop 0
+#define R_IRQ_MASK0_CLR__timer0__timer0__clr 1
+#define R_IRQ_MASK0_CLR__timer0__timer0__nop 0
+
+#endif
+
+/*
+ * R_IRQ_MASK0_RD
+ * - type: RO
+ * - addr: 0xb00000c0
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK0_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000c0)
+#define R_IRQ_MASK0_RD__SVAL REG_SVAL_SHADOW
+#define R_IRQ_MASK0_RD__SVAL_I REG_SVAL_I_SHADOW
+#define R_IRQ_MASK0_RD__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK0_RD__TYPE (REG_UDWORD)
+#define R_IRQ_MASK0_RD__GET REG_GET_RO
+#define R_IRQ_MASK0_RD__IGET REG_IGET_RO
+#define R_IRQ_MASK0_RD__SET REG_SET_RO
+#define R_IRQ_MASK0_RD__ISET REG_ISET_RO
+#define R_IRQ_MASK0_RD__SET_VAL REG_SET_VAL_RO
+#define R_IRQ_MASK0_RD__EQL REG_EQL_RO
+#define R_IRQ_MASK0_RD__IEQL REG_IEQL_RO
+#define R_IRQ_MASK0_RD__RD REG_RD_RO
+#define R_IRQ_MASK0_RD__IRD REG_IRD_RO
+#define R_IRQ_MASK0_RD__WR REG_WR_RO
+#define R_IRQ_MASK0_RD__IWR REG_IWR_RO
+
+#define R_IRQ_MASK0_RD__READ(addr) \
+ (*(addr))
+
+#define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__MASK 0x80000000U
+#define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__MASK 0x40000000U
+#define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__MASK 0x20000000U
+#define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__MASK 0x10000000U
+#define R_IRQ_MASK0_RD__deferred__deferred__MASK 0x08000000U
+#define R_IRQ_MASK0_RD__late_col__late_col__MASK 0x04000000U
+#define R_IRQ_MASK0_RD__multiple_col__multiple_col__MASK 0x02000000U
+#define R_IRQ_MASK0_RD__single_col__single_col__MASK 0x01000000U
+#define R_IRQ_MASK0_RD__congestion__congestion__MASK 0x00800000U
+#define R_IRQ_MASK0_RD__oversize__oversize__MASK 0x00400000U
+#define R_IRQ_MASK0_RD__alignment_error__alignment_error__MASK 0x00200000U
+#define R_IRQ_MASK0_RD__crc_error__crc_error__MASK 0x00100000U
+#define R_IRQ_MASK0_RD__overrun__overrun__MASK 0x00080000U
+#define R_IRQ_MASK0_RD__underrun__underrun__MASK 0x00040000U
+#define R_IRQ_MASK0_RD__excessive_col__excessive_col__MASK 0x00020000U
+#define R_IRQ_MASK0_RD__mdio__mdio__MASK 0x00010000U
+#define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__MASK 0x00008000U
+#define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__MASK 0x00004000U
+#define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__MASK 0x00002000U
+#define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__MASK 0x00001000U
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U
+#define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__MASK 0x00000800U
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__ata_irq3__MASK 0x00000800U
+#define R_IRQ_MASK0_RD__par0_peri__par0_peri__MASK 0x00000400U
+#define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__MASK 0x00000400U
+#define R_IRQ_MASK0_RD__par0_peri__ata_irq2__MASK 0x00000400U
+#define R_IRQ_MASK0_RD__par0_data__par0_data__MASK 0x00000200U
+#define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__MASK 0x00000200U
+#define R_IRQ_MASK0_RD__par0_data__ata_irq1__MASK 0x00000200U
+#define R_IRQ_MASK0_RD__par0_ready__par0_ready__MASK 0x00000100U
+#define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__MASK 0x00000100U
+#define R_IRQ_MASK0_RD__par0_ready__ata_irq0__MASK 0x00000100U
+#define R_IRQ_MASK0_RD__mio__mio__MASK 0x00000100U
+#define R_IRQ_MASK0_RD__par0_ready__mio__MASK 0x00000100U
+#define R_IRQ_MASK0_RD__scsi0__scsi0__MASK 0x00000100U
+#define R_IRQ_MASK0_RD__par0_ready__scsi0__MASK 0x00000100U
+#define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__MASK 0x00000080U
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U
+#define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__MASK 0x00000008U
+#define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__MASK 0x00000004U
+#define R_IRQ_MASK0_RD__timer1__timer1__MASK 0x00000002U
+#define R_IRQ_MASK0_RD__timer0__timer0__MASK 0x00000001U
+
+#define R_IRQ_MASK0_RD__nmi_pin__MAX 0x1
+#define R_IRQ_MASK0_RD__watchdog_nmi__MAX 0x1
+#define R_IRQ_MASK0_RD__sqe_test_error__MAX 0x1
+#define R_IRQ_MASK0_RD__carrier_loss__MAX 0x1
+#define R_IRQ_MASK0_RD__deferred__MAX 0x1
+#define R_IRQ_MASK0_RD__late_col__MAX 0x1
+#define R_IRQ_MASK0_RD__multiple_col__MAX 0x1
+#define R_IRQ_MASK0_RD__single_col__MAX 0x1
+#define R_IRQ_MASK0_RD__congestion__MAX 0x1
+#define R_IRQ_MASK0_RD__oversize__MAX 0x1
+#define R_IRQ_MASK0_RD__alignment_error__MAX 0x1
+#define R_IRQ_MASK0_RD__crc_error__MAX 0x1
+#define R_IRQ_MASK0_RD__overrun__MAX 0x1
+#define R_IRQ_MASK0_RD__underrun__MAX 0x1
+#define R_IRQ_MASK0_RD__excessive_col__MAX 0x1
+#define R_IRQ_MASK0_RD__mdio__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_drq3__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_drq2__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_drq1__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_drq0__MAX 0x1
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_irq3__MAX 0x1
+#define R_IRQ_MASK0_RD__par0_peri__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_irq2__MAX 0x1
+#define R_IRQ_MASK0_RD__par0_data__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_irq1__MAX 0x1
+#define R_IRQ_MASK0_RD__par0_ready__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_irq0__MAX 0x1
+#define R_IRQ_MASK0_RD__mio__MAX 0x1
+#define R_IRQ_MASK0_RD__scsi0__MAX 0x1
+#define R_IRQ_MASK0_RD__ata_dmaend__MAX 0x1
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__MAX 0x1
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__MAX 0x1
+#define R_IRQ_MASK0_RD__ext_dma1__MAX 0x1
+#define R_IRQ_MASK0_RD__ext_dma0__MAX 0x1
+#define R_IRQ_MASK0_RD__timer1__MAX 0x1
+#define R_IRQ_MASK0_RD__timer0__MAX 0x1
+
+#define R_IRQ_MASK0_RD__nmi_pin__MIN 0
+#define R_IRQ_MASK0_RD__watchdog_nmi__MIN 0
+#define R_IRQ_MASK0_RD__sqe_test_error__MIN 0
+#define R_IRQ_MASK0_RD__carrier_loss__MIN 0
+#define R_IRQ_MASK0_RD__deferred__MIN 0
+#define R_IRQ_MASK0_RD__late_col__MIN 0
+#define R_IRQ_MASK0_RD__multiple_col__MIN 0
+#define R_IRQ_MASK0_RD__single_col__MIN 0
+#define R_IRQ_MASK0_RD__congestion__MIN 0
+#define R_IRQ_MASK0_RD__oversize__MIN 0
+#define R_IRQ_MASK0_RD__alignment_error__MIN 0
+#define R_IRQ_MASK0_RD__crc_error__MIN 0
+#define R_IRQ_MASK0_RD__overrun__MIN 0
+#define R_IRQ_MASK0_RD__underrun__MIN 0
+#define R_IRQ_MASK0_RD__excessive_col__MIN 0
+#define R_IRQ_MASK0_RD__mdio__MIN 0
+#define R_IRQ_MASK0_RD__ata_drq3__MIN 0
+#define R_IRQ_MASK0_RD__ata_drq2__MIN 0
+#define R_IRQ_MASK0_RD__ata_drq1__MIN 0
+#define R_IRQ_MASK0_RD__ata_drq0__MIN 0
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__MIN 0
+#define R_IRQ_MASK0_RD__ata_irq3__MIN 0
+#define R_IRQ_MASK0_RD__par0_peri__MIN 0
+#define R_IRQ_MASK0_RD__ata_irq2__MIN 0
+#define R_IRQ_MASK0_RD__par0_data__MIN 0
+#define R_IRQ_MASK0_RD__ata_irq1__MIN 0
+#define R_IRQ_MASK0_RD__par0_ready__MIN 0
+#define R_IRQ_MASK0_RD__ata_irq0__MIN 0
+#define R_IRQ_MASK0_RD__mio__MIN 0
+#define R_IRQ_MASK0_RD__scsi0__MIN 0
+#define R_IRQ_MASK0_RD__ata_dmaend__MIN 0
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__MIN 0
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__MIN 0
+#define R_IRQ_MASK0_RD__ext_dma1__MIN 0
+#define R_IRQ_MASK0_RD__ext_dma0__MIN 0
+#define R_IRQ_MASK0_RD__timer1__MIN 0
+#define R_IRQ_MASK0_RD__timer0__MIN 0
+
+#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31
+#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30
+#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29
+#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28
+#define R_IRQ_MASK0_RD__deferred__BITNR 27
+#define R_IRQ_MASK0_RD__late_col__BITNR 26
+#define R_IRQ_MASK0_RD__multiple_col__BITNR 25
+#define R_IRQ_MASK0_RD__single_col__BITNR 24
+#define R_IRQ_MASK0_RD__congestion__BITNR 23
+#define R_IRQ_MASK0_RD__oversize__BITNR 22
+#define R_IRQ_MASK0_RD__alignment_error__BITNR 21
+#define R_IRQ_MASK0_RD__crc_error__BITNR 20
+#define R_IRQ_MASK0_RD__overrun__BITNR 19
+#define R_IRQ_MASK0_RD__underrun__BITNR 18
+#define R_IRQ_MASK0_RD__excessive_col__BITNR 17
+#define R_IRQ_MASK0_RD__mdio__BITNR 16
+#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15
+#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14
+#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13
+#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11
+#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11
+#define R_IRQ_MASK0_RD__par0_peri__BITNR 10
+#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10
+#define R_IRQ_MASK0_RD__par0_data__BITNR 9
+#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9
+#define R_IRQ_MASK0_RD__par0_ready__BITNR 8
+#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8
+#define R_IRQ_MASK0_RD__mio__BITNR 8
+#define R_IRQ_MASK0_RD__scsi0__BITNR 8
+#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4
+#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3
+#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2
+#define R_IRQ_MASK0_RD__timer1__BITNR 1
+#define R_IRQ_MASK0_RD__timer0__BITNR 0
+
+#define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__deferred__deferred__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__late_col__late_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__multiple_col__multiple_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__single_col__single_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__congestion__congestion__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__oversize__oversize__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__alignment_error__alignment_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__crc_error__crc_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__overrun__overrun__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__underrun__underrun__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__excessive_col__excessive_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__mdio__mdio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_peri__par0_peri__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_peri__ata_irq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_data__par0_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_data__ata_irq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_ready__par0_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_ready__ata_irq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__mio__mio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_ready__mio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__par0_ready__scsi0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__timer1__timer1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_RD__timer0__timer0__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__active 1
+#define R_IRQ_MASK0_RD__nmi_pin__nmi_pin__inactive 0
+#define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__active 1
+#define R_IRQ_MASK0_RD__watchdog_nmi__watchdog_nmi__inactive 0
+#define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__active 1
+#define R_IRQ_MASK0_RD__sqe_test_error__sqe_test_error__inactive 0
+#define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__active 1
+#define R_IRQ_MASK0_RD__carrier_loss__carrier_loss__inactive 0
+#define R_IRQ_MASK0_RD__deferred__deferred__active 1
+#define R_IRQ_MASK0_RD__deferred__deferred__inactive 0
+#define R_IRQ_MASK0_RD__late_col__late_col__active 1
+#define R_IRQ_MASK0_RD__late_col__late_col__inactive 0
+#define R_IRQ_MASK0_RD__multiple_col__multiple_col__active 1
+#define R_IRQ_MASK0_RD__multiple_col__multiple_col__inactive 0
+#define R_IRQ_MASK0_RD__single_col__single_col__active 1
+#define R_IRQ_MASK0_RD__single_col__single_col__inactive 0
+#define R_IRQ_MASK0_RD__congestion__congestion__active 1
+#define R_IRQ_MASK0_RD__congestion__congestion__inactive 0
+#define R_IRQ_MASK0_RD__oversize__oversize__active 1
+#define R_IRQ_MASK0_RD__oversize__oversize__inactive 0
+#define R_IRQ_MASK0_RD__alignment_error__alignment_error__active 1
+#define R_IRQ_MASK0_RD__alignment_error__alignment_error__inactive 0
+#define R_IRQ_MASK0_RD__crc_error__crc_error__active 1
+#define R_IRQ_MASK0_RD__crc_error__crc_error__inactive 0
+#define R_IRQ_MASK0_RD__overrun__overrun__active 1
+#define R_IRQ_MASK0_RD__overrun__overrun__inactive 0
+#define R_IRQ_MASK0_RD__underrun__underrun__active 1
+#define R_IRQ_MASK0_RD__underrun__underrun__inactive 0
+#define R_IRQ_MASK0_RD__excessive_col__excessive_col__active 1
+#define R_IRQ_MASK0_RD__excessive_col__excessive_col__inactive 0
+#define R_IRQ_MASK0_RD__mdio__mdio__active 1
+#define R_IRQ_MASK0_RD__mdio__mdio__inactive 0
+#define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__active 1
+#define R_IRQ_MASK0_RD__ata_drq3__ata_drq3__inactive 0
+#define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__active 1
+#define R_IRQ_MASK0_RD__ata_drq2__ata_drq2__inactive 0
+#define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__active 1
+#define R_IRQ_MASK0_RD__ata_drq1__ata_drq1__inactive 0
+#define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__active 1
+#define R_IRQ_MASK0_RD__ata_drq0__ata_drq0__inactive 0
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__active 1
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__par0_ecp_cmd__inactive 0
+#define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__active 1
+#define R_IRQ_MASK0_RD__ata_irq3__ata_irq3__inactive 0
+#define R_IRQ_MASK0_RD__par0_peri__par0_peri__active 1
+#define R_IRQ_MASK0_RD__par0_peri__par0_peri__inactive 0
+#define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__active 1
+#define R_IRQ_MASK0_RD__ata_irq2__ata_irq2__inactive 0
+#define R_IRQ_MASK0_RD__par0_data__par0_data__active 1
+#define R_IRQ_MASK0_RD__par0_data__par0_data__inactive 0
+#define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__active 1
+#define R_IRQ_MASK0_RD__ata_irq1__ata_irq1__inactive 0
+#define R_IRQ_MASK0_RD__par0_ready__par0_ready__active 1
+#define R_IRQ_MASK0_RD__par0_ready__par0_ready__inactive 0
+#define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__active 1
+#define R_IRQ_MASK0_RD__ata_irq0__ata_irq0__inactive 0
+#define R_IRQ_MASK0_RD__mio__mio__active 1
+#define R_IRQ_MASK0_RD__mio__mio__inactive 0
+#define R_IRQ_MASK0_RD__scsi0__scsi0__active 1
+#define R_IRQ_MASK0_RD__scsi0__scsi0__inactive 0
+#define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__active 1
+#define R_IRQ_MASK0_RD__ata_dmaend__ata_dmaend__inactive 0
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__active 1
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__irq_ext_vector_nr__inactive 0
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__active 1
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__irq_int_vector_nr__inactive 0
+#define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__active 1
+#define R_IRQ_MASK0_RD__ext_dma1__ext_dma1__inactive 0
+#define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__active 1
+#define R_IRQ_MASK0_RD__ext_dma0__ext_dma0__inactive 0
+#define R_IRQ_MASK0_RD__timer1__timer1__active 1
+#define R_IRQ_MASK0_RD__timer1__timer1__inactive 0
+#define R_IRQ_MASK0_RD__timer0__timer0__active 1
+#define R_IRQ_MASK0_RD__timer0__timer0__inactive 0
+
+#endif
+
+/*
+ * R_IRQ_MASK0_SET
+ * - type: WO
+ * - addr: 0xb00000c4
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK0_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000c4)
+
+#ifndef REG_NO_SHADOW
+#define R_IRQ_MASK0_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK0_SET + 0))
+#define R_IRQ_MASK0_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK0_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_IRQ_MASK0_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_IRQ_MASK0_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_IRQ_MASK0_SET__STYPECAST REG_STYPECAST_UDWORD
+#define R_IRQ_MASK0_SET__SVAL REG_SVAL_ZERO
+#define R_IRQ_MASK0_SET__SVAL_I REG_SVAL_I_ZERO
+#define R_IRQ_MASK0_SET__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK0_SET__TYPE (REG_UDWORD)
+#define R_IRQ_MASK0_SET__GET REG_GET_WO
+#define R_IRQ_MASK0_SET__IGET REG_IGET_WO
+#define R_IRQ_MASK0_SET__SET REG_SET_WO
+#define R_IRQ_MASK0_SET__ISET REG_ISET_WO
+#define R_IRQ_MASK0_SET__SET_VAL REG_SET_VAL_WO
+#define R_IRQ_MASK0_SET__EQL REG_EQL_WO
+#define R_IRQ_MASK0_SET__IEQL REG_IEQL_WO
+#define R_IRQ_MASK0_SET__RD REG_RD_WO
+#define R_IRQ_MASK0_SET__IRD REG_IRD_WO
+#define R_IRQ_MASK0_SET__WR REG_WR_WO
+#define R_IRQ_MASK0_SET__IWR REG_IWR_WO
+
+#define R_IRQ_MASK0_SET__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__MASK 0x80000000U
+#define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__MASK 0x40000000U
+#define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__MASK 0x20000000U
+#define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__MASK 0x10000000U
+#define R_IRQ_MASK0_SET__deferred__deferred__MASK 0x08000000U
+#define R_IRQ_MASK0_SET__late_col__late_col__MASK 0x04000000U
+#define R_IRQ_MASK0_SET__multiple_col__multiple_col__MASK 0x02000000U
+#define R_IRQ_MASK0_SET__single_col__single_col__MASK 0x01000000U
+#define R_IRQ_MASK0_SET__congestion__congestion__MASK 0x00800000U
+#define R_IRQ_MASK0_SET__oversize__oversize__MASK 0x00400000U
+#define R_IRQ_MASK0_SET__alignment_error__alignment_error__MASK 0x00200000U
+#define R_IRQ_MASK0_SET__crc_error__crc_error__MASK 0x00100000U
+#define R_IRQ_MASK0_SET__overrun__overrun__MASK 0x00080000U
+#define R_IRQ_MASK0_SET__underrun__underrun__MASK 0x00040000U
+#define R_IRQ_MASK0_SET__excessive_col__excessive_col__MASK 0x00020000U
+#define R_IRQ_MASK0_SET__mdio__mdio__MASK 0x00010000U
+#define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__MASK 0x00008000U
+#define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__MASK 0x00004000U
+#define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__MASK 0x00002000U
+#define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__MASK 0x00001000U
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U
+#define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__MASK 0x00000800U
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__ata_irq3__MASK 0x00000800U
+#define R_IRQ_MASK0_SET__par0_peri__par0_peri__MASK 0x00000400U
+#define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__MASK 0x00000400U
+#define R_IRQ_MASK0_SET__par0_peri__ata_irq2__MASK 0x00000400U
+#define R_IRQ_MASK0_SET__par0_data__par0_data__MASK 0x00000200U
+#define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__MASK 0x00000200U
+#define R_IRQ_MASK0_SET__par0_data__ata_irq1__MASK 0x00000200U
+#define R_IRQ_MASK0_SET__par0_ready__par0_ready__MASK 0x00000100U
+#define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__MASK 0x00000100U
+#define R_IRQ_MASK0_SET__par0_ready__ata_irq0__MASK 0x00000100U
+#define R_IRQ_MASK0_SET__mio__mio__MASK 0x00000100U
+#define R_IRQ_MASK0_SET__par0_ready__mio__MASK 0x00000100U
+#define R_IRQ_MASK0_SET__scsi0__scsi0__MASK 0x00000100U
+#define R_IRQ_MASK0_SET__par0_ready__scsi0__MASK 0x00000100U
+#define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__MASK 0x00000080U
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U
+#define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__MASK 0x00000008U
+#define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__MASK 0x00000004U
+#define R_IRQ_MASK0_SET__timer1__timer1__MASK 0x00000002U
+#define R_IRQ_MASK0_SET__timer0__timer0__MASK 0x00000001U
+
+#define R_IRQ_MASK0_SET__nmi_pin__MAX 0x1
+#define R_IRQ_MASK0_SET__watchdog_nmi__MAX 0x1
+#define R_IRQ_MASK0_SET__sqe_test_error__MAX 0x1
+#define R_IRQ_MASK0_SET__carrier_loss__MAX 0x1
+#define R_IRQ_MASK0_SET__deferred__MAX 0x1
+#define R_IRQ_MASK0_SET__late_col__MAX 0x1
+#define R_IRQ_MASK0_SET__multiple_col__MAX 0x1
+#define R_IRQ_MASK0_SET__single_col__MAX 0x1
+#define R_IRQ_MASK0_SET__congestion__MAX 0x1
+#define R_IRQ_MASK0_SET__oversize__MAX 0x1
+#define R_IRQ_MASK0_SET__alignment_error__MAX 0x1
+#define R_IRQ_MASK0_SET__crc_error__MAX 0x1
+#define R_IRQ_MASK0_SET__overrun__MAX 0x1
+#define R_IRQ_MASK0_SET__underrun__MAX 0x1
+#define R_IRQ_MASK0_SET__excessive_col__MAX 0x1
+#define R_IRQ_MASK0_SET__mdio__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_drq3__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_drq2__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_drq1__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_drq0__MAX 0x1
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_irq3__MAX 0x1
+#define R_IRQ_MASK0_SET__par0_peri__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_irq2__MAX 0x1
+#define R_IRQ_MASK0_SET__par0_data__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_irq1__MAX 0x1
+#define R_IRQ_MASK0_SET__par0_ready__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_irq0__MAX 0x1
+#define R_IRQ_MASK0_SET__mio__MAX 0x1
+#define R_IRQ_MASK0_SET__scsi0__MAX 0x1
+#define R_IRQ_MASK0_SET__ata_dmaend__MAX 0x1
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__MAX 0x1
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__MAX 0x1
+#define R_IRQ_MASK0_SET__ext_dma1__MAX 0x1
+#define R_IRQ_MASK0_SET__ext_dma0__MAX 0x1
+#define R_IRQ_MASK0_SET__timer1__MAX 0x1
+#define R_IRQ_MASK0_SET__timer0__MAX 0x1
+
+#define R_IRQ_MASK0_SET__nmi_pin__MIN 0
+#define R_IRQ_MASK0_SET__watchdog_nmi__MIN 0
+#define R_IRQ_MASK0_SET__sqe_test_error__MIN 0
+#define R_IRQ_MASK0_SET__carrier_loss__MIN 0
+#define R_IRQ_MASK0_SET__deferred__MIN 0
+#define R_IRQ_MASK0_SET__late_col__MIN 0
+#define R_IRQ_MASK0_SET__multiple_col__MIN 0
+#define R_IRQ_MASK0_SET__single_col__MIN 0
+#define R_IRQ_MASK0_SET__congestion__MIN 0
+#define R_IRQ_MASK0_SET__oversize__MIN 0
+#define R_IRQ_MASK0_SET__alignment_error__MIN 0
+#define R_IRQ_MASK0_SET__crc_error__MIN 0
+#define R_IRQ_MASK0_SET__overrun__MIN 0
+#define R_IRQ_MASK0_SET__underrun__MIN 0
+#define R_IRQ_MASK0_SET__excessive_col__MIN 0
+#define R_IRQ_MASK0_SET__mdio__MIN 0
+#define R_IRQ_MASK0_SET__ata_drq3__MIN 0
+#define R_IRQ_MASK0_SET__ata_drq2__MIN 0
+#define R_IRQ_MASK0_SET__ata_drq1__MIN 0
+#define R_IRQ_MASK0_SET__ata_drq0__MIN 0
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__MIN 0
+#define R_IRQ_MASK0_SET__ata_irq3__MIN 0
+#define R_IRQ_MASK0_SET__par0_peri__MIN 0
+#define R_IRQ_MASK0_SET__ata_irq2__MIN 0
+#define R_IRQ_MASK0_SET__par0_data__MIN 0
+#define R_IRQ_MASK0_SET__ata_irq1__MIN 0
+#define R_IRQ_MASK0_SET__par0_ready__MIN 0
+#define R_IRQ_MASK0_SET__ata_irq0__MIN 0
+#define R_IRQ_MASK0_SET__mio__MIN 0
+#define R_IRQ_MASK0_SET__scsi0__MIN 0
+#define R_IRQ_MASK0_SET__ata_dmaend__MIN 0
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__MIN 0
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__MIN 0
+#define R_IRQ_MASK0_SET__ext_dma1__MIN 0
+#define R_IRQ_MASK0_SET__ext_dma0__MIN 0
+#define R_IRQ_MASK0_SET__timer1__MIN 0
+#define R_IRQ_MASK0_SET__timer0__MIN 0
+
+#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31
+#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30
+#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29
+#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28
+#define R_IRQ_MASK0_SET__deferred__BITNR 27
+#define R_IRQ_MASK0_SET__late_col__BITNR 26
+#define R_IRQ_MASK0_SET__multiple_col__BITNR 25
+#define R_IRQ_MASK0_SET__single_col__BITNR 24
+#define R_IRQ_MASK0_SET__congestion__BITNR 23
+#define R_IRQ_MASK0_SET__oversize__BITNR 22
+#define R_IRQ_MASK0_SET__alignment_error__BITNR 21
+#define R_IRQ_MASK0_SET__crc_error__BITNR 20
+#define R_IRQ_MASK0_SET__overrun__BITNR 19
+#define R_IRQ_MASK0_SET__underrun__BITNR 18
+#define R_IRQ_MASK0_SET__excessive_col__BITNR 17
+#define R_IRQ_MASK0_SET__mdio__BITNR 16
+#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15
+#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14
+#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13
+#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11
+#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11
+#define R_IRQ_MASK0_SET__par0_peri__BITNR 10
+#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10
+#define R_IRQ_MASK0_SET__par0_data__BITNR 9
+#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9
+#define R_IRQ_MASK0_SET__par0_ready__BITNR 8
+#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8
+#define R_IRQ_MASK0_SET__mio__BITNR 8
+#define R_IRQ_MASK0_SET__scsi0__BITNR 8
+#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4
+#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3
+#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2
+#define R_IRQ_MASK0_SET__timer1__BITNR 1
+#define R_IRQ_MASK0_SET__timer0__BITNR 0
+
+#define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__deferred__deferred__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__late_col__late_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__multiple_col__multiple_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__single_col__single_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__congestion__congestion__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__oversize__oversize__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__alignment_error__alignment_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__crc_error__crc_error__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__overrun__overrun__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__underrun__underrun__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__excessive_col__excessive_col__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__mdio__mdio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_peri__par0_peri__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_peri__ata_irq2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_data__par0_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_data__ata_irq1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_ready__par0_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_ready__ata_irq0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__mio__mio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_ready__mio__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__par0_ready__scsi0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__timer1__timer1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK0_SET__timer0__timer0__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__nop 0
+#define R_IRQ_MASK0_SET__nmi_pin__nmi_pin__set 1
+#define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__nop 0
+#define R_IRQ_MASK0_SET__watchdog_nmi__watchdog_nmi__set 1
+#define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__nop 0
+#define R_IRQ_MASK0_SET__sqe_test_error__sqe_test_error__set 1
+#define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__nop 0
+#define R_IRQ_MASK0_SET__carrier_loss__carrier_loss__set 1
+#define R_IRQ_MASK0_SET__deferred__deferred__nop 0
+#define R_IRQ_MASK0_SET__deferred__deferred__set 1
+#define R_IRQ_MASK0_SET__late_col__late_col__nop 0
+#define R_IRQ_MASK0_SET__late_col__late_col__set 1
+#define R_IRQ_MASK0_SET__multiple_col__multiple_col__nop 0
+#define R_IRQ_MASK0_SET__multiple_col__multiple_col__set 1
+#define R_IRQ_MASK0_SET__single_col__single_col__nop 0
+#define R_IRQ_MASK0_SET__single_col__single_col__set 1
+#define R_IRQ_MASK0_SET__congestion__congestion__nop 0
+#define R_IRQ_MASK0_SET__congestion__congestion__set 1
+#define R_IRQ_MASK0_SET__oversize__oversize__nop 0
+#define R_IRQ_MASK0_SET__oversize__oversize__set 1
+#define R_IRQ_MASK0_SET__alignment_error__alignment_error__nop 0
+#define R_IRQ_MASK0_SET__alignment_error__alignment_error__set 1
+#define R_IRQ_MASK0_SET__crc_error__crc_error__nop 0
+#define R_IRQ_MASK0_SET__crc_error__crc_error__set 1
+#define R_IRQ_MASK0_SET__overrun__overrun__nop 0
+#define R_IRQ_MASK0_SET__overrun__overrun__set 1
+#define R_IRQ_MASK0_SET__underrun__underrun__nop 0
+#define R_IRQ_MASK0_SET__underrun__underrun__set 1
+#define R_IRQ_MASK0_SET__excessive_col__excessive_col__nop 0
+#define R_IRQ_MASK0_SET__excessive_col__excessive_col__set 1
+#define R_IRQ_MASK0_SET__mdio__mdio__nop 0
+#define R_IRQ_MASK0_SET__mdio__mdio__set 1
+#define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__nop 0
+#define R_IRQ_MASK0_SET__ata_drq3__ata_drq3__set 1
+#define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__nop 0
+#define R_IRQ_MASK0_SET__ata_drq2__ata_drq2__set 1
+#define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__nop 0
+#define R_IRQ_MASK0_SET__ata_drq1__ata_drq1__set 1
+#define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__nop 0
+#define R_IRQ_MASK0_SET__ata_drq0__ata_drq0__set 1
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__nop 0
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__par0_ecp_cmd__set 1
+#define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__nop 0
+#define R_IRQ_MASK0_SET__ata_irq3__ata_irq3__set 1
+#define R_IRQ_MASK0_SET__par0_peri__par0_peri__nop 0
+#define R_IRQ_MASK0_SET__par0_peri__par0_peri__set 1
+#define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__nop 0
+#define R_IRQ_MASK0_SET__ata_irq2__ata_irq2__set 1
+#define R_IRQ_MASK0_SET__par0_data__par0_data__nop 0
+#define R_IRQ_MASK0_SET__par0_data__par0_data__set 1
+#define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__nop 0
+#define R_IRQ_MASK0_SET__ata_irq1__ata_irq1__set 1
+#define R_IRQ_MASK0_SET__par0_ready__par0_ready__nop 0
+#define R_IRQ_MASK0_SET__par0_ready__par0_ready__set 1
+#define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__nop 0
+#define R_IRQ_MASK0_SET__ata_irq0__ata_irq0__set 1
+#define R_IRQ_MASK0_SET__mio__mio__nop 0
+#define R_IRQ_MASK0_SET__mio__mio__set 1
+#define R_IRQ_MASK0_SET__scsi0__scsi0__nop 0
+#define R_IRQ_MASK0_SET__scsi0__scsi0__set 1
+#define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__nop 0
+#define R_IRQ_MASK0_SET__ata_dmaend__ata_dmaend__set 1
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__nop 0
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__irq_ext_vector_nr__set 1
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__nop 0
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__irq_int_vector_nr__set 1
+#define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__nop 0
+#define R_IRQ_MASK0_SET__ext_dma1__ext_dma1__set 1
+#define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__nop 0
+#define R_IRQ_MASK0_SET__ext_dma0__ext_dma0__set 1
+#define R_IRQ_MASK0_SET__timer1__timer1__nop 0
+#define R_IRQ_MASK0_SET__timer1__timer1__set 1
+#define R_IRQ_MASK0_SET__timer0__timer0__nop 0
+#define R_IRQ_MASK0_SET__timer0__timer0__set 1
+
+#endif
+
+/*
+ * R_IRQ_MASK1_CLR
+ * - type: WO
+ * - addr: 0xb00000c8
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK1_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000c8)
+
+#ifndef REG_NO_SHADOW
+#define R_IRQ_MASK1_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK1_CLR + 0))
+#define R_IRQ_MASK1_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK1_CLR + 0))
+#else /* REG_NO_SHADOW */
+#define R_IRQ_MASK1_CLR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_IRQ_MASK1_CLR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_IRQ_MASK1_CLR__STYPECAST REG_STYPECAST_UDWORD
+#define R_IRQ_MASK1_CLR__SVAL REG_SVAL_ZERO
+#define R_IRQ_MASK1_CLR__SVAL_I REG_SVAL_I_ZERO
+#define R_IRQ_MASK1_CLR__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK1_CLR__TYPE (REG_UDWORD)
+#define R_IRQ_MASK1_CLR__GET REG_GET_WO
+#define R_IRQ_MASK1_CLR__IGET REG_IGET_WO
+#define R_IRQ_MASK1_CLR__SET REG_SET_WO
+#define R_IRQ_MASK1_CLR__ISET REG_ISET_WO
+#define R_IRQ_MASK1_CLR__SET_VAL REG_SET_VAL_WO
+#define R_IRQ_MASK1_CLR__EQL REG_EQL_WO
+#define R_IRQ_MASK1_CLR__IEQL REG_IEQL_WO
+#define R_IRQ_MASK1_CLR__RD REG_RD_WO
+#define R_IRQ_MASK1_CLR__IRD REG_IRD_WO
+#define R_IRQ_MASK1_CLR__WR REG_WR_WO
+#define R_IRQ_MASK1_CLR__IWR REG_IWR_WO
+
+#define R_IRQ_MASK1_CLR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_IRQ_MASK1_CLR__sw_int7__sw_int7__MASK 0x80000000U
+#define R_IRQ_MASK1_CLR__sw_int6__sw_int6__MASK 0x40000000U
+#define R_IRQ_MASK1_CLR__sw_int5__sw_int5__MASK 0x20000000U
+#define R_IRQ_MASK1_CLR__sw_int4__sw_int4__MASK 0x10000000U
+#define R_IRQ_MASK1_CLR__sw_int3__sw_int3__MASK 0x08000000U
+#define R_IRQ_MASK1_CLR__sw_int2__sw_int2__MASK 0x04000000U
+#define R_IRQ_MASK1_CLR__sw_int1__sw_int1__MASK 0x02000000U
+#define R_IRQ_MASK1_CLR__sw_int0__sw_int0__MASK 0x01000000U
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U
+#define R_IRQ_MASK1_CLR__par1_peri__par1_peri__MASK 0x00040000U
+#define R_IRQ_MASK1_CLR__par1_data__par1_data__MASK 0x00020000U
+#define R_IRQ_MASK1_CLR__par1_ready__par1_ready__MASK 0x00010000U
+#define R_IRQ_MASK1_CLR__scsi1__scsi1__MASK 0x00010000U
+#define R_IRQ_MASK1_CLR__par1_ready__scsi1__MASK 0x00010000U
+#define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__MASK 0x00008000U
+#define R_IRQ_MASK1_CLR__ser3_data__ser3_data__MASK 0x00004000U
+#define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__MASK 0x00002000U
+#define R_IRQ_MASK1_CLR__ser2_data__ser2_data__MASK 0x00001000U
+#define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__MASK 0x00000800U
+#define R_IRQ_MASK1_CLR__ser1_data__ser1_data__MASK 0x00000400U
+#define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__MASK 0x00000200U
+#define R_IRQ_MASK1_CLR__ser0_data__ser0_data__MASK 0x00000100U
+#define R_IRQ_MASK1_CLR__pa7__pa7__MASK 0x00000080U
+#define R_IRQ_MASK1_CLR__pa6__pa6__MASK 0x00000040U
+#define R_IRQ_MASK1_CLR__pa5__pa5__MASK 0x00000020U
+#define R_IRQ_MASK1_CLR__pa4__pa4__MASK 0x00000010U
+#define R_IRQ_MASK1_CLR__pa3__pa3__MASK 0x00000008U
+#define R_IRQ_MASK1_CLR__pa2__pa2__MASK 0x00000004U
+#define R_IRQ_MASK1_CLR__pa1__pa1__MASK 0x00000002U
+#define R_IRQ_MASK1_CLR__pa0__pa0__MASK 0x00000001U
+
+#define R_IRQ_MASK1_CLR__sw_int7__MAX 0x1
+#define R_IRQ_MASK1_CLR__sw_int6__MAX 0x1
+#define R_IRQ_MASK1_CLR__sw_int5__MAX 0x1
+#define R_IRQ_MASK1_CLR__sw_int4__MAX 0x1
+#define R_IRQ_MASK1_CLR__sw_int3__MAX 0x1
+#define R_IRQ_MASK1_CLR__sw_int2__MAX 0x1
+#define R_IRQ_MASK1_CLR__sw_int1__MAX 0x1
+#define R_IRQ_MASK1_CLR__sw_int0__MAX 0x1
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__MAX 0x1
+#define R_IRQ_MASK1_CLR__par1_peri__MAX 0x1
+#define R_IRQ_MASK1_CLR__par1_data__MAX 0x1
+#define R_IRQ_MASK1_CLR__par1_ready__MAX 0x1
+#define R_IRQ_MASK1_CLR__scsi1__MAX 0x1
+#define R_IRQ_MASK1_CLR__ser3_ready__MAX 0x1
+#define R_IRQ_MASK1_CLR__ser3_data__MAX 0x1
+#define R_IRQ_MASK1_CLR__ser2_ready__MAX 0x1
+#define R_IRQ_MASK1_CLR__ser2_data__MAX 0x1
+#define R_IRQ_MASK1_CLR__ser1_ready__MAX 0x1
+#define R_IRQ_MASK1_CLR__ser1_data__MAX 0x1
+#define R_IRQ_MASK1_CLR__ser0_ready__MAX 0x1
+#define R_IRQ_MASK1_CLR__ser0_data__MAX 0x1
+#define R_IRQ_MASK1_CLR__pa7__MAX 0x1
+#define R_IRQ_MASK1_CLR__pa6__MAX 0x1
+#define R_IRQ_MASK1_CLR__pa5__MAX 0x1
+#define R_IRQ_MASK1_CLR__pa4__MAX 0x1
+#define R_IRQ_MASK1_CLR__pa3__MAX 0x1
+#define R_IRQ_MASK1_CLR__pa2__MAX 0x1
+#define R_IRQ_MASK1_CLR__pa1__MAX 0x1
+#define R_IRQ_MASK1_CLR__pa0__MAX 0x1
+
+#define R_IRQ_MASK1_CLR__sw_int7__MIN 0
+#define R_IRQ_MASK1_CLR__sw_int6__MIN 0
+#define R_IRQ_MASK1_CLR__sw_int5__MIN 0
+#define R_IRQ_MASK1_CLR__sw_int4__MIN 0
+#define R_IRQ_MASK1_CLR__sw_int3__MIN 0
+#define R_IRQ_MASK1_CLR__sw_int2__MIN 0
+#define R_IRQ_MASK1_CLR__sw_int1__MIN 0
+#define R_IRQ_MASK1_CLR__sw_int0__MIN 0
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__MIN 0
+#define R_IRQ_MASK1_CLR__par1_peri__MIN 0
+#define R_IRQ_MASK1_CLR__par1_data__MIN 0
+#define R_IRQ_MASK1_CLR__par1_ready__MIN 0
+#define R_IRQ_MASK1_CLR__scsi1__MIN 0
+#define R_IRQ_MASK1_CLR__ser3_ready__MIN 0
+#define R_IRQ_MASK1_CLR__ser3_data__MIN 0
+#define R_IRQ_MASK1_CLR__ser2_ready__MIN 0
+#define R_IRQ_MASK1_CLR__ser2_data__MIN 0
+#define R_IRQ_MASK1_CLR__ser1_ready__MIN 0
+#define R_IRQ_MASK1_CLR__ser1_data__MIN 0
+#define R_IRQ_MASK1_CLR__ser0_ready__MIN 0
+#define R_IRQ_MASK1_CLR__ser0_data__MIN 0
+#define R_IRQ_MASK1_CLR__pa7__MIN 0
+#define R_IRQ_MASK1_CLR__pa6__MIN 0
+#define R_IRQ_MASK1_CLR__pa5__MIN 0
+#define R_IRQ_MASK1_CLR__pa4__MIN 0
+#define R_IRQ_MASK1_CLR__pa3__MIN 0
+#define R_IRQ_MASK1_CLR__pa2__MIN 0
+#define R_IRQ_MASK1_CLR__pa1__MIN 0
+#define R_IRQ_MASK1_CLR__pa0__MIN 0
+
+#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31
+#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30
+#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29
+#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28
+#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27
+#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26
+#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25
+#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19
+#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18
+#define R_IRQ_MASK1_CLR__par1_data__BITNR 17
+#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16
+#define R_IRQ_MASK1_CLR__scsi1__BITNR 16
+#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15
+#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14
+#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13
+#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12
+#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11
+#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10
+#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9
+#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8
+#define R_IRQ_MASK1_CLR__pa7__BITNR 7
+#define R_IRQ_MASK1_CLR__pa6__BITNR 6
+#define R_IRQ_MASK1_CLR__pa5__BITNR 5
+#define R_IRQ_MASK1_CLR__pa4__BITNR 4
+#define R_IRQ_MASK1_CLR__pa3__BITNR 3
+#define R_IRQ_MASK1_CLR__pa2__BITNR 2
+#define R_IRQ_MASK1_CLR__pa1__BITNR 1
+#define R_IRQ_MASK1_CLR__pa0__BITNR 0
+
+#define R_IRQ_MASK1_CLR__sw_int7__sw_int7__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__sw_int6__sw_int6__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__sw_int5__sw_int5__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__sw_int4__sw_int4__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__sw_int3__sw_int3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__sw_int2__sw_int2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__sw_int1__sw_int1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__sw_int0__sw_int0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__par1_peri__par1_peri__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__par1_data__par1_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__par1_ready__par1_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__par1_ready__scsi1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__ser3_data__ser3_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__ser2_data__ser2_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__ser1_data__ser1_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__ser0_data__ser0_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__pa7__pa7__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__pa6__pa6__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__pa5__pa5__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__pa4__pa4__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__pa3__pa3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__pa2__pa2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__pa1__pa1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_CLR__pa0__pa0__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK1_CLR__sw_int7__sw_int7__clr 1
+#define R_IRQ_MASK1_CLR__sw_int7__sw_int7__nop 0
+#define R_IRQ_MASK1_CLR__sw_int6__sw_int6__clr 1
+#define R_IRQ_MASK1_CLR__sw_int6__sw_int6__nop 0
+#define R_IRQ_MASK1_CLR__sw_int5__sw_int5__clr 1
+#define R_IRQ_MASK1_CLR__sw_int5__sw_int5__nop 0
+#define R_IRQ_MASK1_CLR__sw_int4__sw_int4__clr 1
+#define R_IRQ_MASK1_CLR__sw_int4__sw_int4__nop 0
+#define R_IRQ_MASK1_CLR__sw_int3__sw_int3__clr 1
+#define R_IRQ_MASK1_CLR__sw_int3__sw_int3__nop 0
+#define R_IRQ_MASK1_CLR__sw_int2__sw_int2__clr 1
+#define R_IRQ_MASK1_CLR__sw_int2__sw_int2__nop 0
+#define R_IRQ_MASK1_CLR__sw_int1__sw_int1__clr 1
+#define R_IRQ_MASK1_CLR__sw_int1__sw_int1__nop 0
+#define R_IRQ_MASK1_CLR__sw_int0__sw_int0__clr 1
+#define R_IRQ_MASK1_CLR__sw_int0__sw_int0__nop 0
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__clr 1
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__par1_ecp_cmd__nop 0
+#define R_IRQ_MASK1_CLR__par1_peri__par1_peri__clr 1
+#define R_IRQ_MASK1_CLR__par1_peri__par1_peri__nop 0
+#define R_IRQ_MASK1_CLR__par1_data__par1_data__clr 1
+#define R_IRQ_MASK1_CLR__par1_data__par1_data__nop 0
+#define R_IRQ_MASK1_CLR__par1_ready__par1_ready__clr 1
+#define R_IRQ_MASK1_CLR__par1_ready__par1_ready__nop 0
+#define R_IRQ_MASK1_CLR__scsi1__scsi1__clr 1
+#define R_IRQ_MASK1_CLR__scsi1__scsi1__nop 0
+#define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__clr 1
+#define R_IRQ_MASK1_CLR__ser3_ready__ser3_ready__nop 0
+#define R_IRQ_MASK1_CLR__ser3_data__ser3_data__clr 1
+#define R_IRQ_MASK1_CLR__ser3_data__ser3_data__nop 0
+#define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__clr 1
+#define R_IRQ_MASK1_CLR__ser2_ready__ser2_ready__nop 0
+#define R_IRQ_MASK1_CLR__ser2_data__ser2_data__clr 1
+#define R_IRQ_MASK1_CLR__ser2_data__ser2_data__nop 0
+#define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__clr 1
+#define R_IRQ_MASK1_CLR__ser1_ready__ser1_ready__nop 0
+#define R_IRQ_MASK1_CLR__ser1_data__ser1_data__clr 1
+#define R_IRQ_MASK1_CLR__ser1_data__ser1_data__nop 0
+#define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__clr 1
+#define R_IRQ_MASK1_CLR__ser0_ready__ser0_ready__nop 0
+#define R_IRQ_MASK1_CLR__ser0_data__ser0_data__clr 1
+#define R_IRQ_MASK1_CLR__ser0_data__ser0_data__nop 0
+#define R_IRQ_MASK1_CLR__pa7__pa7__clr 1
+#define R_IRQ_MASK1_CLR__pa7__pa7__nop 0
+#define R_IRQ_MASK1_CLR__pa6__pa6__clr 1
+#define R_IRQ_MASK1_CLR__pa6__pa6__nop 0
+#define R_IRQ_MASK1_CLR__pa5__pa5__clr 1
+#define R_IRQ_MASK1_CLR__pa5__pa5__nop 0
+#define R_IRQ_MASK1_CLR__pa4__pa4__clr 1
+#define R_IRQ_MASK1_CLR__pa4__pa4__nop 0
+#define R_IRQ_MASK1_CLR__pa3__pa3__clr 1
+#define R_IRQ_MASK1_CLR__pa3__pa3__nop 0
+#define R_IRQ_MASK1_CLR__pa2__pa2__clr 1
+#define R_IRQ_MASK1_CLR__pa2__pa2__nop 0
+#define R_IRQ_MASK1_CLR__pa1__pa1__clr 1
+#define R_IRQ_MASK1_CLR__pa1__pa1__nop 0
+#define R_IRQ_MASK1_CLR__pa0__pa0__clr 1
+#define R_IRQ_MASK1_CLR__pa0__pa0__nop 0
+
+#endif
+
+/*
+ * R_IRQ_MASK1_RD
+ * - type: RO
+ * - addr: 0xb00000c8
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK1_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000c8)
+#define R_IRQ_MASK1_RD__SVAL REG_SVAL_SHADOW
+#define R_IRQ_MASK1_RD__SVAL_I REG_SVAL_I_SHADOW
+#define R_IRQ_MASK1_RD__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK1_RD__TYPE (REG_UDWORD)
+#define R_IRQ_MASK1_RD__GET REG_GET_RO
+#define R_IRQ_MASK1_RD__IGET REG_IGET_RO
+#define R_IRQ_MASK1_RD__SET REG_SET_RO
+#define R_IRQ_MASK1_RD__ISET REG_ISET_RO
+#define R_IRQ_MASK1_RD__SET_VAL REG_SET_VAL_RO
+#define R_IRQ_MASK1_RD__EQL REG_EQL_RO
+#define R_IRQ_MASK1_RD__IEQL REG_IEQL_RO
+#define R_IRQ_MASK1_RD__RD REG_RD_RO
+#define R_IRQ_MASK1_RD__IRD REG_IRD_RO
+#define R_IRQ_MASK1_RD__WR REG_WR_RO
+#define R_IRQ_MASK1_RD__IWR REG_IWR_RO
+
+#define R_IRQ_MASK1_RD__READ(addr) \
+ (*(addr))
+
+#define R_IRQ_MASK1_RD__sw_int7__sw_int7__MASK 0x80000000U
+#define R_IRQ_MASK1_RD__sw_int6__sw_int6__MASK 0x40000000U
+#define R_IRQ_MASK1_RD__sw_int5__sw_int5__MASK 0x20000000U
+#define R_IRQ_MASK1_RD__sw_int4__sw_int4__MASK 0x10000000U
+#define R_IRQ_MASK1_RD__sw_int3__sw_int3__MASK 0x08000000U
+#define R_IRQ_MASK1_RD__sw_int2__sw_int2__MASK 0x04000000U
+#define R_IRQ_MASK1_RD__sw_int1__sw_int1__MASK 0x02000000U
+#define R_IRQ_MASK1_RD__sw_int0__sw_int0__MASK 0x01000000U
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U
+#define R_IRQ_MASK1_RD__par1_peri__par1_peri__MASK 0x00040000U
+#define R_IRQ_MASK1_RD__par1_data__par1_data__MASK 0x00020000U
+#define R_IRQ_MASK1_RD__par1_ready__par1_ready__MASK 0x00010000U
+#define R_IRQ_MASK1_RD__scsi1__scsi1__MASK 0x00010000U
+#define R_IRQ_MASK1_RD__par1_ready__scsi1__MASK 0x00010000U
+#define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__MASK 0x00008000U
+#define R_IRQ_MASK1_RD__ser3_data__ser3_data__MASK 0x00004000U
+#define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__MASK 0x00002000U
+#define R_IRQ_MASK1_RD__ser2_data__ser2_data__MASK 0x00001000U
+#define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__MASK 0x00000800U
+#define R_IRQ_MASK1_RD__ser1_data__ser1_data__MASK 0x00000400U
+#define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__MASK 0x00000200U
+#define R_IRQ_MASK1_RD__ser0_data__ser0_data__MASK 0x00000100U
+#define R_IRQ_MASK1_RD__pa7__pa7__MASK 0x00000080U
+#define R_IRQ_MASK1_RD__pa6__pa6__MASK 0x00000040U
+#define R_IRQ_MASK1_RD__pa5__pa5__MASK 0x00000020U
+#define R_IRQ_MASK1_RD__pa4__pa4__MASK 0x00000010U
+#define R_IRQ_MASK1_RD__pa3__pa3__MASK 0x00000008U
+#define R_IRQ_MASK1_RD__pa2__pa2__MASK 0x00000004U
+#define R_IRQ_MASK1_RD__pa1__pa1__MASK 0x00000002U
+#define R_IRQ_MASK1_RD__pa0__pa0__MASK 0x00000001U
+
+#define R_IRQ_MASK1_RD__sw_int7__MAX 0x1
+#define R_IRQ_MASK1_RD__sw_int6__MAX 0x1
+#define R_IRQ_MASK1_RD__sw_int5__MAX 0x1
+#define R_IRQ_MASK1_RD__sw_int4__MAX 0x1
+#define R_IRQ_MASK1_RD__sw_int3__MAX 0x1
+#define R_IRQ_MASK1_RD__sw_int2__MAX 0x1
+#define R_IRQ_MASK1_RD__sw_int1__MAX 0x1
+#define R_IRQ_MASK1_RD__sw_int0__MAX 0x1
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__MAX 0x1
+#define R_IRQ_MASK1_RD__par1_peri__MAX 0x1
+#define R_IRQ_MASK1_RD__par1_data__MAX 0x1
+#define R_IRQ_MASK1_RD__par1_ready__MAX 0x1
+#define R_IRQ_MASK1_RD__scsi1__MAX 0x1
+#define R_IRQ_MASK1_RD__ser3_ready__MAX 0x1
+#define R_IRQ_MASK1_RD__ser3_data__MAX 0x1
+#define R_IRQ_MASK1_RD__ser2_ready__MAX 0x1
+#define R_IRQ_MASK1_RD__ser2_data__MAX 0x1
+#define R_IRQ_MASK1_RD__ser1_ready__MAX 0x1
+#define R_IRQ_MASK1_RD__ser1_data__MAX 0x1
+#define R_IRQ_MASK1_RD__ser0_ready__MAX 0x1
+#define R_IRQ_MASK1_RD__ser0_data__MAX 0x1
+#define R_IRQ_MASK1_RD__pa7__MAX 0x1
+#define R_IRQ_MASK1_RD__pa6__MAX 0x1
+#define R_IRQ_MASK1_RD__pa5__MAX 0x1
+#define R_IRQ_MASK1_RD__pa4__MAX 0x1
+#define R_IRQ_MASK1_RD__pa3__MAX 0x1
+#define R_IRQ_MASK1_RD__pa2__MAX 0x1
+#define R_IRQ_MASK1_RD__pa1__MAX 0x1
+#define R_IRQ_MASK1_RD__pa0__MAX 0x1
+
+#define R_IRQ_MASK1_RD__sw_int7__MIN 0
+#define R_IRQ_MASK1_RD__sw_int6__MIN 0
+#define R_IRQ_MASK1_RD__sw_int5__MIN 0
+#define R_IRQ_MASK1_RD__sw_int4__MIN 0
+#define R_IRQ_MASK1_RD__sw_int3__MIN 0
+#define R_IRQ_MASK1_RD__sw_int2__MIN 0
+#define R_IRQ_MASK1_RD__sw_int1__MIN 0
+#define R_IRQ_MASK1_RD__sw_int0__MIN 0
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__MIN 0
+#define R_IRQ_MASK1_RD__par1_peri__MIN 0
+#define R_IRQ_MASK1_RD__par1_data__MIN 0
+#define R_IRQ_MASK1_RD__par1_ready__MIN 0
+#define R_IRQ_MASK1_RD__scsi1__MIN 0
+#define R_IRQ_MASK1_RD__ser3_ready__MIN 0
+#define R_IRQ_MASK1_RD__ser3_data__MIN 0
+#define R_IRQ_MASK1_RD__ser2_ready__MIN 0
+#define R_IRQ_MASK1_RD__ser2_data__MIN 0
+#define R_IRQ_MASK1_RD__ser1_ready__MIN 0
+#define R_IRQ_MASK1_RD__ser1_data__MIN 0
+#define R_IRQ_MASK1_RD__ser0_ready__MIN 0
+#define R_IRQ_MASK1_RD__ser0_data__MIN 0
+#define R_IRQ_MASK1_RD__pa7__MIN 0
+#define R_IRQ_MASK1_RD__pa6__MIN 0
+#define R_IRQ_MASK1_RD__pa5__MIN 0
+#define R_IRQ_MASK1_RD__pa4__MIN 0
+#define R_IRQ_MASK1_RD__pa3__MIN 0
+#define R_IRQ_MASK1_RD__pa2__MIN 0
+#define R_IRQ_MASK1_RD__pa1__MIN 0
+#define R_IRQ_MASK1_RD__pa0__MIN 0
+
+#define R_IRQ_MASK1_RD__sw_int7__BITNR 31
+#define R_IRQ_MASK1_RD__sw_int6__BITNR 30
+#define R_IRQ_MASK1_RD__sw_int5__BITNR 29
+#define R_IRQ_MASK1_RD__sw_int4__BITNR 28
+#define R_IRQ_MASK1_RD__sw_int3__BITNR 27
+#define R_IRQ_MASK1_RD__sw_int2__BITNR 26
+#define R_IRQ_MASK1_RD__sw_int1__BITNR 25
+#define R_IRQ_MASK1_RD__sw_int0__BITNR 24
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19
+#define R_IRQ_MASK1_RD__par1_peri__BITNR 18
+#define R_IRQ_MASK1_RD__par1_data__BITNR 17
+#define R_IRQ_MASK1_RD__par1_ready__BITNR 16
+#define R_IRQ_MASK1_RD__scsi1__BITNR 16
+#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15
+#define R_IRQ_MASK1_RD__ser3_data__BITNR 14
+#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13
+#define R_IRQ_MASK1_RD__ser2_data__BITNR 12
+#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11
+#define R_IRQ_MASK1_RD__ser1_data__BITNR 10
+#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9
+#define R_IRQ_MASK1_RD__ser0_data__BITNR 8
+#define R_IRQ_MASK1_RD__pa7__BITNR 7
+#define R_IRQ_MASK1_RD__pa6__BITNR 6
+#define R_IRQ_MASK1_RD__pa5__BITNR 5
+#define R_IRQ_MASK1_RD__pa4__BITNR 4
+#define R_IRQ_MASK1_RD__pa3__BITNR 3
+#define R_IRQ_MASK1_RD__pa2__BITNR 2
+#define R_IRQ_MASK1_RD__pa1__BITNR 1
+#define R_IRQ_MASK1_RD__pa0__BITNR 0
+
+#define R_IRQ_MASK1_RD__sw_int7__sw_int7__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__sw_int6__sw_int6__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__sw_int5__sw_int5__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__sw_int4__sw_int4__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__sw_int3__sw_int3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__sw_int2__sw_int2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__sw_int1__sw_int1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__sw_int0__sw_int0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__par1_peri__par1_peri__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__par1_data__par1_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__par1_ready__par1_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__par1_ready__scsi1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__ser3_data__ser3_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__ser2_data__ser2_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__ser1_data__ser1_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__ser0_data__ser0_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__pa7__pa7__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__pa6__pa6__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__pa5__pa5__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__pa4__pa4__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__pa3__pa3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__pa2__pa2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__pa1__pa1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_RD__pa0__pa0__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK1_RD__sw_int7__sw_int7__active 1
+#define R_IRQ_MASK1_RD__sw_int7__sw_int7__inactive 0
+#define R_IRQ_MASK1_RD__sw_int6__sw_int6__active 1
+#define R_IRQ_MASK1_RD__sw_int6__sw_int6__inactive 0
+#define R_IRQ_MASK1_RD__sw_int5__sw_int5__active 1
+#define R_IRQ_MASK1_RD__sw_int5__sw_int5__inactive 0
+#define R_IRQ_MASK1_RD__sw_int4__sw_int4__active 1
+#define R_IRQ_MASK1_RD__sw_int4__sw_int4__inactive 0
+#define R_IRQ_MASK1_RD__sw_int3__sw_int3__active 1
+#define R_IRQ_MASK1_RD__sw_int3__sw_int3__inactive 0
+#define R_IRQ_MASK1_RD__sw_int2__sw_int2__active 1
+#define R_IRQ_MASK1_RD__sw_int2__sw_int2__inactive 0
+#define R_IRQ_MASK1_RD__sw_int1__sw_int1__active 1
+#define R_IRQ_MASK1_RD__sw_int1__sw_int1__inactive 0
+#define R_IRQ_MASK1_RD__sw_int0__sw_int0__active 1
+#define R_IRQ_MASK1_RD__sw_int0__sw_int0__inactive 0
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__active 1
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__par1_ecp_cmd__inactive 0
+#define R_IRQ_MASK1_RD__par1_peri__par1_peri__active 1
+#define R_IRQ_MASK1_RD__par1_peri__par1_peri__inactive 0
+#define R_IRQ_MASK1_RD__par1_data__par1_data__active 1
+#define R_IRQ_MASK1_RD__par1_data__par1_data__inactive 0
+#define R_IRQ_MASK1_RD__par1_ready__par1_ready__active 1
+#define R_IRQ_MASK1_RD__par1_ready__par1_ready__inactive 0
+#define R_IRQ_MASK1_RD__scsi1__scsi1__active 1
+#define R_IRQ_MASK1_RD__scsi1__scsi1__inactive 0
+#define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__active 1
+#define R_IRQ_MASK1_RD__ser3_ready__ser3_ready__inactive 0
+#define R_IRQ_MASK1_RD__ser3_data__ser3_data__active 1
+#define R_IRQ_MASK1_RD__ser3_data__ser3_data__inactive 0
+#define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__active 1
+#define R_IRQ_MASK1_RD__ser2_ready__ser2_ready__inactive 0
+#define R_IRQ_MASK1_RD__ser2_data__ser2_data__active 1
+#define R_IRQ_MASK1_RD__ser2_data__ser2_data__inactive 0
+#define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__active 1
+#define R_IRQ_MASK1_RD__ser1_ready__ser1_ready__inactive 0
+#define R_IRQ_MASK1_RD__ser1_data__ser1_data__active 1
+#define R_IRQ_MASK1_RD__ser1_data__ser1_data__inactive 0
+#define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__active 1
+#define R_IRQ_MASK1_RD__ser0_ready__ser0_ready__inactive 0
+#define R_IRQ_MASK1_RD__ser0_data__ser0_data__active 1
+#define R_IRQ_MASK1_RD__ser0_data__ser0_data__inactive 0
+#define R_IRQ_MASK1_RD__pa7__pa7__active 1
+#define R_IRQ_MASK1_RD__pa7__pa7__inactive 0
+#define R_IRQ_MASK1_RD__pa6__pa6__active 1
+#define R_IRQ_MASK1_RD__pa6__pa6__inactive 0
+#define R_IRQ_MASK1_RD__pa5__pa5__active 1
+#define R_IRQ_MASK1_RD__pa5__pa5__inactive 0
+#define R_IRQ_MASK1_RD__pa4__pa4__active 1
+#define R_IRQ_MASK1_RD__pa4__pa4__inactive 0
+#define R_IRQ_MASK1_RD__pa3__pa3__active 1
+#define R_IRQ_MASK1_RD__pa3__pa3__inactive 0
+#define R_IRQ_MASK1_RD__pa2__pa2__active 1
+#define R_IRQ_MASK1_RD__pa2__pa2__inactive 0
+#define R_IRQ_MASK1_RD__pa1__pa1__active 1
+#define R_IRQ_MASK1_RD__pa1__pa1__inactive 0
+#define R_IRQ_MASK1_RD__pa0__pa0__active 1
+#define R_IRQ_MASK1_RD__pa0__pa0__inactive 0
+
+#endif
+
+/*
+ * R_IRQ_MASK1_SET
+ * - type: WO
+ * - addr: 0xb00000cc
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK1_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000cc)
+
+#ifndef REG_NO_SHADOW
+#define R_IRQ_MASK1_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK1_SET + 0))
+#define R_IRQ_MASK1_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK1_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_IRQ_MASK1_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_IRQ_MASK1_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_IRQ_MASK1_SET__STYPECAST REG_STYPECAST_UDWORD
+#define R_IRQ_MASK1_SET__SVAL REG_SVAL_ZERO
+#define R_IRQ_MASK1_SET__SVAL_I REG_SVAL_I_ZERO
+#define R_IRQ_MASK1_SET__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK1_SET__TYPE (REG_UDWORD)
+#define R_IRQ_MASK1_SET__GET REG_GET_WO
+#define R_IRQ_MASK1_SET__IGET REG_IGET_WO
+#define R_IRQ_MASK1_SET__SET REG_SET_WO
+#define R_IRQ_MASK1_SET__ISET REG_ISET_WO
+#define R_IRQ_MASK1_SET__SET_VAL REG_SET_VAL_WO
+#define R_IRQ_MASK1_SET__EQL REG_EQL_WO
+#define R_IRQ_MASK1_SET__IEQL REG_IEQL_WO
+#define R_IRQ_MASK1_SET__RD REG_RD_WO
+#define R_IRQ_MASK1_SET__IRD REG_IRD_WO
+#define R_IRQ_MASK1_SET__WR REG_WR_WO
+#define R_IRQ_MASK1_SET__IWR REG_IWR_WO
+
+#define R_IRQ_MASK1_SET__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_IRQ_MASK1_SET__sw_int7__sw_int7__MASK 0x80000000U
+#define R_IRQ_MASK1_SET__sw_int6__sw_int6__MASK 0x40000000U
+#define R_IRQ_MASK1_SET__sw_int5__sw_int5__MASK 0x20000000U
+#define R_IRQ_MASK1_SET__sw_int4__sw_int4__MASK 0x10000000U
+#define R_IRQ_MASK1_SET__sw_int3__sw_int3__MASK 0x08000000U
+#define R_IRQ_MASK1_SET__sw_int2__sw_int2__MASK 0x04000000U
+#define R_IRQ_MASK1_SET__sw_int1__sw_int1__MASK 0x02000000U
+#define R_IRQ_MASK1_SET__sw_int0__sw_int0__MASK 0x01000000U
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U
+#define R_IRQ_MASK1_SET__par1_peri__par1_peri__MASK 0x00040000U
+#define R_IRQ_MASK1_SET__par1_data__par1_data__MASK 0x00020000U
+#define R_IRQ_MASK1_SET__par1_ready__par1_ready__MASK 0x00010000U
+#define R_IRQ_MASK1_SET__scsi1__scsi1__MASK 0x00010000U
+#define R_IRQ_MASK1_SET__par1_ready__scsi1__MASK 0x00010000U
+#define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__MASK 0x00008000U
+#define R_IRQ_MASK1_SET__ser3_data__ser3_data__MASK 0x00004000U
+#define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__MASK 0x00002000U
+#define R_IRQ_MASK1_SET__ser2_data__ser2_data__MASK 0x00001000U
+#define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__MASK 0x00000800U
+#define R_IRQ_MASK1_SET__ser1_data__ser1_data__MASK 0x00000400U
+#define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__MASK 0x00000200U
+#define R_IRQ_MASK1_SET__ser0_data__ser0_data__MASK 0x00000100U
+#define R_IRQ_MASK1_SET__pa7__pa7__MASK 0x00000080U
+#define R_IRQ_MASK1_SET__pa6__pa6__MASK 0x00000040U
+#define R_IRQ_MASK1_SET__pa5__pa5__MASK 0x00000020U
+#define R_IRQ_MASK1_SET__pa4__pa4__MASK 0x00000010U
+#define R_IRQ_MASK1_SET__pa3__pa3__MASK 0x00000008U
+#define R_IRQ_MASK1_SET__pa2__pa2__MASK 0x00000004U
+#define R_IRQ_MASK1_SET__pa1__pa1__MASK 0x00000002U
+#define R_IRQ_MASK1_SET__pa0__pa0__MASK 0x00000001U
+
+#define R_IRQ_MASK1_SET__sw_int7__MAX 0x1
+#define R_IRQ_MASK1_SET__sw_int6__MAX 0x1
+#define R_IRQ_MASK1_SET__sw_int5__MAX 0x1
+#define R_IRQ_MASK1_SET__sw_int4__MAX 0x1
+#define R_IRQ_MASK1_SET__sw_int3__MAX 0x1
+#define R_IRQ_MASK1_SET__sw_int2__MAX 0x1
+#define R_IRQ_MASK1_SET__sw_int1__MAX 0x1
+#define R_IRQ_MASK1_SET__sw_int0__MAX 0x1
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__MAX 0x1
+#define R_IRQ_MASK1_SET__par1_peri__MAX 0x1
+#define R_IRQ_MASK1_SET__par1_data__MAX 0x1
+#define R_IRQ_MASK1_SET__par1_ready__MAX 0x1
+#define R_IRQ_MASK1_SET__scsi1__MAX 0x1
+#define R_IRQ_MASK1_SET__ser3_ready__MAX 0x1
+#define R_IRQ_MASK1_SET__ser3_data__MAX 0x1
+#define R_IRQ_MASK1_SET__ser2_ready__MAX 0x1
+#define R_IRQ_MASK1_SET__ser2_data__MAX 0x1
+#define R_IRQ_MASK1_SET__ser1_ready__MAX 0x1
+#define R_IRQ_MASK1_SET__ser1_data__MAX 0x1
+#define R_IRQ_MASK1_SET__ser0_ready__MAX 0x1
+#define R_IRQ_MASK1_SET__ser0_data__MAX 0x1
+#define R_IRQ_MASK1_SET__pa7__MAX 0x1
+#define R_IRQ_MASK1_SET__pa6__MAX 0x1
+#define R_IRQ_MASK1_SET__pa5__MAX 0x1
+#define R_IRQ_MASK1_SET__pa4__MAX 0x1
+#define R_IRQ_MASK1_SET__pa3__MAX 0x1
+#define R_IRQ_MASK1_SET__pa2__MAX 0x1
+#define R_IRQ_MASK1_SET__pa1__MAX 0x1
+#define R_IRQ_MASK1_SET__pa0__MAX 0x1
+
+#define R_IRQ_MASK1_SET__sw_int7__MIN 0
+#define R_IRQ_MASK1_SET__sw_int6__MIN 0
+#define R_IRQ_MASK1_SET__sw_int5__MIN 0
+#define R_IRQ_MASK1_SET__sw_int4__MIN 0
+#define R_IRQ_MASK1_SET__sw_int3__MIN 0
+#define R_IRQ_MASK1_SET__sw_int2__MIN 0
+#define R_IRQ_MASK1_SET__sw_int1__MIN 0
+#define R_IRQ_MASK1_SET__sw_int0__MIN 0
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__MIN 0
+#define R_IRQ_MASK1_SET__par1_peri__MIN 0
+#define R_IRQ_MASK1_SET__par1_data__MIN 0
+#define R_IRQ_MASK1_SET__par1_ready__MIN 0
+#define R_IRQ_MASK1_SET__scsi1__MIN 0
+#define R_IRQ_MASK1_SET__ser3_ready__MIN 0
+#define R_IRQ_MASK1_SET__ser3_data__MIN 0
+#define R_IRQ_MASK1_SET__ser2_ready__MIN 0
+#define R_IRQ_MASK1_SET__ser2_data__MIN 0
+#define R_IRQ_MASK1_SET__ser1_ready__MIN 0
+#define R_IRQ_MASK1_SET__ser1_data__MIN 0
+#define R_IRQ_MASK1_SET__ser0_ready__MIN 0
+#define R_IRQ_MASK1_SET__ser0_data__MIN 0
+#define R_IRQ_MASK1_SET__pa7__MIN 0
+#define R_IRQ_MASK1_SET__pa6__MIN 0
+#define R_IRQ_MASK1_SET__pa5__MIN 0
+#define R_IRQ_MASK1_SET__pa4__MIN 0
+#define R_IRQ_MASK1_SET__pa3__MIN 0
+#define R_IRQ_MASK1_SET__pa2__MIN 0
+#define R_IRQ_MASK1_SET__pa1__MIN 0
+#define R_IRQ_MASK1_SET__pa0__MIN 0
+
+#define R_IRQ_MASK1_SET__sw_int7__BITNR 31
+#define R_IRQ_MASK1_SET__sw_int6__BITNR 30
+#define R_IRQ_MASK1_SET__sw_int5__BITNR 29
+#define R_IRQ_MASK1_SET__sw_int4__BITNR 28
+#define R_IRQ_MASK1_SET__sw_int3__BITNR 27
+#define R_IRQ_MASK1_SET__sw_int2__BITNR 26
+#define R_IRQ_MASK1_SET__sw_int1__BITNR 25
+#define R_IRQ_MASK1_SET__sw_int0__BITNR 24
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19
+#define R_IRQ_MASK1_SET__par1_peri__BITNR 18
+#define R_IRQ_MASK1_SET__par1_data__BITNR 17
+#define R_IRQ_MASK1_SET__par1_ready__BITNR 16
+#define R_IRQ_MASK1_SET__scsi1__BITNR 16
+#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15
+#define R_IRQ_MASK1_SET__ser3_data__BITNR 14
+#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13
+#define R_IRQ_MASK1_SET__ser2_data__BITNR 12
+#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11
+#define R_IRQ_MASK1_SET__ser1_data__BITNR 10
+#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9
+#define R_IRQ_MASK1_SET__ser0_data__BITNR 8
+#define R_IRQ_MASK1_SET__pa7__BITNR 7
+#define R_IRQ_MASK1_SET__pa6__BITNR 6
+#define R_IRQ_MASK1_SET__pa5__BITNR 5
+#define R_IRQ_MASK1_SET__pa4__BITNR 4
+#define R_IRQ_MASK1_SET__pa3__BITNR 3
+#define R_IRQ_MASK1_SET__pa2__BITNR 2
+#define R_IRQ_MASK1_SET__pa1__BITNR 1
+#define R_IRQ_MASK1_SET__pa0__BITNR 0
+
+#define R_IRQ_MASK1_SET__sw_int7__sw_int7__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__sw_int6__sw_int6__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__sw_int5__sw_int5__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__sw_int4__sw_int4__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__sw_int3__sw_int3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__sw_int2__sw_int2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__sw_int1__sw_int1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__sw_int0__sw_int0__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__par1_peri__par1_peri__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__par1_data__par1_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__par1_ready__par1_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__par1_ready__scsi1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__ser3_data__ser3_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__ser2_data__ser2_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__ser1_data__ser1_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__ser0_data__ser0_data__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__pa7__pa7__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__pa6__pa6__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__pa5__pa5__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__pa4__pa4__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__pa3__pa3__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__pa2__pa2__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__pa1__pa1__VAL REG_VAL_ENUM
+#define R_IRQ_MASK1_SET__pa0__pa0__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK1_SET__sw_int7__sw_int7__nop 0
+#define R_IRQ_MASK1_SET__sw_int7__sw_int7__set 1
+#define R_IRQ_MASK1_SET__sw_int6__sw_int6__nop 0
+#define R_IRQ_MASK1_SET__sw_int6__sw_int6__set 1
+#define R_IRQ_MASK1_SET__sw_int5__sw_int5__nop 0
+#define R_IRQ_MASK1_SET__sw_int5__sw_int5__set 1
+#define R_IRQ_MASK1_SET__sw_int4__sw_int4__nop 0
+#define R_IRQ_MASK1_SET__sw_int4__sw_int4__set 1
+#define R_IRQ_MASK1_SET__sw_int3__sw_int3__nop 0
+#define R_IRQ_MASK1_SET__sw_int3__sw_int3__set 1
+#define R_IRQ_MASK1_SET__sw_int2__sw_int2__nop 0
+#define R_IRQ_MASK1_SET__sw_int2__sw_int2__set 1
+#define R_IRQ_MASK1_SET__sw_int1__sw_int1__nop 0
+#define R_IRQ_MASK1_SET__sw_int1__sw_int1__set 1
+#define R_IRQ_MASK1_SET__sw_int0__sw_int0__nop 0
+#define R_IRQ_MASK1_SET__sw_int0__sw_int0__set 1
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__nop 0
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__par1_ecp_cmd__set 1
+#define R_IRQ_MASK1_SET__par1_peri__par1_peri__nop 0
+#define R_IRQ_MASK1_SET__par1_peri__par1_peri__set 1
+#define R_IRQ_MASK1_SET__par1_data__par1_data__nop 0
+#define R_IRQ_MASK1_SET__par1_data__par1_data__set 1
+#define R_IRQ_MASK1_SET__par1_ready__par1_ready__nop 0
+#define R_IRQ_MASK1_SET__par1_ready__par1_ready__set 1
+#define R_IRQ_MASK1_SET__scsi1__scsi1__nop 0
+#define R_IRQ_MASK1_SET__scsi1__scsi1__set 1
+#define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__nop 0
+#define R_IRQ_MASK1_SET__ser3_ready__ser3_ready__set 1
+#define R_IRQ_MASK1_SET__ser3_data__ser3_data__nop 0
+#define R_IRQ_MASK1_SET__ser3_data__ser3_data__set 1
+#define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__nop 0
+#define R_IRQ_MASK1_SET__ser2_ready__ser2_ready__set 1
+#define R_IRQ_MASK1_SET__ser2_data__ser2_data__nop 0
+#define R_IRQ_MASK1_SET__ser2_data__ser2_data__set 1
+#define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__nop 0
+#define R_IRQ_MASK1_SET__ser1_ready__ser1_ready__set 1
+#define R_IRQ_MASK1_SET__ser1_data__ser1_data__nop 0
+#define R_IRQ_MASK1_SET__ser1_data__ser1_data__set 1
+#define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__nop 0
+#define R_IRQ_MASK1_SET__ser0_ready__ser0_ready__set 1
+#define R_IRQ_MASK1_SET__ser0_data__ser0_data__nop 0
+#define R_IRQ_MASK1_SET__ser0_data__ser0_data__set 1
+#define R_IRQ_MASK1_SET__pa7__pa7__nop 0
+#define R_IRQ_MASK1_SET__pa7__pa7__set 1
+#define R_IRQ_MASK1_SET__pa6__pa6__nop 0
+#define R_IRQ_MASK1_SET__pa6__pa6__set 1
+#define R_IRQ_MASK1_SET__pa5__pa5__nop 0
+#define R_IRQ_MASK1_SET__pa5__pa5__set 1
+#define R_IRQ_MASK1_SET__pa4__pa4__nop 0
+#define R_IRQ_MASK1_SET__pa4__pa4__set 1
+#define R_IRQ_MASK1_SET__pa3__pa3__nop 0
+#define R_IRQ_MASK1_SET__pa3__pa3__set 1
+#define R_IRQ_MASK1_SET__pa2__pa2__nop 0
+#define R_IRQ_MASK1_SET__pa2__pa2__set 1
+#define R_IRQ_MASK1_SET__pa1__pa1__nop 0
+#define R_IRQ_MASK1_SET__pa1__pa1__set 1
+#define R_IRQ_MASK1_SET__pa0__pa0__nop 0
+#define R_IRQ_MASK1_SET__pa0__pa0__set 1
+
+#endif
+
+/*
+ * R_IRQ_MASK2_CLR
+ * - type: WO
+ * - addr: 0xb00000d0
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK2_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000d0)
+
+#ifndef REG_NO_SHADOW
+#define R_IRQ_MASK2_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK2_CLR + 0))
+#define R_IRQ_MASK2_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK2_CLR + 0))
+#else /* REG_NO_SHADOW */
+#define R_IRQ_MASK2_CLR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_IRQ_MASK2_CLR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_IRQ_MASK2_CLR__STYPECAST REG_STYPECAST_UDWORD
+#define R_IRQ_MASK2_CLR__SVAL REG_SVAL_ZERO
+#define R_IRQ_MASK2_CLR__SVAL_I REG_SVAL_I_ZERO
+#define R_IRQ_MASK2_CLR__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK2_CLR__TYPE (REG_UDWORD)
+#define R_IRQ_MASK2_CLR__GET REG_GET_WO
+#define R_IRQ_MASK2_CLR__IGET REG_IGET_WO
+#define R_IRQ_MASK2_CLR__SET REG_SET_WO
+#define R_IRQ_MASK2_CLR__ISET REG_ISET_WO
+#define R_IRQ_MASK2_CLR__SET_VAL REG_SET_VAL_WO
+#define R_IRQ_MASK2_CLR__EQL REG_EQL_WO
+#define R_IRQ_MASK2_CLR__IEQL REG_IEQL_WO
+#define R_IRQ_MASK2_CLR__RD REG_RD_WO
+#define R_IRQ_MASK2_CLR__IRD REG_IRD_WO
+#define R_IRQ_MASK2_CLR__WR REG_WR_WO
+#define R_IRQ_MASK2_CLR__IWR REG_IWR_WO
+
+#define R_IRQ_MASK2_CLR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U
+#define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__MASK 0x00080000U
+#define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__MASK 0x00040000U
+#define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__MASK 0x00020000U
+#define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__MASK 0x00010000U
+#define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__MASK 0x00008000U
+#define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__MASK 0x00004000U
+#define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__MASK 0x00002000U
+#define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__MASK 0x00001000U
+#define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__MASK 0x00000800U
+#define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__MASK 0x00000400U
+#define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__MASK 0x00000200U
+#define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__MASK 0x00000100U
+#define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__MASK 0x00000080U
+#define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__MASK 0x00000040U
+#define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__MASK 0x00000020U
+#define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__MASK 0x00000010U
+#define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__MASK 0x00000008U
+#define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__MASK 0x00000004U
+#define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__MASK 0x00000002U
+#define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__MASK 0x00000001U
+
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma9_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma9_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma8_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma8_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma7_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma7_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma6_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma6_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma5_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma5_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma4_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma4_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma3_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma3_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma2_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma2_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma1_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma1_descr__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma0_eop__MAX 0x1
+#define R_IRQ_MASK2_CLR__dma0_descr__MAX 0x1
+
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma9_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma9_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma8_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma8_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma7_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma7_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma6_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma6_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma5_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma5_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma4_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma4_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma3_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma3_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma2_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma2_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma1_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma1_descr__MIN 0
+#define R_IRQ_MASK2_CLR__dma0_eop__MIN 0
+#define R_IRQ_MASK2_CLR__dma0_descr__MIN 0
+
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20
+#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19
+#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18
+#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17
+#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16
+#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15
+#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14
+#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13
+#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12
+#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11
+#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10
+#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9
+#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8
+#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7
+#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6
+#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5
+#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4
+#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3
+#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2
+#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1
+#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0
+
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__dma8_sub3_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__dma8_sub2_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__dma8_sub1_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__dma8_sub0_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma9_eop__dma9_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma9_descr__dma9_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma8_eop__dma8_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_descr__dma8_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma7_eop__dma7_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma7_descr__dma7_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma6_eop__dma6_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma6_descr__dma6_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma5_eop__dma5_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma5_descr__dma5_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma4_eop__dma4_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma4_descr__dma4_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma3_eop__dma3_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma3_descr__dma3_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma2_eop__dma2_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma2_descr__dma2_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma1_eop__dma1_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma1_descr__dma1_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma0_eop__dma0_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma0_descr__dma0_descr__nop 0
+
+#endif
+
+/*
+ * R_IRQ_MASK2_RD
+ * - type: RO
+ * - addr: 0xb00000d0
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK2_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000d0)
+#define R_IRQ_MASK2_RD__SVAL REG_SVAL_SHADOW
+#define R_IRQ_MASK2_RD__SVAL_I REG_SVAL_I_SHADOW
+#define R_IRQ_MASK2_RD__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK2_RD__TYPE (REG_UDWORD)
+#define R_IRQ_MASK2_RD__GET REG_GET_RO
+#define R_IRQ_MASK2_RD__IGET REG_IGET_RO
+#define R_IRQ_MASK2_RD__SET REG_SET_RO
+#define R_IRQ_MASK2_RD__ISET REG_ISET_RO
+#define R_IRQ_MASK2_RD__SET_VAL REG_SET_VAL_RO
+#define R_IRQ_MASK2_RD__EQL REG_EQL_RO
+#define R_IRQ_MASK2_RD__IEQL REG_IEQL_RO
+#define R_IRQ_MASK2_RD__RD REG_RD_RO
+#define R_IRQ_MASK2_RD__IRD REG_IRD_RO
+#define R_IRQ_MASK2_RD__WR REG_WR_RO
+#define R_IRQ_MASK2_RD__IWR REG_IWR_RO
+
+#define R_IRQ_MASK2_RD__READ(addr) \
+ (*(addr))
+
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U
+#define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__MASK 0x00080000U
+#define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__MASK 0x00040000U
+#define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__MASK 0x00020000U
+#define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__MASK 0x00010000U
+#define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__MASK 0x00008000U
+#define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__MASK 0x00004000U
+#define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__MASK 0x00002000U
+#define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__MASK 0x00001000U
+#define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__MASK 0x00000800U
+#define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__MASK 0x00000400U
+#define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__MASK 0x00000200U
+#define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__MASK 0x00000100U
+#define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__MASK 0x00000080U
+#define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__MASK 0x00000040U
+#define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__MASK 0x00000020U
+#define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__MASK 0x00000010U
+#define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__MASK 0x00000008U
+#define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__MASK 0x00000004U
+#define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__MASK 0x00000002U
+#define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__MASK 0x00000001U
+
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma9_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma9_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma8_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma8_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma7_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma7_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma6_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma6_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma5_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma5_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma4_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma4_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma3_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma3_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma2_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma2_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma1_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma1_descr__MAX 0x1
+#define R_IRQ_MASK2_RD__dma0_eop__MAX 0x1
+#define R_IRQ_MASK2_RD__dma0_descr__MAX 0x1
+
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma9_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma9_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma8_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma8_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma7_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma7_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma6_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma6_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma5_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma5_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma4_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma4_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma3_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma3_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma2_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma2_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma1_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma1_descr__MIN 0
+#define R_IRQ_MASK2_RD__dma0_eop__MIN 0
+#define R_IRQ_MASK2_RD__dma0_descr__MIN 0
+
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20
+#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19
+#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18
+#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17
+#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16
+#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15
+#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14
+#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13
+#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12
+#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11
+#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10
+#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9
+#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8
+#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7
+#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6
+#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5
+#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4
+#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3
+#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2
+#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1
+#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0
+
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__dma8_sub3_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__dma8_sub2_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__dma8_sub1_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__dma8_sub0_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__active 1
+#define R_IRQ_MASK2_RD__dma9_eop__dma9_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__active 1
+#define R_IRQ_MASK2_RD__dma9_descr__dma9_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__active 1
+#define R_IRQ_MASK2_RD__dma8_eop__dma8_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_descr__dma8_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__active 1
+#define R_IRQ_MASK2_RD__dma7_eop__dma7_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__active 1
+#define R_IRQ_MASK2_RD__dma7_descr__dma7_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__active 1
+#define R_IRQ_MASK2_RD__dma6_eop__dma6_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__active 1
+#define R_IRQ_MASK2_RD__dma6_descr__dma6_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__active 1
+#define R_IRQ_MASK2_RD__dma5_eop__dma5_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__active 1
+#define R_IRQ_MASK2_RD__dma5_descr__dma5_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__active 1
+#define R_IRQ_MASK2_RD__dma4_eop__dma4_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__active 1
+#define R_IRQ_MASK2_RD__dma4_descr__dma4_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__active 1
+#define R_IRQ_MASK2_RD__dma3_eop__dma3_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__active 1
+#define R_IRQ_MASK2_RD__dma3_descr__dma3_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__active 1
+#define R_IRQ_MASK2_RD__dma2_eop__dma2_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__active 1
+#define R_IRQ_MASK2_RD__dma2_descr__dma2_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__active 1
+#define R_IRQ_MASK2_RD__dma1_eop__dma1_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__active 1
+#define R_IRQ_MASK2_RD__dma1_descr__dma1_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__active 1
+#define R_IRQ_MASK2_RD__dma0_eop__dma0_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__active 1
+#define R_IRQ_MASK2_RD__dma0_descr__dma0_descr__inactive 0
+
+#endif
+
+/*
+ * R_IRQ_MASK2_SET
+ * - type: WO
+ * - addr: 0xb00000d4
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_MASK2_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000d4)
+
+#ifndef REG_NO_SHADOW
+#define R_IRQ_MASK2_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_IRQ_MASK2_SET + 0))
+#define R_IRQ_MASK2_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_IRQ_MASK2_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_IRQ_MASK2_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_IRQ_MASK2_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_IRQ_MASK2_SET__STYPECAST REG_STYPECAST_UDWORD
+#define R_IRQ_MASK2_SET__SVAL REG_SVAL_ZERO
+#define R_IRQ_MASK2_SET__SVAL_I REG_SVAL_I_ZERO
+#define R_IRQ_MASK2_SET__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_MASK2_SET__TYPE (REG_UDWORD)
+#define R_IRQ_MASK2_SET__GET REG_GET_WO
+#define R_IRQ_MASK2_SET__IGET REG_IGET_WO
+#define R_IRQ_MASK2_SET__SET REG_SET_WO
+#define R_IRQ_MASK2_SET__ISET REG_ISET_WO
+#define R_IRQ_MASK2_SET__SET_VAL REG_SET_VAL_WO
+#define R_IRQ_MASK2_SET__EQL REG_EQL_WO
+#define R_IRQ_MASK2_SET__IEQL REG_IEQL_WO
+#define R_IRQ_MASK2_SET__RD REG_RD_WO
+#define R_IRQ_MASK2_SET__IRD REG_IRD_WO
+#define R_IRQ_MASK2_SET__WR REG_WR_WO
+#define R_IRQ_MASK2_SET__IWR REG_IWR_WO
+
+#define R_IRQ_MASK2_SET__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U
+#define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__MASK 0x00080000U
+#define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__MASK 0x00040000U
+#define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__MASK 0x00020000U
+#define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__MASK 0x00010000U
+#define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__MASK 0x00008000U
+#define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__MASK 0x00004000U
+#define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__MASK 0x00002000U
+#define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__MASK 0x00001000U
+#define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__MASK 0x00000800U
+#define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__MASK 0x00000400U
+#define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__MASK 0x00000200U
+#define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__MASK 0x00000100U
+#define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__MASK 0x00000080U
+#define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__MASK 0x00000040U
+#define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__MASK 0x00000020U
+#define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__MASK 0x00000010U
+#define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__MASK 0x00000008U
+#define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__MASK 0x00000004U
+#define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__MASK 0x00000002U
+#define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__MASK 0x00000001U
+
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma9_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma9_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma8_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma8_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma7_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma7_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma6_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma6_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma5_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma5_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma4_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma4_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma3_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma3_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma2_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma2_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma1_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma1_descr__MAX 0x1
+#define R_IRQ_MASK2_SET__dma0_eop__MAX 0x1
+#define R_IRQ_MASK2_SET__dma0_descr__MAX 0x1
+
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma9_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma9_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma8_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma8_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma7_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma7_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma6_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma6_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma5_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma5_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma4_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma4_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma3_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma3_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma2_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma2_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma1_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma1_descr__MIN 0
+#define R_IRQ_MASK2_SET__dma0_eop__MIN 0
+#define R_IRQ_MASK2_SET__dma0_descr__MIN 0
+
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20
+#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19
+#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18
+#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17
+#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16
+#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15
+#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14
+#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13
+#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12
+#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11
+#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10
+#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9
+#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8
+#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7
+#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6
+#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5
+#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4
+#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3
+#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2
+#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1
+#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0
+
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__VAL REG_VAL_ENUM
+#define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__VAL REG_VAL_ENUM
+
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__dma8_sub3_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__dma8_sub2_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__dma8_sub1_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__dma8_sub0_descr__set 1
+#define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__nop 0
+#define R_IRQ_MASK2_SET__dma9_eop__dma9_eop__set 1
+#define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__nop 0
+#define R_IRQ_MASK2_SET__dma9_descr__dma9_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__nop 0
+#define R_IRQ_MASK2_SET__dma8_eop__dma8_eop__set 1
+#define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_descr__dma8_descr__set 1
+#define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__nop 0
+#define R_IRQ_MASK2_SET__dma7_eop__dma7_eop__set 1
+#define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__nop 0
+#define R_IRQ_MASK2_SET__dma7_descr__dma7_descr__set 1
+#define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__nop 0
+#define R_IRQ_MASK2_SET__dma6_eop__dma6_eop__set 1
+#define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__nop 0
+#define R_IRQ_MASK2_SET__dma6_descr__dma6_descr__set 1
+#define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__nop 0
+#define R_IRQ_MASK2_SET__dma5_eop__dma5_eop__set 1
+#define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__nop 0
+#define R_IRQ_MASK2_SET__dma5_descr__dma5_descr__set 1
+#define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__nop 0
+#define R_IRQ_MASK2_SET__dma4_eop__dma4_eop__set 1
+#define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__nop 0
+#define R_IRQ_MASK2_SET__dma4_descr__dma4_descr__set 1
+#define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__nop 0
+#define R_IRQ_MASK2_SET__dma3_eop__dma3_eop__set 1
+#define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__nop 0
+#define R_IRQ_MASK2_SET__dma3_descr__dma3_descr__set 1
+#define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__nop 0
+#define R_IRQ_MASK2_SET__dma2_eop__dma2_eop__set 1
+#define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__nop 0
+#define R_IRQ_MASK2_SET__dma2_descr__dma2_descr__set 1
+#define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__nop 0
+#define R_IRQ_MASK2_SET__dma1_eop__dma1_eop__set 1
+#define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__nop 0
+#define R_IRQ_MASK2_SET__dma1_descr__dma1_descr__set 1
+#define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__nop 0
+#define R_IRQ_MASK2_SET__dma0_eop__dma0_eop__set 1
+#define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__nop 0
+#define R_IRQ_MASK2_SET__dma0_descr__dma0_descr__set 1
+
+#endif
+
+/*
+ * R_IRQ_READ0
+ * - type: RO
+ * - addr: 0xb00000c4
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_READ0__ADDR (REG_TYPECAST_UDWORD 0xb00000c4)
+#define R_IRQ_READ0__SVAL REG_SVAL_SHADOW
+#define R_IRQ_READ0__SVAL_I REG_SVAL_I_SHADOW
+#define R_IRQ_READ0__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_READ0__TYPE (REG_UDWORD)
+#define R_IRQ_READ0__GET REG_GET_RO
+#define R_IRQ_READ0__IGET REG_IGET_RO
+#define R_IRQ_READ0__SET REG_SET_RO
+#define R_IRQ_READ0__ISET REG_ISET_RO
+#define R_IRQ_READ0__SET_VAL REG_SET_VAL_RO
+#define R_IRQ_READ0__EQL REG_EQL_RO
+#define R_IRQ_READ0__IEQL REG_IEQL_RO
+#define R_IRQ_READ0__RD REG_RD_RO
+#define R_IRQ_READ0__IRD REG_IRD_RO
+#define R_IRQ_READ0__WR REG_WR_RO
+#define R_IRQ_READ0__IWR REG_IWR_RO
+
+#define R_IRQ_READ0__READ(addr) \
+ (*(addr))
+
+#define R_IRQ_READ0__nmi_pin__nmi_pin__MASK 0x80000000U
+#define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__MASK 0x40000000U
+#define R_IRQ_READ0__sqe_test_error__sqe_test_error__MASK 0x20000000U
+#define R_IRQ_READ0__carrier_loss__carrier_loss__MASK 0x10000000U
+#define R_IRQ_READ0__deferred__deferred__MASK 0x08000000U
+#define R_IRQ_READ0__late_col__late_col__MASK 0x04000000U
+#define R_IRQ_READ0__multiple_col__multiple_col__MASK 0x02000000U
+#define R_IRQ_READ0__single_col__single_col__MASK 0x01000000U
+#define R_IRQ_READ0__congestion__congestion__MASK 0x00800000U
+#define R_IRQ_READ0__oversize__oversize__MASK 0x00400000U
+#define R_IRQ_READ0__alignment_error__alignment_error__MASK 0x00200000U
+#define R_IRQ_READ0__crc_error__crc_error__MASK 0x00100000U
+#define R_IRQ_READ0__overrun__overrun__MASK 0x00080000U
+#define R_IRQ_READ0__underrun__underrun__MASK 0x00040000U
+#define R_IRQ_READ0__excessive_col__excessive_col__MASK 0x00020000U
+#define R_IRQ_READ0__mdio__mdio__MASK 0x00010000U
+#define R_IRQ_READ0__ata_drq3__ata_drq3__MASK 0x00008000U
+#define R_IRQ_READ0__ata_drq2__ata_drq2__MASK 0x00004000U
+#define R_IRQ_READ0__ata_drq1__ata_drq1__MASK 0x00002000U
+#define R_IRQ_READ0__ata_drq0__ata_drq0__MASK 0x00001000U
+#define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__MASK 0x00000800U
+#define R_IRQ_READ0__ata_irq3__ata_irq3__MASK 0x00000800U
+#define R_IRQ_READ0__par0_ecp_cmd__ata_irq3__MASK 0x00000800U
+#define R_IRQ_READ0__par0_peri__par0_peri__MASK 0x00000400U
+#define R_IRQ_READ0__ata_irq2__ata_irq2__MASK 0x00000400U
+#define R_IRQ_READ0__par0_peri__ata_irq2__MASK 0x00000400U
+#define R_IRQ_READ0__par0_data__par0_data__MASK 0x00000200U
+#define R_IRQ_READ0__ata_irq1__ata_irq1__MASK 0x00000200U
+#define R_IRQ_READ0__par0_data__ata_irq1__MASK 0x00000200U
+#define R_IRQ_READ0__par0_ready__par0_ready__MASK 0x00000100U
+#define R_IRQ_READ0__ata_irq0__ata_irq0__MASK 0x00000100U
+#define R_IRQ_READ0__par0_ready__ata_irq0__MASK 0x00000100U
+#define R_IRQ_READ0__mio__mio__MASK 0x00000100U
+#define R_IRQ_READ0__par0_ready__mio__MASK 0x00000100U
+#define R_IRQ_READ0__scsi0__scsi0__MASK 0x00000100U
+#define R_IRQ_READ0__par0_ready__scsi0__MASK 0x00000100U
+#define R_IRQ_READ0__ata_dmaend__ata_dmaend__MASK 0x00000080U
+#define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__MASK 0x00000020U
+#define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__MASK 0x00000010U
+#define R_IRQ_READ0__ext_dma1__ext_dma1__MASK 0x00000008U
+#define R_IRQ_READ0__ext_dma0__ext_dma0__MASK 0x00000004U
+#define R_IRQ_READ0__timer1__timer1__MASK 0x00000002U
+#define R_IRQ_READ0__timer0__timer0__MASK 0x00000001U
+
+#define R_IRQ_READ0__nmi_pin__MAX 0x1
+#define R_IRQ_READ0__watchdog_nmi__MAX 0x1
+#define R_IRQ_READ0__sqe_test_error__MAX 0x1
+#define R_IRQ_READ0__carrier_loss__MAX 0x1
+#define R_IRQ_READ0__deferred__MAX 0x1
+#define R_IRQ_READ0__late_col__MAX 0x1
+#define R_IRQ_READ0__multiple_col__MAX 0x1
+#define R_IRQ_READ0__single_col__MAX 0x1
+#define R_IRQ_READ0__congestion__MAX 0x1
+#define R_IRQ_READ0__oversize__MAX 0x1
+#define R_IRQ_READ0__alignment_error__MAX 0x1
+#define R_IRQ_READ0__crc_error__MAX 0x1
+#define R_IRQ_READ0__overrun__MAX 0x1
+#define R_IRQ_READ0__underrun__MAX 0x1
+#define R_IRQ_READ0__excessive_col__MAX 0x1
+#define R_IRQ_READ0__mdio__MAX 0x1
+#define R_IRQ_READ0__ata_drq3__MAX 0x1
+#define R_IRQ_READ0__ata_drq2__MAX 0x1
+#define R_IRQ_READ0__ata_drq1__MAX 0x1
+#define R_IRQ_READ0__ata_drq0__MAX 0x1
+#define R_IRQ_READ0__par0_ecp_cmd__MAX 0x1
+#define R_IRQ_READ0__ata_irq3__MAX 0x1
+#define R_IRQ_READ0__par0_peri__MAX 0x1
+#define R_IRQ_READ0__ata_irq2__MAX 0x1
+#define R_IRQ_READ0__par0_data__MAX 0x1
+#define R_IRQ_READ0__ata_irq1__MAX 0x1
+#define R_IRQ_READ0__par0_ready__MAX 0x1
+#define R_IRQ_READ0__ata_irq0__MAX 0x1
+#define R_IRQ_READ0__mio__MAX 0x1
+#define R_IRQ_READ0__scsi0__MAX 0x1
+#define R_IRQ_READ0__ata_dmaend__MAX 0x1
+#define R_IRQ_READ0__irq_ext_vector_nr__MAX 0x1
+#define R_IRQ_READ0__irq_int_vector_nr__MAX 0x1
+#define R_IRQ_READ0__ext_dma1__MAX 0x1
+#define R_IRQ_READ0__ext_dma0__MAX 0x1
+#define R_IRQ_READ0__timer1__MAX 0x1
+#define R_IRQ_READ0__timer0__MAX 0x1
+
+#define R_IRQ_READ0__nmi_pin__MIN 0
+#define R_IRQ_READ0__watchdog_nmi__MIN 0
+#define R_IRQ_READ0__sqe_test_error__MIN 0
+#define R_IRQ_READ0__carrier_loss__MIN 0
+#define R_IRQ_READ0__deferred__MIN 0
+#define R_IRQ_READ0__late_col__MIN 0
+#define R_IRQ_READ0__multiple_col__MIN 0
+#define R_IRQ_READ0__single_col__MIN 0
+#define R_IRQ_READ0__congestion__MIN 0
+#define R_IRQ_READ0__oversize__MIN 0
+#define R_IRQ_READ0__alignment_error__MIN 0
+#define R_IRQ_READ0__crc_error__MIN 0
+#define R_IRQ_READ0__overrun__MIN 0
+#define R_IRQ_READ0__underrun__MIN 0
+#define R_IRQ_READ0__excessive_col__MIN 0
+#define R_IRQ_READ0__mdio__MIN 0
+#define R_IRQ_READ0__ata_drq3__MIN 0
+#define R_IRQ_READ0__ata_drq2__MIN 0
+#define R_IRQ_READ0__ata_drq1__MIN 0
+#define R_IRQ_READ0__ata_drq0__MIN 0
+#define R_IRQ_READ0__par0_ecp_cmd__MIN 0
+#define R_IRQ_READ0__ata_irq3__MIN 0
+#define R_IRQ_READ0__par0_peri__MIN 0
+#define R_IRQ_READ0__ata_irq2__MIN 0
+#define R_IRQ_READ0__par0_data__MIN 0
+#define R_IRQ_READ0__ata_irq1__MIN 0
+#define R_IRQ_READ0__par0_ready__MIN 0
+#define R_IRQ_READ0__ata_irq0__MIN 0
+#define R_IRQ_READ0__mio__MIN 0
+#define R_IRQ_READ0__scsi0__MIN 0
+#define R_IRQ_READ0__ata_dmaend__MIN 0
+#define R_IRQ_READ0__irq_ext_vector_nr__MIN 0
+#define R_IRQ_READ0__irq_int_vector_nr__MIN 0
+#define R_IRQ_READ0__ext_dma1__MIN 0
+#define R_IRQ_READ0__ext_dma0__MIN 0
+#define R_IRQ_READ0__timer1__MIN 0
+#define R_IRQ_READ0__timer0__MIN 0
+
+#define R_IRQ_READ0__nmi_pin__BITNR 31
+#define R_IRQ_READ0__watchdog_nmi__BITNR 30
+#define R_IRQ_READ0__sqe_test_error__BITNR 29
+#define R_IRQ_READ0__carrier_loss__BITNR 28
+#define R_IRQ_READ0__deferred__BITNR 27
+#define R_IRQ_READ0__late_col__BITNR 26
+#define R_IRQ_READ0__multiple_col__BITNR 25
+#define R_IRQ_READ0__single_col__BITNR 24
+#define R_IRQ_READ0__congestion__BITNR 23
+#define R_IRQ_READ0__oversize__BITNR 22
+#define R_IRQ_READ0__alignment_error__BITNR 21
+#define R_IRQ_READ0__crc_error__BITNR 20
+#define R_IRQ_READ0__overrun__BITNR 19
+#define R_IRQ_READ0__underrun__BITNR 18
+#define R_IRQ_READ0__excessive_col__BITNR 17
+#define R_IRQ_READ0__mdio__BITNR 16
+#define R_IRQ_READ0__ata_drq3__BITNR 15
+#define R_IRQ_READ0__ata_drq2__BITNR 14
+#define R_IRQ_READ0__ata_drq1__BITNR 13
+#define R_IRQ_READ0__ata_drq0__BITNR 12
+#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11
+#define R_IRQ_READ0__ata_irq3__BITNR 11
+#define R_IRQ_READ0__par0_peri__BITNR 10
+#define R_IRQ_READ0__ata_irq2__BITNR 10
+#define R_IRQ_READ0__par0_data__BITNR 9
+#define R_IRQ_READ0__ata_irq1__BITNR 9
+#define R_IRQ_READ0__par0_ready__BITNR 8
+#define R_IRQ_READ0__ata_irq0__BITNR 8
+#define R_IRQ_READ0__mio__BITNR 8
+#define R_IRQ_READ0__scsi0__BITNR 8
+#define R_IRQ_READ0__ata_dmaend__BITNR 7
+#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5
+#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4
+#define R_IRQ_READ0__ext_dma1__BITNR 3
+#define R_IRQ_READ0__ext_dma0__BITNR 2
+#define R_IRQ_READ0__timer1__BITNR 1
+#define R_IRQ_READ0__timer0__BITNR 0
+
+#define R_IRQ_READ0__nmi_pin__nmi_pin__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__sqe_test_error__sqe_test_error__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__carrier_loss__carrier_loss__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__deferred__deferred__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__late_col__late_col__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__multiple_col__multiple_col__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__single_col__single_col__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__congestion__congestion__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__oversize__oversize__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__alignment_error__alignment_error__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__crc_error__crc_error__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__overrun__overrun__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__underrun__underrun__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__excessive_col__excessive_col__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__mdio__mdio__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_drq3__ata_drq3__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_drq2__ata_drq2__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_drq1__ata_drq1__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_drq0__ata_drq0__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_irq3__ata_irq3__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_ecp_cmd__ata_irq3__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_peri__par0_peri__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_irq2__ata_irq2__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_peri__ata_irq2__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_data__par0_data__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_irq1__ata_irq1__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_data__ata_irq1__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_ready__par0_ready__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_irq0__ata_irq0__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_ready__ata_irq0__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__mio__mio__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_ready__mio__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__par0_ready__scsi0__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ata_dmaend__ata_dmaend__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__timer1__timer1__VAL REG_VAL_ENUM
+#define R_IRQ_READ0__timer0__timer0__VAL REG_VAL_ENUM
+
+#define R_IRQ_READ0__nmi_pin__nmi_pin__active 1
+#define R_IRQ_READ0__nmi_pin__nmi_pin__inactive 0
+#define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__active 1
+#define R_IRQ_READ0__watchdog_nmi__watchdog_nmi__inactive 0
+#define R_IRQ_READ0__sqe_test_error__sqe_test_error__active 1
+#define R_IRQ_READ0__sqe_test_error__sqe_test_error__inactive 0
+#define R_IRQ_READ0__carrier_loss__carrier_loss__active 1
+#define R_IRQ_READ0__carrier_loss__carrier_loss__inactive 0
+#define R_IRQ_READ0__deferred__deferred__active 1
+#define R_IRQ_READ0__deferred__deferred__inactive 0
+#define R_IRQ_READ0__late_col__late_col__active 1
+#define R_IRQ_READ0__late_col__late_col__inactive 0
+#define R_IRQ_READ0__multiple_col__multiple_col__active 1
+#define R_IRQ_READ0__multiple_col__multiple_col__inactive 0
+#define R_IRQ_READ0__single_col__single_col__active 1
+#define R_IRQ_READ0__single_col__single_col__inactive 0
+#define R_IRQ_READ0__congestion__congestion__active 1
+#define R_IRQ_READ0__congestion__congestion__inactive 0
+#define R_IRQ_READ0__oversize__oversize__active 1
+#define R_IRQ_READ0__oversize__oversize__inactive 0
+#define R_IRQ_READ0__alignment_error__alignment_error__active 1
+#define R_IRQ_READ0__alignment_error__alignment_error__inactive 0
+#define R_IRQ_READ0__crc_error__crc_error__active 1
+#define R_IRQ_READ0__crc_error__crc_error__inactive 0
+#define R_IRQ_READ0__overrun__overrun__active 1
+#define R_IRQ_READ0__overrun__overrun__inactive 0
+#define R_IRQ_READ0__underrun__underrun__active 1
+#define R_IRQ_READ0__underrun__underrun__inactive 0
+#define R_IRQ_READ0__excessive_col__excessive_col__active 1
+#define R_IRQ_READ0__excessive_col__excessive_col__inactive 0
+#define R_IRQ_READ0__mdio__mdio__active 1
+#define R_IRQ_READ0__mdio__mdio__inactive 0
+#define R_IRQ_READ0__ata_drq3__ata_drq3__active 1
+#define R_IRQ_READ0__ata_drq3__ata_drq3__inactive 0
+#define R_IRQ_READ0__ata_drq2__ata_drq2__active 1
+#define R_IRQ_READ0__ata_drq2__ata_drq2__inactive 0
+#define R_IRQ_READ0__ata_drq1__ata_drq1__active 1
+#define R_IRQ_READ0__ata_drq1__ata_drq1__inactive 0
+#define R_IRQ_READ0__ata_drq0__ata_drq0__active 1
+#define R_IRQ_READ0__ata_drq0__ata_drq0__inactive 0
+#define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__active 1
+#define R_IRQ_READ0__par0_ecp_cmd__par0_ecp_cmd__inactive 0
+#define R_IRQ_READ0__ata_irq3__ata_irq3__active 1
+#define R_IRQ_READ0__ata_irq3__ata_irq3__inactive 0
+#define R_IRQ_READ0__par0_peri__par0_peri__active 1
+#define R_IRQ_READ0__par0_peri__par0_peri__inactive 0
+#define R_IRQ_READ0__ata_irq2__ata_irq2__active 1
+#define R_IRQ_READ0__ata_irq2__ata_irq2__inactive 0
+#define R_IRQ_READ0__par0_data__par0_data__active 1
+#define R_IRQ_READ0__par0_data__par0_data__inactive 0
+#define R_IRQ_READ0__ata_irq1__ata_irq1__active 1
+#define R_IRQ_READ0__ata_irq1__ata_irq1__inactive 0
+#define R_IRQ_READ0__par0_ready__par0_ready__active 1
+#define R_IRQ_READ0__par0_ready__par0_ready__inactive 0
+#define R_IRQ_READ0__ata_irq0__ata_irq0__active 1
+#define R_IRQ_READ0__ata_irq0__ata_irq0__inactive 0
+#define R_IRQ_READ0__mio__mio__active 1
+#define R_IRQ_READ0__mio__mio__inactive 0
+#define R_IRQ_READ0__scsi0__scsi0__active 1
+#define R_IRQ_READ0__scsi0__scsi0__inactive 0
+#define R_IRQ_READ0__ata_dmaend__ata_dmaend__active 1
+#define R_IRQ_READ0__ata_dmaend__ata_dmaend__inactive 0
+#define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__active 1
+#define R_IRQ_READ0__irq_ext_vector_nr__irq_ext_vector_nr__inactive 0
+#define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__active 1
+#define R_IRQ_READ0__irq_int_vector_nr__irq_int_vector_nr__inactive 0
+#define R_IRQ_READ0__ext_dma1__ext_dma1__active 1
+#define R_IRQ_READ0__ext_dma1__ext_dma1__inactive 0
+#define R_IRQ_READ0__ext_dma0__ext_dma0__active 1
+#define R_IRQ_READ0__ext_dma0__ext_dma0__inactive 0
+#define R_IRQ_READ0__timer1__timer1__active 1
+#define R_IRQ_READ0__timer1__timer1__inactive 0
+#define R_IRQ_READ0__timer0__timer0__active 1
+#define R_IRQ_READ0__timer0__timer0__inactive 0
+
+#endif
+
+/*
+ * R_IRQ_READ1
+ * - type: RO
+ * - addr: 0xb00000cc
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_READ1__ADDR (REG_TYPECAST_UDWORD 0xb00000cc)
+#define R_IRQ_READ1__SVAL REG_SVAL_SHADOW
+#define R_IRQ_READ1__SVAL_I REG_SVAL_I_SHADOW
+#define R_IRQ_READ1__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_READ1__TYPE (REG_UDWORD)
+#define R_IRQ_READ1__GET REG_GET_RO
+#define R_IRQ_READ1__IGET REG_IGET_RO
+#define R_IRQ_READ1__SET REG_SET_RO
+#define R_IRQ_READ1__ISET REG_ISET_RO
+#define R_IRQ_READ1__SET_VAL REG_SET_VAL_RO
+#define R_IRQ_READ1__EQL REG_EQL_RO
+#define R_IRQ_READ1__IEQL REG_IEQL_RO
+#define R_IRQ_READ1__RD REG_RD_RO
+#define R_IRQ_READ1__IRD REG_IRD_RO
+#define R_IRQ_READ1__WR REG_WR_RO
+#define R_IRQ_READ1__IWR REG_IWR_RO
+
+#define R_IRQ_READ1__READ(addr) \
+ (*(addr))
+
+#define R_IRQ_READ1__sw_int7__sw_int7__MASK 0x80000000U
+#define R_IRQ_READ1__sw_int6__sw_int6__MASK 0x40000000U
+#define R_IRQ_READ1__sw_int5__sw_int5__MASK 0x20000000U
+#define R_IRQ_READ1__sw_int4__sw_int4__MASK 0x10000000U
+#define R_IRQ_READ1__sw_int3__sw_int3__MASK 0x08000000U
+#define R_IRQ_READ1__sw_int2__sw_int2__MASK 0x04000000U
+#define R_IRQ_READ1__sw_int1__sw_int1__MASK 0x02000000U
+#define R_IRQ_READ1__sw_int0__sw_int0__MASK 0x01000000U
+#define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__MASK 0x00080000U
+#define R_IRQ_READ1__par1_peri__par1_peri__MASK 0x00040000U
+#define R_IRQ_READ1__par1_data__par1_data__MASK 0x00020000U
+#define R_IRQ_READ1__par1_ready__par1_ready__MASK 0x00010000U
+#define R_IRQ_READ1__scsi1__scsi1__MASK 0x00010000U
+#define R_IRQ_READ1__par1_ready__scsi1__MASK 0x00010000U
+#define R_IRQ_READ1__ser3_ready__ser3_ready__MASK 0x00008000U
+#define R_IRQ_READ1__ser3_data__ser3_data__MASK 0x00004000U
+#define R_IRQ_READ1__ser2_ready__ser2_ready__MASK 0x00002000U
+#define R_IRQ_READ1__ser2_data__ser2_data__MASK 0x00001000U
+#define R_IRQ_READ1__ser1_ready__ser1_ready__MASK 0x00000800U
+#define R_IRQ_READ1__ser1_data__ser1_data__MASK 0x00000400U
+#define R_IRQ_READ1__ser0_ready__ser0_ready__MASK 0x00000200U
+#define R_IRQ_READ1__ser0_data__ser0_data__MASK 0x00000100U
+#define R_IRQ_READ1__pa7__pa7__MASK 0x00000080U
+#define R_IRQ_READ1__pa6__pa6__MASK 0x00000040U
+#define R_IRQ_READ1__pa5__pa5__MASK 0x00000020U
+#define R_IRQ_READ1__pa4__pa4__MASK 0x00000010U
+#define R_IRQ_READ1__pa3__pa3__MASK 0x00000008U
+#define R_IRQ_READ1__pa2__pa2__MASK 0x00000004U
+#define R_IRQ_READ1__pa1__pa1__MASK 0x00000002U
+#define R_IRQ_READ1__pa0__pa0__MASK 0x00000001U
+
+#define R_IRQ_READ1__sw_int7__MAX 0x1
+#define R_IRQ_READ1__sw_int6__MAX 0x1
+#define R_IRQ_READ1__sw_int5__MAX 0x1
+#define R_IRQ_READ1__sw_int4__MAX 0x1
+#define R_IRQ_READ1__sw_int3__MAX 0x1
+#define R_IRQ_READ1__sw_int2__MAX 0x1
+#define R_IRQ_READ1__sw_int1__MAX 0x1
+#define R_IRQ_READ1__sw_int0__MAX 0x1
+#define R_IRQ_READ1__par1_ecp_cmd__MAX 0x1
+#define R_IRQ_READ1__par1_peri__MAX 0x1
+#define R_IRQ_READ1__par1_data__MAX 0x1
+#define R_IRQ_READ1__par1_ready__MAX 0x1
+#define R_IRQ_READ1__scsi1__MAX 0x1
+#define R_IRQ_READ1__ser3_ready__MAX 0x1
+#define R_IRQ_READ1__ser3_data__MAX 0x1
+#define R_IRQ_READ1__ser2_ready__MAX 0x1
+#define R_IRQ_READ1__ser2_data__MAX 0x1
+#define R_IRQ_READ1__ser1_ready__MAX 0x1
+#define R_IRQ_READ1__ser1_data__MAX 0x1
+#define R_IRQ_READ1__ser0_ready__MAX 0x1
+#define R_IRQ_READ1__ser0_data__MAX 0x1
+#define R_IRQ_READ1__pa7__MAX 0x1
+#define R_IRQ_READ1__pa6__MAX 0x1
+#define R_IRQ_READ1__pa5__MAX 0x1
+#define R_IRQ_READ1__pa4__MAX 0x1
+#define R_IRQ_READ1__pa3__MAX 0x1
+#define R_IRQ_READ1__pa2__MAX 0x1
+#define R_IRQ_READ1__pa1__MAX 0x1
+#define R_IRQ_READ1__pa0__MAX 0x1
+
+#define R_IRQ_READ1__sw_int7__MIN 0
+#define R_IRQ_READ1__sw_int6__MIN 0
+#define R_IRQ_READ1__sw_int5__MIN 0
+#define R_IRQ_READ1__sw_int4__MIN 0
+#define R_IRQ_READ1__sw_int3__MIN 0
+#define R_IRQ_READ1__sw_int2__MIN 0
+#define R_IRQ_READ1__sw_int1__MIN 0
+#define R_IRQ_READ1__sw_int0__MIN 0
+#define R_IRQ_READ1__par1_ecp_cmd__MIN 0
+#define R_IRQ_READ1__par1_peri__MIN 0
+#define R_IRQ_READ1__par1_data__MIN 0
+#define R_IRQ_READ1__par1_ready__MIN 0
+#define R_IRQ_READ1__scsi1__MIN 0
+#define R_IRQ_READ1__ser3_ready__MIN 0
+#define R_IRQ_READ1__ser3_data__MIN 0
+#define R_IRQ_READ1__ser2_ready__MIN 0
+#define R_IRQ_READ1__ser2_data__MIN 0
+#define R_IRQ_READ1__ser1_ready__MIN 0
+#define R_IRQ_READ1__ser1_data__MIN 0
+#define R_IRQ_READ1__ser0_ready__MIN 0
+#define R_IRQ_READ1__ser0_data__MIN 0
+#define R_IRQ_READ1__pa7__MIN 0
+#define R_IRQ_READ1__pa6__MIN 0
+#define R_IRQ_READ1__pa5__MIN 0
+#define R_IRQ_READ1__pa4__MIN 0
+#define R_IRQ_READ1__pa3__MIN 0
+#define R_IRQ_READ1__pa2__MIN 0
+#define R_IRQ_READ1__pa1__MIN 0
+#define R_IRQ_READ1__pa0__MIN 0
+
+#define R_IRQ_READ1__sw_int7__BITNR 31
+#define R_IRQ_READ1__sw_int6__BITNR 30
+#define R_IRQ_READ1__sw_int5__BITNR 29
+#define R_IRQ_READ1__sw_int4__BITNR 28
+#define R_IRQ_READ1__sw_int3__BITNR 27
+#define R_IRQ_READ1__sw_int2__BITNR 26
+#define R_IRQ_READ1__sw_int1__BITNR 25
+#define R_IRQ_READ1__sw_int0__BITNR 24
+#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19
+#define R_IRQ_READ1__par1_peri__BITNR 18
+#define R_IRQ_READ1__par1_data__BITNR 17
+#define R_IRQ_READ1__par1_ready__BITNR 16
+#define R_IRQ_READ1__scsi1__BITNR 16
+#define R_IRQ_READ1__ser3_ready__BITNR 15
+#define R_IRQ_READ1__ser3_data__BITNR 14
+#define R_IRQ_READ1__ser2_ready__BITNR 13
+#define R_IRQ_READ1__ser2_data__BITNR 12
+#define R_IRQ_READ1__ser1_ready__BITNR 11
+#define R_IRQ_READ1__ser1_data__BITNR 10
+#define R_IRQ_READ1__ser0_ready__BITNR 9
+#define R_IRQ_READ1__ser0_data__BITNR 8
+#define R_IRQ_READ1__pa7__BITNR 7
+#define R_IRQ_READ1__pa6__BITNR 6
+#define R_IRQ_READ1__pa5__BITNR 5
+#define R_IRQ_READ1__pa4__BITNR 4
+#define R_IRQ_READ1__pa3__BITNR 3
+#define R_IRQ_READ1__pa2__BITNR 2
+#define R_IRQ_READ1__pa1__BITNR 1
+#define R_IRQ_READ1__pa0__BITNR 0
+
+#define R_IRQ_READ1__sw_int7__sw_int7__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__sw_int6__sw_int6__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__sw_int5__sw_int5__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__sw_int4__sw_int4__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__sw_int3__sw_int3__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__sw_int2__sw_int2__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__sw_int1__sw_int1__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__sw_int0__sw_int0__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__par1_peri__par1_peri__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__par1_data__par1_data__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__par1_ready__par1_ready__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__par1_ready__scsi1__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__ser3_ready__ser3_ready__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__ser3_data__ser3_data__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__ser2_ready__ser2_ready__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__ser2_data__ser2_data__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__ser1_ready__ser1_ready__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__ser1_data__ser1_data__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__ser0_ready__ser0_ready__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__ser0_data__ser0_data__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__pa7__pa7__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__pa6__pa6__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__pa5__pa5__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__pa4__pa4__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__pa3__pa3__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__pa2__pa2__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__pa1__pa1__VAL REG_VAL_ENUM
+#define R_IRQ_READ1__pa0__pa0__VAL REG_VAL_ENUM
+
+#define R_IRQ_READ1__sw_int7__sw_int7__active 1
+#define R_IRQ_READ1__sw_int7__sw_int7__inactive 0
+#define R_IRQ_READ1__sw_int6__sw_int6__active 1
+#define R_IRQ_READ1__sw_int6__sw_int6__inactive 0
+#define R_IRQ_READ1__sw_int5__sw_int5__active 1
+#define R_IRQ_READ1__sw_int5__sw_int5__inactive 0
+#define R_IRQ_READ1__sw_int4__sw_int4__active 1
+#define R_IRQ_READ1__sw_int4__sw_int4__inactive 0
+#define R_IRQ_READ1__sw_int3__sw_int3__active 1
+#define R_IRQ_READ1__sw_int3__sw_int3__inactive 0
+#define R_IRQ_READ1__sw_int2__sw_int2__active 1
+#define R_IRQ_READ1__sw_int2__sw_int2__inactive 0
+#define R_IRQ_READ1__sw_int1__sw_int1__active 1
+#define R_IRQ_READ1__sw_int1__sw_int1__inactive 0
+#define R_IRQ_READ1__sw_int0__sw_int0__active 1
+#define R_IRQ_READ1__sw_int0__sw_int0__inactive 0
+#define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__active 1
+#define R_IRQ_READ1__par1_ecp_cmd__par1_ecp_cmd__inactive 0
+#define R_IRQ_READ1__par1_peri__par1_peri__active 1
+#define R_IRQ_READ1__par1_peri__par1_peri__inactive 0
+#define R_IRQ_READ1__par1_data__par1_data__active 1
+#define R_IRQ_READ1__par1_data__par1_data__inactive 0
+#define R_IRQ_READ1__par1_ready__par1_ready__active 1
+#define R_IRQ_READ1__par1_ready__par1_ready__inactive 0
+#define R_IRQ_READ1__scsi1__scsi1__active 1
+#define R_IRQ_READ1__scsi1__scsi1__inactive 0
+#define R_IRQ_READ1__ser3_ready__ser3_ready__active 1
+#define R_IRQ_READ1__ser3_ready__ser3_ready__inactive 0
+#define R_IRQ_READ1__ser3_data__ser3_data__active 1
+#define R_IRQ_READ1__ser3_data__ser3_data__inactive 0
+#define R_IRQ_READ1__ser2_ready__ser2_ready__active 1
+#define R_IRQ_READ1__ser2_ready__ser2_ready__inactive 0
+#define R_IRQ_READ1__ser2_data__ser2_data__active 1
+#define R_IRQ_READ1__ser2_data__ser2_data__inactive 0
+#define R_IRQ_READ1__ser1_ready__ser1_ready__active 1
+#define R_IRQ_READ1__ser1_ready__ser1_ready__inactive 0
+#define R_IRQ_READ1__ser1_data__ser1_data__active 1
+#define R_IRQ_READ1__ser1_data__ser1_data__inactive 0
+#define R_IRQ_READ1__ser0_ready__ser0_ready__active 1
+#define R_IRQ_READ1__ser0_ready__ser0_ready__inactive 0
+#define R_IRQ_READ1__ser0_data__ser0_data__active 1
+#define R_IRQ_READ1__ser0_data__ser0_data__inactive 0
+#define R_IRQ_READ1__pa7__pa7__active 1
+#define R_IRQ_READ1__pa7__pa7__inactive 0
+#define R_IRQ_READ1__pa6__pa6__active 1
+#define R_IRQ_READ1__pa6__pa6__inactive 0
+#define R_IRQ_READ1__pa5__pa5__active 1
+#define R_IRQ_READ1__pa5__pa5__inactive 0
+#define R_IRQ_READ1__pa4__pa4__active 1
+#define R_IRQ_READ1__pa4__pa4__inactive 0
+#define R_IRQ_READ1__pa3__pa3__active 1
+#define R_IRQ_READ1__pa3__pa3__inactive 0
+#define R_IRQ_READ1__pa2__pa2__active 1
+#define R_IRQ_READ1__pa2__pa2__inactive 0
+#define R_IRQ_READ1__pa1__pa1__active 1
+#define R_IRQ_READ1__pa1__pa1__inactive 0
+#define R_IRQ_READ1__pa0__pa0__active 1
+#define R_IRQ_READ1__pa0__pa0__inactive 0
+
+#endif
+
+/*
+ * R_IRQ_READ2
+ * - type: RO
+ * - addr: 0xb00000d4
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_IRQ_READ2__ADDR (REG_TYPECAST_UDWORD 0xb00000d4)
+#define R_IRQ_READ2__SVAL REG_SVAL_SHADOW
+#define R_IRQ_READ2__SVAL_I REG_SVAL_I_SHADOW
+#define R_IRQ_READ2__TYPECAST REG_TYPECAST_UDWORD
+#define R_IRQ_READ2__TYPE (REG_UDWORD)
+#define R_IRQ_READ2__GET REG_GET_RO
+#define R_IRQ_READ2__IGET REG_IGET_RO
+#define R_IRQ_READ2__SET REG_SET_RO
+#define R_IRQ_READ2__ISET REG_ISET_RO
+#define R_IRQ_READ2__SET_VAL REG_SET_VAL_RO
+#define R_IRQ_READ2__EQL REG_EQL_RO
+#define R_IRQ_READ2__IEQL REG_IEQL_RO
+#define R_IRQ_READ2__RD REG_RD_RO
+#define R_IRQ_READ2__IRD REG_IRD_RO
+#define R_IRQ_READ2__WR REG_WR_RO
+#define R_IRQ_READ2__IWR REG_IWR_RO
+
+#define R_IRQ_READ2__READ(addr) \
+ (*(addr))
+
+#define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__MASK 0x00800000U
+#define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__MASK 0x00400000U
+#define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__MASK 0x00200000U
+#define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__MASK 0x00100000U
+#define R_IRQ_READ2__dma9_eop__dma9_eop__MASK 0x00080000U
+#define R_IRQ_READ2__dma9_descr__dma9_descr__MASK 0x00040000U
+#define R_IRQ_READ2__dma8_eop__dma8_eop__MASK 0x00020000U
+#define R_IRQ_READ2__dma8_descr__dma8_descr__MASK 0x00010000U
+#define R_IRQ_READ2__dma7_eop__dma7_eop__MASK 0x00008000U
+#define R_IRQ_READ2__dma7_descr__dma7_descr__MASK 0x00004000U
+#define R_IRQ_READ2__dma6_eop__dma6_eop__MASK 0x00002000U
+#define R_IRQ_READ2__dma6_descr__dma6_descr__MASK 0x00001000U
+#define R_IRQ_READ2__dma5_eop__dma5_eop__MASK 0x00000800U
+#define R_IRQ_READ2__dma5_descr__dma5_descr__MASK 0x00000400U
+#define R_IRQ_READ2__dma4_eop__dma4_eop__MASK 0x00000200U
+#define R_IRQ_READ2__dma4_descr__dma4_descr__MASK 0x00000100U
+#define R_IRQ_READ2__dma3_eop__dma3_eop__MASK 0x00000080U
+#define R_IRQ_READ2__dma3_descr__dma3_descr__MASK 0x00000040U
+#define R_IRQ_READ2__dma2_eop__dma2_eop__MASK 0x00000020U
+#define R_IRQ_READ2__dma2_descr__dma2_descr__MASK 0x00000010U
+#define R_IRQ_READ2__dma1_eop__dma1_eop__MASK 0x00000008U
+#define R_IRQ_READ2__dma1_descr__dma1_descr__MASK 0x00000004U
+#define R_IRQ_READ2__dma0_eop__dma0_eop__MASK 0x00000002U
+#define R_IRQ_READ2__dma0_descr__dma0_descr__MASK 0x00000001U
+
+#define R_IRQ_READ2__dma8_sub3_descr__MAX 0x1
+#define R_IRQ_READ2__dma8_sub2_descr__MAX 0x1
+#define R_IRQ_READ2__dma8_sub1_descr__MAX 0x1
+#define R_IRQ_READ2__dma8_sub0_descr__MAX 0x1
+#define R_IRQ_READ2__dma9_eop__MAX 0x1
+#define R_IRQ_READ2__dma9_descr__MAX 0x1
+#define R_IRQ_READ2__dma8_eop__MAX 0x1
+#define R_IRQ_READ2__dma8_descr__MAX 0x1
+#define R_IRQ_READ2__dma7_eop__MAX 0x1
+#define R_IRQ_READ2__dma7_descr__MAX 0x1
+#define R_IRQ_READ2__dma6_eop__MAX 0x1
+#define R_IRQ_READ2__dma6_descr__MAX 0x1
+#define R_IRQ_READ2__dma5_eop__MAX 0x1
+#define R_IRQ_READ2__dma5_descr__MAX 0x1
+#define R_IRQ_READ2__dma4_eop__MAX 0x1
+#define R_IRQ_READ2__dma4_descr__MAX 0x1
+#define R_IRQ_READ2__dma3_eop__MAX 0x1
+#define R_IRQ_READ2__dma3_descr__MAX 0x1
+#define R_IRQ_READ2__dma2_eop__MAX 0x1
+#define R_IRQ_READ2__dma2_descr__MAX 0x1
+#define R_IRQ_READ2__dma1_eop__MAX 0x1
+#define R_IRQ_READ2__dma1_descr__MAX 0x1
+#define R_IRQ_READ2__dma0_eop__MAX 0x1
+#define R_IRQ_READ2__dma0_descr__MAX 0x1
+
+#define R_IRQ_READ2__dma8_sub3_descr__MIN 0
+#define R_IRQ_READ2__dma8_sub2_descr__MIN 0
+#define R_IRQ_READ2__dma8_sub1_descr__MIN 0
+#define R_IRQ_READ2__dma8_sub0_descr__MIN 0
+#define R_IRQ_READ2__dma9_eop__MIN 0
+#define R_IRQ_READ2__dma9_descr__MIN 0
+#define R_IRQ_READ2__dma8_eop__MIN 0
+#define R_IRQ_READ2__dma8_descr__MIN 0
+#define R_IRQ_READ2__dma7_eop__MIN 0
+#define R_IRQ_READ2__dma7_descr__MIN 0
+#define R_IRQ_READ2__dma6_eop__MIN 0
+#define R_IRQ_READ2__dma6_descr__MIN 0
+#define R_IRQ_READ2__dma5_eop__MIN 0
+#define R_IRQ_READ2__dma5_descr__MIN 0
+#define R_IRQ_READ2__dma4_eop__MIN 0
+#define R_IRQ_READ2__dma4_descr__MIN 0
+#define R_IRQ_READ2__dma3_eop__MIN 0
+#define R_IRQ_READ2__dma3_descr__MIN 0
+#define R_IRQ_READ2__dma2_eop__MIN 0
+#define R_IRQ_READ2__dma2_descr__MIN 0
+#define R_IRQ_READ2__dma1_eop__MIN 0
+#define R_IRQ_READ2__dma1_descr__MIN 0
+#define R_IRQ_READ2__dma0_eop__MIN 0
+#define R_IRQ_READ2__dma0_descr__MIN 0
+
+#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23
+#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22
+#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21
+#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20
+#define R_IRQ_READ2__dma9_eop__BITNR 19
+#define R_IRQ_READ2__dma9_descr__BITNR 18
+#define R_IRQ_READ2__dma8_eop__BITNR 17
+#define R_IRQ_READ2__dma8_descr__BITNR 16
+#define R_IRQ_READ2__dma7_eop__BITNR 15
+#define R_IRQ_READ2__dma7_descr__BITNR 14
+#define R_IRQ_READ2__dma6_eop__BITNR 13
+#define R_IRQ_READ2__dma6_descr__BITNR 12
+#define R_IRQ_READ2__dma5_eop__BITNR 11
+#define R_IRQ_READ2__dma5_descr__BITNR 10
+#define R_IRQ_READ2__dma4_eop__BITNR 9
+#define R_IRQ_READ2__dma4_descr__BITNR 8
+#define R_IRQ_READ2__dma3_eop__BITNR 7
+#define R_IRQ_READ2__dma3_descr__BITNR 6
+#define R_IRQ_READ2__dma2_eop__BITNR 5
+#define R_IRQ_READ2__dma2_descr__BITNR 4
+#define R_IRQ_READ2__dma1_eop__BITNR 3
+#define R_IRQ_READ2__dma1_descr__BITNR 2
+#define R_IRQ_READ2__dma0_eop__BITNR 1
+#define R_IRQ_READ2__dma0_descr__BITNR 0
+
+#define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma9_eop__dma9_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma9_descr__dma9_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma8_eop__dma8_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma8_descr__dma8_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma7_eop__dma7_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma7_descr__dma7_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma6_eop__dma6_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma6_descr__dma6_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma5_eop__dma5_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma5_descr__dma5_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma4_eop__dma4_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma4_descr__dma4_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma3_eop__dma3_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma3_descr__dma3_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma2_eop__dma2_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma2_descr__dma2_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma1_eop__dma1_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma1_descr__dma1_descr__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma0_eop__dma0_eop__VAL REG_VAL_ENUM
+#define R_IRQ_READ2__dma0_descr__dma0_descr__VAL REG_VAL_ENUM
+
+#define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__active 1
+#define R_IRQ_READ2__dma8_sub3_descr__dma8_sub3_descr__inactive 0
+#define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__active 1
+#define R_IRQ_READ2__dma8_sub2_descr__dma8_sub2_descr__inactive 0
+#define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__active 1
+#define R_IRQ_READ2__dma8_sub1_descr__dma8_sub1_descr__inactive 0
+#define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__active 1
+#define R_IRQ_READ2__dma8_sub0_descr__dma8_sub0_descr__inactive 0
+#define R_IRQ_READ2__dma9_eop__dma9_eop__active 1
+#define R_IRQ_READ2__dma9_eop__dma9_eop__inactive 0
+#define R_IRQ_READ2__dma9_descr__dma9_descr__active 1
+#define R_IRQ_READ2__dma9_descr__dma9_descr__inactive 0
+#define R_IRQ_READ2__dma8_eop__dma8_eop__active 1
+#define R_IRQ_READ2__dma8_eop__dma8_eop__inactive 0
+#define R_IRQ_READ2__dma8_descr__dma8_descr__active 1
+#define R_IRQ_READ2__dma8_descr__dma8_descr__inactive 0
+#define R_IRQ_READ2__dma7_eop__dma7_eop__active 1
+#define R_IRQ_READ2__dma7_eop__dma7_eop__inactive 0
+#define R_IRQ_READ2__dma7_descr__dma7_descr__active 1
+#define R_IRQ_READ2__dma7_descr__dma7_descr__inactive 0
+#define R_IRQ_READ2__dma6_eop__dma6_eop__active 1
+#define R_IRQ_READ2__dma6_eop__dma6_eop__inactive 0
+#define R_IRQ_READ2__dma6_descr__dma6_descr__active 1
+#define R_IRQ_READ2__dma6_descr__dma6_descr__inactive 0
+#define R_IRQ_READ2__dma5_eop__dma5_eop__active 1
+#define R_IRQ_READ2__dma5_eop__dma5_eop__inactive 0
+#define R_IRQ_READ2__dma5_descr__dma5_descr__active 1
+#define R_IRQ_READ2__dma5_descr__dma5_descr__inactive 0
+#define R_IRQ_READ2__dma4_eop__dma4_eop__active 1
+#define R_IRQ_READ2__dma4_eop__dma4_eop__inactive 0
+#define R_IRQ_READ2__dma4_descr__dma4_descr__active 1
+#define R_IRQ_READ2__dma4_descr__dma4_descr__inactive 0
+#define R_IRQ_READ2__dma3_eop__dma3_eop__active 1
+#define R_IRQ_READ2__dma3_eop__dma3_eop__inactive 0
+#define R_IRQ_READ2__dma3_descr__dma3_descr__active 1
+#define R_IRQ_READ2__dma3_descr__dma3_descr__inactive 0
+#define R_IRQ_READ2__dma2_eop__dma2_eop__active 1
+#define R_IRQ_READ2__dma2_eop__dma2_eop__inactive 0
+#define R_IRQ_READ2__dma2_descr__dma2_descr__active 1
+#define R_IRQ_READ2__dma2_descr__dma2_descr__inactive 0
+#define R_IRQ_READ2__dma1_eop__dma1_eop__active 1
+#define R_IRQ_READ2__dma1_eop__dma1_eop__inactive 0
+#define R_IRQ_READ2__dma1_descr__dma1_descr__active 1
+#define R_IRQ_READ2__dma1_descr__dma1_descr__inactive 0
+#define R_IRQ_READ2__dma0_eop__dma0_eop__active 1
+#define R_IRQ_READ2__dma0_eop__dma0_eop__inactive 0
+#define R_IRQ_READ2__dma0_descr__dma0_descr__active 1
+#define R_IRQ_READ2__dma0_descr__dma0_descr__inactive 0
+
+#endif
+
+/*
+ * R_MMU_CAUSE
+ * - type: RO
+ * - addr: 0xb0000250
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_MMU_CAUSE__ADDR (REG_TYPECAST_UDWORD 0xb0000250)
+#define R_MMU_CAUSE__SVAL REG_SVAL_SHADOW
+#define R_MMU_CAUSE__SVAL_I REG_SVAL_I_SHADOW
+#define R_MMU_CAUSE__TYPECAST REG_TYPECAST_UDWORD
+#define R_MMU_CAUSE__TYPE (REG_UDWORD)
+#define R_MMU_CAUSE__GET REG_GET_RO
+#define R_MMU_CAUSE__IGET REG_IGET_RO
+#define R_MMU_CAUSE__SET REG_SET_RO
+#define R_MMU_CAUSE__ISET REG_ISET_RO
+#define R_MMU_CAUSE__SET_VAL REG_SET_VAL_RO
+#define R_MMU_CAUSE__EQL REG_EQL_RO
+#define R_MMU_CAUSE__IEQL REG_IEQL_RO
+#define R_MMU_CAUSE__RD REG_RD_RO
+#define R_MMU_CAUSE__IRD REG_IRD_RO
+#define R_MMU_CAUSE__WR REG_WR_RO
+#define R_MMU_CAUSE__IWR REG_IWR_RO
+
+#define R_MMU_CAUSE__READ(addr) \
+ (*(addr))
+
+#define R_MMU_CAUSE__vpn__vpn__MASK 0xffffe000U
+#define R_MMU_CAUSE__miss_excp__miss_excp__MASK 0x00001000U
+#define R_MMU_CAUSE__inv_excp__inv_excp__MASK 0x00000800U
+#define R_MMU_CAUSE__acc_excp__acc_excp__MASK 0x00000400U
+#define R_MMU_CAUSE__we_excp__we_excp__MASK 0x00000200U
+#define R_MMU_CAUSE__wr_rd__wr_rd__MASK 0x00000100U
+#define R_MMU_CAUSE__page_id__page_id__MASK 0x0000003fU
+
+#define R_MMU_CAUSE__vpn__MAX 0x7ffff
+#define R_MMU_CAUSE__miss_excp__MAX 0x1
+#define R_MMU_CAUSE__inv_excp__MAX 0x1
+#define R_MMU_CAUSE__acc_excp__MAX 0x1
+#define R_MMU_CAUSE__we_excp__MAX 0x1
+#define R_MMU_CAUSE__wr_rd__MAX 0x1
+#define R_MMU_CAUSE__page_id__MAX 63
+
+#define R_MMU_CAUSE__vpn__MIN 0
+#define R_MMU_CAUSE__miss_excp__MIN 0
+#define R_MMU_CAUSE__inv_excp__MIN 0
+#define R_MMU_CAUSE__acc_excp__MIN 0
+#define R_MMU_CAUSE__we_excp__MIN 0
+#define R_MMU_CAUSE__wr_rd__MIN 0
+#define R_MMU_CAUSE__page_id__MIN 0
+
+#define R_MMU_CAUSE__vpn__BITNR 13
+#define R_MMU_CAUSE__miss_excp__BITNR 12
+#define R_MMU_CAUSE__inv_excp__BITNR 11
+#define R_MMU_CAUSE__acc_excp__BITNR 10
+#define R_MMU_CAUSE__we_excp__BITNR 9
+#define R_MMU_CAUSE__wr_rd__BITNR 8
+#define R_MMU_CAUSE__page_id__BITNR 0
+
+#define R_MMU_CAUSE__vpn__vpn__VAL REG_VAL_VAL
+#define R_MMU_CAUSE__miss_excp__miss_excp__VAL REG_VAL_ENUM
+#define R_MMU_CAUSE__inv_excp__inv_excp__VAL REG_VAL_ENUM
+#define R_MMU_CAUSE__acc_excp__acc_excp__VAL REG_VAL_ENUM
+#define R_MMU_CAUSE__we_excp__we_excp__VAL REG_VAL_ENUM
+#define R_MMU_CAUSE__wr_rd__wr_rd__VAL REG_VAL_ENUM
+#define R_MMU_CAUSE__page_id__page_id__VAL REG_VAL_VAL
+
+#define R_MMU_CAUSE__miss_excp__miss_excp__no 0
+#define R_MMU_CAUSE__miss_excp__miss_excp__yes 1
+#define R_MMU_CAUSE__inv_excp__inv_excp__no 0
+#define R_MMU_CAUSE__inv_excp__inv_excp__yes 1
+#define R_MMU_CAUSE__acc_excp__acc_excp__no 0
+#define R_MMU_CAUSE__acc_excp__acc_excp__yes 1
+#define R_MMU_CAUSE__we_excp__we_excp__no 0
+#define R_MMU_CAUSE__we_excp__we_excp__yes 1
+#define R_MMU_CAUSE__wr_rd__wr_rd__read 0
+#define R_MMU_CAUSE__wr_rd__wr_rd__write 1
+
+#endif
+
+/*
+ * R_MMU_CONFIG
+ * - type: WO
+ * - addr: 0xb0000240
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_MMU_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000240)
+
+#ifndef REG_NO_SHADOW
+#define R_MMU_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_CONFIG + 2))
+#define R_MMU_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_CONFIG + 2))
+#else /* REG_NO_SHADOW */
+#define R_MMU_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_MMU_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_MMU_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_MMU_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_MMU_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_MMU_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_MMU_CONFIG__TYPE (REG_UDWORD)
+#define R_MMU_CONFIG__GET REG_GET_WO
+#define R_MMU_CONFIG__IGET REG_IGET_WO
+#define R_MMU_CONFIG__SET REG_SET_WO
+#define R_MMU_CONFIG__ISET REG_ISET_WO
+#define R_MMU_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_MMU_CONFIG__EQL REG_EQL_WO
+#define R_MMU_CONFIG__IEQL REG_IEQL_WO
+#define R_MMU_CONFIG__RD REG_RD_WO
+#define R_MMU_CONFIG__IRD REG_IRD_WO
+#define R_MMU_CONFIG__WR REG_WR_WO
+#define R_MMU_CONFIG__IWR REG_IWR_WO
+
+#define R_MMU_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_MMU_CONFIG__mmu_enable__mmu_enable__MASK 0x80000000U
+#define R_MMU_CONFIG__inv_excp__inv_excp__MASK 0x00040000U
+#define R_MMU_CONFIG__acc_excp__acc_excp__MASK 0x00020000U
+#define R_MMU_CONFIG__we_excp__we_excp__MASK 0x00010000U
+#define R_MMU_CONFIG__seg_f__seg_f__MASK 0x00008000U
+#define R_MMU_CONFIG__seg_e__seg_e__MASK 0x00004000U
+#define R_MMU_CONFIG__seg_d__seg_d__MASK 0x00002000U
+#define R_MMU_CONFIG__seg_c__seg_c__MASK 0x00001000U
+#define R_MMU_CONFIG__seg_b__seg_b__MASK 0x00000800U
+#define R_MMU_CONFIG__seg_a__seg_a__MASK 0x00000400U
+#define R_MMU_CONFIG__seg_9__seg_9__MASK 0x00000200U
+#define R_MMU_CONFIG__seg_8__seg_8__MASK 0x00000100U
+#define R_MMU_CONFIG__seg_7__seg_7__MASK 0x00000080U
+#define R_MMU_CONFIG__seg_6__seg_6__MASK 0x00000040U
+#define R_MMU_CONFIG__seg_5__seg_5__MASK 0x00000020U
+#define R_MMU_CONFIG__seg_4__seg_4__MASK 0x00000010U
+#define R_MMU_CONFIG__seg_3__seg_3__MASK 0x00000008U
+#define R_MMU_CONFIG__seg_2__seg_2__MASK 0x00000004U
+#define R_MMU_CONFIG__seg_1__seg_1__MASK 0x00000002U
+#define R_MMU_CONFIG__seg_0__seg_0__MASK 0x00000001U
+
+#define R_MMU_CONFIG__mmu_enable__MAX 0x1
+#define R_MMU_CONFIG__inv_excp__MAX 0x1
+#define R_MMU_CONFIG__acc_excp__MAX 0x1
+#define R_MMU_CONFIG__we_excp__MAX 0x1
+#define R_MMU_CONFIG__seg_f__MAX 0x1
+#define R_MMU_CONFIG__seg_e__MAX 0x1
+#define R_MMU_CONFIG__seg_d__MAX 0x1
+#define R_MMU_CONFIG__seg_c__MAX 0x1
+#define R_MMU_CONFIG__seg_b__MAX 0x1
+#define R_MMU_CONFIG__seg_a__MAX 0x1
+#define R_MMU_CONFIG__seg_9__MAX 0x1
+#define R_MMU_CONFIG__seg_8__MAX 0x1
+#define R_MMU_CONFIG__seg_7__MAX 0x1
+#define R_MMU_CONFIG__seg_6__MAX 0x1
+#define R_MMU_CONFIG__seg_5__MAX 0x1
+#define R_MMU_CONFIG__seg_4__MAX 0x1
+#define R_MMU_CONFIG__seg_3__MAX 0x1
+#define R_MMU_CONFIG__seg_2__MAX 0x1
+#define R_MMU_CONFIG__seg_1__MAX 0x1
+#define R_MMU_CONFIG__seg_0__MAX 0x1
+
+#define R_MMU_CONFIG__mmu_enable__MIN 0
+#define R_MMU_CONFIG__inv_excp__MIN 0
+#define R_MMU_CONFIG__acc_excp__MIN 0
+#define R_MMU_CONFIG__we_excp__MIN 0
+#define R_MMU_CONFIG__seg_f__MIN 0
+#define R_MMU_CONFIG__seg_e__MIN 0
+#define R_MMU_CONFIG__seg_d__MIN 0
+#define R_MMU_CONFIG__seg_c__MIN 0
+#define R_MMU_CONFIG__seg_b__MIN 0
+#define R_MMU_CONFIG__seg_a__MIN 0
+#define R_MMU_CONFIG__seg_9__MIN 0
+#define R_MMU_CONFIG__seg_8__MIN 0
+#define R_MMU_CONFIG__seg_7__MIN 0
+#define R_MMU_CONFIG__seg_6__MIN 0
+#define R_MMU_CONFIG__seg_5__MIN 0
+#define R_MMU_CONFIG__seg_4__MIN 0
+#define R_MMU_CONFIG__seg_3__MIN 0
+#define R_MMU_CONFIG__seg_2__MIN 0
+#define R_MMU_CONFIG__seg_1__MIN 0
+#define R_MMU_CONFIG__seg_0__MIN 0
+
+#define R_MMU_CONFIG__mmu_enable__BITNR 31
+#define R_MMU_CONFIG__inv_excp__BITNR 18
+#define R_MMU_CONFIG__acc_excp__BITNR 17
+#define R_MMU_CONFIG__we_excp__BITNR 16
+#define R_MMU_CONFIG__seg_f__BITNR 15
+#define R_MMU_CONFIG__seg_e__BITNR 14
+#define R_MMU_CONFIG__seg_d__BITNR 13
+#define R_MMU_CONFIG__seg_c__BITNR 12
+#define R_MMU_CONFIG__seg_b__BITNR 11
+#define R_MMU_CONFIG__seg_a__BITNR 10
+#define R_MMU_CONFIG__seg_9__BITNR 9
+#define R_MMU_CONFIG__seg_8__BITNR 8
+#define R_MMU_CONFIG__seg_7__BITNR 7
+#define R_MMU_CONFIG__seg_6__BITNR 6
+#define R_MMU_CONFIG__seg_5__BITNR 5
+#define R_MMU_CONFIG__seg_4__BITNR 4
+#define R_MMU_CONFIG__seg_3__BITNR 3
+#define R_MMU_CONFIG__seg_2__BITNR 2
+#define R_MMU_CONFIG__seg_1__BITNR 1
+#define R_MMU_CONFIG__seg_0__BITNR 0
+
+#define R_MMU_CONFIG__mmu_enable__mmu_enable__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__inv_excp__inv_excp__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__acc_excp__acc_excp__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__we_excp__we_excp__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_f__seg_f__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_e__seg_e__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_d__seg_d__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_c__seg_c__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_b__seg_b__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_a__seg_a__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_9__seg_9__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_8__seg_8__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_7__seg_7__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_6__seg_6__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_5__seg_5__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_4__seg_4__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_3__seg_3__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_2__seg_2__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_1__seg_1__VAL REG_VAL_ENUM
+#define R_MMU_CONFIG__seg_0__seg_0__VAL REG_VAL_ENUM
+
+#define R_MMU_CONFIG__mmu_enable__mmu_enable__disable 0
+#define R_MMU_CONFIG__mmu_enable__mmu_enable__enable 1
+#define R_MMU_CONFIG__inv_excp__inv_excp__disable 0
+#define R_MMU_CONFIG__inv_excp__inv_excp__enable 1
+#define R_MMU_CONFIG__acc_excp__acc_excp__disable 0
+#define R_MMU_CONFIG__acc_excp__acc_excp__enable 1
+#define R_MMU_CONFIG__we_excp__we_excp__disable 0
+#define R_MMU_CONFIG__we_excp__we_excp__enable 1
+#define R_MMU_CONFIG__seg_f__seg_f__page 0
+#define R_MMU_CONFIG__seg_f__seg_f__seg 1
+#define R_MMU_CONFIG__seg_e__seg_e__page 0
+#define R_MMU_CONFIG__seg_e__seg_e__seg 1
+#define R_MMU_CONFIG__seg_d__seg_d__page 0
+#define R_MMU_CONFIG__seg_d__seg_d__seg 1
+#define R_MMU_CONFIG__seg_c__seg_c__page 0
+#define R_MMU_CONFIG__seg_c__seg_c__seg 1
+#define R_MMU_CONFIG__seg_b__seg_b__page 0
+#define R_MMU_CONFIG__seg_b__seg_b__seg 1
+#define R_MMU_CONFIG__seg_a__seg_a__page 0
+#define R_MMU_CONFIG__seg_a__seg_a__seg 1
+#define R_MMU_CONFIG__seg_9__seg_9__page 0
+#define R_MMU_CONFIG__seg_9__seg_9__seg 1
+#define R_MMU_CONFIG__seg_8__seg_8__page 0
+#define R_MMU_CONFIG__seg_8__seg_8__seg 1
+#define R_MMU_CONFIG__seg_7__seg_7__page 0
+#define R_MMU_CONFIG__seg_7__seg_7__seg 1
+#define R_MMU_CONFIG__seg_6__seg_6__page 0
+#define R_MMU_CONFIG__seg_6__seg_6__seg 1
+#define R_MMU_CONFIG__seg_5__seg_5__page 0
+#define R_MMU_CONFIG__seg_5__seg_5__seg 1
+#define R_MMU_CONFIG__seg_4__seg_4__page 0
+#define R_MMU_CONFIG__seg_4__seg_4__seg 1
+#define R_MMU_CONFIG__seg_3__seg_3__page 0
+#define R_MMU_CONFIG__seg_3__seg_3__seg 1
+#define R_MMU_CONFIG__seg_2__seg_2__page 0
+#define R_MMU_CONFIG__seg_2__seg_2__seg 1
+#define R_MMU_CONFIG__seg_1__seg_1__page 0
+#define R_MMU_CONFIG__seg_1__seg_1__seg 1
+#define R_MMU_CONFIG__seg_0__seg_0__page 0
+#define R_MMU_CONFIG__seg_0__seg_0__seg 1
+
+#endif
+
+/*
+ * R_MMU_CONTEXT
+ * - type: RW
+ * - addr: 0xb000024c
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_MMU_CONTEXT__ADDR (REG_TYPECAST_BYTE 0xb000024c)
+#define R_MMU_CONTEXT__SVAL REG_SVAL_SHADOW
+#define R_MMU_CONTEXT__SVAL_I REG_SVAL_I_SHADOW
+#define R_MMU_CONTEXT__TYPECAST REG_TYPECAST_BYTE
+#define R_MMU_CONTEXT__TYPE (REG_BYTE)
+#define R_MMU_CONTEXT__GET REG_GET_RW
+#define R_MMU_CONTEXT__IGET REG_IGET_RW
+#define R_MMU_CONTEXT__SET REG_SET_RW
+#define R_MMU_CONTEXT__ISET REG_ISET_RW
+#define R_MMU_CONTEXT__SET_VAL REG_SET_VAL_RW
+#define R_MMU_CONTEXT__EQL REG_EQL_RW
+#define R_MMU_CONTEXT__IEQL REG_IEQL_RW
+#define R_MMU_CONTEXT__RD REG_RD_RW
+#define R_MMU_CONTEXT__IRD REG_IRD_RW
+#define R_MMU_CONTEXT__WR REG_WR_RW
+#define R_MMU_CONTEXT__IWR REG_IWR_RW
+
+#define R_MMU_CONTEXT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_MMU_CONTEXT__READ(addr) \
+ (*(addr))
+
+#define R_MMU_CONTEXT__page_id__page_id__MASK 0x0000003fU
+
+#define R_MMU_CONTEXT__page_id__MAX 63
+
+#define R_MMU_CONTEXT__page_id__MIN 0
+
+#define R_MMU_CONTEXT__page_id__BITNR 0
+
+#define R_MMU_CONTEXT__page_id__page_id__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_MMU_CTRL
+ * - type: WO
+ * - addr: 0xb0000242
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_MMU_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000242)
+
+#ifndef REG_NO_SHADOW
+#define R_MMU_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_MMU_CONFIG + 0))
+#define R_MMU_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_MMU_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_MMU_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_MMU_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_MMU_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_MMU_CTRL__SVAL REG_SVAL_SHADOW
+#define R_MMU_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_MMU_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_MMU_CTRL__TYPE (REG_BYTE)
+#define R_MMU_CTRL__GET REG_GET_WO
+#define R_MMU_CTRL__IGET REG_IGET_WO
+#define R_MMU_CTRL__SET REG_SET_WO
+#define R_MMU_CTRL__ISET REG_ISET_WO
+#define R_MMU_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_MMU_CTRL__EQL REG_EQL_WO
+#define R_MMU_CTRL__IEQL REG_IEQL_WO
+#define R_MMU_CTRL__RD REG_RD_WO
+#define R_MMU_CTRL__IRD REG_IRD_WO
+#define R_MMU_CTRL__WR REG_WR_WO
+#define R_MMU_CTRL__IWR REG_IWR_WO
+
+#define R_MMU_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_MMU_CTRL__inv_excp__inv_excp__MASK 0x00000004U
+#define R_MMU_CTRL__acc_excp__acc_excp__MASK 0x00000002U
+#define R_MMU_CTRL__we_excp__we_excp__MASK 0x00000001U
+
+#define R_MMU_CTRL__inv_excp__MAX 0x1
+#define R_MMU_CTRL__acc_excp__MAX 0x1
+#define R_MMU_CTRL__we_excp__MAX 0x1
+
+#define R_MMU_CTRL__inv_excp__MIN 0
+#define R_MMU_CTRL__acc_excp__MIN 0
+#define R_MMU_CTRL__we_excp__MIN 0
+
+#define R_MMU_CTRL__inv_excp__BITNR 2
+#define R_MMU_CTRL__acc_excp__BITNR 1
+#define R_MMU_CTRL__we_excp__BITNR 0
+
+#define R_MMU_CTRL__inv_excp__inv_excp__VAL REG_VAL_ENUM
+#define R_MMU_CTRL__acc_excp__acc_excp__VAL REG_VAL_ENUM
+#define R_MMU_CTRL__we_excp__we_excp__VAL REG_VAL_ENUM
+
+#define R_MMU_CTRL__inv_excp__inv_excp__disable 0
+#define R_MMU_CTRL__inv_excp__inv_excp__enable 1
+#define R_MMU_CTRL__acc_excp__acc_excp__disable 0
+#define R_MMU_CTRL__acc_excp__acc_excp__enable 1
+#define R_MMU_CTRL__we_excp__we_excp__disable 0
+#define R_MMU_CTRL__we_excp__we_excp__enable 1
+
+#endif
+
+/*
+ * R_MMU_ENABLE
+ * - type: WO
+ * - addr: 0xb0000243
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_MMU_ENABLE__ADDR (REG_TYPECAST_BYTE 0xb0000243)
+
+#ifndef REG_NO_SHADOW
+#define R_MMU_ENABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_MMU_CONFIG + 1))
+#define R_MMU_ENABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_MMU_CONFIG + 1))
+#else /* REG_NO_SHADOW */
+#define R_MMU_ENABLE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_MMU_ENABLE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_MMU_ENABLE__STYPECAST REG_STYPECAST_BYTE
+#define R_MMU_ENABLE__SVAL REG_SVAL_SHADOW
+#define R_MMU_ENABLE__SVAL_I REG_SVAL_I_SHADOW
+#define R_MMU_ENABLE__TYPECAST REG_TYPECAST_BYTE
+#define R_MMU_ENABLE__TYPE (REG_BYTE)
+#define R_MMU_ENABLE__GET REG_GET_WO
+#define R_MMU_ENABLE__IGET REG_IGET_WO
+#define R_MMU_ENABLE__SET REG_SET_WO
+#define R_MMU_ENABLE__ISET REG_ISET_WO
+#define R_MMU_ENABLE__SET_VAL REG_SET_VAL_WO
+#define R_MMU_ENABLE__EQL REG_EQL_WO
+#define R_MMU_ENABLE__IEQL REG_IEQL_WO
+#define R_MMU_ENABLE__RD REG_RD_WO
+#define R_MMU_ENABLE__IRD REG_IRD_WO
+#define R_MMU_ENABLE__WR REG_WR_WO
+#define R_MMU_ENABLE__IWR REG_IWR_WO
+
+#define R_MMU_ENABLE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_MMU_ENABLE__mmu_enable__mmu_enable__MASK 0x00000080U
+
+#define R_MMU_ENABLE__mmu_enable__MAX 0x1
+
+#define R_MMU_ENABLE__mmu_enable__MIN 0
+
+#define R_MMU_ENABLE__mmu_enable__BITNR 7
+
+#define R_MMU_ENABLE__mmu_enable__mmu_enable__VAL REG_VAL_ENUM
+
+#define R_MMU_ENABLE__mmu_enable__mmu_enable__disable 0
+#define R_MMU_ENABLE__mmu_enable__mmu_enable__enable 1
+
+#endif
+
+/*
+ * R_MMU_KBASE_HI
+ * - type: WO
+ * - addr: 0xb0000248
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_MMU_KBASE_HI__ADDR (REG_TYPECAST_UDWORD 0xb0000248)
+
+#ifndef REG_NO_SHADOW
+#define R_MMU_KBASE_HI__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_KBASE_HI + 2))
+#define R_MMU_KBASE_HI__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_KBASE_HI + 2))
+#else /* REG_NO_SHADOW */
+#define R_MMU_KBASE_HI__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_MMU_KBASE_HI__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_MMU_KBASE_HI__STYPECAST REG_STYPECAST_UDWORD
+#define R_MMU_KBASE_HI__SVAL REG_SVAL_SHADOW
+#define R_MMU_KBASE_HI__SVAL_I REG_SVAL_I_SHADOW
+#define R_MMU_KBASE_HI__TYPECAST REG_TYPECAST_UDWORD
+#define R_MMU_KBASE_HI__TYPE (REG_UDWORD)
+#define R_MMU_KBASE_HI__GET REG_GET_WO
+#define R_MMU_KBASE_HI__IGET REG_IGET_WO
+#define R_MMU_KBASE_HI__SET REG_SET_WO
+#define R_MMU_KBASE_HI__ISET REG_ISET_WO
+#define R_MMU_KBASE_HI__SET_VAL REG_SET_VAL_WO
+#define R_MMU_KBASE_HI__EQL REG_EQL_WO
+#define R_MMU_KBASE_HI__IEQL REG_IEQL_WO
+#define R_MMU_KBASE_HI__RD REG_RD_WO
+#define R_MMU_KBASE_HI__IRD REG_IRD_WO
+#define R_MMU_KBASE_HI__WR REG_WR_WO
+#define R_MMU_KBASE_HI__IWR REG_IWR_WO
+
+#define R_MMU_KBASE_HI__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_MMU_KBASE_HI__base_f__base_f__MASK 0xf0000000U
+#define R_MMU_KBASE_HI__base_e__base_e__MASK 0x0f000000U
+#define R_MMU_KBASE_HI__base_d__base_d__MASK 0x00f00000U
+#define R_MMU_KBASE_HI__base_c__base_c__MASK 0x000f0000U
+#define R_MMU_KBASE_HI__base_b__base_b__MASK 0x0000f000U
+#define R_MMU_KBASE_HI__base_a__base_a__MASK 0x00000f00U
+#define R_MMU_KBASE_HI__base_9__base_9__MASK 0x000000f0U
+#define R_MMU_KBASE_HI__base_8__base_8__MASK 0x0000000fU
+
+#define R_MMU_KBASE_HI__base_f__MAX 15
+#define R_MMU_KBASE_HI__base_e__MAX 15
+#define R_MMU_KBASE_HI__base_d__MAX 15
+#define R_MMU_KBASE_HI__base_c__MAX 15
+#define R_MMU_KBASE_HI__base_b__MAX 15
+#define R_MMU_KBASE_HI__base_a__MAX 15
+#define R_MMU_KBASE_HI__base_9__MAX 15
+#define R_MMU_KBASE_HI__base_8__MAX 15
+
+#define R_MMU_KBASE_HI__base_f__MIN 0
+#define R_MMU_KBASE_HI__base_e__MIN 0
+#define R_MMU_KBASE_HI__base_d__MIN 0
+#define R_MMU_KBASE_HI__base_c__MIN 0
+#define R_MMU_KBASE_HI__base_b__MIN 0
+#define R_MMU_KBASE_HI__base_a__MIN 0
+#define R_MMU_KBASE_HI__base_9__MIN 0
+#define R_MMU_KBASE_HI__base_8__MIN 0
+
+#define R_MMU_KBASE_HI__base_f__BITNR 28
+#define R_MMU_KBASE_HI__base_e__BITNR 24
+#define R_MMU_KBASE_HI__base_d__BITNR 20
+#define R_MMU_KBASE_HI__base_c__BITNR 16
+#define R_MMU_KBASE_HI__base_b__BITNR 12
+#define R_MMU_KBASE_HI__base_a__BITNR 8
+#define R_MMU_KBASE_HI__base_9__BITNR 4
+#define R_MMU_KBASE_HI__base_8__BITNR 0
+
+#define R_MMU_KBASE_HI__base_f__base_f__VAL REG_VAL_VAL
+#define R_MMU_KBASE_HI__base_e__base_e__VAL REG_VAL_VAL
+#define R_MMU_KBASE_HI__base_d__base_d__VAL REG_VAL_VAL
+#define R_MMU_KBASE_HI__base_c__base_c__VAL REG_VAL_VAL
+#define R_MMU_KBASE_HI__base_b__base_b__VAL REG_VAL_VAL
+#define R_MMU_KBASE_HI__base_a__base_a__VAL REG_VAL_VAL
+#define R_MMU_KBASE_HI__base_9__base_9__VAL REG_VAL_VAL
+#define R_MMU_KBASE_HI__base_8__base_8__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_MMU_KBASE_LO
+ * - type: WO
+ * - addr: 0xb0000244
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_MMU_KBASE_LO__ADDR (REG_TYPECAST_UDWORD 0xb0000244)
+
+#ifndef REG_NO_SHADOW
+#define R_MMU_KBASE_LO__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_MMU_KBASE_LO + 2))
+#define R_MMU_KBASE_LO__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_MMU_KBASE_LO + 2))
+#else /* REG_NO_SHADOW */
+#define R_MMU_KBASE_LO__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_MMU_KBASE_LO__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_MMU_KBASE_LO__STYPECAST REG_STYPECAST_UDWORD
+#define R_MMU_KBASE_LO__SVAL REG_SVAL_SHADOW
+#define R_MMU_KBASE_LO__SVAL_I REG_SVAL_I_SHADOW
+#define R_MMU_KBASE_LO__TYPECAST REG_TYPECAST_UDWORD
+#define R_MMU_KBASE_LO__TYPE (REG_UDWORD)
+#define R_MMU_KBASE_LO__GET REG_GET_WO
+#define R_MMU_KBASE_LO__IGET REG_IGET_WO
+#define R_MMU_KBASE_LO__SET REG_SET_WO
+#define R_MMU_KBASE_LO__ISET REG_ISET_WO
+#define R_MMU_KBASE_LO__SET_VAL REG_SET_VAL_WO
+#define R_MMU_KBASE_LO__EQL REG_EQL_WO
+#define R_MMU_KBASE_LO__IEQL REG_IEQL_WO
+#define R_MMU_KBASE_LO__RD REG_RD_WO
+#define R_MMU_KBASE_LO__IRD REG_IRD_WO
+#define R_MMU_KBASE_LO__WR REG_WR_WO
+#define R_MMU_KBASE_LO__IWR REG_IWR_WO
+
+#define R_MMU_KBASE_LO__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_MMU_KBASE_LO__base_7__base_7__MASK 0xf0000000U
+#define R_MMU_KBASE_LO__base_6__base_6__MASK 0x0f000000U
+#define R_MMU_KBASE_LO__base_5__base_5__MASK 0x00f00000U
+#define R_MMU_KBASE_LO__base_4__base_4__MASK 0x000f0000U
+#define R_MMU_KBASE_LO__base_3__base_3__MASK 0x0000f000U
+#define R_MMU_KBASE_LO__base_2__base_2__MASK 0x00000f00U
+#define R_MMU_KBASE_LO__base_1__base_1__MASK 0x000000f0U
+#define R_MMU_KBASE_LO__base_0__base_0__MASK 0x0000000fU
+
+#define R_MMU_KBASE_LO__base_7__MAX 15
+#define R_MMU_KBASE_LO__base_6__MAX 15
+#define R_MMU_KBASE_LO__base_5__MAX 15
+#define R_MMU_KBASE_LO__base_4__MAX 15
+#define R_MMU_KBASE_LO__base_3__MAX 15
+#define R_MMU_KBASE_LO__base_2__MAX 15
+#define R_MMU_KBASE_LO__base_1__MAX 15
+#define R_MMU_KBASE_LO__base_0__MAX 15
+
+#define R_MMU_KBASE_LO__base_7__MIN 0
+#define R_MMU_KBASE_LO__base_6__MIN 0
+#define R_MMU_KBASE_LO__base_5__MIN 0
+#define R_MMU_KBASE_LO__base_4__MIN 0
+#define R_MMU_KBASE_LO__base_3__MIN 0
+#define R_MMU_KBASE_LO__base_2__MIN 0
+#define R_MMU_KBASE_LO__base_1__MIN 0
+#define R_MMU_KBASE_LO__base_0__MIN 0
+
+#define R_MMU_KBASE_LO__base_7__BITNR 28
+#define R_MMU_KBASE_LO__base_6__BITNR 24
+#define R_MMU_KBASE_LO__base_5__BITNR 20
+#define R_MMU_KBASE_LO__base_4__BITNR 16
+#define R_MMU_KBASE_LO__base_3__BITNR 12
+#define R_MMU_KBASE_LO__base_2__BITNR 8
+#define R_MMU_KBASE_LO__base_1__BITNR 4
+#define R_MMU_KBASE_LO__base_0__BITNR 0
+
+#define R_MMU_KBASE_LO__base_7__base_7__VAL REG_VAL_VAL
+#define R_MMU_KBASE_LO__base_6__base_6__VAL REG_VAL_VAL
+#define R_MMU_KBASE_LO__base_5__base_5__VAL REG_VAL_VAL
+#define R_MMU_KBASE_LO__base_4__base_4__VAL REG_VAL_VAL
+#define R_MMU_KBASE_LO__base_3__base_3__VAL REG_VAL_VAL
+#define R_MMU_KBASE_LO__base_2__base_2__VAL REG_VAL_VAL
+#define R_MMU_KBASE_LO__base_1__base_1__VAL REG_VAL_VAL
+#define R_MMU_KBASE_LO__base_0__base_0__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_MMU_KSEG
+ * - type: WO
+ * - addr: 0xb0000240
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_MMU_KSEG__ADDR (REG_TYPECAST_UWORD 0xb0000240)
+
+#ifndef REG_NO_SHADOW
+#define R_MMU_KSEG__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_MMU_CONFIG + 2))
+#define R_MMU_KSEG__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_MMU_CONFIG + 2))
+#else /* REG_NO_SHADOW */
+#define R_MMU_KSEG__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_MMU_KSEG__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_MMU_KSEG__STYPECAST REG_STYPECAST_UWORD
+#define R_MMU_KSEG__SVAL REG_SVAL_SHADOW
+#define R_MMU_KSEG__SVAL_I REG_SVAL_I_SHADOW
+#define R_MMU_KSEG__TYPECAST REG_TYPECAST_UWORD
+#define R_MMU_KSEG__TYPE (REG_UWORD)
+#define R_MMU_KSEG__GET REG_GET_WO
+#define R_MMU_KSEG__IGET REG_IGET_WO
+#define R_MMU_KSEG__SET REG_SET_WO
+#define R_MMU_KSEG__ISET REG_ISET_WO
+#define R_MMU_KSEG__SET_VAL REG_SET_VAL_WO
+#define R_MMU_KSEG__EQL REG_EQL_WO
+#define R_MMU_KSEG__IEQL REG_IEQL_WO
+#define R_MMU_KSEG__RD REG_RD_WO
+#define R_MMU_KSEG__IRD REG_IRD_WO
+#define R_MMU_KSEG__WR REG_WR_WO
+#define R_MMU_KSEG__IWR REG_IWR_WO
+
+#define R_MMU_KSEG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_MMU_KSEG__seg_f__seg_f__MASK 0x00008000U
+#define R_MMU_KSEG__seg_e__seg_e__MASK 0x00004000U
+#define R_MMU_KSEG__seg_d__seg_d__MASK 0x00002000U
+#define R_MMU_KSEG__seg_c__seg_c__MASK 0x00001000U
+#define R_MMU_KSEG__seg_b__seg_b__MASK 0x00000800U
+#define R_MMU_KSEG__seg_a__seg_a__MASK 0x00000400U
+#define R_MMU_KSEG__seg_9__seg_9__MASK 0x00000200U
+#define R_MMU_KSEG__seg_8__seg_8__MASK 0x00000100U
+#define R_MMU_KSEG__seg_7__seg_7__MASK 0x00000080U
+#define R_MMU_KSEG__seg_6__seg_6__MASK 0x00000040U
+#define R_MMU_KSEG__seg_5__seg_5__MASK 0x00000020U
+#define R_MMU_KSEG__seg_4__seg_4__MASK 0x00000010U
+#define R_MMU_KSEG__seg_3__seg_3__MASK 0x00000008U
+#define R_MMU_KSEG__seg_2__seg_2__MASK 0x00000004U
+#define R_MMU_KSEG__seg_1__seg_1__MASK 0x00000002U
+#define R_MMU_KSEG__seg_0__seg_0__MASK 0x00000001U
+
+#define R_MMU_KSEG__seg_f__MAX 0x1
+#define R_MMU_KSEG__seg_e__MAX 0x1
+#define R_MMU_KSEG__seg_d__MAX 0x1
+#define R_MMU_KSEG__seg_c__MAX 0x1
+#define R_MMU_KSEG__seg_b__MAX 0x1
+#define R_MMU_KSEG__seg_a__MAX 0x1
+#define R_MMU_KSEG__seg_9__MAX 0x1
+#define R_MMU_KSEG__seg_8__MAX 0x1
+#define R_MMU_KSEG__seg_7__MAX 0x1
+#define R_MMU_KSEG__seg_6__MAX 0x1
+#define R_MMU_KSEG__seg_5__MAX 0x1
+#define R_MMU_KSEG__seg_4__MAX 0x1
+#define R_MMU_KSEG__seg_3__MAX 0x1
+#define R_MMU_KSEG__seg_2__MAX 0x1
+#define R_MMU_KSEG__seg_1__MAX 0x1
+#define R_MMU_KSEG__seg_0__MAX 0x1
+
+#define R_MMU_KSEG__seg_f__MIN 0
+#define R_MMU_KSEG__seg_e__MIN 0
+#define R_MMU_KSEG__seg_d__MIN 0
+#define R_MMU_KSEG__seg_c__MIN 0
+#define R_MMU_KSEG__seg_b__MIN 0
+#define R_MMU_KSEG__seg_a__MIN 0
+#define R_MMU_KSEG__seg_9__MIN 0
+#define R_MMU_KSEG__seg_8__MIN 0
+#define R_MMU_KSEG__seg_7__MIN 0
+#define R_MMU_KSEG__seg_6__MIN 0
+#define R_MMU_KSEG__seg_5__MIN 0
+#define R_MMU_KSEG__seg_4__MIN 0
+#define R_MMU_KSEG__seg_3__MIN 0
+#define R_MMU_KSEG__seg_2__MIN 0
+#define R_MMU_KSEG__seg_1__MIN 0
+#define R_MMU_KSEG__seg_0__MIN 0
+
+#define R_MMU_KSEG__seg_f__BITNR 15
+#define R_MMU_KSEG__seg_e__BITNR 14
+#define R_MMU_KSEG__seg_d__BITNR 13
+#define R_MMU_KSEG__seg_c__BITNR 12
+#define R_MMU_KSEG__seg_b__BITNR 11
+#define R_MMU_KSEG__seg_a__BITNR 10
+#define R_MMU_KSEG__seg_9__BITNR 9
+#define R_MMU_KSEG__seg_8__BITNR 8
+#define R_MMU_KSEG__seg_7__BITNR 7
+#define R_MMU_KSEG__seg_6__BITNR 6
+#define R_MMU_KSEG__seg_5__BITNR 5
+#define R_MMU_KSEG__seg_4__BITNR 4
+#define R_MMU_KSEG__seg_3__BITNR 3
+#define R_MMU_KSEG__seg_2__BITNR 2
+#define R_MMU_KSEG__seg_1__BITNR 1
+#define R_MMU_KSEG__seg_0__BITNR 0
+
+#define R_MMU_KSEG__seg_f__seg_f__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_e__seg_e__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_d__seg_d__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_c__seg_c__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_b__seg_b__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_a__seg_a__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_9__seg_9__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_8__seg_8__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_7__seg_7__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_6__seg_6__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_5__seg_5__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_4__seg_4__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_3__seg_3__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_2__seg_2__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_1__seg_1__VAL REG_VAL_ENUM
+#define R_MMU_KSEG__seg_0__seg_0__VAL REG_VAL_ENUM
+
+#define R_MMU_KSEG__seg_f__seg_f__page 0
+#define R_MMU_KSEG__seg_f__seg_f__seg 1
+#define R_MMU_KSEG__seg_e__seg_e__page 0
+#define R_MMU_KSEG__seg_e__seg_e__seg 1
+#define R_MMU_KSEG__seg_d__seg_d__page 0
+#define R_MMU_KSEG__seg_d__seg_d__seg 1
+#define R_MMU_KSEG__seg_c__seg_c__page 0
+#define R_MMU_KSEG__seg_c__seg_c__seg 1
+#define R_MMU_KSEG__seg_b__seg_b__page 0
+#define R_MMU_KSEG__seg_b__seg_b__seg 1
+#define R_MMU_KSEG__seg_a__seg_a__page 0
+#define R_MMU_KSEG__seg_a__seg_a__seg 1
+#define R_MMU_KSEG__seg_9__seg_9__page 0
+#define R_MMU_KSEG__seg_9__seg_9__seg 1
+#define R_MMU_KSEG__seg_8__seg_8__page 0
+#define R_MMU_KSEG__seg_8__seg_8__seg 1
+#define R_MMU_KSEG__seg_7__seg_7__page 0
+#define R_MMU_KSEG__seg_7__seg_7__seg 1
+#define R_MMU_KSEG__seg_6__seg_6__page 0
+#define R_MMU_KSEG__seg_6__seg_6__seg 1
+#define R_MMU_KSEG__seg_5__seg_5__page 0
+#define R_MMU_KSEG__seg_5__seg_5__seg 1
+#define R_MMU_KSEG__seg_4__seg_4__page 0
+#define R_MMU_KSEG__seg_4__seg_4__seg 1
+#define R_MMU_KSEG__seg_3__seg_3__page 0
+#define R_MMU_KSEG__seg_3__seg_3__seg 1
+#define R_MMU_KSEG__seg_2__seg_2__page 0
+#define R_MMU_KSEG__seg_2__seg_2__seg 1
+#define R_MMU_KSEG__seg_1__seg_1__page 0
+#define R_MMU_KSEG__seg_1__seg_1__seg 1
+#define R_MMU_KSEG__seg_0__seg_0__page 0
+#define R_MMU_KSEG__seg_0__seg_0__seg 1
+
+#endif
+
+/*
+ * R_NETWORK_GA_0
+ * - type: WO
+ * - addr: 0xb000008c
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_GA_0__ADDR (REG_TYPECAST_UDWORD 0xb000008c)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_GA_0__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GA_0 + 0))
+#define R_NETWORK_GA_0__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GA_0 + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_GA_0__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_GA_0__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_GA_0__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_GA_0__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_GA_0__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_GA_0__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_GA_0__TYPE (REG_UDWORD)
+#define R_NETWORK_GA_0__GET REG_GET_WO
+#define R_NETWORK_GA_0__IGET REG_IGET_WO
+#define R_NETWORK_GA_0__SET REG_SET_WO
+#define R_NETWORK_GA_0__ISET REG_ISET_WO
+#define R_NETWORK_GA_0__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_GA_0__EQL REG_EQL_WO
+#define R_NETWORK_GA_0__IEQL REG_IEQL_WO
+#define R_NETWORK_GA_0__RD REG_RD_WO
+#define R_NETWORK_GA_0__IRD REG_IRD_WO
+#define R_NETWORK_GA_0__WR REG_WR_WO
+#define R_NETWORK_GA_0__IWR REG_IWR_WO
+
+#define R_NETWORK_GA_0__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_GA_0__ga_low__ga_low__MASK 0xffffffffU
+
+#define R_NETWORK_GA_0__ga_low__MAX 0xffffffff
+
+#define R_NETWORK_GA_0__ga_low__MIN 0
+
+#define R_NETWORK_GA_0__ga_low__BITNR 0
+
+#define R_NETWORK_GA_0__ga_low__ga_low__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_NETWORK_GA_1
+ * - type: WO
+ * - addr: 0xb0000090
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_GA_1__ADDR (REG_TYPECAST_UDWORD 0xb0000090)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_GA_1__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GA_1 + 0))
+#define R_NETWORK_GA_1__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GA_1 + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_GA_1__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_GA_1__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_GA_1__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_GA_1__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_GA_1__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_GA_1__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_GA_1__TYPE (REG_UDWORD)
+#define R_NETWORK_GA_1__GET REG_GET_WO
+#define R_NETWORK_GA_1__IGET REG_IGET_WO
+#define R_NETWORK_GA_1__SET REG_SET_WO
+#define R_NETWORK_GA_1__ISET REG_ISET_WO
+#define R_NETWORK_GA_1__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_GA_1__EQL REG_EQL_WO
+#define R_NETWORK_GA_1__IEQL REG_IEQL_WO
+#define R_NETWORK_GA_1__RD REG_RD_WO
+#define R_NETWORK_GA_1__IRD REG_IRD_WO
+#define R_NETWORK_GA_1__WR REG_WR_WO
+#define R_NETWORK_GA_1__IWR REG_IWR_WO
+
+#define R_NETWORK_GA_1__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_GA_1__ga_high__ga_high__MASK 0xffffffffU
+
+#define R_NETWORK_GA_1__ga_high__MAX 0xffffffff
+
+#define R_NETWORK_GA_1__ga_high__MIN 0
+
+#define R_NETWORK_GA_1__ga_high__BITNR 0
+
+#define R_NETWORK_GA_1__ga_high__ga_high__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_NETWORK_GEN_CONFIG
+ * - type: WO
+ * - addr: 0xb0000098
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_GEN_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000098)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_GEN_CONFIG + 0))
+#define R_NETWORK_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_GEN_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_GEN_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_GEN_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_GEN_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_GEN_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_GEN_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_GEN_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_GEN_CONFIG__TYPE (REG_UDWORD)
+#define R_NETWORK_GEN_CONFIG__GET REG_GET_WO
+#define R_NETWORK_GEN_CONFIG__IGET REG_IGET_WO
+#define R_NETWORK_GEN_CONFIG__SET REG_SET_WO
+#define R_NETWORK_GEN_CONFIG__ISET REG_ISET_WO
+#define R_NETWORK_GEN_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_GEN_CONFIG__EQL REG_EQL_WO
+#define R_NETWORK_GEN_CONFIG__IEQL REG_IEQL_WO
+#define R_NETWORK_GEN_CONFIG__RD REG_RD_WO
+#define R_NETWORK_GEN_CONFIG__IRD REG_IRD_WO
+#define R_NETWORK_GEN_CONFIG__WR REG_WR_WO
+#define R_NETWORK_GEN_CONFIG__IWR REG_IWR_WO
+
+#define R_NETWORK_GEN_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_GEN_CONFIG__loopback__loopback__MASK 0x00000020U
+#define R_NETWORK_GEN_CONFIG__frame__frame__MASK 0x00000010U
+#define R_NETWORK_GEN_CONFIG__vg__vg__MASK 0x00000008U
+#define R_NETWORK_GEN_CONFIG__phy__phy__MASK 0x00000006U
+#define R_NETWORK_GEN_CONFIG__enable__enable__MASK 0x00000001U
+
+#define R_NETWORK_GEN_CONFIG__loopback__MAX 0x1
+#define R_NETWORK_GEN_CONFIG__frame__MAX 0x1
+#define R_NETWORK_GEN_CONFIG__vg__MAX 0x1
+#define R_NETWORK_GEN_CONFIG__phy__MAX 0x3
+#define R_NETWORK_GEN_CONFIG__enable__MAX 0x1
+
+#define R_NETWORK_GEN_CONFIG__loopback__MIN 0
+#define R_NETWORK_GEN_CONFIG__frame__MIN 0
+#define R_NETWORK_GEN_CONFIG__vg__MIN 0
+#define R_NETWORK_GEN_CONFIG__phy__MIN 0
+#define R_NETWORK_GEN_CONFIG__enable__MIN 0
+
+#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5
+#define R_NETWORK_GEN_CONFIG__frame__BITNR 4
+#define R_NETWORK_GEN_CONFIG__vg__BITNR 3
+#define R_NETWORK_GEN_CONFIG__phy__BITNR 1
+#define R_NETWORK_GEN_CONFIG__enable__BITNR 0
+
+#define R_NETWORK_GEN_CONFIG__loopback__loopback__VAL REG_VAL_ENUM
+#define R_NETWORK_GEN_CONFIG__frame__frame__VAL REG_VAL_ENUM
+#define R_NETWORK_GEN_CONFIG__vg__vg__VAL REG_VAL_ENUM
+#define R_NETWORK_GEN_CONFIG__phy__phy__VAL REG_VAL_ENUM
+#define R_NETWORK_GEN_CONFIG__enable__enable__VAL REG_VAL_ENUM
+
+#define R_NETWORK_GEN_CONFIG__loopback__loopback__off 0
+#define R_NETWORK_GEN_CONFIG__loopback__loopback__on 1
+#define R_NETWORK_GEN_CONFIG__frame__frame__ether 0
+#define R_NETWORK_GEN_CONFIG__frame__frame__tokenr 1
+#define R_NETWORK_GEN_CONFIG__vg__vg__off 0
+#define R_NETWORK_GEN_CONFIG__vg__vg__on 1
+#define R_NETWORK_GEN_CONFIG__phy__phy__mii_clk 1
+#define R_NETWORK_GEN_CONFIG__phy__phy__mii_err 2
+#define R_NETWORK_GEN_CONFIG__phy__phy__mii_req 3
+#define R_NETWORK_GEN_CONFIG__phy__phy__sni 0
+#define R_NETWORK_GEN_CONFIG__enable__enable__off 0
+#define R_NETWORK_GEN_CONFIG__enable__enable__on 1
+
+#endif
+
+/*
+ * R_NETWORK_MGM_CTRL
+ * - type: WO
+ * - addr: 0xb00000a0
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_MGM_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb00000a0)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_MGM_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_MGM_CTRL + 0))
+#define R_NETWORK_MGM_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_MGM_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_MGM_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_MGM_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_MGM_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_MGM_CTRL__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_MGM_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_MGM_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_MGM_CTRL__TYPE (REG_UDWORD)
+#define R_NETWORK_MGM_CTRL__GET REG_GET_WO
+#define R_NETWORK_MGM_CTRL__IGET REG_IGET_WO
+#define R_NETWORK_MGM_CTRL__SET REG_SET_WO
+#define R_NETWORK_MGM_CTRL__ISET REG_ISET_WO
+#define R_NETWORK_MGM_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_MGM_CTRL__EQL REG_EQL_WO
+#define R_NETWORK_MGM_CTRL__IEQL REG_IEQL_WO
+#define R_NETWORK_MGM_CTRL__RD REG_RD_WO
+#define R_NETWORK_MGM_CTRL__IRD REG_IRD_WO
+#define R_NETWORK_MGM_CTRL__WR REG_WR_WO
+#define R_NETWORK_MGM_CTRL__IWR REG_IWR_WO
+
+#define R_NETWORK_MGM_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_MGM_CTRL__txd_pins__txd_pins__MASK 0x000000f0U
+#define R_NETWORK_MGM_CTRL__txer_pin__txer_pin__MASK 0x00000008U
+#define R_NETWORK_MGM_CTRL__mdck__mdck__MASK 0x00000004U
+#define R_NETWORK_MGM_CTRL__mdoe__mdoe__MASK 0x00000002U
+#define R_NETWORK_MGM_CTRL__mdio__mdio__MASK 0x00000001U
+
+#define R_NETWORK_MGM_CTRL__txd_pins__MAX 0xf
+#define R_NETWORK_MGM_CTRL__txer_pin__MAX 0x1
+#define R_NETWORK_MGM_CTRL__mdck__MAX 0x1
+#define R_NETWORK_MGM_CTRL__mdoe__MAX 0x1
+#define R_NETWORK_MGM_CTRL__mdio__MAX 0x1
+
+#define R_NETWORK_MGM_CTRL__txd_pins__MIN 0
+#define R_NETWORK_MGM_CTRL__txer_pin__MIN 0
+#define R_NETWORK_MGM_CTRL__mdck__MIN 0
+#define R_NETWORK_MGM_CTRL__mdoe__MIN 0
+#define R_NETWORK_MGM_CTRL__mdio__MIN 0
+
+#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4
+#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3
+#define R_NETWORK_MGM_CTRL__mdck__BITNR 2
+#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1
+#define R_NETWORK_MGM_CTRL__mdio__BITNR 0
+
+#define R_NETWORK_MGM_CTRL__txd_pins__txd_pins__VAL REG_VAL_VAL
+#define R_NETWORK_MGM_CTRL__txer_pin__txer_pin__VAL REG_VAL_VAL
+#define R_NETWORK_MGM_CTRL__mdck__mdck__VAL REG_VAL_VAL
+#define R_NETWORK_MGM_CTRL__mdoe__mdoe__VAL REG_VAL_ENUM
+#define R_NETWORK_MGM_CTRL__mdio__mdio__VAL REG_VAL_VAL
+
+#define R_NETWORK_MGM_CTRL__mdoe__mdoe__disable 0
+#define R_NETWORK_MGM_CTRL__mdoe__mdoe__enable 1
+
+#endif
+
+/*
+ * R_NETWORK_REC_CONFIG
+ * - type: WO
+ * - addr: 0xb0000094
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_REC_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000094)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_REC_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_REC_CONFIG + 0))
+#define R_NETWORK_REC_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_REC_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_REC_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_REC_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_REC_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_REC_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_REC_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_REC_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_REC_CONFIG__TYPE (REG_UDWORD)
+#define R_NETWORK_REC_CONFIG__GET REG_GET_WO
+#define R_NETWORK_REC_CONFIG__IGET REG_IGET_WO
+#define R_NETWORK_REC_CONFIG__SET REG_SET_WO
+#define R_NETWORK_REC_CONFIG__ISET REG_ISET_WO
+#define R_NETWORK_REC_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_REC_CONFIG__EQL REG_EQL_WO
+#define R_NETWORK_REC_CONFIG__IEQL REG_IEQL_WO
+#define R_NETWORK_REC_CONFIG__RD REG_RD_WO
+#define R_NETWORK_REC_CONFIG__IRD REG_IRD_WO
+#define R_NETWORK_REC_CONFIG__WR REG_WR_WO
+#define R_NETWORK_REC_CONFIG__IWR REG_IWR_WO
+
+#define R_NETWORK_REC_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_REC_CONFIG__max_size__max_size__MASK 0x00000400U
+#define R_NETWORK_REC_CONFIG__duplex__duplex__MASK 0x00000200U
+#define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__MASK 0x00000100U
+#define R_NETWORK_REC_CONFIG__oversize__oversize__MASK 0x00000080U
+#define R_NETWORK_REC_CONFIG__undersize__undersize__MASK 0x00000040U
+#define R_NETWORK_REC_CONFIG__all_roots__all_roots__MASK 0x00000020U
+#define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__MASK 0x00000010U
+#define R_NETWORK_REC_CONFIG__broadcast__broadcast__MASK 0x00000008U
+#define R_NETWORK_REC_CONFIG__individual__individual__MASK 0x00000004U
+#define R_NETWORK_REC_CONFIG__ma1__ma1__MASK 0x00000002U
+#define R_NETWORK_REC_CONFIG__ma0__ma0__MASK 0x00000001U
+
+#define R_NETWORK_REC_CONFIG__max_size__MAX 0x1
+#define R_NETWORK_REC_CONFIG__duplex__MAX 0x1
+#define R_NETWORK_REC_CONFIG__bad_crc__MAX 0x1
+#define R_NETWORK_REC_CONFIG__oversize__MAX 0x1
+#define R_NETWORK_REC_CONFIG__undersize__MAX 0x1
+#define R_NETWORK_REC_CONFIG__all_roots__MAX 0x1
+#define R_NETWORK_REC_CONFIG__tr_broadcast__MAX 0x1
+#define R_NETWORK_REC_CONFIG__broadcast__MAX 0x1
+#define R_NETWORK_REC_CONFIG__individual__MAX 0x1
+#define R_NETWORK_REC_CONFIG__ma1__MAX 0x1
+#define R_NETWORK_REC_CONFIG__ma0__MAX 0x1
+
+#define R_NETWORK_REC_CONFIG__max_size__MIN 0
+#define R_NETWORK_REC_CONFIG__duplex__MIN 0
+#define R_NETWORK_REC_CONFIG__bad_crc__MIN 0
+#define R_NETWORK_REC_CONFIG__oversize__MIN 0
+#define R_NETWORK_REC_CONFIG__undersize__MIN 0
+#define R_NETWORK_REC_CONFIG__all_roots__MIN 0
+#define R_NETWORK_REC_CONFIG__tr_broadcast__MIN 0
+#define R_NETWORK_REC_CONFIG__broadcast__MIN 0
+#define R_NETWORK_REC_CONFIG__individual__MIN 0
+#define R_NETWORK_REC_CONFIG__ma1__MIN 0
+#define R_NETWORK_REC_CONFIG__ma0__MIN 0
+
+#define R_NETWORK_REC_CONFIG__max_size__BITNR 10
+#define R_NETWORK_REC_CONFIG__duplex__BITNR 9
+#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8
+#define R_NETWORK_REC_CONFIG__oversize__BITNR 7
+#define R_NETWORK_REC_CONFIG__undersize__BITNR 6
+#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5
+#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4
+#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3
+#define R_NETWORK_REC_CONFIG__individual__BITNR 2
+#define R_NETWORK_REC_CONFIG__ma1__BITNR 1
+#define R_NETWORK_REC_CONFIG__ma0__BITNR 0
+
+#define R_NETWORK_REC_CONFIG__max_size__max_size__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__duplex__duplex__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__oversize__oversize__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__undersize__undersize__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__all_roots__all_roots__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__broadcast__broadcast__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__individual__individual__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__ma1__ma1__VAL REG_VAL_ENUM
+#define R_NETWORK_REC_CONFIG__ma0__ma0__VAL REG_VAL_ENUM
+
+#define R_NETWORK_REC_CONFIG__max_size__max_size__size1518 0
+#define R_NETWORK_REC_CONFIG__max_size__max_size__size1522 1
+#define R_NETWORK_REC_CONFIG__duplex__duplex__full 1
+#define R_NETWORK_REC_CONFIG__duplex__duplex__half 0
+#define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__discard 0
+#define R_NETWORK_REC_CONFIG__bad_crc__bad_crc__receive 1
+#define R_NETWORK_REC_CONFIG__oversize__oversize__discard 0
+#define R_NETWORK_REC_CONFIG__oversize__oversize__receive 1
+#define R_NETWORK_REC_CONFIG__undersize__undersize__discard 0
+#define R_NETWORK_REC_CONFIG__undersize__undersize__receive 1
+#define R_NETWORK_REC_CONFIG__all_roots__all_roots__discard 0
+#define R_NETWORK_REC_CONFIG__all_roots__all_roots__receive 1
+#define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__discard 0
+#define R_NETWORK_REC_CONFIG__tr_broadcast__tr_broadcast__receive 1
+#define R_NETWORK_REC_CONFIG__broadcast__broadcast__discard 0
+#define R_NETWORK_REC_CONFIG__broadcast__broadcast__receive 1
+#define R_NETWORK_REC_CONFIG__individual__individual__discard 0
+#define R_NETWORK_REC_CONFIG__individual__individual__receive 1
+#define R_NETWORK_REC_CONFIG__ma1__ma1__disable 0
+#define R_NETWORK_REC_CONFIG__ma1__ma1__enable 1
+#define R_NETWORK_REC_CONFIG__ma0__ma0__disable 0
+#define R_NETWORK_REC_CONFIG__ma0__ma0__enable 1
+
+#endif
+
+/*
+ * R_NETWORK_SA_0
+ * - type: WO
+ * - addr: 0xb0000080
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_SA_0__ADDR (REG_TYPECAST_UDWORD 0xb0000080)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_SA_0__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_0 + 0))
+#define R_NETWORK_SA_0__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_0 + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_SA_0__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_SA_0__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_SA_0__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_SA_0__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_SA_0__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_SA_0__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_SA_0__TYPE (REG_UDWORD)
+#define R_NETWORK_SA_0__GET REG_GET_WO
+#define R_NETWORK_SA_0__IGET REG_IGET_WO
+#define R_NETWORK_SA_0__SET REG_SET_WO
+#define R_NETWORK_SA_0__ISET REG_ISET_WO
+#define R_NETWORK_SA_0__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_SA_0__EQL REG_EQL_WO
+#define R_NETWORK_SA_0__IEQL REG_IEQL_WO
+#define R_NETWORK_SA_0__RD REG_RD_WO
+#define R_NETWORK_SA_0__IRD REG_IRD_WO
+#define R_NETWORK_SA_0__WR REG_WR_WO
+#define R_NETWORK_SA_0__IWR REG_IWR_WO
+
+#define R_NETWORK_SA_0__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_SA_0__ma0_low__ma0_low__MASK 0xffffffffU
+
+#define R_NETWORK_SA_0__ma0_low__MAX 0xffffffff
+
+#define R_NETWORK_SA_0__ma0_low__MIN 0
+
+#define R_NETWORK_SA_0__ma0_low__BITNR 0
+
+#define R_NETWORK_SA_0__ma0_low__ma0_low__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_NETWORK_SA_1
+ * - type: WO
+ * - addr: 0xb0000084
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_SA_1__ADDR (REG_TYPECAST_UDWORD 0xb0000084)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_SA_1__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_1 + 0))
+#define R_NETWORK_SA_1__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_1 + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_SA_1__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_SA_1__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_SA_1__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_SA_1__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_SA_1__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_SA_1__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_SA_1__TYPE (REG_UDWORD)
+#define R_NETWORK_SA_1__GET REG_GET_WO
+#define R_NETWORK_SA_1__IGET REG_IGET_WO
+#define R_NETWORK_SA_1__SET REG_SET_WO
+#define R_NETWORK_SA_1__ISET REG_ISET_WO
+#define R_NETWORK_SA_1__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_SA_1__EQL REG_EQL_WO
+#define R_NETWORK_SA_1__IEQL REG_IEQL_WO
+#define R_NETWORK_SA_1__RD REG_RD_WO
+#define R_NETWORK_SA_1__IRD REG_IRD_WO
+#define R_NETWORK_SA_1__WR REG_WR_WO
+#define R_NETWORK_SA_1__IWR REG_IWR_WO
+
+#define R_NETWORK_SA_1__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_SA_1__ma1_low__ma1_low__MASK 0xffff0000U
+#define R_NETWORK_SA_1__ma0_high__ma0_high__MASK 0x0000ffffU
+
+#define R_NETWORK_SA_1__ma1_low__MAX 0xffff
+#define R_NETWORK_SA_1__ma0_high__MAX 0xffff
+
+#define R_NETWORK_SA_1__ma1_low__MIN 0
+#define R_NETWORK_SA_1__ma0_high__MIN 0
+
+#define R_NETWORK_SA_1__ma1_low__BITNR 16
+#define R_NETWORK_SA_1__ma0_high__BITNR 0
+
+#define R_NETWORK_SA_1__ma1_low__ma1_low__VAL REG_VAL_VAL
+#define R_NETWORK_SA_1__ma0_high__ma0_high__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_NETWORK_SA_2
+ * - type: WO
+ * - addr: 0xb0000088
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_SA_2__ADDR (REG_TYPECAST_UDWORD 0xb0000088)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_SA_2__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_SA_2 + 0))
+#define R_NETWORK_SA_2__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_SA_2 + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_SA_2__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_SA_2__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_SA_2__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_SA_2__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_SA_2__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_SA_2__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_SA_2__TYPE (REG_UDWORD)
+#define R_NETWORK_SA_2__GET REG_GET_WO
+#define R_NETWORK_SA_2__IGET REG_IGET_WO
+#define R_NETWORK_SA_2__SET REG_SET_WO
+#define R_NETWORK_SA_2__ISET REG_ISET_WO
+#define R_NETWORK_SA_2__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_SA_2__EQL REG_EQL_WO
+#define R_NETWORK_SA_2__IEQL REG_IEQL_WO
+#define R_NETWORK_SA_2__RD REG_RD_WO
+#define R_NETWORK_SA_2__IRD REG_IRD_WO
+#define R_NETWORK_SA_2__WR REG_WR_WO
+#define R_NETWORK_SA_2__IWR REG_IWR_WO
+
+#define R_NETWORK_SA_2__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_SA_2__ma1_high__ma1_high__MASK 0xffffffffU
+
+#define R_NETWORK_SA_2__ma1_high__MAX 0xffffffff
+
+#define R_NETWORK_SA_2__ma1_high__MIN 0
+
+#define R_NETWORK_SA_2__ma1_high__BITNR 0
+
+#define R_NETWORK_SA_2__ma1_high__ma1_high__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_NETWORK_STAT
+ * - type: RO
+ * - addr: 0xb00000a0
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_STAT__ADDR (REG_TYPECAST_UDWORD 0xb00000a0)
+#define R_NETWORK_STAT__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_STAT__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_STAT__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_STAT__TYPE (REG_UDWORD)
+#define R_NETWORK_STAT__GET REG_GET_RO
+#define R_NETWORK_STAT__IGET REG_IGET_RO
+#define R_NETWORK_STAT__SET REG_SET_RO
+#define R_NETWORK_STAT__ISET REG_ISET_RO
+#define R_NETWORK_STAT__SET_VAL REG_SET_VAL_RO
+#define R_NETWORK_STAT__EQL REG_EQL_RO
+#define R_NETWORK_STAT__IEQL REG_IEQL_RO
+#define R_NETWORK_STAT__RD REG_RD_RO
+#define R_NETWORK_STAT__IRD REG_IRD_RO
+#define R_NETWORK_STAT__WR REG_WR_RO
+#define R_NETWORK_STAT__IWR REG_IWR_RO
+
+#define R_NETWORK_STAT__READ(addr) \
+ (*(addr))
+
+#define R_NETWORK_STAT__rxd_pins__rxd_pins__MASK 0x000000f0U
+#define R_NETWORK_STAT__rxer__rxer__MASK 0x00000008U
+#define R_NETWORK_STAT__underrun__underrun__MASK 0x00000004U
+#define R_NETWORK_STAT__exc_col__exc_col__MASK 0x00000002U
+#define R_NETWORK_STAT__mdio__mdio__MASK 0x00000001U
+
+#define R_NETWORK_STAT__rxd_pins__MAX 0xf
+#define R_NETWORK_STAT__rxer__MAX 0x1
+#define R_NETWORK_STAT__underrun__MAX 0x1
+#define R_NETWORK_STAT__exc_col__MAX 0x1
+#define R_NETWORK_STAT__mdio__MAX 0x1
+
+#define R_NETWORK_STAT__rxd_pins__MIN 0
+#define R_NETWORK_STAT__rxer__MIN 0
+#define R_NETWORK_STAT__underrun__MIN 0
+#define R_NETWORK_STAT__exc_col__MIN 0
+#define R_NETWORK_STAT__mdio__MIN 0
+
+#define R_NETWORK_STAT__rxd_pins__BITNR 4
+#define R_NETWORK_STAT__rxer__BITNR 3
+#define R_NETWORK_STAT__underrun__BITNR 2
+#define R_NETWORK_STAT__exc_col__BITNR 1
+#define R_NETWORK_STAT__mdio__BITNR 0
+
+#define R_NETWORK_STAT__rxd_pins__rxd_pins__VAL REG_VAL_VAL
+#define R_NETWORK_STAT__rxer__rxer__VAL REG_VAL_VAL
+#define R_NETWORK_STAT__underrun__underrun__VAL REG_VAL_ENUM
+#define R_NETWORK_STAT__exc_col__exc_col__VAL REG_VAL_ENUM
+#define R_NETWORK_STAT__mdio__mdio__VAL REG_VAL_VAL
+
+#define R_NETWORK_STAT__underrun__underrun__no 0
+#define R_NETWORK_STAT__underrun__underrun__yes 1
+#define R_NETWORK_STAT__exc_col__exc_col__no 0
+#define R_NETWORK_STAT__exc_col__exc_col__yes 1
+
+#endif
+
+/*
+ * R_NETWORK_TR_CTRL
+ * - type: WO
+ * - addr: 0xb000009c
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_NETWORK_TR_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb000009c)
+
+#ifndef REG_NO_SHADOW
+#define R_NETWORK_TR_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_NETWORK_TR_CTRL + 0))
+#define R_NETWORK_TR_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_NETWORK_TR_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_NETWORK_TR_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_NETWORK_TR_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_NETWORK_TR_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_NETWORK_TR_CTRL__SVAL REG_SVAL_SHADOW
+#define R_NETWORK_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_NETWORK_TR_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_NETWORK_TR_CTRL__TYPE (REG_UDWORD)
+#define R_NETWORK_TR_CTRL__GET REG_GET_WO
+#define R_NETWORK_TR_CTRL__IGET REG_IGET_WO
+#define R_NETWORK_TR_CTRL__SET REG_SET_WO
+#define R_NETWORK_TR_CTRL__ISET REG_ISET_WO
+#define R_NETWORK_TR_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_NETWORK_TR_CTRL__EQL REG_EQL_WO
+#define R_NETWORK_TR_CTRL__IEQL REG_IEQL_WO
+#define R_NETWORK_TR_CTRL__RD REG_RD_WO
+#define R_NETWORK_TR_CTRL__IRD REG_IRD_WO
+#define R_NETWORK_TR_CTRL__WR REG_WR_WO
+#define R_NETWORK_TR_CTRL__IWR REG_IWR_WO
+
+#define R_NETWORK_TR_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_NETWORK_TR_CTRL__clr_error__clr_error__MASK 0x00000100U
+#define R_NETWORK_TR_CTRL__delay__delay__MASK 0x00000020U
+#define R_NETWORK_TR_CTRL__cancel__cancel__MASK 0x00000010U
+#define R_NETWORK_TR_CTRL__cd__cd__MASK 0x00000008U
+#define R_NETWORK_TR_CTRL__retry__retry__MASK 0x00000004U
+#define R_NETWORK_TR_CTRL__pad__pad__MASK 0x00000002U
+#define R_NETWORK_TR_CTRL__crc__crc__MASK 0x00000001U
+
+#define R_NETWORK_TR_CTRL__clr_error__MAX 0x1
+#define R_NETWORK_TR_CTRL__delay__MAX 0x1
+#define R_NETWORK_TR_CTRL__cancel__MAX 0x1
+#define R_NETWORK_TR_CTRL__cd__MAX 0x1
+#define R_NETWORK_TR_CTRL__retry__MAX 0x1
+#define R_NETWORK_TR_CTRL__pad__MAX 0x1
+#define R_NETWORK_TR_CTRL__crc__MAX 0x1
+
+#define R_NETWORK_TR_CTRL__clr_error__MIN 0
+#define R_NETWORK_TR_CTRL__delay__MIN 0
+#define R_NETWORK_TR_CTRL__cancel__MIN 0
+#define R_NETWORK_TR_CTRL__cd__MIN 0
+#define R_NETWORK_TR_CTRL__retry__MIN 0
+#define R_NETWORK_TR_CTRL__pad__MIN 0
+#define R_NETWORK_TR_CTRL__crc__MIN 0
+
+#define R_NETWORK_TR_CTRL__clr_error__BITNR 8
+#define R_NETWORK_TR_CTRL__delay__BITNR 5
+#define R_NETWORK_TR_CTRL__cancel__BITNR 4
+#define R_NETWORK_TR_CTRL__cd__BITNR 3
+#define R_NETWORK_TR_CTRL__retry__BITNR 2
+#define R_NETWORK_TR_CTRL__pad__BITNR 1
+#define R_NETWORK_TR_CTRL__crc__BITNR 0
+
+#define R_NETWORK_TR_CTRL__clr_error__clr_error__VAL REG_VAL_ENUM
+#define R_NETWORK_TR_CTRL__delay__delay__VAL REG_VAL_ENUM
+#define R_NETWORK_TR_CTRL__cancel__cancel__VAL REG_VAL_ENUM
+#define R_NETWORK_TR_CTRL__cd__cd__VAL REG_VAL_ENUM
+#define R_NETWORK_TR_CTRL__retry__retry__VAL REG_VAL_ENUM
+#define R_NETWORK_TR_CTRL__pad__pad__VAL REG_VAL_ENUM
+#define R_NETWORK_TR_CTRL__crc__crc__VAL REG_VAL_ENUM
+
+#define R_NETWORK_TR_CTRL__clr_error__clr_error__clr 1
+#define R_NETWORK_TR_CTRL__clr_error__clr_error__nop 0
+#define R_NETWORK_TR_CTRL__delay__delay__d2us 1
+#define R_NETWORK_TR_CTRL__delay__delay__none 0
+#define R_NETWORK_TR_CTRL__cancel__cancel__do 1
+#define R_NETWORK_TR_CTRL__cancel__cancel__dont 0
+#define R_NETWORK_TR_CTRL__cd__cd__ack_col 0
+#define R_NETWORK_TR_CTRL__cd__cd__ack_crs 1
+#define R_NETWORK_TR_CTRL__cd__cd__disable 1
+#define R_NETWORK_TR_CTRL__cd__cd__enable 0
+#define R_NETWORK_TR_CTRL__retry__retry__disable 1
+#define R_NETWORK_TR_CTRL__retry__retry__enable 0
+#define R_NETWORK_TR_CTRL__pad__pad__disable 0
+#define R_NETWORK_TR_CTRL__pad__pad__enable 1
+#define R_NETWORK_TR_CTRL__crc__crc__disable 1
+#define R_NETWORK_TR_CTRL__crc__crc__enable 0
+
+#endif
+
+/*
+ * R_PAR0_CONFIG
+ * - type: WO
+ * - addr: 0xb0000044
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR0_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000044)
+
+#ifndef REG_NO_SHADOW
+#define R_PAR0_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0))
+#define R_PAR0_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_PAR0_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_PAR0_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PAR0_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_PAR0_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_PAR0_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR0_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_PAR0_CONFIG__TYPE (REG_UDWORD)
+#define R_PAR0_CONFIG__GET REG_GET_WO
+#define R_PAR0_CONFIG__IGET REG_IGET_WO
+#define R_PAR0_CONFIG__SET REG_SET_WO
+#define R_PAR0_CONFIG__ISET REG_ISET_WO
+#define R_PAR0_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_PAR0_CONFIG__EQL REG_EQL_WO
+#define R_PAR0_CONFIG__IEQL REG_IEQL_WO
+#define R_PAR0_CONFIG__RD REG_RD_WO
+#define R_PAR0_CONFIG__IRD REG_IRD_WO
+#define R_PAR0_CONFIG__WR REG_WR_WO
+#define R_PAR0_CONFIG__IWR REG_IWR_WO
+
+#define R_PAR0_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_PAR0_CONFIG__FIRST 0
+#define R_PAR0_CONFIG__IOFFSET 12
+#define R_PAR0_CONFIG__LAST 1
+#define R_PAR0_CONFIG__OFFSET 16
+#define R_PAR0_CONFIG__SOFFSET 12
+/* end */
+
+#define R_PAR0_CONFIG__ioe__ioe__MASK 0x02000000U
+#define R_PAR0_CONFIG__iseli__iseli__MASK 0x01000000U
+#define R_PAR0_CONFIG__iautofd__iautofd__MASK 0x00800000U
+#define R_PAR0_CONFIG__istrb__istrb__MASK 0x00400000U
+#define R_PAR0_CONFIG__iinit__iinit__MASK 0x00200000U
+#define R_PAR0_CONFIG__iperr__iperr__MASK 0x00100000U
+#define R_PAR0_CONFIG__iack__iack__MASK 0x00080000U
+#define R_PAR0_CONFIG__ibusy__ibusy__MASK 0x00040000U
+#define R_PAR0_CONFIG__ifault__ifault__MASK 0x00020000U
+#define R_PAR0_CONFIG__isel__isel__MASK 0x00010000U
+#define R_PAR0_CONFIG__ext_mode__ext_mode__MASK 0x00000800U
+#define R_PAR0_CONFIG__wide__wide__MASK 0x00000400U
+#define R_PAR0_CONFIG__dma__dma__MASK 0x00000200U
+#define R_PAR0_CONFIG__rle_in__rle_in__MASK 0x00000100U
+#define R_PAR0_CONFIG__rle_out__rle_out__MASK 0x00000080U
+#define R_PAR0_CONFIG__enable__enable__MASK 0x00000040U
+#define R_PAR0_CONFIG__force__force__MASK 0x00000020U
+#define R_PAR0_CONFIG__ign_ack__ign_ack__MASK 0x00000010U
+#define R_PAR0_CONFIG__oe_ack__oe_ack__MASK 0x00000008U
+#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__MASK 0x00000008U
+#define R_PAR0_CONFIG__oe_ack__epp_addr_data__MASK 0x00000008U
+#define R_PAR0_CONFIG__mode__mode__MASK 0x00000007U
+
+#define R_PAR0_CONFIG__ioe__MAX 0x1
+#define R_PAR0_CONFIG__iseli__MAX 0x1
+#define R_PAR0_CONFIG__iautofd__MAX 0x1
+#define R_PAR0_CONFIG__istrb__MAX 0x1
+#define R_PAR0_CONFIG__iinit__MAX 0x1
+#define R_PAR0_CONFIG__iperr__MAX 0x1
+#define R_PAR0_CONFIG__iack__MAX 0x1
+#define R_PAR0_CONFIG__ibusy__MAX 0x1
+#define R_PAR0_CONFIG__ifault__MAX 0x1
+#define R_PAR0_CONFIG__isel__MAX 0x1
+#define R_PAR0_CONFIG__ext_mode__MAX 0x1
+#define R_PAR0_CONFIG__wide__MAX 0x1
+#define R_PAR0_CONFIG__dma__MAX 0x1
+#define R_PAR0_CONFIG__rle_in__MAX 0x1
+#define R_PAR0_CONFIG__rle_out__MAX 0x1
+#define R_PAR0_CONFIG__enable__MAX 0x1
+#define R_PAR0_CONFIG__force__MAX 0x1
+#define R_PAR0_CONFIG__ign_ack__MAX 0x1
+#define R_PAR0_CONFIG__oe_ack__MAX 0x1
+#define R_PAR0_CONFIG__epp_addr_data__MAX 0x1
+#define R_PAR0_CONFIG__mode__MAX 0x7
+
+#define R_PAR0_CONFIG__ioe__MIN 0
+#define R_PAR0_CONFIG__iseli__MIN 0
+#define R_PAR0_CONFIG__iautofd__MIN 0
+#define R_PAR0_CONFIG__istrb__MIN 0
+#define R_PAR0_CONFIG__iinit__MIN 0
+#define R_PAR0_CONFIG__iperr__MIN 0
+#define R_PAR0_CONFIG__iack__MIN 0
+#define R_PAR0_CONFIG__ibusy__MIN 0
+#define R_PAR0_CONFIG__ifault__MIN 0
+#define R_PAR0_CONFIG__isel__MIN 0
+#define R_PAR0_CONFIG__ext_mode__MIN 0
+#define R_PAR0_CONFIG__wide__MIN 0
+#define R_PAR0_CONFIG__dma__MIN 0
+#define R_PAR0_CONFIG__rle_in__MIN 0
+#define R_PAR0_CONFIG__rle_out__MIN 0
+#define R_PAR0_CONFIG__enable__MIN 0
+#define R_PAR0_CONFIG__force__MIN 0
+#define R_PAR0_CONFIG__ign_ack__MIN 0
+#define R_PAR0_CONFIG__oe_ack__MIN 0
+#define R_PAR0_CONFIG__epp_addr_data__MIN 0
+#define R_PAR0_CONFIG__mode__MIN 0
+
+#define R_PAR0_CONFIG__ioe__BITNR 25
+#define R_PAR0_CONFIG__iseli__BITNR 24
+#define R_PAR0_CONFIG__iautofd__BITNR 23
+#define R_PAR0_CONFIG__istrb__BITNR 22
+#define R_PAR0_CONFIG__iinit__BITNR 21
+#define R_PAR0_CONFIG__iperr__BITNR 20
+#define R_PAR0_CONFIG__iack__BITNR 19
+#define R_PAR0_CONFIG__ibusy__BITNR 18
+#define R_PAR0_CONFIG__ifault__BITNR 17
+#define R_PAR0_CONFIG__isel__BITNR 16
+#define R_PAR0_CONFIG__ext_mode__BITNR 11
+#define R_PAR0_CONFIG__wide__BITNR 10
+#define R_PAR0_CONFIG__dma__BITNR 9
+#define R_PAR0_CONFIG__rle_in__BITNR 8
+#define R_PAR0_CONFIG__rle_out__BITNR 7
+#define R_PAR0_CONFIG__enable__BITNR 6
+#define R_PAR0_CONFIG__force__BITNR 5
+#define R_PAR0_CONFIG__ign_ack__BITNR 4
+#define R_PAR0_CONFIG__oe_ack__BITNR 3
+#define R_PAR0_CONFIG__epp_addr_data__BITNR 3
+#define R_PAR0_CONFIG__mode__BITNR 0
+
+#define R_PAR0_CONFIG__ioe__ioe__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__iseli__iseli__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__iautofd__iautofd__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__istrb__istrb__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__iinit__iinit__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__iperr__iperr__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__iack__iack__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__ibusy__ibusy__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__ifault__ifault__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__isel__isel__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__ext_mode__ext_mode__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__wide__wide__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__dma__dma__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__rle_in__rle_in__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__rle_out__rle_out__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__enable__enable__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__force__force__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__ign_ack__ign_ack__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__oe_ack__oe_ack__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__oe_ack__epp_addr_data__VAL REG_VAL_ENUM
+#define R_PAR0_CONFIG__mode__mode__VAL REG_VAL_ENUM
+
+#define R_PAR0_CONFIG__ioe__ioe__inv 1
+#define R_PAR0_CONFIG__ioe__ioe__noninv 0
+#define R_PAR0_CONFIG__iseli__iseli__inv 1
+#define R_PAR0_CONFIG__iseli__iseli__noninv 0
+#define R_PAR0_CONFIG__iautofd__iautofd__inv 1
+#define R_PAR0_CONFIG__iautofd__iautofd__noninv 0
+#define R_PAR0_CONFIG__istrb__istrb__inv 1
+#define R_PAR0_CONFIG__istrb__istrb__noninv 0
+#define R_PAR0_CONFIG__iinit__iinit__inv 1
+#define R_PAR0_CONFIG__iinit__iinit__noninv 0
+#define R_PAR0_CONFIG__iperr__iperr__inv 1
+#define R_PAR0_CONFIG__iperr__iperr__noninv 0
+#define R_PAR0_CONFIG__iack__iack__inv 1
+#define R_PAR0_CONFIG__iack__iack__noninv 0
+#define R_PAR0_CONFIG__ibusy__ibusy__inv 1
+#define R_PAR0_CONFIG__ibusy__ibusy__noninv 0
+#define R_PAR0_CONFIG__ifault__ifault__inv 1
+#define R_PAR0_CONFIG__ifault__ifault__noninv 0
+#define R_PAR0_CONFIG__isel__isel__inv 1
+#define R_PAR0_CONFIG__isel__isel__noninv 0
+#define R_PAR0_CONFIG__ext_mode__ext_mode__disable 0
+#define R_PAR0_CONFIG__ext_mode__ext_mode__enable 1
+#define R_PAR0_CONFIG__wide__wide__disable 0
+#define R_PAR0_CONFIG__wide__wide__enable 1
+#define R_PAR0_CONFIG__dma__dma__disable 0
+#define R_PAR0_CONFIG__dma__dma__enable 1
+#define R_PAR0_CONFIG__rle_in__rle_in__disable 0
+#define R_PAR0_CONFIG__rle_in__rle_in__enable 1
+#define R_PAR0_CONFIG__rle_out__rle_out__disable 0
+#define R_PAR0_CONFIG__rle_out__rle_out__enable 1
+#define R_PAR0_CONFIG__enable__enable__on 1
+#define R_PAR0_CONFIG__enable__enable__reset 0
+#define R_PAR0_CONFIG__force__force__off 0
+#define R_PAR0_CONFIG__force__force__on 1
+#define R_PAR0_CONFIG__ign_ack__ign_ack__ignore 1
+#define R_PAR0_CONFIG__ign_ack__ign_ack__wait 0
+#define R_PAR0_CONFIG__oe_ack__oe_ack__dont_wait 0
+#define R_PAR0_CONFIG__oe_ack__oe_ack__epp_addr 1
+#define R_PAR0_CONFIG__oe_ack__oe_ack__epp_data 0
+#define R_PAR0_CONFIG__oe_ack__oe_ack__wait_oe 1
+#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__dont_wait 0
+#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__epp_addr 1
+#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__epp_data 0
+#define R_PAR0_CONFIG__epp_addr_data__epp_addr_data__wait_oe 1
+#define R_PAR0_CONFIG__mode__mode__byte 4
+#define R_PAR0_CONFIG__mode__mode__centronics 1
+#define R_PAR0_CONFIG__mode__mode__ecp_fwd 5
+#define R_PAR0_CONFIG__mode__mode__ecp_rev 6
+#define R_PAR0_CONFIG__mode__mode__epp_rd 0
+#define R_PAR0_CONFIG__mode__mode__epp_wr1 5
+#define R_PAR0_CONFIG__mode__mode__epp_wr2 6
+#define R_PAR0_CONFIG__mode__mode__epp_wr3 7
+#define R_PAR0_CONFIG__mode__mode__fastbyte 2
+#define R_PAR0_CONFIG__mode__mode__manual 0
+#define R_PAR0_CONFIG__mode__mode__nibble 3
+#define R_PAR0_CONFIG__mode__mode__off 7
+
+#endif
+
+/*
+ * R_PAR0_CTRL
+ * - type: WO
+ * - addr: 0xb0000042
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR0_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000042)
+
+#ifndef REG_NO_SHADOW
+#define R_PAR0_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 2))
+#define R_PAR0_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 2))
+#else /* REG_NO_SHADOW */
+#define R_PAR0_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_PAR0_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PAR0_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_PAR0_CTRL__SVAL REG_SVAL_SHADOW
+#define R_PAR0_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR0_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_PAR0_CTRL__TYPE (REG_BYTE)
+#define R_PAR0_CTRL__GET REG_GET_WO
+#define R_PAR0_CTRL__IGET REG_IGET_WO
+#define R_PAR0_CTRL__SET REG_SET_WO
+#define R_PAR0_CTRL__ISET REG_ISET_WO
+#define R_PAR0_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_PAR0_CTRL__EQL REG_EQL_WO
+#define R_PAR0_CTRL__IEQL REG_IEQL_WO
+#define R_PAR0_CTRL__RD REG_RD_WO
+#define R_PAR0_CTRL__IRD REG_IRD_WO
+#define R_PAR0_CTRL__WR REG_WR_WO
+#define R_PAR0_CTRL__IWR REG_IWR_WO
+
+#define R_PAR0_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_PAR0_CTRL__FIRST 0
+#define R_PAR0_CTRL__IOFFSET 12
+#define R_PAR0_CTRL__LAST 1
+#define R_PAR0_CTRL__OFFSET 16
+#define R_PAR0_CTRL__SOFFSET 12
+/* end */
+
+#define R_PAR0_CTRL__ctrl__ctrl__MASK 0x0000001fU
+
+#define R_PAR0_CTRL__ctrl__MAX 31
+
+#define R_PAR0_CTRL__ctrl__MIN 0
+
+#define R_PAR0_CTRL__ctrl__BITNR 0
+
+#define R_PAR0_CTRL__ctrl__ctrl__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PAR0_CTRL_DATA
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR0_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
+
+#ifndef REG_NO_SHADOW
+#define R_PAR0_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
+#define R_PAR0_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
+#else /* REG_NO_SHADOW */
+#define R_PAR0_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_PAR0_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PAR0_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD
+#define R_PAR0_CTRL_DATA__SVAL REG_SVAL_SHADOW
+#define R_PAR0_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR0_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_PAR0_CTRL_DATA__TYPE (REG_UDWORD)
+#define R_PAR0_CTRL_DATA__GET REG_GET_WO
+#define R_PAR0_CTRL_DATA__IGET REG_IGET_WO
+#define R_PAR0_CTRL_DATA__SET REG_SET_WO
+#define R_PAR0_CTRL_DATA__ISET REG_ISET_WO
+#define R_PAR0_CTRL_DATA__SET_VAL REG_SET_VAL_WO
+#define R_PAR0_CTRL_DATA__EQL REG_EQL_WO
+#define R_PAR0_CTRL_DATA__IEQL REG_IEQL_WO
+#define R_PAR0_CTRL_DATA__RD REG_RD_WO
+#define R_PAR0_CTRL_DATA__IRD REG_IRD_WO
+#define R_PAR0_CTRL_DATA__WR REG_WR_WO
+#define R_PAR0_CTRL_DATA__IWR REG_IWR_WO
+
+#define R_PAR0_CTRL_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_PAR0_CTRL_DATA__FIRST 0
+#define R_PAR0_CTRL_DATA__IOFFSET 12
+#define R_PAR0_CTRL_DATA__LAST 1
+#define R_PAR0_CTRL_DATA__OFFSET 16
+#define R_PAR0_CTRL_DATA__SOFFSET 12
+/* end */
+
+#define R_PAR0_CTRL_DATA__peri_int__peri_int__MASK 0x01000000U
+#define R_PAR0_CTRL_DATA__oe__oe__MASK 0x00100000U
+#define R_PAR0_CTRL_DATA__seli__seli__MASK 0x00080000U
+#define R_PAR0_CTRL_DATA__autofd__autofd__MASK 0x00040000U
+#define R_PAR0_CTRL_DATA__strb__strb__MASK 0x00020000U
+#define R_PAR0_CTRL_DATA__init__init__MASK 0x00010000U
+#define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U
+#define R_PAR0_CTRL_DATA__data__data__MASK 0x000000ffU
+
+#define R_PAR0_CTRL_DATA__peri_int__MAX 0x1
+#define R_PAR0_CTRL_DATA__oe__MAX 0x1
+#define R_PAR0_CTRL_DATA__seli__MAX 0x1
+#define R_PAR0_CTRL_DATA__autofd__MAX 0x1
+#define R_PAR0_CTRL_DATA__strb__MAX 0x1
+#define R_PAR0_CTRL_DATA__init__MAX 0x1
+#define R_PAR0_CTRL_DATA__ecp_cmd__MAX 0x1
+#define R_PAR0_CTRL_DATA__data__MAX 0xff
+
+#define R_PAR0_CTRL_DATA__peri_int__MIN 0
+#define R_PAR0_CTRL_DATA__oe__MIN 0
+#define R_PAR0_CTRL_DATA__seli__MIN 0
+#define R_PAR0_CTRL_DATA__autofd__MIN 0
+#define R_PAR0_CTRL_DATA__strb__MIN 0
+#define R_PAR0_CTRL_DATA__init__MIN 0
+#define R_PAR0_CTRL_DATA__ecp_cmd__MIN 0
+#define R_PAR0_CTRL_DATA__data__MIN 0
+
+#define R_PAR0_CTRL_DATA__peri_int__BITNR 24
+#define R_PAR0_CTRL_DATA__oe__BITNR 20
+#define R_PAR0_CTRL_DATA__seli__BITNR 19
+#define R_PAR0_CTRL_DATA__autofd__BITNR 18
+#define R_PAR0_CTRL_DATA__strb__BITNR 17
+#define R_PAR0_CTRL_DATA__init__BITNR 16
+#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8
+#define R_PAR0_CTRL_DATA__data__BITNR 0
+
+#define R_PAR0_CTRL_DATA__peri_int__peri_int__VAL REG_VAL_ENUM
+#define R_PAR0_CTRL_DATA__oe__oe__VAL REG_VAL_ENUM
+#define R_PAR0_CTRL_DATA__seli__seli__VAL REG_VAL_ENUM
+#define R_PAR0_CTRL_DATA__autofd__autofd__VAL REG_VAL_ENUM
+#define R_PAR0_CTRL_DATA__strb__strb__VAL REG_VAL_ENUM
+#define R_PAR0_CTRL_DATA__init__init__VAL REG_VAL_ENUM
+#define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM
+#define R_PAR0_CTRL_DATA__data__data__VAL REG_VAL_VAL
+
+#define R_PAR0_CTRL_DATA__peri_int__peri_int__ack 1
+#define R_PAR0_CTRL_DATA__peri_int__peri_int__nop 0
+#define R_PAR0_CTRL_DATA__oe__oe__disable 0
+#define R_PAR0_CTRL_DATA__oe__oe__enable 1
+#define R_PAR0_CTRL_DATA__seli__seli__active 1
+#define R_PAR0_CTRL_DATA__seli__seli__inactive 0
+#define R_PAR0_CTRL_DATA__autofd__autofd__active 1
+#define R_PAR0_CTRL_DATA__autofd__autofd__inactive 0
+#define R_PAR0_CTRL_DATA__strb__strb__active 1
+#define R_PAR0_CTRL_DATA__strb__strb__inactive 0
+#define R_PAR0_CTRL_DATA__init__init__active 1
+#define R_PAR0_CTRL_DATA__init__init__inactive 0
+#define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__command 1
+#define R_PAR0_CTRL_DATA__ecp_cmd__ecp_cmd__data 0
+
+#endif
+
+/*
+ * R_PAR0_DELAY
+ * - type: WO
+ * - addr: 0xb0000048
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR0_DELAY__ADDR (REG_TYPECAST_UDWORD 0xb0000048)
+
+#ifndef REG_NO_SHADOW
+#define R_PAR0_DELAY__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR0_DELAY + 0))
+#define R_PAR0_DELAY__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR0_DELAY + 0))
+#else /* REG_NO_SHADOW */
+#define R_PAR0_DELAY__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_PAR0_DELAY__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PAR0_DELAY__STYPECAST REG_STYPECAST_UDWORD
+#define R_PAR0_DELAY__SVAL REG_SVAL_SHADOW
+#define R_PAR0_DELAY__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR0_DELAY__TYPECAST REG_TYPECAST_UDWORD
+#define R_PAR0_DELAY__TYPE (REG_UDWORD)
+#define R_PAR0_DELAY__GET REG_GET_WO
+#define R_PAR0_DELAY__IGET REG_IGET_WO
+#define R_PAR0_DELAY__SET REG_SET_WO
+#define R_PAR0_DELAY__ISET REG_ISET_WO
+#define R_PAR0_DELAY__SET_VAL REG_SET_VAL_WO
+#define R_PAR0_DELAY__EQL REG_EQL_WO
+#define R_PAR0_DELAY__IEQL REG_IEQL_WO
+#define R_PAR0_DELAY__RD REG_RD_WO
+#define R_PAR0_DELAY__IRD REG_IRD_WO
+#define R_PAR0_DELAY__WR REG_WR_WO
+#define R_PAR0_DELAY__IWR REG_IWR_WO
+
+#define R_PAR0_DELAY__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_PAR0_DELAY__FIRST 0
+#define R_PAR0_DELAY__IOFFSET 12
+#define R_PAR0_DELAY__LAST 1
+#define R_PAR0_DELAY__OFFSET 16
+#define R_PAR0_DELAY__SOFFSET 12
+/* end */
+
+#define R_PAR0_DELAY__fine_hold__fine_hold__MASK 0x00e00000U
+#define R_PAR0_DELAY__hold__hold__MASK 0x001f0000U
+#define R_PAR0_DELAY__fine_strb__fine_strb__MASK 0x0000e000U
+#define R_PAR0_DELAY__strobe__strobe__MASK 0x00001f00U
+#define R_PAR0_DELAY__fine_setup__fine_setup__MASK 0x000000e0U
+#define R_PAR0_DELAY__setup__setup__MASK 0x0000001fU
+
+#define R_PAR0_DELAY__fine_hold__MAX 0x7
+#define R_PAR0_DELAY__hold__MAX 0x1f
+#define R_PAR0_DELAY__fine_strb__MAX 0x7
+#define R_PAR0_DELAY__strobe__MAX 0x1f
+#define R_PAR0_DELAY__fine_setup__MAX 0x7
+#define R_PAR0_DELAY__setup__MAX 0x1f
+
+#define R_PAR0_DELAY__fine_hold__MIN 0
+#define R_PAR0_DELAY__hold__MIN 0
+#define R_PAR0_DELAY__fine_strb__MIN 0
+#define R_PAR0_DELAY__strobe__MIN 0
+#define R_PAR0_DELAY__fine_setup__MIN 0
+#define R_PAR0_DELAY__setup__MIN 0
+
+#define R_PAR0_DELAY__fine_hold__BITNR 21
+#define R_PAR0_DELAY__hold__BITNR 16
+#define R_PAR0_DELAY__fine_strb__BITNR 13
+#define R_PAR0_DELAY__strobe__BITNR 8
+#define R_PAR0_DELAY__fine_setup__BITNR 5
+#define R_PAR0_DELAY__setup__BITNR 0
+
+#define R_PAR0_DELAY__fine_hold__fine_hold__VAL REG_VAL_VAL
+#define R_PAR0_DELAY__hold__hold__VAL REG_VAL_VAL
+#define R_PAR0_DELAY__fine_strb__fine_strb__VAL REG_VAL_VAL
+#define R_PAR0_DELAY__strobe__strobe__VAL REG_VAL_VAL
+#define R_PAR0_DELAY__fine_setup__fine_setup__VAL REG_VAL_VAL
+#define R_PAR0_DELAY__setup__setup__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PAR0_STATUS
+ * - type: RO
+ * - addr: 0xb0000042
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR0_STATUS__ADDR (REG_TYPECAST_UWORD 0xb0000042)
+#define R_PAR0_STATUS__SVAL REG_SVAL_SHADOW
+#define R_PAR0_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR0_STATUS__TYPECAST REG_TYPECAST_UWORD
+#define R_PAR0_STATUS__TYPE (REG_UWORD)
+#define R_PAR0_STATUS__GET REG_GET_RO
+#define R_PAR0_STATUS__IGET REG_IGET_RO
+#define R_PAR0_STATUS__SET REG_SET_RO
+#define R_PAR0_STATUS__ISET REG_ISET_RO
+#define R_PAR0_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_PAR0_STATUS__EQL REG_EQL_RO
+#define R_PAR0_STATUS__IEQL REG_IEQL_RO
+#define R_PAR0_STATUS__RD REG_RD_RO
+#define R_PAR0_STATUS__IRD REG_IRD_RO
+#define R_PAR0_STATUS__WR REG_WR_RO
+#define R_PAR0_STATUS__IWR REG_IWR_RO
+
+#define R_PAR0_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_PAR0_STATUS__mode__mode__MASK 0x0000e000U
+#define R_PAR0_STATUS__perr__perr__MASK 0x00001000U
+#define R_PAR0_STATUS__ack__ack__MASK 0x00000800U
+#define R_PAR0_STATUS__busy__busy__MASK 0x00000400U
+#define R_PAR0_STATUS__fault__fault__MASK 0x00000200U
+#define R_PAR0_STATUS__sel__sel__MASK 0x00000100U
+#define R_PAR0_STATUS__ext_mode__ext_mode__MASK 0x00000080U
+#define R_PAR0_STATUS__ecp_16__ecp_16__MASK 0x00000040U
+#define R_PAR0_STATUS__tr_rdy__tr_rdy__MASK 0x00000002U
+#define R_PAR0_STATUS__dav__dav__MASK 0x00000001U
+
+#define R_PAR0_STATUS__mode__MAX 0x7
+#define R_PAR0_STATUS__perr__MAX 0x1
+#define R_PAR0_STATUS__ack__MAX 0x1
+#define R_PAR0_STATUS__busy__MAX 0x1
+#define R_PAR0_STATUS__fault__MAX 0x1
+#define R_PAR0_STATUS__sel__MAX 0x1
+#define R_PAR0_STATUS__ext_mode__MAX 0x1
+#define R_PAR0_STATUS__ecp_16__MAX 0x1
+#define R_PAR0_STATUS__tr_rdy__MAX 0x1
+#define R_PAR0_STATUS__dav__MAX 0x1
+
+#define R_PAR0_STATUS__mode__MIN 0
+#define R_PAR0_STATUS__perr__MIN 0
+#define R_PAR0_STATUS__ack__MIN 0
+#define R_PAR0_STATUS__busy__MIN 0
+#define R_PAR0_STATUS__fault__MIN 0
+#define R_PAR0_STATUS__sel__MIN 0
+#define R_PAR0_STATUS__ext_mode__MIN 0
+#define R_PAR0_STATUS__ecp_16__MIN 0
+#define R_PAR0_STATUS__tr_rdy__MIN 0
+#define R_PAR0_STATUS__dav__MIN 0
+
+#define R_PAR0_STATUS__mode__BITNR 13
+#define R_PAR0_STATUS__perr__BITNR 12
+#define R_PAR0_STATUS__ack__BITNR 11
+#define R_PAR0_STATUS__busy__BITNR 10
+#define R_PAR0_STATUS__fault__BITNR 9
+#define R_PAR0_STATUS__sel__BITNR 8
+#define R_PAR0_STATUS__ext_mode__BITNR 7
+#define R_PAR0_STATUS__ecp_16__BITNR 6
+#define R_PAR0_STATUS__tr_rdy__BITNR 1
+#define R_PAR0_STATUS__dav__BITNR 0
+
+#define R_PAR0_STATUS__mode__mode__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__perr__perr__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__ack__ack__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__busy__busy__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__fault__fault__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__sel__sel__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__ext_mode__ext_mode__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__ecp_16__ecp_16__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS__dav__dav__VAL REG_VAL_ENUM
+
+#define R_PAR0_STATUS__mode__mode__byte 4
+#define R_PAR0_STATUS__mode__mode__centronics 1
+#define R_PAR0_STATUS__mode__mode__ecp_fwd 5
+#define R_PAR0_STATUS__mode__mode__ecp_rev 6
+#define R_PAR0_STATUS__mode__mode__epp_rd 0
+#define R_PAR0_STATUS__mode__mode__epp_wr1 5
+#define R_PAR0_STATUS__mode__mode__epp_wr2 6
+#define R_PAR0_STATUS__mode__mode__epp_wr3 7
+#define R_PAR0_STATUS__mode__mode__fastbyte 2
+#define R_PAR0_STATUS__mode__mode__manual 0
+#define R_PAR0_STATUS__mode__mode__nibble 3
+#define R_PAR0_STATUS__mode__mode__off 7
+#define R_PAR0_STATUS__perr__perr__active 1
+#define R_PAR0_STATUS__perr__perr__inactive 0
+#define R_PAR0_STATUS__ack__ack__active 0
+#define R_PAR0_STATUS__ack__ack__inactive 1
+#define R_PAR0_STATUS__busy__busy__active 1
+#define R_PAR0_STATUS__busy__busy__inactive 0
+#define R_PAR0_STATUS__fault__fault__active 0
+#define R_PAR0_STATUS__fault__fault__inactive 1
+#define R_PAR0_STATUS__sel__sel__active 1
+#define R_PAR0_STATUS__sel__sel__inactive 0
+#define R_PAR0_STATUS__ext_mode__ext_mode__disable 0
+#define R_PAR0_STATUS__ext_mode__ext_mode__enable 1
+#define R_PAR0_STATUS__ecp_16__ecp_16__active 1
+#define R_PAR0_STATUS__ecp_16__ecp_16__inactive 0
+#define R_PAR0_STATUS__tr_rdy__tr_rdy__busy 0
+#define R_PAR0_STATUS__tr_rdy__tr_rdy__ready 1
+#define R_PAR0_STATUS__dav__dav__data 1
+#define R_PAR0_STATUS__dav__dav__nodata 0
+
+#endif
+
+/*
+ * R_PAR0_STATUS_DATA
+ * - type: RO
+ * - addr: 0xb0000040
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR0_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
+#define R_PAR0_STATUS_DATA__SVAL REG_SVAL_SHADOW
+#define R_PAR0_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR0_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_PAR0_STATUS_DATA__TYPE (REG_UDWORD)
+#define R_PAR0_STATUS_DATA__GET REG_GET_RO
+#define R_PAR0_STATUS_DATA__IGET REG_IGET_RO
+#define R_PAR0_STATUS_DATA__SET REG_SET_RO
+#define R_PAR0_STATUS_DATA__ISET REG_ISET_RO
+#define R_PAR0_STATUS_DATA__SET_VAL REG_SET_VAL_RO
+#define R_PAR0_STATUS_DATA__EQL REG_EQL_RO
+#define R_PAR0_STATUS_DATA__IEQL REG_IEQL_RO
+#define R_PAR0_STATUS_DATA__RD REG_RD_RO
+#define R_PAR0_STATUS_DATA__IRD REG_IRD_RO
+#define R_PAR0_STATUS_DATA__WR REG_WR_RO
+#define R_PAR0_STATUS_DATA__IWR REG_IWR_RO
+
+#define R_PAR0_STATUS_DATA__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_PAR0_STATUS_DATA__FIRST 0
+#define R_PAR0_STATUS_DATA__LAST 1
+#define R_PAR0_STATUS_DATA__OFFSET 16
+/* end */
+
+#define R_PAR0_STATUS_DATA__mode__mode__MASK 0xe0000000U
+#define R_PAR0_STATUS_DATA__perr__perr__MASK 0x10000000U
+#define R_PAR0_STATUS_DATA__ack__ack__MASK 0x08000000U
+#define R_PAR0_STATUS_DATA__busy__busy__MASK 0x04000000U
+#define R_PAR0_STATUS_DATA__fault__fault__MASK 0x02000000U
+#define R_PAR0_STATUS_DATA__sel__sel__MASK 0x01000000U
+#define R_PAR0_STATUS_DATA__ext_mode__ext_mode__MASK 0x00800000U
+#define R_PAR0_STATUS_DATA__ecp_16__ecp_16__MASK 0x00400000U
+#define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U
+#define R_PAR0_STATUS_DATA__dav__dav__MASK 0x00010000U
+#define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U
+#define R_PAR0_STATUS_DATA__data__data__MASK 0x000000ffU
+
+#define R_PAR0_STATUS_DATA__mode__MAX 0x7
+#define R_PAR0_STATUS_DATA__perr__MAX 0x1
+#define R_PAR0_STATUS_DATA__ack__MAX 0x1
+#define R_PAR0_STATUS_DATA__busy__MAX 0x1
+#define R_PAR0_STATUS_DATA__fault__MAX 0x1
+#define R_PAR0_STATUS_DATA__sel__MAX 0x1
+#define R_PAR0_STATUS_DATA__ext_mode__MAX 0x1
+#define R_PAR0_STATUS_DATA__ecp_16__MAX 0x1
+#define R_PAR0_STATUS_DATA__tr_rdy__MAX 0x1
+#define R_PAR0_STATUS_DATA__dav__MAX 0x1
+#define R_PAR0_STATUS_DATA__ecp_cmd__MAX 0x1
+#define R_PAR0_STATUS_DATA__data__MAX 0xff
+
+#define R_PAR0_STATUS_DATA__mode__MIN 0
+#define R_PAR0_STATUS_DATA__perr__MIN 0
+#define R_PAR0_STATUS_DATA__ack__MIN 0
+#define R_PAR0_STATUS_DATA__busy__MIN 0
+#define R_PAR0_STATUS_DATA__fault__MIN 0
+#define R_PAR0_STATUS_DATA__sel__MIN 0
+#define R_PAR0_STATUS_DATA__ext_mode__MIN 0
+#define R_PAR0_STATUS_DATA__ecp_16__MIN 0
+#define R_PAR0_STATUS_DATA__tr_rdy__MIN 0
+#define R_PAR0_STATUS_DATA__dav__MIN 0
+#define R_PAR0_STATUS_DATA__ecp_cmd__MIN 0
+#define R_PAR0_STATUS_DATA__data__MIN 0
+
+#define R_PAR0_STATUS_DATA__mode__BITNR 29
+#define R_PAR0_STATUS_DATA__perr__BITNR 28
+#define R_PAR0_STATUS_DATA__ack__BITNR 27
+#define R_PAR0_STATUS_DATA__busy__BITNR 26
+#define R_PAR0_STATUS_DATA__fault__BITNR 25
+#define R_PAR0_STATUS_DATA__sel__BITNR 24
+#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23
+#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22
+#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17
+#define R_PAR0_STATUS_DATA__dav__BITNR 16
+#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8
+#define R_PAR0_STATUS_DATA__data__BITNR 0
+
+#define R_PAR0_STATUS_DATA__mode__mode__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__perr__perr__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__ack__ack__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__fault__fault__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__sel__sel__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__ext_mode__ext_mode__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__ecp_16__ecp_16__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM
+#define R_PAR0_STATUS_DATA__data__data__VAL REG_VAL_VAL
+
+#define R_PAR0_STATUS_DATA__mode__mode__byte 4
+#define R_PAR0_STATUS_DATA__mode__mode__centronics 1
+#define R_PAR0_STATUS_DATA__mode__mode__ecp_fwd 5
+#define R_PAR0_STATUS_DATA__mode__mode__ecp_rev 6
+#define R_PAR0_STATUS_DATA__mode__mode__epp_rd 0
+#define R_PAR0_STATUS_DATA__mode__mode__epp_wr1 5
+#define R_PAR0_STATUS_DATA__mode__mode__epp_wr2 6
+#define R_PAR0_STATUS_DATA__mode__mode__epp_wr3 7
+#define R_PAR0_STATUS_DATA__mode__mode__fastbyte 2
+#define R_PAR0_STATUS_DATA__mode__mode__manual 0
+#define R_PAR0_STATUS_DATA__mode__mode__nibble 3
+#define R_PAR0_STATUS_DATA__mode__mode__off 7
+#define R_PAR0_STATUS_DATA__perr__perr__active 1
+#define R_PAR0_STATUS_DATA__perr__perr__inactive 0
+#define R_PAR0_STATUS_DATA__ack__ack__active 0
+#define R_PAR0_STATUS_DATA__ack__ack__inactive 1
+#define R_PAR0_STATUS_DATA__busy__busy__active 1
+#define R_PAR0_STATUS_DATA__busy__busy__inactive 0
+#define R_PAR0_STATUS_DATA__fault__fault__active 0
+#define R_PAR0_STATUS_DATA__fault__fault__inactive 1
+#define R_PAR0_STATUS_DATA__sel__sel__active 1
+#define R_PAR0_STATUS_DATA__sel__sel__inactive 0
+#define R_PAR0_STATUS_DATA__ext_mode__ext_mode__disable 0
+#define R_PAR0_STATUS_DATA__ext_mode__ext_mode__enable 1
+#define R_PAR0_STATUS_DATA__ecp_16__ecp_16__active 1
+#define R_PAR0_STATUS_DATA__ecp_16__ecp_16__inactive 0
+#define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__busy 0
+#define R_PAR0_STATUS_DATA__tr_rdy__tr_rdy__ready 1
+#define R_PAR0_STATUS_DATA__dav__dav__data 1
+#define R_PAR0_STATUS_DATA__dav__dav__nodata 0
+#define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__command 1
+#define R_PAR0_STATUS_DATA__ecp_cmd__ecp_cmd__data 0
+
+#endif
+
+/*
+ * R_PAR1_CONFIG
+ * - type: WO
+ * - addr: 0xb0000054
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR1_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000054)
+
+#ifndef REG_NO_SHADOW
+#define R_PAR1_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CONFIG + 0))
+#define R_PAR1_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_PAR1_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_PAR1_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PAR1_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_PAR1_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_PAR1_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR1_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_PAR1_CONFIG__TYPE (REG_UDWORD)
+#define R_PAR1_CONFIG__GET REG_GET_WO
+#define R_PAR1_CONFIG__IGET REG_IGET_WO
+#define R_PAR1_CONFIG__SET REG_SET_WO
+#define R_PAR1_CONFIG__ISET REG_ISET_WO
+#define R_PAR1_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_PAR1_CONFIG__EQL REG_EQL_WO
+#define R_PAR1_CONFIG__IEQL REG_IEQL_WO
+#define R_PAR1_CONFIG__RD REG_RD_WO
+#define R_PAR1_CONFIG__IRD REG_IRD_WO
+#define R_PAR1_CONFIG__WR REG_WR_WO
+#define R_PAR1_CONFIG__IWR REG_IWR_WO
+
+#define R_PAR1_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PAR1_CONFIG__ioe__ioe__MASK 0x02000000U
+#define R_PAR1_CONFIG__iseli__iseli__MASK 0x01000000U
+#define R_PAR1_CONFIG__iautofd__iautofd__MASK 0x00800000U
+#define R_PAR1_CONFIG__istrb__istrb__MASK 0x00400000U
+#define R_PAR1_CONFIG__iinit__iinit__MASK 0x00200000U
+#define R_PAR1_CONFIG__iperr__iperr__MASK 0x00100000U
+#define R_PAR1_CONFIG__iack__iack__MASK 0x00080000U
+#define R_PAR1_CONFIG__ibusy__ibusy__MASK 0x00040000U
+#define R_PAR1_CONFIG__ifault__ifault__MASK 0x00020000U
+#define R_PAR1_CONFIG__isel__isel__MASK 0x00010000U
+#define R_PAR1_CONFIG__ext_mode__ext_mode__MASK 0x00000800U
+#define R_PAR1_CONFIG__dma__dma__MASK 0x00000200U
+#define R_PAR1_CONFIG__rle_in__rle_in__MASK 0x00000100U
+#define R_PAR1_CONFIG__rle_out__rle_out__MASK 0x00000080U
+#define R_PAR1_CONFIG__enable__enable__MASK 0x00000040U
+#define R_PAR1_CONFIG__force__force__MASK 0x00000020U
+#define R_PAR1_CONFIG__ign_ack__ign_ack__MASK 0x00000010U
+#define R_PAR1_CONFIG__oe_ack__oe_ack__MASK 0x00000008U
+#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__MASK 0x00000008U
+#define R_PAR1_CONFIG__oe_ack__epp_addr_data__MASK 0x00000008U
+#define R_PAR1_CONFIG__mode__mode__MASK 0x00000007U
+
+#define R_PAR1_CONFIG__ioe__MAX 0x1
+#define R_PAR1_CONFIG__iseli__MAX 0x1
+#define R_PAR1_CONFIG__iautofd__MAX 0x1
+#define R_PAR1_CONFIG__istrb__MAX 0x1
+#define R_PAR1_CONFIG__iinit__MAX 0x1
+#define R_PAR1_CONFIG__iperr__MAX 0x1
+#define R_PAR1_CONFIG__iack__MAX 0x1
+#define R_PAR1_CONFIG__ibusy__MAX 0x1
+#define R_PAR1_CONFIG__ifault__MAX 0x1
+#define R_PAR1_CONFIG__isel__MAX 0x1
+#define R_PAR1_CONFIG__ext_mode__MAX 0x1
+#define R_PAR1_CONFIG__dma__MAX 0x1
+#define R_PAR1_CONFIG__rle_in__MAX 0x1
+#define R_PAR1_CONFIG__rle_out__MAX 0x1
+#define R_PAR1_CONFIG__enable__MAX 0x1
+#define R_PAR1_CONFIG__force__MAX 0x1
+#define R_PAR1_CONFIG__ign_ack__MAX 0x1
+#define R_PAR1_CONFIG__oe_ack__MAX 0x1
+#define R_PAR1_CONFIG__epp_addr_data__MAX 0x1
+#define R_PAR1_CONFIG__mode__MAX 0x7
+
+#define R_PAR1_CONFIG__ioe__MIN 0
+#define R_PAR1_CONFIG__iseli__MIN 0
+#define R_PAR1_CONFIG__iautofd__MIN 0
+#define R_PAR1_CONFIG__istrb__MIN 0
+#define R_PAR1_CONFIG__iinit__MIN 0
+#define R_PAR1_CONFIG__iperr__MIN 0
+#define R_PAR1_CONFIG__iack__MIN 0
+#define R_PAR1_CONFIG__ibusy__MIN 0
+#define R_PAR1_CONFIG__ifault__MIN 0
+#define R_PAR1_CONFIG__isel__MIN 0
+#define R_PAR1_CONFIG__ext_mode__MIN 0
+#define R_PAR1_CONFIG__dma__MIN 0
+#define R_PAR1_CONFIG__rle_in__MIN 0
+#define R_PAR1_CONFIG__rle_out__MIN 0
+#define R_PAR1_CONFIG__enable__MIN 0
+#define R_PAR1_CONFIG__force__MIN 0
+#define R_PAR1_CONFIG__ign_ack__MIN 0
+#define R_PAR1_CONFIG__oe_ack__MIN 0
+#define R_PAR1_CONFIG__epp_addr_data__MIN 0
+#define R_PAR1_CONFIG__mode__MIN 0
+
+#define R_PAR1_CONFIG__ioe__BITNR 25
+#define R_PAR1_CONFIG__iseli__BITNR 24
+#define R_PAR1_CONFIG__iautofd__BITNR 23
+#define R_PAR1_CONFIG__istrb__BITNR 22
+#define R_PAR1_CONFIG__iinit__BITNR 21
+#define R_PAR1_CONFIG__iperr__BITNR 20
+#define R_PAR1_CONFIG__iack__BITNR 19
+#define R_PAR1_CONFIG__ibusy__BITNR 18
+#define R_PAR1_CONFIG__ifault__BITNR 17
+#define R_PAR1_CONFIG__isel__BITNR 16
+#define R_PAR1_CONFIG__ext_mode__BITNR 11
+#define R_PAR1_CONFIG__dma__BITNR 9
+#define R_PAR1_CONFIG__rle_in__BITNR 8
+#define R_PAR1_CONFIG__rle_out__BITNR 7
+#define R_PAR1_CONFIG__enable__BITNR 6
+#define R_PAR1_CONFIG__force__BITNR 5
+#define R_PAR1_CONFIG__ign_ack__BITNR 4
+#define R_PAR1_CONFIG__oe_ack__BITNR 3
+#define R_PAR1_CONFIG__epp_addr_data__BITNR 3
+#define R_PAR1_CONFIG__mode__BITNR 0
+
+#define R_PAR1_CONFIG__ioe__ioe__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__iseli__iseli__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__iautofd__iautofd__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__istrb__istrb__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__iinit__iinit__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__iperr__iperr__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__iack__iack__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__ibusy__ibusy__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__ifault__ifault__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__isel__isel__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__ext_mode__ext_mode__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__dma__dma__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__rle_in__rle_in__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__rle_out__rle_out__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__enable__enable__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__force__force__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__ign_ack__ign_ack__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__oe_ack__oe_ack__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__oe_ack__epp_addr_data__VAL REG_VAL_ENUM
+#define R_PAR1_CONFIG__mode__mode__VAL REG_VAL_ENUM
+
+#define R_PAR1_CONFIG__ioe__ioe__inv 1
+#define R_PAR1_CONFIG__ioe__ioe__noninv 0
+#define R_PAR1_CONFIG__iseli__iseli__inv 1
+#define R_PAR1_CONFIG__iseli__iseli__noninv 0
+#define R_PAR1_CONFIG__iautofd__iautofd__inv 1
+#define R_PAR1_CONFIG__iautofd__iautofd__noninv 0
+#define R_PAR1_CONFIG__istrb__istrb__inv 1
+#define R_PAR1_CONFIG__istrb__istrb__noninv 0
+#define R_PAR1_CONFIG__iinit__iinit__inv 1
+#define R_PAR1_CONFIG__iinit__iinit__noninv 0
+#define R_PAR1_CONFIG__iperr__iperr__inv 1
+#define R_PAR1_CONFIG__iperr__iperr__noninv 0
+#define R_PAR1_CONFIG__iack__iack__inv 1
+#define R_PAR1_CONFIG__iack__iack__noninv 0
+#define R_PAR1_CONFIG__ibusy__ibusy__inv 1
+#define R_PAR1_CONFIG__ibusy__ibusy__noninv 0
+#define R_PAR1_CONFIG__ifault__ifault__inv 1
+#define R_PAR1_CONFIG__ifault__ifault__noninv 0
+#define R_PAR1_CONFIG__isel__isel__inv 1
+#define R_PAR1_CONFIG__isel__isel__noninv 0
+#define R_PAR1_CONFIG__ext_mode__ext_mode__disable 0
+#define R_PAR1_CONFIG__ext_mode__ext_mode__enable 1
+#define R_PAR1_CONFIG__dma__dma__disable 0
+#define R_PAR1_CONFIG__dma__dma__enable 1
+#define R_PAR1_CONFIG__rle_in__rle_in__disable 0
+#define R_PAR1_CONFIG__rle_in__rle_in__enable 1
+#define R_PAR1_CONFIG__rle_out__rle_out__disable 0
+#define R_PAR1_CONFIG__rle_out__rle_out__enable 1
+#define R_PAR1_CONFIG__enable__enable__on 1
+#define R_PAR1_CONFIG__enable__enable__reset 0
+#define R_PAR1_CONFIG__force__force__off 0
+#define R_PAR1_CONFIG__force__force__on 1
+#define R_PAR1_CONFIG__ign_ack__ign_ack__ignore 1
+#define R_PAR1_CONFIG__ign_ack__ign_ack__wait 0
+#define R_PAR1_CONFIG__oe_ack__oe_ack__dont_wait 0
+#define R_PAR1_CONFIG__oe_ack__oe_ack__epp_addr 1
+#define R_PAR1_CONFIG__oe_ack__oe_ack__epp_data 0
+#define R_PAR1_CONFIG__oe_ack__oe_ack__wait_oe 1
+#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__dont_wait 0
+#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__epp_addr 1
+#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__epp_data 0
+#define R_PAR1_CONFIG__epp_addr_data__epp_addr_data__wait_oe 1
+#define R_PAR1_CONFIG__mode__mode__byte 4
+#define R_PAR1_CONFIG__mode__mode__centronics 1
+#define R_PAR1_CONFIG__mode__mode__ecp_fwd 5
+#define R_PAR1_CONFIG__mode__mode__ecp_rev 6
+#define R_PAR1_CONFIG__mode__mode__epp_rd 0
+#define R_PAR1_CONFIG__mode__mode__epp_wr1 5
+#define R_PAR1_CONFIG__mode__mode__epp_wr2 6
+#define R_PAR1_CONFIG__mode__mode__epp_wr3 7
+#define R_PAR1_CONFIG__mode__mode__fastbyte 2
+#define R_PAR1_CONFIG__mode__mode__manual 0
+#define R_PAR1_CONFIG__mode__mode__nibble 3
+#define R_PAR1_CONFIG__mode__mode__off 7
+
+#endif
+
+/*
+ * R_PAR1_CTRL
+ * - type: WO
+ * - addr: 0xb0000052
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR1_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000052)
+
+#ifndef REG_NO_SHADOW
+#define R_PAR1_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2))
+#define R_PAR1_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2))
+#else /* REG_NO_SHADOW */
+#define R_PAR1_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_PAR1_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PAR1_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_PAR1_CTRL__SVAL REG_SVAL_SHADOW
+#define R_PAR1_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR1_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_PAR1_CTRL__TYPE (REG_BYTE)
+#define R_PAR1_CTRL__GET REG_GET_WO
+#define R_PAR1_CTRL__IGET REG_IGET_WO
+#define R_PAR1_CTRL__SET REG_SET_WO
+#define R_PAR1_CTRL__ISET REG_ISET_WO
+#define R_PAR1_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_PAR1_CTRL__EQL REG_EQL_WO
+#define R_PAR1_CTRL__IEQL REG_IEQL_WO
+#define R_PAR1_CTRL__RD REG_RD_WO
+#define R_PAR1_CTRL__IRD REG_IRD_WO
+#define R_PAR1_CTRL__WR REG_WR_WO
+#define R_PAR1_CTRL__IWR REG_IWR_WO
+
+#define R_PAR1_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PAR1_CTRL__ctrl__ctrl__MASK 0x0000001fU
+
+#define R_PAR1_CTRL__ctrl__MAX 31
+
+#define R_PAR1_CTRL__ctrl__MIN 0
+
+#define R_PAR1_CTRL__ctrl__BITNR 0
+
+#define R_PAR1_CTRL__ctrl__ctrl__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PAR1_CTRL_DATA
+ * - type: WO
+ * - addr: 0xb0000050
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR1_CTRL_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050)
+
+#ifndef REG_NO_SHADOW
+#define R_PAR1_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0))
+#define R_PAR1_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0))
+#else /* REG_NO_SHADOW */
+#define R_PAR1_CTRL_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_PAR1_CTRL_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PAR1_CTRL_DATA__STYPECAST REG_STYPECAST_UDWORD
+#define R_PAR1_CTRL_DATA__SVAL REG_SVAL_SHADOW
+#define R_PAR1_CTRL_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR1_CTRL_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_PAR1_CTRL_DATA__TYPE (REG_UDWORD)
+#define R_PAR1_CTRL_DATA__GET REG_GET_WO
+#define R_PAR1_CTRL_DATA__IGET REG_IGET_WO
+#define R_PAR1_CTRL_DATA__SET REG_SET_WO
+#define R_PAR1_CTRL_DATA__ISET REG_ISET_WO
+#define R_PAR1_CTRL_DATA__SET_VAL REG_SET_VAL_WO
+#define R_PAR1_CTRL_DATA__EQL REG_EQL_WO
+#define R_PAR1_CTRL_DATA__IEQL REG_IEQL_WO
+#define R_PAR1_CTRL_DATA__RD REG_RD_WO
+#define R_PAR1_CTRL_DATA__IRD REG_IRD_WO
+#define R_PAR1_CTRL_DATA__WR REG_WR_WO
+#define R_PAR1_CTRL_DATA__IWR REG_IWR_WO
+
+#define R_PAR1_CTRL_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PAR1_CTRL_DATA__peri_int__peri_int__MASK 0x01000000U
+#define R_PAR1_CTRL_DATA__oe__oe__MASK 0x00100000U
+#define R_PAR1_CTRL_DATA__seli__seli__MASK 0x00080000U
+#define R_PAR1_CTRL_DATA__autofd__autofd__MASK 0x00040000U
+#define R_PAR1_CTRL_DATA__strb__strb__MASK 0x00020000U
+#define R_PAR1_CTRL_DATA__init__init__MASK 0x00010000U
+#define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U
+#define R_PAR1_CTRL_DATA__data__data__MASK 0x000000ffU
+
+#define R_PAR1_CTRL_DATA__peri_int__MAX 0x1
+#define R_PAR1_CTRL_DATA__oe__MAX 0x1
+#define R_PAR1_CTRL_DATA__seli__MAX 0x1
+#define R_PAR1_CTRL_DATA__autofd__MAX 0x1
+#define R_PAR1_CTRL_DATA__strb__MAX 0x1
+#define R_PAR1_CTRL_DATA__init__MAX 0x1
+#define R_PAR1_CTRL_DATA__ecp_cmd__MAX 0x1
+#define R_PAR1_CTRL_DATA__data__MAX 0xff
+
+#define R_PAR1_CTRL_DATA__peri_int__MIN 0
+#define R_PAR1_CTRL_DATA__oe__MIN 0
+#define R_PAR1_CTRL_DATA__seli__MIN 0
+#define R_PAR1_CTRL_DATA__autofd__MIN 0
+#define R_PAR1_CTRL_DATA__strb__MIN 0
+#define R_PAR1_CTRL_DATA__init__MIN 0
+#define R_PAR1_CTRL_DATA__ecp_cmd__MIN 0
+#define R_PAR1_CTRL_DATA__data__MIN 0
+
+#define R_PAR1_CTRL_DATA__peri_int__BITNR 24
+#define R_PAR1_CTRL_DATA__oe__BITNR 20
+#define R_PAR1_CTRL_DATA__seli__BITNR 19
+#define R_PAR1_CTRL_DATA__autofd__BITNR 18
+#define R_PAR1_CTRL_DATA__strb__BITNR 17
+#define R_PAR1_CTRL_DATA__init__BITNR 16
+#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8
+#define R_PAR1_CTRL_DATA__data__BITNR 0
+
+#define R_PAR1_CTRL_DATA__peri_int__peri_int__VAL REG_VAL_ENUM
+#define R_PAR1_CTRL_DATA__oe__oe__VAL REG_VAL_ENUM
+#define R_PAR1_CTRL_DATA__seli__seli__VAL REG_VAL_ENUM
+#define R_PAR1_CTRL_DATA__autofd__autofd__VAL REG_VAL_ENUM
+#define R_PAR1_CTRL_DATA__strb__strb__VAL REG_VAL_ENUM
+#define R_PAR1_CTRL_DATA__init__init__VAL REG_VAL_ENUM
+#define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM
+#define R_PAR1_CTRL_DATA__data__data__VAL REG_VAL_VAL
+
+#define R_PAR1_CTRL_DATA__peri_int__peri_int__ack 1
+#define R_PAR1_CTRL_DATA__peri_int__peri_int__nop 0
+#define R_PAR1_CTRL_DATA__oe__oe__disable 0
+#define R_PAR1_CTRL_DATA__oe__oe__enable 1
+#define R_PAR1_CTRL_DATA__seli__seli__active 1
+#define R_PAR1_CTRL_DATA__seli__seli__inactive 0
+#define R_PAR1_CTRL_DATA__autofd__autofd__active 1
+#define R_PAR1_CTRL_DATA__autofd__autofd__inactive 0
+#define R_PAR1_CTRL_DATA__strb__strb__active 1
+#define R_PAR1_CTRL_DATA__strb__strb__inactive 0
+#define R_PAR1_CTRL_DATA__init__init__active 1
+#define R_PAR1_CTRL_DATA__init__init__inactive 0
+#define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__command 1
+#define R_PAR1_CTRL_DATA__ecp_cmd__ecp_cmd__data 0
+
+#endif
+
+/*
+ * R_PAR1_DELAY
+ * - type: WO
+ * - addr: 0xb0000058
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR1_DELAY__ADDR (REG_TYPECAST_UDWORD 0xb0000058)
+
+#ifndef REG_NO_SHADOW
+#define R_PAR1_DELAY__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_DELAY + 0))
+#define R_PAR1_DELAY__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_DELAY + 0))
+#else /* REG_NO_SHADOW */
+#define R_PAR1_DELAY__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_PAR1_DELAY__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PAR1_DELAY__STYPECAST REG_STYPECAST_UDWORD
+#define R_PAR1_DELAY__SVAL REG_SVAL_SHADOW
+#define R_PAR1_DELAY__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR1_DELAY__TYPECAST REG_TYPECAST_UDWORD
+#define R_PAR1_DELAY__TYPE (REG_UDWORD)
+#define R_PAR1_DELAY__GET REG_GET_WO
+#define R_PAR1_DELAY__IGET REG_IGET_WO
+#define R_PAR1_DELAY__SET REG_SET_WO
+#define R_PAR1_DELAY__ISET REG_ISET_WO
+#define R_PAR1_DELAY__SET_VAL REG_SET_VAL_WO
+#define R_PAR1_DELAY__EQL REG_EQL_WO
+#define R_PAR1_DELAY__IEQL REG_IEQL_WO
+#define R_PAR1_DELAY__RD REG_RD_WO
+#define R_PAR1_DELAY__IRD REG_IRD_WO
+#define R_PAR1_DELAY__WR REG_WR_WO
+#define R_PAR1_DELAY__IWR REG_IWR_WO
+
+#define R_PAR1_DELAY__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PAR1_DELAY__fine_hold__fine_hold__MASK 0x00e00000U
+#define R_PAR1_DELAY__hold__hold__MASK 0x001f0000U
+#define R_PAR1_DELAY__fine_strb__fine_strb__MASK 0x0000e000U
+#define R_PAR1_DELAY__strobe__strobe__MASK 0x00001f00U
+#define R_PAR1_DELAY__fine_setup__fine_setup__MASK 0x000000e0U
+#define R_PAR1_DELAY__setup__setup__MASK 0x0000001fU
+
+#define R_PAR1_DELAY__fine_hold__MAX 0x7
+#define R_PAR1_DELAY__hold__MAX 0x1f
+#define R_PAR1_DELAY__fine_strb__MAX 0x7
+#define R_PAR1_DELAY__strobe__MAX 0x1f
+#define R_PAR1_DELAY__fine_setup__MAX 0x7
+#define R_PAR1_DELAY__setup__MAX 0x1f
+
+#define R_PAR1_DELAY__fine_hold__MIN 0
+#define R_PAR1_DELAY__hold__MIN 0
+#define R_PAR1_DELAY__fine_strb__MIN 0
+#define R_PAR1_DELAY__strobe__MIN 0
+#define R_PAR1_DELAY__fine_setup__MIN 0
+#define R_PAR1_DELAY__setup__MIN 0
+
+#define R_PAR1_DELAY__fine_hold__BITNR 21
+#define R_PAR1_DELAY__hold__BITNR 16
+#define R_PAR1_DELAY__fine_strb__BITNR 13
+#define R_PAR1_DELAY__strobe__BITNR 8
+#define R_PAR1_DELAY__fine_setup__BITNR 5
+#define R_PAR1_DELAY__setup__BITNR 0
+
+#define R_PAR1_DELAY__fine_hold__fine_hold__VAL REG_VAL_VAL
+#define R_PAR1_DELAY__hold__hold__VAL REG_VAL_VAL
+#define R_PAR1_DELAY__fine_strb__fine_strb__VAL REG_VAL_VAL
+#define R_PAR1_DELAY__strobe__strobe__VAL REG_VAL_VAL
+#define R_PAR1_DELAY__fine_setup__fine_setup__VAL REG_VAL_VAL
+#define R_PAR1_DELAY__setup__setup__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PAR1_STATUS
+ * - type: RO
+ * - addr: 0xb0000052
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR1_STATUS__ADDR (REG_TYPECAST_UWORD 0xb0000052)
+#define R_PAR1_STATUS__SVAL REG_SVAL_SHADOW
+#define R_PAR1_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR1_STATUS__TYPECAST REG_TYPECAST_UWORD
+#define R_PAR1_STATUS__TYPE (REG_UWORD)
+#define R_PAR1_STATUS__GET REG_GET_RO
+#define R_PAR1_STATUS__IGET REG_IGET_RO
+#define R_PAR1_STATUS__SET REG_SET_RO
+#define R_PAR1_STATUS__ISET REG_ISET_RO
+#define R_PAR1_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_PAR1_STATUS__EQL REG_EQL_RO
+#define R_PAR1_STATUS__IEQL REG_IEQL_RO
+#define R_PAR1_STATUS__RD REG_RD_RO
+#define R_PAR1_STATUS__IRD REG_IRD_RO
+#define R_PAR1_STATUS__WR REG_WR_RO
+#define R_PAR1_STATUS__IWR REG_IWR_RO
+
+#define R_PAR1_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_PAR1_STATUS__mode__mode__MASK 0x0000e000U
+#define R_PAR1_STATUS__perr__perr__MASK 0x00001000U
+#define R_PAR1_STATUS__ack__ack__MASK 0x00000800U
+#define R_PAR1_STATUS__busy__busy__MASK 0x00000400U
+#define R_PAR1_STATUS__fault__fault__MASK 0x00000200U
+#define R_PAR1_STATUS__sel__sel__MASK 0x00000100U
+#define R_PAR1_STATUS__ext_mode__ext_mode__MASK 0x00000080U
+#define R_PAR1_STATUS__tr_rdy__tr_rdy__MASK 0x00000002U
+#define R_PAR1_STATUS__dav__dav__MASK 0x00000001U
+
+#define R_PAR1_STATUS__mode__MAX 0x7
+#define R_PAR1_STATUS__perr__MAX 0x1
+#define R_PAR1_STATUS__ack__MAX 0x1
+#define R_PAR1_STATUS__busy__MAX 0x1
+#define R_PAR1_STATUS__fault__MAX 0x1
+#define R_PAR1_STATUS__sel__MAX 0x1
+#define R_PAR1_STATUS__ext_mode__MAX 0x1
+#define R_PAR1_STATUS__tr_rdy__MAX 0x1
+#define R_PAR1_STATUS__dav__MAX 0x1
+
+#define R_PAR1_STATUS__mode__MIN 0
+#define R_PAR1_STATUS__perr__MIN 0
+#define R_PAR1_STATUS__ack__MIN 0
+#define R_PAR1_STATUS__busy__MIN 0
+#define R_PAR1_STATUS__fault__MIN 0
+#define R_PAR1_STATUS__sel__MIN 0
+#define R_PAR1_STATUS__ext_mode__MIN 0
+#define R_PAR1_STATUS__tr_rdy__MIN 0
+#define R_PAR1_STATUS__dav__MIN 0
+
+#define R_PAR1_STATUS__mode__BITNR 13
+#define R_PAR1_STATUS__perr__BITNR 12
+#define R_PAR1_STATUS__ack__BITNR 11
+#define R_PAR1_STATUS__busy__BITNR 10
+#define R_PAR1_STATUS__fault__BITNR 9
+#define R_PAR1_STATUS__sel__BITNR 8
+#define R_PAR1_STATUS__ext_mode__BITNR 7
+#define R_PAR1_STATUS__tr_rdy__BITNR 1
+#define R_PAR1_STATUS__dav__BITNR 0
+
+#define R_PAR1_STATUS__mode__mode__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS__perr__perr__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS__ack__ack__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS__busy__busy__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS__fault__fault__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS__sel__sel__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS__ext_mode__ext_mode__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS__dav__dav__VAL REG_VAL_ENUM
+
+#define R_PAR1_STATUS__mode__mode__byte 4
+#define R_PAR1_STATUS__mode__mode__centronics 1
+#define R_PAR1_STATUS__mode__mode__ecp_fwd 5
+#define R_PAR1_STATUS__mode__mode__ecp_rev 6
+#define R_PAR1_STATUS__mode__mode__epp_rd 0
+#define R_PAR1_STATUS__mode__mode__epp_wr1 5
+#define R_PAR1_STATUS__mode__mode__epp_wr2 6
+#define R_PAR1_STATUS__mode__mode__epp_wr3 7
+#define R_PAR1_STATUS__mode__mode__fastbyte 2
+#define R_PAR1_STATUS__mode__mode__manual 0
+#define R_PAR1_STATUS__mode__mode__nibble 3
+#define R_PAR1_STATUS__mode__mode__off 7
+#define R_PAR1_STATUS__perr__perr__active 1
+#define R_PAR1_STATUS__perr__perr__inactive 0
+#define R_PAR1_STATUS__ack__ack__active 0
+#define R_PAR1_STATUS__ack__ack__inactive 1
+#define R_PAR1_STATUS__busy__busy__active 1
+#define R_PAR1_STATUS__busy__busy__inactive 0
+#define R_PAR1_STATUS__fault__fault__active 0
+#define R_PAR1_STATUS__fault__fault__inactive 1
+#define R_PAR1_STATUS__sel__sel__active 1
+#define R_PAR1_STATUS__sel__sel__inactive 0
+#define R_PAR1_STATUS__ext_mode__ext_mode__disable 0
+#define R_PAR1_STATUS__ext_mode__ext_mode__enable 1
+#define R_PAR1_STATUS__tr_rdy__tr_rdy__busy 0
+#define R_PAR1_STATUS__tr_rdy__tr_rdy__ready 1
+#define R_PAR1_STATUS__dav__dav__data 1
+#define R_PAR1_STATUS__dav__dav__nodata 0
+
+#endif
+
+/*
+ * R_PAR1_STATUS_DATA
+ * - type: RO
+ * - addr: 0xb0000050
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR1_STATUS_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050)
+#define R_PAR1_STATUS_DATA__SVAL REG_SVAL_SHADOW
+#define R_PAR1_STATUS_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR1_STATUS_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_PAR1_STATUS_DATA__TYPE (REG_UDWORD)
+#define R_PAR1_STATUS_DATA__GET REG_GET_RO
+#define R_PAR1_STATUS_DATA__IGET REG_IGET_RO
+#define R_PAR1_STATUS_DATA__SET REG_SET_RO
+#define R_PAR1_STATUS_DATA__ISET REG_ISET_RO
+#define R_PAR1_STATUS_DATA__SET_VAL REG_SET_VAL_RO
+#define R_PAR1_STATUS_DATA__EQL REG_EQL_RO
+#define R_PAR1_STATUS_DATA__IEQL REG_IEQL_RO
+#define R_PAR1_STATUS_DATA__RD REG_RD_RO
+#define R_PAR1_STATUS_DATA__IRD REG_IRD_RO
+#define R_PAR1_STATUS_DATA__WR REG_WR_RO
+#define R_PAR1_STATUS_DATA__IWR REG_IWR_RO
+
+#define R_PAR1_STATUS_DATA__READ(addr) \
+ (*(addr))
+
+#define R_PAR1_STATUS_DATA__mode__mode__MASK 0xe0000000U
+#define R_PAR1_STATUS_DATA__perr__perr__MASK 0x10000000U
+#define R_PAR1_STATUS_DATA__ack__ack__MASK 0x08000000U
+#define R_PAR1_STATUS_DATA__busy__busy__MASK 0x04000000U
+#define R_PAR1_STATUS_DATA__fault__fault__MASK 0x02000000U
+#define R_PAR1_STATUS_DATA__sel__sel__MASK 0x01000000U
+#define R_PAR1_STATUS_DATA__ext_mode__ext_mode__MASK 0x00800000U
+#define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__MASK 0x00020000U
+#define R_PAR1_STATUS_DATA__dav__dav__MASK 0x00010000U
+#define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__MASK 0x00000100U
+#define R_PAR1_STATUS_DATA__data__data__MASK 0x000000ffU
+
+#define R_PAR1_STATUS_DATA__mode__MAX 0x7
+#define R_PAR1_STATUS_DATA__perr__MAX 0x1
+#define R_PAR1_STATUS_DATA__ack__MAX 0x1
+#define R_PAR1_STATUS_DATA__busy__MAX 0x1
+#define R_PAR1_STATUS_DATA__fault__MAX 0x1
+#define R_PAR1_STATUS_DATA__sel__MAX 0x1
+#define R_PAR1_STATUS_DATA__ext_mode__MAX 0x1
+#define R_PAR1_STATUS_DATA__tr_rdy__MAX 0x1
+#define R_PAR1_STATUS_DATA__dav__MAX 0x1
+#define R_PAR1_STATUS_DATA__ecp_cmd__MAX 0x1
+#define R_PAR1_STATUS_DATA__data__MAX 0xff
+
+#define R_PAR1_STATUS_DATA__mode__MIN 0
+#define R_PAR1_STATUS_DATA__perr__MIN 0
+#define R_PAR1_STATUS_DATA__ack__MIN 0
+#define R_PAR1_STATUS_DATA__busy__MIN 0
+#define R_PAR1_STATUS_DATA__fault__MIN 0
+#define R_PAR1_STATUS_DATA__sel__MIN 0
+#define R_PAR1_STATUS_DATA__ext_mode__MIN 0
+#define R_PAR1_STATUS_DATA__tr_rdy__MIN 0
+#define R_PAR1_STATUS_DATA__dav__MIN 0
+#define R_PAR1_STATUS_DATA__ecp_cmd__MIN 0
+#define R_PAR1_STATUS_DATA__data__MIN 0
+
+#define R_PAR1_STATUS_DATA__mode__BITNR 29
+#define R_PAR1_STATUS_DATA__perr__BITNR 28
+#define R_PAR1_STATUS_DATA__ack__BITNR 27
+#define R_PAR1_STATUS_DATA__busy__BITNR 26
+#define R_PAR1_STATUS_DATA__fault__BITNR 25
+#define R_PAR1_STATUS_DATA__sel__BITNR 24
+#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23
+#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17
+#define R_PAR1_STATUS_DATA__dav__BITNR 16
+#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8
+#define R_PAR1_STATUS_DATA__data__BITNR 0
+
+#define R_PAR1_STATUS_DATA__mode__mode__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__perr__perr__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__ack__ack__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__busy__busy__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__fault__fault__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__sel__sel__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__ext_mode__ext_mode__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__dav__dav__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__VAL REG_VAL_ENUM
+#define R_PAR1_STATUS_DATA__data__data__VAL REG_VAL_VAL
+
+#define R_PAR1_STATUS_DATA__mode__mode__byte 4
+#define R_PAR1_STATUS_DATA__mode__mode__centronics 1
+#define R_PAR1_STATUS_DATA__mode__mode__ecp_fwd 5
+#define R_PAR1_STATUS_DATA__mode__mode__ecp_rev 6
+#define R_PAR1_STATUS_DATA__mode__mode__epp_rd 0
+#define R_PAR1_STATUS_DATA__mode__mode__epp_wr1 5
+#define R_PAR1_STATUS_DATA__mode__mode__epp_wr2 6
+#define R_PAR1_STATUS_DATA__mode__mode__epp_wr3 7
+#define R_PAR1_STATUS_DATA__mode__mode__fastbyte 2
+#define R_PAR1_STATUS_DATA__mode__mode__manual 0
+#define R_PAR1_STATUS_DATA__mode__mode__nibble 3
+#define R_PAR1_STATUS_DATA__mode__mode__off 7
+#define R_PAR1_STATUS_DATA__perr__perr__active 1
+#define R_PAR1_STATUS_DATA__perr__perr__inactive 0
+#define R_PAR1_STATUS_DATA__ack__ack__active 0
+#define R_PAR1_STATUS_DATA__ack__ack__inactive 1
+#define R_PAR1_STATUS_DATA__busy__busy__active 1
+#define R_PAR1_STATUS_DATA__busy__busy__inactive 0
+#define R_PAR1_STATUS_DATA__fault__fault__active 0
+#define R_PAR1_STATUS_DATA__fault__fault__inactive 1
+#define R_PAR1_STATUS_DATA__sel__sel__active 1
+#define R_PAR1_STATUS_DATA__sel__sel__inactive 0
+#define R_PAR1_STATUS_DATA__ext_mode__ext_mode__disable 0
+#define R_PAR1_STATUS_DATA__ext_mode__ext_mode__enable 1
+#define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__busy 0
+#define R_PAR1_STATUS_DATA__tr_rdy__tr_rdy__ready 1
+#define R_PAR1_STATUS_DATA__dav__dav__data 1
+#define R_PAR1_STATUS_DATA__dav__dav__nodata 0
+#define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__command 1
+#define R_PAR1_STATUS_DATA__ecp_cmd__ecp_cmd__data 0
+
+#endif
+
+/*
+ * R_PAR_ECP16_DATA
+ * - type: RW
+ * - addr: 0xb0000040
+ * - group: Parallel printer port registers
+ */
+
+#if USE_GROUP__Parallel_printer_port_registers
+
+#define R_PAR_ECP16_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000040)
+#define R_PAR_ECP16_DATA__SVAL REG_SVAL_SHADOW
+#define R_PAR_ECP16_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_PAR_ECP16_DATA__TYPECAST REG_TYPECAST_UWORD
+#define R_PAR_ECP16_DATA__TYPE (REG_UWORD)
+#define R_PAR_ECP16_DATA__GET REG_GET_RW
+#define R_PAR_ECP16_DATA__IGET REG_IGET_RW
+#define R_PAR_ECP16_DATA__SET REG_SET_RW
+#define R_PAR_ECP16_DATA__ISET REG_ISET_RW
+#define R_PAR_ECP16_DATA__SET_VAL REG_SET_VAL_RW
+#define R_PAR_ECP16_DATA__EQL REG_EQL_RW
+#define R_PAR_ECP16_DATA__IEQL REG_IEQL_RW
+#define R_PAR_ECP16_DATA__RD REG_RD_RW
+#define R_PAR_ECP16_DATA__IRD REG_IRD_RW
+#define R_PAR_ECP16_DATA__WR REG_WR_RW
+#define R_PAR_ECP16_DATA__IWR REG_IWR_RW
+
+#define R_PAR_ECP16_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_PAR_ECP16_DATA__READ(addr) \
+ (*(addr))
+
+#define R_PAR_ECP16_DATA__data__data__MASK 0x0000ffffU
+
+#define R_PAR_ECP16_DATA__data__MAX 0xffff
+
+#define R_PAR_ECP16_DATA__data__MIN 0
+
+#define R_PAR_ECP16_DATA__data__BITNR 0
+
+#define R_PAR_ECP16_DATA__data__data__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PHY_COUNTERS
+ * - type: RO
+ * - addr: 0xb00000ac
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_PHY_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000ac)
+#define R_PHY_COUNTERS__SVAL REG_SVAL_SHADOW
+#define R_PHY_COUNTERS__SVAL_I REG_SVAL_I_SHADOW
+#define R_PHY_COUNTERS__TYPECAST REG_TYPECAST_UDWORD
+#define R_PHY_COUNTERS__TYPE (REG_UDWORD)
+#define R_PHY_COUNTERS__GET REG_GET_RO
+#define R_PHY_COUNTERS__IGET REG_IGET_RO
+#define R_PHY_COUNTERS__SET REG_SET_RO
+#define R_PHY_COUNTERS__ISET REG_ISET_RO
+#define R_PHY_COUNTERS__SET_VAL REG_SET_VAL_RO
+#define R_PHY_COUNTERS__EQL REG_EQL_RO
+#define R_PHY_COUNTERS__IEQL REG_IEQL_RO
+#define R_PHY_COUNTERS__RD REG_RD_RO
+#define R_PHY_COUNTERS__IRD REG_IRD_RO
+#define R_PHY_COUNTERS__WR REG_WR_RO
+#define R_PHY_COUNTERS__IWR REG_IWR_RO
+
+#define R_PHY_COUNTERS__READ(addr) \
+ (*(addr))
+
+#define R_PHY_COUNTERS__sqe_test_error__sqe_test_error__MASK 0x0000ff00U
+#define R_PHY_COUNTERS__carrier_loss__carrier_loss__MASK 0x000000ffU
+
+#define R_PHY_COUNTERS__sqe_test_error__MAX 0xff
+#define R_PHY_COUNTERS__carrier_loss__MAX 0xff
+
+#define R_PHY_COUNTERS__sqe_test_error__MIN 0
+#define R_PHY_COUNTERS__carrier_loss__MIN 0
+
+#define R_PHY_COUNTERS__sqe_test_error__BITNR 8
+#define R_PHY_COUNTERS__carrier_loss__BITNR 0
+
+#define R_PHY_COUNTERS__sqe_test_error__sqe_test_error__VAL REG_VAL_VAL
+#define R_PHY_COUNTERS__carrier_loss__carrier_loss__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PORT_G_DATA
+ * - type: RW
+ * - addr: 0xb0000028
+ * - group: General config registers
+ */
+
+#if USE_GROUP__General_config_registers
+
+#define R_PORT_G_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000028)
+#define R_PORT_G_DATA__SVAL REG_SVAL_SHADOW
+#define R_PORT_G_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_G_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_PORT_G_DATA__TYPE (REG_UDWORD)
+#define R_PORT_G_DATA__GET REG_GET_RW
+#define R_PORT_G_DATA__IGET REG_IGET_RW
+#define R_PORT_G_DATA__SET REG_SET_RW
+#define R_PORT_G_DATA__ISET REG_ISET_RW
+#define R_PORT_G_DATA__SET_VAL REG_SET_VAL_RW
+#define R_PORT_G_DATA__EQL REG_EQL_RW
+#define R_PORT_G_DATA__IEQL REG_IEQL_RW
+#define R_PORT_G_DATA__RD REG_RD_RW
+#define R_PORT_G_DATA__IRD REG_IRD_RW
+#define R_PORT_G_DATA__WR REG_WR_RW
+#define R_PORT_G_DATA__IWR REG_IWR_RW
+
+#define R_PORT_G_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_PORT_G_DATA__READ(addr) \
+ (*(addr))
+
+#define R_PORT_G_DATA__data__data__MASK 0xffffffffU
+
+#define R_PORT_G_DATA__data__MAX 0xffffffff
+
+#define R_PORT_G_DATA__data__MIN 0
+
+#define R_PORT_G_DATA__data__BITNR 0
+
+#define R_PORT_G_DATA__data__data__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PORT_PA_DATA
+ * - type: WO
+ * - addr: 0xb0000030
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PA_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000030)
+
+#ifndef REG_NO_SHADOW
+#define R_PORT_PA_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PA_SET + 0))
+#define R_PORT_PA_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PA_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_PORT_PA_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_PORT_PA_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PORT_PA_DATA__STYPECAST REG_STYPECAST_BYTE
+#define R_PORT_PA_DATA__SVAL REG_SVAL_SHADOW
+#define R_PORT_PA_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PA_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_PORT_PA_DATA__TYPE (REG_BYTE)
+#define R_PORT_PA_DATA__GET REG_GET_WO
+#define R_PORT_PA_DATA__IGET REG_IGET_WO
+#define R_PORT_PA_DATA__SET REG_SET_WO
+#define R_PORT_PA_DATA__ISET REG_ISET_WO
+#define R_PORT_PA_DATA__SET_VAL REG_SET_VAL_WO
+#define R_PORT_PA_DATA__EQL REG_EQL_WO
+#define R_PORT_PA_DATA__IEQL REG_IEQL_WO
+#define R_PORT_PA_DATA__RD REG_RD_WO
+#define R_PORT_PA_DATA__IRD REG_IRD_WO
+#define R_PORT_PA_DATA__WR REG_WR_WO
+#define R_PORT_PA_DATA__IWR REG_IWR_WO
+
+#define R_PORT_PA_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PORT_PA_DATA__data_out__data_out__MASK 0x000000ffU
+
+#define R_PORT_PA_DATA__data_out__MAX 255
+
+#define R_PORT_PA_DATA__data_out__MIN 0
+
+#define R_PORT_PA_DATA__data_out__BITNR 0
+
+#define R_PORT_PA_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PORT_PA_DIR
+ * - type: WO
+ * - addr: 0xb0000031
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PA_DIR__ADDR (REG_TYPECAST_BYTE 0xb0000031)
+
+#ifndef REG_NO_SHADOW
+#define R_PORT_PA_DIR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PA_SET + 1))
+#define R_PORT_PA_DIR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PA_SET + 1))
+#else /* REG_NO_SHADOW */
+#define R_PORT_PA_DIR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_PORT_PA_DIR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PORT_PA_DIR__STYPECAST REG_STYPECAST_BYTE
+#define R_PORT_PA_DIR__SVAL REG_SVAL_SHADOW
+#define R_PORT_PA_DIR__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PA_DIR__TYPECAST REG_TYPECAST_BYTE
+#define R_PORT_PA_DIR__TYPE (REG_BYTE)
+#define R_PORT_PA_DIR__GET REG_GET_WO
+#define R_PORT_PA_DIR__IGET REG_IGET_WO
+#define R_PORT_PA_DIR__SET REG_SET_WO
+#define R_PORT_PA_DIR__ISET REG_ISET_WO
+#define R_PORT_PA_DIR__SET_VAL REG_SET_VAL_WO
+#define R_PORT_PA_DIR__EQL REG_EQL_WO
+#define R_PORT_PA_DIR__IEQL REG_IEQL_WO
+#define R_PORT_PA_DIR__RD REG_RD_WO
+#define R_PORT_PA_DIR__IRD REG_IRD_WO
+#define R_PORT_PA_DIR__WR REG_WR_WO
+#define R_PORT_PA_DIR__IWR REG_IWR_WO
+
+#define R_PORT_PA_DIR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PORT_PA_DIR__dir7__dir7__MASK 0x00000080U
+#define R_PORT_PA_DIR__dir6__dir6__MASK 0x00000040U
+#define R_PORT_PA_DIR__dir5__dir5__MASK 0x00000020U
+#define R_PORT_PA_DIR__dir4__dir4__MASK 0x00000010U
+#define R_PORT_PA_DIR__dir3__dir3__MASK 0x00000008U
+#define R_PORT_PA_DIR__dir2__dir2__MASK 0x00000004U
+#define R_PORT_PA_DIR__dir1__dir1__MASK 0x00000002U
+#define R_PORT_PA_DIR__dir0__dir0__MASK 0x00000001U
+
+#define R_PORT_PA_DIR__dir7__MAX 0x1
+#define R_PORT_PA_DIR__dir6__MAX 0x1
+#define R_PORT_PA_DIR__dir5__MAX 0x1
+#define R_PORT_PA_DIR__dir4__MAX 0x1
+#define R_PORT_PA_DIR__dir3__MAX 0x1
+#define R_PORT_PA_DIR__dir2__MAX 0x1
+#define R_PORT_PA_DIR__dir1__MAX 0x1
+#define R_PORT_PA_DIR__dir0__MAX 0x1
+
+#define R_PORT_PA_DIR__dir7__MIN 0
+#define R_PORT_PA_DIR__dir6__MIN 0
+#define R_PORT_PA_DIR__dir5__MIN 0
+#define R_PORT_PA_DIR__dir4__MIN 0
+#define R_PORT_PA_DIR__dir3__MIN 0
+#define R_PORT_PA_DIR__dir2__MIN 0
+#define R_PORT_PA_DIR__dir1__MIN 0
+#define R_PORT_PA_DIR__dir0__MIN 0
+
+#define R_PORT_PA_DIR__dir7__BITNR 7
+#define R_PORT_PA_DIR__dir6__BITNR 6
+#define R_PORT_PA_DIR__dir5__BITNR 5
+#define R_PORT_PA_DIR__dir4__BITNR 4
+#define R_PORT_PA_DIR__dir3__BITNR 3
+#define R_PORT_PA_DIR__dir2__BITNR 2
+#define R_PORT_PA_DIR__dir1__BITNR 1
+#define R_PORT_PA_DIR__dir0__BITNR 0
+
+#define R_PORT_PA_DIR__dir7__dir7__VAL REG_VAL_ENUM
+#define R_PORT_PA_DIR__dir6__dir6__VAL REG_VAL_ENUM
+#define R_PORT_PA_DIR__dir5__dir5__VAL REG_VAL_ENUM
+#define R_PORT_PA_DIR__dir4__dir4__VAL REG_VAL_ENUM
+#define R_PORT_PA_DIR__dir3__dir3__VAL REG_VAL_ENUM
+#define R_PORT_PA_DIR__dir2__dir2__VAL REG_VAL_ENUM
+#define R_PORT_PA_DIR__dir1__dir1__VAL REG_VAL_ENUM
+#define R_PORT_PA_DIR__dir0__dir0__VAL REG_VAL_ENUM
+
+#define R_PORT_PA_DIR__dir7__dir7__input 0
+#define R_PORT_PA_DIR__dir7__dir7__output 1
+#define R_PORT_PA_DIR__dir6__dir6__input 0
+#define R_PORT_PA_DIR__dir6__dir6__output 1
+#define R_PORT_PA_DIR__dir5__dir5__input 0
+#define R_PORT_PA_DIR__dir5__dir5__output 1
+#define R_PORT_PA_DIR__dir4__dir4__input 0
+#define R_PORT_PA_DIR__dir4__dir4__output 1
+#define R_PORT_PA_DIR__dir3__dir3__input 0
+#define R_PORT_PA_DIR__dir3__dir3__output 1
+#define R_PORT_PA_DIR__dir2__dir2__input 0
+#define R_PORT_PA_DIR__dir2__dir2__output 1
+#define R_PORT_PA_DIR__dir1__dir1__input 0
+#define R_PORT_PA_DIR__dir1__dir1__output 1
+#define R_PORT_PA_DIR__dir0__dir0__input 0
+#define R_PORT_PA_DIR__dir0__dir0__output 1
+
+#endif
+
+/*
+ * R_PORT_PA_READ
+ * - type: RO
+ * - addr: 0xb0000030
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PA_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000030)
+#define R_PORT_PA_READ__SVAL REG_SVAL_SHADOW
+#define R_PORT_PA_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PA_READ__TYPECAST REG_TYPECAST_UDWORD
+#define R_PORT_PA_READ__TYPE (REG_UDWORD)
+#define R_PORT_PA_READ__GET REG_GET_RO
+#define R_PORT_PA_READ__IGET REG_IGET_RO
+#define R_PORT_PA_READ__SET REG_SET_RO
+#define R_PORT_PA_READ__ISET REG_ISET_RO
+#define R_PORT_PA_READ__SET_VAL REG_SET_VAL_RO
+#define R_PORT_PA_READ__EQL REG_EQL_RO
+#define R_PORT_PA_READ__IEQL REG_IEQL_RO
+#define R_PORT_PA_READ__RD REG_RD_RO
+#define R_PORT_PA_READ__IRD REG_IRD_RO
+#define R_PORT_PA_READ__WR REG_WR_RO
+#define R_PORT_PA_READ__IWR REG_IWR_RO
+
+#define R_PORT_PA_READ__READ(addr) \
+ (*(addr))
+
+#define R_PORT_PA_READ__data_in__data_in__MASK 0x000000ffU
+
+#define R_PORT_PA_READ__data_in__MAX 255
+
+#define R_PORT_PA_READ__data_in__MIN 0
+
+#define R_PORT_PA_READ__data_in__BITNR 0
+
+#define R_PORT_PA_READ__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PORT_PA_SET
+ * - type: WO
+ * - addr: 0xb0000030
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PA_SET__ADDR (REG_TYPECAST_UDWORD 0xb0000030)
+
+#ifndef REG_NO_SHADOW
+#define R_PORT_PA_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PORT_PA_SET + 0))
+#define R_PORT_PA_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PORT_PA_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_PORT_PA_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_PORT_PA_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PORT_PA_SET__STYPECAST REG_STYPECAST_UDWORD
+#define R_PORT_PA_SET__SVAL REG_SVAL_SHADOW
+#define R_PORT_PA_SET__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PA_SET__TYPECAST REG_TYPECAST_UDWORD
+#define R_PORT_PA_SET__TYPE (REG_UDWORD)
+#define R_PORT_PA_SET__GET REG_GET_WO
+#define R_PORT_PA_SET__IGET REG_IGET_WO
+#define R_PORT_PA_SET__SET REG_SET_WO
+#define R_PORT_PA_SET__ISET REG_ISET_WO
+#define R_PORT_PA_SET__SET_VAL REG_SET_VAL_WO
+#define R_PORT_PA_SET__EQL REG_EQL_WO
+#define R_PORT_PA_SET__IEQL REG_IEQL_WO
+#define R_PORT_PA_SET__RD REG_RD_WO
+#define R_PORT_PA_SET__IRD REG_IRD_WO
+#define R_PORT_PA_SET__WR REG_WR_WO
+#define R_PORT_PA_SET__IWR REG_IWR_WO
+
+#define R_PORT_PA_SET__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PORT_PA_SET__dir7__dir7__MASK 0x00008000U
+#define R_PORT_PA_SET__dir6__dir6__MASK 0x00004000U
+#define R_PORT_PA_SET__dir5__dir5__MASK 0x00002000U
+#define R_PORT_PA_SET__dir4__dir4__MASK 0x00001000U
+#define R_PORT_PA_SET__dir3__dir3__MASK 0x00000800U
+#define R_PORT_PA_SET__dir2__dir2__MASK 0x00000400U
+#define R_PORT_PA_SET__dir1__dir1__MASK 0x00000200U
+#define R_PORT_PA_SET__dir0__dir0__MASK 0x00000100U
+#define R_PORT_PA_SET__data_out__data_out__MASK 0x000000ffU
+
+#define R_PORT_PA_SET__dir7__MAX 0x1
+#define R_PORT_PA_SET__dir6__MAX 0x1
+#define R_PORT_PA_SET__dir5__MAX 0x1
+#define R_PORT_PA_SET__dir4__MAX 0x1
+#define R_PORT_PA_SET__dir3__MAX 0x1
+#define R_PORT_PA_SET__dir2__MAX 0x1
+#define R_PORT_PA_SET__dir1__MAX 0x1
+#define R_PORT_PA_SET__dir0__MAX 0x1
+#define R_PORT_PA_SET__data_out__MAX 255
+
+#define R_PORT_PA_SET__dir7__MIN 0
+#define R_PORT_PA_SET__dir6__MIN 0
+#define R_PORT_PA_SET__dir5__MIN 0
+#define R_PORT_PA_SET__dir4__MIN 0
+#define R_PORT_PA_SET__dir3__MIN 0
+#define R_PORT_PA_SET__dir2__MIN 0
+#define R_PORT_PA_SET__dir1__MIN 0
+#define R_PORT_PA_SET__dir0__MIN 0
+#define R_PORT_PA_SET__data_out__MIN 0
+
+#define R_PORT_PA_SET__dir7__BITNR 15
+#define R_PORT_PA_SET__dir6__BITNR 14
+#define R_PORT_PA_SET__dir5__BITNR 13
+#define R_PORT_PA_SET__dir4__BITNR 12
+#define R_PORT_PA_SET__dir3__BITNR 11
+#define R_PORT_PA_SET__dir2__BITNR 10
+#define R_PORT_PA_SET__dir1__BITNR 9
+#define R_PORT_PA_SET__dir0__BITNR 8
+#define R_PORT_PA_SET__data_out__BITNR 0
+
+#define R_PORT_PA_SET__dir7__dir7__VAL REG_VAL_ENUM
+#define R_PORT_PA_SET__dir6__dir6__VAL REG_VAL_ENUM
+#define R_PORT_PA_SET__dir5__dir5__VAL REG_VAL_ENUM
+#define R_PORT_PA_SET__dir4__dir4__VAL REG_VAL_ENUM
+#define R_PORT_PA_SET__dir3__dir3__VAL REG_VAL_ENUM
+#define R_PORT_PA_SET__dir2__dir2__VAL REG_VAL_ENUM
+#define R_PORT_PA_SET__dir1__dir1__VAL REG_VAL_ENUM
+#define R_PORT_PA_SET__dir0__dir0__VAL REG_VAL_ENUM
+#define R_PORT_PA_SET__data_out__data_out__VAL REG_VAL_VAL
+
+#define R_PORT_PA_SET__dir7__dir7__input 0
+#define R_PORT_PA_SET__dir7__dir7__output 1
+#define R_PORT_PA_SET__dir6__dir6__input 0
+#define R_PORT_PA_SET__dir6__dir6__output 1
+#define R_PORT_PA_SET__dir5__dir5__input 0
+#define R_PORT_PA_SET__dir5__dir5__output 1
+#define R_PORT_PA_SET__dir4__dir4__input 0
+#define R_PORT_PA_SET__dir4__dir4__output 1
+#define R_PORT_PA_SET__dir3__dir3__input 0
+#define R_PORT_PA_SET__dir3__dir3__output 1
+#define R_PORT_PA_SET__dir2__dir2__input 0
+#define R_PORT_PA_SET__dir2__dir2__output 1
+#define R_PORT_PA_SET__dir1__dir1__input 0
+#define R_PORT_PA_SET__dir1__dir1__output 1
+#define R_PORT_PA_SET__dir0__dir0__input 0
+#define R_PORT_PA_SET__dir0__dir0__output 1
+
+#endif
+
+/*
+ * R_PORT_PB_CONFIG
+ * - type: WO
+ * - addr: 0xb000003a
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PB_CONFIG__ADDR (REG_TYPECAST_BYTE 0xb000003a)
+
+#ifndef REG_NO_SHADOW
+#define R_PORT_PB_CONFIG__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 2))
+#define R_PORT_PB_CONFIG__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 2))
+#else /* REG_NO_SHADOW */
+#define R_PORT_PB_CONFIG__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_PORT_PB_CONFIG__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PORT_PB_CONFIG__STYPECAST REG_STYPECAST_BYTE
+#define R_PORT_PB_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_PORT_PB_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PB_CONFIG__TYPECAST REG_TYPECAST_BYTE
+#define R_PORT_PB_CONFIG__TYPE (REG_BYTE)
+#define R_PORT_PB_CONFIG__GET REG_GET_WO
+#define R_PORT_PB_CONFIG__IGET REG_IGET_WO
+#define R_PORT_PB_CONFIG__SET REG_SET_WO
+#define R_PORT_PB_CONFIG__ISET REG_ISET_WO
+#define R_PORT_PB_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_PORT_PB_CONFIG__EQL REG_EQL_WO
+#define R_PORT_PB_CONFIG__IEQL REG_IEQL_WO
+#define R_PORT_PB_CONFIG__RD REG_RD_WO
+#define R_PORT_PB_CONFIG__IRD REG_IRD_WO
+#define R_PORT_PB_CONFIG__WR REG_WR_WO
+#define R_PORT_PB_CONFIG__IWR REG_IWR_WO
+
+#define R_PORT_PB_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PORT_PB_CONFIG__cs7__cs7__MASK 0x00000080U
+#define R_PORT_PB_CONFIG__cs6__cs6__MASK 0x00000040U
+#define R_PORT_PB_CONFIG__cs5__cs5__MASK 0x00000020U
+#define R_PORT_PB_CONFIG__cs4__cs4__MASK 0x00000010U
+#define R_PORT_PB_CONFIG__cs3__cs3__MASK 0x00000008U
+#define R_PORT_PB_CONFIG__cs2__cs2__MASK 0x00000004U
+#define R_PORT_PB_CONFIG__scsi1__scsi1__MASK 0x00000002U
+#define R_PORT_PB_CONFIG__scsi0__scsi0__MASK 0x00000001U
+
+#define R_PORT_PB_CONFIG__cs7__MAX 0x1
+#define R_PORT_PB_CONFIG__cs6__MAX 0x1
+#define R_PORT_PB_CONFIG__cs5__MAX 0x1
+#define R_PORT_PB_CONFIG__cs4__MAX 0x1
+#define R_PORT_PB_CONFIG__cs3__MAX 0x1
+#define R_PORT_PB_CONFIG__cs2__MAX 0x1
+#define R_PORT_PB_CONFIG__scsi1__MAX 0x1
+#define R_PORT_PB_CONFIG__scsi0__MAX 0x1
+
+#define R_PORT_PB_CONFIG__cs7__MIN 0
+#define R_PORT_PB_CONFIG__cs6__MIN 0
+#define R_PORT_PB_CONFIG__cs5__MIN 0
+#define R_PORT_PB_CONFIG__cs4__MIN 0
+#define R_PORT_PB_CONFIG__cs3__MIN 0
+#define R_PORT_PB_CONFIG__cs2__MIN 0
+#define R_PORT_PB_CONFIG__scsi1__MIN 0
+#define R_PORT_PB_CONFIG__scsi0__MIN 0
+
+#define R_PORT_PB_CONFIG__cs7__BITNR 7
+#define R_PORT_PB_CONFIG__cs6__BITNR 6
+#define R_PORT_PB_CONFIG__cs5__BITNR 5
+#define R_PORT_PB_CONFIG__cs4__BITNR 4
+#define R_PORT_PB_CONFIG__cs3__BITNR 3
+#define R_PORT_PB_CONFIG__cs2__BITNR 2
+#define R_PORT_PB_CONFIG__scsi1__BITNR 1
+#define R_PORT_PB_CONFIG__scsi0__BITNR 0
+
+#define R_PORT_PB_CONFIG__cs7__cs7__VAL REG_VAL_ENUM
+#define R_PORT_PB_CONFIG__cs6__cs6__VAL REG_VAL_ENUM
+#define R_PORT_PB_CONFIG__cs5__cs5__VAL REG_VAL_ENUM
+#define R_PORT_PB_CONFIG__cs4__cs4__VAL REG_VAL_ENUM
+#define R_PORT_PB_CONFIG__cs3__cs3__VAL REG_VAL_ENUM
+#define R_PORT_PB_CONFIG__cs2__cs2__VAL REG_VAL_ENUM
+#define R_PORT_PB_CONFIG__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_PORT_PB_CONFIG__scsi0__scsi0__VAL REG_VAL_ENUM
+
+#define R_PORT_PB_CONFIG__cs7__cs7__cs 1
+#define R_PORT_PB_CONFIG__cs7__cs7__port 0
+#define R_PORT_PB_CONFIG__cs6__cs6__cs 1
+#define R_PORT_PB_CONFIG__cs6__cs6__port 0
+#define R_PORT_PB_CONFIG__cs5__cs5__cs 1
+#define R_PORT_PB_CONFIG__cs5__cs5__port 0
+#define R_PORT_PB_CONFIG__cs4__cs4__cs 1
+#define R_PORT_PB_CONFIG__cs4__cs4__port 0
+#define R_PORT_PB_CONFIG__cs3__cs3__cs 1
+#define R_PORT_PB_CONFIG__cs3__cs3__port 0
+#define R_PORT_PB_CONFIG__cs2__cs2__cs 1
+#define R_PORT_PB_CONFIG__cs2__cs2__port 0
+#define R_PORT_PB_CONFIG__scsi1__scsi1__enph 1
+#define R_PORT_PB_CONFIG__scsi1__scsi1__port_cs 0
+#define R_PORT_PB_CONFIG__scsi0__scsi0__enph 1
+#define R_PORT_PB_CONFIG__scsi0__scsi0__port_cs 0
+
+#endif
+
+/*
+ * R_PORT_PB_DATA
+ * - type: WO
+ * - addr: 0xb0000038
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PB_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000038)
+
+#ifndef REG_NO_SHADOW
+#define R_PORT_PB_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 0))
+#define R_PORT_PB_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_PORT_PB_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_PORT_PB_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PORT_PB_DATA__STYPECAST REG_STYPECAST_BYTE
+#define R_PORT_PB_DATA__SVAL REG_SVAL_SHADOW
+#define R_PORT_PB_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PB_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_PORT_PB_DATA__TYPE (REG_BYTE)
+#define R_PORT_PB_DATA__GET REG_GET_WO
+#define R_PORT_PB_DATA__IGET REG_IGET_WO
+#define R_PORT_PB_DATA__SET REG_SET_WO
+#define R_PORT_PB_DATA__ISET REG_ISET_WO
+#define R_PORT_PB_DATA__SET_VAL REG_SET_VAL_WO
+#define R_PORT_PB_DATA__EQL REG_EQL_WO
+#define R_PORT_PB_DATA__IEQL REG_IEQL_WO
+#define R_PORT_PB_DATA__RD REG_RD_WO
+#define R_PORT_PB_DATA__IRD REG_IRD_WO
+#define R_PORT_PB_DATA__WR REG_WR_WO
+#define R_PORT_PB_DATA__IWR REG_IWR_WO
+
+#define R_PORT_PB_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PORT_PB_DATA__data_out__data_out__MASK 0x000000ffU
+
+#define R_PORT_PB_DATA__data_out__MAX 255
+
+#define R_PORT_PB_DATA__data_out__MIN 0
+
+#define R_PORT_PB_DATA__data_out__BITNR 0
+
+#define R_PORT_PB_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PORT_PB_DIR
+ * - type: WO
+ * - addr: 0xb0000039
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PB_DIR__ADDR (REG_TYPECAST_BYTE 0xb0000039)
+
+#ifndef REG_NO_SHADOW
+#define R_PORT_PB_DIR__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 1))
+#define R_PORT_PB_DIR__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 1))
+#else /* REG_NO_SHADOW */
+#define R_PORT_PB_DIR__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_PORT_PB_DIR__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PORT_PB_DIR__STYPECAST REG_STYPECAST_BYTE
+#define R_PORT_PB_DIR__SVAL REG_SVAL_SHADOW
+#define R_PORT_PB_DIR__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PB_DIR__TYPECAST REG_TYPECAST_BYTE
+#define R_PORT_PB_DIR__TYPE (REG_BYTE)
+#define R_PORT_PB_DIR__GET REG_GET_WO
+#define R_PORT_PB_DIR__IGET REG_IGET_WO
+#define R_PORT_PB_DIR__SET REG_SET_WO
+#define R_PORT_PB_DIR__ISET REG_ISET_WO
+#define R_PORT_PB_DIR__SET_VAL REG_SET_VAL_WO
+#define R_PORT_PB_DIR__EQL REG_EQL_WO
+#define R_PORT_PB_DIR__IEQL REG_IEQL_WO
+#define R_PORT_PB_DIR__RD REG_RD_WO
+#define R_PORT_PB_DIR__IRD REG_IRD_WO
+#define R_PORT_PB_DIR__WR REG_WR_WO
+#define R_PORT_PB_DIR__IWR REG_IWR_WO
+
+#define R_PORT_PB_DIR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PORT_PB_DIR__dir7__dir7__MASK 0x00000080U
+#define R_PORT_PB_DIR__dir6__dir6__MASK 0x00000040U
+#define R_PORT_PB_DIR__dir5__dir5__MASK 0x00000020U
+#define R_PORT_PB_DIR__dir4__dir4__MASK 0x00000010U
+#define R_PORT_PB_DIR__dir3__dir3__MASK 0x00000008U
+#define R_PORT_PB_DIR__dir2__dir2__MASK 0x00000004U
+#define R_PORT_PB_DIR__dir1__dir1__MASK 0x00000002U
+#define R_PORT_PB_DIR__dir0__dir0__MASK 0x00000001U
+
+#define R_PORT_PB_DIR__dir7__MAX 0x1
+#define R_PORT_PB_DIR__dir6__MAX 0x1
+#define R_PORT_PB_DIR__dir5__MAX 0x1
+#define R_PORT_PB_DIR__dir4__MAX 0x1
+#define R_PORT_PB_DIR__dir3__MAX 0x1
+#define R_PORT_PB_DIR__dir2__MAX 0x1
+#define R_PORT_PB_DIR__dir1__MAX 0x1
+#define R_PORT_PB_DIR__dir0__MAX 0x1
+
+#define R_PORT_PB_DIR__dir7__MIN 0
+#define R_PORT_PB_DIR__dir6__MIN 0
+#define R_PORT_PB_DIR__dir5__MIN 0
+#define R_PORT_PB_DIR__dir4__MIN 0
+#define R_PORT_PB_DIR__dir3__MIN 0
+#define R_PORT_PB_DIR__dir2__MIN 0
+#define R_PORT_PB_DIR__dir1__MIN 0
+#define R_PORT_PB_DIR__dir0__MIN 0
+
+#define R_PORT_PB_DIR__dir7__BITNR 7
+#define R_PORT_PB_DIR__dir6__BITNR 6
+#define R_PORT_PB_DIR__dir5__BITNR 5
+#define R_PORT_PB_DIR__dir4__BITNR 4
+#define R_PORT_PB_DIR__dir3__BITNR 3
+#define R_PORT_PB_DIR__dir2__BITNR 2
+#define R_PORT_PB_DIR__dir1__BITNR 1
+#define R_PORT_PB_DIR__dir0__BITNR 0
+
+#define R_PORT_PB_DIR__dir7__dir7__VAL REG_VAL_ENUM
+#define R_PORT_PB_DIR__dir6__dir6__VAL REG_VAL_ENUM
+#define R_PORT_PB_DIR__dir5__dir5__VAL REG_VAL_ENUM
+#define R_PORT_PB_DIR__dir4__dir4__VAL REG_VAL_ENUM
+#define R_PORT_PB_DIR__dir3__dir3__VAL REG_VAL_ENUM
+#define R_PORT_PB_DIR__dir2__dir2__VAL REG_VAL_ENUM
+#define R_PORT_PB_DIR__dir1__dir1__VAL REG_VAL_ENUM
+#define R_PORT_PB_DIR__dir0__dir0__VAL REG_VAL_ENUM
+
+#define R_PORT_PB_DIR__dir7__dir7__input 0
+#define R_PORT_PB_DIR__dir7__dir7__output 1
+#define R_PORT_PB_DIR__dir6__dir6__input 0
+#define R_PORT_PB_DIR__dir6__dir6__output 1
+#define R_PORT_PB_DIR__dir5__dir5__input 0
+#define R_PORT_PB_DIR__dir5__dir5__output 1
+#define R_PORT_PB_DIR__dir4__dir4__input 0
+#define R_PORT_PB_DIR__dir4__dir4__output 1
+#define R_PORT_PB_DIR__dir3__dir3__input 0
+#define R_PORT_PB_DIR__dir3__dir3__output 1
+#define R_PORT_PB_DIR__dir2__dir2__input 0
+#define R_PORT_PB_DIR__dir2__dir2__output 1
+#define R_PORT_PB_DIR__dir1__dir1__input 0
+#define R_PORT_PB_DIR__dir1__dir1__output 1
+#define R_PORT_PB_DIR__dir0__dir0__input 0
+#define R_PORT_PB_DIR__dir0__dir0__output 1
+
+#endif
+
+/*
+ * R_PORT_PB_I2C
+ * - type: WO
+ * - addr: 0xb000003b
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PB_I2C__ADDR (REG_TYPECAST_BYTE 0xb000003b)
+
+#ifndef REG_NO_SHADOW
+#define R_PORT_PB_I2C__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PORT_PB_SET + 3))
+#define R_PORT_PB_I2C__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PORT_PB_SET + 3))
+#else /* REG_NO_SHADOW */
+#define R_PORT_PB_I2C__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_PORT_PB_I2C__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PORT_PB_I2C__STYPECAST REG_STYPECAST_BYTE
+#define R_PORT_PB_I2C__SVAL REG_SVAL_SHADOW
+#define R_PORT_PB_I2C__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PB_I2C__TYPECAST REG_TYPECAST_BYTE
+#define R_PORT_PB_I2C__TYPE (REG_BYTE)
+#define R_PORT_PB_I2C__GET REG_GET_WO
+#define R_PORT_PB_I2C__IGET REG_IGET_WO
+#define R_PORT_PB_I2C__SET REG_SET_WO
+#define R_PORT_PB_I2C__ISET REG_ISET_WO
+#define R_PORT_PB_I2C__SET_VAL REG_SET_VAL_WO
+#define R_PORT_PB_I2C__EQL REG_EQL_WO
+#define R_PORT_PB_I2C__IEQL REG_IEQL_WO
+#define R_PORT_PB_I2C__RD REG_RD_WO
+#define R_PORT_PB_I2C__IRD REG_IRD_WO
+#define R_PORT_PB_I2C__WR REG_WR_WO
+#define R_PORT_PB_I2C__IWR REG_IWR_WO
+
+#define R_PORT_PB_I2C__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PORT_PB_I2C__syncser3__syncser3__MASK 0x00000020U
+#define R_PORT_PB_I2C__syncser1__syncser1__MASK 0x00000010U
+#define R_PORT_PB_I2C__i2c_en__i2c_en__MASK 0x00000008U
+#define R_PORT_PB_I2C__i2c_d__i2c_d__MASK 0x00000004U
+#define R_PORT_PB_I2C__i2c_clk__i2c_clk__MASK 0x00000002U
+#define R_PORT_PB_I2C__i2c_oe___i2c_oe___MASK 0x00000001U
+
+#define R_PORT_PB_I2C__syncser3__MAX 0x1
+#define R_PORT_PB_I2C__syncser1__MAX 0x1
+#define R_PORT_PB_I2C__i2c_en__MAX 0x1
+#define R_PORT_PB_I2C__i2c_d__MAX 1
+#define R_PORT_PB_I2C__i2c_clk__MAX 1
+#define R_PORT_PB_I2C__i2c_oe___MAX 0x1
+
+#define R_PORT_PB_I2C__syncser3__MIN 0
+#define R_PORT_PB_I2C__syncser1__MIN 0
+#define R_PORT_PB_I2C__i2c_en__MIN 0
+#define R_PORT_PB_I2C__i2c_d__MIN 0
+#define R_PORT_PB_I2C__i2c_clk__MIN 0
+#define R_PORT_PB_I2C__i2c_oe___MIN 0
+
+#define R_PORT_PB_I2C__syncser3__BITNR 5
+#define R_PORT_PB_I2C__syncser1__BITNR 4
+#define R_PORT_PB_I2C__i2c_en__BITNR 3
+#define R_PORT_PB_I2C__i2c_d__BITNR 2
+#define R_PORT_PB_I2C__i2c_clk__BITNR 1
+#define R_PORT_PB_I2C__i2c_oe___BITNR 0
+
+#define R_PORT_PB_I2C__syncser3__syncser3__VAL REG_VAL_ENUM
+#define R_PORT_PB_I2C__syncser1__syncser1__VAL REG_VAL_ENUM
+#define R_PORT_PB_I2C__i2c_en__i2c_en__VAL REG_VAL_ENUM
+#define R_PORT_PB_I2C__i2c_d__i2c_d__VAL REG_VAL_VAL
+#define R_PORT_PB_I2C__i2c_clk__i2c_clk__VAL REG_VAL_VAL
+#define R_PORT_PB_I2C__i2c_oe___i2c_oe___VAL REG_VAL_ENUM
+
+#define R_PORT_PB_I2C__syncser3__syncser3__port_cs 0
+#define R_PORT_PB_I2C__syncser3__syncser3__ss3extra 1
+#define R_PORT_PB_I2C__syncser1__syncser1__port_cs 0
+#define R_PORT_PB_I2C__syncser1__syncser1__ss1extra 1
+#define R_PORT_PB_I2C__i2c_en__i2c_en__off 0
+#define R_PORT_PB_I2C__i2c_en__i2c_en__on 1
+#define R_PORT_PB_I2C__i2c_oe___i2c_oe___disable 1
+#define R_PORT_PB_I2C__i2c_oe___i2c_oe___enable 0
+
+#endif
+
+/*
+ * R_PORT_PB_READ
+ * - type: RO
+ * - addr: 0xb0000038
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PB_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000038)
+#define R_PORT_PB_READ__SVAL REG_SVAL_SHADOW
+#define R_PORT_PB_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PB_READ__TYPECAST REG_TYPECAST_UDWORD
+#define R_PORT_PB_READ__TYPE (REG_UDWORD)
+#define R_PORT_PB_READ__GET REG_GET_RO
+#define R_PORT_PB_READ__IGET REG_IGET_RO
+#define R_PORT_PB_READ__SET REG_SET_RO
+#define R_PORT_PB_READ__ISET REG_ISET_RO
+#define R_PORT_PB_READ__SET_VAL REG_SET_VAL_RO
+#define R_PORT_PB_READ__EQL REG_EQL_RO
+#define R_PORT_PB_READ__IEQL REG_IEQL_RO
+#define R_PORT_PB_READ__RD REG_RD_RO
+#define R_PORT_PB_READ__IRD REG_IRD_RO
+#define R_PORT_PB_READ__WR REG_WR_RO
+#define R_PORT_PB_READ__IWR REG_IWR_RO
+
+#define R_PORT_PB_READ__READ(addr) \
+ (*(addr))
+
+#define R_PORT_PB_READ__data_in__data_in__MASK 0x000000ffU
+
+#define R_PORT_PB_READ__data_in__MAX 255
+
+#define R_PORT_PB_READ__data_in__MIN 0
+
+#define R_PORT_PB_READ__data_in__BITNR 0
+
+#define R_PORT_PB_READ__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_PORT_PB_SET
+ * - type: WO
+ * - addr: 0xb0000038
+ * - group: General port configuration registers
+ */
+
+#if USE_GROUP__General_port_configuration_registers
+
+#define R_PORT_PB_SET__ADDR (REG_TYPECAST_UDWORD 0xb0000038)
+
+#ifndef REG_NO_SHADOW
+#define R_PORT_PB_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PORT_PB_SET + 0))
+#define R_PORT_PB_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PORT_PB_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_PORT_PB_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_PORT_PB_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_PORT_PB_SET__STYPECAST REG_STYPECAST_UDWORD
+#define R_PORT_PB_SET__SVAL REG_SVAL_SHADOW
+#define R_PORT_PB_SET__SVAL_I REG_SVAL_I_SHADOW
+#define R_PORT_PB_SET__TYPECAST REG_TYPECAST_UDWORD
+#define R_PORT_PB_SET__TYPE (REG_UDWORD)
+#define R_PORT_PB_SET__GET REG_GET_WO
+#define R_PORT_PB_SET__IGET REG_IGET_WO
+#define R_PORT_PB_SET__SET REG_SET_WO
+#define R_PORT_PB_SET__ISET REG_ISET_WO
+#define R_PORT_PB_SET__SET_VAL REG_SET_VAL_WO
+#define R_PORT_PB_SET__EQL REG_EQL_WO
+#define R_PORT_PB_SET__IEQL REG_IEQL_WO
+#define R_PORT_PB_SET__RD REG_RD_WO
+#define R_PORT_PB_SET__IRD REG_IRD_WO
+#define R_PORT_PB_SET__WR REG_WR_WO
+#define R_PORT_PB_SET__IWR REG_IWR_WO
+
+#define R_PORT_PB_SET__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_PORT_PB_SET__syncser3__syncser3__MASK 0x20000000U
+#define R_PORT_PB_SET__syncser1__syncser1__MASK 0x10000000U
+#define R_PORT_PB_SET__i2c_en__i2c_en__MASK 0x08000000U
+#define R_PORT_PB_SET__i2c_d__i2c_d__MASK 0x04000000U
+#define R_PORT_PB_SET__i2c_clk__i2c_clk__MASK 0x02000000U
+#define R_PORT_PB_SET__i2c_oe___i2c_oe___MASK 0x01000000U
+#define R_PORT_PB_SET__cs7__cs7__MASK 0x00800000U
+#define R_PORT_PB_SET__cs6__cs6__MASK 0x00400000U
+#define R_PORT_PB_SET__cs5__cs5__MASK 0x00200000U
+#define R_PORT_PB_SET__cs4__cs4__MASK 0x00100000U
+#define R_PORT_PB_SET__cs3__cs3__MASK 0x00080000U
+#define R_PORT_PB_SET__cs2__cs2__MASK 0x00040000U
+#define R_PORT_PB_SET__scsi1__scsi1__MASK 0x00020000U
+#define R_PORT_PB_SET__scsi0__scsi0__MASK 0x00010000U
+#define R_PORT_PB_SET__dir7__dir7__MASK 0x00008000U
+#define R_PORT_PB_SET__dir6__dir6__MASK 0x00004000U
+#define R_PORT_PB_SET__dir5__dir5__MASK 0x00002000U
+#define R_PORT_PB_SET__dir4__dir4__MASK 0x00001000U
+#define R_PORT_PB_SET__dir3__dir3__MASK 0x00000800U
+#define R_PORT_PB_SET__dir2__dir2__MASK 0x00000400U
+#define R_PORT_PB_SET__dir1__dir1__MASK 0x00000200U
+#define R_PORT_PB_SET__dir0__dir0__MASK 0x00000100U
+#define R_PORT_PB_SET__data_out__data_out__MASK 0x000000ffU
+
+#define R_PORT_PB_SET__syncser3__MAX 0x1
+#define R_PORT_PB_SET__syncser1__MAX 0x1
+#define R_PORT_PB_SET__i2c_en__MAX 0x1
+#define R_PORT_PB_SET__i2c_d__MAX 1
+#define R_PORT_PB_SET__i2c_clk__MAX 1
+#define R_PORT_PB_SET__i2c_oe___MAX 0x1
+#define R_PORT_PB_SET__cs7__MAX 0x1
+#define R_PORT_PB_SET__cs6__MAX 0x1
+#define R_PORT_PB_SET__cs5__MAX 0x1
+#define R_PORT_PB_SET__cs4__MAX 0x1
+#define R_PORT_PB_SET__cs3__MAX 0x1
+#define R_PORT_PB_SET__cs2__MAX 0x1
+#define R_PORT_PB_SET__scsi1__MAX 0x1
+#define R_PORT_PB_SET__scsi0__MAX 0x1
+#define R_PORT_PB_SET__dir7__MAX 0x1
+#define R_PORT_PB_SET__dir6__MAX 0x1
+#define R_PORT_PB_SET__dir5__MAX 0x1
+#define R_PORT_PB_SET__dir4__MAX 0x1
+#define R_PORT_PB_SET__dir3__MAX 0x1
+#define R_PORT_PB_SET__dir2__MAX 0x1
+#define R_PORT_PB_SET__dir1__MAX 0x1
+#define R_PORT_PB_SET__dir0__MAX 0x1
+#define R_PORT_PB_SET__data_out__MAX 255
+
+#define R_PORT_PB_SET__syncser3__MIN 0
+#define R_PORT_PB_SET__syncser1__MIN 0
+#define R_PORT_PB_SET__i2c_en__MIN 0
+#define R_PORT_PB_SET__i2c_d__MIN 0
+#define R_PORT_PB_SET__i2c_clk__MIN 0
+#define R_PORT_PB_SET__i2c_oe___MIN 0
+#define R_PORT_PB_SET__cs7__MIN 0
+#define R_PORT_PB_SET__cs6__MIN 0
+#define R_PORT_PB_SET__cs5__MIN 0
+#define R_PORT_PB_SET__cs4__MIN 0
+#define R_PORT_PB_SET__cs3__MIN 0
+#define R_PORT_PB_SET__cs2__MIN 0
+#define R_PORT_PB_SET__scsi1__MIN 0
+#define R_PORT_PB_SET__scsi0__MIN 0
+#define R_PORT_PB_SET__dir7__MIN 0
+#define R_PORT_PB_SET__dir6__MIN 0
+#define R_PORT_PB_SET__dir5__MIN 0
+#define R_PORT_PB_SET__dir4__MIN 0
+#define R_PORT_PB_SET__dir3__MIN 0
+#define R_PORT_PB_SET__dir2__MIN 0
+#define R_PORT_PB_SET__dir1__MIN 0
+#define R_PORT_PB_SET__dir0__MIN 0
+#define R_PORT_PB_SET__data_out__MIN 0
+
+#define R_PORT_PB_SET__syncser3__BITNR 29
+#define R_PORT_PB_SET__syncser1__BITNR 28
+#define R_PORT_PB_SET__i2c_en__BITNR 27
+#define R_PORT_PB_SET__i2c_d__BITNR 26
+#define R_PORT_PB_SET__i2c_clk__BITNR 25
+#define R_PORT_PB_SET__i2c_oe___BITNR 24
+#define R_PORT_PB_SET__cs7__BITNR 23
+#define R_PORT_PB_SET__cs6__BITNR 22
+#define R_PORT_PB_SET__cs5__BITNR 21
+#define R_PORT_PB_SET__cs4__BITNR 20
+#define R_PORT_PB_SET__cs3__BITNR 19
+#define R_PORT_PB_SET__cs2__BITNR 18
+#define R_PORT_PB_SET__scsi1__BITNR 17
+#define R_PORT_PB_SET__scsi0__BITNR 16
+#define R_PORT_PB_SET__dir7__BITNR 15
+#define R_PORT_PB_SET__dir6__BITNR 14
+#define R_PORT_PB_SET__dir5__BITNR 13
+#define R_PORT_PB_SET__dir4__BITNR 12
+#define R_PORT_PB_SET__dir3__BITNR 11
+#define R_PORT_PB_SET__dir2__BITNR 10
+#define R_PORT_PB_SET__dir1__BITNR 9
+#define R_PORT_PB_SET__dir0__BITNR 8
+#define R_PORT_PB_SET__data_out__BITNR 0
+
+#define R_PORT_PB_SET__syncser3__syncser3__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__syncser1__syncser1__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__i2c_en__i2c_en__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__i2c_d__i2c_d__VAL REG_VAL_VAL
+#define R_PORT_PB_SET__i2c_clk__i2c_clk__VAL REG_VAL_VAL
+#define R_PORT_PB_SET__i2c_oe___i2c_oe___VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__cs7__cs7__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__cs6__cs6__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__cs5__cs5__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__cs4__cs4__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__cs3__cs3__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__cs2__cs2__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__dir7__dir7__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__dir6__dir6__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__dir5__dir5__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__dir4__dir4__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__dir3__dir3__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__dir2__dir2__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__dir1__dir1__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__dir0__dir0__VAL REG_VAL_ENUM
+#define R_PORT_PB_SET__data_out__data_out__VAL REG_VAL_VAL
+
+#define R_PORT_PB_SET__syncser3__syncser3__port_cs 0
+#define R_PORT_PB_SET__syncser3__syncser3__ss3extra 1
+#define R_PORT_PB_SET__syncser1__syncser1__port_cs 0
+#define R_PORT_PB_SET__syncser1__syncser1__ss1extra 1
+#define R_PORT_PB_SET__i2c_en__i2c_en__off 0
+#define R_PORT_PB_SET__i2c_en__i2c_en__on 1
+#define R_PORT_PB_SET__i2c_oe___i2c_oe___disable 1
+#define R_PORT_PB_SET__i2c_oe___i2c_oe___enable 0
+#define R_PORT_PB_SET__cs7__cs7__cs 1
+#define R_PORT_PB_SET__cs7__cs7__port 0
+#define R_PORT_PB_SET__cs6__cs6__cs 1
+#define R_PORT_PB_SET__cs6__cs6__port 0
+#define R_PORT_PB_SET__cs5__cs5__cs 1
+#define R_PORT_PB_SET__cs5__cs5__port 0
+#define R_PORT_PB_SET__cs4__cs4__cs 1
+#define R_PORT_PB_SET__cs4__cs4__port 0
+#define R_PORT_PB_SET__cs3__cs3__cs 1
+#define R_PORT_PB_SET__cs3__cs3__port 0
+#define R_PORT_PB_SET__cs2__cs2__cs 1
+#define R_PORT_PB_SET__cs2__cs2__port 0
+#define R_PORT_PB_SET__scsi1__scsi1__enph 1
+#define R_PORT_PB_SET__scsi1__scsi1__port_cs 0
+#define R_PORT_PB_SET__scsi0__scsi0__enph 1
+#define R_PORT_PB_SET__scsi0__scsi0__port_cs 0
+#define R_PORT_PB_SET__dir7__dir7__input 0
+#define R_PORT_PB_SET__dir7__dir7__output 1
+#define R_PORT_PB_SET__dir6__dir6__input 0
+#define R_PORT_PB_SET__dir6__dir6__output 1
+#define R_PORT_PB_SET__dir5__dir5__input 0
+#define R_PORT_PB_SET__dir5__dir5__output 1
+#define R_PORT_PB_SET__dir4__dir4__input 0
+#define R_PORT_PB_SET__dir4__dir4__output 1
+#define R_PORT_PB_SET__dir3__dir3__input 0
+#define R_PORT_PB_SET__dir3__dir3__output 1
+#define R_PORT_PB_SET__dir2__dir2__input 0
+#define R_PORT_PB_SET__dir2__dir2__output 1
+#define R_PORT_PB_SET__dir1__dir1__input 0
+#define R_PORT_PB_SET__dir1__dir1__output 1
+#define R_PORT_PB_SET__dir0__dir0__input 0
+#define R_PORT_PB_SET__dir0__dir0__output 1
+
+#endif
+
+/*
+ * R_PRESCALE_STATUS
+ * - type: RO
+ * - addr: 0xb00000f0
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_PRESCALE_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb00000f0)
+#define R_PRESCALE_STATUS__SVAL REG_SVAL_SHADOW
+#define R_PRESCALE_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_PRESCALE_STATUS__TYPECAST REG_TYPECAST_UDWORD
+#define R_PRESCALE_STATUS__TYPE (REG_UDWORD)
+#define R_PRESCALE_STATUS__GET REG_GET_RO
+#define R_PRESCALE_STATUS__IGET REG_IGET_RO
+#define R_PRESCALE_STATUS__SET REG_SET_RO
+#define R_PRESCALE_STATUS__ISET REG_ISET_RO
+#define R_PRESCALE_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_PRESCALE_STATUS__EQL REG_EQL_RO
+#define R_PRESCALE_STATUS__IEQL REG_IEQL_RO
+#define R_PRESCALE_STATUS__RD REG_RD_RO
+#define R_PRESCALE_STATUS__IRD REG_IRD_RO
+#define R_PRESCALE_STATUS__WR REG_WR_RO
+#define R_PRESCALE_STATUS__IWR REG_IWR_RO
+
+#define R_PRESCALE_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_PRESCALE_STATUS__ser_status__ser_status__MASK 0xffff0000U
+#define R_PRESCALE_STATUS__tim_status__tim_status__MASK 0x0000ffffU
+
+#define R_PRESCALE_STATUS__ser_status__MAX 0xffff
+#define R_PRESCALE_STATUS__tim_status__MAX 0xffff
+
+#define R_PRESCALE_STATUS__ser_status__MIN 0
+#define R_PRESCALE_STATUS__tim_status__MIN 0
+
+#define R_PRESCALE_STATUS__ser_status__BITNR 16
+#define R_PRESCALE_STATUS__tim_status__BITNR 0
+
+#define R_PRESCALE_STATUS__ser_status__ser_status__VAL REG_VAL_VAL
+#define R_PRESCALE_STATUS__tim_status__tim_status__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_REC_COUNTERS
+ * - type: RO
+ * - addr: 0xb00000a4
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_REC_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000a4)
+#define R_REC_COUNTERS__SVAL REG_SVAL_SHADOW
+#define R_REC_COUNTERS__SVAL_I REG_SVAL_I_SHADOW
+#define R_REC_COUNTERS__TYPECAST REG_TYPECAST_UDWORD
+#define R_REC_COUNTERS__TYPE (REG_UDWORD)
+#define R_REC_COUNTERS__GET REG_GET_RO
+#define R_REC_COUNTERS__IGET REG_IGET_RO
+#define R_REC_COUNTERS__SET REG_SET_RO
+#define R_REC_COUNTERS__ISET REG_ISET_RO
+#define R_REC_COUNTERS__SET_VAL REG_SET_VAL_RO
+#define R_REC_COUNTERS__EQL REG_EQL_RO
+#define R_REC_COUNTERS__IEQL REG_IEQL_RO
+#define R_REC_COUNTERS__RD REG_RD_RO
+#define R_REC_COUNTERS__IRD REG_IRD_RO
+#define R_REC_COUNTERS__WR REG_WR_RO
+#define R_REC_COUNTERS__IWR REG_IWR_RO
+
+#define R_REC_COUNTERS__READ(addr) \
+ (*(addr))
+
+#define R_REC_COUNTERS__congestion__congestion__MASK 0xff000000U
+#define R_REC_COUNTERS__oversize__oversize__MASK 0x00ff0000U
+#define R_REC_COUNTERS__alignment_error__alignment_error__MASK 0x0000ff00U
+#define R_REC_COUNTERS__crc_error__crc_error__MASK 0x000000ffU
+
+#define R_REC_COUNTERS__congestion__MAX 0xff
+#define R_REC_COUNTERS__oversize__MAX 0xff
+#define R_REC_COUNTERS__alignment_error__MAX 0xff
+#define R_REC_COUNTERS__crc_error__MAX 0xff
+
+#define R_REC_COUNTERS__congestion__MIN 0
+#define R_REC_COUNTERS__oversize__MIN 0
+#define R_REC_COUNTERS__alignment_error__MIN 0
+#define R_REC_COUNTERS__crc_error__MIN 0
+
+#define R_REC_COUNTERS__congestion__BITNR 24
+#define R_REC_COUNTERS__oversize__BITNR 16
+#define R_REC_COUNTERS__alignment_error__BITNR 8
+#define R_REC_COUNTERS__crc_error__BITNR 0
+
+#define R_REC_COUNTERS__congestion__congestion__VAL REG_VAL_VAL
+#define R_REC_COUNTERS__oversize__oversize__VAL REG_VAL_VAL
+#define R_REC_COUNTERS__alignment_error__alignment_error__VAL REG_VAL_VAL
+#define R_REC_COUNTERS__crc_error__crc_error__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SCSI0_CMD
+ * - type: WO
+ * - addr: 0xb0000042
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI0_CMD__ADDR (REG_TYPECAST_BYTE 0xb0000042)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI0_CMD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 2))
+#define R_SCSI0_CMD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 2))
+#else /* REG_NO_SHADOW */
+#define R_SCSI0_CMD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SCSI0_CMD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI0_CMD__STYPECAST REG_STYPECAST_BYTE
+#define R_SCSI0_CMD__SVAL REG_SVAL_SHADOW
+#define R_SCSI0_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI0_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_SCSI0_CMD__TYPE (REG_BYTE)
+#define R_SCSI0_CMD__GET REG_GET_WO
+#define R_SCSI0_CMD__IGET REG_IGET_WO
+#define R_SCSI0_CMD__SET REG_SET_WO
+#define R_SCSI0_CMD__ISET REG_ISET_WO
+#define R_SCSI0_CMD__SET_VAL REG_SET_VAL_WO
+#define R_SCSI0_CMD__EQL REG_EQL_WO
+#define R_SCSI0_CMD__IEQL REG_IEQL_WO
+#define R_SCSI0_CMD__RD REG_RD_WO
+#define R_SCSI0_CMD__IRD REG_IRD_WO
+#define R_SCSI0_CMD__WR REG_WR_WO
+#define R_SCSI0_CMD__IWR REG_IWR_WO
+
+#define R_SCSI0_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SCSI0_CMD__FIRST 0
+#define R_SCSI0_CMD__IOFFSET 12
+#define R_SCSI0_CMD__LAST 1
+#define R_SCSI0_CMD__OFFSET 16
+#define R_SCSI0_CMD__SOFFSET 12
+/* end */
+
+#define R_SCSI0_CMD__asynch_setup__asynch_setup__MASK 0x000000f0U
+#define R_SCSI0_CMD__command__command__MASK 0x0000000fU
+
+#define R_SCSI0_CMD__asynch_setup__MAX 0xf
+#define R_SCSI0_CMD__command__MAX 0xf
+
+#define R_SCSI0_CMD__asynch_setup__MIN 0
+#define R_SCSI0_CMD__command__MIN 0
+
+#define R_SCSI0_CMD__asynch_setup__BITNR 4
+#define R_SCSI0_CMD__command__BITNR 0
+
+#define R_SCSI0_CMD__asynch_setup__asynch_setup__VAL REG_VAL_VAL
+#define R_SCSI0_CMD__command__command__VAL REG_VAL_ENUM
+
+#define R_SCSI0_CMD__command__command__arb_only 6
+#define R_SCSI0_CMD__command__command__full_din_1 0
+#define R_SCSI0_CMD__command__command__full_din_3 8
+#define R_SCSI0_CMD__command__command__full_dout_1 1
+#define R_SCSI0_CMD__command__command__full_dout_3 9
+#define R_SCSI0_CMD__command__command__full_stat_1 2
+#define R_SCSI0_CMD__command__command__full_stat_3 10
+#define R_SCSI0_CMD__command__command__man_data_in 11
+#define R_SCSI0_CMD__command__command__man_data_out 12
+#define R_SCSI0_CMD__command__command__man_rat 13
+#define R_SCSI0_CMD__command__command__resel_din 3
+#define R_SCSI0_CMD__command__command__resel_dout 4
+#define R_SCSI0_CMD__command__command__resel_stat 5
+
+#endif
+
+/*
+ * R_SCSI0_CMD_DATA
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI0_CMD_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI0_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
+#define R_SCSI0_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
+#else /* REG_NO_SHADOW */
+#define R_SCSI0_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SCSI0_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI0_CMD_DATA__STYPECAST REG_STYPECAST_UDWORD
+#define R_SCSI0_CMD_DATA__SVAL REG_SVAL_SHADOW
+#define R_SCSI0_CMD_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI0_CMD_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_SCSI0_CMD_DATA__TYPE (REG_UDWORD)
+#define R_SCSI0_CMD_DATA__GET REG_GET_WO
+#define R_SCSI0_CMD_DATA__IGET REG_IGET_WO
+#define R_SCSI0_CMD_DATA__SET REG_SET_WO
+#define R_SCSI0_CMD_DATA__ISET REG_ISET_WO
+#define R_SCSI0_CMD_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SCSI0_CMD_DATA__EQL REG_EQL_WO
+#define R_SCSI0_CMD_DATA__IEQL REG_IEQL_WO
+#define R_SCSI0_CMD_DATA__RD REG_RD_WO
+#define R_SCSI0_CMD_DATA__IRD REG_IRD_WO
+#define R_SCSI0_CMD_DATA__WR REG_WR_WO
+#define R_SCSI0_CMD_DATA__IWR REG_IWR_WO
+
+#define R_SCSI0_CMD_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SCSI0_CMD_DATA__FIRST 0
+#define R_SCSI0_CMD_DATA__IOFFSET 12
+#define R_SCSI0_CMD_DATA__LAST 1
+#define R_SCSI0_CMD_DATA__OFFSET 16
+#define R_SCSI0_CMD_DATA__SOFFSET 12
+/* end */
+
+#define R_SCSI0_CMD_DATA__parity_in__parity_in__MASK 0x04000000U
+#define R_SCSI0_CMD_DATA__skip__skip__MASK 0x02000000U
+#define R_SCSI0_CMD_DATA__clr_status__clr_status__MASK 0x01000000U
+#define R_SCSI0_CMD_DATA__asynch_setup__asynch_setup__MASK 0x00f00000U
+#define R_SCSI0_CMD_DATA__command__command__MASK 0x000f0000U
+#define R_SCSI0_CMD_DATA__data_out__data_out__MASK 0x0000ffffU
+
+#define R_SCSI0_CMD_DATA__parity_in__MAX 0x1
+#define R_SCSI0_CMD_DATA__skip__MAX 0x1
+#define R_SCSI0_CMD_DATA__clr_status__MAX 0x1
+#define R_SCSI0_CMD_DATA__asynch_setup__MAX 0xf
+#define R_SCSI0_CMD_DATA__command__MAX 0xf
+#define R_SCSI0_CMD_DATA__data_out__MAX 0xffff
+
+#define R_SCSI0_CMD_DATA__parity_in__MIN 0
+#define R_SCSI0_CMD_DATA__skip__MIN 0
+#define R_SCSI0_CMD_DATA__clr_status__MIN 0
+#define R_SCSI0_CMD_DATA__asynch_setup__MIN 0
+#define R_SCSI0_CMD_DATA__command__MIN 0
+#define R_SCSI0_CMD_DATA__data_out__MIN 0
+
+#define R_SCSI0_CMD_DATA__parity_in__BITNR 26
+#define R_SCSI0_CMD_DATA__skip__BITNR 25
+#define R_SCSI0_CMD_DATA__clr_status__BITNR 24
+#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20
+#define R_SCSI0_CMD_DATA__command__BITNR 16
+#define R_SCSI0_CMD_DATA__data_out__BITNR 0
+
+#define R_SCSI0_CMD_DATA__parity_in__parity_in__VAL REG_VAL_ENUM
+#define R_SCSI0_CMD_DATA__skip__skip__VAL REG_VAL_ENUM
+#define R_SCSI0_CMD_DATA__clr_status__clr_status__VAL REG_VAL_ENUM
+#define R_SCSI0_CMD_DATA__asynch_setup__asynch_setup__VAL REG_VAL_VAL
+#define R_SCSI0_CMD_DATA__command__command__VAL REG_VAL_ENUM
+#define R_SCSI0_CMD_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+#define R_SCSI0_CMD_DATA__parity_in__parity_in__off 1
+#define R_SCSI0_CMD_DATA__parity_in__parity_in__on 0
+#define R_SCSI0_CMD_DATA__skip__skip__off 0
+#define R_SCSI0_CMD_DATA__skip__skip__on 1
+#define R_SCSI0_CMD_DATA__clr_status__clr_status__nop 0
+#define R_SCSI0_CMD_DATA__clr_status__clr_status__yes 1
+#define R_SCSI0_CMD_DATA__command__command__arb_only 6
+#define R_SCSI0_CMD_DATA__command__command__full_din_1 0
+#define R_SCSI0_CMD_DATA__command__command__full_din_3 8
+#define R_SCSI0_CMD_DATA__command__command__full_dout_1 1
+#define R_SCSI0_CMD_DATA__command__command__full_dout_3 9
+#define R_SCSI0_CMD_DATA__command__command__full_stat_1 2
+#define R_SCSI0_CMD_DATA__command__command__full_stat_3 10
+#define R_SCSI0_CMD_DATA__command__command__man_data_in 11
+#define R_SCSI0_CMD_DATA__command__command__man_data_out 12
+#define R_SCSI0_CMD_DATA__command__command__man_rat 13
+#define R_SCSI0_CMD_DATA__command__command__resel_din 3
+#define R_SCSI0_CMD_DATA__command__command__resel_dout 4
+#define R_SCSI0_CMD_DATA__command__command__resel_stat 5
+
+#endif
+
+/*
+ * R_SCSI0_CTRL
+ * - type: WO
+ * - addr: 0xb0000044
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI0_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000044)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI0_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0))
+#define R_SCSI0_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_SCSI0_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SCSI0_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI0_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_SCSI0_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SCSI0_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI0_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_SCSI0_CTRL__TYPE (REG_UDWORD)
+#define R_SCSI0_CTRL__GET REG_GET_WO
+#define R_SCSI0_CTRL__IGET REG_IGET_WO
+#define R_SCSI0_CTRL__SET REG_SET_WO
+#define R_SCSI0_CTRL__ISET REG_ISET_WO
+#define R_SCSI0_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SCSI0_CTRL__EQL REG_EQL_WO
+#define R_SCSI0_CTRL__IEQL REG_IEQL_WO
+#define R_SCSI0_CTRL__RD REG_RD_WO
+#define R_SCSI0_CTRL__IRD REG_IRD_WO
+#define R_SCSI0_CTRL__WR REG_WR_WO
+#define R_SCSI0_CTRL__IWR REG_IWR_WO
+
+#define R_SCSI0_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SCSI0_CTRL__FIRST 0
+#define R_SCSI0_CTRL__IOFFSET 12
+#define R_SCSI0_CTRL__LAST 1
+#define R_SCSI0_CTRL__OFFSET 16
+#define R_SCSI0_CTRL__SOFFSET 12
+/* end */
+
+#define R_SCSI0_CTRL__id_type__id_type__MASK 0x80000000U
+#define R_SCSI0_CTRL__sel_timeout__sel_timeout__MASK 0x7f000000U
+#define R_SCSI0_CTRL__synch_per__synch_per__MASK 0x00ff0000U
+#define R_SCSI0_CTRL__rst__rst__MASK 0x00008000U
+#define R_SCSI0_CTRL__atn__atn__MASK 0x00004000U
+#define R_SCSI0_CTRL__my_id__my_id__MASK 0x00001e00U
+#define R_SCSI0_CTRL__target_id__target_id__MASK 0x000000f0U
+#define R_SCSI0_CTRL__fast_20__fast_20__MASK 0x00000008U
+#define R_SCSI0_CTRL__bus_width__bus_width__MASK 0x00000004U
+#define R_SCSI0_CTRL__synch__synch__MASK 0x00000002U
+#define R_SCSI0_CTRL__enable__enable__MASK 0x00000001U
+
+#define R_SCSI0_CTRL__id_type__MAX 0x1
+#define R_SCSI0_CTRL__sel_timeout__MAX 0x7f
+#define R_SCSI0_CTRL__synch_per__MAX 0xff
+#define R_SCSI0_CTRL__rst__MAX 0x1
+#define R_SCSI0_CTRL__atn__MAX 0x1
+#define R_SCSI0_CTRL__my_id__MAX 0xf
+#define R_SCSI0_CTRL__target_id__MAX 0xf
+#define R_SCSI0_CTRL__fast_20__MAX 0x1
+#define R_SCSI0_CTRL__bus_width__MAX 0x1
+#define R_SCSI0_CTRL__synch__MAX 0x1
+#define R_SCSI0_CTRL__enable__MAX 0x1
+
+#define R_SCSI0_CTRL__id_type__MIN 0
+#define R_SCSI0_CTRL__sel_timeout__MIN 0
+#define R_SCSI0_CTRL__synch_per__MIN 0
+#define R_SCSI0_CTRL__rst__MIN 0
+#define R_SCSI0_CTRL__atn__MIN 0
+#define R_SCSI0_CTRL__my_id__MIN 0
+#define R_SCSI0_CTRL__target_id__MIN 0
+#define R_SCSI0_CTRL__fast_20__MIN 0
+#define R_SCSI0_CTRL__bus_width__MIN 0
+#define R_SCSI0_CTRL__synch__MIN 0
+#define R_SCSI0_CTRL__enable__MIN 0
+
+#define R_SCSI0_CTRL__id_type__BITNR 31
+#define R_SCSI0_CTRL__sel_timeout__BITNR 24
+#define R_SCSI0_CTRL__synch_per__BITNR 16
+#define R_SCSI0_CTRL__rst__BITNR 15
+#define R_SCSI0_CTRL__atn__BITNR 14
+#define R_SCSI0_CTRL__my_id__BITNR 9
+#define R_SCSI0_CTRL__target_id__BITNR 4
+#define R_SCSI0_CTRL__fast_20__BITNR 3
+#define R_SCSI0_CTRL__bus_width__BITNR 2
+#define R_SCSI0_CTRL__synch__BITNR 1
+#define R_SCSI0_CTRL__enable__BITNR 0
+
+#define R_SCSI0_CTRL__id_type__id_type__VAL REG_VAL_ENUM
+#define R_SCSI0_CTRL__sel_timeout__sel_timeout__VAL REG_VAL_VAL
+#define R_SCSI0_CTRL__synch_per__synch_per__VAL REG_VAL_VAL
+#define R_SCSI0_CTRL__rst__rst__VAL REG_VAL_ENUM
+#define R_SCSI0_CTRL__atn__atn__VAL REG_VAL_ENUM
+#define R_SCSI0_CTRL__my_id__my_id__VAL REG_VAL_VAL
+#define R_SCSI0_CTRL__target_id__target_id__VAL REG_VAL_VAL
+#define R_SCSI0_CTRL__fast_20__fast_20__VAL REG_VAL_ENUM
+#define R_SCSI0_CTRL__bus_width__bus_width__VAL REG_VAL_ENUM
+#define R_SCSI0_CTRL__synch__synch__VAL REG_VAL_ENUM
+#define R_SCSI0_CTRL__enable__enable__VAL REG_VAL_ENUM
+
+#define R_SCSI0_CTRL__id_type__id_type__hardware 0
+#define R_SCSI0_CTRL__id_type__id_type__software 1
+#define R_SCSI0_CTRL__rst__rst__no 0
+#define R_SCSI0_CTRL__rst__rst__yes 1
+#define R_SCSI0_CTRL__atn__atn__no 0
+#define R_SCSI0_CTRL__atn__atn__yes 1
+#define R_SCSI0_CTRL__fast_20__fast_20__no 0
+#define R_SCSI0_CTRL__fast_20__fast_20__yes 1
+#define R_SCSI0_CTRL__bus_width__bus_width__narrow 0
+#define R_SCSI0_CTRL__bus_width__bus_width__wide 1
+#define R_SCSI0_CTRL__synch__synch__asynch 0
+#define R_SCSI0_CTRL__synch__synch__synch 1
+#define R_SCSI0_CTRL__enable__enable__off 0
+#define R_SCSI0_CTRL__enable__enable__on 1
+
+#endif
+
+/*
+ * R_SCSI0_DATA
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI0_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000040)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI0_DATA__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
+#define R_SCSI0_DATA__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
+#else /* REG_NO_SHADOW */
+#define R_SCSI0_DATA__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_SCSI0_DATA__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI0_DATA__STYPECAST REG_STYPECAST_UWORD
+#define R_SCSI0_DATA__SVAL REG_SVAL_SHADOW
+#define R_SCSI0_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI0_DATA__TYPECAST REG_TYPECAST_UWORD
+#define R_SCSI0_DATA__TYPE (REG_UWORD)
+#define R_SCSI0_DATA__GET REG_GET_WO
+#define R_SCSI0_DATA__IGET REG_IGET_WO
+#define R_SCSI0_DATA__SET REG_SET_WO
+#define R_SCSI0_DATA__ISET REG_ISET_WO
+#define R_SCSI0_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SCSI0_DATA__EQL REG_EQL_WO
+#define R_SCSI0_DATA__IEQL REG_IEQL_WO
+#define R_SCSI0_DATA__RD REG_RD_WO
+#define R_SCSI0_DATA__IRD REG_IRD_WO
+#define R_SCSI0_DATA__WR REG_WR_WO
+#define R_SCSI0_DATA__IWR REG_IWR_WO
+
+#define R_SCSI0_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SCSI0_DATA__FIRST 0
+#define R_SCSI0_DATA__IOFFSET 12
+#define R_SCSI0_DATA__LAST 1
+#define R_SCSI0_DATA__OFFSET 16
+#define R_SCSI0_DATA__SOFFSET 12
+/* end */
+
+#define R_SCSI0_DATA__data_out__data_out__MASK 0x0000ffffU
+
+#define R_SCSI0_DATA__data_out__MAX 0xffff
+
+#define R_SCSI0_DATA__data_out__MIN 0
+
+#define R_SCSI0_DATA__data_out__BITNR 0
+
+#define R_SCSI0_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SCSI0_DATA_IN
+ * - type: RO
+ * - addr: 0xb0000040
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI0_DATA_IN__ADDR (REG_TYPECAST_UWORD 0xb0000040)
+#define R_SCSI0_DATA_IN__SVAL REG_SVAL_SHADOW
+#define R_SCSI0_DATA_IN__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI0_DATA_IN__TYPECAST REG_TYPECAST_UWORD
+#define R_SCSI0_DATA_IN__TYPE (REG_UWORD)
+#define R_SCSI0_DATA_IN__GET REG_GET_RO
+#define R_SCSI0_DATA_IN__IGET REG_IGET_RO
+#define R_SCSI0_DATA_IN__SET REG_SET_RO
+#define R_SCSI0_DATA_IN__ISET REG_ISET_RO
+#define R_SCSI0_DATA_IN__SET_VAL REG_SET_VAL_RO
+#define R_SCSI0_DATA_IN__EQL REG_EQL_RO
+#define R_SCSI0_DATA_IN__IEQL REG_IEQL_RO
+#define R_SCSI0_DATA_IN__RD REG_RD_RO
+#define R_SCSI0_DATA_IN__IRD REG_IRD_RO
+#define R_SCSI0_DATA_IN__WR REG_WR_RO
+#define R_SCSI0_DATA_IN__IWR REG_IWR_RO
+
+#define R_SCSI0_DATA_IN__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SCSI0_DATA_IN__FIRST 0
+#define R_SCSI0_DATA_IN__LAST 1
+#define R_SCSI0_DATA_IN__OFFSET 16
+/* end */
+
+#define R_SCSI0_DATA_IN__data_in__data_in__MASK 0x0000ffffU
+
+#define R_SCSI0_DATA_IN__data_in__MAX 0xffff
+
+#define R_SCSI0_DATA_IN__data_in__MIN 0
+
+#define R_SCSI0_DATA_IN__data_in__BITNR 0
+
+#define R_SCSI0_DATA_IN__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SCSI0_STATUS
+ * - type: RO
+ * - addr: 0xb0000048
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI0_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000048)
+#define R_SCSI0_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SCSI0_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI0_STATUS__TYPECAST REG_TYPECAST_UDWORD
+#define R_SCSI0_STATUS__TYPE (REG_UDWORD)
+#define R_SCSI0_STATUS__GET REG_GET_RO
+#define R_SCSI0_STATUS__IGET REG_IGET_RO
+#define R_SCSI0_STATUS__SET REG_SET_RO
+#define R_SCSI0_STATUS__ISET REG_ISET_RO
+#define R_SCSI0_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SCSI0_STATUS__EQL REG_EQL_RO
+#define R_SCSI0_STATUS__IEQL REG_IEQL_RO
+#define R_SCSI0_STATUS__RD REG_RD_RO
+#define R_SCSI0_STATUS__IRD REG_IRD_RO
+#define R_SCSI0_STATUS__WR REG_WR_RO
+#define R_SCSI0_STATUS__IWR REG_IWR_RO
+
+#define R_SCSI0_STATUS__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SCSI0_STATUS__FIRST 0
+#define R_SCSI0_STATUS__LAST 1
+#define R_SCSI0_STATUS__OFFSET 16
+/* end */
+
+#define R_SCSI0_STATUS__tst_arb_won__tst_arb_won__MASK 0x00800000U
+#define R_SCSI0_STATUS__tst_resel__tst_resel__MASK 0x00400000U
+#define R_SCSI0_STATUS__parity_error__parity_error__MASK 0x00200000U
+#define R_SCSI0_STATUS__bus_reset__bus_reset__MASK 0x00100000U
+#define R_SCSI0_STATUS__resel_target__resel_target__MASK 0x00078000U
+#define R_SCSI0_STATUS__resel__resel__MASK 0x00004000U
+#define R_SCSI0_STATUS__curr_phase__curr_phase__MASK 0x00003800U
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__MASK 0x000007c0U
+#define R_SCSI0_STATUS__valid_status__valid_status__MASK 0x00000020U
+#define R_SCSI0_STATUS__seq_status__seq_status__MASK 0x0000001fU
+
+#define R_SCSI0_STATUS__tst_arb_won__MAX 0x1
+#define R_SCSI0_STATUS__tst_resel__MAX 0x1
+#define R_SCSI0_STATUS__parity_error__MAX 0x1
+#define R_SCSI0_STATUS__bus_reset__MAX 0x1
+#define R_SCSI0_STATUS__resel_target__MAX 0xf
+#define R_SCSI0_STATUS__resel__MAX 0x1
+#define R_SCSI0_STATUS__curr_phase__MAX 0x7
+#define R_SCSI0_STATUS__last_seq_step__MAX 0x1f
+#define R_SCSI0_STATUS__valid_status__MAX 0x1
+#define R_SCSI0_STATUS__seq_status__MAX 0x1f
+
+#define R_SCSI0_STATUS__tst_arb_won__MIN 0
+#define R_SCSI0_STATUS__tst_resel__MIN 0
+#define R_SCSI0_STATUS__parity_error__MIN 0
+#define R_SCSI0_STATUS__bus_reset__MIN 0
+#define R_SCSI0_STATUS__resel_target__MIN 0
+#define R_SCSI0_STATUS__resel__MIN 0
+#define R_SCSI0_STATUS__curr_phase__MIN 0
+#define R_SCSI0_STATUS__last_seq_step__MIN 0
+#define R_SCSI0_STATUS__valid_status__MIN 0
+#define R_SCSI0_STATUS__seq_status__MIN 0
+
+#define R_SCSI0_STATUS__tst_arb_won__BITNR 23
+#define R_SCSI0_STATUS__tst_resel__BITNR 22
+#define R_SCSI0_STATUS__parity_error__BITNR 21
+#define R_SCSI0_STATUS__bus_reset__BITNR 20
+#define R_SCSI0_STATUS__resel_target__BITNR 15
+#define R_SCSI0_STATUS__resel__BITNR 14
+#define R_SCSI0_STATUS__curr_phase__BITNR 11
+#define R_SCSI0_STATUS__last_seq_step__BITNR 6
+#define R_SCSI0_STATUS__valid_status__BITNR 5
+#define R_SCSI0_STATUS__seq_status__BITNR 0
+
+#define R_SCSI0_STATUS__tst_arb_won__tst_arb_won__VAL REG_VAL_VAL
+#define R_SCSI0_STATUS__tst_resel__tst_resel__VAL REG_VAL_VAL
+#define R_SCSI0_STATUS__parity_error__parity_error__VAL REG_VAL_VAL
+#define R_SCSI0_STATUS__bus_reset__bus_reset__VAL REG_VAL_ENUM
+#define R_SCSI0_STATUS__resel_target__resel_target__VAL REG_VAL_VAL
+#define R_SCSI0_STATUS__resel__resel__VAL REG_VAL_ENUM
+#define R_SCSI0_STATUS__curr_phase__curr_phase__VAL REG_VAL_ENUM
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__VAL REG_VAL_ENUM
+#define R_SCSI0_STATUS__valid_status__valid_status__VAL REG_VAL_ENUM
+#define R_SCSI0_STATUS__seq_status__seq_status__VAL REG_VAL_ENUM
+
+#define R_SCSI0_STATUS__bus_reset__bus_reset__no 0
+#define R_SCSI0_STATUS__bus_reset__bus_reset__yes 1
+#define R_SCSI0_STATUS__resel__resel__no 0
+#define R_SCSI0_STATUS__resel__resel__yes 1
+#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_command 2
+#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_data_in 5
+#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_data_out 4
+#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_msg_in 7
+#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_msg_out 6
+#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_resel 1
+#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_status 3
+#define R_SCSI0_STATUS__curr_phase__curr_phase__ph_undef 0
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_answer 3
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_arbitrate 8
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_din 9
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_dout 25
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_asynch_dout_end 11
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_bus_free 24
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_cc 31
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr 27
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr_cc 23
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_iwr_good 14
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual 28
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual_din_prot 18
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_manual_req 10
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_1 2
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_2 6
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_msg_3 22
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_resel_req 29
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_sdp_disc 7
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din 13
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_ack 12
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_ack_perr 5
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_din_perr 1
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_dout 0
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_synch_dout_ack 4
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_transf_cmd 30
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_transfer_done 15
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_cc 20
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_disc 21
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_iwr_cc 17
+#define R_SCSI0_STATUS__last_seq_step__last_seq_step__st_wait_free_sdp_disc 16
+#define R_SCSI0_STATUS__valid_status__valid_status__no 0
+#define R_SCSI0_STATUS__valid_status__valid_status__yes 1
+#define R_SCSI0_STATUS__seq_status__seq_status__info_arb_lost 4
+#define R_SCSI0_STATUS__seq_status__seq_status__info_bus_free 13
+#define R_SCSI0_STATUS__seq_status__seq_status__info_bus_reset 11
+#define R_SCSI0_STATUS__seq_status__seq_status__info_illegal_bf 12
+#define R_SCSI0_STATUS__seq_status__seq_status__info_illegal_op 7
+#define R_SCSI0_STATUS__seq_status__seq_status__info_parity_error 1
+#define R_SCSI0_STATUS__seq_status__seq_status__info_rec_recvd 8
+#define R_SCSI0_STATUS__seq_status__seq_status__info_reselected 9
+#define R_SCSI0_STATUS__seq_status__seq_status__info_sel_timeout 5
+#define R_SCSI0_STATUS__seq_status__seq_status__info_seq_complete 0
+#define R_SCSI0_STATUS__seq_status__seq_status__info_unexp_bf 6
+#define R_SCSI0_STATUS__seq_status__seq_status__info_unexp_ph_change 3
+#define R_SCSI0_STATUS__seq_status__seq_status__info_unhandled_msg_in 2
+#define R_SCSI0_STATUS__seq_status__seq_status__info_unhandled_status 10
+
+#endif
+
+/*
+ * R_SCSI0_STATUS_CTRL
+ * - type: WO
+ * - addr: 0xb0000043
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI0_STATUS_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000043)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI0_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_ATA_CTRL_DATA + 3))
+#define R_SCSI0_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_ATA_CTRL_DATA + 3))
+#else /* REG_NO_SHADOW */
+#define R_SCSI0_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SCSI0_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI0_STATUS_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SCSI0_STATUS_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SCSI0_STATUS_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI0_STATUS_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SCSI0_STATUS_CTRL__TYPE (REG_BYTE)
+#define R_SCSI0_STATUS_CTRL__GET REG_GET_WO
+#define R_SCSI0_STATUS_CTRL__IGET REG_IGET_WO
+#define R_SCSI0_STATUS_CTRL__SET REG_SET_WO
+#define R_SCSI0_STATUS_CTRL__ISET REG_ISET_WO
+#define R_SCSI0_STATUS_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SCSI0_STATUS_CTRL__EQL REG_EQL_WO
+#define R_SCSI0_STATUS_CTRL__IEQL REG_IEQL_WO
+#define R_SCSI0_STATUS_CTRL__RD REG_RD_WO
+#define R_SCSI0_STATUS_CTRL__IRD REG_IRD_WO
+#define R_SCSI0_STATUS_CTRL__WR REG_WR_WO
+#define R_SCSI0_STATUS_CTRL__IWR REG_IWR_WO
+
+#define R_SCSI0_STATUS_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SCSI0_STATUS_CTRL__FIRST 0
+#define R_SCSI0_STATUS_CTRL__IOFFSET 12
+#define R_SCSI0_STATUS_CTRL__LAST 1
+#define R_SCSI0_STATUS_CTRL__OFFSET 16
+#define R_SCSI0_STATUS_CTRL__SOFFSET 12
+/* end */
+
+#define R_SCSI0_STATUS_CTRL__parity_in__parity_in__MASK 0x00000004U
+#define R_SCSI0_STATUS_CTRL__skip__skip__MASK 0x00000002U
+#define R_SCSI0_STATUS_CTRL__clr_status__clr_status__MASK 0x00000001U
+
+#define R_SCSI0_STATUS_CTRL__parity_in__MAX 0x1
+#define R_SCSI0_STATUS_CTRL__skip__MAX 0x1
+#define R_SCSI0_STATUS_CTRL__clr_status__MAX 0x1
+
+#define R_SCSI0_STATUS_CTRL__parity_in__MIN 0
+#define R_SCSI0_STATUS_CTRL__skip__MIN 0
+#define R_SCSI0_STATUS_CTRL__clr_status__MIN 0
+
+#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2
+#define R_SCSI0_STATUS_CTRL__skip__BITNR 1
+#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0
+
+#define R_SCSI0_STATUS_CTRL__parity_in__parity_in__VAL REG_VAL_ENUM
+#define R_SCSI0_STATUS_CTRL__skip__skip__VAL REG_VAL_ENUM
+#define R_SCSI0_STATUS_CTRL__clr_status__clr_status__VAL REG_VAL_ENUM
+
+#define R_SCSI0_STATUS_CTRL__parity_in__parity_in__off 1
+#define R_SCSI0_STATUS_CTRL__parity_in__parity_in__on 0
+#define R_SCSI0_STATUS_CTRL__skip__skip__off 0
+#define R_SCSI0_STATUS_CTRL__skip__skip__on 1
+#define R_SCSI0_STATUS_CTRL__clr_status__clr_status__nop 0
+#define R_SCSI0_STATUS_CTRL__clr_status__clr_status__yes 1
+
+#endif
+
+/*
+ * R_SCSI1_CMD
+ * - type: WO
+ * - addr: 0xb0000052
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI1_CMD__ADDR (REG_TYPECAST_BYTE 0xb0000052)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI1_CMD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2))
+#define R_SCSI1_CMD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2))
+#else /* REG_NO_SHADOW */
+#define R_SCSI1_CMD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SCSI1_CMD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI1_CMD__STYPECAST REG_STYPECAST_BYTE
+#define R_SCSI1_CMD__SVAL REG_SVAL_SHADOW
+#define R_SCSI1_CMD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI1_CMD__TYPECAST REG_TYPECAST_BYTE
+#define R_SCSI1_CMD__TYPE (REG_BYTE)
+#define R_SCSI1_CMD__GET REG_GET_WO
+#define R_SCSI1_CMD__IGET REG_IGET_WO
+#define R_SCSI1_CMD__SET REG_SET_WO
+#define R_SCSI1_CMD__ISET REG_ISET_WO
+#define R_SCSI1_CMD__SET_VAL REG_SET_VAL_WO
+#define R_SCSI1_CMD__EQL REG_EQL_WO
+#define R_SCSI1_CMD__IEQL REG_IEQL_WO
+#define R_SCSI1_CMD__RD REG_RD_WO
+#define R_SCSI1_CMD__IRD REG_IRD_WO
+#define R_SCSI1_CMD__WR REG_WR_WO
+#define R_SCSI1_CMD__IWR REG_IWR_WO
+
+#define R_SCSI1_CMD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SCSI1_CMD__asynch_setup__asynch_setup__MASK 0x000000f0U
+#define R_SCSI1_CMD__command__command__MASK 0x0000000fU
+
+#define R_SCSI1_CMD__asynch_setup__MAX 0xf
+#define R_SCSI1_CMD__command__MAX 0xf
+
+#define R_SCSI1_CMD__asynch_setup__MIN 0
+#define R_SCSI1_CMD__command__MIN 0
+
+#define R_SCSI1_CMD__asynch_setup__BITNR 4
+#define R_SCSI1_CMD__command__BITNR 0
+
+#define R_SCSI1_CMD__asynch_setup__asynch_setup__VAL REG_VAL_VAL
+#define R_SCSI1_CMD__command__command__VAL REG_VAL_ENUM
+
+#define R_SCSI1_CMD__command__command__arb_only 6
+#define R_SCSI1_CMD__command__command__full_din_1 0
+#define R_SCSI1_CMD__command__command__full_din_3 8
+#define R_SCSI1_CMD__command__command__full_dout_1 1
+#define R_SCSI1_CMD__command__command__full_dout_3 9
+#define R_SCSI1_CMD__command__command__full_stat_1 2
+#define R_SCSI1_CMD__command__command__full_stat_3 10
+#define R_SCSI1_CMD__command__command__man_data_in 11
+#define R_SCSI1_CMD__command__command__man_data_out 12
+#define R_SCSI1_CMD__command__command__man_rat 13
+#define R_SCSI1_CMD__command__command__resel_din 3
+#define R_SCSI1_CMD__command__command__resel_dout 4
+#define R_SCSI1_CMD__command__command__resel_stat 5
+
+#endif
+
+/*
+ * R_SCSI1_CMD_DATA
+ * - type: WO
+ * - addr: 0xb0000050
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI1_CMD_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000050)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI1_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0))
+#define R_SCSI1_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0))
+#else /* REG_NO_SHADOW */
+#define R_SCSI1_CMD_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SCSI1_CMD_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI1_CMD_DATA__STYPECAST REG_STYPECAST_UDWORD
+#define R_SCSI1_CMD_DATA__SVAL REG_SVAL_SHADOW
+#define R_SCSI1_CMD_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI1_CMD_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_SCSI1_CMD_DATA__TYPE (REG_UDWORD)
+#define R_SCSI1_CMD_DATA__GET REG_GET_WO
+#define R_SCSI1_CMD_DATA__IGET REG_IGET_WO
+#define R_SCSI1_CMD_DATA__SET REG_SET_WO
+#define R_SCSI1_CMD_DATA__ISET REG_ISET_WO
+#define R_SCSI1_CMD_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SCSI1_CMD_DATA__EQL REG_EQL_WO
+#define R_SCSI1_CMD_DATA__IEQL REG_IEQL_WO
+#define R_SCSI1_CMD_DATA__RD REG_RD_WO
+#define R_SCSI1_CMD_DATA__IRD REG_IRD_WO
+#define R_SCSI1_CMD_DATA__WR REG_WR_WO
+#define R_SCSI1_CMD_DATA__IWR REG_IWR_WO
+
+#define R_SCSI1_CMD_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SCSI1_CMD_DATA__parity_in__parity_in__MASK 0x04000000U
+#define R_SCSI1_CMD_DATA__skip__skip__MASK 0x02000000U
+#define R_SCSI1_CMD_DATA__clr_status__clr_status__MASK 0x01000000U
+#define R_SCSI1_CMD_DATA__asynch_setup__asynch_setup__MASK 0x00f00000U
+#define R_SCSI1_CMD_DATA__command__command__MASK 0x000f0000U
+#define R_SCSI1_CMD_DATA__data_out__data_out__MASK 0x0000ffffU
+
+#define R_SCSI1_CMD_DATA__parity_in__MAX 0x1
+#define R_SCSI1_CMD_DATA__skip__MAX 0x1
+#define R_SCSI1_CMD_DATA__clr_status__MAX 0x1
+#define R_SCSI1_CMD_DATA__asynch_setup__MAX 0xf
+#define R_SCSI1_CMD_DATA__command__MAX 0xf
+#define R_SCSI1_CMD_DATA__data_out__MAX 0xffff
+
+#define R_SCSI1_CMD_DATA__parity_in__MIN 0
+#define R_SCSI1_CMD_DATA__skip__MIN 0
+#define R_SCSI1_CMD_DATA__clr_status__MIN 0
+#define R_SCSI1_CMD_DATA__asynch_setup__MIN 0
+#define R_SCSI1_CMD_DATA__command__MIN 0
+#define R_SCSI1_CMD_DATA__data_out__MIN 0
+
+#define R_SCSI1_CMD_DATA__parity_in__BITNR 26
+#define R_SCSI1_CMD_DATA__skip__BITNR 25
+#define R_SCSI1_CMD_DATA__clr_status__BITNR 24
+#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20
+#define R_SCSI1_CMD_DATA__command__BITNR 16
+#define R_SCSI1_CMD_DATA__data_out__BITNR 0
+
+#define R_SCSI1_CMD_DATA__parity_in__parity_in__VAL REG_VAL_ENUM
+#define R_SCSI1_CMD_DATA__skip__skip__VAL REG_VAL_ENUM
+#define R_SCSI1_CMD_DATA__clr_status__clr_status__VAL REG_VAL_ENUM
+#define R_SCSI1_CMD_DATA__asynch_setup__asynch_setup__VAL REG_VAL_VAL
+#define R_SCSI1_CMD_DATA__command__command__VAL REG_VAL_ENUM
+#define R_SCSI1_CMD_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+#define R_SCSI1_CMD_DATA__parity_in__parity_in__off 1
+#define R_SCSI1_CMD_DATA__parity_in__parity_in__on 0
+#define R_SCSI1_CMD_DATA__skip__skip__off 0
+#define R_SCSI1_CMD_DATA__skip__skip__on 1
+#define R_SCSI1_CMD_DATA__clr_status__clr_status__nop 0
+#define R_SCSI1_CMD_DATA__clr_status__clr_status__yes 1
+#define R_SCSI1_CMD_DATA__command__command__arb_only 6
+#define R_SCSI1_CMD_DATA__command__command__full_din_1 0
+#define R_SCSI1_CMD_DATA__command__command__full_din_3 8
+#define R_SCSI1_CMD_DATA__command__command__full_dout_1 1
+#define R_SCSI1_CMD_DATA__command__command__full_dout_3 9
+#define R_SCSI1_CMD_DATA__command__command__full_stat_1 2
+#define R_SCSI1_CMD_DATA__command__command__full_stat_3 10
+#define R_SCSI1_CMD_DATA__command__command__man_data_in 11
+#define R_SCSI1_CMD_DATA__command__command__man_data_out 12
+#define R_SCSI1_CMD_DATA__command__command__man_rat 13
+#define R_SCSI1_CMD_DATA__command__command__resel_din 3
+#define R_SCSI1_CMD_DATA__command__command__resel_dout 4
+#define R_SCSI1_CMD_DATA__command__command__resel_stat 5
+
+#endif
+
+/*
+ * R_SCSI1_CTRL
+ * - type: WO
+ * - addr: 0xb0000054
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000054)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_PAR1_CONFIG + 0))
+#define R_SCSI1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_PAR1_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_SCSI1_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SCSI1_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI1_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_SCSI1_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SCSI1_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI1_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_SCSI1_CTRL__TYPE (REG_UDWORD)
+#define R_SCSI1_CTRL__GET REG_GET_WO
+#define R_SCSI1_CTRL__IGET REG_IGET_WO
+#define R_SCSI1_CTRL__SET REG_SET_WO
+#define R_SCSI1_CTRL__ISET REG_ISET_WO
+#define R_SCSI1_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SCSI1_CTRL__EQL REG_EQL_WO
+#define R_SCSI1_CTRL__IEQL REG_IEQL_WO
+#define R_SCSI1_CTRL__RD REG_RD_WO
+#define R_SCSI1_CTRL__IRD REG_IRD_WO
+#define R_SCSI1_CTRL__WR REG_WR_WO
+#define R_SCSI1_CTRL__IWR REG_IWR_WO
+
+#define R_SCSI1_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SCSI1_CTRL__id_type__id_type__MASK 0x80000000U
+#define R_SCSI1_CTRL__sel_timeout__sel_timeout__MASK 0x7f000000U
+#define R_SCSI1_CTRL__synch_per__synch_per__MASK 0x00ff0000U
+#define R_SCSI1_CTRL__rst__rst__MASK 0x00008000U
+#define R_SCSI1_CTRL__atn__atn__MASK 0x00004000U
+#define R_SCSI1_CTRL__my_id__my_id__MASK 0x00001e00U
+#define R_SCSI1_CTRL__target_id__target_id__MASK 0x000000f0U
+#define R_SCSI1_CTRL__fast_20__fast_20__MASK 0x00000008U
+#define R_SCSI1_CTRL__bus_width__bus_width__MASK 0x00000004U
+#define R_SCSI1_CTRL__synch__synch__MASK 0x00000002U
+#define R_SCSI1_CTRL__enable__enable__MASK 0x00000001U
+
+#define R_SCSI1_CTRL__id_type__MAX 0x1
+#define R_SCSI1_CTRL__sel_timeout__MAX 0x7f
+#define R_SCSI1_CTRL__synch_per__MAX 0xff
+#define R_SCSI1_CTRL__rst__MAX 0x1
+#define R_SCSI1_CTRL__atn__MAX 0x1
+#define R_SCSI1_CTRL__my_id__MAX 0xf
+#define R_SCSI1_CTRL__target_id__MAX 0xf
+#define R_SCSI1_CTRL__fast_20__MAX 0x1
+#define R_SCSI1_CTRL__bus_width__MAX 0x1
+#define R_SCSI1_CTRL__synch__MAX 0x1
+#define R_SCSI1_CTRL__enable__MAX 0x1
+
+#define R_SCSI1_CTRL__id_type__MIN 0
+#define R_SCSI1_CTRL__sel_timeout__MIN 0
+#define R_SCSI1_CTRL__synch_per__MIN 0
+#define R_SCSI1_CTRL__rst__MIN 0
+#define R_SCSI1_CTRL__atn__MIN 0
+#define R_SCSI1_CTRL__my_id__MIN 0
+#define R_SCSI1_CTRL__target_id__MIN 0
+#define R_SCSI1_CTRL__fast_20__MIN 0
+#define R_SCSI1_CTRL__bus_width__MIN 0
+#define R_SCSI1_CTRL__synch__MIN 0
+#define R_SCSI1_CTRL__enable__MIN 0
+
+#define R_SCSI1_CTRL__id_type__BITNR 31
+#define R_SCSI1_CTRL__sel_timeout__BITNR 24
+#define R_SCSI1_CTRL__synch_per__BITNR 16
+#define R_SCSI1_CTRL__rst__BITNR 15
+#define R_SCSI1_CTRL__atn__BITNR 14
+#define R_SCSI1_CTRL__my_id__BITNR 9
+#define R_SCSI1_CTRL__target_id__BITNR 4
+#define R_SCSI1_CTRL__fast_20__BITNR 3
+#define R_SCSI1_CTRL__bus_width__BITNR 2
+#define R_SCSI1_CTRL__synch__BITNR 1
+#define R_SCSI1_CTRL__enable__BITNR 0
+
+#define R_SCSI1_CTRL__id_type__id_type__VAL REG_VAL_ENUM
+#define R_SCSI1_CTRL__sel_timeout__sel_timeout__VAL REG_VAL_VAL
+#define R_SCSI1_CTRL__synch_per__synch_per__VAL REG_VAL_VAL
+#define R_SCSI1_CTRL__rst__rst__VAL REG_VAL_ENUM
+#define R_SCSI1_CTRL__atn__atn__VAL REG_VAL_ENUM
+#define R_SCSI1_CTRL__my_id__my_id__VAL REG_VAL_VAL
+#define R_SCSI1_CTRL__target_id__target_id__VAL REG_VAL_VAL
+#define R_SCSI1_CTRL__fast_20__fast_20__VAL REG_VAL_ENUM
+#define R_SCSI1_CTRL__bus_width__bus_width__VAL REG_VAL_ENUM
+#define R_SCSI1_CTRL__synch__synch__VAL REG_VAL_ENUM
+#define R_SCSI1_CTRL__enable__enable__VAL REG_VAL_ENUM
+
+#define R_SCSI1_CTRL__id_type__id_type__hardware 0
+#define R_SCSI1_CTRL__id_type__id_type__software 1
+#define R_SCSI1_CTRL__rst__rst__no 0
+#define R_SCSI1_CTRL__rst__rst__yes 1
+#define R_SCSI1_CTRL__atn__atn__no 0
+#define R_SCSI1_CTRL__atn__atn__yes 1
+#define R_SCSI1_CTRL__fast_20__fast_20__no 0
+#define R_SCSI1_CTRL__fast_20__fast_20__yes 1
+#define R_SCSI1_CTRL__bus_width__bus_width__narrow 0
+#define R_SCSI1_CTRL__bus_width__bus_width__wide 1
+#define R_SCSI1_CTRL__synch__synch__asynch 0
+#define R_SCSI1_CTRL__synch__synch__synch 1
+#define R_SCSI1_CTRL__enable__enable__off 0
+#define R_SCSI1_CTRL__enable__enable__on 1
+
+#endif
+
+/*
+ * R_SCSI1_DATA
+ * - type: WO
+ * - addr: 0xb0000050
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI1_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000050)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI1_DATA__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 0))
+#define R_SCSI1_DATA__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 0))
+#else /* REG_NO_SHADOW */
+#define R_SCSI1_DATA__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_SCSI1_DATA__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI1_DATA__STYPECAST REG_STYPECAST_UWORD
+#define R_SCSI1_DATA__SVAL REG_SVAL_SHADOW
+#define R_SCSI1_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI1_DATA__TYPECAST REG_TYPECAST_UWORD
+#define R_SCSI1_DATA__TYPE (REG_UWORD)
+#define R_SCSI1_DATA__GET REG_GET_WO
+#define R_SCSI1_DATA__IGET REG_IGET_WO
+#define R_SCSI1_DATA__SET REG_SET_WO
+#define R_SCSI1_DATA__ISET REG_ISET_WO
+#define R_SCSI1_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SCSI1_DATA__EQL REG_EQL_WO
+#define R_SCSI1_DATA__IEQL REG_IEQL_WO
+#define R_SCSI1_DATA__RD REG_RD_WO
+#define R_SCSI1_DATA__IRD REG_IRD_WO
+#define R_SCSI1_DATA__WR REG_WR_WO
+#define R_SCSI1_DATA__IWR REG_IWR_WO
+
+#define R_SCSI1_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SCSI1_DATA__data_out__data_out__MASK 0x0000ffffU
+
+#define R_SCSI1_DATA__data_out__MAX 0xffff
+
+#define R_SCSI1_DATA__data_out__MIN 0
+
+#define R_SCSI1_DATA__data_out__BITNR 0
+
+#define R_SCSI1_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SCSI1_DATA_IN
+ * - type: RO
+ * - addr: 0xb0000050
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI1_DATA_IN__ADDR (REG_TYPECAST_UWORD 0xb0000050)
+#define R_SCSI1_DATA_IN__SVAL REG_SVAL_SHADOW
+#define R_SCSI1_DATA_IN__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI1_DATA_IN__TYPECAST REG_TYPECAST_UWORD
+#define R_SCSI1_DATA_IN__TYPE (REG_UWORD)
+#define R_SCSI1_DATA_IN__GET REG_GET_RO
+#define R_SCSI1_DATA_IN__IGET REG_IGET_RO
+#define R_SCSI1_DATA_IN__SET REG_SET_RO
+#define R_SCSI1_DATA_IN__ISET REG_ISET_RO
+#define R_SCSI1_DATA_IN__SET_VAL REG_SET_VAL_RO
+#define R_SCSI1_DATA_IN__EQL REG_EQL_RO
+#define R_SCSI1_DATA_IN__IEQL REG_IEQL_RO
+#define R_SCSI1_DATA_IN__RD REG_RD_RO
+#define R_SCSI1_DATA_IN__IRD REG_IRD_RO
+#define R_SCSI1_DATA_IN__WR REG_WR_RO
+#define R_SCSI1_DATA_IN__IWR REG_IWR_RO
+
+#define R_SCSI1_DATA_IN__READ(addr) \
+ (*(addr))
+
+#define R_SCSI1_DATA_IN__data_in__data_in__MASK 0x0000ffffU
+
+#define R_SCSI1_DATA_IN__data_in__MAX 0xffff
+
+#define R_SCSI1_DATA_IN__data_in__MIN 0
+
+#define R_SCSI1_DATA_IN__data_in__BITNR 0
+
+#define R_SCSI1_DATA_IN__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SCSI1_STATUS
+ * - type: RO
+ * - addr: 0xb0000058
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI1_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000058)
+#define R_SCSI1_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SCSI1_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI1_STATUS__TYPECAST REG_TYPECAST_UDWORD
+#define R_SCSI1_STATUS__TYPE (REG_UDWORD)
+#define R_SCSI1_STATUS__GET REG_GET_RO
+#define R_SCSI1_STATUS__IGET REG_IGET_RO
+#define R_SCSI1_STATUS__SET REG_SET_RO
+#define R_SCSI1_STATUS__ISET REG_ISET_RO
+#define R_SCSI1_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SCSI1_STATUS__EQL REG_EQL_RO
+#define R_SCSI1_STATUS__IEQL REG_IEQL_RO
+#define R_SCSI1_STATUS__RD REG_RD_RO
+#define R_SCSI1_STATUS__IRD REG_IRD_RO
+#define R_SCSI1_STATUS__WR REG_WR_RO
+#define R_SCSI1_STATUS__IWR REG_IWR_RO
+
+#define R_SCSI1_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_SCSI1_STATUS__tst_arb_won__tst_arb_won__MASK 0x00800000U
+#define R_SCSI1_STATUS__tst_resel__tst_resel__MASK 0x00400000U
+#define R_SCSI1_STATUS__parity_error__parity_error__MASK 0x00200000U
+#define R_SCSI1_STATUS__bus_reset__bus_reset__MASK 0x00100000U
+#define R_SCSI1_STATUS__resel_target__resel_target__MASK 0x00078000U
+#define R_SCSI1_STATUS__resel__resel__MASK 0x00004000U
+#define R_SCSI1_STATUS__curr_phase__curr_phase__MASK 0x00003800U
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__MASK 0x000007c0U
+#define R_SCSI1_STATUS__valid_status__valid_status__MASK 0x00000020U
+#define R_SCSI1_STATUS__seq_status__seq_status__MASK 0x0000001fU
+
+#define R_SCSI1_STATUS__tst_arb_won__MAX 0x1
+#define R_SCSI1_STATUS__tst_resel__MAX 0x1
+#define R_SCSI1_STATUS__parity_error__MAX 0x1
+#define R_SCSI1_STATUS__bus_reset__MAX 0x1
+#define R_SCSI1_STATUS__resel_target__MAX 0xf
+#define R_SCSI1_STATUS__resel__MAX 0x1
+#define R_SCSI1_STATUS__curr_phase__MAX 0x7
+#define R_SCSI1_STATUS__last_seq_step__MAX 0x1f
+#define R_SCSI1_STATUS__valid_status__MAX 0x1
+#define R_SCSI1_STATUS__seq_status__MAX 0x1f
+
+#define R_SCSI1_STATUS__tst_arb_won__MIN 0
+#define R_SCSI1_STATUS__tst_resel__MIN 0
+#define R_SCSI1_STATUS__parity_error__MIN 0
+#define R_SCSI1_STATUS__bus_reset__MIN 0
+#define R_SCSI1_STATUS__resel_target__MIN 0
+#define R_SCSI1_STATUS__resel__MIN 0
+#define R_SCSI1_STATUS__curr_phase__MIN 0
+#define R_SCSI1_STATUS__last_seq_step__MIN 0
+#define R_SCSI1_STATUS__valid_status__MIN 0
+#define R_SCSI1_STATUS__seq_status__MIN 0
+
+#define R_SCSI1_STATUS__tst_arb_won__BITNR 23
+#define R_SCSI1_STATUS__tst_resel__BITNR 22
+#define R_SCSI1_STATUS__parity_error__BITNR 21
+#define R_SCSI1_STATUS__bus_reset__BITNR 20
+#define R_SCSI1_STATUS__resel_target__BITNR 15
+#define R_SCSI1_STATUS__resel__BITNR 14
+#define R_SCSI1_STATUS__curr_phase__BITNR 11
+#define R_SCSI1_STATUS__last_seq_step__BITNR 6
+#define R_SCSI1_STATUS__valid_status__BITNR 5
+#define R_SCSI1_STATUS__seq_status__BITNR 0
+
+#define R_SCSI1_STATUS__tst_arb_won__tst_arb_won__VAL REG_VAL_VAL
+#define R_SCSI1_STATUS__tst_resel__tst_resel__VAL REG_VAL_VAL
+#define R_SCSI1_STATUS__parity_error__parity_error__VAL REG_VAL_VAL
+#define R_SCSI1_STATUS__bus_reset__bus_reset__VAL REG_VAL_ENUM
+#define R_SCSI1_STATUS__resel_target__resel_target__VAL REG_VAL_VAL
+#define R_SCSI1_STATUS__resel__resel__VAL REG_VAL_ENUM
+#define R_SCSI1_STATUS__curr_phase__curr_phase__VAL REG_VAL_ENUM
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__VAL REG_VAL_ENUM
+#define R_SCSI1_STATUS__valid_status__valid_status__VAL REG_VAL_ENUM
+#define R_SCSI1_STATUS__seq_status__seq_status__VAL REG_VAL_ENUM
+
+#define R_SCSI1_STATUS__bus_reset__bus_reset__no 0
+#define R_SCSI1_STATUS__bus_reset__bus_reset__yes 1
+#define R_SCSI1_STATUS__resel__resel__no 0
+#define R_SCSI1_STATUS__resel__resel__yes 1
+#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_command 2
+#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_data_in 5
+#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_data_out 4
+#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_msg_in 7
+#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_msg_out 6
+#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_resel 1
+#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_status 3
+#define R_SCSI1_STATUS__curr_phase__curr_phase__ph_undef 0
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_answer 3
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_arbitrate 8
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_din 9
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_dout 25
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_asynch_dout_end 11
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_bus_free 24
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_cc 31
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr 27
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr_cc 23
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_iwr_good 14
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual 28
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual_din_prot 18
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_manual_req 10
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_1 2
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_2 6
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_msg_3 22
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_resel_req 29
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_sdp_disc 7
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din 13
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_ack 12
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_ack_perr 5
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_din_perr 1
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_dout 0
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_synch_dout_ack 4
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_transf_cmd 30
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_transfer_done 15
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_cc 20
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_disc 21
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_iwr_cc 17
+#define R_SCSI1_STATUS__last_seq_step__last_seq_step__st_wait_free_sdp_disc 16
+#define R_SCSI1_STATUS__valid_status__valid_status__no 0
+#define R_SCSI1_STATUS__valid_status__valid_status__yes 1
+#define R_SCSI1_STATUS__seq_status__seq_status__info_arb_lost 4
+#define R_SCSI1_STATUS__seq_status__seq_status__info_bus_free 13
+#define R_SCSI1_STATUS__seq_status__seq_status__info_bus_reset 11
+#define R_SCSI1_STATUS__seq_status__seq_status__info_illegal_bf 12
+#define R_SCSI1_STATUS__seq_status__seq_status__info_illegal_op 7
+#define R_SCSI1_STATUS__seq_status__seq_status__info_parity_error 1
+#define R_SCSI1_STATUS__seq_status__seq_status__info_rec_recvd 8
+#define R_SCSI1_STATUS__seq_status__seq_status__info_reselected 9
+#define R_SCSI1_STATUS__seq_status__seq_status__info_sel_timeout 5
+#define R_SCSI1_STATUS__seq_status__seq_status__info_seq_complete 0
+#define R_SCSI1_STATUS__seq_status__seq_status__info_unexp_bf 6
+#define R_SCSI1_STATUS__seq_status__seq_status__info_unexp_ph_change 3
+#define R_SCSI1_STATUS__seq_status__seq_status__info_unhandled_msg_in 2
+#define R_SCSI1_STATUS__seq_status__seq_status__info_unhandled_status 10
+
+#endif
+
+/*
+ * R_SCSI1_STATUS_CTRL
+ * - type: WO
+ * - addr: 0xb0000053
+ * - group: SCSI registers
+ */
+
+#if USE_GROUP__SCSI_registers
+
+#define R_SCSI1_STATUS_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000053)
+
+#ifndef REG_NO_SHADOW
+#define R_SCSI1_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 3))
+#define R_SCSI1_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 3))
+#else /* REG_NO_SHADOW */
+#define R_SCSI1_STATUS_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SCSI1_STATUS_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SCSI1_STATUS_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SCSI1_STATUS_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SCSI1_STATUS_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SCSI1_STATUS_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SCSI1_STATUS_CTRL__TYPE (REG_BYTE)
+#define R_SCSI1_STATUS_CTRL__GET REG_GET_WO
+#define R_SCSI1_STATUS_CTRL__IGET REG_IGET_WO
+#define R_SCSI1_STATUS_CTRL__SET REG_SET_WO
+#define R_SCSI1_STATUS_CTRL__ISET REG_ISET_WO
+#define R_SCSI1_STATUS_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SCSI1_STATUS_CTRL__EQL REG_EQL_WO
+#define R_SCSI1_STATUS_CTRL__IEQL REG_IEQL_WO
+#define R_SCSI1_STATUS_CTRL__RD REG_RD_WO
+#define R_SCSI1_STATUS_CTRL__IRD REG_IRD_WO
+#define R_SCSI1_STATUS_CTRL__WR REG_WR_WO
+#define R_SCSI1_STATUS_CTRL__IWR REG_IWR_WO
+
+#define R_SCSI1_STATUS_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SCSI1_STATUS_CTRL__parity_in__parity_in__MASK 0x00000004U
+#define R_SCSI1_STATUS_CTRL__skip__skip__MASK 0x00000002U
+#define R_SCSI1_STATUS_CTRL__clr_status__clr_status__MASK 0x00000001U
+
+#define R_SCSI1_STATUS_CTRL__parity_in__MAX 0x1
+#define R_SCSI1_STATUS_CTRL__skip__MAX 0x1
+#define R_SCSI1_STATUS_CTRL__clr_status__MAX 0x1
+
+#define R_SCSI1_STATUS_CTRL__parity_in__MIN 0
+#define R_SCSI1_STATUS_CTRL__skip__MIN 0
+#define R_SCSI1_STATUS_CTRL__clr_status__MIN 0
+
+#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2
+#define R_SCSI1_STATUS_CTRL__skip__BITNR 1
+#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0
+
+#define R_SCSI1_STATUS_CTRL__parity_in__parity_in__VAL REG_VAL_ENUM
+#define R_SCSI1_STATUS_CTRL__skip__skip__VAL REG_VAL_ENUM
+#define R_SCSI1_STATUS_CTRL__clr_status__clr_status__VAL REG_VAL_ENUM
+
+#define R_SCSI1_STATUS_CTRL__parity_in__parity_in__off 1
+#define R_SCSI1_STATUS_CTRL__parity_in__parity_in__on 0
+#define R_SCSI1_STATUS_CTRL__skip__skip__off 0
+#define R_SCSI1_STATUS_CTRL__skip__skip__on 1
+#define R_SCSI1_STATUS_CTRL__clr_status__clr_status__nop 0
+#define R_SCSI1_STATUS_CTRL__clr_status__clr_status__yes 1
+
+#endif
+
+/*
+ * R_SDRAM_CONFIG
+ * - type: WO
+ * - addr: 0xb000000c
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+#define R_SDRAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb000000c)
+
+#ifndef REG_NO_SHADOW
+#define R_SDRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_CONFIG + 0))
+#define R_SDRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_SDRAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SDRAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SDRAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_SDRAM_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_SDRAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_SDRAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_SDRAM_CONFIG__TYPE (REG_UDWORD)
+#define R_SDRAM_CONFIG__GET REG_GET_WO
+#define R_SDRAM_CONFIG__IGET REG_IGET_WO
+#define R_SDRAM_CONFIG__SET REG_SET_WO
+#define R_SDRAM_CONFIG__ISET REG_ISET_WO
+#define R_SDRAM_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_SDRAM_CONFIG__EQL REG_EQL_WO
+#define R_SDRAM_CONFIG__IEQL REG_IEQL_WO
+#define R_SDRAM_CONFIG__RD REG_RD_WO
+#define R_SDRAM_CONFIG__IRD REG_IRD_WO
+#define R_SDRAM_CONFIG__WR REG_WR_WO
+#define R_SDRAM_CONFIG__IWR REG_IWR_WO
+
+#define R_SDRAM_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SDRAM_CONFIG__wmm1__wmm1__MASK 0x80000000U
+#define R_SDRAM_CONFIG__wmm0__wmm0__MASK 0x40000000U
+#define R_SDRAM_CONFIG__sh1__sh1__MASK 0x38000000U
+#define R_SDRAM_CONFIG__sh0__sh0__MASK 0x07000000U
+#define R_SDRAM_CONFIG__w__w__MASK 0x00800000U
+#define R_SDRAM_CONFIG__type1__type1__MASK 0x00400000U
+#define R_SDRAM_CONFIG__type0__type0__MASK 0x00200000U
+#define R_SDRAM_CONFIG__group_sel__group_sel__MASK 0x001f0000U
+#define R_SDRAM_CONFIG__ca1__ca1__MASK 0x0000e000U
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__MASK 0x00001f00U
+#define R_SDRAM_CONFIG__ca0__ca0__MASK 0x000000e0U
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__MASK 0x0000001fU
+
+#define R_SDRAM_CONFIG__wmm1__MAX 0x1
+#define R_SDRAM_CONFIG__wmm0__MAX 0x1
+#define R_SDRAM_CONFIG__sh1__MAX 7
+#define R_SDRAM_CONFIG__sh0__MAX 7
+#define R_SDRAM_CONFIG__w__MAX 0x1
+#define R_SDRAM_CONFIG__type1__MAX 0x1
+#define R_SDRAM_CONFIG__type0__MAX 0x1
+#define R_SDRAM_CONFIG__group_sel__MAX 0x1f
+#define R_SDRAM_CONFIG__ca1__MAX 7
+#define R_SDRAM_CONFIG__bank_sel1__MAX 0x1f
+#define R_SDRAM_CONFIG__ca0__MAX 7
+#define R_SDRAM_CONFIG__bank_sel0__MAX 0x1f
+
+#define R_SDRAM_CONFIG__wmm1__MIN 0
+#define R_SDRAM_CONFIG__wmm0__MIN 0
+#define R_SDRAM_CONFIG__sh1__MIN 0
+#define R_SDRAM_CONFIG__sh0__MIN 0
+#define R_SDRAM_CONFIG__w__MIN 0
+#define R_SDRAM_CONFIG__type1__MIN 0
+#define R_SDRAM_CONFIG__type0__MIN 0
+#define R_SDRAM_CONFIG__group_sel__MIN 0
+#define R_SDRAM_CONFIG__ca1__MIN 0
+#define R_SDRAM_CONFIG__bank_sel1__MIN 0
+#define R_SDRAM_CONFIG__ca0__MIN 0
+#define R_SDRAM_CONFIG__bank_sel0__MIN 0
+
+#define R_SDRAM_CONFIG__wmm1__BITNR 31
+#define R_SDRAM_CONFIG__wmm0__BITNR 30
+#define R_SDRAM_CONFIG__sh1__BITNR 27
+#define R_SDRAM_CONFIG__sh0__BITNR 24
+#define R_SDRAM_CONFIG__w__BITNR 23
+#define R_SDRAM_CONFIG__type1__BITNR 22
+#define R_SDRAM_CONFIG__type0__BITNR 21
+#define R_SDRAM_CONFIG__group_sel__BITNR 16
+#define R_SDRAM_CONFIG__ca1__BITNR 13
+#define R_SDRAM_CONFIG__bank_sel1__BITNR 8
+#define R_SDRAM_CONFIG__ca0__BITNR 5
+#define R_SDRAM_CONFIG__bank_sel0__BITNR 0
+
+#define R_SDRAM_CONFIG__wmm1__wmm1__VAL REG_VAL_ENUM
+#define R_SDRAM_CONFIG__wmm0__wmm0__VAL REG_VAL_ENUM
+#define R_SDRAM_CONFIG__sh1__sh1__VAL REG_VAL_VAL
+#define R_SDRAM_CONFIG__sh0__sh0__VAL REG_VAL_VAL
+#define R_SDRAM_CONFIG__w__w__VAL REG_VAL_ENUM
+#define R_SDRAM_CONFIG__type1__type1__VAL REG_VAL_ENUM
+#define R_SDRAM_CONFIG__type0__type0__VAL REG_VAL_ENUM
+#define R_SDRAM_CONFIG__group_sel__group_sel__VAL REG_VAL_ENUM
+#define R_SDRAM_CONFIG__ca1__ca1__VAL REG_VAL_VAL
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__VAL REG_VAL_ENUM
+#define R_SDRAM_CONFIG__ca0__ca0__VAL REG_VAL_VAL
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__VAL REG_VAL_ENUM
+
+#define R_SDRAM_CONFIG__wmm1__wmm1__norm 0
+#define R_SDRAM_CONFIG__wmm1__wmm1__wmm 1
+#define R_SDRAM_CONFIG__wmm0__wmm0__norm 0
+#define R_SDRAM_CONFIG__wmm0__wmm0__wmm 1
+#define R_SDRAM_CONFIG__w__w__bw16 0
+#define R_SDRAM_CONFIG__w__w__bw32 1
+#define R_SDRAM_CONFIG__type1__type1__bank2 0
+#define R_SDRAM_CONFIG__type1__type1__bank4 1
+#define R_SDRAM_CONFIG__type0__type0__bank2 0
+#define R_SDRAM_CONFIG__type0__type0__bank4 1
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit10 10
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit11 11
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit12 12
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit13 13
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit14 14
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit15 15
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit16 16
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit17 17
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit18 18
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit19 19
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit20 20
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit21 21
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit22 22
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit23 23
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit24 24
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit25 25
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit26 26
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit27 27
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit28 28
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit29 29
+#define R_SDRAM_CONFIG__group_sel__group_sel__bit9 9
+#define R_SDRAM_CONFIG__group_sel__group_sel__grp0 0
+#define R_SDRAM_CONFIG__group_sel__group_sel__grp1 1
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit10 10
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit11 11
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit12 12
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit13 13
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit14 14
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit15 15
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit16 16
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit17 17
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit18 18
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit19 19
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit20 20
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit21 21
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit22 22
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit23 23
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit24 24
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit25 25
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit26 26
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit27 27
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit28 28
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit29 29
+#define R_SDRAM_CONFIG__bank_sel1__bank_sel1__bit9 9
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit10 10
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit11 11
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit12 12
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit13 13
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit14 14
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit15 15
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit16 16
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit17 17
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit18 18
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit19 19
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit20 20
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit21 21
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit22 22
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit23 23
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit24 24
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit25 25
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit26 26
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit27 27
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit28 28
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit29 29
+#define R_SDRAM_CONFIG__bank_sel0__bank_sel0__bit9 9
+
+#endif
+
+/*
+ * R_SDRAM_TIMING
+ * - type: WO
+ * - addr: 0xb0000008
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+#define R_SDRAM_TIMING__ADDR (REG_TYPECAST_UDWORD 0xb0000008)
+
+#ifndef REG_NO_SHADOW
+#define R_SDRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_DRAM_TIMING + 0))
+#define R_SDRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_DRAM_TIMING + 0))
+#else /* REG_NO_SHADOW */
+#define R_SDRAM_TIMING__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SDRAM_TIMING__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SDRAM_TIMING__STYPECAST REG_STYPECAST_UDWORD
+#define R_SDRAM_TIMING__SVAL REG_SVAL_SHADOW
+#define R_SDRAM_TIMING__SVAL_I REG_SVAL_I_SHADOW
+#define R_SDRAM_TIMING__TYPECAST REG_TYPECAST_UDWORD
+#define R_SDRAM_TIMING__TYPE (REG_UDWORD)
+#define R_SDRAM_TIMING__GET REG_GET_WO
+#define R_SDRAM_TIMING__IGET REG_IGET_WO
+#define R_SDRAM_TIMING__SET REG_SET_WO
+#define R_SDRAM_TIMING__ISET REG_ISET_WO
+#define R_SDRAM_TIMING__SET_VAL REG_SET_VAL_WO
+#define R_SDRAM_TIMING__EQL REG_EQL_WO
+#define R_SDRAM_TIMING__IEQL REG_IEQL_WO
+#define R_SDRAM_TIMING__RD REG_RD_WO
+#define R_SDRAM_TIMING__IRD REG_IRD_WO
+#define R_SDRAM_TIMING__WR REG_WR_WO
+#define R_SDRAM_TIMING__IWR REG_IWR_WO
+
+#define R_SDRAM_TIMING__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SDRAM_TIMING__sdram__sdram__MASK 0x80000000U
+#define R_SDRAM_TIMING__mrs_data__mrs_data__MASK 0x7fff0000U
+#define R_SDRAM_TIMING__ref__ref__MASK 0x0000c000U
+#define R_SDRAM_TIMING__ddr__ddr__MASK 0x00002000U
+#define R_SDRAM_TIMING__clk100__clk100__MASK 0x00001000U
+#define R_SDRAM_TIMING__ps__ps__MASK 0x00000800U
+#define R_SDRAM_TIMING__cmd__cmd__MASK 0x00000600U
+#define R_SDRAM_TIMING__pde__pde__MASK 0x00000100U
+#define R_SDRAM_TIMING__rc__rc__MASK 0x000000c0U
+#define R_SDRAM_TIMING__rp__rp__MASK 0x00000030U
+#define R_SDRAM_TIMING__rcd__rcd__MASK 0x0000000cU
+#define R_SDRAM_TIMING__cl__cl__MASK 0x00000003U
+
+#define R_SDRAM_TIMING__sdram__MAX 0x1
+#define R_SDRAM_TIMING__mrs_data__MAX 0x7fff
+#define R_SDRAM_TIMING__ref__MAX 0x3
+#define R_SDRAM_TIMING__ddr__MAX 0x1
+#define R_SDRAM_TIMING__clk100__MAX 0x1
+#define R_SDRAM_TIMING__ps__MAX 0x1
+#define R_SDRAM_TIMING__cmd__MAX 0x3
+#define R_SDRAM_TIMING__pde__MAX 1
+#define R_SDRAM_TIMING__rc__MAX 3
+#define R_SDRAM_TIMING__rp__MAX 3
+#define R_SDRAM_TIMING__rcd__MAX 3
+#define R_SDRAM_TIMING__cl__MAX 2
+
+#define R_SDRAM_TIMING__sdram__MIN 0
+#define R_SDRAM_TIMING__mrs_data__MIN 0
+#define R_SDRAM_TIMING__ref__MIN 0
+#define R_SDRAM_TIMING__ddr__MIN 0
+#define R_SDRAM_TIMING__clk100__MIN 0
+#define R_SDRAM_TIMING__ps__MIN 0
+#define R_SDRAM_TIMING__cmd__MIN 0
+#define R_SDRAM_TIMING__pde__MIN 0
+#define R_SDRAM_TIMING__rc__MIN 0
+#define R_SDRAM_TIMING__rp__MIN 0
+#define R_SDRAM_TIMING__rcd__MIN 0
+#define R_SDRAM_TIMING__cl__MIN 0
+
+#define R_SDRAM_TIMING__sdram__BITNR 31
+#define R_SDRAM_TIMING__mrs_data__BITNR 16
+#define R_SDRAM_TIMING__ref__BITNR 14
+#define R_SDRAM_TIMING__ddr__BITNR 13
+#define R_SDRAM_TIMING__clk100__BITNR 12
+#define R_SDRAM_TIMING__ps__BITNR 11
+#define R_SDRAM_TIMING__cmd__BITNR 9
+#define R_SDRAM_TIMING__pde__BITNR 8
+#define R_SDRAM_TIMING__rc__BITNR 6
+#define R_SDRAM_TIMING__rp__BITNR 4
+#define R_SDRAM_TIMING__rcd__BITNR 2
+#define R_SDRAM_TIMING__cl__BITNR 0
+
+#define R_SDRAM_TIMING__sdram__sdram__VAL REG_VAL_ENUM
+#define R_SDRAM_TIMING__mrs_data__mrs_data__VAL REG_VAL_VAL
+#define R_SDRAM_TIMING__ref__ref__VAL REG_VAL_ENUM
+#define R_SDRAM_TIMING__ddr__ddr__VAL REG_VAL_ENUM
+#define R_SDRAM_TIMING__clk100__clk100__VAL REG_VAL_ENUM
+#define R_SDRAM_TIMING__ps__ps__VAL REG_VAL_ENUM
+#define R_SDRAM_TIMING__cmd__cmd__VAL REG_VAL_ENUM
+#define R_SDRAM_TIMING__pde__pde__VAL REG_VAL_VAL
+#define R_SDRAM_TIMING__rc__rc__VAL REG_VAL_VAL
+#define R_SDRAM_TIMING__rp__rp__VAL REG_VAL_VAL
+#define R_SDRAM_TIMING__rcd__rcd__VAL REG_VAL_VAL
+#define R_SDRAM_TIMING__cl__cl__VAL REG_VAL_VAL
+
+#define R_SDRAM_TIMING__sdram__sdram__disable 0
+#define R_SDRAM_TIMING__sdram__sdram__enable 1
+#define R_SDRAM_TIMING__ref__ref__disable 3
+#define R_SDRAM_TIMING__ref__ref__e13us 1
+#define R_SDRAM_TIMING__ref__ref__e52us 0
+#define R_SDRAM_TIMING__ref__ref__e6500ns 2
+#define R_SDRAM_TIMING__ddr__ddr__off 0
+#define R_SDRAM_TIMING__ddr__ddr__on 1
+#define R_SDRAM_TIMING__clk100__clk100__off 0
+#define R_SDRAM_TIMING__clk100__clk100__on 1
+#define R_SDRAM_TIMING__ps__ps__off 0
+#define R_SDRAM_TIMING__ps__ps__on 1
+#define R_SDRAM_TIMING__cmd__cmd__mrs 1
+#define R_SDRAM_TIMING__cmd__cmd__nop 0
+#define R_SDRAM_TIMING__cmd__cmd__pre 3
+#define R_SDRAM_TIMING__cmd__cmd__ref 2
+
+#endif
+
+/*
+ * R_SERIAL0_BAUD
+ * - type: WO
+ * - addr: 0xb0000063
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_BAUD__ADDR (REG_TYPECAST_BYTE 0xb0000063)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL0_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 3))
+#define R_SERIAL0_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 3))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL0_BAUD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL0_BAUD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL0_BAUD__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL0_BAUD__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_BAUD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_BAUD__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL0_BAUD__TYPE (REG_BYTE)
+#define R_SERIAL0_BAUD__GET REG_GET_WO
+#define R_SERIAL0_BAUD__IGET REG_IGET_WO
+#define R_SERIAL0_BAUD__SET REG_SET_WO
+#define R_SERIAL0_BAUD__ISET REG_ISET_WO
+#define R_SERIAL0_BAUD__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL0_BAUD__EQL REG_EQL_WO
+#define R_SERIAL0_BAUD__IEQL REG_IEQL_WO
+#define R_SERIAL0_BAUD__RD REG_RD_WO
+#define R_SERIAL0_BAUD__IRD REG_IRD_WO
+#define R_SERIAL0_BAUD__WR REG_WR_WO
+#define R_SERIAL0_BAUD__IWR REG_IWR_WO
+
+#define R_SERIAL0_BAUD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_BAUD__FIRST 0
+#define R_SERIAL0_BAUD__IOFFSET 8
+#define R_SERIAL0_BAUD__LAST 3
+#define R_SERIAL0_BAUD__OFFSET 8
+#define R_SERIAL0_BAUD__SOFFSET 8
+/* end */
+
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__MASK 0x000000f0U
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__MASK 0x0000000fU
+
+#define R_SERIAL0_BAUD__tr_baud__MAX 0xf
+#define R_SERIAL0_BAUD__rec_baud__MAX 0xf
+
+#define R_SERIAL0_BAUD__tr_baud__MIN 0
+#define R_SERIAL0_BAUD__rec_baud__MIN 0
+
+#define R_SERIAL0_BAUD__tr_baud__BITNR 4
+#define R_SERIAL0_BAUD__rec_baud__BITNR 0
+
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM
+
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c115k2Hz 9
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c1200Hz 2
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c1843k2Hz 13
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c19k2Hz 6
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c230k4Hz 10
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c2400Hz 3
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c300Hz 0
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c38k4Hz 7
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c460k8Hz 11
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c4800Hz 4
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c57k6Hz 8
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c600Hz 1
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c6250kHz 14
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c921k6Hz 12
+#define R_SERIAL0_BAUD__tr_baud__tr_baud__c9600Hz 5
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c115k2Hz 9
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c1200Hz 2
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c1843k2Hz 13
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c19k2Hz 6
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c230k4Hz 10
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c2400Hz 3
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c300Hz 0
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c38k4Hz 7
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c460k8Hz 11
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c4800Hz 4
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c57k6Hz 8
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c600Hz 1
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c6250kHz 14
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c921k6Hz 12
+#define R_SERIAL0_BAUD__rec_baud__rec_baud__c9600Hz 5
+
+#endif
+
+/*
+ * R_SERIAL0_CTRL
+ * - type: WO
+ * - addr: 0xb0000060
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000060)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL0_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL0_CTRL + 0))
+#define R_SERIAL0_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL0_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL0_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SERIAL0_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL0_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_SERIAL0_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL0_CTRL__TYPE (REG_UDWORD)
+#define R_SERIAL0_CTRL__GET REG_GET_WO
+#define R_SERIAL0_CTRL__IGET REG_IGET_WO
+#define R_SERIAL0_CTRL__SET REG_SET_WO
+#define R_SERIAL0_CTRL__ISET REG_ISET_WO
+#define R_SERIAL0_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL0_CTRL__EQL REG_EQL_WO
+#define R_SERIAL0_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL0_CTRL__RD REG_RD_WO
+#define R_SERIAL0_CTRL__IRD REG_IRD_WO
+#define R_SERIAL0_CTRL__WR REG_WR_WO
+#define R_SERIAL0_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL0_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_CTRL__FIRST 0
+#define R_SERIAL0_CTRL__IOFFSET 8
+#define R_SERIAL0_CTRL__LAST 3
+#define R_SERIAL0_CTRL__OFFSET 8
+#define R_SERIAL0_CTRL__SOFFSET 8
+/* end */
+
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__MASK 0x0f000000U
+#define R_SERIAL0_CTRL__dma_err__dma_err__MASK 0x00800000U
+#define R_SERIAL0_CTRL__rec_enable__rec_enable__MASK 0x00400000U
+#define R_SERIAL0_CTRL__rts___rts___MASK 0x00200000U
+#define R_SERIAL0_CTRL__sampling__sampling__MASK 0x00100000U
+#define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U
+#define R_SERIAL0_CTRL__rec_par__rec_par__MASK 0x00040000U
+#define R_SERIAL0_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U
+#define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U
+#define R_SERIAL0_CTRL__txd__txd__MASK 0x00008000U
+#define R_SERIAL0_CTRL__tr_enable__tr_enable__MASK 0x00004000U
+#define R_SERIAL0_CTRL__auto_cts__auto_cts__MASK 0x00002000U
+#define R_SERIAL0_CTRL__stop_bits__stop_bits__MASK 0x00001000U
+#define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U
+#define R_SERIAL0_CTRL__tr_par__tr_par__MASK 0x00000400U
+#define R_SERIAL0_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U
+#define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U
+#define R_SERIAL0_CTRL__data_out__data_out__MASK 0x000000ffU
+
+#define R_SERIAL0_CTRL__tr_baud__MAX 0xf
+#define R_SERIAL0_CTRL__rec_baud__MAX 0xf
+#define R_SERIAL0_CTRL__dma_err__MAX 0x1
+#define R_SERIAL0_CTRL__rec_enable__MAX 0x1
+#define R_SERIAL0_CTRL__rts___MAX 0x1
+#define R_SERIAL0_CTRL__sampling__MAX 0x1
+#define R_SERIAL0_CTRL__rec_stick_par__MAX 0x1
+#define R_SERIAL0_CTRL__rec_par__MAX 0x1
+#define R_SERIAL0_CTRL__rec_par_en__MAX 0x1
+#define R_SERIAL0_CTRL__rec_bitnr__MAX 0x1
+#define R_SERIAL0_CTRL__txd__MAX 0x1
+#define R_SERIAL0_CTRL__tr_enable__MAX 0x1
+#define R_SERIAL0_CTRL__auto_cts__MAX 0x1
+#define R_SERIAL0_CTRL__stop_bits__MAX 0x1
+#define R_SERIAL0_CTRL__tr_stick_par__MAX 0x1
+#define R_SERIAL0_CTRL__tr_par__MAX 0x1
+#define R_SERIAL0_CTRL__tr_par_en__MAX 0x1
+#define R_SERIAL0_CTRL__tr_bitnr__MAX 0x1
+#define R_SERIAL0_CTRL__data_out__MAX 0xff
+
+#define R_SERIAL0_CTRL__tr_baud__MIN 0
+#define R_SERIAL0_CTRL__rec_baud__MIN 0
+#define R_SERIAL0_CTRL__dma_err__MIN 0
+#define R_SERIAL0_CTRL__rec_enable__MIN 0
+#define R_SERIAL0_CTRL__rts___MIN 0
+#define R_SERIAL0_CTRL__sampling__MIN 0
+#define R_SERIAL0_CTRL__rec_stick_par__MIN 0
+#define R_SERIAL0_CTRL__rec_par__MIN 0
+#define R_SERIAL0_CTRL__rec_par_en__MIN 0
+#define R_SERIAL0_CTRL__rec_bitnr__MIN 0
+#define R_SERIAL0_CTRL__txd__MIN 0
+#define R_SERIAL0_CTRL__tr_enable__MIN 0
+#define R_SERIAL0_CTRL__auto_cts__MIN 0
+#define R_SERIAL0_CTRL__stop_bits__MIN 0
+#define R_SERIAL0_CTRL__tr_stick_par__MIN 0
+#define R_SERIAL0_CTRL__tr_par__MIN 0
+#define R_SERIAL0_CTRL__tr_par_en__MIN 0
+#define R_SERIAL0_CTRL__tr_bitnr__MIN 0
+#define R_SERIAL0_CTRL__data_out__MIN 0
+
+#define R_SERIAL0_CTRL__tr_baud__BITNR 28
+#define R_SERIAL0_CTRL__rec_baud__BITNR 24
+#define R_SERIAL0_CTRL__dma_err__BITNR 23
+#define R_SERIAL0_CTRL__rec_enable__BITNR 22
+#define R_SERIAL0_CTRL__rts___BITNR 21
+#define R_SERIAL0_CTRL__sampling__BITNR 20
+#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19
+#define R_SERIAL0_CTRL__rec_par__BITNR 18
+#define R_SERIAL0_CTRL__rec_par_en__BITNR 17
+#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16
+#define R_SERIAL0_CTRL__txd__BITNR 15
+#define R_SERIAL0_CTRL__tr_enable__BITNR 14
+#define R_SERIAL0_CTRL__auto_cts__BITNR 13
+#define R_SERIAL0_CTRL__stop_bits__BITNR 12
+#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11
+#define R_SERIAL0_CTRL__tr_par__BITNR 10
+#define R_SERIAL0_CTRL__tr_par_en__BITNR 9
+#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8
+#define R_SERIAL0_CTRL__data_out__BITNR 0
+
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__rts___rts___VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__sampling__sampling__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__txd__txd__VAL REG_VAL_VAL
+#define R_SERIAL0_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
+#define R_SERIAL0_CTRL__data_out__data_out__VAL REG_VAL_VAL
+
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c115k2Hz 9
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c1200Hz 2
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c1843k2Hz 13
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c19k2Hz 6
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c230k4Hz 10
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c2400Hz 3
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c300Hz 0
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c38k4Hz 7
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c460k8Hz 11
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c4800Hz 4
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c57k6Hz 8
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c600Hz 1
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c6250kHz 14
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c921k6Hz 12
+#define R_SERIAL0_CTRL__tr_baud__tr_baud__c9600Hz 5
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c115k2Hz 9
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c1200Hz 2
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c1843k2Hz 13
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c19k2Hz 6
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c230k4Hz 10
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c2400Hz 3
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c300Hz 0
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c38k4Hz 7
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c460k8Hz 11
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c4800Hz 4
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c57k6Hz 8
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c600Hz 1
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c6250kHz 14
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c921k6Hz 12
+#define R_SERIAL0_CTRL__rec_baud__rec_baud__c9600Hz 5
+#define R_SERIAL0_CTRL__dma_err__dma_err__ignore 1
+#define R_SERIAL0_CTRL__dma_err__dma_err__stop 0
+#define R_SERIAL0_CTRL__rec_enable__rec_enable__disable 0
+#define R_SERIAL0_CTRL__rec_enable__rec_enable__enable 1
+#define R_SERIAL0_CTRL__rts___rts___active 0
+#define R_SERIAL0_CTRL__rts___rts___inactive 1
+#define R_SERIAL0_CTRL__sampling__sampling__majority 1
+#define R_SERIAL0_CTRL__sampling__sampling__middle 0
+#define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__normal 0
+#define R_SERIAL0_CTRL__rec_stick_par__rec_stick_par__stick 1
+#define R_SERIAL0_CTRL__rec_par__rec_par__even 0
+#define R_SERIAL0_CTRL__rec_par__rec_par__odd 1
+#define R_SERIAL0_CTRL__rec_par_en__rec_par_en__disable 0
+#define R_SERIAL0_CTRL__rec_par_en__rec_par_en__enable 1
+#define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
+#define R_SERIAL0_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
+#define R_SERIAL0_CTRL__tr_enable__tr_enable__disable 0
+#define R_SERIAL0_CTRL__tr_enable__tr_enable__enable 1
+#define R_SERIAL0_CTRL__auto_cts__auto_cts__active 1
+#define R_SERIAL0_CTRL__auto_cts__auto_cts__disabled 0
+#define R_SERIAL0_CTRL__stop_bits__stop_bits__one_bit 0
+#define R_SERIAL0_CTRL__stop_bits__stop_bits__two_bits 1
+#define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__normal 0
+#define R_SERIAL0_CTRL__tr_stick_par__tr_stick_par__stick 1
+#define R_SERIAL0_CTRL__tr_par__tr_par__even 0
+#define R_SERIAL0_CTRL__tr_par__tr_par__odd 1
+#define R_SERIAL0_CTRL__tr_par_en__tr_par_en__disable 0
+#define R_SERIAL0_CTRL__tr_par_en__tr_par_en__enable 1
+#define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
+#define R_SERIAL0_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL0_READ
+ * - type: RO
+ * - addr: 0xb0000060
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000060)
+#define R_SERIAL0_READ__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_READ__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL0_READ__TYPE (REG_UDWORD)
+#define R_SERIAL0_READ__GET REG_GET_RO
+#define R_SERIAL0_READ__IGET REG_IGET_RO
+#define R_SERIAL0_READ__SET REG_SET_RO
+#define R_SERIAL0_READ__ISET REG_ISET_RO
+#define R_SERIAL0_READ__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL0_READ__EQL REG_EQL_RO
+#define R_SERIAL0_READ__IEQL REG_IEQL_RO
+#define R_SERIAL0_READ__RD REG_RD_RO
+#define R_SERIAL0_READ__IRD REG_IRD_RO
+#define R_SERIAL0_READ__WR REG_WR_RO
+#define R_SERIAL0_READ__IWR REG_IWR_RO
+
+#define R_SERIAL0_READ__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_READ__FIRST 0
+#define R_SERIAL0_READ__LAST 3
+#define R_SERIAL0_READ__OFFSET 8
+/* end */
+
+#define R_SERIAL0_READ__xoff_detect__xoff_detect__MASK 0x00008000U
+#define R_SERIAL0_READ__cts___cts___MASK 0x00004000U
+#define R_SERIAL0_READ__tr_ready__tr_ready__MASK 0x00002000U
+#define R_SERIAL0_READ__rxd__rxd__MASK 0x00001000U
+#define R_SERIAL0_READ__overrun__overrun__MASK 0x00000800U
+#define R_SERIAL0_READ__par_err__par_err__MASK 0x00000400U
+#define R_SERIAL0_READ__framing_err__framing_err__MASK 0x00000200U
+#define R_SERIAL0_READ__data_avail__data_avail__MASK 0x00000100U
+#define R_SERIAL0_READ__data_in__data_in__MASK 0x000000ffU
+
+#define R_SERIAL0_READ__xoff_detect__MAX 0x1
+#define R_SERIAL0_READ__cts___MAX 0x1
+#define R_SERIAL0_READ__tr_ready__MAX 0x1
+#define R_SERIAL0_READ__rxd__MAX 0x1
+#define R_SERIAL0_READ__overrun__MAX 0x1
+#define R_SERIAL0_READ__par_err__MAX 0x1
+#define R_SERIAL0_READ__framing_err__MAX 0x1
+#define R_SERIAL0_READ__data_avail__MAX 0x1
+#define R_SERIAL0_READ__data_in__MAX 0xff
+
+#define R_SERIAL0_READ__xoff_detect__MIN 0
+#define R_SERIAL0_READ__cts___MIN 0
+#define R_SERIAL0_READ__tr_ready__MIN 0
+#define R_SERIAL0_READ__rxd__MIN 0
+#define R_SERIAL0_READ__overrun__MIN 0
+#define R_SERIAL0_READ__par_err__MIN 0
+#define R_SERIAL0_READ__framing_err__MIN 0
+#define R_SERIAL0_READ__data_avail__MIN 0
+#define R_SERIAL0_READ__data_in__MIN 0
+
+#define R_SERIAL0_READ__xoff_detect__BITNR 15
+#define R_SERIAL0_READ__cts___BITNR 14
+#define R_SERIAL0_READ__tr_ready__BITNR 13
+#define R_SERIAL0_READ__rxd__BITNR 12
+#define R_SERIAL0_READ__overrun__BITNR 11
+#define R_SERIAL0_READ__par_err__BITNR 10
+#define R_SERIAL0_READ__framing_err__BITNR 9
+#define R_SERIAL0_READ__data_avail__BITNR 8
+#define R_SERIAL0_READ__data_in__BITNR 0
+
+#define R_SERIAL0_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
+#define R_SERIAL0_READ__cts___cts___VAL REG_VAL_ENUM
+#define R_SERIAL0_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SERIAL0_READ__rxd__rxd__VAL REG_VAL_VAL
+#define R_SERIAL0_READ__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SERIAL0_READ__par_err__par_err__VAL REG_VAL_ENUM
+#define R_SERIAL0_READ__framing_err__framing_err__VAL REG_VAL_ENUM
+#define R_SERIAL0_READ__data_avail__data_avail__VAL REG_VAL_ENUM
+#define R_SERIAL0_READ__data_in__data_in__VAL REG_VAL_VAL
+
+#define R_SERIAL0_READ__xoff_detect__xoff_detect__no_xoff 0
+#define R_SERIAL0_READ__xoff_detect__xoff_detect__xoff 1
+#define R_SERIAL0_READ__cts___cts___active 0
+#define R_SERIAL0_READ__cts___cts___inactive 1
+#define R_SERIAL0_READ__tr_ready__tr_ready__full 0
+#define R_SERIAL0_READ__tr_ready__tr_ready__ready 1
+#define R_SERIAL0_READ__overrun__overrun__no 0
+#define R_SERIAL0_READ__overrun__overrun__yes 1
+#define R_SERIAL0_READ__par_err__par_err__no 0
+#define R_SERIAL0_READ__par_err__par_err__yes 1
+#define R_SERIAL0_READ__framing_err__framing_err__no 0
+#define R_SERIAL0_READ__framing_err__framing_err__yes 1
+#define R_SERIAL0_READ__data_avail__data_avail__no 0
+#define R_SERIAL0_READ__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SERIAL0_REC_CTRL
+ * - type: WO
+ * - addr: 0xb0000062
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000062)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL0_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 2))
+#define R_SERIAL0_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 2))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL0_REC_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL0_REC_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL0_REC_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL0_REC_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_REC_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL0_REC_CTRL__TYPE (REG_BYTE)
+#define R_SERIAL0_REC_CTRL__GET REG_GET_WO
+#define R_SERIAL0_REC_CTRL__IGET REG_IGET_WO
+#define R_SERIAL0_REC_CTRL__SET REG_SET_WO
+#define R_SERIAL0_REC_CTRL__ISET REG_ISET_WO
+#define R_SERIAL0_REC_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL0_REC_CTRL__EQL REG_EQL_WO
+#define R_SERIAL0_REC_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL0_REC_CTRL__RD REG_RD_WO
+#define R_SERIAL0_REC_CTRL__IRD REG_IRD_WO
+#define R_SERIAL0_REC_CTRL__WR REG_WR_WO
+#define R_SERIAL0_REC_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL0_REC_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_REC_CTRL__FIRST 0
+#define R_SERIAL0_REC_CTRL__IOFFSET 8
+#define R_SERIAL0_REC_CTRL__LAST 3
+#define R_SERIAL0_REC_CTRL__OFFSET 8
+#define R_SERIAL0_REC_CTRL__SOFFSET 8
+/* end */
+
+#define R_SERIAL0_REC_CTRL__dma_err__dma_err__MASK 0x00000080U
+#define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U
+#define R_SERIAL0_REC_CTRL__rts___rts___MASK 0x00000020U
+#define R_SERIAL0_REC_CTRL__sampling__sampling__MASK 0x00000010U
+#define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U
+#define R_SERIAL0_REC_CTRL__rec_par__rec_par__MASK 0x00000004U
+#define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U
+#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U
+
+#define R_SERIAL0_REC_CTRL__dma_err__MAX 0x1
+#define R_SERIAL0_REC_CTRL__rec_enable__MAX 0x1
+#define R_SERIAL0_REC_CTRL__rts___MAX 0x1
+#define R_SERIAL0_REC_CTRL__sampling__MAX 0x1
+#define R_SERIAL0_REC_CTRL__rec_stick_par__MAX 0x1
+#define R_SERIAL0_REC_CTRL__rec_par__MAX 0x1
+#define R_SERIAL0_REC_CTRL__rec_par_en__MAX 0x1
+#define R_SERIAL0_REC_CTRL__rec_bitnr__MAX 0x1
+
+#define R_SERIAL0_REC_CTRL__dma_err__MIN 0
+#define R_SERIAL0_REC_CTRL__rec_enable__MIN 0
+#define R_SERIAL0_REC_CTRL__rts___MIN 0
+#define R_SERIAL0_REC_CTRL__sampling__MIN 0
+#define R_SERIAL0_REC_CTRL__rec_stick_par__MIN 0
+#define R_SERIAL0_REC_CTRL__rec_par__MIN 0
+#define R_SERIAL0_REC_CTRL__rec_par_en__MIN 0
+#define R_SERIAL0_REC_CTRL__rec_bitnr__MIN 0
+
+#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7
+#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6
+#define R_SERIAL0_REC_CTRL__rts___BITNR 5
+#define R_SERIAL0_REC_CTRL__sampling__BITNR 4
+#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3
+#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2
+#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1
+#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0
+
+#define R_SERIAL0_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
+#define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SERIAL0_REC_CTRL__rts___rts___VAL REG_VAL_ENUM
+#define R_SERIAL0_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM
+#define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL0_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
+#define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
+
+#define R_SERIAL0_REC_CTRL__dma_err__dma_err__ignore 1
+#define R_SERIAL0_REC_CTRL__dma_err__dma_err__stop 0
+#define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__disable 0
+#define R_SERIAL0_REC_CTRL__rec_enable__rec_enable__enable 1
+#define R_SERIAL0_REC_CTRL__rts___rts___active 0
+#define R_SERIAL0_REC_CTRL__rts___rts___inactive 1
+#define R_SERIAL0_REC_CTRL__sampling__sampling__majority 1
+#define R_SERIAL0_REC_CTRL__sampling__sampling__middle 0
+#define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__normal 0
+#define R_SERIAL0_REC_CTRL__rec_stick_par__rec_stick_par__stick 1
+#define R_SERIAL0_REC_CTRL__rec_par__rec_par__even 0
+#define R_SERIAL0_REC_CTRL__rec_par__rec_par__odd 1
+#define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__disable 0
+#define R_SERIAL0_REC_CTRL__rec_par_en__rec_par_en__enable 1
+#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
+#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL0_REC_DATA
+ * - type: RO
+ * - addr: 0xb0000060
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000060)
+#define R_SERIAL0_REC_DATA__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_REC_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL0_REC_DATA__TYPE (REG_BYTE)
+#define R_SERIAL0_REC_DATA__GET REG_GET_RO
+#define R_SERIAL0_REC_DATA__IGET REG_IGET_RO
+#define R_SERIAL0_REC_DATA__SET REG_SET_RO
+#define R_SERIAL0_REC_DATA__ISET REG_ISET_RO
+#define R_SERIAL0_REC_DATA__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL0_REC_DATA__EQL REG_EQL_RO
+#define R_SERIAL0_REC_DATA__IEQL REG_IEQL_RO
+#define R_SERIAL0_REC_DATA__RD REG_RD_RO
+#define R_SERIAL0_REC_DATA__IRD REG_IRD_RO
+#define R_SERIAL0_REC_DATA__WR REG_WR_RO
+#define R_SERIAL0_REC_DATA__IWR REG_IWR_RO
+
+#define R_SERIAL0_REC_DATA__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_REC_DATA__FIRST 0
+#define R_SERIAL0_REC_DATA__LAST 3
+#define R_SERIAL0_REC_DATA__OFFSET 8
+/* end */
+
+#define R_SERIAL0_REC_DATA__data_in__data_in__MASK 0x000000ffU
+
+#define R_SERIAL0_REC_DATA__data_in__MAX 0xff
+
+#define R_SERIAL0_REC_DATA__data_in__MIN 0
+
+#define R_SERIAL0_REC_DATA__data_in__BITNR 0
+
+#define R_SERIAL0_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SERIAL0_STATUS
+ * - type: RO
+ * - addr: 0xb0000061
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000061)
+#define R_SERIAL0_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL0_STATUS__TYPE (REG_BYTE)
+#define R_SERIAL0_STATUS__GET REG_GET_RO
+#define R_SERIAL0_STATUS__IGET REG_IGET_RO
+#define R_SERIAL0_STATUS__SET REG_SET_RO
+#define R_SERIAL0_STATUS__ISET REG_ISET_RO
+#define R_SERIAL0_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL0_STATUS__EQL REG_EQL_RO
+#define R_SERIAL0_STATUS__IEQL REG_IEQL_RO
+#define R_SERIAL0_STATUS__RD REG_RD_RO
+#define R_SERIAL0_STATUS__IRD REG_IRD_RO
+#define R_SERIAL0_STATUS__WR REG_WR_RO
+#define R_SERIAL0_STATUS__IWR REG_IWR_RO
+
+#define R_SERIAL0_STATUS__READ(addr) \
+ (*(addr))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_STATUS__FIRST 0
+#define R_SERIAL0_STATUS__LAST 3
+#define R_SERIAL0_STATUS__OFFSET 8
+/* end */
+
+#define R_SERIAL0_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U
+#define R_SERIAL0_STATUS__cts___cts___MASK 0x00000040U
+#define R_SERIAL0_STATUS__tr_ready__tr_ready__MASK 0x00000020U
+#define R_SERIAL0_STATUS__rxd__rxd__MASK 0x00000010U
+#define R_SERIAL0_STATUS__overrun__overrun__MASK 0x00000008U
+#define R_SERIAL0_STATUS__par_err__par_err__MASK 0x00000004U
+#define R_SERIAL0_STATUS__framing_err__framing_err__MASK 0x00000002U
+#define R_SERIAL0_STATUS__data_avail__data_avail__MASK 0x00000001U
+
+#define R_SERIAL0_STATUS__xoff_detect__MAX 0x1
+#define R_SERIAL0_STATUS__cts___MAX 0x1
+#define R_SERIAL0_STATUS__tr_ready__MAX 0x1
+#define R_SERIAL0_STATUS__rxd__MAX 0x1
+#define R_SERIAL0_STATUS__overrun__MAX 0x1
+#define R_SERIAL0_STATUS__par_err__MAX 0x1
+#define R_SERIAL0_STATUS__framing_err__MAX 0x1
+#define R_SERIAL0_STATUS__data_avail__MAX 0x1
+
+#define R_SERIAL0_STATUS__xoff_detect__MIN 0
+#define R_SERIAL0_STATUS__cts___MIN 0
+#define R_SERIAL0_STATUS__tr_ready__MIN 0
+#define R_SERIAL0_STATUS__rxd__MIN 0
+#define R_SERIAL0_STATUS__overrun__MIN 0
+#define R_SERIAL0_STATUS__par_err__MIN 0
+#define R_SERIAL0_STATUS__framing_err__MIN 0
+#define R_SERIAL0_STATUS__data_avail__MIN 0
+
+#define R_SERIAL0_STATUS__xoff_detect__BITNR 7
+#define R_SERIAL0_STATUS__cts___BITNR 6
+#define R_SERIAL0_STATUS__tr_ready__BITNR 5
+#define R_SERIAL0_STATUS__rxd__BITNR 4
+#define R_SERIAL0_STATUS__overrun__BITNR 3
+#define R_SERIAL0_STATUS__par_err__BITNR 2
+#define R_SERIAL0_STATUS__framing_err__BITNR 1
+#define R_SERIAL0_STATUS__data_avail__BITNR 0
+
+#define R_SERIAL0_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
+#define R_SERIAL0_STATUS__cts___cts___VAL REG_VAL_ENUM
+#define R_SERIAL0_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SERIAL0_STATUS__rxd__rxd__VAL REG_VAL_VAL
+#define R_SERIAL0_STATUS__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SERIAL0_STATUS__par_err__par_err__VAL REG_VAL_ENUM
+#define R_SERIAL0_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM
+#define R_SERIAL0_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
+
+#define R_SERIAL0_STATUS__xoff_detect__xoff_detect__no_xoff 0
+#define R_SERIAL0_STATUS__xoff_detect__xoff_detect__xoff 1
+#define R_SERIAL0_STATUS__cts___cts___active 0
+#define R_SERIAL0_STATUS__cts___cts___inactive 1
+#define R_SERIAL0_STATUS__tr_ready__tr_ready__full 0
+#define R_SERIAL0_STATUS__tr_ready__tr_ready__ready 1
+#define R_SERIAL0_STATUS__overrun__overrun__no 0
+#define R_SERIAL0_STATUS__overrun__overrun__yes 1
+#define R_SERIAL0_STATUS__par_err__par_err__no 0
+#define R_SERIAL0_STATUS__par_err__par_err__yes 1
+#define R_SERIAL0_STATUS__framing_err__framing_err__no 0
+#define R_SERIAL0_STATUS__framing_err__framing_err__yes 1
+#define R_SERIAL0_STATUS__data_avail__data_avail__no 0
+#define R_SERIAL0_STATUS__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SERIAL0_TR_CTRL
+ * - type: WO
+ * - addr: 0xb0000061
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000061)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL0_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 1))
+#define R_SERIAL0_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 1))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL0_TR_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL0_TR_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL0_TR_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL0_TR_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_TR_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL0_TR_CTRL__TYPE (REG_BYTE)
+#define R_SERIAL0_TR_CTRL__GET REG_GET_WO
+#define R_SERIAL0_TR_CTRL__IGET REG_IGET_WO
+#define R_SERIAL0_TR_CTRL__SET REG_SET_WO
+#define R_SERIAL0_TR_CTRL__ISET REG_ISET_WO
+#define R_SERIAL0_TR_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL0_TR_CTRL__EQL REG_EQL_WO
+#define R_SERIAL0_TR_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL0_TR_CTRL__RD REG_RD_WO
+#define R_SERIAL0_TR_CTRL__IRD REG_IRD_WO
+#define R_SERIAL0_TR_CTRL__WR REG_WR_WO
+#define R_SERIAL0_TR_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL0_TR_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_TR_CTRL__FIRST 0
+#define R_SERIAL0_TR_CTRL__IOFFSET 8
+#define R_SERIAL0_TR_CTRL__LAST 3
+#define R_SERIAL0_TR_CTRL__OFFSET 8
+#define R_SERIAL0_TR_CTRL__SOFFSET 8
+/* end */
+
+#define R_SERIAL0_TR_CTRL__txd__txd__MASK 0x00000080U
+#define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U
+#define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U
+#define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U
+#define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U
+#define R_SERIAL0_TR_CTRL__tr_par__tr_par__MASK 0x00000004U
+#define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U
+#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U
+
+#define R_SERIAL0_TR_CTRL__txd__MAX 0x1
+#define R_SERIAL0_TR_CTRL__tr_enable__MAX 0x1
+#define R_SERIAL0_TR_CTRL__auto_cts__MAX 0x1
+#define R_SERIAL0_TR_CTRL__stop_bits__MAX 0x1
+#define R_SERIAL0_TR_CTRL__tr_stick_par__MAX 0x1
+#define R_SERIAL0_TR_CTRL__tr_par__MAX 0x1
+#define R_SERIAL0_TR_CTRL__tr_par_en__MAX 0x1
+#define R_SERIAL0_TR_CTRL__tr_bitnr__MAX 0x1
+
+#define R_SERIAL0_TR_CTRL__txd__MIN 0
+#define R_SERIAL0_TR_CTRL__tr_enable__MIN 0
+#define R_SERIAL0_TR_CTRL__auto_cts__MIN 0
+#define R_SERIAL0_TR_CTRL__stop_bits__MIN 0
+#define R_SERIAL0_TR_CTRL__tr_stick_par__MIN 0
+#define R_SERIAL0_TR_CTRL__tr_par__MIN 0
+#define R_SERIAL0_TR_CTRL__tr_par_en__MIN 0
+#define R_SERIAL0_TR_CTRL__tr_bitnr__MIN 0
+
+#define R_SERIAL0_TR_CTRL__txd__BITNR 7
+#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6
+#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5
+#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4
+#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3
+#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2
+#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1
+#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0
+
+#define R_SERIAL0_TR_CTRL__txd__txd__VAL REG_VAL_VAL
+#define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
+#define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
+#define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL0_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
+#define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
+
+#define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__disable 0
+#define R_SERIAL0_TR_CTRL__tr_enable__tr_enable__enable 1
+#define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__active 1
+#define R_SERIAL0_TR_CTRL__auto_cts__auto_cts__disabled 0
+#define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__one_bit 0
+#define R_SERIAL0_TR_CTRL__stop_bits__stop_bits__two_bits 1
+#define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__normal 0
+#define R_SERIAL0_TR_CTRL__tr_stick_par__tr_stick_par__stick 1
+#define R_SERIAL0_TR_CTRL__tr_par__tr_par__even 0
+#define R_SERIAL0_TR_CTRL__tr_par__tr_par__odd 1
+#define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__disable 0
+#define R_SERIAL0_TR_CTRL__tr_par_en__tr_par_en__enable 1
+#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
+#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL0_TR_DATA
+ * - type: WO
+ * - addr: 0xb0000060
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000060)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL0_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL0_CTRL + 0))
+#define R_SERIAL0_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL0_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL0_TR_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL0_TR_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL0_TR_DATA__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL0_TR_DATA__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_TR_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL0_TR_DATA__TYPE (REG_BYTE)
+#define R_SERIAL0_TR_DATA__GET REG_GET_WO
+#define R_SERIAL0_TR_DATA__IGET REG_IGET_WO
+#define R_SERIAL0_TR_DATA__SET REG_SET_WO
+#define R_SERIAL0_TR_DATA__ISET REG_ISET_WO
+#define R_SERIAL0_TR_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL0_TR_DATA__EQL REG_EQL_WO
+#define R_SERIAL0_TR_DATA__IEQL REG_IEQL_WO
+#define R_SERIAL0_TR_DATA__RD REG_RD_WO
+#define R_SERIAL0_TR_DATA__IRD REG_IRD_WO
+#define R_SERIAL0_TR_DATA__WR REG_WR_WO
+#define R_SERIAL0_TR_DATA__IWR REG_IWR_WO
+
+#define R_SERIAL0_TR_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_TR_DATA__FIRST 0
+#define R_SERIAL0_TR_DATA__IOFFSET 8
+#define R_SERIAL0_TR_DATA__LAST 3
+#define R_SERIAL0_TR_DATA__OFFSET 8
+#define R_SERIAL0_TR_DATA__SOFFSET 8
+/* end */
+
+#define R_SERIAL0_TR_DATA__data_out__data_out__MASK 0x000000ffU
+
+#define R_SERIAL0_TR_DATA__data_out__MAX 0xff
+
+#define R_SERIAL0_TR_DATA__data_out__MIN 0
+
+#define R_SERIAL0_TR_DATA__data_out__BITNR 0
+
+#define R_SERIAL0_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SERIAL0_XOFF
+ * - type: WO
+ * - addr: 0xb0000064
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL0_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb0000064)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL0_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL0_XOFF + 0))
+#define R_SERIAL0_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL0_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL0_XOFF__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SERIAL0_XOFF__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL0_XOFF__STYPECAST REG_STYPECAST_UDWORD
+#define R_SERIAL0_XOFF__SVAL REG_SVAL_SHADOW
+#define R_SERIAL0_XOFF__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL0_XOFF__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL0_XOFF__TYPE (REG_UDWORD)
+#define R_SERIAL0_XOFF__GET REG_GET_WO
+#define R_SERIAL0_XOFF__IGET REG_IGET_WO
+#define R_SERIAL0_XOFF__SET REG_SET_WO
+#define R_SERIAL0_XOFF__ISET REG_ISET_WO
+#define R_SERIAL0_XOFF__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL0_XOFF__EQL REG_EQL_WO
+#define R_SERIAL0_XOFF__IEQL REG_IEQL_WO
+#define R_SERIAL0_XOFF__RD REG_RD_WO
+#define R_SERIAL0_XOFF__IRD REG_IRD_WO
+#define R_SERIAL0_XOFF__WR REG_WR_WO
+#define R_SERIAL0_XOFF__IWR REG_IWR_WO
+
+#define R_SERIAL0_XOFF__WRITE(addr,value) \
+ (*(addr) = (value))
+
+/* From control-file '/n/asic/projects/etrax_ng/include//hwregs.ctrl' */
+#define R_SERIAL0_XOFF__FIRST 0
+#define R_SERIAL0_XOFF__IOFFSET 8
+#define R_SERIAL0_XOFF__LAST 3
+#define R_SERIAL0_XOFF__OFFSET 8
+#define R_SERIAL0_XOFF__SOFFSET 8
+/* end */
+
+#define R_SERIAL0_XOFF__tx_stop__tx_stop__MASK 0x00000200U
+#define R_SERIAL0_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U
+#define R_SERIAL0_XOFF__xoff_char__xoff_char__MASK 0x000000ffU
+
+#define R_SERIAL0_XOFF__tx_stop__MAX 0x1
+#define R_SERIAL0_XOFF__auto_xoff__MAX 0x1
+#define R_SERIAL0_XOFF__xoff_char__MAX 0xff
+
+#define R_SERIAL0_XOFF__tx_stop__MIN 0
+#define R_SERIAL0_XOFF__auto_xoff__MIN 0
+#define R_SERIAL0_XOFF__xoff_char__MIN 0
+
+#define R_SERIAL0_XOFF__tx_stop__BITNR 9
+#define R_SERIAL0_XOFF__auto_xoff__BITNR 8
+#define R_SERIAL0_XOFF__xoff_char__BITNR 0
+
+#define R_SERIAL0_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM
+#define R_SERIAL0_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM
+#define R_SERIAL0_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL
+
+#define R_SERIAL0_XOFF__tx_stop__tx_stop__enable 0
+#define R_SERIAL0_XOFF__tx_stop__tx_stop__stop 1
+#define R_SERIAL0_XOFF__auto_xoff__auto_xoff__disable 0
+#define R_SERIAL0_XOFF__auto_xoff__auto_xoff__enable 1
+
+#endif
+
+/*
+ * R_SERIAL1_BAUD
+ * - type: WO
+ * - addr: 0xb000006b
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_BAUD__ADDR (REG_TYPECAST_BYTE 0xb000006b)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL1_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 3))
+#define R_SERIAL1_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 3))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL1_BAUD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL1_BAUD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL1_BAUD__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL1_BAUD__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_BAUD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_BAUD__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL1_BAUD__TYPE (REG_BYTE)
+#define R_SERIAL1_BAUD__GET REG_GET_WO
+#define R_SERIAL1_BAUD__IGET REG_IGET_WO
+#define R_SERIAL1_BAUD__SET REG_SET_WO
+#define R_SERIAL1_BAUD__ISET REG_ISET_WO
+#define R_SERIAL1_BAUD__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL1_BAUD__EQL REG_EQL_WO
+#define R_SERIAL1_BAUD__IEQL REG_IEQL_WO
+#define R_SERIAL1_BAUD__RD REG_RD_WO
+#define R_SERIAL1_BAUD__IRD REG_IRD_WO
+#define R_SERIAL1_BAUD__WR REG_WR_WO
+#define R_SERIAL1_BAUD__IWR REG_IWR_WO
+
+#define R_SERIAL1_BAUD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__MASK 0x000000f0U
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__MASK 0x0000000fU
+
+#define R_SERIAL1_BAUD__tr_baud__MAX 0xf
+#define R_SERIAL1_BAUD__rec_baud__MAX 0xf
+
+#define R_SERIAL1_BAUD__tr_baud__MIN 0
+#define R_SERIAL1_BAUD__rec_baud__MIN 0
+
+#define R_SERIAL1_BAUD__tr_baud__BITNR 4
+#define R_SERIAL1_BAUD__rec_baud__BITNR 0
+
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM
+
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c115k2Hz 9
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c1200Hz 2
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c1843k2Hz 13
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c19k2Hz 6
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c230k4Hz 10
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c2400Hz 3
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c300Hz 0
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c38k4Hz 7
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c460k8Hz 11
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c4800Hz 4
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c57k6Hz 8
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c600Hz 1
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c6250kHz 14
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c921k6Hz 12
+#define R_SERIAL1_BAUD__tr_baud__tr_baud__c9600Hz 5
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c115k2Hz 9
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c1200Hz 2
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c1843k2Hz 13
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c19k2Hz 6
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c230k4Hz 10
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c2400Hz 3
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c300Hz 0
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c38k4Hz 7
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c460k8Hz 11
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c4800Hz 4
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c57k6Hz 8
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c600Hz 1
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c6250kHz 14
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c921k6Hz 12
+#define R_SERIAL1_BAUD__rec_baud__rec_baud__c9600Hz 5
+
+#endif
+
+/*
+ * R_SERIAL1_CTRL
+ * - type: WO
+ * - addr: 0xb0000068
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000068)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_CTRL + 0))
+#define R_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL1_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_SERIAL1_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL1_CTRL__TYPE (REG_UDWORD)
+#define R_SERIAL1_CTRL__GET REG_GET_WO
+#define R_SERIAL1_CTRL__IGET REG_IGET_WO
+#define R_SERIAL1_CTRL__SET REG_SET_WO
+#define R_SERIAL1_CTRL__ISET REG_ISET_WO
+#define R_SERIAL1_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL1_CTRL__EQL REG_EQL_WO
+#define R_SERIAL1_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL1_CTRL__RD REG_RD_WO
+#define R_SERIAL1_CTRL__IRD REG_IRD_WO
+#define R_SERIAL1_CTRL__WR REG_WR_WO
+#define R_SERIAL1_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL1_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__MASK 0x0f000000U
+#define R_SERIAL1_CTRL__dma_err__dma_err__MASK 0x00800000U
+#define R_SERIAL1_CTRL__rec_enable__rec_enable__MASK 0x00400000U
+#define R_SERIAL1_CTRL__rts___rts___MASK 0x00200000U
+#define R_SERIAL1_CTRL__sampling__sampling__MASK 0x00100000U
+#define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U
+#define R_SERIAL1_CTRL__rec_par__rec_par__MASK 0x00040000U
+#define R_SERIAL1_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U
+#define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U
+#define R_SERIAL1_CTRL__txd__txd__MASK 0x00008000U
+#define R_SERIAL1_CTRL__tr_enable__tr_enable__MASK 0x00004000U
+#define R_SERIAL1_CTRL__auto_cts__auto_cts__MASK 0x00002000U
+#define R_SERIAL1_CTRL__stop_bits__stop_bits__MASK 0x00001000U
+#define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U
+#define R_SERIAL1_CTRL__tr_par__tr_par__MASK 0x00000400U
+#define R_SERIAL1_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U
+#define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U
+#define R_SERIAL1_CTRL__data_out__data_out__MASK 0x000000ffU
+
+#define R_SERIAL1_CTRL__tr_baud__MAX 0xf
+#define R_SERIAL1_CTRL__rec_baud__MAX 0xf
+#define R_SERIAL1_CTRL__dma_err__MAX 0x1
+#define R_SERIAL1_CTRL__rec_enable__MAX 0x1
+#define R_SERIAL1_CTRL__rts___MAX 0x1
+#define R_SERIAL1_CTRL__sampling__MAX 0x1
+#define R_SERIAL1_CTRL__rec_stick_par__MAX 0x1
+#define R_SERIAL1_CTRL__rec_par__MAX 0x1
+#define R_SERIAL1_CTRL__rec_par_en__MAX 0x1
+#define R_SERIAL1_CTRL__rec_bitnr__MAX 0x1
+#define R_SERIAL1_CTRL__txd__MAX 0x1
+#define R_SERIAL1_CTRL__tr_enable__MAX 0x1
+#define R_SERIAL1_CTRL__auto_cts__MAX 0x1
+#define R_SERIAL1_CTRL__stop_bits__MAX 0x1
+#define R_SERIAL1_CTRL__tr_stick_par__MAX 0x1
+#define R_SERIAL1_CTRL__tr_par__MAX 0x1
+#define R_SERIAL1_CTRL__tr_par_en__MAX 0x1
+#define R_SERIAL1_CTRL__tr_bitnr__MAX 0x1
+#define R_SERIAL1_CTRL__data_out__MAX 0xff
+
+#define R_SERIAL1_CTRL__tr_baud__MIN 0
+#define R_SERIAL1_CTRL__rec_baud__MIN 0
+#define R_SERIAL1_CTRL__dma_err__MIN 0
+#define R_SERIAL1_CTRL__rec_enable__MIN 0
+#define R_SERIAL1_CTRL__rts___MIN 0
+#define R_SERIAL1_CTRL__sampling__MIN 0
+#define R_SERIAL1_CTRL__rec_stick_par__MIN 0
+#define R_SERIAL1_CTRL__rec_par__MIN 0
+#define R_SERIAL1_CTRL__rec_par_en__MIN 0
+#define R_SERIAL1_CTRL__rec_bitnr__MIN 0
+#define R_SERIAL1_CTRL__txd__MIN 0
+#define R_SERIAL1_CTRL__tr_enable__MIN 0
+#define R_SERIAL1_CTRL__auto_cts__MIN 0
+#define R_SERIAL1_CTRL__stop_bits__MIN 0
+#define R_SERIAL1_CTRL__tr_stick_par__MIN 0
+#define R_SERIAL1_CTRL__tr_par__MIN 0
+#define R_SERIAL1_CTRL__tr_par_en__MIN 0
+#define R_SERIAL1_CTRL__tr_bitnr__MIN 0
+#define R_SERIAL1_CTRL__data_out__MIN 0
+
+#define R_SERIAL1_CTRL__tr_baud__BITNR 28
+#define R_SERIAL1_CTRL__rec_baud__BITNR 24
+#define R_SERIAL1_CTRL__dma_err__BITNR 23
+#define R_SERIAL1_CTRL__rec_enable__BITNR 22
+#define R_SERIAL1_CTRL__rts___BITNR 21
+#define R_SERIAL1_CTRL__sampling__BITNR 20
+#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19
+#define R_SERIAL1_CTRL__rec_par__BITNR 18
+#define R_SERIAL1_CTRL__rec_par_en__BITNR 17
+#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16
+#define R_SERIAL1_CTRL__txd__BITNR 15
+#define R_SERIAL1_CTRL__tr_enable__BITNR 14
+#define R_SERIAL1_CTRL__auto_cts__BITNR 13
+#define R_SERIAL1_CTRL__stop_bits__BITNR 12
+#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11
+#define R_SERIAL1_CTRL__tr_par__BITNR 10
+#define R_SERIAL1_CTRL__tr_par_en__BITNR 9
+#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8
+#define R_SERIAL1_CTRL__data_out__BITNR 0
+
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__rts___rts___VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__sampling__sampling__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__txd__txd__VAL REG_VAL_VAL
+#define R_SERIAL1_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
+#define R_SERIAL1_CTRL__data_out__data_out__VAL REG_VAL_VAL
+
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c115k2Hz 9
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c1200Hz 2
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c1843k2Hz 13
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c19k2Hz 6
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c230k4Hz 10
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c2400Hz 3
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c300Hz 0
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c38k4Hz 7
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c460k8Hz 11
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c4800Hz 4
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c57k6Hz 8
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c600Hz 1
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c6250kHz 14
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c921k6Hz 12
+#define R_SERIAL1_CTRL__tr_baud__tr_baud__c9600Hz 5
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c115k2Hz 9
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c1200Hz 2
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c1843k2Hz 13
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c19k2Hz 6
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c230k4Hz 10
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c2400Hz 3
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c300Hz 0
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c38k4Hz 7
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c460k8Hz 11
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c4800Hz 4
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c57k6Hz 8
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c600Hz 1
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c6250kHz 14
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c921k6Hz 12
+#define R_SERIAL1_CTRL__rec_baud__rec_baud__c9600Hz 5
+#define R_SERIAL1_CTRL__dma_err__dma_err__ignore 1
+#define R_SERIAL1_CTRL__dma_err__dma_err__stop 0
+#define R_SERIAL1_CTRL__rec_enable__rec_enable__disable 0
+#define R_SERIAL1_CTRL__rec_enable__rec_enable__enable 1
+#define R_SERIAL1_CTRL__rts___rts___active 0
+#define R_SERIAL1_CTRL__rts___rts___inactive 1
+#define R_SERIAL1_CTRL__sampling__sampling__majority 1
+#define R_SERIAL1_CTRL__sampling__sampling__middle 0
+#define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__normal 0
+#define R_SERIAL1_CTRL__rec_stick_par__rec_stick_par__stick 1
+#define R_SERIAL1_CTRL__rec_par__rec_par__even 0
+#define R_SERIAL1_CTRL__rec_par__rec_par__odd 1
+#define R_SERIAL1_CTRL__rec_par_en__rec_par_en__disable 0
+#define R_SERIAL1_CTRL__rec_par_en__rec_par_en__enable 1
+#define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
+#define R_SERIAL1_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
+#define R_SERIAL1_CTRL__tr_enable__tr_enable__disable 0
+#define R_SERIAL1_CTRL__tr_enable__tr_enable__enable 1
+#define R_SERIAL1_CTRL__auto_cts__auto_cts__active 1
+#define R_SERIAL1_CTRL__auto_cts__auto_cts__disabled 0
+#define R_SERIAL1_CTRL__stop_bits__stop_bits__one_bit 0
+#define R_SERIAL1_CTRL__stop_bits__stop_bits__two_bits 1
+#define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__normal 0
+#define R_SERIAL1_CTRL__tr_stick_par__tr_stick_par__stick 1
+#define R_SERIAL1_CTRL__tr_par__tr_par__even 0
+#define R_SERIAL1_CTRL__tr_par__tr_par__odd 1
+#define R_SERIAL1_CTRL__tr_par_en__tr_par_en__disable 0
+#define R_SERIAL1_CTRL__tr_par_en__tr_par_en__enable 1
+#define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
+#define R_SERIAL1_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL1_READ
+ * - type: RO
+ * - addr: 0xb0000068
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000068)
+#define R_SERIAL1_READ__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_READ__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL1_READ__TYPE (REG_UDWORD)
+#define R_SERIAL1_READ__GET REG_GET_RO
+#define R_SERIAL1_READ__IGET REG_IGET_RO
+#define R_SERIAL1_READ__SET REG_SET_RO
+#define R_SERIAL1_READ__ISET REG_ISET_RO
+#define R_SERIAL1_READ__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL1_READ__EQL REG_EQL_RO
+#define R_SERIAL1_READ__IEQL REG_IEQL_RO
+#define R_SERIAL1_READ__RD REG_RD_RO
+#define R_SERIAL1_READ__IRD REG_IRD_RO
+#define R_SERIAL1_READ__WR REG_WR_RO
+#define R_SERIAL1_READ__IWR REG_IWR_RO
+
+#define R_SERIAL1_READ__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL1_READ__xoff_detect__xoff_detect__MASK 0x00008000U
+#define R_SERIAL1_READ__cts___cts___MASK 0x00004000U
+#define R_SERIAL1_READ__tr_ready__tr_ready__MASK 0x00002000U
+#define R_SERIAL1_READ__rxd__rxd__MASK 0x00001000U
+#define R_SERIAL1_READ__overrun__overrun__MASK 0x00000800U
+#define R_SERIAL1_READ__par_err__par_err__MASK 0x00000400U
+#define R_SERIAL1_READ__framing_err__framing_err__MASK 0x00000200U
+#define R_SERIAL1_READ__data_avail__data_avail__MASK 0x00000100U
+#define R_SERIAL1_READ__data_in__data_in__MASK 0x000000ffU
+
+#define R_SERIAL1_READ__xoff_detect__MAX 0x1
+#define R_SERIAL1_READ__cts___MAX 0x1
+#define R_SERIAL1_READ__tr_ready__MAX 0x1
+#define R_SERIAL1_READ__rxd__MAX 0x1
+#define R_SERIAL1_READ__overrun__MAX 0x1
+#define R_SERIAL1_READ__par_err__MAX 0x1
+#define R_SERIAL1_READ__framing_err__MAX 0x1
+#define R_SERIAL1_READ__data_avail__MAX 0x1
+#define R_SERIAL1_READ__data_in__MAX 0xff
+
+#define R_SERIAL1_READ__xoff_detect__MIN 0
+#define R_SERIAL1_READ__cts___MIN 0
+#define R_SERIAL1_READ__tr_ready__MIN 0
+#define R_SERIAL1_READ__rxd__MIN 0
+#define R_SERIAL1_READ__overrun__MIN 0
+#define R_SERIAL1_READ__par_err__MIN 0
+#define R_SERIAL1_READ__framing_err__MIN 0
+#define R_SERIAL1_READ__data_avail__MIN 0
+#define R_SERIAL1_READ__data_in__MIN 0
+
+#define R_SERIAL1_READ__xoff_detect__BITNR 15
+#define R_SERIAL1_READ__cts___BITNR 14
+#define R_SERIAL1_READ__tr_ready__BITNR 13
+#define R_SERIAL1_READ__rxd__BITNR 12
+#define R_SERIAL1_READ__overrun__BITNR 11
+#define R_SERIAL1_READ__par_err__BITNR 10
+#define R_SERIAL1_READ__framing_err__BITNR 9
+#define R_SERIAL1_READ__data_avail__BITNR 8
+#define R_SERIAL1_READ__data_in__BITNR 0
+
+#define R_SERIAL1_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
+#define R_SERIAL1_READ__cts___cts___VAL REG_VAL_ENUM
+#define R_SERIAL1_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SERIAL1_READ__rxd__rxd__VAL REG_VAL_VAL
+#define R_SERIAL1_READ__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SERIAL1_READ__par_err__par_err__VAL REG_VAL_ENUM
+#define R_SERIAL1_READ__framing_err__framing_err__VAL REG_VAL_ENUM
+#define R_SERIAL1_READ__data_avail__data_avail__VAL REG_VAL_ENUM
+#define R_SERIAL1_READ__data_in__data_in__VAL REG_VAL_VAL
+
+#define R_SERIAL1_READ__xoff_detect__xoff_detect__no_xoff 0
+#define R_SERIAL1_READ__xoff_detect__xoff_detect__xoff 1
+#define R_SERIAL1_READ__cts___cts___active 0
+#define R_SERIAL1_READ__cts___cts___inactive 1
+#define R_SERIAL1_READ__tr_ready__tr_ready__full 0
+#define R_SERIAL1_READ__tr_ready__tr_ready__ready 1
+#define R_SERIAL1_READ__overrun__overrun__no 0
+#define R_SERIAL1_READ__overrun__overrun__yes 1
+#define R_SERIAL1_READ__par_err__par_err__no 0
+#define R_SERIAL1_READ__par_err__par_err__yes 1
+#define R_SERIAL1_READ__framing_err__framing_err__no 0
+#define R_SERIAL1_READ__framing_err__framing_err__yes 1
+#define R_SERIAL1_READ__data_avail__data_avail__no 0
+#define R_SERIAL1_READ__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SERIAL1_REC_CTRL
+ * - type: WO
+ * - addr: 0xb000006a
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb000006a)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL1_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 2))
+#define R_SERIAL1_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 2))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL1_REC_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL1_REC_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL1_REC_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL1_REC_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_REC_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL1_REC_CTRL__TYPE (REG_BYTE)
+#define R_SERIAL1_REC_CTRL__GET REG_GET_WO
+#define R_SERIAL1_REC_CTRL__IGET REG_IGET_WO
+#define R_SERIAL1_REC_CTRL__SET REG_SET_WO
+#define R_SERIAL1_REC_CTRL__ISET REG_ISET_WO
+#define R_SERIAL1_REC_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL1_REC_CTRL__EQL REG_EQL_WO
+#define R_SERIAL1_REC_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL1_REC_CTRL__RD REG_RD_WO
+#define R_SERIAL1_REC_CTRL__IRD REG_IRD_WO
+#define R_SERIAL1_REC_CTRL__WR REG_WR_WO
+#define R_SERIAL1_REC_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL1_REC_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL1_REC_CTRL__dma_err__dma_err__MASK 0x00000080U
+#define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U
+#define R_SERIAL1_REC_CTRL__rts___rts___MASK 0x00000020U
+#define R_SERIAL1_REC_CTRL__sampling__sampling__MASK 0x00000010U
+#define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U
+#define R_SERIAL1_REC_CTRL__rec_par__rec_par__MASK 0x00000004U
+#define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U
+#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U
+
+#define R_SERIAL1_REC_CTRL__dma_err__MAX 0x1
+#define R_SERIAL1_REC_CTRL__rec_enable__MAX 0x1
+#define R_SERIAL1_REC_CTRL__rts___MAX 0x1
+#define R_SERIAL1_REC_CTRL__sampling__MAX 0x1
+#define R_SERIAL1_REC_CTRL__rec_stick_par__MAX 0x1
+#define R_SERIAL1_REC_CTRL__rec_par__MAX 0x1
+#define R_SERIAL1_REC_CTRL__rec_par_en__MAX 0x1
+#define R_SERIAL1_REC_CTRL__rec_bitnr__MAX 0x1
+
+#define R_SERIAL1_REC_CTRL__dma_err__MIN 0
+#define R_SERIAL1_REC_CTRL__rec_enable__MIN 0
+#define R_SERIAL1_REC_CTRL__rts___MIN 0
+#define R_SERIAL1_REC_CTRL__sampling__MIN 0
+#define R_SERIAL1_REC_CTRL__rec_stick_par__MIN 0
+#define R_SERIAL1_REC_CTRL__rec_par__MIN 0
+#define R_SERIAL1_REC_CTRL__rec_par_en__MIN 0
+#define R_SERIAL1_REC_CTRL__rec_bitnr__MIN 0
+
+#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7
+#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6
+#define R_SERIAL1_REC_CTRL__rts___BITNR 5
+#define R_SERIAL1_REC_CTRL__sampling__BITNR 4
+#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3
+#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2
+#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1
+#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0
+
+#define R_SERIAL1_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
+#define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SERIAL1_REC_CTRL__rts___rts___VAL REG_VAL_ENUM
+#define R_SERIAL1_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM
+#define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL1_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
+#define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
+
+#define R_SERIAL1_REC_CTRL__dma_err__dma_err__ignore 1
+#define R_SERIAL1_REC_CTRL__dma_err__dma_err__stop 0
+#define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__disable 0
+#define R_SERIAL1_REC_CTRL__rec_enable__rec_enable__enable 1
+#define R_SERIAL1_REC_CTRL__rts___rts___active 0
+#define R_SERIAL1_REC_CTRL__rts___rts___inactive 1
+#define R_SERIAL1_REC_CTRL__sampling__sampling__majority 1
+#define R_SERIAL1_REC_CTRL__sampling__sampling__middle 0
+#define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__normal 0
+#define R_SERIAL1_REC_CTRL__rec_stick_par__rec_stick_par__stick 1
+#define R_SERIAL1_REC_CTRL__rec_par__rec_par__even 0
+#define R_SERIAL1_REC_CTRL__rec_par__rec_par__odd 1
+#define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__disable 0
+#define R_SERIAL1_REC_CTRL__rec_par_en__rec_par_en__enable 1
+#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
+#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL1_REC_DATA
+ * - type: RO
+ * - addr: 0xb0000068
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000068)
+#define R_SERIAL1_REC_DATA__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_REC_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL1_REC_DATA__TYPE (REG_BYTE)
+#define R_SERIAL1_REC_DATA__GET REG_GET_RO
+#define R_SERIAL1_REC_DATA__IGET REG_IGET_RO
+#define R_SERIAL1_REC_DATA__SET REG_SET_RO
+#define R_SERIAL1_REC_DATA__ISET REG_ISET_RO
+#define R_SERIAL1_REC_DATA__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL1_REC_DATA__EQL REG_EQL_RO
+#define R_SERIAL1_REC_DATA__IEQL REG_IEQL_RO
+#define R_SERIAL1_REC_DATA__RD REG_RD_RO
+#define R_SERIAL1_REC_DATA__IRD REG_IRD_RO
+#define R_SERIAL1_REC_DATA__WR REG_WR_RO
+#define R_SERIAL1_REC_DATA__IWR REG_IWR_RO
+
+#define R_SERIAL1_REC_DATA__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL1_REC_DATA__data_in__data_in__MASK 0x000000ffU
+
+#define R_SERIAL1_REC_DATA__data_in__MAX 0xff
+
+#define R_SERIAL1_REC_DATA__data_in__MIN 0
+
+#define R_SERIAL1_REC_DATA__data_in__BITNR 0
+
+#define R_SERIAL1_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SERIAL1_STATUS
+ * - type: RO
+ * - addr: 0xb0000069
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000069)
+#define R_SERIAL1_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL1_STATUS__TYPE (REG_BYTE)
+#define R_SERIAL1_STATUS__GET REG_GET_RO
+#define R_SERIAL1_STATUS__IGET REG_IGET_RO
+#define R_SERIAL1_STATUS__SET REG_SET_RO
+#define R_SERIAL1_STATUS__ISET REG_ISET_RO
+#define R_SERIAL1_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL1_STATUS__EQL REG_EQL_RO
+#define R_SERIAL1_STATUS__IEQL REG_IEQL_RO
+#define R_SERIAL1_STATUS__RD REG_RD_RO
+#define R_SERIAL1_STATUS__IRD REG_IRD_RO
+#define R_SERIAL1_STATUS__WR REG_WR_RO
+#define R_SERIAL1_STATUS__IWR REG_IWR_RO
+
+#define R_SERIAL1_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL1_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U
+#define R_SERIAL1_STATUS__cts___cts___MASK 0x00000040U
+#define R_SERIAL1_STATUS__tr_ready__tr_ready__MASK 0x00000020U
+#define R_SERIAL1_STATUS__rxd__rxd__MASK 0x00000010U
+#define R_SERIAL1_STATUS__overrun__overrun__MASK 0x00000008U
+#define R_SERIAL1_STATUS__par_err__par_err__MASK 0x00000004U
+#define R_SERIAL1_STATUS__framing_err__framing_err__MASK 0x00000002U
+#define R_SERIAL1_STATUS__data_avail__data_avail__MASK 0x00000001U
+
+#define R_SERIAL1_STATUS__xoff_detect__MAX 0x1
+#define R_SERIAL1_STATUS__cts___MAX 0x1
+#define R_SERIAL1_STATUS__tr_ready__MAX 0x1
+#define R_SERIAL1_STATUS__rxd__MAX 0x1
+#define R_SERIAL1_STATUS__overrun__MAX 0x1
+#define R_SERIAL1_STATUS__par_err__MAX 0x1
+#define R_SERIAL1_STATUS__framing_err__MAX 0x1
+#define R_SERIAL1_STATUS__data_avail__MAX 0x1
+
+#define R_SERIAL1_STATUS__xoff_detect__MIN 0
+#define R_SERIAL1_STATUS__cts___MIN 0
+#define R_SERIAL1_STATUS__tr_ready__MIN 0
+#define R_SERIAL1_STATUS__rxd__MIN 0
+#define R_SERIAL1_STATUS__overrun__MIN 0
+#define R_SERIAL1_STATUS__par_err__MIN 0
+#define R_SERIAL1_STATUS__framing_err__MIN 0
+#define R_SERIAL1_STATUS__data_avail__MIN 0
+
+#define R_SERIAL1_STATUS__xoff_detect__BITNR 7
+#define R_SERIAL1_STATUS__cts___BITNR 6
+#define R_SERIAL1_STATUS__tr_ready__BITNR 5
+#define R_SERIAL1_STATUS__rxd__BITNR 4
+#define R_SERIAL1_STATUS__overrun__BITNR 3
+#define R_SERIAL1_STATUS__par_err__BITNR 2
+#define R_SERIAL1_STATUS__framing_err__BITNR 1
+#define R_SERIAL1_STATUS__data_avail__BITNR 0
+
+#define R_SERIAL1_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
+#define R_SERIAL1_STATUS__cts___cts___VAL REG_VAL_ENUM
+#define R_SERIAL1_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SERIAL1_STATUS__rxd__rxd__VAL REG_VAL_VAL
+#define R_SERIAL1_STATUS__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SERIAL1_STATUS__par_err__par_err__VAL REG_VAL_ENUM
+#define R_SERIAL1_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM
+#define R_SERIAL1_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
+
+#define R_SERIAL1_STATUS__xoff_detect__xoff_detect__no_xoff 0
+#define R_SERIAL1_STATUS__xoff_detect__xoff_detect__xoff 1
+#define R_SERIAL1_STATUS__cts___cts___active 0
+#define R_SERIAL1_STATUS__cts___cts___inactive 1
+#define R_SERIAL1_STATUS__tr_ready__tr_ready__full 0
+#define R_SERIAL1_STATUS__tr_ready__tr_ready__ready 1
+#define R_SERIAL1_STATUS__overrun__overrun__no 0
+#define R_SERIAL1_STATUS__overrun__overrun__yes 1
+#define R_SERIAL1_STATUS__par_err__par_err__no 0
+#define R_SERIAL1_STATUS__par_err__par_err__yes 1
+#define R_SERIAL1_STATUS__framing_err__framing_err__no 0
+#define R_SERIAL1_STATUS__framing_err__framing_err__yes 1
+#define R_SERIAL1_STATUS__data_avail__data_avail__no 0
+#define R_SERIAL1_STATUS__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SERIAL1_TR_CTRL
+ * - type: WO
+ * - addr: 0xb0000069
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000069)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL1_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 1))
+#define R_SERIAL1_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 1))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL1_TR_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL1_TR_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL1_TR_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL1_TR_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_TR_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL1_TR_CTRL__TYPE (REG_BYTE)
+#define R_SERIAL1_TR_CTRL__GET REG_GET_WO
+#define R_SERIAL1_TR_CTRL__IGET REG_IGET_WO
+#define R_SERIAL1_TR_CTRL__SET REG_SET_WO
+#define R_SERIAL1_TR_CTRL__ISET REG_ISET_WO
+#define R_SERIAL1_TR_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL1_TR_CTRL__EQL REG_EQL_WO
+#define R_SERIAL1_TR_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL1_TR_CTRL__RD REG_RD_WO
+#define R_SERIAL1_TR_CTRL__IRD REG_IRD_WO
+#define R_SERIAL1_TR_CTRL__WR REG_WR_WO
+#define R_SERIAL1_TR_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL1_TR_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL1_TR_CTRL__txd__txd__MASK 0x00000080U
+#define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U
+#define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U
+#define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U
+#define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U
+#define R_SERIAL1_TR_CTRL__tr_par__tr_par__MASK 0x00000004U
+#define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U
+#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U
+
+#define R_SERIAL1_TR_CTRL__txd__MAX 0x1
+#define R_SERIAL1_TR_CTRL__tr_enable__MAX 0x1
+#define R_SERIAL1_TR_CTRL__auto_cts__MAX 0x1
+#define R_SERIAL1_TR_CTRL__stop_bits__MAX 0x1
+#define R_SERIAL1_TR_CTRL__tr_stick_par__MAX 0x1
+#define R_SERIAL1_TR_CTRL__tr_par__MAX 0x1
+#define R_SERIAL1_TR_CTRL__tr_par_en__MAX 0x1
+#define R_SERIAL1_TR_CTRL__tr_bitnr__MAX 0x1
+
+#define R_SERIAL1_TR_CTRL__txd__MIN 0
+#define R_SERIAL1_TR_CTRL__tr_enable__MIN 0
+#define R_SERIAL1_TR_CTRL__auto_cts__MIN 0
+#define R_SERIAL1_TR_CTRL__stop_bits__MIN 0
+#define R_SERIAL1_TR_CTRL__tr_stick_par__MIN 0
+#define R_SERIAL1_TR_CTRL__tr_par__MIN 0
+#define R_SERIAL1_TR_CTRL__tr_par_en__MIN 0
+#define R_SERIAL1_TR_CTRL__tr_bitnr__MIN 0
+
+#define R_SERIAL1_TR_CTRL__txd__BITNR 7
+#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6
+#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5
+#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4
+#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3
+#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2
+#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1
+#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0
+
+#define R_SERIAL1_TR_CTRL__txd__txd__VAL REG_VAL_VAL
+#define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
+#define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
+#define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL1_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
+#define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
+
+#define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__disable 0
+#define R_SERIAL1_TR_CTRL__tr_enable__tr_enable__enable 1
+#define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__active 1
+#define R_SERIAL1_TR_CTRL__auto_cts__auto_cts__disabled 0
+#define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__one_bit 0
+#define R_SERIAL1_TR_CTRL__stop_bits__stop_bits__two_bits 1
+#define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__normal 0
+#define R_SERIAL1_TR_CTRL__tr_stick_par__tr_stick_par__stick 1
+#define R_SERIAL1_TR_CTRL__tr_par__tr_par__even 0
+#define R_SERIAL1_TR_CTRL__tr_par__tr_par__odd 1
+#define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__disable 0
+#define R_SERIAL1_TR_CTRL__tr_par_en__tr_par_en__enable 1
+#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
+#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL1_TR_DATA
+ * - type: WO
+ * - addr: 0xb0000068
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000068)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 0))
+#define R_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL1_TR_DATA__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL1_TR_DATA__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_TR_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL1_TR_DATA__TYPE (REG_BYTE)
+#define R_SERIAL1_TR_DATA__GET REG_GET_WO
+#define R_SERIAL1_TR_DATA__IGET REG_IGET_WO
+#define R_SERIAL1_TR_DATA__SET REG_SET_WO
+#define R_SERIAL1_TR_DATA__ISET REG_ISET_WO
+#define R_SERIAL1_TR_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL1_TR_DATA__EQL REG_EQL_WO
+#define R_SERIAL1_TR_DATA__IEQL REG_IEQL_WO
+#define R_SERIAL1_TR_DATA__RD REG_RD_WO
+#define R_SERIAL1_TR_DATA__IRD REG_IRD_WO
+#define R_SERIAL1_TR_DATA__WR REG_WR_WO
+#define R_SERIAL1_TR_DATA__IWR REG_IWR_WO
+
+#define R_SERIAL1_TR_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL1_TR_DATA__data_out__data_out__MASK 0x000000ffU
+
+#define R_SERIAL1_TR_DATA__data_out__MAX 0xff
+
+#define R_SERIAL1_TR_DATA__data_out__MIN 0
+
+#define R_SERIAL1_TR_DATA__data_out__BITNR 0
+
+#define R_SERIAL1_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SERIAL1_XOFF
+ * - type: WO
+ * - addr: 0xb000006c
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL1_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb000006c)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL1_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0))
+#define R_SERIAL1_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL1_XOFF__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SERIAL1_XOFF__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL1_XOFF__STYPECAST REG_STYPECAST_UDWORD
+#define R_SERIAL1_XOFF__SVAL REG_SVAL_SHADOW
+#define R_SERIAL1_XOFF__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL1_XOFF__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL1_XOFF__TYPE (REG_UDWORD)
+#define R_SERIAL1_XOFF__GET REG_GET_WO
+#define R_SERIAL1_XOFF__IGET REG_IGET_WO
+#define R_SERIAL1_XOFF__SET REG_SET_WO
+#define R_SERIAL1_XOFF__ISET REG_ISET_WO
+#define R_SERIAL1_XOFF__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL1_XOFF__EQL REG_EQL_WO
+#define R_SERIAL1_XOFF__IEQL REG_IEQL_WO
+#define R_SERIAL1_XOFF__RD REG_RD_WO
+#define R_SERIAL1_XOFF__IRD REG_IRD_WO
+#define R_SERIAL1_XOFF__WR REG_WR_WO
+#define R_SERIAL1_XOFF__IWR REG_IWR_WO
+
+#define R_SERIAL1_XOFF__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL1_XOFF__tx_stop__tx_stop__MASK 0x00000200U
+#define R_SERIAL1_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U
+#define R_SERIAL1_XOFF__xoff_char__xoff_char__MASK 0x000000ffU
+
+#define R_SERIAL1_XOFF__tx_stop__MAX 0x1
+#define R_SERIAL1_XOFF__auto_xoff__MAX 0x1
+#define R_SERIAL1_XOFF__xoff_char__MAX 0xff
+
+#define R_SERIAL1_XOFF__tx_stop__MIN 0
+#define R_SERIAL1_XOFF__auto_xoff__MIN 0
+#define R_SERIAL1_XOFF__xoff_char__MIN 0
+
+#define R_SERIAL1_XOFF__tx_stop__BITNR 9
+#define R_SERIAL1_XOFF__auto_xoff__BITNR 8
+#define R_SERIAL1_XOFF__xoff_char__BITNR 0
+
+#define R_SERIAL1_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM
+#define R_SERIAL1_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM
+#define R_SERIAL1_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL
+
+#define R_SERIAL1_XOFF__tx_stop__tx_stop__enable 0
+#define R_SERIAL1_XOFF__tx_stop__tx_stop__stop 1
+#define R_SERIAL1_XOFF__auto_xoff__auto_xoff__disable 0
+#define R_SERIAL1_XOFF__auto_xoff__auto_xoff__enable 1
+
+#endif
+
+/*
+ * R_SERIAL2_BAUD
+ * - type: WO
+ * - addr: 0xb0000073
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_BAUD__ADDR (REG_TYPECAST_BYTE 0xb0000073)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL2_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 3))
+#define R_SERIAL2_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 3))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL2_BAUD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL2_BAUD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL2_BAUD__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL2_BAUD__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_BAUD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_BAUD__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL2_BAUD__TYPE (REG_BYTE)
+#define R_SERIAL2_BAUD__GET REG_GET_WO
+#define R_SERIAL2_BAUD__IGET REG_IGET_WO
+#define R_SERIAL2_BAUD__SET REG_SET_WO
+#define R_SERIAL2_BAUD__ISET REG_ISET_WO
+#define R_SERIAL2_BAUD__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL2_BAUD__EQL REG_EQL_WO
+#define R_SERIAL2_BAUD__IEQL REG_IEQL_WO
+#define R_SERIAL2_BAUD__RD REG_RD_WO
+#define R_SERIAL2_BAUD__IRD REG_IRD_WO
+#define R_SERIAL2_BAUD__WR REG_WR_WO
+#define R_SERIAL2_BAUD__IWR REG_IWR_WO
+
+#define R_SERIAL2_BAUD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__MASK 0x000000f0U
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__MASK 0x0000000fU
+
+#define R_SERIAL2_BAUD__tr_baud__MAX 0xf
+#define R_SERIAL2_BAUD__rec_baud__MAX 0xf
+
+#define R_SERIAL2_BAUD__tr_baud__MIN 0
+#define R_SERIAL2_BAUD__rec_baud__MIN 0
+
+#define R_SERIAL2_BAUD__tr_baud__BITNR 4
+#define R_SERIAL2_BAUD__rec_baud__BITNR 0
+
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM
+
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c115k2Hz 9
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c1200Hz 2
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c1843k2Hz 13
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c19k2Hz 6
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c230k4Hz 10
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c2400Hz 3
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c300Hz 0
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c38k4Hz 7
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c460k8Hz 11
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c4800Hz 4
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c57k6Hz 8
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c600Hz 1
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c6250kHz 14
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c921k6Hz 12
+#define R_SERIAL2_BAUD__tr_baud__tr_baud__c9600Hz 5
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c115k2Hz 9
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c1200Hz 2
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c1843k2Hz 13
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c19k2Hz 6
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c230k4Hz 10
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c2400Hz 3
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c300Hz 0
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c38k4Hz 7
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c460k8Hz 11
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c4800Hz 4
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c57k6Hz 8
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c600Hz 1
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c6250kHz 14
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c921k6Hz 12
+#define R_SERIAL2_BAUD__rec_baud__rec_baud__c9600Hz 5
+
+#endif
+
+/*
+ * R_SERIAL2_CTRL
+ * - type: WO
+ * - addr: 0xb0000070
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000070)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL2_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL2_CTRL + 0))
+#define R_SERIAL2_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL2_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL2_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SERIAL2_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL2_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_SERIAL2_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL2_CTRL__TYPE (REG_UDWORD)
+#define R_SERIAL2_CTRL__GET REG_GET_WO
+#define R_SERIAL2_CTRL__IGET REG_IGET_WO
+#define R_SERIAL2_CTRL__SET REG_SET_WO
+#define R_SERIAL2_CTRL__ISET REG_ISET_WO
+#define R_SERIAL2_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL2_CTRL__EQL REG_EQL_WO
+#define R_SERIAL2_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL2_CTRL__RD REG_RD_WO
+#define R_SERIAL2_CTRL__IRD REG_IRD_WO
+#define R_SERIAL2_CTRL__WR REG_WR_WO
+#define R_SERIAL2_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL2_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__MASK 0x0f000000U
+#define R_SERIAL2_CTRL__dma_err__dma_err__MASK 0x00800000U
+#define R_SERIAL2_CTRL__rec_enable__rec_enable__MASK 0x00400000U
+#define R_SERIAL2_CTRL__rts___rts___MASK 0x00200000U
+#define R_SERIAL2_CTRL__sampling__sampling__MASK 0x00100000U
+#define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U
+#define R_SERIAL2_CTRL__rec_par__rec_par__MASK 0x00040000U
+#define R_SERIAL2_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U
+#define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U
+#define R_SERIAL2_CTRL__txd__txd__MASK 0x00008000U
+#define R_SERIAL2_CTRL__tr_enable__tr_enable__MASK 0x00004000U
+#define R_SERIAL2_CTRL__auto_cts__auto_cts__MASK 0x00002000U
+#define R_SERIAL2_CTRL__stop_bits__stop_bits__MASK 0x00001000U
+#define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U
+#define R_SERIAL2_CTRL__tr_par__tr_par__MASK 0x00000400U
+#define R_SERIAL2_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U
+#define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U
+#define R_SERIAL2_CTRL__data_out__data_out__MASK 0x000000ffU
+
+#define R_SERIAL2_CTRL__tr_baud__MAX 0xf
+#define R_SERIAL2_CTRL__rec_baud__MAX 0xf
+#define R_SERIAL2_CTRL__dma_err__MAX 0x1
+#define R_SERIAL2_CTRL__rec_enable__MAX 0x1
+#define R_SERIAL2_CTRL__rts___MAX 0x1
+#define R_SERIAL2_CTRL__sampling__MAX 0x1
+#define R_SERIAL2_CTRL__rec_stick_par__MAX 0x1
+#define R_SERIAL2_CTRL__rec_par__MAX 0x1
+#define R_SERIAL2_CTRL__rec_par_en__MAX 0x1
+#define R_SERIAL2_CTRL__rec_bitnr__MAX 0x1
+#define R_SERIAL2_CTRL__txd__MAX 0x1
+#define R_SERIAL2_CTRL__tr_enable__MAX 0x1
+#define R_SERIAL2_CTRL__auto_cts__MAX 0x1
+#define R_SERIAL2_CTRL__stop_bits__MAX 0x1
+#define R_SERIAL2_CTRL__tr_stick_par__MAX 0x1
+#define R_SERIAL2_CTRL__tr_par__MAX 0x1
+#define R_SERIAL2_CTRL__tr_par_en__MAX 0x1
+#define R_SERIAL2_CTRL__tr_bitnr__MAX 0x1
+#define R_SERIAL2_CTRL__data_out__MAX 0xff
+
+#define R_SERIAL2_CTRL__tr_baud__MIN 0
+#define R_SERIAL2_CTRL__rec_baud__MIN 0
+#define R_SERIAL2_CTRL__dma_err__MIN 0
+#define R_SERIAL2_CTRL__rec_enable__MIN 0
+#define R_SERIAL2_CTRL__rts___MIN 0
+#define R_SERIAL2_CTRL__sampling__MIN 0
+#define R_SERIAL2_CTRL__rec_stick_par__MIN 0
+#define R_SERIAL2_CTRL__rec_par__MIN 0
+#define R_SERIAL2_CTRL__rec_par_en__MIN 0
+#define R_SERIAL2_CTRL__rec_bitnr__MIN 0
+#define R_SERIAL2_CTRL__txd__MIN 0
+#define R_SERIAL2_CTRL__tr_enable__MIN 0
+#define R_SERIAL2_CTRL__auto_cts__MIN 0
+#define R_SERIAL2_CTRL__stop_bits__MIN 0
+#define R_SERIAL2_CTRL__tr_stick_par__MIN 0
+#define R_SERIAL2_CTRL__tr_par__MIN 0
+#define R_SERIAL2_CTRL__tr_par_en__MIN 0
+#define R_SERIAL2_CTRL__tr_bitnr__MIN 0
+#define R_SERIAL2_CTRL__data_out__MIN 0
+
+#define R_SERIAL2_CTRL__tr_baud__BITNR 28
+#define R_SERIAL2_CTRL__rec_baud__BITNR 24
+#define R_SERIAL2_CTRL__dma_err__BITNR 23
+#define R_SERIAL2_CTRL__rec_enable__BITNR 22
+#define R_SERIAL2_CTRL__rts___BITNR 21
+#define R_SERIAL2_CTRL__sampling__BITNR 20
+#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19
+#define R_SERIAL2_CTRL__rec_par__BITNR 18
+#define R_SERIAL2_CTRL__rec_par_en__BITNR 17
+#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16
+#define R_SERIAL2_CTRL__txd__BITNR 15
+#define R_SERIAL2_CTRL__tr_enable__BITNR 14
+#define R_SERIAL2_CTRL__auto_cts__BITNR 13
+#define R_SERIAL2_CTRL__stop_bits__BITNR 12
+#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11
+#define R_SERIAL2_CTRL__tr_par__BITNR 10
+#define R_SERIAL2_CTRL__tr_par_en__BITNR 9
+#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8
+#define R_SERIAL2_CTRL__data_out__BITNR 0
+
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__rts___rts___VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__sampling__sampling__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__txd__txd__VAL REG_VAL_VAL
+#define R_SERIAL2_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
+#define R_SERIAL2_CTRL__data_out__data_out__VAL REG_VAL_VAL
+
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c115k2Hz 9
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c1200Hz 2
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c1843k2Hz 13
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c19k2Hz 6
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c230k4Hz 10
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c2400Hz 3
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c300Hz 0
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c38k4Hz 7
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c460k8Hz 11
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c4800Hz 4
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c57k6Hz 8
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c600Hz 1
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c6250kHz 14
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c921k6Hz 12
+#define R_SERIAL2_CTRL__tr_baud__tr_baud__c9600Hz 5
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c115k2Hz 9
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c1200Hz 2
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c1843k2Hz 13
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c19k2Hz 6
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c230k4Hz 10
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c2400Hz 3
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c300Hz 0
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c38k4Hz 7
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c460k8Hz 11
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c4800Hz 4
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c57k6Hz 8
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c600Hz 1
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c6250kHz 14
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c921k6Hz 12
+#define R_SERIAL2_CTRL__rec_baud__rec_baud__c9600Hz 5
+#define R_SERIAL2_CTRL__dma_err__dma_err__ignore 1
+#define R_SERIAL2_CTRL__dma_err__dma_err__stop 0
+#define R_SERIAL2_CTRL__rec_enable__rec_enable__disable 0
+#define R_SERIAL2_CTRL__rec_enable__rec_enable__enable 1
+#define R_SERIAL2_CTRL__rts___rts___active 0
+#define R_SERIAL2_CTRL__rts___rts___inactive 1
+#define R_SERIAL2_CTRL__sampling__sampling__majority 1
+#define R_SERIAL2_CTRL__sampling__sampling__middle 0
+#define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__normal 0
+#define R_SERIAL2_CTRL__rec_stick_par__rec_stick_par__stick 1
+#define R_SERIAL2_CTRL__rec_par__rec_par__even 0
+#define R_SERIAL2_CTRL__rec_par__rec_par__odd 1
+#define R_SERIAL2_CTRL__rec_par_en__rec_par_en__disable 0
+#define R_SERIAL2_CTRL__rec_par_en__rec_par_en__enable 1
+#define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
+#define R_SERIAL2_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
+#define R_SERIAL2_CTRL__tr_enable__tr_enable__disable 0
+#define R_SERIAL2_CTRL__tr_enable__tr_enable__enable 1
+#define R_SERIAL2_CTRL__auto_cts__auto_cts__active 1
+#define R_SERIAL2_CTRL__auto_cts__auto_cts__disabled 0
+#define R_SERIAL2_CTRL__stop_bits__stop_bits__one_bit 0
+#define R_SERIAL2_CTRL__stop_bits__stop_bits__two_bits 1
+#define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__normal 0
+#define R_SERIAL2_CTRL__tr_stick_par__tr_stick_par__stick 1
+#define R_SERIAL2_CTRL__tr_par__tr_par__even 0
+#define R_SERIAL2_CTRL__tr_par__tr_par__odd 1
+#define R_SERIAL2_CTRL__tr_par_en__tr_par_en__disable 0
+#define R_SERIAL2_CTRL__tr_par_en__tr_par_en__enable 1
+#define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
+#define R_SERIAL2_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL2_READ
+ * - type: RO
+ * - addr: 0xb0000070
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000070)
+#define R_SERIAL2_READ__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_READ__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL2_READ__TYPE (REG_UDWORD)
+#define R_SERIAL2_READ__GET REG_GET_RO
+#define R_SERIAL2_READ__IGET REG_IGET_RO
+#define R_SERIAL2_READ__SET REG_SET_RO
+#define R_SERIAL2_READ__ISET REG_ISET_RO
+#define R_SERIAL2_READ__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL2_READ__EQL REG_EQL_RO
+#define R_SERIAL2_READ__IEQL REG_IEQL_RO
+#define R_SERIAL2_READ__RD REG_RD_RO
+#define R_SERIAL2_READ__IRD REG_IRD_RO
+#define R_SERIAL2_READ__WR REG_WR_RO
+#define R_SERIAL2_READ__IWR REG_IWR_RO
+
+#define R_SERIAL2_READ__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL2_READ__xoff_detect__xoff_detect__MASK 0x00008000U
+#define R_SERIAL2_READ__cts___cts___MASK 0x00004000U
+#define R_SERIAL2_READ__tr_ready__tr_ready__MASK 0x00002000U
+#define R_SERIAL2_READ__rxd__rxd__MASK 0x00001000U
+#define R_SERIAL2_READ__overrun__overrun__MASK 0x00000800U
+#define R_SERIAL2_READ__par_err__par_err__MASK 0x00000400U
+#define R_SERIAL2_READ__framing_err__framing_err__MASK 0x00000200U
+#define R_SERIAL2_READ__data_avail__data_avail__MASK 0x00000100U
+#define R_SERIAL2_READ__data_in__data_in__MASK 0x000000ffU
+
+#define R_SERIAL2_READ__xoff_detect__MAX 0x1
+#define R_SERIAL2_READ__cts___MAX 0x1
+#define R_SERIAL2_READ__tr_ready__MAX 0x1
+#define R_SERIAL2_READ__rxd__MAX 0x1
+#define R_SERIAL2_READ__overrun__MAX 0x1
+#define R_SERIAL2_READ__par_err__MAX 0x1
+#define R_SERIAL2_READ__framing_err__MAX 0x1
+#define R_SERIAL2_READ__data_avail__MAX 0x1
+#define R_SERIAL2_READ__data_in__MAX 0xff
+
+#define R_SERIAL2_READ__xoff_detect__MIN 0
+#define R_SERIAL2_READ__cts___MIN 0
+#define R_SERIAL2_READ__tr_ready__MIN 0
+#define R_SERIAL2_READ__rxd__MIN 0
+#define R_SERIAL2_READ__overrun__MIN 0
+#define R_SERIAL2_READ__par_err__MIN 0
+#define R_SERIAL2_READ__framing_err__MIN 0
+#define R_SERIAL2_READ__data_avail__MIN 0
+#define R_SERIAL2_READ__data_in__MIN 0
+
+#define R_SERIAL2_READ__xoff_detect__BITNR 15
+#define R_SERIAL2_READ__cts___BITNR 14
+#define R_SERIAL2_READ__tr_ready__BITNR 13
+#define R_SERIAL2_READ__rxd__BITNR 12
+#define R_SERIAL2_READ__overrun__BITNR 11
+#define R_SERIAL2_READ__par_err__BITNR 10
+#define R_SERIAL2_READ__framing_err__BITNR 9
+#define R_SERIAL2_READ__data_avail__BITNR 8
+#define R_SERIAL2_READ__data_in__BITNR 0
+
+#define R_SERIAL2_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
+#define R_SERIAL2_READ__cts___cts___VAL REG_VAL_ENUM
+#define R_SERIAL2_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SERIAL2_READ__rxd__rxd__VAL REG_VAL_VAL
+#define R_SERIAL2_READ__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SERIAL2_READ__par_err__par_err__VAL REG_VAL_ENUM
+#define R_SERIAL2_READ__framing_err__framing_err__VAL REG_VAL_ENUM
+#define R_SERIAL2_READ__data_avail__data_avail__VAL REG_VAL_ENUM
+#define R_SERIAL2_READ__data_in__data_in__VAL REG_VAL_VAL
+
+#define R_SERIAL2_READ__xoff_detect__xoff_detect__no_xoff 0
+#define R_SERIAL2_READ__xoff_detect__xoff_detect__xoff 1
+#define R_SERIAL2_READ__cts___cts___active 0
+#define R_SERIAL2_READ__cts___cts___inactive 1
+#define R_SERIAL2_READ__tr_ready__tr_ready__full 0
+#define R_SERIAL2_READ__tr_ready__tr_ready__ready 1
+#define R_SERIAL2_READ__overrun__overrun__no 0
+#define R_SERIAL2_READ__overrun__overrun__yes 1
+#define R_SERIAL2_READ__par_err__par_err__no 0
+#define R_SERIAL2_READ__par_err__par_err__yes 1
+#define R_SERIAL2_READ__framing_err__framing_err__no 0
+#define R_SERIAL2_READ__framing_err__framing_err__yes 1
+#define R_SERIAL2_READ__data_avail__data_avail__no 0
+#define R_SERIAL2_READ__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SERIAL2_REC_CTRL
+ * - type: WO
+ * - addr: 0xb0000072
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000072)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL2_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 2))
+#define R_SERIAL2_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 2))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL2_REC_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL2_REC_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL2_REC_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL2_REC_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_REC_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL2_REC_CTRL__TYPE (REG_BYTE)
+#define R_SERIAL2_REC_CTRL__GET REG_GET_WO
+#define R_SERIAL2_REC_CTRL__IGET REG_IGET_WO
+#define R_SERIAL2_REC_CTRL__SET REG_SET_WO
+#define R_SERIAL2_REC_CTRL__ISET REG_ISET_WO
+#define R_SERIAL2_REC_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL2_REC_CTRL__EQL REG_EQL_WO
+#define R_SERIAL2_REC_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL2_REC_CTRL__RD REG_RD_WO
+#define R_SERIAL2_REC_CTRL__IRD REG_IRD_WO
+#define R_SERIAL2_REC_CTRL__WR REG_WR_WO
+#define R_SERIAL2_REC_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL2_REC_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL2_REC_CTRL__dma_err__dma_err__MASK 0x00000080U
+#define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U
+#define R_SERIAL2_REC_CTRL__rts___rts___MASK 0x00000020U
+#define R_SERIAL2_REC_CTRL__sampling__sampling__MASK 0x00000010U
+#define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U
+#define R_SERIAL2_REC_CTRL__rec_par__rec_par__MASK 0x00000004U
+#define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U
+#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U
+
+#define R_SERIAL2_REC_CTRL__dma_err__MAX 0x1
+#define R_SERIAL2_REC_CTRL__rec_enable__MAX 0x1
+#define R_SERIAL2_REC_CTRL__rts___MAX 0x1
+#define R_SERIAL2_REC_CTRL__sampling__MAX 0x1
+#define R_SERIAL2_REC_CTRL__rec_stick_par__MAX 0x1
+#define R_SERIAL2_REC_CTRL__rec_par__MAX 0x1
+#define R_SERIAL2_REC_CTRL__rec_par_en__MAX 0x1
+#define R_SERIAL2_REC_CTRL__rec_bitnr__MAX 0x1
+
+#define R_SERIAL2_REC_CTRL__dma_err__MIN 0
+#define R_SERIAL2_REC_CTRL__rec_enable__MIN 0
+#define R_SERIAL2_REC_CTRL__rts___MIN 0
+#define R_SERIAL2_REC_CTRL__sampling__MIN 0
+#define R_SERIAL2_REC_CTRL__rec_stick_par__MIN 0
+#define R_SERIAL2_REC_CTRL__rec_par__MIN 0
+#define R_SERIAL2_REC_CTRL__rec_par_en__MIN 0
+#define R_SERIAL2_REC_CTRL__rec_bitnr__MIN 0
+
+#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7
+#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6
+#define R_SERIAL2_REC_CTRL__rts___BITNR 5
+#define R_SERIAL2_REC_CTRL__sampling__BITNR 4
+#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3
+#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2
+#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1
+#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0
+
+#define R_SERIAL2_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
+#define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SERIAL2_REC_CTRL__rts___rts___VAL REG_VAL_ENUM
+#define R_SERIAL2_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM
+#define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL2_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
+#define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
+
+#define R_SERIAL2_REC_CTRL__dma_err__dma_err__ignore 1
+#define R_SERIAL2_REC_CTRL__dma_err__dma_err__stop 0
+#define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__disable 0
+#define R_SERIAL2_REC_CTRL__rec_enable__rec_enable__enable 1
+#define R_SERIAL2_REC_CTRL__rts___rts___active 0
+#define R_SERIAL2_REC_CTRL__rts___rts___inactive 1
+#define R_SERIAL2_REC_CTRL__sampling__sampling__majority 1
+#define R_SERIAL2_REC_CTRL__sampling__sampling__middle 0
+#define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__normal 0
+#define R_SERIAL2_REC_CTRL__rec_stick_par__rec_stick_par__stick 1
+#define R_SERIAL2_REC_CTRL__rec_par__rec_par__even 0
+#define R_SERIAL2_REC_CTRL__rec_par__rec_par__odd 1
+#define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__disable 0
+#define R_SERIAL2_REC_CTRL__rec_par_en__rec_par_en__enable 1
+#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
+#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL2_REC_DATA
+ * - type: RO
+ * - addr: 0xb0000070
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000070)
+#define R_SERIAL2_REC_DATA__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_REC_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL2_REC_DATA__TYPE (REG_BYTE)
+#define R_SERIAL2_REC_DATA__GET REG_GET_RO
+#define R_SERIAL2_REC_DATA__IGET REG_IGET_RO
+#define R_SERIAL2_REC_DATA__SET REG_SET_RO
+#define R_SERIAL2_REC_DATA__ISET REG_ISET_RO
+#define R_SERIAL2_REC_DATA__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL2_REC_DATA__EQL REG_EQL_RO
+#define R_SERIAL2_REC_DATA__IEQL REG_IEQL_RO
+#define R_SERIAL2_REC_DATA__RD REG_RD_RO
+#define R_SERIAL2_REC_DATA__IRD REG_IRD_RO
+#define R_SERIAL2_REC_DATA__WR REG_WR_RO
+#define R_SERIAL2_REC_DATA__IWR REG_IWR_RO
+
+#define R_SERIAL2_REC_DATA__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL2_REC_DATA__data_in__data_in__MASK 0x000000ffU
+
+#define R_SERIAL2_REC_DATA__data_in__MAX 0xff
+
+#define R_SERIAL2_REC_DATA__data_in__MIN 0
+
+#define R_SERIAL2_REC_DATA__data_in__BITNR 0
+
+#define R_SERIAL2_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SERIAL2_STATUS
+ * - type: RO
+ * - addr: 0xb0000071
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000071)
+#define R_SERIAL2_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL2_STATUS__TYPE (REG_BYTE)
+#define R_SERIAL2_STATUS__GET REG_GET_RO
+#define R_SERIAL2_STATUS__IGET REG_IGET_RO
+#define R_SERIAL2_STATUS__SET REG_SET_RO
+#define R_SERIAL2_STATUS__ISET REG_ISET_RO
+#define R_SERIAL2_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL2_STATUS__EQL REG_EQL_RO
+#define R_SERIAL2_STATUS__IEQL REG_IEQL_RO
+#define R_SERIAL2_STATUS__RD REG_RD_RO
+#define R_SERIAL2_STATUS__IRD REG_IRD_RO
+#define R_SERIAL2_STATUS__WR REG_WR_RO
+#define R_SERIAL2_STATUS__IWR REG_IWR_RO
+
+#define R_SERIAL2_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL2_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U
+#define R_SERIAL2_STATUS__cts___cts___MASK 0x00000040U
+#define R_SERIAL2_STATUS__tr_ready__tr_ready__MASK 0x00000020U
+#define R_SERIAL2_STATUS__rxd__rxd__MASK 0x00000010U
+#define R_SERIAL2_STATUS__overrun__overrun__MASK 0x00000008U
+#define R_SERIAL2_STATUS__par_err__par_err__MASK 0x00000004U
+#define R_SERIAL2_STATUS__framing_err__framing_err__MASK 0x00000002U
+#define R_SERIAL2_STATUS__data_avail__data_avail__MASK 0x00000001U
+
+#define R_SERIAL2_STATUS__xoff_detect__MAX 0x1
+#define R_SERIAL2_STATUS__cts___MAX 0x1
+#define R_SERIAL2_STATUS__tr_ready__MAX 0x1
+#define R_SERIAL2_STATUS__rxd__MAX 0x1
+#define R_SERIAL2_STATUS__overrun__MAX 0x1
+#define R_SERIAL2_STATUS__par_err__MAX 0x1
+#define R_SERIAL2_STATUS__framing_err__MAX 0x1
+#define R_SERIAL2_STATUS__data_avail__MAX 0x1
+
+#define R_SERIAL2_STATUS__xoff_detect__MIN 0
+#define R_SERIAL2_STATUS__cts___MIN 0
+#define R_SERIAL2_STATUS__tr_ready__MIN 0
+#define R_SERIAL2_STATUS__rxd__MIN 0
+#define R_SERIAL2_STATUS__overrun__MIN 0
+#define R_SERIAL2_STATUS__par_err__MIN 0
+#define R_SERIAL2_STATUS__framing_err__MIN 0
+#define R_SERIAL2_STATUS__data_avail__MIN 0
+
+#define R_SERIAL2_STATUS__xoff_detect__BITNR 7
+#define R_SERIAL2_STATUS__cts___BITNR 6
+#define R_SERIAL2_STATUS__tr_ready__BITNR 5
+#define R_SERIAL2_STATUS__rxd__BITNR 4
+#define R_SERIAL2_STATUS__overrun__BITNR 3
+#define R_SERIAL2_STATUS__par_err__BITNR 2
+#define R_SERIAL2_STATUS__framing_err__BITNR 1
+#define R_SERIAL2_STATUS__data_avail__BITNR 0
+
+#define R_SERIAL2_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
+#define R_SERIAL2_STATUS__cts___cts___VAL REG_VAL_ENUM
+#define R_SERIAL2_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SERIAL2_STATUS__rxd__rxd__VAL REG_VAL_VAL
+#define R_SERIAL2_STATUS__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SERIAL2_STATUS__par_err__par_err__VAL REG_VAL_ENUM
+#define R_SERIAL2_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM
+#define R_SERIAL2_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
+
+#define R_SERIAL2_STATUS__xoff_detect__xoff_detect__no_xoff 0
+#define R_SERIAL2_STATUS__xoff_detect__xoff_detect__xoff 1
+#define R_SERIAL2_STATUS__cts___cts___active 0
+#define R_SERIAL2_STATUS__cts___cts___inactive 1
+#define R_SERIAL2_STATUS__tr_ready__tr_ready__full 0
+#define R_SERIAL2_STATUS__tr_ready__tr_ready__ready 1
+#define R_SERIAL2_STATUS__overrun__overrun__no 0
+#define R_SERIAL2_STATUS__overrun__overrun__yes 1
+#define R_SERIAL2_STATUS__par_err__par_err__no 0
+#define R_SERIAL2_STATUS__par_err__par_err__yes 1
+#define R_SERIAL2_STATUS__framing_err__framing_err__no 0
+#define R_SERIAL2_STATUS__framing_err__framing_err__yes 1
+#define R_SERIAL2_STATUS__data_avail__data_avail__no 0
+#define R_SERIAL2_STATUS__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SERIAL2_TR_CTRL
+ * - type: WO
+ * - addr: 0xb0000071
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000071)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL2_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 1))
+#define R_SERIAL2_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 1))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL2_TR_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL2_TR_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL2_TR_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL2_TR_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_TR_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL2_TR_CTRL__TYPE (REG_BYTE)
+#define R_SERIAL2_TR_CTRL__GET REG_GET_WO
+#define R_SERIAL2_TR_CTRL__IGET REG_IGET_WO
+#define R_SERIAL2_TR_CTRL__SET REG_SET_WO
+#define R_SERIAL2_TR_CTRL__ISET REG_ISET_WO
+#define R_SERIAL2_TR_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL2_TR_CTRL__EQL REG_EQL_WO
+#define R_SERIAL2_TR_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL2_TR_CTRL__RD REG_RD_WO
+#define R_SERIAL2_TR_CTRL__IRD REG_IRD_WO
+#define R_SERIAL2_TR_CTRL__WR REG_WR_WO
+#define R_SERIAL2_TR_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL2_TR_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL2_TR_CTRL__txd__txd__MASK 0x00000080U
+#define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U
+#define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U
+#define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U
+#define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U
+#define R_SERIAL2_TR_CTRL__tr_par__tr_par__MASK 0x00000004U
+#define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U
+#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U
+
+#define R_SERIAL2_TR_CTRL__txd__MAX 0x1
+#define R_SERIAL2_TR_CTRL__tr_enable__MAX 0x1
+#define R_SERIAL2_TR_CTRL__auto_cts__MAX 0x1
+#define R_SERIAL2_TR_CTRL__stop_bits__MAX 0x1
+#define R_SERIAL2_TR_CTRL__tr_stick_par__MAX 0x1
+#define R_SERIAL2_TR_CTRL__tr_par__MAX 0x1
+#define R_SERIAL2_TR_CTRL__tr_par_en__MAX 0x1
+#define R_SERIAL2_TR_CTRL__tr_bitnr__MAX 0x1
+
+#define R_SERIAL2_TR_CTRL__txd__MIN 0
+#define R_SERIAL2_TR_CTRL__tr_enable__MIN 0
+#define R_SERIAL2_TR_CTRL__auto_cts__MIN 0
+#define R_SERIAL2_TR_CTRL__stop_bits__MIN 0
+#define R_SERIAL2_TR_CTRL__tr_stick_par__MIN 0
+#define R_SERIAL2_TR_CTRL__tr_par__MIN 0
+#define R_SERIAL2_TR_CTRL__tr_par_en__MIN 0
+#define R_SERIAL2_TR_CTRL__tr_bitnr__MIN 0
+
+#define R_SERIAL2_TR_CTRL__txd__BITNR 7
+#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6
+#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5
+#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4
+#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3
+#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2
+#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1
+#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0
+
+#define R_SERIAL2_TR_CTRL__txd__txd__VAL REG_VAL_VAL
+#define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
+#define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
+#define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL2_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
+#define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
+
+#define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__disable 0
+#define R_SERIAL2_TR_CTRL__tr_enable__tr_enable__enable 1
+#define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__active 1
+#define R_SERIAL2_TR_CTRL__auto_cts__auto_cts__disabled 0
+#define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__one_bit 0
+#define R_SERIAL2_TR_CTRL__stop_bits__stop_bits__two_bits 1
+#define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__normal 0
+#define R_SERIAL2_TR_CTRL__tr_stick_par__tr_stick_par__stick 1
+#define R_SERIAL2_TR_CTRL__tr_par__tr_par__even 0
+#define R_SERIAL2_TR_CTRL__tr_par__tr_par__odd 1
+#define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__disable 0
+#define R_SERIAL2_TR_CTRL__tr_par_en__tr_par_en__enable 1
+#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
+#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL2_TR_DATA
+ * - type: WO
+ * - addr: 0xb0000070
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000070)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL2_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL2_CTRL + 0))
+#define R_SERIAL2_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL2_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL2_TR_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL2_TR_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL2_TR_DATA__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL2_TR_DATA__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_TR_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL2_TR_DATA__TYPE (REG_BYTE)
+#define R_SERIAL2_TR_DATA__GET REG_GET_WO
+#define R_SERIAL2_TR_DATA__IGET REG_IGET_WO
+#define R_SERIAL2_TR_DATA__SET REG_SET_WO
+#define R_SERIAL2_TR_DATA__ISET REG_ISET_WO
+#define R_SERIAL2_TR_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL2_TR_DATA__EQL REG_EQL_WO
+#define R_SERIAL2_TR_DATA__IEQL REG_IEQL_WO
+#define R_SERIAL2_TR_DATA__RD REG_RD_WO
+#define R_SERIAL2_TR_DATA__IRD REG_IRD_WO
+#define R_SERIAL2_TR_DATA__WR REG_WR_WO
+#define R_SERIAL2_TR_DATA__IWR REG_IWR_WO
+
+#define R_SERIAL2_TR_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL2_TR_DATA__data_out__data_out__MASK 0x000000ffU
+
+#define R_SERIAL2_TR_DATA__data_out__MAX 0xff
+
+#define R_SERIAL2_TR_DATA__data_out__MIN 0
+
+#define R_SERIAL2_TR_DATA__data_out__BITNR 0
+
+#define R_SERIAL2_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SERIAL2_XOFF
+ * - type: WO
+ * - addr: 0xb0000074
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL2_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb0000074)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL2_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL2_XOFF + 0))
+#define R_SERIAL2_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL2_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL2_XOFF__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SERIAL2_XOFF__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL2_XOFF__STYPECAST REG_STYPECAST_UDWORD
+#define R_SERIAL2_XOFF__SVAL REG_SVAL_SHADOW
+#define R_SERIAL2_XOFF__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL2_XOFF__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL2_XOFF__TYPE (REG_UDWORD)
+#define R_SERIAL2_XOFF__GET REG_GET_WO
+#define R_SERIAL2_XOFF__IGET REG_IGET_WO
+#define R_SERIAL2_XOFF__SET REG_SET_WO
+#define R_SERIAL2_XOFF__ISET REG_ISET_WO
+#define R_SERIAL2_XOFF__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL2_XOFF__EQL REG_EQL_WO
+#define R_SERIAL2_XOFF__IEQL REG_IEQL_WO
+#define R_SERIAL2_XOFF__RD REG_RD_WO
+#define R_SERIAL2_XOFF__IRD REG_IRD_WO
+#define R_SERIAL2_XOFF__WR REG_WR_WO
+#define R_SERIAL2_XOFF__IWR REG_IWR_WO
+
+#define R_SERIAL2_XOFF__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL2_XOFF__tx_stop__tx_stop__MASK 0x00000200U
+#define R_SERIAL2_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U
+#define R_SERIAL2_XOFF__xoff_char__xoff_char__MASK 0x000000ffU
+
+#define R_SERIAL2_XOFF__tx_stop__MAX 0x1
+#define R_SERIAL2_XOFF__auto_xoff__MAX 0x1
+#define R_SERIAL2_XOFF__xoff_char__MAX 0xff
+
+#define R_SERIAL2_XOFF__tx_stop__MIN 0
+#define R_SERIAL2_XOFF__auto_xoff__MIN 0
+#define R_SERIAL2_XOFF__xoff_char__MIN 0
+
+#define R_SERIAL2_XOFF__tx_stop__BITNR 9
+#define R_SERIAL2_XOFF__auto_xoff__BITNR 8
+#define R_SERIAL2_XOFF__xoff_char__BITNR 0
+
+#define R_SERIAL2_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM
+#define R_SERIAL2_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM
+#define R_SERIAL2_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL
+
+#define R_SERIAL2_XOFF__tx_stop__tx_stop__enable 0
+#define R_SERIAL2_XOFF__tx_stop__tx_stop__stop 1
+#define R_SERIAL2_XOFF__auto_xoff__auto_xoff__disable 0
+#define R_SERIAL2_XOFF__auto_xoff__auto_xoff__enable 1
+
+#endif
+
+/*
+ * R_SERIAL3_BAUD
+ * - type: WO
+ * - addr: 0xb000007b
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_BAUD__ADDR (REG_TYPECAST_BYTE 0xb000007b)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL3_BAUD__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 3))
+#define R_SERIAL3_BAUD__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 3))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL3_BAUD__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL3_BAUD__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL3_BAUD__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL3_BAUD__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_BAUD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_BAUD__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL3_BAUD__TYPE (REG_BYTE)
+#define R_SERIAL3_BAUD__GET REG_GET_WO
+#define R_SERIAL3_BAUD__IGET REG_IGET_WO
+#define R_SERIAL3_BAUD__SET REG_SET_WO
+#define R_SERIAL3_BAUD__ISET REG_ISET_WO
+#define R_SERIAL3_BAUD__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL3_BAUD__EQL REG_EQL_WO
+#define R_SERIAL3_BAUD__IEQL REG_IEQL_WO
+#define R_SERIAL3_BAUD__RD REG_RD_WO
+#define R_SERIAL3_BAUD__IRD REG_IRD_WO
+#define R_SERIAL3_BAUD__WR REG_WR_WO
+#define R_SERIAL3_BAUD__IWR REG_IWR_WO
+
+#define R_SERIAL3_BAUD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__MASK 0x000000f0U
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__MASK 0x0000000fU
+
+#define R_SERIAL3_BAUD__tr_baud__MAX 0xf
+#define R_SERIAL3_BAUD__rec_baud__MAX 0xf
+
+#define R_SERIAL3_BAUD__tr_baud__MIN 0
+#define R_SERIAL3_BAUD__rec_baud__MIN 0
+
+#define R_SERIAL3_BAUD__tr_baud__BITNR 4
+#define R_SERIAL3_BAUD__rec_baud__BITNR 0
+
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__VAL REG_VAL_ENUM
+
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c115k2Hz 9
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c1200Hz 2
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c1843k2Hz 13
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c19k2Hz 6
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c230k4Hz 10
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c2400Hz 3
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c300Hz 0
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c38k4Hz 7
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c460k8Hz 11
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c4800Hz 4
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c57k6Hz 8
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c600Hz 1
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c6250kHz 14
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c921k6Hz 12
+#define R_SERIAL3_BAUD__tr_baud__tr_baud__c9600Hz 5
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c115k2Hz 9
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c1200Hz 2
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c1843k2Hz 13
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c19k2Hz 6
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c230k4Hz 10
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c2400Hz 3
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c300Hz 0
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c38k4Hz 7
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c460k8Hz 11
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c4800Hz 4
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c57k6Hz 8
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c600Hz 1
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c6250kHz 14
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c921k6Hz 12
+#define R_SERIAL3_BAUD__rec_baud__rec_baud__c9600Hz 5
+
+#endif
+
+/*
+ * R_SERIAL3_CTRL
+ * - type: WO
+ * - addr: 0xb0000078
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000078)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_CTRL + 0))
+#define R_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL3_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_SERIAL3_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL3_CTRL__TYPE (REG_UDWORD)
+#define R_SERIAL3_CTRL__GET REG_GET_WO
+#define R_SERIAL3_CTRL__IGET REG_IGET_WO
+#define R_SERIAL3_CTRL__SET REG_SET_WO
+#define R_SERIAL3_CTRL__ISET REG_ISET_WO
+#define R_SERIAL3_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL3_CTRL__EQL REG_EQL_WO
+#define R_SERIAL3_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL3_CTRL__RD REG_RD_WO
+#define R_SERIAL3_CTRL__IRD REG_IRD_WO
+#define R_SERIAL3_CTRL__WR REG_WR_WO
+#define R_SERIAL3_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL3_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__MASK 0x0f000000U
+#define R_SERIAL3_CTRL__dma_err__dma_err__MASK 0x00800000U
+#define R_SERIAL3_CTRL__rec_enable__rec_enable__MASK 0x00400000U
+#define R_SERIAL3_CTRL__rts___rts___MASK 0x00200000U
+#define R_SERIAL3_CTRL__sampling__sampling__MASK 0x00100000U
+#define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__MASK 0x00080000U
+#define R_SERIAL3_CTRL__rec_par__rec_par__MASK 0x00040000U
+#define R_SERIAL3_CTRL__rec_par_en__rec_par_en__MASK 0x00020000U
+#define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__MASK 0x00010000U
+#define R_SERIAL3_CTRL__txd__txd__MASK 0x00008000U
+#define R_SERIAL3_CTRL__tr_enable__tr_enable__MASK 0x00004000U
+#define R_SERIAL3_CTRL__auto_cts__auto_cts__MASK 0x00002000U
+#define R_SERIAL3_CTRL__stop_bits__stop_bits__MASK 0x00001000U
+#define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000800U
+#define R_SERIAL3_CTRL__tr_par__tr_par__MASK 0x00000400U
+#define R_SERIAL3_CTRL__tr_par_en__tr_par_en__MASK 0x00000200U
+#define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000100U
+#define R_SERIAL3_CTRL__data_out__data_out__MASK 0x000000ffU
+
+#define R_SERIAL3_CTRL__tr_baud__MAX 0xf
+#define R_SERIAL3_CTRL__rec_baud__MAX 0xf
+#define R_SERIAL3_CTRL__dma_err__MAX 0x1
+#define R_SERIAL3_CTRL__rec_enable__MAX 0x1
+#define R_SERIAL3_CTRL__rts___MAX 0x1
+#define R_SERIAL3_CTRL__sampling__MAX 0x1
+#define R_SERIAL3_CTRL__rec_stick_par__MAX 0x1
+#define R_SERIAL3_CTRL__rec_par__MAX 0x1
+#define R_SERIAL3_CTRL__rec_par_en__MAX 0x1
+#define R_SERIAL3_CTRL__rec_bitnr__MAX 0x1
+#define R_SERIAL3_CTRL__txd__MAX 0x1
+#define R_SERIAL3_CTRL__tr_enable__MAX 0x1
+#define R_SERIAL3_CTRL__auto_cts__MAX 0x1
+#define R_SERIAL3_CTRL__stop_bits__MAX 0x1
+#define R_SERIAL3_CTRL__tr_stick_par__MAX 0x1
+#define R_SERIAL3_CTRL__tr_par__MAX 0x1
+#define R_SERIAL3_CTRL__tr_par_en__MAX 0x1
+#define R_SERIAL3_CTRL__tr_bitnr__MAX 0x1
+#define R_SERIAL3_CTRL__data_out__MAX 0xff
+
+#define R_SERIAL3_CTRL__tr_baud__MIN 0
+#define R_SERIAL3_CTRL__rec_baud__MIN 0
+#define R_SERIAL3_CTRL__dma_err__MIN 0
+#define R_SERIAL3_CTRL__rec_enable__MIN 0
+#define R_SERIAL3_CTRL__rts___MIN 0
+#define R_SERIAL3_CTRL__sampling__MIN 0
+#define R_SERIAL3_CTRL__rec_stick_par__MIN 0
+#define R_SERIAL3_CTRL__rec_par__MIN 0
+#define R_SERIAL3_CTRL__rec_par_en__MIN 0
+#define R_SERIAL3_CTRL__rec_bitnr__MIN 0
+#define R_SERIAL3_CTRL__txd__MIN 0
+#define R_SERIAL3_CTRL__tr_enable__MIN 0
+#define R_SERIAL3_CTRL__auto_cts__MIN 0
+#define R_SERIAL3_CTRL__stop_bits__MIN 0
+#define R_SERIAL3_CTRL__tr_stick_par__MIN 0
+#define R_SERIAL3_CTRL__tr_par__MIN 0
+#define R_SERIAL3_CTRL__tr_par_en__MIN 0
+#define R_SERIAL3_CTRL__tr_bitnr__MIN 0
+#define R_SERIAL3_CTRL__data_out__MIN 0
+
+#define R_SERIAL3_CTRL__tr_baud__BITNR 28
+#define R_SERIAL3_CTRL__rec_baud__BITNR 24
+#define R_SERIAL3_CTRL__dma_err__BITNR 23
+#define R_SERIAL3_CTRL__rec_enable__BITNR 22
+#define R_SERIAL3_CTRL__rts___BITNR 21
+#define R_SERIAL3_CTRL__sampling__BITNR 20
+#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19
+#define R_SERIAL3_CTRL__rec_par__BITNR 18
+#define R_SERIAL3_CTRL__rec_par_en__BITNR 17
+#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16
+#define R_SERIAL3_CTRL__txd__BITNR 15
+#define R_SERIAL3_CTRL__tr_enable__BITNR 14
+#define R_SERIAL3_CTRL__auto_cts__BITNR 13
+#define R_SERIAL3_CTRL__stop_bits__BITNR 12
+#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11
+#define R_SERIAL3_CTRL__tr_par__BITNR 10
+#define R_SERIAL3_CTRL__tr_par_en__BITNR 9
+#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8
+#define R_SERIAL3_CTRL__data_out__BITNR 0
+
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__rts___rts___VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__sampling__sampling__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__txd__txd__VAL REG_VAL_VAL
+#define R_SERIAL3_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
+#define R_SERIAL3_CTRL__data_out__data_out__VAL REG_VAL_VAL
+
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c115k2Hz 9
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c1200Hz 2
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c1843k2Hz 13
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c19k2Hz 6
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c230k4Hz 10
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c2400Hz 3
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c300Hz 0
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c38k4Hz 7
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c460k8Hz 11
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c4800Hz 4
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c57k6Hz 8
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c600Hz 1
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c6250kHz 14
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c921k6Hz 12
+#define R_SERIAL3_CTRL__tr_baud__tr_baud__c9600Hz 5
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c115k2Hz 9
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c1200Hz 2
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c1843k2Hz 13
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c19k2Hz 6
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c230k4Hz 10
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c2400Hz 3
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c300Hz 0
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c38k4Hz 7
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c460k8Hz 11
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c4800Hz 4
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c57k6Hz 8
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c600Hz 1
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c6250kHz 14
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c921k6Hz 12
+#define R_SERIAL3_CTRL__rec_baud__rec_baud__c9600Hz 5
+#define R_SERIAL3_CTRL__dma_err__dma_err__ignore 1
+#define R_SERIAL3_CTRL__dma_err__dma_err__stop 0
+#define R_SERIAL3_CTRL__rec_enable__rec_enable__disable 0
+#define R_SERIAL3_CTRL__rec_enable__rec_enable__enable 1
+#define R_SERIAL3_CTRL__rts___rts___active 0
+#define R_SERIAL3_CTRL__rts___rts___inactive 1
+#define R_SERIAL3_CTRL__sampling__sampling__majority 1
+#define R_SERIAL3_CTRL__sampling__sampling__middle 0
+#define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__normal 0
+#define R_SERIAL3_CTRL__rec_stick_par__rec_stick_par__stick 1
+#define R_SERIAL3_CTRL__rec_par__rec_par__even 0
+#define R_SERIAL3_CTRL__rec_par__rec_par__odd 1
+#define R_SERIAL3_CTRL__rec_par_en__rec_par_en__disable 0
+#define R_SERIAL3_CTRL__rec_par_en__rec_par_en__enable 1
+#define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
+#define R_SERIAL3_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
+#define R_SERIAL3_CTRL__tr_enable__tr_enable__disable 0
+#define R_SERIAL3_CTRL__tr_enable__tr_enable__enable 1
+#define R_SERIAL3_CTRL__auto_cts__auto_cts__active 1
+#define R_SERIAL3_CTRL__auto_cts__auto_cts__disabled 0
+#define R_SERIAL3_CTRL__stop_bits__stop_bits__one_bit 0
+#define R_SERIAL3_CTRL__stop_bits__stop_bits__two_bits 1
+#define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__normal 0
+#define R_SERIAL3_CTRL__tr_stick_par__tr_stick_par__stick 1
+#define R_SERIAL3_CTRL__tr_par__tr_par__even 0
+#define R_SERIAL3_CTRL__tr_par__tr_par__odd 1
+#define R_SERIAL3_CTRL__tr_par_en__tr_par_en__disable 0
+#define R_SERIAL3_CTRL__tr_par_en__tr_par_en__enable 1
+#define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
+#define R_SERIAL3_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL3_READ
+ * - type: RO
+ * - addr: 0xb0000078
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_READ__ADDR (REG_TYPECAST_UDWORD 0xb0000078)
+#define R_SERIAL3_READ__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_READ__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL3_READ__TYPE (REG_UDWORD)
+#define R_SERIAL3_READ__GET REG_GET_RO
+#define R_SERIAL3_READ__IGET REG_IGET_RO
+#define R_SERIAL3_READ__SET REG_SET_RO
+#define R_SERIAL3_READ__ISET REG_ISET_RO
+#define R_SERIAL3_READ__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL3_READ__EQL REG_EQL_RO
+#define R_SERIAL3_READ__IEQL REG_IEQL_RO
+#define R_SERIAL3_READ__RD REG_RD_RO
+#define R_SERIAL3_READ__IRD REG_IRD_RO
+#define R_SERIAL3_READ__WR REG_WR_RO
+#define R_SERIAL3_READ__IWR REG_IWR_RO
+
+#define R_SERIAL3_READ__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL3_READ__xoff_detect__xoff_detect__MASK 0x00008000U
+#define R_SERIAL3_READ__cts___cts___MASK 0x00004000U
+#define R_SERIAL3_READ__tr_ready__tr_ready__MASK 0x00002000U
+#define R_SERIAL3_READ__rxd__rxd__MASK 0x00001000U
+#define R_SERIAL3_READ__overrun__overrun__MASK 0x00000800U
+#define R_SERIAL3_READ__par_err__par_err__MASK 0x00000400U
+#define R_SERIAL3_READ__framing_err__framing_err__MASK 0x00000200U
+#define R_SERIAL3_READ__data_avail__data_avail__MASK 0x00000100U
+#define R_SERIAL3_READ__data_in__data_in__MASK 0x000000ffU
+
+#define R_SERIAL3_READ__xoff_detect__MAX 0x1
+#define R_SERIAL3_READ__cts___MAX 0x1
+#define R_SERIAL3_READ__tr_ready__MAX 0x1
+#define R_SERIAL3_READ__rxd__MAX 0x1
+#define R_SERIAL3_READ__overrun__MAX 0x1
+#define R_SERIAL3_READ__par_err__MAX 0x1
+#define R_SERIAL3_READ__framing_err__MAX 0x1
+#define R_SERIAL3_READ__data_avail__MAX 0x1
+#define R_SERIAL3_READ__data_in__MAX 0xff
+
+#define R_SERIAL3_READ__xoff_detect__MIN 0
+#define R_SERIAL3_READ__cts___MIN 0
+#define R_SERIAL3_READ__tr_ready__MIN 0
+#define R_SERIAL3_READ__rxd__MIN 0
+#define R_SERIAL3_READ__overrun__MIN 0
+#define R_SERIAL3_READ__par_err__MIN 0
+#define R_SERIAL3_READ__framing_err__MIN 0
+#define R_SERIAL3_READ__data_avail__MIN 0
+#define R_SERIAL3_READ__data_in__MIN 0
+
+#define R_SERIAL3_READ__xoff_detect__BITNR 15
+#define R_SERIAL3_READ__cts___BITNR 14
+#define R_SERIAL3_READ__tr_ready__BITNR 13
+#define R_SERIAL3_READ__rxd__BITNR 12
+#define R_SERIAL3_READ__overrun__BITNR 11
+#define R_SERIAL3_READ__par_err__BITNR 10
+#define R_SERIAL3_READ__framing_err__BITNR 9
+#define R_SERIAL3_READ__data_avail__BITNR 8
+#define R_SERIAL3_READ__data_in__BITNR 0
+
+#define R_SERIAL3_READ__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
+#define R_SERIAL3_READ__cts___cts___VAL REG_VAL_ENUM
+#define R_SERIAL3_READ__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SERIAL3_READ__rxd__rxd__VAL REG_VAL_VAL
+#define R_SERIAL3_READ__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SERIAL3_READ__par_err__par_err__VAL REG_VAL_ENUM
+#define R_SERIAL3_READ__framing_err__framing_err__VAL REG_VAL_ENUM
+#define R_SERIAL3_READ__data_avail__data_avail__VAL REG_VAL_ENUM
+#define R_SERIAL3_READ__data_in__data_in__VAL REG_VAL_VAL
+
+#define R_SERIAL3_READ__xoff_detect__xoff_detect__no_xoff 0
+#define R_SERIAL3_READ__xoff_detect__xoff_detect__xoff 1
+#define R_SERIAL3_READ__cts___cts___active 0
+#define R_SERIAL3_READ__cts___cts___inactive 1
+#define R_SERIAL3_READ__tr_ready__tr_ready__full 0
+#define R_SERIAL3_READ__tr_ready__tr_ready__ready 1
+#define R_SERIAL3_READ__overrun__overrun__no 0
+#define R_SERIAL3_READ__overrun__overrun__yes 1
+#define R_SERIAL3_READ__par_err__par_err__no 0
+#define R_SERIAL3_READ__par_err__par_err__yes 1
+#define R_SERIAL3_READ__framing_err__framing_err__no 0
+#define R_SERIAL3_READ__framing_err__framing_err__yes 1
+#define R_SERIAL3_READ__data_avail__data_avail__no 0
+#define R_SERIAL3_READ__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SERIAL3_REC_CTRL
+ * - type: WO
+ * - addr: 0xb000007a
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_REC_CTRL__ADDR (REG_TYPECAST_BYTE 0xb000007a)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL3_REC_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 2))
+#define R_SERIAL3_REC_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 2))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL3_REC_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL3_REC_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL3_REC_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL3_REC_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_REC_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_REC_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL3_REC_CTRL__TYPE (REG_BYTE)
+#define R_SERIAL3_REC_CTRL__GET REG_GET_WO
+#define R_SERIAL3_REC_CTRL__IGET REG_IGET_WO
+#define R_SERIAL3_REC_CTRL__SET REG_SET_WO
+#define R_SERIAL3_REC_CTRL__ISET REG_ISET_WO
+#define R_SERIAL3_REC_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL3_REC_CTRL__EQL REG_EQL_WO
+#define R_SERIAL3_REC_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL3_REC_CTRL__RD REG_RD_WO
+#define R_SERIAL3_REC_CTRL__IRD REG_IRD_WO
+#define R_SERIAL3_REC_CTRL__WR REG_WR_WO
+#define R_SERIAL3_REC_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL3_REC_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL3_REC_CTRL__dma_err__dma_err__MASK 0x00000080U
+#define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__MASK 0x00000040U
+#define R_SERIAL3_REC_CTRL__rts___rts___MASK 0x00000020U
+#define R_SERIAL3_REC_CTRL__sampling__sampling__MASK 0x00000010U
+#define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__MASK 0x00000008U
+#define R_SERIAL3_REC_CTRL__rec_par__rec_par__MASK 0x00000004U
+#define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__MASK 0x00000002U
+#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__MASK 0x00000001U
+
+#define R_SERIAL3_REC_CTRL__dma_err__MAX 0x1
+#define R_SERIAL3_REC_CTRL__rec_enable__MAX 0x1
+#define R_SERIAL3_REC_CTRL__rts___MAX 0x1
+#define R_SERIAL3_REC_CTRL__sampling__MAX 0x1
+#define R_SERIAL3_REC_CTRL__rec_stick_par__MAX 0x1
+#define R_SERIAL3_REC_CTRL__rec_par__MAX 0x1
+#define R_SERIAL3_REC_CTRL__rec_par_en__MAX 0x1
+#define R_SERIAL3_REC_CTRL__rec_bitnr__MAX 0x1
+
+#define R_SERIAL3_REC_CTRL__dma_err__MIN 0
+#define R_SERIAL3_REC_CTRL__rec_enable__MIN 0
+#define R_SERIAL3_REC_CTRL__rts___MIN 0
+#define R_SERIAL3_REC_CTRL__sampling__MIN 0
+#define R_SERIAL3_REC_CTRL__rec_stick_par__MIN 0
+#define R_SERIAL3_REC_CTRL__rec_par__MIN 0
+#define R_SERIAL3_REC_CTRL__rec_par_en__MIN 0
+#define R_SERIAL3_REC_CTRL__rec_bitnr__MIN 0
+
+#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7
+#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6
+#define R_SERIAL3_REC_CTRL__rts___BITNR 5
+#define R_SERIAL3_REC_CTRL__sampling__BITNR 4
+#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3
+#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2
+#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1
+#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0
+
+#define R_SERIAL3_REC_CTRL__dma_err__dma_err__VAL REG_VAL_ENUM
+#define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SERIAL3_REC_CTRL__rts___rts___VAL REG_VAL_ENUM
+#define R_SERIAL3_REC_CTRL__sampling__sampling__VAL REG_VAL_ENUM
+#define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL3_REC_CTRL__rec_par__rec_par__VAL REG_VAL_ENUM
+#define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__VAL REG_VAL_ENUM
+
+#define R_SERIAL3_REC_CTRL__dma_err__dma_err__ignore 1
+#define R_SERIAL3_REC_CTRL__dma_err__dma_err__stop 0
+#define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__disable 0
+#define R_SERIAL3_REC_CTRL__rec_enable__rec_enable__enable 1
+#define R_SERIAL3_REC_CTRL__rts___rts___active 0
+#define R_SERIAL3_REC_CTRL__rts___rts___inactive 1
+#define R_SERIAL3_REC_CTRL__sampling__sampling__majority 1
+#define R_SERIAL3_REC_CTRL__sampling__sampling__middle 0
+#define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__normal 0
+#define R_SERIAL3_REC_CTRL__rec_stick_par__rec_stick_par__stick 1
+#define R_SERIAL3_REC_CTRL__rec_par__rec_par__even 0
+#define R_SERIAL3_REC_CTRL__rec_par__rec_par__odd 1
+#define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__disable 0
+#define R_SERIAL3_REC_CTRL__rec_par_en__rec_par_en__enable 1
+#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__rec_7bit 1
+#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_bitnr__rec_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL3_REC_DATA
+ * - type: RO
+ * - addr: 0xb0000078
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_REC_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000078)
+#define R_SERIAL3_REC_DATA__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_REC_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL3_REC_DATA__TYPE (REG_BYTE)
+#define R_SERIAL3_REC_DATA__GET REG_GET_RO
+#define R_SERIAL3_REC_DATA__IGET REG_IGET_RO
+#define R_SERIAL3_REC_DATA__SET REG_SET_RO
+#define R_SERIAL3_REC_DATA__ISET REG_ISET_RO
+#define R_SERIAL3_REC_DATA__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL3_REC_DATA__EQL REG_EQL_RO
+#define R_SERIAL3_REC_DATA__IEQL REG_IEQL_RO
+#define R_SERIAL3_REC_DATA__RD REG_RD_RO
+#define R_SERIAL3_REC_DATA__IRD REG_IRD_RO
+#define R_SERIAL3_REC_DATA__WR REG_WR_RO
+#define R_SERIAL3_REC_DATA__IWR REG_IWR_RO
+
+#define R_SERIAL3_REC_DATA__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL3_REC_DATA__data_in__data_in__MASK 0x000000ffU
+
+#define R_SERIAL3_REC_DATA__data_in__MAX 0xff
+
+#define R_SERIAL3_REC_DATA__data_in__MIN 0
+
+#define R_SERIAL3_REC_DATA__data_in__BITNR 0
+
+#define R_SERIAL3_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SERIAL3_STATUS
+ * - type: RO
+ * - addr: 0xb0000079
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000079)
+#define R_SERIAL3_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL3_STATUS__TYPE (REG_BYTE)
+#define R_SERIAL3_STATUS__GET REG_GET_RO
+#define R_SERIAL3_STATUS__IGET REG_IGET_RO
+#define R_SERIAL3_STATUS__SET REG_SET_RO
+#define R_SERIAL3_STATUS__ISET REG_ISET_RO
+#define R_SERIAL3_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SERIAL3_STATUS__EQL REG_EQL_RO
+#define R_SERIAL3_STATUS__IEQL REG_IEQL_RO
+#define R_SERIAL3_STATUS__RD REG_RD_RO
+#define R_SERIAL3_STATUS__IRD REG_IRD_RO
+#define R_SERIAL3_STATUS__WR REG_WR_RO
+#define R_SERIAL3_STATUS__IWR REG_IWR_RO
+
+#define R_SERIAL3_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_SERIAL3_STATUS__xoff_detect__xoff_detect__MASK 0x00000080U
+#define R_SERIAL3_STATUS__cts___cts___MASK 0x00000040U
+#define R_SERIAL3_STATUS__tr_ready__tr_ready__MASK 0x00000020U
+#define R_SERIAL3_STATUS__rxd__rxd__MASK 0x00000010U
+#define R_SERIAL3_STATUS__overrun__overrun__MASK 0x00000008U
+#define R_SERIAL3_STATUS__par_err__par_err__MASK 0x00000004U
+#define R_SERIAL3_STATUS__framing_err__framing_err__MASK 0x00000002U
+#define R_SERIAL3_STATUS__data_avail__data_avail__MASK 0x00000001U
+
+#define R_SERIAL3_STATUS__xoff_detect__MAX 0x1
+#define R_SERIAL3_STATUS__cts___MAX 0x1
+#define R_SERIAL3_STATUS__tr_ready__MAX 0x1
+#define R_SERIAL3_STATUS__rxd__MAX 0x1
+#define R_SERIAL3_STATUS__overrun__MAX 0x1
+#define R_SERIAL3_STATUS__par_err__MAX 0x1
+#define R_SERIAL3_STATUS__framing_err__MAX 0x1
+#define R_SERIAL3_STATUS__data_avail__MAX 0x1
+
+#define R_SERIAL3_STATUS__xoff_detect__MIN 0
+#define R_SERIAL3_STATUS__cts___MIN 0
+#define R_SERIAL3_STATUS__tr_ready__MIN 0
+#define R_SERIAL3_STATUS__rxd__MIN 0
+#define R_SERIAL3_STATUS__overrun__MIN 0
+#define R_SERIAL3_STATUS__par_err__MIN 0
+#define R_SERIAL3_STATUS__framing_err__MIN 0
+#define R_SERIAL3_STATUS__data_avail__MIN 0
+
+#define R_SERIAL3_STATUS__xoff_detect__BITNR 7
+#define R_SERIAL3_STATUS__cts___BITNR 6
+#define R_SERIAL3_STATUS__tr_ready__BITNR 5
+#define R_SERIAL3_STATUS__rxd__BITNR 4
+#define R_SERIAL3_STATUS__overrun__BITNR 3
+#define R_SERIAL3_STATUS__par_err__BITNR 2
+#define R_SERIAL3_STATUS__framing_err__BITNR 1
+#define R_SERIAL3_STATUS__data_avail__BITNR 0
+
+#define R_SERIAL3_STATUS__xoff_detect__xoff_detect__VAL REG_VAL_ENUM
+#define R_SERIAL3_STATUS__cts___cts___VAL REG_VAL_ENUM
+#define R_SERIAL3_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SERIAL3_STATUS__rxd__rxd__VAL REG_VAL_VAL
+#define R_SERIAL3_STATUS__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SERIAL3_STATUS__par_err__par_err__VAL REG_VAL_ENUM
+#define R_SERIAL3_STATUS__framing_err__framing_err__VAL REG_VAL_ENUM
+#define R_SERIAL3_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
+
+#define R_SERIAL3_STATUS__xoff_detect__xoff_detect__no_xoff 0
+#define R_SERIAL3_STATUS__xoff_detect__xoff_detect__xoff 1
+#define R_SERIAL3_STATUS__cts___cts___active 0
+#define R_SERIAL3_STATUS__cts___cts___inactive 1
+#define R_SERIAL3_STATUS__tr_ready__tr_ready__full 0
+#define R_SERIAL3_STATUS__tr_ready__tr_ready__ready 1
+#define R_SERIAL3_STATUS__overrun__overrun__no 0
+#define R_SERIAL3_STATUS__overrun__overrun__yes 1
+#define R_SERIAL3_STATUS__par_err__par_err__no 0
+#define R_SERIAL3_STATUS__par_err__par_err__yes 1
+#define R_SERIAL3_STATUS__framing_err__framing_err__no 0
+#define R_SERIAL3_STATUS__framing_err__framing_err__yes 1
+#define R_SERIAL3_STATUS__data_avail__data_avail__no 0
+#define R_SERIAL3_STATUS__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SERIAL3_TR_CTRL
+ * - type: WO
+ * - addr: 0xb0000079
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_TR_CTRL__ADDR (REG_TYPECAST_BYTE 0xb0000079)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL3_TR_CTRL__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 1))
+#define R_SERIAL3_TR_CTRL__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 1))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL3_TR_CTRL__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL3_TR_CTRL__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL3_TR_CTRL__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL3_TR_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_TR_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_TR_CTRL__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL3_TR_CTRL__TYPE (REG_BYTE)
+#define R_SERIAL3_TR_CTRL__GET REG_GET_WO
+#define R_SERIAL3_TR_CTRL__IGET REG_IGET_WO
+#define R_SERIAL3_TR_CTRL__SET REG_SET_WO
+#define R_SERIAL3_TR_CTRL__ISET REG_ISET_WO
+#define R_SERIAL3_TR_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL3_TR_CTRL__EQL REG_EQL_WO
+#define R_SERIAL3_TR_CTRL__IEQL REG_IEQL_WO
+#define R_SERIAL3_TR_CTRL__RD REG_RD_WO
+#define R_SERIAL3_TR_CTRL__IRD REG_IRD_WO
+#define R_SERIAL3_TR_CTRL__WR REG_WR_WO
+#define R_SERIAL3_TR_CTRL__IWR REG_IWR_WO
+
+#define R_SERIAL3_TR_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL3_TR_CTRL__txd__txd__MASK 0x00000080U
+#define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__MASK 0x00000040U
+#define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__MASK 0x00000020U
+#define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__MASK 0x00000010U
+#define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__MASK 0x00000008U
+#define R_SERIAL3_TR_CTRL__tr_par__tr_par__MASK 0x00000004U
+#define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__MASK 0x00000002U
+#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__MASK 0x00000001U
+
+#define R_SERIAL3_TR_CTRL__txd__MAX 0x1
+#define R_SERIAL3_TR_CTRL__tr_enable__MAX 0x1
+#define R_SERIAL3_TR_CTRL__auto_cts__MAX 0x1
+#define R_SERIAL3_TR_CTRL__stop_bits__MAX 0x1
+#define R_SERIAL3_TR_CTRL__tr_stick_par__MAX 0x1
+#define R_SERIAL3_TR_CTRL__tr_par__MAX 0x1
+#define R_SERIAL3_TR_CTRL__tr_par_en__MAX 0x1
+#define R_SERIAL3_TR_CTRL__tr_bitnr__MAX 0x1
+
+#define R_SERIAL3_TR_CTRL__txd__MIN 0
+#define R_SERIAL3_TR_CTRL__tr_enable__MIN 0
+#define R_SERIAL3_TR_CTRL__auto_cts__MIN 0
+#define R_SERIAL3_TR_CTRL__stop_bits__MIN 0
+#define R_SERIAL3_TR_CTRL__tr_stick_par__MIN 0
+#define R_SERIAL3_TR_CTRL__tr_par__MIN 0
+#define R_SERIAL3_TR_CTRL__tr_par_en__MIN 0
+#define R_SERIAL3_TR_CTRL__tr_bitnr__MIN 0
+
+#define R_SERIAL3_TR_CTRL__txd__BITNR 7
+#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6
+#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5
+#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4
+#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3
+#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2
+#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1
+#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0
+
+#define R_SERIAL3_TR_CTRL__txd__txd__VAL REG_VAL_VAL
+#define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__VAL REG_VAL_ENUM
+#define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__VAL REG_VAL_ENUM
+#define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__VAL REG_VAL_ENUM
+#define R_SERIAL3_TR_CTRL__tr_par__tr_par__VAL REG_VAL_ENUM
+#define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__VAL REG_VAL_ENUM
+#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__VAL REG_VAL_ENUM
+
+#define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__disable 0
+#define R_SERIAL3_TR_CTRL__tr_enable__tr_enable__enable 1
+#define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__active 1
+#define R_SERIAL3_TR_CTRL__auto_cts__auto_cts__disabled 0
+#define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__one_bit 0
+#define R_SERIAL3_TR_CTRL__stop_bits__stop_bits__two_bits 1
+#define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__normal 0
+#define R_SERIAL3_TR_CTRL__tr_stick_par__tr_stick_par__stick 1
+#define R_SERIAL3_TR_CTRL__tr_par__tr_par__even 0
+#define R_SERIAL3_TR_CTRL__tr_par__tr_par__odd 1
+#define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__disable 0
+#define R_SERIAL3_TR_CTRL__tr_par_en__tr_par_en__enable 1
+#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__tr_7bit 1
+#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_bitnr__tr_8bit 0
+
+#endif
+
+/*
+ * R_SERIAL3_TR_DATA
+ * - type: WO
+ * - addr: 0xb0000078
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_TR_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000078)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_CTRL + 0))
+#define R_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL3_TR_DATA__STYPECAST REG_STYPECAST_BYTE
+#define R_SERIAL3_TR_DATA__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_TR_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_SERIAL3_TR_DATA__TYPE (REG_BYTE)
+#define R_SERIAL3_TR_DATA__GET REG_GET_WO
+#define R_SERIAL3_TR_DATA__IGET REG_IGET_WO
+#define R_SERIAL3_TR_DATA__SET REG_SET_WO
+#define R_SERIAL3_TR_DATA__ISET REG_ISET_WO
+#define R_SERIAL3_TR_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL3_TR_DATA__EQL REG_EQL_WO
+#define R_SERIAL3_TR_DATA__IEQL REG_IEQL_WO
+#define R_SERIAL3_TR_DATA__RD REG_RD_WO
+#define R_SERIAL3_TR_DATA__IRD REG_IRD_WO
+#define R_SERIAL3_TR_DATA__WR REG_WR_WO
+#define R_SERIAL3_TR_DATA__IWR REG_IWR_WO
+
+#define R_SERIAL3_TR_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL3_TR_DATA__data_out__data_out__MASK 0x000000ffU
+
+#define R_SERIAL3_TR_DATA__data_out__MAX 0xff
+
+#define R_SERIAL3_TR_DATA__data_out__MIN 0
+
+#define R_SERIAL3_TR_DATA__data_out__BITNR 0
+
+#define R_SERIAL3_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SERIAL3_XOFF
+ * - type: WO
+ * - addr: 0xb000007c
+ * - group: Serial port registers
+ */
+
+#if USE_GROUP__Serial_port_registers
+
+#define R_SERIAL3_XOFF__ADDR (REG_TYPECAST_UDWORD 0xb000007c)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL3_XOFF__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0))
+#define R_SERIAL3_XOFF__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL3_XOFF__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SERIAL3_XOFF__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL3_XOFF__STYPECAST REG_STYPECAST_UDWORD
+#define R_SERIAL3_XOFF__SVAL REG_SVAL_SHADOW
+#define R_SERIAL3_XOFF__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL3_XOFF__TYPECAST REG_TYPECAST_UDWORD
+#define R_SERIAL3_XOFF__TYPE (REG_UDWORD)
+#define R_SERIAL3_XOFF__GET REG_GET_WO
+#define R_SERIAL3_XOFF__IGET REG_IGET_WO
+#define R_SERIAL3_XOFF__SET REG_SET_WO
+#define R_SERIAL3_XOFF__ISET REG_ISET_WO
+#define R_SERIAL3_XOFF__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL3_XOFF__EQL REG_EQL_WO
+#define R_SERIAL3_XOFF__IEQL REG_IEQL_WO
+#define R_SERIAL3_XOFF__RD REG_RD_WO
+#define R_SERIAL3_XOFF__IRD REG_IRD_WO
+#define R_SERIAL3_XOFF__WR REG_WR_WO
+#define R_SERIAL3_XOFF__IWR REG_IWR_WO
+
+#define R_SERIAL3_XOFF__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL3_XOFF__tx_stop__tx_stop__MASK 0x00000200U
+#define R_SERIAL3_XOFF__auto_xoff__auto_xoff__MASK 0x00000100U
+#define R_SERIAL3_XOFF__xoff_char__xoff_char__MASK 0x000000ffU
+
+#define R_SERIAL3_XOFF__tx_stop__MAX 0x1
+#define R_SERIAL3_XOFF__auto_xoff__MAX 0x1
+#define R_SERIAL3_XOFF__xoff_char__MAX 0xff
+
+#define R_SERIAL3_XOFF__tx_stop__MIN 0
+#define R_SERIAL3_XOFF__auto_xoff__MIN 0
+#define R_SERIAL3_XOFF__xoff_char__MIN 0
+
+#define R_SERIAL3_XOFF__tx_stop__BITNR 9
+#define R_SERIAL3_XOFF__auto_xoff__BITNR 8
+#define R_SERIAL3_XOFF__xoff_char__BITNR 0
+
+#define R_SERIAL3_XOFF__tx_stop__tx_stop__VAL REG_VAL_ENUM
+#define R_SERIAL3_XOFF__auto_xoff__auto_xoff__VAL REG_VAL_ENUM
+#define R_SERIAL3_XOFF__xoff_char__xoff_char__VAL REG_VAL_VAL
+
+#define R_SERIAL3_XOFF__tx_stop__tx_stop__enable 0
+#define R_SERIAL3_XOFF__tx_stop__tx_stop__stop 1
+#define R_SERIAL3_XOFF__auto_xoff__auto_xoff__disable 0
+#define R_SERIAL3_XOFF__auto_xoff__auto_xoff__enable 1
+
+#endif
+
+/*
+ * R_SERIAL_PRESCALE
+ * - type: WO
+ * - addr: 0xb00000f2
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_SERIAL_PRESCALE__ADDR (REG_TYPECAST_UWORD 0xb00000f2)
+
+#ifndef REG_NO_SHADOW
+#define R_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 2))
+#define R_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 2))
+#else /* REG_NO_SHADOW */
+#define R_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SERIAL_PRESCALE__STYPECAST REG_STYPECAST_UWORD
+#define R_SERIAL_PRESCALE__SVAL REG_SVAL_SHADOW
+#define R_SERIAL_PRESCALE__SVAL_I REG_SVAL_I_SHADOW
+#define R_SERIAL_PRESCALE__TYPECAST REG_TYPECAST_UWORD
+#define R_SERIAL_PRESCALE__TYPE (REG_UWORD)
+#define R_SERIAL_PRESCALE__GET REG_GET_WO
+#define R_SERIAL_PRESCALE__IGET REG_IGET_WO
+#define R_SERIAL_PRESCALE__SET REG_SET_WO
+#define R_SERIAL_PRESCALE__ISET REG_ISET_WO
+#define R_SERIAL_PRESCALE__SET_VAL REG_SET_VAL_WO
+#define R_SERIAL_PRESCALE__EQL REG_EQL_WO
+#define R_SERIAL_PRESCALE__IEQL REG_IEQL_WO
+#define R_SERIAL_PRESCALE__RD REG_RD_WO
+#define R_SERIAL_PRESCALE__IRD REG_IRD_WO
+#define R_SERIAL_PRESCALE__WR REG_WR_WO
+#define R_SERIAL_PRESCALE__IWR REG_IWR_WO
+
+#define R_SERIAL_PRESCALE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SERIAL_PRESCALE__ser_presc__ser_presc__MASK 0x0000ffffU
+
+#define R_SERIAL_PRESCALE__ser_presc__MAX 0xffff
+
+#define R_SERIAL_PRESCALE__ser_presc__MIN 0
+
+#define R_SERIAL_PRESCALE__ser_presc__BITNR 0
+
+#define R_SERIAL_PRESCALE__ser_presc__ser_presc__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SER_PRESC_STATUS
+ * - type: RO
+ * - addr: 0xb00000f2
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_SER_PRESC_STATUS__ADDR (REG_TYPECAST_UWORD 0xb00000f2)
+#define R_SER_PRESC_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SER_PRESC_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SER_PRESC_STATUS__TYPECAST REG_TYPECAST_UWORD
+#define R_SER_PRESC_STATUS__TYPE (REG_UWORD)
+#define R_SER_PRESC_STATUS__GET REG_GET_RO
+#define R_SER_PRESC_STATUS__IGET REG_IGET_RO
+#define R_SER_PRESC_STATUS__SET REG_SET_RO
+#define R_SER_PRESC_STATUS__ISET REG_ISET_RO
+#define R_SER_PRESC_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SER_PRESC_STATUS__EQL REG_EQL_RO
+#define R_SER_PRESC_STATUS__IEQL REG_IEQL_RO
+#define R_SER_PRESC_STATUS__RD REG_RD_RO
+#define R_SER_PRESC_STATUS__IRD REG_IRD_RO
+#define R_SER_PRESC_STATUS__WR REG_WR_RO
+#define R_SER_PRESC_STATUS__IWR REG_IWR_RO
+
+#define R_SER_PRESC_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_SER_PRESC_STATUS__ser_status__ser_status__MASK 0x0000ffffU
+
+#define R_SER_PRESC_STATUS__ser_status__MAX 0xffff
+
+#define R_SER_PRESC_STATUS__ser_status__MIN 0
+
+#define R_SER_PRESC_STATUS__ser_status__BITNR 0
+
+#define R_SER_PRESC_STATUS__ser_status__ser_status__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SET_EOP
+ * - type: WO
+ * - addr: 0xb000003c
+ * - group: DMA registers
+ */
+
+#if USE_GROUP__DMA_registers
+
+#define R_SET_EOP__ADDR (REG_TYPECAST_UDWORD 0xb000003c)
+
+#ifndef REG_NO_SHADOW
+#define R_SET_EOP__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SET_EOP + 0))
+#define R_SET_EOP__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SET_EOP + 0))
+#else /* REG_NO_SHADOW */
+#define R_SET_EOP__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SET_EOP__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SET_EOP__STYPECAST REG_STYPECAST_UDWORD
+#define R_SET_EOP__SVAL REG_SVAL_ZERO
+#define R_SET_EOP__SVAL_I REG_SVAL_I_ZERO
+#define R_SET_EOP__TYPECAST REG_TYPECAST_UDWORD
+#define R_SET_EOP__TYPE (REG_UDWORD)
+#define R_SET_EOP__GET REG_GET_WO
+#define R_SET_EOP__IGET REG_IGET_WO
+#define R_SET_EOP__SET REG_SET_WO
+#define R_SET_EOP__ISET REG_ISET_WO
+#define R_SET_EOP__SET_VAL REG_SET_VAL_WO
+#define R_SET_EOP__EQL REG_EQL_WO
+#define R_SET_EOP__IEQL REG_IEQL_WO
+#define R_SET_EOP__RD REG_RD_WO
+#define R_SET_EOP__IRD REG_IRD_WO
+#define R_SET_EOP__WR REG_WR_WO
+#define R_SET_EOP__IWR REG_IWR_WO
+
+#define R_SET_EOP__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SET_EOP__ch9_eop__ch9_eop__MASK 0x00000008U
+#define R_SET_EOP__ch7_eop__ch7_eop__MASK 0x00000004U
+#define R_SET_EOP__ch5_eop__ch5_eop__MASK 0x00000002U
+#define R_SET_EOP__ch3_eop__ch3_eop__MASK 0x00000001U
+
+#define R_SET_EOP__ch9_eop__MAX 0x1
+#define R_SET_EOP__ch7_eop__MAX 0x1
+#define R_SET_EOP__ch5_eop__MAX 0x1
+#define R_SET_EOP__ch3_eop__MAX 0x1
+
+#define R_SET_EOP__ch9_eop__MIN 0
+#define R_SET_EOP__ch7_eop__MIN 0
+#define R_SET_EOP__ch5_eop__MIN 0
+#define R_SET_EOP__ch3_eop__MIN 0
+
+#define R_SET_EOP__ch9_eop__BITNR 3
+#define R_SET_EOP__ch7_eop__BITNR 2
+#define R_SET_EOP__ch5_eop__BITNR 1
+#define R_SET_EOP__ch3_eop__BITNR 0
+
+#define R_SET_EOP__ch9_eop__ch9_eop__VAL REG_VAL_ENUM
+#define R_SET_EOP__ch7_eop__ch7_eop__VAL REG_VAL_ENUM
+#define R_SET_EOP__ch5_eop__ch5_eop__VAL REG_VAL_ENUM
+#define R_SET_EOP__ch3_eop__ch3_eop__VAL REG_VAL_ENUM
+
+#define R_SET_EOP__ch9_eop__ch9_eop__nop 0
+#define R_SET_EOP__ch9_eop__ch9_eop__set 1
+#define R_SET_EOP__ch7_eop__ch7_eop__nop 0
+#define R_SET_EOP__ch7_eop__ch7_eop__set 1
+#define R_SET_EOP__ch5_eop__ch5_eop__nop 0
+#define R_SET_EOP__ch5_eop__ch5_eop__set 1
+#define R_SET_EOP__ch3_eop__ch3_eop__nop 0
+#define R_SET_EOP__ch3_eop__ch3_eop__set 1
+
+#endif
+
+/*
+ * R_SHARED_RAM_ADDR
+ * - type: WO
+ * - addr: 0xb0000044
+ * - group: Shared RAM interface registers
+ */
+
+#if USE_GROUP__Shared_RAM_interface_registers
+
+#define R_SHARED_RAM_ADDR__ADDR (REG_TYPECAST_UDWORD 0xb0000044)
+
+#ifndef REG_NO_SHADOW
+#define R_SHARED_RAM_ADDR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CONFIG + 0))
+#define R_SHARED_RAM_ADDR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CONFIG + 0))
+#else /* REG_NO_SHADOW */
+#define R_SHARED_RAM_ADDR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SHARED_RAM_ADDR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SHARED_RAM_ADDR__STYPECAST REG_STYPECAST_UDWORD
+#define R_SHARED_RAM_ADDR__SVAL REG_SVAL_SHADOW
+#define R_SHARED_RAM_ADDR__SVAL_I REG_SVAL_I_SHADOW
+#define R_SHARED_RAM_ADDR__TYPECAST REG_TYPECAST_UDWORD
+#define R_SHARED_RAM_ADDR__TYPE (REG_UDWORD)
+#define R_SHARED_RAM_ADDR__GET REG_GET_WO
+#define R_SHARED_RAM_ADDR__IGET REG_IGET_WO
+#define R_SHARED_RAM_ADDR__SET REG_SET_WO
+#define R_SHARED_RAM_ADDR__ISET REG_ISET_WO
+#define R_SHARED_RAM_ADDR__SET_VAL REG_SET_VAL_WO
+#define R_SHARED_RAM_ADDR__EQL REG_EQL_WO
+#define R_SHARED_RAM_ADDR__IEQL REG_IEQL_WO
+#define R_SHARED_RAM_ADDR__RD REG_RD_WO
+#define R_SHARED_RAM_ADDR__IRD REG_IRD_WO
+#define R_SHARED_RAM_ADDR__WR REG_WR_WO
+#define R_SHARED_RAM_ADDR__IWR REG_IWR_WO
+
+#define R_SHARED_RAM_ADDR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SHARED_RAM_ADDR__base_addr__base_addr__MASK 0x3fffff00U
+
+#define R_SHARED_RAM_ADDR__base_addr__MAX 0x3fffff
+
+#define R_SHARED_RAM_ADDR__base_addr__MIN 0
+
+#define R_SHARED_RAM_ADDR__base_addr__BITNR 8
+
+#define R_SHARED_RAM_ADDR__base_addr__base_addr__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SHARED_RAM_CONFIG
+ * - type: WO
+ * - addr: 0xb0000040
+ * - group: Shared RAM interface registers
+ */
+
+#if USE_GROUP__Shared_RAM_interface_registers
+
+#define R_SHARED_RAM_CONFIG__ADDR (REG_TYPECAST_UDWORD 0xb0000040)
+
+#ifndef REG_NO_SHADOW
+#define R_SHARED_RAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_ATA_CTRL_DATA + 0))
+#define R_SHARED_RAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_ATA_CTRL_DATA + 0))
+#else /* REG_NO_SHADOW */
+#define R_SHARED_RAM_CONFIG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SHARED_RAM_CONFIG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SHARED_RAM_CONFIG__STYPECAST REG_STYPECAST_UDWORD
+#define R_SHARED_RAM_CONFIG__SVAL REG_SVAL_SHADOW
+#define R_SHARED_RAM_CONFIG__SVAL_I REG_SVAL_I_SHADOW
+#define R_SHARED_RAM_CONFIG__TYPECAST REG_TYPECAST_UDWORD
+#define R_SHARED_RAM_CONFIG__TYPE (REG_UDWORD)
+#define R_SHARED_RAM_CONFIG__GET REG_GET_WO
+#define R_SHARED_RAM_CONFIG__IGET REG_IGET_WO
+#define R_SHARED_RAM_CONFIG__SET REG_SET_WO
+#define R_SHARED_RAM_CONFIG__ISET REG_ISET_WO
+#define R_SHARED_RAM_CONFIG__SET_VAL REG_SET_VAL_WO
+#define R_SHARED_RAM_CONFIG__EQL REG_EQL_WO
+#define R_SHARED_RAM_CONFIG__IEQL REG_IEQL_WO
+#define R_SHARED_RAM_CONFIG__RD REG_RD_WO
+#define R_SHARED_RAM_CONFIG__IRD REG_IRD_WO
+#define R_SHARED_RAM_CONFIG__WR REG_WR_WO
+#define R_SHARED_RAM_CONFIG__IWR REG_IWR_WO
+
+#define R_SHARED_RAM_CONFIG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SHARED_RAM_CONFIG__width__width__MASK 0x00000008U
+#define R_SHARED_RAM_CONFIG__enable__enable__MASK 0x00000004U
+#define R_SHARED_RAM_CONFIG__pint__pint__MASK 0x00000002U
+#define R_SHARED_RAM_CONFIG__clri__clri__MASK 0x00000001U
+
+#define R_SHARED_RAM_CONFIG__width__MAX 0x1
+#define R_SHARED_RAM_CONFIG__enable__MAX 0x1
+#define R_SHARED_RAM_CONFIG__pint__MAX 0x1
+#define R_SHARED_RAM_CONFIG__clri__MAX 0x1
+
+#define R_SHARED_RAM_CONFIG__width__MIN 0
+#define R_SHARED_RAM_CONFIG__enable__MIN 0
+#define R_SHARED_RAM_CONFIG__pint__MIN 0
+#define R_SHARED_RAM_CONFIG__clri__MIN 0
+
+#define R_SHARED_RAM_CONFIG__width__BITNR 3
+#define R_SHARED_RAM_CONFIG__enable__BITNR 2
+#define R_SHARED_RAM_CONFIG__pint__BITNR 1
+#define R_SHARED_RAM_CONFIG__clri__BITNR 0
+
+#define R_SHARED_RAM_CONFIG__width__width__VAL REG_VAL_ENUM
+#define R_SHARED_RAM_CONFIG__enable__enable__VAL REG_VAL_ENUM
+#define R_SHARED_RAM_CONFIG__pint__pint__VAL REG_VAL_ENUM
+#define R_SHARED_RAM_CONFIG__clri__clri__VAL REG_VAL_ENUM
+
+#define R_SHARED_RAM_CONFIG__width__width__byte 0
+#define R_SHARED_RAM_CONFIG__width__width__word 1
+#define R_SHARED_RAM_CONFIG__enable__enable__no 0
+#define R_SHARED_RAM_CONFIG__enable__enable__yes 1
+#define R_SHARED_RAM_CONFIG__pint__pint__int 1
+#define R_SHARED_RAM_CONFIG__pint__pint__nop 0
+#define R_SHARED_RAM_CONFIG__clri__clri__clr 1
+#define R_SHARED_RAM_CONFIG__clri__clri__nop 0
+
+#endif
+
+/*
+ * R_SINGLE_STEP
+ * - type: WO
+ * - addr: 0xb00000fe
+ * - group: Test mode registers
+ */
+
+#if USE_GROUP__Test_mode_registers
+
+#define R_SINGLE_STEP__ADDR (REG_TYPECAST_BYTE 0xb00000fe)
+
+#ifndef REG_NO_SHADOW
+#define R_SINGLE_STEP__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_TEST_MODE + 2))
+#define R_SINGLE_STEP__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_TEST_MODE + 2))
+#else /* REG_NO_SHADOW */
+#define R_SINGLE_STEP__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SINGLE_STEP__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SINGLE_STEP__STYPECAST REG_STYPECAST_BYTE
+#define R_SINGLE_STEP__SVAL REG_SVAL_SHADOW
+#define R_SINGLE_STEP__SVAL_I REG_SVAL_I_SHADOW
+#define R_SINGLE_STEP__TYPECAST REG_TYPECAST_BYTE
+#define R_SINGLE_STEP__TYPE (REG_BYTE)
+#define R_SINGLE_STEP__GET REG_GET_WO
+#define R_SINGLE_STEP__IGET REG_IGET_WO
+#define R_SINGLE_STEP__SET REG_SET_WO
+#define R_SINGLE_STEP__ISET REG_ISET_WO
+#define R_SINGLE_STEP__SET_VAL REG_SET_VAL_WO
+#define R_SINGLE_STEP__EQL REG_EQL_WO
+#define R_SINGLE_STEP__IEQL REG_IEQL_WO
+#define R_SINGLE_STEP__RD REG_RD_WO
+#define R_SINGLE_STEP__IRD REG_IRD_WO
+#define R_SINGLE_STEP__WR REG_WR_WO
+#define R_SINGLE_STEP__IWR REG_IWR_WO
+
+#define R_SINGLE_STEP__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SINGLE_STEP__single_step__single_step__MASK 0x00000008U
+#define R_SINGLE_STEP__step_wr__step_wr__MASK 0x00000004U
+#define R_SINGLE_STEP__step_rd__step_rd__MASK 0x00000002U
+#define R_SINGLE_STEP__step_fetch__step_fetch__MASK 0x00000001U
+
+#define R_SINGLE_STEP__single_step__MAX 0x1
+#define R_SINGLE_STEP__step_wr__MAX 0x1
+#define R_SINGLE_STEP__step_rd__MAX 0x1
+#define R_SINGLE_STEP__step_fetch__MAX 0x1
+
+#define R_SINGLE_STEP__single_step__MIN 0
+#define R_SINGLE_STEP__step_wr__MIN 0
+#define R_SINGLE_STEP__step_rd__MIN 0
+#define R_SINGLE_STEP__step_fetch__MIN 0
+
+#define R_SINGLE_STEP__single_step__BITNR 3
+#define R_SINGLE_STEP__step_wr__BITNR 2
+#define R_SINGLE_STEP__step_rd__BITNR 1
+#define R_SINGLE_STEP__step_fetch__BITNR 0
+
+#define R_SINGLE_STEP__single_step__single_step__VAL REG_VAL_ENUM
+#define R_SINGLE_STEP__step_wr__step_wr__VAL REG_VAL_ENUM
+#define R_SINGLE_STEP__step_rd__step_rd__VAL REG_VAL_ENUM
+#define R_SINGLE_STEP__step_fetch__step_fetch__VAL REG_VAL_ENUM
+
+#define R_SINGLE_STEP__single_step__single_step__off 0
+#define R_SINGLE_STEP__single_step__single_step__on 1
+#define R_SINGLE_STEP__step_wr__step_wr__off 0
+#define R_SINGLE_STEP__step_wr__step_wr__on 1
+#define R_SINGLE_STEP__step_rd__step_rd__off 0
+#define R_SINGLE_STEP__step_rd__step_rd__on 1
+#define R_SINGLE_STEP__step_fetch__step_fetch__off 0
+#define R_SINGLE_STEP__step_fetch__step_fetch__on 1
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_CTRL
+ * - type: WO
+ * - addr: 0xb0000068
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL1_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000068)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_CTRL + 0))
+#define R_SYNC_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL1_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL1_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL1_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_SYNC_SERIAL1_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL1_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL1_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL1_CTRL__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL1_CTRL__GET REG_GET_WO
+#define R_SYNC_SERIAL1_CTRL__IGET REG_IGET_WO
+#define R_SYNC_SERIAL1_CTRL__SET REG_SET_WO
+#define R_SYNC_SERIAL1_CTRL__ISET REG_ISET_WO
+#define R_SYNC_SERIAL1_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL1_CTRL__EQL REG_EQL_WO
+#define R_SYNC_SERIAL1_CTRL__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL1_CTRL__RD REG_RD_WO
+#define R_SYNC_SERIAL1_CTRL__IRD REG_IRD_WO
+#define R_SYNC_SERIAL1_CTRL__WR REG_WR_WO
+#define R_SYNC_SERIAL1_CTRL__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL1_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
+#define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__MASK 0x08000000U
+#define R_SYNC_SERIAL1_CTRL__mode__mode__MASK 0x07000000U
+#define R_SYNC_SERIAL1_CTRL__error__error__MASK 0x00800000U
+#define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__MASK 0x00400000U
+#define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__MASK 0x00200000U
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__MASK 0x00180000U
+#define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__MASK 0x00040000U
+#define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__MASK 0x00020000U
+#define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__MASK 0x00010000U
+#define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__MASK 0x00008000U
+#define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__MASK 0x00004000U
+#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__MASK 0x00003800U
+#define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__MASK 0x00000400U
+#define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__MASK 0x00000200U
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__MASK 0x00000100U
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__MASK 0x00000040U
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__MASK 0x00000020U
+#define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__MASK 0x00000010U
+#define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__MASK 0x00000008U
+#define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__MASK 0x00000004U
+#define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__MASK 0x00000002U
+#define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__MASK 0x00000001U
+
+#define R_SYNC_SERIAL1_CTRL__tr_baud__MAX 0xf
+#define R_SYNC_SERIAL1_CTRL__dma_enable__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__mode__MAX 0x7
+#define R_SYNC_SERIAL1_CTRL__error__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__rec_enable__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__f_synctype__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__MAX 0x3
+#define R_SYNC_SERIAL1_CTRL__f_sync__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__clk_mode__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__clk_halt__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__bitorder__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__tr_enable__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__wordsize__MAX 0x7
+#define R_SYNC_SERIAL1_CTRL__buf_empty__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__buf_full__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__status_polarity__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__clk_driver__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__frame_driver__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__status_driver__MAX 0x1
+#define R_SYNC_SERIAL1_CTRL__def_out0__MAX 0x1
+
+#define R_SYNC_SERIAL1_CTRL__tr_baud__MIN 0
+#define R_SYNC_SERIAL1_CTRL__dma_enable__MIN 0
+#define R_SYNC_SERIAL1_CTRL__mode__MIN 0
+#define R_SYNC_SERIAL1_CTRL__error__MIN 0
+#define R_SYNC_SERIAL1_CTRL__rec_enable__MIN 0
+#define R_SYNC_SERIAL1_CTRL__f_synctype__MIN 0
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__MIN 0
+#define R_SYNC_SERIAL1_CTRL__f_sync__MIN 0
+#define R_SYNC_SERIAL1_CTRL__clk_mode__MIN 0
+#define R_SYNC_SERIAL1_CTRL__clk_halt__MIN 0
+#define R_SYNC_SERIAL1_CTRL__bitorder__MIN 0
+#define R_SYNC_SERIAL1_CTRL__tr_enable__MIN 0
+#define R_SYNC_SERIAL1_CTRL__wordsize__MIN 0
+#define R_SYNC_SERIAL1_CTRL__buf_empty__MIN 0
+#define R_SYNC_SERIAL1_CTRL__buf_full__MIN 0
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__MIN 0
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__MIN 0
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__MIN 0
+#define R_SYNC_SERIAL1_CTRL__status_polarity__MIN 0
+#define R_SYNC_SERIAL1_CTRL__clk_driver__MIN 0
+#define R_SYNC_SERIAL1_CTRL__frame_driver__MIN 0
+#define R_SYNC_SERIAL1_CTRL__status_driver__MIN 0
+#define R_SYNC_SERIAL1_CTRL__def_out0__MIN 0
+
+#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28
+#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27
+#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24
+#define R_SYNC_SERIAL1_CTRL__error__BITNR 23
+#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22
+#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19
+#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18
+#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17
+#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16
+#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15
+#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14
+#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11
+#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10
+#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5
+#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4
+#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3
+#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2
+#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1
+#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0
+
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__mode__mode__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__error__error__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__VAL REG_VAL_ENUM
+
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c115k2Hz 10
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c1200Hz 3
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c150Hz 0
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c19k2Hz 7
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c230k4Hz 11
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c2400Hz 4
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c28k8Hz 8
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c300Hz 1
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c3125kHz 14
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c460k8Hz 12
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c4800Hz 5
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c57k6Hz 9
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c600Hz 2
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c921k6Hz 13
+#define R_SYNC_SERIAL1_CTRL__tr_baud__tr_baud__c9600Hz 6
+#define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__off 0
+#define R_SYNC_SERIAL1_CTRL__dma_enable__dma_enable__on 1
+#define R_SYNC_SERIAL1_CTRL__mode__mode__master_bidir 4
+#define R_SYNC_SERIAL1_CTRL__mode__mode__master_input 2
+#define R_SYNC_SERIAL1_CTRL__mode__mode__master_output 0
+#define R_SYNC_SERIAL1_CTRL__mode__mode__slave_bidir 5
+#define R_SYNC_SERIAL1_CTRL__mode__mode__slave_input 3
+#define R_SYNC_SERIAL1_CTRL__mode__mode__slave_output 1
+#define R_SYNC_SERIAL1_CTRL__error__error__ignore 1
+#define R_SYNC_SERIAL1_CTRL__error__error__normal 0
+#define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__disable 0
+#define R_SYNC_SERIAL1_CTRL__rec_enable__rec_enable__enable 1
+#define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__early 1
+#define R_SYNC_SERIAL1_CTRL__f_synctype__f_synctype__normal 0
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__bit 0
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__extended 2
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__f_syncsize__word 1
+#define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__off 1
+#define R_SYNC_SERIAL1_CTRL__f_sync__f_sync__on 0
+#define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__gated 1
+#define R_SYNC_SERIAL1_CTRL__clk_mode__clk_mode__normal 0
+#define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__running 0
+#define R_SYNC_SERIAL1_CTRL__clk_halt__clk_halt__stopped 1
+#define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__lsb 0
+#define R_SYNC_SERIAL1_CTRL__bitorder__bitorder__msb 1
+#define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__disable 0
+#define R_SYNC_SERIAL1_CTRL__tr_enable__tr_enable__enable 1
+#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size12bit 1
+#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size16bit 2
+#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size24bit 3
+#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size32bit 4
+#define R_SYNC_SERIAL1_CTRL__wordsize__wordsize__size8bit 0
+#define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__lmt_0 1
+#define R_SYNC_SERIAL1_CTRL__buf_empty__buf_empty__lmt_8 0
+#define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__lmt_32 0
+#define R_SYNC_SERIAL1_CTRL__buf_full__buf_full__lmt_8 1
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__disabled 0
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__flow_ctrl__enabled 1
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__neg 1
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__clk_polarity__pos 0
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__inverted 1
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__frame_polarity__normal 0
+#define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__inverted 1
+#define R_SYNC_SERIAL1_CTRL__status_polarity__status_polarity__normal 0
+#define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__inverted 1
+#define R_SYNC_SERIAL1_CTRL__clk_driver__clk_driver__normal 0
+#define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__inverted 1
+#define R_SYNC_SERIAL1_CTRL__frame_driver__frame_driver__normal 0
+#define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__inverted 1
+#define R_SYNC_SERIAL1_CTRL__status_driver__status_driver__normal 0
+#define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__high 1
+#define R_SYNC_SERIAL1_CTRL__def_out0__def_out0__low 0
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_REC_BYTE
+ * - type: RO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL1_REC_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000006c)
+#define R_SYNC_SERIAL1_REC_BYTE__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL1_REC_BYTE__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL1_REC_BYTE__TYPECAST REG_TYPECAST_BYTE
+#define R_SYNC_SERIAL1_REC_BYTE__TYPE (REG_BYTE)
+#define R_SYNC_SERIAL1_REC_BYTE__GET REG_GET_RO
+#define R_SYNC_SERIAL1_REC_BYTE__IGET REG_IGET_RO
+#define R_SYNC_SERIAL1_REC_BYTE__SET REG_SET_RO
+#define R_SYNC_SERIAL1_REC_BYTE__ISET REG_ISET_RO
+#define R_SYNC_SERIAL1_REC_BYTE__SET_VAL REG_SET_VAL_RO
+#define R_SYNC_SERIAL1_REC_BYTE__EQL REG_EQL_RO
+#define R_SYNC_SERIAL1_REC_BYTE__IEQL REG_IEQL_RO
+#define R_SYNC_SERIAL1_REC_BYTE__RD REG_RD_RO
+#define R_SYNC_SERIAL1_REC_BYTE__IRD REG_IRD_RO
+#define R_SYNC_SERIAL1_REC_BYTE__WR REG_WR_RO
+#define R_SYNC_SERIAL1_REC_BYTE__IWR REG_IWR_RO
+
+#define R_SYNC_SERIAL1_REC_BYTE__READ(addr) \
+ (*(addr))
+
+#define R_SYNC_SERIAL1_REC_BYTE__data_in__data_in__MASK 0x000000ffU
+
+#define R_SYNC_SERIAL1_REC_BYTE__data_in__MAX 0xff
+
+#define R_SYNC_SERIAL1_REC_BYTE__data_in__MIN 0
+
+#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0
+
+#define R_SYNC_SERIAL1_REC_BYTE__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_REC_DATA
+ * - type: RO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL1_REC_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000006c)
+#define R_SYNC_SERIAL1_REC_DATA__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL1_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL1_REC_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL1_REC_DATA__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL1_REC_DATA__GET REG_GET_RO
+#define R_SYNC_SERIAL1_REC_DATA__IGET REG_IGET_RO
+#define R_SYNC_SERIAL1_REC_DATA__SET REG_SET_RO
+#define R_SYNC_SERIAL1_REC_DATA__ISET REG_ISET_RO
+#define R_SYNC_SERIAL1_REC_DATA__SET_VAL REG_SET_VAL_RO
+#define R_SYNC_SERIAL1_REC_DATA__EQL REG_EQL_RO
+#define R_SYNC_SERIAL1_REC_DATA__IEQL REG_IEQL_RO
+#define R_SYNC_SERIAL1_REC_DATA__RD REG_RD_RO
+#define R_SYNC_SERIAL1_REC_DATA__IRD REG_IRD_RO
+#define R_SYNC_SERIAL1_REC_DATA__WR REG_WR_RO
+#define R_SYNC_SERIAL1_REC_DATA__IWR REG_IWR_RO
+
+#define R_SYNC_SERIAL1_REC_DATA__READ(addr) \
+ (*(addr))
+
+#define R_SYNC_SERIAL1_REC_DATA__data_in__data_in__MASK 0xffffffffU
+
+#define R_SYNC_SERIAL1_REC_DATA__data_in__MAX 0xffffffff
+
+#define R_SYNC_SERIAL1_REC_DATA__data_in__MIN 0
+
+#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0
+
+#define R_SYNC_SERIAL1_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_REC_WORD
+ * - type: RO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL1_REC_WORD__ADDR (REG_TYPECAST_UWORD 0xb000006c)
+#define R_SYNC_SERIAL1_REC_WORD__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL1_REC_WORD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL1_REC_WORD__TYPECAST REG_TYPECAST_UWORD
+#define R_SYNC_SERIAL1_REC_WORD__TYPE (REG_UWORD)
+#define R_SYNC_SERIAL1_REC_WORD__GET REG_GET_RO
+#define R_SYNC_SERIAL1_REC_WORD__IGET REG_IGET_RO
+#define R_SYNC_SERIAL1_REC_WORD__SET REG_SET_RO
+#define R_SYNC_SERIAL1_REC_WORD__ISET REG_ISET_RO
+#define R_SYNC_SERIAL1_REC_WORD__SET_VAL REG_SET_VAL_RO
+#define R_SYNC_SERIAL1_REC_WORD__EQL REG_EQL_RO
+#define R_SYNC_SERIAL1_REC_WORD__IEQL REG_IEQL_RO
+#define R_SYNC_SERIAL1_REC_WORD__RD REG_RD_RO
+#define R_SYNC_SERIAL1_REC_WORD__IRD REG_IRD_RO
+#define R_SYNC_SERIAL1_REC_WORD__WR REG_WR_RO
+#define R_SYNC_SERIAL1_REC_WORD__IWR REG_IWR_RO
+
+#define R_SYNC_SERIAL1_REC_WORD__READ(addr) \
+ (*(addr))
+
+#define R_SYNC_SERIAL1_REC_WORD__data_in__data_in__MASK 0x0000ffffU
+
+#define R_SYNC_SERIAL1_REC_WORD__data_in__MAX 0xffff
+
+#define R_SYNC_SERIAL1_REC_WORD__data_in__MIN 0
+
+#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0
+
+#define R_SYNC_SERIAL1_REC_WORD__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_STATUS
+ * - type: RO
+ * - addr: 0xb0000068
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL1_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000068)
+#define R_SYNC_SERIAL1_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL1_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL1_STATUS__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL1_STATUS__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL1_STATUS__GET REG_GET_RO
+#define R_SYNC_SERIAL1_STATUS__IGET REG_IGET_RO
+#define R_SYNC_SERIAL1_STATUS__SET REG_SET_RO
+#define R_SYNC_SERIAL1_STATUS__ISET REG_ISET_RO
+#define R_SYNC_SERIAL1_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SYNC_SERIAL1_STATUS__EQL REG_EQL_RO
+#define R_SYNC_SERIAL1_STATUS__IEQL REG_IEQL_RO
+#define R_SYNC_SERIAL1_STATUS__RD REG_RD_RO
+#define R_SYNC_SERIAL1_STATUS__IRD REG_IRD_RO
+#define R_SYNC_SERIAL1_STATUS__WR REG_WR_RO
+#define R_SYNC_SERIAL1_STATUS__IWR REG_IWR_RO
+
+#define R_SYNC_SERIAL1_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__MASK 0x00008000U
+#define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__MASK 0x00004000U
+#define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__MASK 0x00002000U
+#define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__MASK 0x00001000U
+#define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__MASK 0x00000800U
+#define R_SYNC_SERIAL1_STATUS__underflow__underflow__MASK 0x00000400U
+#define R_SYNC_SERIAL1_STATUS__overrun__overrun__MASK 0x00000200U
+#define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__MASK 0x00000100U
+#define R_SYNC_SERIAL1_STATUS__data__data__MASK 0x000000ffU
+
+#define R_SYNC_SERIAL1_STATUS__rec_status__MAX 0x1
+#define R_SYNC_SERIAL1_STATUS__tr_empty__MAX 0x1
+#define R_SYNC_SERIAL1_STATUS__tr_ready__MAX 0x1
+#define R_SYNC_SERIAL1_STATUS__pin_1__MAX 0x1
+#define R_SYNC_SERIAL1_STATUS__pin_0__MAX 0x1
+#define R_SYNC_SERIAL1_STATUS__underflow__MAX 0x1
+#define R_SYNC_SERIAL1_STATUS__overrun__MAX 0x1
+#define R_SYNC_SERIAL1_STATUS__data_avail__MAX 0x1
+#define R_SYNC_SERIAL1_STATUS__data__MAX 0xff
+
+#define R_SYNC_SERIAL1_STATUS__rec_status__MIN 0
+#define R_SYNC_SERIAL1_STATUS__tr_empty__MIN 0
+#define R_SYNC_SERIAL1_STATUS__tr_ready__MIN 0
+#define R_SYNC_SERIAL1_STATUS__pin_1__MIN 0
+#define R_SYNC_SERIAL1_STATUS__pin_0__MIN 0
+#define R_SYNC_SERIAL1_STATUS__underflow__MIN 0
+#define R_SYNC_SERIAL1_STATUS__overrun__MIN 0
+#define R_SYNC_SERIAL1_STATUS__data_avail__MIN 0
+#define R_SYNC_SERIAL1_STATUS__data__MIN 0
+
+#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15
+#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14
+#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13
+#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12
+#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11
+#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10
+#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9
+#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8
+#define R_SYNC_SERIAL1_STATUS__data__BITNR 0
+
+#define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_STATUS__underflow__underflow__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_STATUS__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL1_STATUS__data__data__VAL REG_VAL_VAL
+
+#define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__idle 1
+#define R_SYNC_SERIAL1_STATUS__rec_status__rec_status__running 0
+#define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__empty 1
+#define R_SYNC_SERIAL1_STATUS__tr_empty__tr_empty__not_empty 0
+#define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__full 0
+#define R_SYNC_SERIAL1_STATUS__tr_ready__tr_ready__ready 1
+#define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__high 1
+#define R_SYNC_SERIAL1_STATUS__pin_1__pin_1__low 0
+#define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__high 1
+#define R_SYNC_SERIAL1_STATUS__pin_0__pin_0__low 0
+#define R_SYNC_SERIAL1_STATUS__underflow__underflow__no 0
+#define R_SYNC_SERIAL1_STATUS__underflow__underflow__yes 1
+#define R_SYNC_SERIAL1_STATUS__overrun__overrun__no 0
+#define R_SYNC_SERIAL1_STATUS__overrun__overrun__yes 1
+#define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__no 0
+#define R_SYNC_SERIAL1_STATUS__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_TR_BYTE
+ * - type: WO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL1_TR_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000006c)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL1_TR_BYTE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_XOFF + 0))
+#define R_SYNC_SERIAL1_TR_BYTE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL1_TR_BYTE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL1_TR_BYTE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL1_TR_BYTE__STYPECAST REG_STYPECAST_BYTE
+#define R_SYNC_SERIAL1_TR_BYTE__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL1_TR_BYTE__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL1_TR_BYTE__TYPECAST REG_TYPECAST_BYTE
+#define R_SYNC_SERIAL1_TR_BYTE__TYPE (REG_BYTE)
+#define R_SYNC_SERIAL1_TR_BYTE__GET REG_GET_WO
+#define R_SYNC_SERIAL1_TR_BYTE__IGET REG_IGET_WO
+#define R_SYNC_SERIAL1_TR_BYTE__SET REG_SET_WO
+#define R_SYNC_SERIAL1_TR_BYTE__ISET REG_ISET_WO
+#define R_SYNC_SERIAL1_TR_BYTE__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL1_TR_BYTE__EQL REG_EQL_WO
+#define R_SYNC_SERIAL1_TR_BYTE__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL1_TR_BYTE__RD REG_RD_WO
+#define R_SYNC_SERIAL1_TR_BYTE__IRD REG_IRD_WO
+#define R_SYNC_SERIAL1_TR_BYTE__WR REG_WR_WO
+#define R_SYNC_SERIAL1_TR_BYTE__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL1_TR_BYTE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL1_TR_BYTE__data_out__data_out__MASK 0x000000ffU
+
+#define R_SYNC_SERIAL1_TR_BYTE__data_out__MAX 0xff
+
+#define R_SYNC_SERIAL1_TR_BYTE__data_out__MIN 0
+
+#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0
+
+#define R_SYNC_SERIAL1_TR_BYTE__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_TR_DATA
+ * - type: WO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL1_TR_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000006c)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0))
+#define R_SYNC_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL1_TR_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL1_TR_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL1_TR_DATA__STYPECAST REG_STYPECAST_UDWORD
+#define R_SYNC_SERIAL1_TR_DATA__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL1_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL1_TR_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL1_TR_DATA__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL1_TR_DATA__GET REG_GET_WO
+#define R_SYNC_SERIAL1_TR_DATA__IGET REG_IGET_WO
+#define R_SYNC_SERIAL1_TR_DATA__SET REG_SET_WO
+#define R_SYNC_SERIAL1_TR_DATA__ISET REG_ISET_WO
+#define R_SYNC_SERIAL1_TR_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL1_TR_DATA__EQL REG_EQL_WO
+#define R_SYNC_SERIAL1_TR_DATA__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL1_TR_DATA__RD REG_RD_WO
+#define R_SYNC_SERIAL1_TR_DATA__IRD REG_IRD_WO
+#define R_SYNC_SERIAL1_TR_DATA__WR REG_WR_WO
+#define R_SYNC_SERIAL1_TR_DATA__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL1_TR_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL1_TR_DATA__data_out__data_out__MASK 0xffffffffU
+
+#define R_SYNC_SERIAL1_TR_DATA__data_out__MAX 0xffffffff
+
+#define R_SYNC_SERIAL1_TR_DATA__data_out__MIN 0
+
+#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0
+
+#define R_SYNC_SERIAL1_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL1_TR_WORD
+ * - type: WO
+ * - addr: 0xb000006c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL1_TR_WORD__ADDR (REG_TYPECAST_UWORD 0xb000006c)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL1_TR_WORD__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_SERIAL1_XOFF + 0))
+#define R_SYNC_SERIAL1_TR_WORD__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_SERIAL1_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL1_TR_WORD__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL1_TR_WORD__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL1_TR_WORD__STYPECAST REG_STYPECAST_UWORD
+#define R_SYNC_SERIAL1_TR_WORD__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL1_TR_WORD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL1_TR_WORD__TYPECAST REG_TYPECAST_UWORD
+#define R_SYNC_SERIAL1_TR_WORD__TYPE (REG_UWORD)
+#define R_SYNC_SERIAL1_TR_WORD__GET REG_GET_WO
+#define R_SYNC_SERIAL1_TR_WORD__IGET REG_IGET_WO
+#define R_SYNC_SERIAL1_TR_WORD__SET REG_SET_WO
+#define R_SYNC_SERIAL1_TR_WORD__ISET REG_ISET_WO
+#define R_SYNC_SERIAL1_TR_WORD__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL1_TR_WORD__EQL REG_EQL_WO
+#define R_SYNC_SERIAL1_TR_WORD__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL1_TR_WORD__RD REG_RD_WO
+#define R_SYNC_SERIAL1_TR_WORD__IRD REG_IRD_WO
+#define R_SYNC_SERIAL1_TR_WORD__WR REG_WR_WO
+#define R_SYNC_SERIAL1_TR_WORD__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL1_TR_WORD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL1_TR_WORD__data_out__data_out__MASK 0x0000ffffU
+
+#define R_SYNC_SERIAL1_TR_WORD__data_out__MAX 0xffff
+
+#define R_SYNC_SERIAL1_TR_WORD__data_out__MIN 0
+
+#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0
+
+#define R_SYNC_SERIAL1_TR_WORD__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_CTRL
+ * - type: WO
+ * - addr: 0xb0000078
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL3_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000078)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_CTRL + 0))
+#define R_SYNC_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL3_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL3_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL3_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_SYNC_SERIAL3_CTRL__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL3_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL3_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL3_CTRL__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL3_CTRL__GET REG_GET_WO
+#define R_SYNC_SERIAL3_CTRL__IGET REG_IGET_WO
+#define R_SYNC_SERIAL3_CTRL__SET REG_SET_WO
+#define R_SYNC_SERIAL3_CTRL__ISET REG_ISET_WO
+#define R_SYNC_SERIAL3_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL3_CTRL__EQL REG_EQL_WO
+#define R_SYNC_SERIAL3_CTRL__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL3_CTRL__RD REG_RD_WO
+#define R_SYNC_SERIAL3_CTRL__IRD REG_IRD_WO
+#define R_SYNC_SERIAL3_CTRL__WR REG_WR_WO
+#define R_SYNC_SERIAL3_CTRL__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL3_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__MASK 0xf0000000U
+#define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__MASK 0x08000000U
+#define R_SYNC_SERIAL3_CTRL__mode__mode__MASK 0x07000000U
+#define R_SYNC_SERIAL3_CTRL__error__error__MASK 0x00800000U
+#define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__MASK 0x00400000U
+#define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__MASK 0x00200000U
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__MASK 0x00180000U
+#define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__MASK 0x00040000U
+#define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__MASK 0x00020000U
+#define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__MASK 0x00010000U
+#define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__MASK 0x00008000U
+#define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__MASK 0x00004000U
+#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__MASK 0x00003800U
+#define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__MASK 0x00000400U
+#define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__MASK 0x00000200U
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__MASK 0x00000100U
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__MASK 0x00000040U
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__MASK 0x00000020U
+#define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__MASK 0x00000010U
+#define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__MASK 0x00000008U
+#define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__MASK 0x00000004U
+#define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__MASK 0x00000002U
+#define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__MASK 0x00000001U
+
+#define R_SYNC_SERIAL3_CTRL__tr_baud__MAX 0xf
+#define R_SYNC_SERIAL3_CTRL__dma_enable__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__mode__MAX 0x7
+#define R_SYNC_SERIAL3_CTRL__error__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__rec_enable__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__f_synctype__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__MAX 0x3
+#define R_SYNC_SERIAL3_CTRL__f_sync__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__clk_mode__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__clk_halt__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__bitorder__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__tr_enable__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__wordsize__MAX 0x7
+#define R_SYNC_SERIAL3_CTRL__buf_empty__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__buf_full__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__status_polarity__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__clk_driver__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__frame_driver__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__status_driver__MAX 0x1
+#define R_SYNC_SERIAL3_CTRL__def_out0__MAX 0x1
+
+#define R_SYNC_SERIAL3_CTRL__tr_baud__MIN 0
+#define R_SYNC_SERIAL3_CTRL__dma_enable__MIN 0
+#define R_SYNC_SERIAL3_CTRL__mode__MIN 0
+#define R_SYNC_SERIAL3_CTRL__error__MIN 0
+#define R_SYNC_SERIAL3_CTRL__rec_enable__MIN 0
+#define R_SYNC_SERIAL3_CTRL__f_synctype__MIN 0
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__MIN 0
+#define R_SYNC_SERIAL3_CTRL__f_sync__MIN 0
+#define R_SYNC_SERIAL3_CTRL__clk_mode__MIN 0
+#define R_SYNC_SERIAL3_CTRL__clk_halt__MIN 0
+#define R_SYNC_SERIAL3_CTRL__bitorder__MIN 0
+#define R_SYNC_SERIAL3_CTRL__tr_enable__MIN 0
+#define R_SYNC_SERIAL3_CTRL__wordsize__MIN 0
+#define R_SYNC_SERIAL3_CTRL__buf_empty__MIN 0
+#define R_SYNC_SERIAL3_CTRL__buf_full__MIN 0
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__MIN 0
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__MIN 0
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__MIN 0
+#define R_SYNC_SERIAL3_CTRL__status_polarity__MIN 0
+#define R_SYNC_SERIAL3_CTRL__clk_driver__MIN 0
+#define R_SYNC_SERIAL3_CTRL__frame_driver__MIN 0
+#define R_SYNC_SERIAL3_CTRL__status_driver__MIN 0
+#define R_SYNC_SERIAL3_CTRL__def_out0__MIN 0
+
+#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28
+#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27
+#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24
+#define R_SYNC_SERIAL3_CTRL__error__BITNR 23
+#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22
+#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19
+#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18
+#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17
+#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16
+#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15
+#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14
+#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11
+#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10
+#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5
+#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4
+#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3
+#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2
+#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1
+#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0
+
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__mode__mode__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__error__error__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__VAL REG_VAL_ENUM
+
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c115k2Hz 10
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c1200Hz 3
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c150Hz 0
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c19k2Hz 7
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c230k4Hz 11
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c2400Hz 4
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c28k8Hz 8
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c300Hz 1
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c3125kHz 14
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c460k8Hz 12
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c4800Hz 5
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c57k6Hz 9
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c600Hz 2
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c921k6Hz 13
+#define R_SYNC_SERIAL3_CTRL__tr_baud__tr_baud__c9600Hz 6
+#define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__off 0
+#define R_SYNC_SERIAL3_CTRL__dma_enable__dma_enable__on 1
+#define R_SYNC_SERIAL3_CTRL__mode__mode__master_bidir 4
+#define R_SYNC_SERIAL3_CTRL__mode__mode__master_input 2
+#define R_SYNC_SERIAL3_CTRL__mode__mode__master_output 0
+#define R_SYNC_SERIAL3_CTRL__mode__mode__slave_bidir 5
+#define R_SYNC_SERIAL3_CTRL__mode__mode__slave_input 3
+#define R_SYNC_SERIAL3_CTRL__mode__mode__slave_output 1
+#define R_SYNC_SERIAL3_CTRL__error__error__ignore 1
+#define R_SYNC_SERIAL3_CTRL__error__error__normal 0
+#define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__disable 0
+#define R_SYNC_SERIAL3_CTRL__rec_enable__rec_enable__enable 1
+#define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__early 1
+#define R_SYNC_SERIAL3_CTRL__f_synctype__f_synctype__normal 0
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__bit 0
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__extended 2
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__f_syncsize__word 1
+#define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__off 1
+#define R_SYNC_SERIAL3_CTRL__f_sync__f_sync__on 0
+#define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__gated 1
+#define R_SYNC_SERIAL3_CTRL__clk_mode__clk_mode__normal 0
+#define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__running 0
+#define R_SYNC_SERIAL3_CTRL__clk_halt__clk_halt__stopped 1
+#define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__lsb 0
+#define R_SYNC_SERIAL3_CTRL__bitorder__bitorder__msb 1
+#define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__disable 0
+#define R_SYNC_SERIAL3_CTRL__tr_enable__tr_enable__enable 1
+#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size12bit 1
+#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size16bit 2
+#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size24bit 3
+#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size32bit 4
+#define R_SYNC_SERIAL3_CTRL__wordsize__wordsize__size8bit 0
+#define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__lmt_0 1
+#define R_SYNC_SERIAL3_CTRL__buf_empty__buf_empty__lmt_8 0
+#define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__lmt_32 0
+#define R_SYNC_SERIAL3_CTRL__buf_full__buf_full__lmt_8 1
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__disabled 0
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__flow_ctrl__enabled 1
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__neg 1
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__clk_polarity__pos 0
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__inverted 1
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__frame_polarity__normal 0
+#define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__inverted 1
+#define R_SYNC_SERIAL3_CTRL__status_polarity__status_polarity__normal 0
+#define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__inverted 1
+#define R_SYNC_SERIAL3_CTRL__clk_driver__clk_driver__normal 0
+#define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__inverted 1
+#define R_SYNC_SERIAL3_CTRL__frame_driver__frame_driver__normal 0
+#define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__inverted 1
+#define R_SYNC_SERIAL3_CTRL__status_driver__status_driver__normal 0
+#define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__high 1
+#define R_SYNC_SERIAL3_CTRL__def_out0__def_out0__low 0
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_REC_BYTE
+ * - type: RO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL3_REC_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000007c)
+#define R_SYNC_SERIAL3_REC_BYTE__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL3_REC_BYTE__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL3_REC_BYTE__TYPECAST REG_TYPECAST_BYTE
+#define R_SYNC_SERIAL3_REC_BYTE__TYPE (REG_BYTE)
+#define R_SYNC_SERIAL3_REC_BYTE__GET REG_GET_RO
+#define R_SYNC_SERIAL3_REC_BYTE__IGET REG_IGET_RO
+#define R_SYNC_SERIAL3_REC_BYTE__SET REG_SET_RO
+#define R_SYNC_SERIAL3_REC_BYTE__ISET REG_ISET_RO
+#define R_SYNC_SERIAL3_REC_BYTE__SET_VAL REG_SET_VAL_RO
+#define R_SYNC_SERIAL3_REC_BYTE__EQL REG_EQL_RO
+#define R_SYNC_SERIAL3_REC_BYTE__IEQL REG_IEQL_RO
+#define R_SYNC_SERIAL3_REC_BYTE__RD REG_RD_RO
+#define R_SYNC_SERIAL3_REC_BYTE__IRD REG_IRD_RO
+#define R_SYNC_SERIAL3_REC_BYTE__WR REG_WR_RO
+#define R_SYNC_SERIAL3_REC_BYTE__IWR REG_IWR_RO
+
+#define R_SYNC_SERIAL3_REC_BYTE__READ(addr) \
+ (*(addr))
+
+#define R_SYNC_SERIAL3_REC_BYTE__data_in__data_in__MASK 0x000000ffU
+
+#define R_SYNC_SERIAL3_REC_BYTE__data_in__MAX 0xff
+
+#define R_SYNC_SERIAL3_REC_BYTE__data_in__MIN 0
+
+#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0
+
+#define R_SYNC_SERIAL3_REC_BYTE__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_REC_DATA
+ * - type: RO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL3_REC_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000007c)
+#define R_SYNC_SERIAL3_REC_DATA__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL3_REC_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL3_REC_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL3_REC_DATA__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL3_REC_DATA__GET REG_GET_RO
+#define R_SYNC_SERIAL3_REC_DATA__IGET REG_IGET_RO
+#define R_SYNC_SERIAL3_REC_DATA__SET REG_SET_RO
+#define R_SYNC_SERIAL3_REC_DATA__ISET REG_ISET_RO
+#define R_SYNC_SERIAL3_REC_DATA__SET_VAL REG_SET_VAL_RO
+#define R_SYNC_SERIAL3_REC_DATA__EQL REG_EQL_RO
+#define R_SYNC_SERIAL3_REC_DATA__IEQL REG_IEQL_RO
+#define R_SYNC_SERIAL3_REC_DATA__RD REG_RD_RO
+#define R_SYNC_SERIAL3_REC_DATA__IRD REG_IRD_RO
+#define R_SYNC_SERIAL3_REC_DATA__WR REG_WR_RO
+#define R_SYNC_SERIAL3_REC_DATA__IWR REG_IWR_RO
+
+#define R_SYNC_SERIAL3_REC_DATA__READ(addr) \
+ (*(addr))
+
+#define R_SYNC_SERIAL3_REC_DATA__data_in__data_in__MASK 0xffffffffU
+
+#define R_SYNC_SERIAL3_REC_DATA__data_in__MAX 0xffffffff
+
+#define R_SYNC_SERIAL3_REC_DATA__data_in__MIN 0
+
+#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0
+
+#define R_SYNC_SERIAL3_REC_DATA__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_REC_WORD
+ * - type: RO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL3_REC_WORD__ADDR (REG_TYPECAST_UWORD 0xb000007c)
+#define R_SYNC_SERIAL3_REC_WORD__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL3_REC_WORD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL3_REC_WORD__TYPECAST REG_TYPECAST_UWORD
+#define R_SYNC_SERIAL3_REC_WORD__TYPE (REG_UWORD)
+#define R_SYNC_SERIAL3_REC_WORD__GET REG_GET_RO
+#define R_SYNC_SERIAL3_REC_WORD__IGET REG_IGET_RO
+#define R_SYNC_SERIAL3_REC_WORD__SET REG_SET_RO
+#define R_SYNC_SERIAL3_REC_WORD__ISET REG_ISET_RO
+#define R_SYNC_SERIAL3_REC_WORD__SET_VAL REG_SET_VAL_RO
+#define R_SYNC_SERIAL3_REC_WORD__EQL REG_EQL_RO
+#define R_SYNC_SERIAL3_REC_WORD__IEQL REG_IEQL_RO
+#define R_SYNC_SERIAL3_REC_WORD__RD REG_RD_RO
+#define R_SYNC_SERIAL3_REC_WORD__IRD REG_IRD_RO
+#define R_SYNC_SERIAL3_REC_WORD__WR REG_WR_RO
+#define R_SYNC_SERIAL3_REC_WORD__IWR REG_IWR_RO
+
+#define R_SYNC_SERIAL3_REC_WORD__READ(addr) \
+ (*(addr))
+
+#define R_SYNC_SERIAL3_REC_WORD__data_in__data_in__MASK 0x0000ffffU
+
+#define R_SYNC_SERIAL3_REC_WORD__data_in__MAX 0xffff
+
+#define R_SYNC_SERIAL3_REC_WORD__data_in__MIN 0
+
+#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0
+
+#define R_SYNC_SERIAL3_REC_WORD__data_in__data_in__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_STATUS
+ * - type: RO
+ * - addr: 0xb0000078
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL3_STATUS__ADDR (REG_TYPECAST_UDWORD 0xb0000078)
+#define R_SYNC_SERIAL3_STATUS__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL3_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL3_STATUS__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL3_STATUS__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL3_STATUS__GET REG_GET_RO
+#define R_SYNC_SERIAL3_STATUS__IGET REG_IGET_RO
+#define R_SYNC_SERIAL3_STATUS__SET REG_SET_RO
+#define R_SYNC_SERIAL3_STATUS__ISET REG_ISET_RO
+#define R_SYNC_SERIAL3_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_SYNC_SERIAL3_STATUS__EQL REG_EQL_RO
+#define R_SYNC_SERIAL3_STATUS__IEQL REG_IEQL_RO
+#define R_SYNC_SERIAL3_STATUS__RD REG_RD_RO
+#define R_SYNC_SERIAL3_STATUS__IRD REG_IRD_RO
+#define R_SYNC_SERIAL3_STATUS__WR REG_WR_RO
+#define R_SYNC_SERIAL3_STATUS__IWR REG_IWR_RO
+
+#define R_SYNC_SERIAL3_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__MASK 0x00008000U
+#define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__MASK 0x00004000U
+#define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__MASK 0x00002000U
+#define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__MASK 0x00001000U
+#define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__MASK 0x00000800U
+#define R_SYNC_SERIAL3_STATUS__underflow__underflow__MASK 0x00000400U
+#define R_SYNC_SERIAL3_STATUS__overrun__overrun__MASK 0x00000200U
+#define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__MASK 0x00000100U
+#define R_SYNC_SERIAL3_STATUS__data__data__MASK 0x000000ffU
+
+#define R_SYNC_SERIAL3_STATUS__rec_status__MAX 0x1
+#define R_SYNC_SERIAL3_STATUS__tr_empty__MAX 0x1
+#define R_SYNC_SERIAL3_STATUS__tr_ready__MAX 0x1
+#define R_SYNC_SERIAL3_STATUS__pin_1__MAX 0x1
+#define R_SYNC_SERIAL3_STATUS__pin_0__MAX 0x1
+#define R_SYNC_SERIAL3_STATUS__underflow__MAX 0x1
+#define R_SYNC_SERIAL3_STATUS__overrun__MAX 0x1
+#define R_SYNC_SERIAL3_STATUS__data_avail__MAX 0x1
+#define R_SYNC_SERIAL3_STATUS__data__MAX 0xff
+
+#define R_SYNC_SERIAL3_STATUS__rec_status__MIN 0
+#define R_SYNC_SERIAL3_STATUS__tr_empty__MIN 0
+#define R_SYNC_SERIAL3_STATUS__tr_ready__MIN 0
+#define R_SYNC_SERIAL3_STATUS__pin_1__MIN 0
+#define R_SYNC_SERIAL3_STATUS__pin_0__MIN 0
+#define R_SYNC_SERIAL3_STATUS__underflow__MIN 0
+#define R_SYNC_SERIAL3_STATUS__overrun__MIN 0
+#define R_SYNC_SERIAL3_STATUS__data_avail__MIN 0
+#define R_SYNC_SERIAL3_STATUS__data__MIN 0
+
+#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15
+#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14
+#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13
+#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12
+#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11
+#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10
+#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9
+#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8
+#define R_SYNC_SERIAL3_STATUS__data__BITNR 0
+
+#define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_STATUS__underflow__underflow__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_STATUS__overrun__overrun__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL3_STATUS__data__data__VAL REG_VAL_VAL
+
+#define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__idle 1
+#define R_SYNC_SERIAL3_STATUS__rec_status__rec_status__running 0
+#define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__empty 1
+#define R_SYNC_SERIAL3_STATUS__tr_empty__tr_empty__not_empty 0
+#define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__full 0
+#define R_SYNC_SERIAL3_STATUS__tr_ready__tr_ready__ready 1
+#define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__high 1
+#define R_SYNC_SERIAL3_STATUS__pin_1__pin_1__low 0
+#define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__high 1
+#define R_SYNC_SERIAL3_STATUS__pin_0__pin_0__low 0
+#define R_SYNC_SERIAL3_STATUS__underflow__underflow__no 0
+#define R_SYNC_SERIAL3_STATUS__underflow__underflow__yes 1
+#define R_SYNC_SERIAL3_STATUS__overrun__overrun__no 0
+#define R_SYNC_SERIAL3_STATUS__overrun__overrun__yes 1
+#define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__no 0
+#define R_SYNC_SERIAL3_STATUS__data_avail__data_avail__yes 1
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_TR_BYTE
+ * - type: WO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL3_TR_BYTE__ADDR (REG_TYPECAST_BYTE 0xb000007c)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL3_TR_BYTE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL3_XOFF + 0))
+#define R_SYNC_SERIAL3_TR_BYTE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL3_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL3_TR_BYTE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL3_TR_BYTE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL3_TR_BYTE__STYPECAST REG_STYPECAST_BYTE
+#define R_SYNC_SERIAL3_TR_BYTE__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL3_TR_BYTE__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL3_TR_BYTE__TYPECAST REG_TYPECAST_BYTE
+#define R_SYNC_SERIAL3_TR_BYTE__TYPE (REG_BYTE)
+#define R_SYNC_SERIAL3_TR_BYTE__GET REG_GET_WO
+#define R_SYNC_SERIAL3_TR_BYTE__IGET REG_IGET_WO
+#define R_SYNC_SERIAL3_TR_BYTE__SET REG_SET_WO
+#define R_SYNC_SERIAL3_TR_BYTE__ISET REG_ISET_WO
+#define R_SYNC_SERIAL3_TR_BYTE__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL3_TR_BYTE__EQL REG_EQL_WO
+#define R_SYNC_SERIAL3_TR_BYTE__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL3_TR_BYTE__RD REG_RD_WO
+#define R_SYNC_SERIAL3_TR_BYTE__IRD REG_IRD_WO
+#define R_SYNC_SERIAL3_TR_BYTE__WR REG_WR_WO
+#define R_SYNC_SERIAL3_TR_BYTE__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL3_TR_BYTE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL3_TR_BYTE__data_out__data_out__MASK 0x000000ffU
+
+#define R_SYNC_SERIAL3_TR_BYTE__data_out__MAX 0xff
+
+#define R_SYNC_SERIAL3_TR_BYTE__data_out__MIN 0
+
+#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0
+
+#define R_SYNC_SERIAL3_TR_BYTE__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_TR_DATA
+ * - type: WO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL3_TR_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000007c)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0))
+#define R_SYNC_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL3_TR_DATA__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL3_TR_DATA__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL3_TR_DATA__STYPECAST REG_STYPECAST_UDWORD
+#define R_SYNC_SERIAL3_TR_DATA__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL3_TR_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL3_TR_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL3_TR_DATA__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL3_TR_DATA__GET REG_GET_WO
+#define R_SYNC_SERIAL3_TR_DATA__IGET REG_IGET_WO
+#define R_SYNC_SERIAL3_TR_DATA__SET REG_SET_WO
+#define R_SYNC_SERIAL3_TR_DATA__ISET REG_ISET_WO
+#define R_SYNC_SERIAL3_TR_DATA__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL3_TR_DATA__EQL REG_EQL_WO
+#define R_SYNC_SERIAL3_TR_DATA__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL3_TR_DATA__RD REG_RD_WO
+#define R_SYNC_SERIAL3_TR_DATA__IRD REG_IRD_WO
+#define R_SYNC_SERIAL3_TR_DATA__WR REG_WR_WO
+#define R_SYNC_SERIAL3_TR_DATA__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL3_TR_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL3_TR_DATA__data_out__data_out__MASK 0xffffffffU
+
+#define R_SYNC_SERIAL3_TR_DATA__data_out__MAX 0xffffffff
+
+#define R_SYNC_SERIAL3_TR_DATA__data_out__MIN 0
+
+#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0
+
+#define R_SYNC_SERIAL3_TR_DATA__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL3_TR_WORD
+ * - type: WO
+ * - addr: 0xb000007c
+ * - group: Syncrounous serial port registers
+ */
+
+#if USE_GROUP__Syncrounous_serial_port_registers
+
+#define R_SYNC_SERIAL3_TR_WORD__ADDR (REG_TYPECAST_UWORD 0xb000007c)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL3_TR_WORD__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_SERIAL3_XOFF + 0))
+#define R_SYNC_SERIAL3_TR_WORD__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_SERIAL3_XOFF + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL3_TR_WORD__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL3_TR_WORD__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL3_TR_WORD__STYPECAST REG_STYPECAST_UWORD
+#define R_SYNC_SERIAL3_TR_WORD__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL3_TR_WORD__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL3_TR_WORD__TYPECAST REG_TYPECAST_UWORD
+#define R_SYNC_SERIAL3_TR_WORD__TYPE (REG_UWORD)
+#define R_SYNC_SERIAL3_TR_WORD__GET REG_GET_WO
+#define R_SYNC_SERIAL3_TR_WORD__IGET REG_IGET_WO
+#define R_SYNC_SERIAL3_TR_WORD__SET REG_SET_WO
+#define R_SYNC_SERIAL3_TR_WORD__ISET REG_ISET_WO
+#define R_SYNC_SERIAL3_TR_WORD__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL3_TR_WORD__EQL REG_EQL_WO
+#define R_SYNC_SERIAL3_TR_WORD__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL3_TR_WORD__RD REG_RD_WO
+#define R_SYNC_SERIAL3_TR_WORD__IRD REG_IRD_WO
+#define R_SYNC_SERIAL3_TR_WORD__WR REG_WR_WO
+#define R_SYNC_SERIAL3_TR_WORD__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL3_TR_WORD__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL3_TR_WORD__data_out__data_out__MASK 0x0000ffffU
+
+#define R_SYNC_SERIAL3_TR_WORD__data_out__MAX 0xffff
+
+#define R_SYNC_SERIAL3_TR_WORD__data_out__MIN 0
+
+#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0
+
+#define R_SYNC_SERIAL3_TR_WORD__data_out__data_out__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_SYNC_SERIAL_PRESCALE
+ * - type: WO
+ * - addr: 0xb00000f4
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_SYNC_SERIAL_PRESCALE__ADDR (REG_TYPECAST_UDWORD 0xb00000f4)
+
+#ifndef REG_NO_SHADOW
+#define R_SYNC_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_SYNC_SERIAL_PRESCALE + 0))
+#define R_SYNC_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_SYNC_SERIAL_PRESCALE + 0))
+#else /* REG_NO_SHADOW */
+#define R_SYNC_SERIAL_PRESCALE__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_SYNC_SERIAL_PRESCALE__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_SYNC_SERIAL_PRESCALE__STYPECAST REG_STYPECAST_UDWORD
+#define R_SYNC_SERIAL_PRESCALE__SVAL REG_SVAL_SHADOW
+#define R_SYNC_SERIAL_PRESCALE__SVAL_I REG_SVAL_I_SHADOW
+#define R_SYNC_SERIAL_PRESCALE__TYPECAST REG_TYPECAST_UDWORD
+#define R_SYNC_SERIAL_PRESCALE__TYPE (REG_UDWORD)
+#define R_SYNC_SERIAL_PRESCALE__GET REG_GET_WO
+#define R_SYNC_SERIAL_PRESCALE__IGET REG_IGET_WO
+#define R_SYNC_SERIAL_PRESCALE__SET REG_SET_WO
+#define R_SYNC_SERIAL_PRESCALE__ISET REG_ISET_WO
+#define R_SYNC_SERIAL_PRESCALE__SET_VAL REG_SET_VAL_WO
+#define R_SYNC_SERIAL_PRESCALE__EQL REG_EQL_WO
+#define R_SYNC_SERIAL_PRESCALE__IEQL REG_IEQL_WO
+#define R_SYNC_SERIAL_PRESCALE__RD REG_RD_WO
+#define R_SYNC_SERIAL_PRESCALE__IRD REG_IRD_WO
+#define R_SYNC_SERIAL_PRESCALE__WR REG_WR_WO
+#define R_SYNC_SERIAL_PRESCALE__IWR REG_IWR_WO
+
+#define R_SYNC_SERIAL_PRESCALE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__MASK 0x00800000U
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__MASK 0x00400000U
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__MASK 0x00200000U
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__MASK 0x00100000U
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__MASK 0x00070000U
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__MASK 0x00008000U
+#define R_SYNC_SERIAL_PRESCALE__frame_rate__frame_rate__MASK 0x00007800U
+#define R_SYNC_SERIAL_PRESCALE__word_rate__word_rate__MASK 0x000003ffU
+
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__MAX 0x1
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__MAX 0x1
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__MAX 0x1
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__MAX 0x1
+#define R_SYNC_SERIAL_PRESCALE__prescaler__MAX 0x7
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__MAX 0x1
+#define R_SYNC_SERIAL_PRESCALE__frame_rate__MAX 0xf
+#define R_SYNC_SERIAL_PRESCALE__word_rate__MAX 0x3ff
+
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__MIN 0
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__MIN 0
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__MIN 0
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__MIN 0
+#define R_SYNC_SERIAL_PRESCALE__prescaler__MIN 0
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__MIN 0
+#define R_SYNC_SERIAL_PRESCALE__frame_rate__MIN 0
+#define R_SYNC_SERIAL_PRESCALE__word_rate__MIN 0
+
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20
+#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15
+#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11
+#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0
+
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__VAL REG_VAL_ENUM
+#define R_SYNC_SERIAL_PRESCALE__frame_rate__frame_rate__VAL REG_VAL_VAL
+#define R_SYNC_SERIAL_PRESCALE__word_rate__word_rate__VAL REG_VAL_VAL
+
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__baudrate 1
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__clk_sel_u3__codec 0
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__external 0
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__word_stb_sel_u3__internal 1
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__baudrate 1
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__clk_sel_u1__codec 0
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__external 0
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__word_stb_sel_u1__internal 1
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div1 0
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div128 7
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div16 4
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div2 1
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div32 5
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div4 2
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div64 6
+#define R_SYNC_SERIAL_PRESCALE__prescaler__prescaler__div8 3
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__enabled 1
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__warp_mode__normal 0
+
+#endif
+
+/*
+ * R_TEST_MODE
+ * - type: WO
+ * - addr: 0xb00000fc
+ * - group: Test mode registers
+ */
+
+#if USE_GROUP__Test_mode_registers
+
+#define R_TEST_MODE__ADDR (REG_TYPECAST_UDWORD 0xb00000fc)
+
+#ifndef REG_NO_SHADOW
+#define R_TEST_MODE__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_TEST_MODE + 0))
+#define R_TEST_MODE__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_TEST_MODE + 0))
+#else /* REG_NO_SHADOW */
+#define R_TEST_MODE__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_TEST_MODE__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_TEST_MODE__STYPECAST REG_STYPECAST_UDWORD
+#define R_TEST_MODE__SVAL REG_SVAL_SHADOW
+#define R_TEST_MODE__SVAL_I REG_SVAL_I_SHADOW
+#define R_TEST_MODE__TYPECAST REG_TYPECAST_UDWORD
+#define R_TEST_MODE__TYPE (REG_UDWORD)
+#define R_TEST_MODE__GET REG_GET_WO
+#define R_TEST_MODE__IGET REG_IGET_WO
+#define R_TEST_MODE__SET REG_SET_WO
+#define R_TEST_MODE__ISET REG_ISET_WO
+#define R_TEST_MODE__SET_VAL REG_SET_VAL_WO
+#define R_TEST_MODE__EQL REG_EQL_WO
+#define R_TEST_MODE__IEQL REG_IEQL_WO
+#define R_TEST_MODE__RD REG_RD_WO
+#define R_TEST_MODE__IRD REG_IRD_WO
+#define R_TEST_MODE__WR REG_WR_WO
+#define R_TEST_MODE__IWR REG_IWR_WO
+
+#define R_TEST_MODE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_TEST_MODE__single_step__single_step__MASK 0x00080000U
+#define R_TEST_MODE__step_wr__step_wr__MASK 0x00040000U
+#define R_TEST_MODE__step_rd__step_rd__MASK 0x00020000U
+#define R_TEST_MODE__step_fetch__step_fetch__MASK 0x00010000U
+#define R_TEST_MODE__mmu_test__mmu_test__MASK 0x00001000U
+#define R_TEST_MODE__usb_test__usb_test__MASK 0x00000800U
+#define R_TEST_MODE__scsi_timer_test__scsi_timer_test__MASK 0x00000400U
+#define R_TEST_MODE__backoff__backoff__MASK 0x00000200U
+#define R_TEST_MODE__snmp_test__snmp_test__MASK 0x00000100U
+#define R_TEST_MODE__snmp_inc__snmp_inc__MASK 0x00000080U
+#define R_TEST_MODE__ser_loop__ser_loop__MASK 0x00000040U
+#define R_TEST_MODE__baudrate__baudrate__MASK 0x00000020U
+#define R_TEST_MODE__timer__timer__MASK 0x00000018U
+#define R_TEST_MODE__cache_test__cache_test__MASK 0x00000004U
+#define R_TEST_MODE__tag_test__tag_test__MASK 0x00000002U
+#define R_TEST_MODE__cache_enable__cache_enable__MASK 0x00000001U
+
+#define R_TEST_MODE__single_step__MAX 0x1
+#define R_TEST_MODE__step_wr__MAX 0x1
+#define R_TEST_MODE__step_rd__MAX 0x1
+#define R_TEST_MODE__step_fetch__MAX 0x1
+#define R_TEST_MODE__mmu_test__MAX 0x1
+#define R_TEST_MODE__usb_test__MAX 0x1
+#define R_TEST_MODE__scsi_timer_test__MAX 0x1
+#define R_TEST_MODE__backoff__MAX 0x1
+#define R_TEST_MODE__snmp_test__MAX 0x1
+#define R_TEST_MODE__snmp_inc__MAX 0x1
+#define R_TEST_MODE__ser_loop__MAX 0x1
+#define R_TEST_MODE__baudrate__MAX 0x1
+#define R_TEST_MODE__timer__MAX 0x3
+#define R_TEST_MODE__cache_test__MAX 0x1
+#define R_TEST_MODE__tag_test__MAX 0x1
+#define R_TEST_MODE__cache_enable__MAX 0x1
+
+#define R_TEST_MODE__single_step__MIN 0
+#define R_TEST_MODE__step_wr__MIN 0
+#define R_TEST_MODE__step_rd__MIN 0
+#define R_TEST_MODE__step_fetch__MIN 0
+#define R_TEST_MODE__mmu_test__MIN 0
+#define R_TEST_MODE__usb_test__MIN 0
+#define R_TEST_MODE__scsi_timer_test__MIN 0
+#define R_TEST_MODE__backoff__MIN 0
+#define R_TEST_MODE__snmp_test__MIN 0
+#define R_TEST_MODE__snmp_inc__MIN 0
+#define R_TEST_MODE__ser_loop__MIN 0
+#define R_TEST_MODE__baudrate__MIN 0
+#define R_TEST_MODE__timer__MIN 0
+#define R_TEST_MODE__cache_test__MIN 0
+#define R_TEST_MODE__tag_test__MIN 0
+#define R_TEST_MODE__cache_enable__MIN 0
+
+#define R_TEST_MODE__single_step__BITNR 19
+#define R_TEST_MODE__step_wr__BITNR 18
+#define R_TEST_MODE__step_rd__BITNR 17
+#define R_TEST_MODE__step_fetch__BITNR 16
+#define R_TEST_MODE__mmu_test__BITNR 12
+#define R_TEST_MODE__usb_test__BITNR 11
+#define R_TEST_MODE__scsi_timer_test__BITNR 10
+#define R_TEST_MODE__backoff__BITNR 9
+#define R_TEST_MODE__snmp_test__BITNR 8
+#define R_TEST_MODE__snmp_inc__BITNR 7
+#define R_TEST_MODE__ser_loop__BITNR 6
+#define R_TEST_MODE__baudrate__BITNR 5
+#define R_TEST_MODE__timer__BITNR 3
+#define R_TEST_MODE__cache_test__BITNR 2
+#define R_TEST_MODE__tag_test__BITNR 1
+#define R_TEST_MODE__cache_enable__BITNR 0
+
+#define R_TEST_MODE__single_step__single_step__VAL REG_VAL_ENUM
+#define R_TEST_MODE__step_wr__step_wr__VAL REG_VAL_ENUM
+#define R_TEST_MODE__step_rd__step_rd__VAL REG_VAL_ENUM
+#define R_TEST_MODE__step_fetch__step_fetch__VAL REG_VAL_ENUM
+#define R_TEST_MODE__mmu_test__mmu_test__VAL REG_VAL_ENUM
+#define R_TEST_MODE__usb_test__usb_test__VAL REG_VAL_ENUM
+#define R_TEST_MODE__scsi_timer_test__scsi_timer_test__VAL REG_VAL_ENUM
+#define R_TEST_MODE__backoff__backoff__VAL REG_VAL_ENUM
+#define R_TEST_MODE__snmp_test__snmp_test__VAL REG_VAL_ENUM
+#define R_TEST_MODE__snmp_inc__snmp_inc__VAL REG_VAL_ENUM
+#define R_TEST_MODE__ser_loop__ser_loop__VAL REG_VAL_ENUM
+#define R_TEST_MODE__baudrate__baudrate__VAL REG_VAL_ENUM
+#define R_TEST_MODE__timer__timer__VAL REG_VAL_ENUM
+#define R_TEST_MODE__cache_test__cache_test__VAL REG_VAL_ENUM
+#define R_TEST_MODE__tag_test__tag_test__VAL REG_VAL_ENUM
+#define R_TEST_MODE__cache_enable__cache_enable__VAL REG_VAL_ENUM
+
+#define R_TEST_MODE__single_step__single_step__off 0
+#define R_TEST_MODE__single_step__single_step__on 1
+#define R_TEST_MODE__step_wr__step_wr__off 0
+#define R_TEST_MODE__step_wr__step_wr__on 1
+#define R_TEST_MODE__step_rd__step_rd__off 0
+#define R_TEST_MODE__step_rd__step_rd__on 1
+#define R_TEST_MODE__step_fetch__step_fetch__off 0
+#define R_TEST_MODE__step_fetch__step_fetch__on 1
+#define R_TEST_MODE__mmu_test__mmu_test__off 0
+#define R_TEST_MODE__mmu_test__mmu_test__on 1
+#define R_TEST_MODE__usb_test__usb_test__off 0
+#define R_TEST_MODE__usb_test__usb_test__on 1
+#define R_TEST_MODE__scsi_timer_test__scsi_timer_test__off 0
+#define R_TEST_MODE__scsi_timer_test__scsi_timer_test__on 1
+#define R_TEST_MODE__backoff__backoff__off 0
+#define R_TEST_MODE__backoff__backoff__on 1
+#define R_TEST_MODE__snmp_test__snmp_test__off 0
+#define R_TEST_MODE__snmp_test__snmp_test__on 1
+#define R_TEST_MODE__snmp_inc__snmp_inc__do 1
+#define R_TEST_MODE__snmp_inc__snmp_inc__dont 0
+#define R_TEST_MODE__ser_loop__ser_loop__off 0
+#define R_TEST_MODE__ser_loop__ser_loop__on 1
+#define R_TEST_MODE__baudrate__baudrate__off 0
+#define R_TEST_MODE__baudrate__baudrate__on 1
+#define R_TEST_MODE__timer__timer__all 3
+#define R_TEST_MODE__timer__timer__even 1
+#define R_TEST_MODE__timer__timer__odd 2
+#define R_TEST_MODE__timer__timer__off 0
+#define R_TEST_MODE__cache_test__cache_test__normal 0
+#define R_TEST_MODE__cache_test__cache_test__test 1
+#define R_TEST_MODE__tag_test__tag_test__normal 0
+#define R_TEST_MODE__tag_test__tag_test__test 1
+#define R_TEST_MODE__cache_enable__cache_enable__disable 0
+#define R_TEST_MODE__cache_enable__cache_enable__enable 1
+
+#endif
+
+/*
+ * R_TIMER01_DATA
+ * - type: RO
+ * - addr: 0xb0000022
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_TIMER01_DATA__ADDR (REG_TYPECAST_UWORD 0xb0000022)
+#define R_TIMER01_DATA__SVAL REG_SVAL_SHADOW
+#define R_TIMER01_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_TIMER01_DATA__TYPECAST REG_TYPECAST_UWORD
+#define R_TIMER01_DATA__TYPE (REG_UWORD)
+#define R_TIMER01_DATA__GET REG_GET_RO
+#define R_TIMER01_DATA__IGET REG_IGET_RO
+#define R_TIMER01_DATA__SET REG_SET_RO
+#define R_TIMER01_DATA__ISET REG_ISET_RO
+#define R_TIMER01_DATA__SET_VAL REG_SET_VAL_RO
+#define R_TIMER01_DATA__EQL REG_EQL_RO
+#define R_TIMER01_DATA__IEQL REG_IEQL_RO
+#define R_TIMER01_DATA__RD REG_RD_RO
+#define R_TIMER01_DATA__IRD REG_IRD_RO
+#define R_TIMER01_DATA__WR REG_WR_RO
+#define R_TIMER01_DATA__IWR REG_IWR_RO
+
+#define R_TIMER01_DATA__READ(addr) \
+ (*(addr))
+
+#define R_TIMER01_DATA__count__count__MASK 0x0000ffffU
+
+#define R_TIMER01_DATA__count__MAX 0xffff
+
+#define R_TIMER01_DATA__count__MIN 0
+
+#define R_TIMER01_DATA__count__BITNR 0
+
+#define R_TIMER01_DATA__count__count__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_TIMER0_DATA
+ * - type: RO
+ * - addr: 0xb0000022
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_TIMER0_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000022)
+#define R_TIMER0_DATA__SVAL REG_SVAL_SHADOW
+#define R_TIMER0_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_TIMER0_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_TIMER0_DATA__TYPE (REG_BYTE)
+#define R_TIMER0_DATA__GET REG_GET_RO
+#define R_TIMER0_DATA__IGET REG_IGET_RO
+#define R_TIMER0_DATA__SET REG_SET_RO
+#define R_TIMER0_DATA__ISET REG_ISET_RO
+#define R_TIMER0_DATA__SET_VAL REG_SET_VAL_RO
+#define R_TIMER0_DATA__EQL REG_EQL_RO
+#define R_TIMER0_DATA__IEQL REG_IEQL_RO
+#define R_TIMER0_DATA__RD REG_RD_RO
+#define R_TIMER0_DATA__IRD REG_IRD_RO
+#define R_TIMER0_DATA__WR REG_WR_RO
+#define R_TIMER0_DATA__IWR REG_IWR_RO
+
+#define R_TIMER0_DATA__READ(addr) \
+ (*(addr))
+
+#define R_TIMER0_DATA__count__count__MASK 0x000000ffU
+
+#define R_TIMER0_DATA__count__MAX 0xff
+
+#define R_TIMER0_DATA__count__MIN 0
+
+#define R_TIMER0_DATA__count__BITNR 0
+
+#define R_TIMER0_DATA__count__count__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_TIMER1_DATA
+ * - type: RO
+ * - addr: 0xb0000023
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_TIMER1_DATA__ADDR (REG_TYPECAST_BYTE 0xb0000023)
+#define R_TIMER1_DATA__SVAL REG_SVAL_SHADOW
+#define R_TIMER1_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_TIMER1_DATA__TYPECAST REG_TYPECAST_BYTE
+#define R_TIMER1_DATA__TYPE (REG_BYTE)
+#define R_TIMER1_DATA__GET REG_GET_RO
+#define R_TIMER1_DATA__IGET REG_IGET_RO
+#define R_TIMER1_DATA__SET REG_SET_RO
+#define R_TIMER1_DATA__ISET REG_ISET_RO
+#define R_TIMER1_DATA__SET_VAL REG_SET_VAL_RO
+#define R_TIMER1_DATA__EQL REG_EQL_RO
+#define R_TIMER1_DATA__IEQL REG_IEQL_RO
+#define R_TIMER1_DATA__RD REG_RD_RO
+#define R_TIMER1_DATA__IRD REG_IRD_RO
+#define R_TIMER1_DATA__WR REG_WR_RO
+#define R_TIMER1_DATA__IWR REG_IWR_RO
+
+#define R_TIMER1_DATA__READ(addr) \
+ (*(addr))
+
+#define R_TIMER1_DATA__count__count__MASK 0x000000ffU
+
+#define R_TIMER1_DATA__count__MAX 0xff
+
+#define R_TIMER1_DATA__count__MIN 0
+
+#define R_TIMER1_DATA__count__BITNR 0
+
+#define R_TIMER1_DATA__count__count__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_TIMER_CTRL
+ * - type: WO
+ * - addr: 0xb0000020
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_TIMER_CTRL__ADDR (REG_TYPECAST_UDWORD 0xb0000020)
+
+#ifndef REG_NO_SHADOW
+#define R_TIMER_CTRL__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_TIMER_CTRL + 0))
+#define R_TIMER_CTRL__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_TIMER_CTRL + 0))
+#else /* REG_NO_SHADOW */
+#define R_TIMER_CTRL__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_TIMER_CTRL__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_TIMER_CTRL__STYPECAST REG_STYPECAST_UDWORD
+#define R_TIMER_CTRL__SVAL REG_SVAL_SHADOW
+#define R_TIMER_CTRL__SVAL_I REG_SVAL_I_SHADOW
+#define R_TIMER_CTRL__TYPECAST REG_TYPECAST_UDWORD
+#define R_TIMER_CTRL__TYPE (REG_UDWORD)
+#define R_TIMER_CTRL__GET REG_GET_WO
+#define R_TIMER_CTRL__IGET REG_IGET_WO
+#define R_TIMER_CTRL__SET REG_SET_WO
+#define R_TIMER_CTRL__ISET REG_ISET_WO
+#define R_TIMER_CTRL__SET_VAL REG_SET_VAL_WO
+#define R_TIMER_CTRL__EQL REG_EQL_WO
+#define R_TIMER_CTRL__IEQL REG_IEQL_WO
+#define R_TIMER_CTRL__RD REG_RD_WO
+#define R_TIMER_CTRL__IRD REG_IRD_WO
+#define R_TIMER_CTRL__WR REG_WR_WO
+#define R_TIMER_CTRL__IWR REG_IWR_WO
+
+#define R_TIMER_CTRL__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_TIMER_CTRL__timerdiv1__timerdiv1__MASK 0xff000000U
+#define R_TIMER_CTRL__timerdiv0__timerdiv0__MASK 0x00ff0000U
+#define R_TIMER_CTRL__presc_timer1__presc_timer1__MASK 0x00008000U
+#define R_TIMER_CTRL__i1__i1__MASK 0x00004000U
+#define R_TIMER_CTRL__tm1__tm1__MASK 0x00003000U
+#define R_TIMER_CTRL__clksel1__clksel1__MASK 0x00000f00U
+#define R_TIMER_CTRL__presc_ext__presc_ext__MASK 0x00000080U
+#define R_TIMER_CTRL__i0__i0__MASK 0x00000040U
+#define R_TIMER_CTRL__tm0__tm0__MASK 0x00000030U
+#define R_TIMER_CTRL__clksel0__clksel0__MASK 0x0000000fU
+
+#define R_TIMER_CTRL__timerdiv1__MAX 0xff
+#define R_TIMER_CTRL__timerdiv0__MAX 0xff
+#define R_TIMER_CTRL__presc_timer1__MAX 0x1
+#define R_TIMER_CTRL__i1__MAX 0x1
+#define R_TIMER_CTRL__tm1__MAX 0x3
+#define R_TIMER_CTRL__clksel1__MAX 0xf
+#define R_TIMER_CTRL__presc_ext__MAX 0x1
+#define R_TIMER_CTRL__i0__MAX 0x1
+#define R_TIMER_CTRL__tm0__MAX 0x3
+#define R_TIMER_CTRL__clksel0__MAX 0xf
+
+#define R_TIMER_CTRL__timerdiv1__MIN 0
+#define R_TIMER_CTRL__timerdiv0__MIN 0
+#define R_TIMER_CTRL__presc_timer1__MIN 0
+#define R_TIMER_CTRL__i1__MIN 0
+#define R_TIMER_CTRL__tm1__MIN 0
+#define R_TIMER_CTRL__clksel1__MIN 0
+#define R_TIMER_CTRL__presc_ext__MIN 0
+#define R_TIMER_CTRL__i0__MIN 0
+#define R_TIMER_CTRL__tm0__MIN 0
+#define R_TIMER_CTRL__clksel0__MIN 0
+
+#define R_TIMER_CTRL__timerdiv1__BITNR 24
+#define R_TIMER_CTRL__timerdiv0__BITNR 16
+#define R_TIMER_CTRL__presc_timer1__BITNR 15
+#define R_TIMER_CTRL__i1__BITNR 14
+#define R_TIMER_CTRL__tm1__BITNR 12
+#define R_TIMER_CTRL__clksel1__BITNR 8
+#define R_TIMER_CTRL__presc_ext__BITNR 7
+#define R_TIMER_CTRL__i0__BITNR 6
+#define R_TIMER_CTRL__tm0__BITNR 4
+#define R_TIMER_CTRL__clksel0__BITNR 0
+
+#define R_TIMER_CTRL__timerdiv1__timerdiv1__VAL REG_VAL_VAL
+#define R_TIMER_CTRL__timerdiv0__timerdiv0__VAL REG_VAL_VAL
+#define R_TIMER_CTRL__presc_timer1__presc_timer1__VAL REG_VAL_ENUM
+#define R_TIMER_CTRL__i1__i1__VAL REG_VAL_ENUM
+#define R_TIMER_CTRL__tm1__tm1__VAL REG_VAL_ENUM
+#define R_TIMER_CTRL__clksel1__clksel1__VAL REG_VAL_ENUM
+#define R_TIMER_CTRL__presc_ext__presc_ext__VAL REG_VAL_ENUM
+#define R_TIMER_CTRL__i0__i0__VAL REG_VAL_ENUM
+#define R_TIMER_CTRL__tm0__tm0__VAL REG_VAL_ENUM
+#define R_TIMER_CTRL__clksel0__clksel0__VAL REG_VAL_ENUM
+
+#define R_TIMER_CTRL__presc_timer1__presc_timer1__normal 0
+#define R_TIMER_CTRL__presc_timer1__presc_timer1__prescale 1
+#define R_TIMER_CTRL__i1__i1__clr 1
+#define R_TIMER_CTRL__i1__i1__nop 0
+#define R_TIMER_CTRL__tm1__tm1__freeze 1
+#define R_TIMER_CTRL__tm1__tm1__run 2
+#define R_TIMER_CTRL__tm1__tm1__stop_ld 0
+#define R_TIMER_CTRL__clksel1__clksel1__c115k2Hz 9
+#define R_TIMER_CTRL__clksel1__clksel1__c1200Hz 2
+#define R_TIMER_CTRL__clksel1__clksel1__c1843k2Hz 13
+#define R_TIMER_CTRL__clksel1__clksel1__c19k2Hz 6
+#define R_TIMER_CTRL__clksel1__clksel1__c230k4Hz 10
+#define R_TIMER_CTRL__clksel1__clksel1__c2400Hz 3
+#define R_TIMER_CTRL__clksel1__clksel1__c300Hz 0
+#define R_TIMER_CTRL__clksel1__clksel1__c38k4Hz 7
+#define R_TIMER_CTRL__clksel1__clksel1__c460k8Hz 11
+#define R_TIMER_CTRL__clksel1__clksel1__c4800Hz 4
+#define R_TIMER_CTRL__clksel1__clksel1__c57k6Hz 8
+#define R_TIMER_CTRL__clksel1__clksel1__c600Hz 1
+#define R_TIMER_CTRL__clksel1__clksel1__c6250kHz 14
+#define R_TIMER_CTRL__clksel1__clksel1__c921k6Hz 12
+#define R_TIMER_CTRL__clksel1__clksel1__c9600Hz 5
+#define R_TIMER_CTRL__clksel1__clksel1__cascade0 15
+#define R_TIMER_CTRL__presc_ext__presc_ext__external 1
+#define R_TIMER_CTRL__presc_ext__presc_ext__prescale 0
+#define R_TIMER_CTRL__i0__i0__clr 1
+#define R_TIMER_CTRL__i0__i0__nop 0
+#define R_TIMER_CTRL__tm0__tm0__freeze 1
+#define R_TIMER_CTRL__tm0__tm0__run 2
+#define R_TIMER_CTRL__tm0__tm0__stop_ld 0
+#define R_TIMER_CTRL__clksel0__clksel0__c115k2Hz 9
+#define R_TIMER_CTRL__clksel0__clksel0__c1200Hz 2
+#define R_TIMER_CTRL__clksel0__clksel0__c1843k2Hz 13
+#define R_TIMER_CTRL__clksel0__clksel0__c19k2Hz 6
+#define R_TIMER_CTRL__clksel0__clksel0__c230k4Hz 10
+#define R_TIMER_CTRL__clksel0__clksel0__c2400Hz 3
+#define R_TIMER_CTRL__clksel0__clksel0__c300Hz 0
+#define R_TIMER_CTRL__clksel0__clksel0__c38k4Hz 7
+#define R_TIMER_CTRL__clksel0__clksel0__c460k8Hz 11
+#define R_TIMER_CTRL__clksel0__clksel0__c4800Hz 4
+#define R_TIMER_CTRL__clksel0__clksel0__c57k6Hz 8
+#define R_TIMER_CTRL__clksel0__clksel0__c600Hz 1
+#define R_TIMER_CTRL__clksel0__clksel0__c6250kHz 14
+#define R_TIMER_CTRL__clksel0__clksel0__c921k6Hz 12
+#define R_TIMER_CTRL__clksel0__clksel0__c9600Hz 5
+#define R_TIMER_CTRL__clksel0__clksel0__flexible 15
+
+#endif
+
+/*
+ * R_TIMER_DATA
+ * - type: RO
+ * - addr: 0xb0000020
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_TIMER_DATA__ADDR (REG_TYPECAST_UDWORD 0xb0000020)
+#define R_TIMER_DATA__SVAL REG_SVAL_SHADOW
+#define R_TIMER_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_TIMER_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_TIMER_DATA__TYPE (REG_UDWORD)
+#define R_TIMER_DATA__GET REG_GET_RO
+#define R_TIMER_DATA__IGET REG_IGET_RO
+#define R_TIMER_DATA__SET REG_SET_RO
+#define R_TIMER_DATA__ISET REG_ISET_RO
+#define R_TIMER_DATA__SET_VAL REG_SET_VAL_RO
+#define R_TIMER_DATA__EQL REG_EQL_RO
+#define R_TIMER_DATA__IEQL REG_IEQL_RO
+#define R_TIMER_DATA__RD REG_RD_RO
+#define R_TIMER_DATA__IRD REG_IRD_RO
+#define R_TIMER_DATA__WR REG_WR_RO
+#define R_TIMER_DATA__IWR REG_IWR_RO
+
+#define R_TIMER_DATA__READ(addr) \
+ (*(addr))
+
+#define R_TIMER_DATA__timer1__timer1__MASK 0xff000000U
+#define R_TIMER_DATA__timer0__timer0__MASK 0x00ff0000U
+#define R_TIMER_DATA__clkdiv_high__clkdiv_high__MASK 0x0000ff00U
+#define R_TIMER_DATA__clkdiv_low__clkdiv_low__MASK 0x000000ffU
+
+#define R_TIMER_DATA__timer1__MAX 0xff
+#define R_TIMER_DATA__timer0__MAX 0xff
+#define R_TIMER_DATA__clkdiv_high__MAX 0xff
+#define R_TIMER_DATA__clkdiv_low__MAX 0xff
+
+#define R_TIMER_DATA__timer1__MIN 0
+#define R_TIMER_DATA__timer0__MIN 0
+#define R_TIMER_DATA__clkdiv_high__MIN 0
+#define R_TIMER_DATA__clkdiv_low__MIN 0
+
+#define R_TIMER_DATA__timer1__BITNR 24
+#define R_TIMER_DATA__timer0__BITNR 16
+#define R_TIMER_DATA__clkdiv_high__BITNR 8
+#define R_TIMER_DATA__clkdiv_low__BITNR 0
+
+#define R_TIMER_DATA__timer1__timer1__VAL REG_VAL_VAL
+#define R_TIMER_DATA__timer0__timer0__VAL REG_VAL_VAL
+#define R_TIMER_DATA__clkdiv_high__clkdiv_high__VAL REG_VAL_VAL
+#define R_TIMER_DATA__clkdiv_low__clkdiv_low__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_TIMER_PRESCALE
+ * - type: WO
+ * - addr: 0xb00000f0
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_TIMER_PRESCALE__ADDR (REG_TYPECAST_UWORD 0xb00000f0)
+
+#ifndef REG_NO_SHADOW
+#define R_TIMER_PRESCALE__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_CLOCK_PRESCALE + 0))
+#define R_TIMER_PRESCALE__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_CLOCK_PRESCALE + 0))
+#else /* REG_NO_SHADOW */
+#define R_TIMER_PRESCALE__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_TIMER_PRESCALE__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_TIMER_PRESCALE__STYPECAST REG_STYPECAST_UWORD
+#define R_TIMER_PRESCALE__SVAL REG_SVAL_SHADOW
+#define R_TIMER_PRESCALE__SVAL_I REG_SVAL_I_SHADOW
+#define R_TIMER_PRESCALE__TYPECAST REG_TYPECAST_UWORD
+#define R_TIMER_PRESCALE__TYPE (REG_UWORD)
+#define R_TIMER_PRESCALE__GET REG_GET_WO
+#define R_TIMER_PRESCALE__IGET REG_IGET_WO
+#define R_TIMER_PRESCALE__SET REG_SET_WO
+#define R_TIMER_PRESCALE__ISET REG_ISET_WO
+#define R_TIMER_PRESCALE__SET_VAL REG_SET_VAL_WO
+#define R_TIMER_PRESCALE__EQL REG_EQL_WO
+#define R_TIMER_PRESCALE__IEQL REG_IEQL_WO
+#define R_TIMER_PRESCALE__RD REG_RD_WO
+#define R_TIMER_PRESCALE__IRD REG_IRD_WO
+#define R_TIMER_PRESCALE__WR REG_WR_WO
+#define R_TIMER_PRESCALE__IWR REG_IWR_WO
+
+#define R_TIMER_PRESCALE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_TIMER_PRESCALE__tim_presc__tim_presc__MASK 0x0000ffffU
+
+#define R_TIMER_PRESCALE__tim_presc__MAX 0xffff
+
+#define R_TIMER_PRESCALE__tim_presc__MIN 0
+
+#define R_TIMER_PRESCALE__tim_presc__BITNR 0
+
+#define R_TIMER_PRESCALE__tim_presc__tim_presc__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_TIM_PRESC_STATUS
+ * - type: RO
+ * - addr: 0xb00000f0
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_TIM_PRESC_STATUS__ADDR (REG_TYPECAST_UWORD 0xb00000f0)
+#define R_TIM_PRESC_STATUS__SVAL REG_SVAL_SHADOW
+#define R_TIM_PRESC_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_TIM_PRESC_STATUS__TYPECAST REG_TYPECAST_UWORD
+#define R_TIM_PRESC_STATUS__TYPE (REG_UWORD)
+#define R_TIM_PRESC_STATUS__GET REG_GET_RO
+#define R_TIM_PRESC_STATUS__IGET REG_IGET_RO
+#define R_TIM_PRESC_STATUS__SET REG_SET_RO
+#define R_TIM_PRESC_STATUS__ISET REG_ISET_RO
+#define R_TIM_PRESC_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_TIM_PRESC_STATUS__EQL REG_EQL_RO
+#define R_TIM_PRESC_STATUS__IEQL REG_IEQL_RO
+#define R_TIM_PRESC_STATUS__RD REG_RD_RO
+#define R_TIM_PRESC_STATUS__IRD REG_IRD_RO
+#define R_TIM_PRESC_STATUS__WR REG_WR_RO
+#define R_TIM_PRESC_STATUS__IWR REG_IWR_RO
+
+#define R_TIM_PRESC_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_TIM_PRESC_STATUS__tim_status__tim_status__MASK 0x0000ffffU
+
+#define R_TIM_PRESC_STATUS__tim_status__MAX 0xffff
+
+#define R_TIM_PRESC_STATUS__tim_status__MIN 0
+
+#define R_TIM_PRESC_STATUS__tim_status__BITNR 0
+
+#define R_TIM_PRESC_STATUS__tim_status__tim_status__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_TLB_HI
+ * - type: RW
+ * - addr: 0xb000025c
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_TLB_HI__ADDR (REG_TYPECAST_UDWORD 0xb000025c)
+#define R_TLB_HI__SVAL REG_SVAL_SHADOW
+#define R_TLB_HI__SVAL_I REG_SVAL_I_SHADOW
+#define R_TLB_HI__TYPECAST REG_TYPECAST_UDWORD
+#define R_TLB_HI__TYPE (REG_UDWORD)
+#define R_TLB_HI__GET REG_GET_RW
+#define R_TLB_HI__IGET REG_IGET_RW
+#define R_TLB_HI__SET REG_SET_RW
+#define R_TLB_HI__ISET REG_ISET_RW
+#define R_TLB_HI__SET_VAL REG_SET_VAL_RW
+#define R_TLB_HI__EQL REG_EQL_RW
+#define R_TLB_HI__IEQL REG_IEQL_RW
+#define R_TLB_HI__RD REG_RD_RW
+#define R_TLB_HI__IRD REG_IRD_RW
+#define R_TLB_HI__WR REG_WR_RW
+#define R_TLB_HI__IWR REG_IWR_RW
+
+#define R_TLB_HI__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_TLB_HI__READ(addr) \
+ (*(addr))
+
+#define R_TLB_HI__vpn__vpn__MASK 0xffffe000U
+#define R_TLB_HI__page_id__page_id__MASK 0x0000003fU
+
+#define R_TLB_HI__vpn__MAX 0x7ffff
+#define R_TLB_HI__page_id__MAX 63
+
+#define R_TLB_HI__vpn__MIN 0
+#define R_TLB_HI__page_id__MIN 0
+
+#define R_TLB_HI__vpn__BITNR 13
+#define R_TLB_HI__page_id__BITNR 0
+
+#define R_TLB_HI__vpn__vpn__VAL REG_VAL_VAL
+#define R_TLB_HI__page_id__page_id__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_TLB_LO
+ * - type: RW
+ * - addr: 0xb0000258
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_TLB_LO__ADDR (REG_TYPECAST_UDWORD 0xb0000258)
+#define R_TLB_LO__SVAL REG_SVAL_SHADOW
+#define R_TLB_LO__SVAL_I REG_SVAL_I_SHADOW
+#define R_TLB_LO__TYPECAST REG_TYPECAST_UDWORD
+#define R_TLB_LO__TYPE (REG_UDWORD)
+#define R_TLB_LO__GET REG_GET_RW
+#define R_TLB_LO__IGET REG_IGET_RW
+#define R_TLB_LO__SET REG_SET_RW
+#define R_TLB_LO__ISET REG_ISET_RW
+#define R_TLB_LO__SET_VAL REG_SET_VAL_RW
+#define R_TLB_LO__EQL REG_EQL_RW
+#define R_TLB_LO__IEQL REG_IEQL_RW
+#define R_TLB_LO__RD REG_RD_RW
+#define R_TLB_LO__IRD REG_IRD_RW
+#define R_TLB_LO__WR REG_WR_RW
+#define R_TLB_LO__IWR REG_IWR_RW
+
+#define R_TLB_LO__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_TLB_LO__READ(addr) \
+ (*(addr))
+
+#define R_TLB_LO__pfn__pfn__MASK 0xffffe000U
+#define R_TLB_LO__global__global__MASK 0x00000008U
+#define R_TLB_LO__valid__valid__MASK 0x00000004U
+#define R_TLB_LO__kernel__kernel__MASK 0x00000002U
+#define R_TLB_LO__we__we__MASK 0x00000001U
+
+#define R_TLB_LO__pfn__MAX 0x7ffff
+#define R_TLB_LO__global__MAX 0x1
+#define R_TLB_LO__valid__MAX 0x1
+#define R_TLB_LO__kernel__MAX 0x1
+#define R_TLB_LO__we__MAX 0x1
+
+#define R_TLB_LO__pfn__MIN 0
+#define R_TLB_LO__global__MIN 0
+#define R_TLB_LO__valid__MIN 0
+#define R_TLB_LO__kernel__MIN 0
+#define R_TLB_LO__we__MIN 0
+
+#define R_TLB_LO__pfn__BITNR 13
+#define R_TLB_LO__global__BITNR 3
+#define R_TLB_LO__valid__BITNR 2
+#define R_TLB_LO__kernel__BITNR 1
+#define R_TLB_LO__we__BITNR 0
+
+#define R_TLB_LO__pfn__pfn__VAL REG_VAL_VAL
+#define R_TLB_LO__global__global__VAL REG_VAL_ENUM
+#define R_TLB_LO__valid__valid__VAL REG_VAL_ENUM
+#define R_TLB_LO__kernel__kernel__VAL REG_VAL_ENUM
+#define R_TLB_LO__we__we__VAL REG_VAL_ENUM
+
+#define R_TLB_LO__global__global__no 0
+#define R_TLB_LO__global__global__yes 1
+#define R_TLB_LO__valid__valid__no 0
+#define R_TLB_LO__valid__valid__yes 1
+#define R_TLB_LO__kernel__kernel__no 0
+#define R_TLB_LO__kernel__kernel__yes 1
+#define R_TLB_LO__we__we__no 0
+#define R_TLB_LO__we__we__yes 1
+
+#endif
+
+/*
+ * R_TLB_SELECT
+ * - type: RW
+ * - addr: 0xb0000254
+ * - group: MMU registers
+ */
+
+#if USE_GROUP__MMU_registers
+
+#define R_TLB_SELECT__ADDR (REG_TYPECAST_BYTE 0xb0000254)
+#define R_TLB_SELECT__SVAL REG_SVAL_SHADOW
+#define R_TLB_SELECT__SVAL_I REG_SVAL_I_SHADOW
+#define R_TLB_SELECT__TYPECAST REG_TYPECAST_BYTE
+#define R_TLB_SELECT__TYPE (REG_BYTE)
+#define R_TLB_SELECT__GET REG_GET_RW
+#define R_TLB_SELECT__IGET REG_IGET_RW
+#define R_TLB_SELECT__SET REG_SET_RW
+#define R_TLB_SELECT__ISET REG_ISET_RW
+#define R_TLB_SELECT__SET_VAL REG_SET_VAL_RW
+#define R_TLB_SELECT__EQL REG_EQL_RW
+#define R_TLB_SELECT__IEQL REG_IEQL_RW
+#define R_TLB_SELECT__RD REG_RD_RW
+#define R_TLB_SELECT__IRD REG_IRD_RW
+#define R_TLB_SELECT__WR REG_WR_RW
+#define R_TLB_SELECT__IWR REG_IWR_RW
+
+#define R_TLB_SELECT__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_TLB_SELECT__READ(addr) \
+ (*(addr))
+
+#define R_TLB_SELECT__index__index__MASK 0x0000003fU
+
+#define R_TLB_SELECT__index__MAX 63
+
+#define R_TLB_SELECT__index__MIN 0
+
+#define R_TLB_SELECT__index__BITNR 0
+
+#define R_TLB_SELECT__index__index__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_TR_COUNTERS
+ * - type: RO
+ * - addr: 0xb00000a8
+ * - group: Network interface registers
+ */
+
+#if USE_GROUP__Network_interface_registers
+
+#define R_TR_COUNTERS__ADDR (REG_TYPECAST_UDWORD 0xb00000a8)
+#define R_TR_COUNTERS__SVAL REG_SVAL_SHADOW
+#define R_TR_COUNTERS__SVAL_I REG_SVAL_I_SHADOW
+#define R_TR_COUNTERS__TYPECAST REG_TYPECAST_UDWORD
+#define R_TR_COUNTERS__TYPE (REG_UDWORD)
+#define R_TR_COUNTERS__GET REG_GET_RO
+#define R_TR_COUNTERS__IGET REG_IGET_RO
+#define R_TR_COUNTERS__SET REG_SET_RO
+#define R_TR_COUNTERS__ISET REG_ISET_RO
+#define R_TR_COUNTERS__SET_VAL REG_SET_VAL_RO
+#define R_TR_COUNTERS__EQL REG_EQL_RO
+#define R_TR_COUNTERS__IEQL REG_IEQL_RO
+#define R_TR_COUNTERS__RD REG_RD_RO
+#define R_TR_COUNTERS__IRD REG_IRD_RO
+#define R_TR_COUNTERS__WR REG_WR_RO
+#define R_TR_COUNTERS__IWR REG_IWR_RO
+
+#define R_TR_COUNTERS__READ(addr) \
+ (*(addr))
+
+#define R_TR_COUNTERS__deferred__deferred__MASK 0xff000000U
+#define R_TR_COUNTERS__late_col__late_col__MASK 0x00ff0000U
+#define R_TR_COUNTERS__multiple_col__multiple_col__MASK 0x0000ff00U
+#define R_TR_COUNTERS__single_col__single_col__MASK 0x000000ffU
+
+#define R_TR_COUNTERS__deferred__MAX 0xff
+#define R_TR_COUNTERS__late_col__MAX 0xff
+#define R_TR_COUNTERS__multiple_col__MAX 0xff
+#define R_TR_COUNTERS__single_col__MAX 0xff
+
+#define R_TR_COUNTERS__deferred__MIN 0
+#define R_TR_COUNTERS__late_col__MIN 0
+#define R_TR_COUNTERS__multiple_col__MIN 0
+#define R_TR_COUNTERS__single_col__MIN 0
+
+#define R_TR_COUNTERS__deferred__BITNR 24
+#define R_TR_COUNTERS__late_col__BITNR 16
+#define R_TR_COUNTERS__multiple_col__BITNR 8
+#define R_TR_COUNTERS__single_col__BITNR 0
+
+#define R_TR_COUNTERS__deferred__deferred__VAL REG_VAL_VAL
+#define R_TR_COUNTERS__late_col__late_col__VAL REG_VAL_VAL
+#define R_TR_COUNTERS__multiple_col__multiple_col__VAL REG_VAL_VAL
+#define R_TR_COUNTERS__single_col__single_col__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_USB_COMMAND
+ * - type: RW
+ * - addr: 0xb0000201
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_COMMAND__ADDR (REG_TYPECAST_BYTE 0xb0000201)
+#define R_USB_COMMAND__SVAL REG_SVAL_SHADOW
+#define R_USB_COMMAND__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_COMMAND__TYPECAST REG_TYPECAST_BYTE
+#define R_USB_COMMAND__TYPE (REG_BYTE)
+#define R_USB_COMMAND__GET REG_GET_RW
+#define R_USB_COMMAND__IGET REG_IGET_RW
+#define R_USB_COMMAND__SET REG_SET_RW
+#define R_USB_COMMAND__ISET REG_ISET_RW
+#define R_USB_COMMAND__SET_VAL REG_SET_VAL_RW
+#define R_USB_COMMAND__EQL REG_EQL_RW
+#define R_USB_COMMAND__IEQL REG_IEQL_RW
+#define R_USB_COMMAND__RD REG_RD_RW
+#define R_USB_COMMAND__IRD REG_IRD_RW
+#define R_USB_COMMAND__WR REG_WR_RW
+#define R_USB_COMMAND__IWR REG_IWR_RW
+
+#define R_USB_COMMAND__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_COMMAND__READ(addr) \
+ (*(addr))
+
+#define R_USB_COMMAND__port_sel__port_sel__MASK 0x000000c0U
+#define R_USB_COMMAND__port_cmd__port_cmd__MASK 0x00000030U
+#define R_USB_COMMAND__busy__busy__MASK 0x00000008U
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__MASK 0x00000007U
+
+#define R_USB_COMMAND__port_sel__MAX 0x3
+#define R_USB_COMMAND__port_cmd__MAX 0x3
+#define R_USB_COMMAND__busy__MAX 0x1
+#define R_USB_COMMAND__ctrl_cmd__MAX 0x7
+
+#define R_USB_COMMAND__port_sel__MIN 0
+#define R_USB_COMMAND__port_cmd__MIN 0
+#define R_USB_COMMAND__busy__MIN 0
+#define R_USB_COMMAND__ctrl_cmd__MIN 0
+
+#define R_USB_COMMAND__port_sel__BITNR 6
+#define R_USB_COMMAND__port_cmd__BITNR 4
+#define R_USB_COMMAND__busy__BITNR 3
+#define R_USB_COMMAND__ctrl_cmd__BITNR 0
+
+#define R_USB_COMMAND__port_sel__port_sel__VAL REG_VAL_ENUM
+#define R_USB_COMMAND__port_cmd__port_cmd__VAL REG_VAL_ENUM
+#define R_USB_COMMAND__busy__busy__VAL REG_VAL_ENUM
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__VAL REG_VAL_ENUM
+
+#define R_USB_COMMAND__port_sel__port_sel__both 3
+#define R_USB_COMMAND__port_sel__port_sel__nop 0
+#define R_USB_COMMAND__port_sel__port_sel__port1 1
+#define R_USB_COMMAND__port_sel__port_sel__port2 2
+#define R_USB_COMMAND__port_cmd__port_cmd__disable 1
+#define R_USB_COMMAND__port_cmd__port_cmd__reset 0
+#define R_USB_COMMAND__port_cmd__port_cmd__resume 3
+#define R_USB_COMMAND__port_cmd__port_cmd__suspend 2
+#define R_USB_COMMAND__busy__busy__no 0
+#define R_USB_COMMAND__busy__busy__yes 1
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__deconfig 2
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__dev_config 4
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_config 3
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_nop 5
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_run 6
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__host_stop 7
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__nop 0
+#define R_USB_COMMAND__ctrl_cmd__ctrl_cmd__reset 1
+
+#endif
+
+/*
+ * R_USB_COMMAND_DEV
+ * - type: RW
+ * - addr: 0xb0000201
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_COMMAND_DEV__ADDR (REG_TYPECAST_BYTE 0xb0000201)
+#define R_USB_COMMAND_DEV__SVAL REG_SVAL_SHADOW
+#define R_USB_COMMAND_DEV__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_COMMAND_DEV__TYPECAST REG_TYPECAST_BYTE
+#define R_USB_COMMAND_DEV__TYPE (REG_BYTE)
+#define R_USB_COMMAND_DEV__GET REG_GET_RW
+#define R_USB_COMMAND_DEV__IGET REG_IGET_RW
+#define R_USB_COMMAND_DEV__SET REG_SET_RW
+#define R_USB_COMMAND_DEV__ISET REG_ISET_RW
+#define R_USB_COMMAND_DEV__SET_VAL REG_SET_VAL_RW
+#define R_USB_COMMAND_DEV__EQL REG_EQL_RW
+#define R_USB_COMMAND_DEV__IEQL REG_IEQL_RW
+#define R_USB_COMMAND_DEV__RD REG_RD_RW
+#define R_USB_COMMAND_DEV__IRD REG_IRD_RW
+#define R_USB_COMMAND_DEV__WR REG_WR_RW
+#define R_USB_COMMAND_DEV__IWR REG_IWR_RW
+
+#define R_USB_COMMAND_DEV__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_COMMAND_DEV__READ(addr) \
+ (*(addr))
+
+#define R_USB_COMMAND_DEV__port_sel__port_sel__MASK 0x000000c0U
+#define R_USB_COMMAND_DEV__port_cmd__port_cmd__MASK 0x00000030U
+#define R_USB_COMMAND_DEV__busy__busy__MASK 0x00000008U
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__MASK 0x00000007U
+
+#define R_USB_COMMAND_DEV__port_sel__MAX 0x3
+#define R_USB_COMMAND_DEV__port_cmd__MAX 0x3
+#define R_USB_COMMAND_DEV__busy__MAX 0x1
+#define R_USB_COMMAND_DEV__ctrl_cmd__MAX 0x7
+
+#define R_USB_COMMAND_DEV__port_sel__MIN 0
+#define R_USB_COMMAND_DEV__port_cmd__MIN 0
+#define R_USB_COMMAND_DEV__busy__MIN 0
+#define R_USB_COMMAND_DEV__ctrl_cmd__MIN 0
+
+#define R_USB_COMMAND_DEV__port_sel__BITNR 6
+#define R_USB_COMMAND_DEV__port_cmd__BITNR 4
+#define R_USB_COMMAND_DEV__busy__BITNR 3
+#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0
+
+#define R_USB_COMMAND_DEV__port_sel__port_sel__VAL REG_VAL_ENUM
+#define R_USB_COMMAND_DEV__port_cmd__port_cmd__VAL REG_VAL_ENUM
+#define R_USB_COMMAND_DEV__busy__busy__VAL REG_VAL_ENUM
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__VAL REG_VAL_ENUM
+
+#define R_USB_COMMAND_DEV__port_sel__port_sel__any 3
+#define R_USB_COMMAND_DEV__port_sel__port_sel__dummy1 1
+#define R_USB_COMMAND_DEV__port_sel__port_sel__dummy2 2
+#define R_USB_COMMAND_DEV__port_sel__port_sel__nop 0
+#define R_USB_COMMAND_DEV__port_cmd__port_cmd__active 0
+#define R_USB_COMMAND_DEV__port_cmd__port_cmd__nop 2
+#define R_USB_COMMAND_DEV__port_cmd__port_cmd__passive 1
+#define R_USB_COMMAND_DEV__port_cmd__port_cmd__wakeup 3
+#define R_USB_COMMAND_DEV__busy__busy__no 0
+#define R_USB_COMMAND_DEV__busy__busy__yes 1
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__deconfig 2
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_config 4
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop 1
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop2 5
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop3 6
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__dev_nop4 7
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__host_config 3
+#define R_USB_COMMAND_DEV__ctrl_cmd__ctrl_cmd__nop 0
+
+#endif
+
+/*
+ * R_USB_EPID_ATTN
+ * - type: RO
+ * - addr: 0xb0000224
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_EPID_ATTN__ADDR (REG_TYPECAST_UDWORD 0xb0000224)
+#define R_USB_EPID_ATTN__SVAL REG_SVAL_SHADOW
+#define R_USB_EPID_ATTN__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_EPID_ATTN__TYPECAST REG_TYPECAST_UDWORD
+#define R_USB_EPID_ATTN__TYPE (REG_UDWORD)
+#define R_USB_EPID_ATTN__GET REG_GET_RO
+#define R_USB_EPID_ATTN__IGET REG_IGET_RO
+#define R_USB_EPID_ATTN__SET REG_SET_RO
+#define R_USB_EPID_ATTN__ISET REG_ISET_RO
+#define R_USB_EPID_ATTN__SET_VAL REG_SET_VAL_RO
+#define R_USB_EPID_ATTN__EQL REG_EQL_RO
+#define R_USB_EPID_ATTN__IEQL REG_IEQL_RO
+#define R_USB_EPID_ATTN__RD REG_RD_RO
+#define R_USB_EPID_ATTN__IRD REG_IRD_RO
+#define R_USB_EPID_ATTN__WR REG_WR_RO
+#define R_USB_EPID_ATTN__IWR REG_IWR_RO
+
+#define R_USB_EPID_ATTN__READ(addr) \
+ (*(addr))
+
+#define R_USB_EPID_ATTN__value__value__MASK 0xffffffffU
+
+#define R_USB_EPID_ATTN__value__MAX 0xffffffff
+
+#define R_USB_EPID_ATTN__value__MIN 0
+
+#define R_USB_EPID_ATTN__value__BITNR 0
+
+#define R_USB_EPID_ATTN__value__value__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_USB_EPT_DATA
+ * - type: RW
+ * - addr: 0xb000021c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_EPT_DATA__ADDR (REG_TYPECAST_UDWORD 0xb000021c)
+#define R_USB_EPT_DATA__SVAL REG_SVAL_SHADOW
+#define R_USB_EPT_DATA__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_EPT_DATA__TYPECAST REG_TYPECAST_UDWORD
+#define R_USB_EPT_DATA__TYPE (REG_UDWORD)
+#define R_USB_EPT_DATA__GET REG_GET_RW
+#define R_USB_EPT_DATA__IGET REG_IGET_RW
+#define R_USB_EPT_DATA__SET REG_SET_RW
+#define R_USB_EPT_DATA__ISET REG_ISET_RW
+#define R_USB_EPT_DATA__SET_VAL REG_SET_VAL_RW
+#define R_USB_EPT_DATA__EQL REG_EQL_RW
+#define R_USB_EPT_DATA__IEQL REG_IEQL_RW
+#define R_USB_EPT_DATA__RD REG_RD_RW
+#define R_USB_EPT_DATA__IRD REG_IRD_RW
+#define R_USB_EPT_DATA__WR REG_WR_RW
+#define R_USB_EPT_DATA__IWR REG_IWR_RW
+
+#define R_USB_EPT_DATA__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_EPT_DATA__READ(addr) \
+ (*(addr))
+
+#define R_USB_EPT_DATA__valid__valid__MASK 0x80000000U
+#define R_USB_EPT_DATA__hold__hold__MASK 0x40000000U
+#define R_USB_EPT_DATA__error_count_in__error_count_in__MASK 0x30000000U
+#define R_USB_EPT_DATA__t_in__t_in__MASK 0x08000000U
+#define R_USB_EPT_DATA__low_speed__low_speed__MASK 0x04000000U
+#define R_USB_EPT_DATA__port__port__MASK 0x03000000U
+#define R_USB_EPT_DATA__error_code__error_code__MASK 0x00c00000U
+#define R_USB_EPT_DATA__t_out__t_out__MASK 0x00200000U
+#define R_USB_EPT_DATA__error_count_out__error_count_out__MASK 0x00180000U
+#define R_USB_EPT_DATA__max_len__max_len__MASK 0x0003f800U
+#define R_USB_EPT_DATA__ep__ep__MASK 0x00000780U
+#define R_USB_EPT_DATA__dev__dev__MASK 0x0000007fU
+
+#define R_USB_EPT_DATA__valid__MAX 0x1
+#define R_USB_EPT_DATA__hold__MAX 0x1
+#define R_USB_EPT_DATA__error_count_in__MAX 3
+#define R_USB_EPT_DATA__t_in__MAX 1
+#define R_USB_EPT_DATA__low_speed__MAX 0x1
+#define R_USB_EPT_DATA__port__MAX 0x3
+#define R_USB_EPT_DATA__error_code__MAX 0x3
+#define R_USB_EPT_DATA__t_out__MAX 1
+#define R_USB_EPT_DATA__error_count_out__MAX 3
+#define R_USB_EPT_DATA__max_len__MAX 64
+#define R_USB_EPT_DATA__ep__MAX 0xf
+#define R_USB_EPT_DATA__dev__MAX 0x7f
+
+#define R_USB_EPT_DATA__valid__MIN 0
+#define R_USB_EPT_DATA__hold__MIN 0
+#define R_USB_EPT_DATA__error_count_in__MIN 0
+#define R_USB_EPT_DATA__t_in__MIN 0
+#define R_USB_EPT_DATA__low_speed__MIN 0
+#define R_USB_EPT_DATA__port__MIN 0
+#define R_USB_EPT_DATA__error_code__MIN 0
+#define R_USB_EPT_DATA__t_out__MIN 0
+#define R_USB_EPT_DATA__error_count_out__MIN 0
+#define R_USB_EPT_DATA__max_len__MIN 1
+#define R_USB_EPT_DATA__ep__MIN 0
+#define R_USB_EPT_DATA__dev__MIN 0
+
+#define R_USB_EPT_DATA__valid__BITNR 31
+#define R_USB_EPT_DATA__hold__BITNR 30
+#define R_USB_EPT_DATA__error_count_in__BITNR 28
+#define R_USB_EPT_DATA__t_in__BITNR 27
+#define R_USB_EPT_DATA__low_speed__BITNR 26
+#define R_USB_EPT_DATA__port__BITNR 24
+#define R_USB_EPT_DATA__error_code__BITNR 22
+#define R_USB_EPT_DATA__t_out__BITNR 21
+#define R_USB_EPT_DATA__error_count_out__BITNR 19
+#define R_USB_EPT_DATA__max_len__BITNR 11
+#define R_USB_EPT_DATA__ep__BITNR 7
+#define R_USB_EPT_DATA__dev__BITNR 0
+
+#define R_USB_EPT_DATA__valid__valid__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA__hold__hold__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA__error_count_in__error_count_in__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA__t_in__t_in__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA__low_speed__low_speed__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA__port__port__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA__error_code__error_code__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA__t_out__t_out__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA__error_count_out__error_count_out__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA__max_len__max_len__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA__ep__ep__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA__dev__dev__VAL REG_VAL_VAL
+
+#define R_USB_EPT_DATA__valid__valid__no 0
+#define R_USB_EPT_DATA__valid__valid__yes 1
+#define R_USB_EPT_DATA__hold__hold__no 0
+#define R_USB_EPT_DATA__hold__hold__yes 1
+#define R_USB_EPT_DATA__low_speed__low_speed__no 0
+#define R_USB_EPT_DATA__low_speed__low_speed__yes 1
+#define R_USB_EPT_DATA__port__port__any 0
+#define R_USB_EPT_DATA__port__port__p1 1
+#define R_USB_EPT_DATA__port__port__p2 2
+#define R_USB_EPT_DATA__port__port__undef 3
+#define R_USB_EPT_DATA__error_code__error_code__buffer_error 3
+#define R_USB_EPT_DATA__error_code__error_code__bus_error 2
+#define R_USB_EPT_DATA__error_code__error_code__no_error 0
+#define R_USB_EPT_DATA__error_code__error_code__stall 1
+
+#endif
+
+/*
+ * R_USB_EPT_DATA_DEV
+ * - type: RW
+ * - addr: 0xb000021c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_EPT_DATA_DEV__ADDR (REG_TYPECAST_UDWORD 0xb000021c)
+#define R_USB_EPT_DATA_DEV__SVAL REG_SVAL_SHADOW
+#define R_USB_EPT_DATA_DEV__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_EPT_DATA_DEV__TYPECAST REG_TYPECAST_UDWORD
+#define R_USB_EPT_DATA_DEV__TYPE (REG_UDWORD)
+#define R_USB_EPT_DATA_DEV__GET REG_GET_RW
+#define R_USB_EPT_DATA_DEV__IGET REG_IGET_RW
+#define R_USB_EPT_DATA_DEV__SET REG_SET_RW
+#define R_USB_EPT_DATA_DEV__ISET REG_ISET_RW
+#define R_USB_EPT_DATA_DEV__SET_VAL REG_SET_VAL_RW
+#define R_USB_EPT_DATA_DEV__EQL REG_EQL_RW
+#define R_USB_EPT_DATA_DEV__IEQL REG_IEQL_RW
+#define R_USB_EPT_DATA_DEV__RD REG_RD_RW
+#define R_USB_EPT_DATA_DEV__IRD REG_IRD_RW
+#define R_USB_EPT_DATA_DEV__WR REG_WR_RW
+#define R_USB_EPT_DATA_DEV__IWR REG_IWR_RW
+
+#define R_USB_EPT_DATA_DEV__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_EPT_DATA_DEV__READ(addr) \
+ (*(addr))
+
+#define R_USB_EPT_DATA_DEV__valid__valid__MASK 0x80000000U
+#define R_USB_EPT_DATA_DEV__hold__hold__MASK 0x40000000U
+#define R_USB_EPT_DATA_DEV__stall__stall__MASK 0x20000000U
+#define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__MASK 0x10000000U
+#define R_USB_EPT_DATA_DEV__ctrl__ctrl__MASK 0x08000000U
+#define R_USB_EPT_DATA_DEV__iso__iso__MASK 0x04000000U
+#define R_USB_EPT_DATA_DEV__port__port__MASK 0x03000000U
+#define R_USB_EPT_DATA_DEV__control_phase__control_phase__MASK 0x00400000U
+#define R_USB_EPT_DATA_DEV__t__t__MASK 0x00200000U
+#define R_USB_EPT_DATA_DEV__max_len__max_len__MASK 0x001ff800U
+#define R_USB_EPT_DATA_DEV__ep__ep__MASK 0x00000780U
+#define R_USB_EPT_DATA_DEV__dev__dev__MASK 0x0000007fU
+
+#define R_USB_EPT_DATA_DEV__valid__MAX 0x1
+#define R_USB_EPT_DATA_DEV__hold__MAX 0x1
+#define R_USB_EPT_DATA_DEV__stall__MAX 0x1
+#define R_USB_EPT_DATA_DEV__iso_resp__MAX 0x1
+#define R_USB_EPT_DATA_DEV__ctrl__MAX 0x1
+#define R_USB_EPT_DATA_DEV__iso__MAX 0x1
+#define R_USB_EPT_DATA_DEV__port__MAX 0x3
+#define R_USB_EPT_DATA_DEV__control_phase__MAX 0x1
+#define R_USB_EPT_DATA_DEV__t__MAX 1
+#define R_USB_EPT_DATA_DEV__max_len__MAX 1023
+#define R_USB_EPT_DATA_DEV__ep__MAX 15
+#define R_USB_EPT_DATA_DEV__dev__MAX 127
+
+#define R_USB_EPT_DATA_DEV__valid__MIN 0
+#define R_USB_EPT_DATA_DEV__hold__MIN 0
+#define R_USB_EPT_DATA_DEV__stall__MIN 0
+#define R_USB_EPT_DATA_DEV__iso_resp__MIN 0
+#define R_USB_EPT_DATA_DEV__ctrl__MIN 0
+#define R_USB_EPT_DATA_DEV__iso__MIN 0
+#define R_USB_EPT_DATA_DEV__port__MIN 0
+#define R_USB_EPT_DATA_DEV__control_phase__MIN 0
+#define R_USB_EPT_DATA_DEV__t__MIN 0
+#define R_USB_EPT_DATA_DEV__max_len__MIN 1
+#define R_USB_EPT_DATA_DEV__ep__MIN 0
+#define R_USB_EPT_DATA_DEV__dev__MIN 0
+
+#define R_USB_EPT_DATA_DEV__valid__BITNR 31
+#define R_USB_EPT_DATA_DEV__hold__BITNR 30
+#define R_USB_EPT_DATA_DEV__stall__BITNR 29
+#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28
+#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27
+#define R_USB_EPT_DATA_DEV__iso__BITNR 26
+#define R_USB_EPT_DATA_DEV__port__BITNR 24
+#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22
+#define R_USB_EPT_DATA_DEV__t__BITNR 21
+#define R_USB_EPT_DATA_DEV__max_len__BITNR 11
+#define R_USB_EPT_DATA_DEV__ep__BITNR 7
+#define R_USB_EPT_DATA_DEV__dev__BITNR 0
+
+#define R_USB_EPT_DATA_DEV__valid__valid__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_DEV__hold__hold__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_DEV__stall__stall__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_DEV__ctrl__ctrl__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_DEV__iso__iso__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_DEV__port__port__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA_DEV__control_phase__control_phase__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA_DEV__t__t__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA_DEV__max_len__max_len__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA_DEV__ep__ep__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA_DEV__dev__dev__VAL REG_VAL_VAL
+
+#define R_USB_EPT_DATA_DEV__valid__valid__no 0
+#define R_USB_EPT_DATA_DEV__valid__valid__yes 1
+#define R_USB_EPT_DATA_DEV__hold__hold__no 0
+#define R_USB_EPT_DATA_DEV__hold__hold__yes 1
+#define R_USB_EPT_DATA_DEV__stall__stall__no 0
+#define R_USB_EPT_DATA_DEV__stall__stall__yes 1
+#define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__quiet 0
+#define R_USB_EPT_DATA_DEV__iso_resp__iso_resp__yes 1
+#define R_USB_EPT_DATA_DEV__ctrl__ctrl__no 0
+#define R_USB_EPT_DATA_DEV__ctrl__ctrl__yes 1
+#define R_USB_EPT_DATA_DEV__iso__iso__no 0
+#define R_USB_EPT_DATA_DEV__iso__iso__yes 1
+
+#endif
+
+/*
+ * R_USB_EPT_DATA_ISO
+ * - type: RW
+ * - addr: 0xb000021c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_EPT_DATA_ISO__ADDR (REG_TYPECAST_UDWORD 0xb000021c)
+#define R_USB_EPT_DATA_ISO__SVAL REG_SVAL_SHADOW
+#define R_USB_EPT_DATA_ISO__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_EPT_DATA_ISO__TYPECAST REG_TYPECAST_UDWORD
+#define R_USB_EPT_DATA_ISO__TYPE (REG_UDWORD)
+#define R_USB_EPT_DATA_ISO__GET REG_GET_RW
+#define R_USB_EPT_DATA_ISO__IGET REG_IGET_RW
+#define R_USB_EPT_DATA_ISO__SET REG_SET_RW
+#define R_USB_EPT_DATA_ISO__ISET REG_ISET_RW
+#define R_USB_EPT_DATA_ISO__SET_VAL REG_SET_VAL_RW
+#define R_USB_EPT_DATA_ISO__EQL REG_EQL_RW
+#define R_USB_EPT_DATA_ISO__IEQL REG_IEQL_RW
+#define R_USB_EPT_DATA_ISO__RD REG_RD_RW
+#define R_USB_EPT_DATA_ISO__IRD REG_IRD_RW
+#define R_USB_EPT_DATA_ISO__WR REG_WR_RW
+#define R_USB_EPT_DATA_ISO__IWR REG_IWR_RW
+
+#define R_USB_EPT_DATA_ISO__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_EPT_DATA_ISO__READ(addr) \
+ (*(addr))
+
+#define R_USB_EPT_DATA_ISO__valid__valid__MASK 0x80000000U
+#define R_USB_EPT_DATA_ISO__port__port__MASK 0x03000000U
+#define R_USB_EPT_DATA_ISO__error_code__error_code__MASK 0x00c00000U
+#define R_USB_EPT_DATA_ISO__max_len__max_len__MASK 0x001ff800U
+#define R_USB_EPT_DATA_ISO__ep__ep__MASK 0x00000780U
+#define R_USB_EPT_DATA_ISO__dev__dev__MASK 0x0000007fU
+
+#define R_USB_EPT_DATA_ISO__valid__MAX 0x1
+#define R_USB_EPT_DATA_ISO__port__MAX 0x3
+#define R_USB_EPT_DATA_ISO__error_code__MAX 0x3
+#define R_USB_EPT_DATA_ISO__max_len__MAX 1023
+#define R_USB_EPT_DATA_ISO__ep__MAX 0xf
+#define R_USB_EPT_DATA_ISO__dev__MAX 0x7f
+
+#define R_USB_EPT_DATA_ISO__valid__MIN 0
+#define R_USB_EPT_DATA_ISO__port__MIN 0
+#define R_USB_EPT_DATA_ISO__error_code__MIN 0
+#define R_USB_EPT_DATA_ISO__max_len__MIN 1
+#define R_USB_EPT_DATA_ISO__ep__MIN 0
+#define R_USB_EPT_DATA_ISO__dev__MIN 0
+
+#define R_USB_EPT_DATA_ISO__valid__BITNR 31
+#define R_USB_EPT_DATA_ISO__port__BITNR 24
+#define R_USB_EPT_DATA_ISO__error_code__BITNR 22
+#define R_USB_EPT_DATA_ISO__max_len__BITNR 11
+#define R_USB_EPT_DATA_ISO__ep__BITNR 7
+#define R_USB_EPT_DATA_ISO__dev__BITNR 0
+
+#define R_USB_EPT_DATA_ISO__valid__valid__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_ISO__port__port__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_ISO__error_code__error_code__VAL REG_VAL_ENUM
+#define R_USB_EPT_DATA_ISO__max_len__max_len__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA_ISO__ep__ep__VAL REG_VAL_VAL
+#define R_USB_EPT_DATA_ISO__dev__dev__VAL REG_VAL_VAL
+
+#define R_USB_EPT_DATA_ISO__valid__valid__no 0
+#define R_USB_EPT_DATA_ISO__valid__valid__yes 1
+#define R_USB_EPT_DATA_ISO__port__port__any 0
+#define R_USB_EPT_DATA_ISO__port__port__p1 1
+#define R_USB_EPT_DATA_ISO__port__port__p2 2
+#define R_USB_EPT_DATA_ISO__port__port__undef 3
+#define R_USB_EPT_DATA_ISO__error_code__error_code__TBD3 3
+#define R_USB_EPT_DATA_ISO__error_code__error_code__bus_error 2
+#define R_USB_EPT_DATA_ISO__error_code__error_code__no_error 0
+#define R_USB_EPT_DATA_ISO__error_code__error_code__stall 1
+
+#endif
+
+/*
+ * R_USB_EPT_INDEX
+ * - type: RW
+ * - addr: 0xb0000208
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_EPT_INDEX__ADDR (REG_TYPECAST_BYTE 0xb0000208)
+#define R_USB_EPT_INDEX__SVAL REG_SVAL_SHADOW
+#define R_USB_EPT_INDEX__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_EPT_INDEX__TYPECAST REG_TYPECAST_BYTE
+#define R_USB_EPT_INDEX__TYPE (REG_BYTE)
+#define R_USB_EPT_INDEX__GET REG_GET_RW
+#define R_USB_EPT_INDEX__IGET REG_IGET_RW
+#define R_USB_EPT_INDEX__SET REG_SET_RW
+#define R_USB_EPT_INDEX__ISET REG_ISET_RW
+#define R_USB_EPT_INDEX__SET_VAL REG_SET_VAL_RW
+#define R_USB_EPT_INDEX__EQL REG_EQL_RW
+#define R_USB_EPT_INDEX__IEQL REG_IEQL_RW
+#define R_USB_EPT_INDEX__RD REG_RD_RW
+#define R_USB_EPT_INDEX__IRD REG_IRD_RW
+#define R_USB_EPT_INDEX__WR REG_WR_RW
+#define R_USB_EPT_INDEX__IWR REG_IWR_RW
+
+#define R_USB_EPT_INDEX__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_EPT_INDEX__READ(addr) \
+ (*(addr))
+
+#define R_USB_EPT_INDEX__value__value__MASK 0x0000001fU
+
+#define R_USB_EPT_INDEX__value__MAX 31
+
+#define R_USB_EPT_INDEX__value__MIN 0
+
+#define R_USB_EPT_INDEX__value__BITNR 0
+
+#define R_USB_EPT_INDEX__value__value__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_USB_FM_INTERVAL
+ * - type: RW
+ * - addr: 0xb0000210
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_FM_INTERVAL__ADDR (REG_TYPECAST_UWORD 0xb0000210)
+#define R_USB_FM_INTERVAL__SVAL REG_SVAL_SHADOW
+#define R_USB_FM_INTERVAL__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_FM_INTERVAL__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_FM_INTERVAL__TYPE (REG_UWORD)
+#define R_USB_FM_INTERVAL__GET REG_GET_RW
+#define R_USB_FM_INTERVAL__IGET REG_IGET_RW
+#define R_USB_FM_INTERVAL__SET REG_SET_RW
+#define R_USB_FM_INTERVAL__ISET REG_ISET_RW
+#define R_USB_FM_INTERVAL__SET_VAL REG_SET_VAL_RW
+#define R_USB_FM_INTERVAL__EQL REG_EQL_RW
+#define R_USB_FM_INTERVAL__IEQL REG_IEQL_RW
+#define R_USB_FM_INTERVAL__RD REG_RD_RW
+#define R_USB_FM_INTERVAL__IRD REG_IRD_RW
+#define R_USB_FM_INTERVAL__WR REG_WR_RW
+#define R_USB_FM_INTERVAL__IWR REG_IWR_RW
+
+#define R_USB_FM_INTERVAL__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_FM_INTERVAL__READ(addr) \
+ (*(addr))
+
+#define R_USB_FM_INTERVAL__fixed__fixed__MASK 0x00003fc0U
+#define R_USB_FM_INTERVAL__adj__adj__MASK 0x0000003fU
+
+#define R_USB_FM_INTERVAL__fixed__MAX 0xff
+#define R_USB_FM_INTERVAL__adj__MAX 63
+
+#define R_USB_FM_INTERVAL__fixed__MIN 0
+#define R_USB_FM_INTERVAL__adj__MIN 0
+
+#define R_USB_FM_INTERVAL__fixed__BITNR 6
+#define R_USB_FM_INTERVAL__adj__BITNR 0
+
+#define R_USB_FM_INTERVAL__fixed__fixed__VAL REG_VAL_VAL
+#define R_USB_FM_INTERVAL__adj__adj__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_USB_FM_NUMBER
+ * - type: RW
+ * - addr: 0xb000020c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_FM_NUMBER__ADDR (REG_TYPECAST_UDWORD 0xb000020c)
+#define R_USB_FM_NUMBER__SVAL REG_SVAL_SHADOW
+#define R_USB_FM_NUMBER__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_FM_NUMBER__TYPECAST REG_TYPECAST_UDWORD
+#define R_USB_FM_NUMBER__TYPE (REG_UDWORD)
+#define R_USB_FM_NUMBER__GET REG_GET_RW
+#define R_USB_FM_NUMBER__IGET REG_IGET_RW
+#define R_USB_FM_NUMBER__SET REG_SET_RW
+#define R_USB_FM_NUMBER__ISET REG_ISET_RW
+#define R_USB_FM_NUMBER__SET_VAL REG_SET_VAL_RW
+#define R_USB_FM_NUMBER__EQL REG_EQL_RW
+#define R_USB_FM_NUMBER__IEQL REG_IEQL_RW
+#define R_USB_FM_NUMBER__RD REG_RD_RW
+#define R_USB_FM_NUMBER__IRD REG_IRD_RW
+#define R_USB_FM_NUMBER__WR REG_WR_RW
+#define R_USB_FM_NUMBER__IWR REG_IWR_RW
+
+#define R_USB_FM_NUMBER__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_FM_NUMBER__READ(addr) \
+ (*(addr))
+
+#define R_USB_FM_NUMBER__value__value__MASK 0xffffffffU
+
+#define R_USB_FM_NUMBER__value__MAX 0xffffffff
+
+#define R_USB_FM_NUMBER__value__MIN 0
+
+#define R_USB_FM_NUMBER__value__BITNR 0
+
+#define R_USB_FM_NUMBER__value__value__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_USB_FM_NUMBER_DEV
+ * - type: RW
+ * - addr: 0xb000020c
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_FM_NUMBER_DEV__ADDR (REG_TYPECAST_UDWORD 0xb000020c)
+#define R_USB_FM_NUMBER_DEV__SVAL REG_SVAL_SHADOW
+#define R_USB_FM_NUMBER_DEV__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_FM_NUMBER_DEV__TYPECAST REG_TYPECAST_UDWORD
+#define R_USB_FM_NUMBER_DEV__TYPE (REG_UDWORD)
+#define R_USB_FM_NUMBER_DEV__GET REG_GET_RW
+#define R_USB_FM_NUMBER_DEV__IGET REG_IGET_RW
+#define R_USB_FM_NUMBER_DEV__SET REG_SET_RW
+#define R_USB_FM_NUMBER_DEV__ISET REG_ISET_RW
+#define R_USB_FM_NUMBER_DEV__SET_VAL REG_SET_VAL_RW
+#define R_USB_FM_NUMBER_DEV__EQL REG_EQL_RW
+#define R_USB_FM_NUMBER_DEV__IEQL REG_IEQL_RW
+#define R_USB_FM_NUMBER_DEV__RD REG_RD_RW
+#define R_USB_FM_NUMBER_DEV__IRD REG_IRD_RW
+#define R_USB_FM_NUMBER_DEV__WR REG_WR_RW
+#define R_USB_FM_NUMBER_DEV__IWR REG_IWR_RW
+
+#define R_USB_FM_NUMBER_DEV__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_FM_NUMBER_DEV__READ(addr) \
+ (*(addr))
+
+#define R_USB_FM_NUMBER_DEV__sign__sign__MASK 0x80000000U
+#define R_USB_FM_NUMBER_DEV__deviation__deviation__MASK 0x7f000000U
+#define R_USB_FM_NUMBER_DEV__fm_number__fm_number__MASK 0x000007ffU
+
+#define R_USB_FM_NUMBER_DEV__sign__MAX 0x1
+#define R_USB_FM_NUMBER_DEV__deviation__MAX 127
+#define R_USB_FM_NUMBER_DEV__fm_number__MAX 0x7ff
+
+#define R_USB_FM_NUMBER_DEV__sign__MIN 0
+#define R_USB_FM_NUMBER_DEV__deviation__MIN 0
+#define R_USB_FM_NUMBER_DEV__fm_number__MIN 0
+
+#define R_USB_FM_NUMBER_DEV__sign__BITNR 31
+#define R_USB_FM_NUMBER_DEV__deviation__BITNR 24
+#define R_USB_FM_NUMBER_DEV__fm_number__BITNR 0
+
+#define R_USB_FM_NUMBER_DEV__sign__sign__VAL REG_VAL_ENUM
+#define R_USB_FM_NUMBER_DEV__deviation__deviation__VAL REG_VAL_VAL
+#define R_USB_FM_NUMBER_DEV__fm_number__fm_number__VAL REG_VAL_VAL
+
+#define R_USB_FM_NUMBER_DEV__sign__sign__early 0
+#define R_USB_FM_NUMBER_DEV__sign__sign__late 1
+
+#endif
+
+/*
+ * R_USB_FM_PSTART
+ * - type: RW
+ * - addr: 0xb0000214
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_FM_PSTART__ADDR (REG_TYPECAST_UWORD 0xb0000214)
+#define R_USB_FM_PSTART__SVAL REG_SVAL_SHADOW
+#define R_USB_FM_PSTART__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_FM_PSTART__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_FM_PSTART__TYPE (REG_UWORD)
+#define R_USB_FM_PSTART__GET REG_GET_RW
+#define R_USB_FM_PSTART__IGET REG_IGET_RW
+#define R_USB_FM_PSTART__SET REG_SET_RW
+#define R_USB_FM_PSTART__ISET REG_ISET_RW
+#define R_USB_FM_PSTART__SET_VAL REG_SET_VAL_RW
+#define R_USB_FM_PSTART__EQL REG_EQL_RW
+#define R_USB_FM_PSTART__IEQL REG_IEQL_RW
+#define R_USB_FM_PSTART__RD REG_RD_RW
+#define R_USB_FM_PSTART__IRD REG_IRD_RW
+#define R_USB_FM_PSTART__WR REG_WR_RW
+#define R_USB_FM_PSTART__IWR REG_IWR_RW
+
+#define R_USB_FM_PSTART__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_FM_PSTART__READ(addr) \
+ (*(addr))
+
+#define R_USB_FM_PSTART__value__value__MASK 0x00003fffU
+
+#define R_USB_FM_PSTART__value__MAX 0x3fff
+
+#define R_USB_FM_PSTART__value__MIN 0
+
+#define R_USB_FM_PSTART__value__BITNR 0
+
+#define R_USB_FM_PSTART__value__value__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_USB_FM_REMAINING
+ * - type: RO
+ * - addr: 0xb0000212
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_FM_REMAINING__ADDR (REG_TYPECAST_UWORD 0xb0000212)
+#define R_USB_FM_REMAINING__SVAL REG_SVAL_SHADOW
+#define R_USB_FM_REMAINING__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_FM_REMAINING__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_FM_REMAINING__TYPE (REG_UWORD)
+#define R_USB_FM_REMAINING__GET REG_GET_RO
+#define R_USB_FM_REMAINING__IGET REG_IGET_RO
+#define R_USB_FM_REMAINING__SET REG_SET_RO
+#define R_USB_FM_REMAINING__ISET REG_ISET_RO
+#define R_USB_FM_REMAINING__SET_VAL REG_SET_VAL_RO
+#define R_USB_FM_REMAINING__EQL REG_EQL_RO
+#define R_USB_FM_REMAINING__IEQL REG_IEQL_RO
+#define R_USB_FM_REMAINING__RD REG_RD_RO
+#define R_USB_FM_REMAINING__IRD REG_IRD_RO
+#define R_USB_FM_REMAINING__WR REG_WR_RO
+#define R_USB_FM_REMAINING__IWR REG_IWR_RO
+
+#define R_USB_FM_REMAINING__READ(addr) \
+ (*(addr))
+
+#define R_USB_FM_REMAINING__value__value__MASK 0x00003fffU
+
+#define R_USB_FM_REMAINING__value__MAX 0x3fff
+
+#define R_USB_FM_REMAINING__value__MIN 0
+
+#define R_USB_FM_REMAINING__value__BITNR 0
+
+#define R_USB_FM_REMAINING__value__value__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_CLR
+ * - type: WO
+ * - addr: 0xb0000206
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_IRQ_MASK_CLR__ADDR (REG_TYPECAST_UWORD 0xb0000206)
+
+#ifndef REG_NO_SHADOW
+#define R_USB_IRQ_MASK_CLR__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_CLR + 0))
+#define R_USB_IRQ_MASK_CLR__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_CLR + 0))
+#else /* REG_NO_SHADOW */
+#define R_USB_IRQ_MASK_CLR__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_USB_IRQ_MASK_CLR__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_USB_IRQ_MASK_CLR__STYPECAST REG_STYPECAST_UWORD
+#define R_USB_IRQ_MASK_CLR__SVAL REG_SVAL_ZERO
+#define R_USB_IRQ_MASK_CLR__SVAL_I REG_SVAL_I_ZERO
+#define R_USB_IRQ_MASK_CLR__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_IRQ_MASK_CLR__TYPE (REG_UWORD)
+#define R_USB_IRQ_MASK_CLR__GET REG_GET_WO
+#define R_USB_IRQ_MASK_CLR__IGET REG_IGET_WO
+#define R_USB_IRQ_MASK_CLR__SET REG_SET_WO
+#define R_USB_IRQ_MASK_CLR__ISET REG_ISET_WO
+#define R_USB_IRQ_MASK_CLR__SET_VAL REG_SET_VAL_WO
+#define R_USB_IRQ_MASK_CLR__EQL REG_EQL_WO
+#define R_USB_IRQ_MASK_CLR__IEQL REG_IEQL_WO
+#define R_USB_IRQ_MASK_CLR__RD REG_RD_WO
+#define R_USB_IRQ_MASK_CLR__IRD REG_IRD_WO
+#define R_USB_IRQ_MASK_CLR__WR REG_WR_WO
+#define R_USB_IRQ_MASK_CLR__IWR REG_IWR_WO
+
+#define R_USB_IRQ_MASK_CLR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__MASK 0x00002000U
+#define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__MASK 0x00001000U
+#define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__MASK 0x00000800U
+#define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__MASK 0x00000400U
+#define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__MASK 0x00000200U
+#define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__MASK 0x00000100U
+#define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__MASK 0x00000008U
+#define R_USB_IRQ_MASK_CLR__sof__sof__MASK 0x00000004U
+#define R_USB_IRQ_MASK_CLR__port_status__port_status__MASK 0x00000002U
+#define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__MASK 0x00000001U
+
+#define R_USB_IRQ_MASK_CLR__iso_eof__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__intr_eof__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__iso_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__intr_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__ctl_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__bulk_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__epid_attn__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__sof__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__port_status__MAX 0x1
+#define R_USB_IRQ_MASK_CLR__ctl_status__MAX 0x1
+
+#define R_USB_IRQ_MASK_CLR__iso_eof__MIN 0
+#define R_USB_IRQ_MASK_CLR__intr_eof__MIN 0
+#define R_USB_IRQ_MASK_CLR__iso_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR__intr_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR__ctl_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR__bulk_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR__epid_attn__MIN 0
+#define R_USB_IRQ_MASK_CLR__sof__MIN 0
+#define R_USB_IRQ_MASK_CLR__port_status__MIN 0
+#define R_USB_IRQ_MASK_CLR__ctl_status__MIN 0
+
+#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13
+#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11
+#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_CLR__sof__BITNR 2
+#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1
+#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0
+
+#define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__sof__sof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__port_status__port_status__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__VAL REG_VAL_ENUM
+
+#define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__clr 1
+#define R_USB_IRQ_MASK_CLR__iso_eof__iso_eof__nop 0
+#define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__clr 1
+#define R_USB_IRQ_MASK_CLR__intr_eof__intr_eof__nop 0
+#define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__iso_eot__iso_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__intr_eot__intr_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__ctl_eot__ctl_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__bulk_eot__bulk_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__clr 1
+#define R_USB_IRQ_MASK_CLR__epid_attn__epid_attn__nop 0
+#define R_USB_IRQ_MASK_CLR__sof__sof__clr 1
+#define R_USB_IRQ_MASK_CLR__sof__sof__nop 0
+#define R_USB_IRQ_MASK_CLR__port_status__port_status__clr 1
+#define R_USB_IRQ_MASK_CLR__port_status__port_status__nop 0
+#define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__clr 1
+#define R_USB_IRQ_MASK_CLR__ctl_status__ctl_status__nop 0
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_CLR_DEV
+ * - type: WO
+ * - addr: 0xb0000206
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_IRQ_MASK_CLR_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000206)
+
+#ifndef REG_NO_SHADOW
+#define R_USB_IRQ_MASK_CLR_DEV__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_CLR + 0))
+#define R_USB_IRQ_MASK_CLR_DEV__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_CLR + 0))
+#else /* REG_NO_SHADOW */
+#define R_USB_IRQ_MASK_CLR_DEV__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_USB_IRQ_MASK_CLR_DEV__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_USB_IRQ_MASK_CLR_DEV__STYPECAST REG_STYPECAST_UWORD
+#define R_USB_IRQ_MASK_CLR_DEV__SVAL REG_SVAL_SHADOW
+#define R_USB_IRQ_MASK_CLR_DEV__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_IRQ_MASK_CLR_DEV__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_IRQ_MASK_CLR_DEV__TYPE (REG_UWORD)
+#define R_USB_IRQ_MASK_CLR_DEV__GET REG_GET_WO
+#define R_USB_IRQ_MASK_CLR_DEV__IGET REG_IGET_WO
+#define R_USB_IRQ_MASK_CLR_DEV__SET REG_SET_WO
+#define R_USB_IRQ_MASK_CLR_DEV__ISET REG_ISET_WO
+#define R_USB_IRQ_MASK_CLR_DEV__SET_VAL REG_SET_VAL_WO
+#define R_USB_IRQ_MASK_CLR_DEV__EQL REG_EQL_WO
+#define R_USB_IRQ_MASK_CLR_DEV__IEQL REG_IEQL_WO
+#define R_USB_IRQ_MASK_CLR_DEV__RD REG_RD_WO
+#define R_USB_IRQ_MASK_CLR_DEV__IRD REG_IRD_WO
+#define R_USB_IRQ_MASK_CLR_DEV__WR REG_WR_WO
+#define R_USB_IRQ_MASK_CLR_DEV__IWR REG_IWR_WO
+
+#define R_USB_IRQ_MASK_CLR_DEV__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__MASK 0x00001000U
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__MASK 0x00000008U
+#define R_USB_IRQ_MASK_CLR_DEV__sof__sof__MASK 0x00000004U
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__MASK 0x00000002U
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__MASK 0x00000001U
+
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__MAX 0x1
+#define R_USB_IRQ_MASK_CLR_DEV__sof__MAX 0x1
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__MAX 0x1
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__MAX 0x1
+
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__MIN 0
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__MIN 0
+#define R_USB_IRQ_MASK_CLR_DEV__sof__MIN 0
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__MIN 0
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__MIN 0
+
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0
+
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR_DEV__sof__sof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM
+
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__out_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__ep3_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__ep2_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__ep1_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__ep0_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__epid_attn__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__sof__sof__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__sof__sof__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__port_status__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__ctl_status__nop 0
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_READ
+ * - type: RO
+ * - addr: 0xb0000204
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_IRQ_MASK_READ__ADDR (REG_TYPECAST_UWORD 0xb0000204)
+#define R_USB_IRQ_MASK_READ__SVAL REG_SVAL_SHADOW
+#define R_USB_IRQ_MASK_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_IRQ_MASK_READ__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_IRQ_MASK_READ__TYPE (REG_UWORD)
+#define R_USB_IRQ_MASK_READ__GET REG_GET_RO
+#define R_USB_IRQ_MASK_READ__IGET REG_IGET_RO
+#define R_USB_IRQ_MASK_READ__SET REG_SET_RO
+#define R_USB_IRQ_MASK_READ__ISET REG_ISET_RO
+#define R_USB_IRQ_MASK_READ__SET_VAL REG_SET_VAL_RO
+#define R_USB_IRQ_MASK_READ__EQL REG_EQL_RO
+#define R_USB_IRQ_MASK_READ__IEQL REG_IEQL_RO
+#define R_USB_IRQ_MASK_READ__RD REG_RD_RO
+#define R_USB_IRQ_MASK_READ__IRD REG_IRD_RO
+#define R_USB_IRQ_MASK_READ__WR REG_WR_RO
+#define R_USB_IRQ_MASK_READ__IWR REG_IWR_RO
+
+#define R_USB_IRQ_MASK_READ__READ(addr) \
+ (*(addr))
+
+#define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__MASK 0x00002000U
+#define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__MASK 0x00001000U
+#define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__MASK 0x00000800U
+#define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__MASK 0x00000400U
+#define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__MASK 0x00000200U
+#define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__MASK 0x00000100U
+#define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__MASK 0x00000008U
+#define R_USB_IRQ_MASK_READ__sof__sof__MASK 0x00000004U
+#define R_USB_IRQ_MASK_READ__port_status__port_status__MASK 0x00000002U
+#define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__MASK 0x00000001U
+
+#define R_USB_IRQ_MASK_READ__iso_eof__MAX 0x1
+#define R_USB_IRQ_MASK_READ__intr_eof__MAX 0x1
+#define R_USB_IRQ_MASK_READ__iso_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ__intr_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ__ctl_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ__bulk_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ__epid_attn__MAX 0x1
+#define R_USB_IRQ_MASK_READ__sof__MAX 0x1
+#define R_USB_IRQ_MASK_READ__port_status__MAX 0x1
+#define R_USB_IRQ_MASK_READ__ctl_status__MAX 0x1
+
+#define R_USB_IRQ_MASK_READ__iso_eof__MIN 0
+#define R_USB_IRQ_MASK_READ__intr_eof__MIN 0
+#define R_USB_IRQ_MASK_READ__iso_eot__MIN 0
+#define R_USB_IRQ_MASK_READ__intr_eot__MIN 0
+#define R_USB_IRQ_MASK_READ__ctl_eot__MIN 0
+#define R_USB_IRQ_MASK_READ__bulk_eot__MIN 0
+#define R_USB_IRQ_MASK_READ__epid_attn__MIN 0
+#define R_USB_IRQ_MASK_READ__sof__MIN 0
+#define R_USB_IRQ_MASK_READ__port_status__MIN 0
+#define R_USB_IRQ_MASK_READ__ctl_status__MIN 0
+
+#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13
+#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11
+#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_READ__sof__BITNR 2
+#define R_USB_IRQ_MASK_READ__port_status__BITNR 1
+#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0
+
+#define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__sof__sof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__port_status__port_status__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__VAL REG_VAL_ENUM
+
+#define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__no_pend 0
+#define R_USB_IRQ_MASK_READ__iso_eof__iso_eof__pend 1
+#define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__no_pend 0
+#define R_USB_IRQ_MASK_READ__intr_eof__intr_eof__pend 1
+#define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__iso_eot__iso_eot__pend 1
+#define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__intr_eot__intr_eot__pend 1
+#define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__ctl_eot__ctl_eot__pend 1
+#define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__bulk_eot__bulk_eot__pend 1
+#define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__no_pend 0
+#define R_USB_IRQ_MASK_READ__epid_attn__epid_attn__pend 1
+#define R_USB_IRQ_MASK_READ__sof__sof__no_pend 0
+#define R_USB_IRQ_MASK_READ__sof__sof__pend 1
+#define R_USB_IRQ_MASK_READ__port_status__port_status__no_pend 0
+#define R_USB_IRQ_MASK_READ__port_status__port_status__pend 1
+#define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__no_pend 0
+#define R_USB_IRQ_MASK_READ__ctl_status__ctl_status__pend 1
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_READ_DEV
+ * - type: RO
+ * - addr: 0xb0000204
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_IRQ_MASK_READ_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000204)
+#define R_USB_IRQ_MASK_READ_DEV__SVAL REG_SVAL_SHADOW
+#define R_USB_IRQ_MASK_READ_DEV__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_IRQ_MASK_READ_DEV__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_IRQ_MASK_READ_DEV__TYPE (REG_UWORD)
+#define R_USB_IRQ_MASK_READ_DEV__GET REG_GET_RO
+#define R_USB_IRQ_MASK_READ_DEV__IGET REG_IGET_RO
+#define R_USB_IRQ_MASK_READ_DEV__SET REG_SET_RO
+#define R_USB_IRQ_MASK_READ_DEV__ISET REG_ISET_RO
+#define R_USB_IRQ_MASK_READ_DEV__SET_VAL REG_SET_VAL_RO
+#define R_USB_IRQ_MASK_READ_DEV__EQL REG_EQL_RO
+#define R_USB_IRQ_MASK_READ_DEV__IEQL REG_IEQL_RO
+#define R_USB_IRQ_MASK_READ_DEV__RD REG_RD_RO
+#define R_USB_IRQ_MASK_READ_DEV__IRD REG_IRD_RO
+#define R_USB_IRQ_MASK_READ_DEV__WR REG_WR_RO
+#define R_USB_IRQ_MASK_READ_DEV__IWR REG_IWR_RO
+
+#define R_USB_IRQ_MASK_READ_DEV__READ(addr) \
+ (*(addr))
+
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__MASK 0x00001000U
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__MASK 0x00000008U
+#define R_USB_IRQ_MASK_READ_DEV__sof__sof__MASK 0x00000004U
+#define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__MASK 0x00000002U
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__MASK 0x00000001U
+
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__MAX 0x1
+#define R_USB_IRQ_MASK_READ_DEV__sof__MAX 0x1
+#define R_USB_IRQ_MASK_READ_DEV__port_status__MAX 0x1
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__MAX 0x1
+
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__MIN 0
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__MIN 0
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__MIN 0
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__MIN 0
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__MIN 0
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__MIN 0
+#define R_USB_IRQ_MASK_READ_DEV__sof__MIN 0
+#define R_USB_IRQ_MASK_READ_DEV__port_status__MIN 0
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__MIN 0
+
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0
+
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ_DEV__sof__sof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM
+
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__out_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__ep3_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__ep2_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__ep1_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__ep0_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__epid_attn__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__sof__sof__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__sof__sof__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__port_status__port_status__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__ctl_status__pend 1
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_SET
+ * - type: WO
+ * - addr: 0xb0000204
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_IRQ_MASK_SET__ADDR (REG_TYPECAST_UWORD 0xb0000204)
+
+#ifndef REG_NO_SHADOW
+#define R_USB_IRQ_MASK_SET__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_SET + 0))
+#define R_USB_IRQ_MASK_SET__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_USB_IRQ_MASK_SET__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_USB_IRQ_MASK_SET__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_USB_IRQ_MASK_SET__STYPECAST REG_STYPECAST_UWORD
+#define R_USB_IRQ_MASK_SET__SVAL REG_SVAL_ZERO
+#define R_USB_IRQ_MASK_SET__SVAL_I REG_SVAL_I_ZERO
+#define R_USB_IRQ_MASK_SET__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_IRQ_MASK_SET__TYPE (REG_UWORD)
+#define R_USB_IRQ_MASK_SET__GET REG_GET_WO
+#define R_USB_IRQ_MASK_SET__IGET REG_IGET_WO
+#define R_USB_IRQ_MASK_SET__SET REG_SET_WO
+#define R_USB_IRQ_MASK_SET__ISET REG_ISET_WO
+#define R_USB_IRQ_MASK_SET__SET_VAL REG_SET_VAL_WO
+#define R_USB_IRQ_MASK_SET__EQL REG_EQL_WO
+#define R_USB_IRQ_MASK_SET__IEQL REG_IEQL_WO
+#define R_USB_IRQ_MASK_SET__RD REG_RD_WO
+#define R_USB_IRQ_MASK_SET__IRD REG_IRD_WO
+#define R_USB_IRQ_MASK_SET__WR REG_WR_WO
+#define R_USB_IRQ_MASK_SET__IWR REG_IWR_WO
+
+#define R_USB_IRQ_MASK_SET__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__MASK 0x00002000U
+#define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__MASK 0x00001000U
+#define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__MASK 0x00000800U
+#define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__MASK 0x00000400U
+#define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__MASK 0x00000200U
+#define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__MASK 0x00000100U
+#define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__MASK 0x00000008U
+#define R_USB_IRQ_MASK_SET__sof__sof__MASK 0x00000004U
+#define R_USB_IRQ_MASK_SET__port_status__port_status__MASK 0x00000002U
+#define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__MASK 0x00000001U
+
+#define R_USB_IRQ_MASK_SET__iso_eof__MAX 0x1
+#define R_USB_IRQ_MASK_SET__intr_eof__MAX 0x1
+#define R_USB_IRQ_MASK_SET__iso_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET__intr_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET__ctl_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET__bulk_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET__epid_attn__MAX 0x1
+#define R_USB_IRQ_MASK_SET__sof__MAX 0x1
+#define R_USB_IRQ_MASK_SET__port_status__MAX 0x1
+#define R_USB_IRQ_MASK_SET__ctl_status__MAX 0x1
+
+#define R_USB_IRQ_MASK_SET__iso_eof__MIN 0
+#define R_USB_IRQ_MASK_SET__intr_eof__MIN 0
+#define R_USB_IRQ_MASK_SET__iso_eot__MIN 0
+#define R_USB_IRQ_MASK_SET__intr_eot__MIN 0
+#define R_USB_IRQ_MASK_SET__ctl_eot__MIN 0
+#define R_USB_IRQ_MASK_SET__bulk_eot__MIN 0
+#define R_USB_IRQ_MASK_SET__epid_attn__MIN 0
+#define R_USB_IRQ_MASK_SET__sof__MIN 0
+#define R_USB_IRQ_MASK_SET__port_status__MIN 0
+#define R_USB_IRQ_MASK_SET__ctl_status__MIN 0
+
+#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13
+#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11
+#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_SET__sof__BITNR 2
+#define R_USB_IRQ_MASK_SET__port_status__BITNR 1
+#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0
+
+#define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__sof__sof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__port_status__port_status__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__VAL REG_VAL_ENUM
+
+#define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__nop 0
+#define R_USB_IRQ_MASK_SET__iso_eof__iso_eof__set 1
+#define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__nop 0
+#define R_USB_IRQ_MASK_SET__intr_eof__intr_eof__set 1
+#define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__nop 0
+#define R_USB_IRQ_MASK_SET__iso_eot__iso_eot__set 1
+#define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__nop 0
+#define R_USB_IRQ_MASK_SET__intr_eot__intr_eot__set 1
+#define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__nop 0
+#define R_USB_IRQ_MASK_SET__ctl_eot__ctl_eot__set 1
+#define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__nop 0
+#define R_USB_IRQ_MASK_SET__bulk_eot__bulk_eot__set 1
+#define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__nop 0
+#define R_USB_IRQ_MASK_SET__epid_attn__epid_attn__set 1
+#define R_USB_IRQ_MASK_SET__sof__sof__nop 0
+#define R_USB_IRQ_MASK_SET__sof__sof__set 1
+#define R_USB_IRQ_MASK_SET__port_status__port_status__nop 0
+#define R_USB_IRQ_MASK_SET__port_status__port_status__set 1
+#define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__nop 0
+#define R_USB_IRQ_MASK_SET__ctl_status__ctl_status__set 1
+
+#endif
+
+/*
+ * R_USB_IRQ_MASK_SET_DEV
+ * - type: WO
+ * - addr: 0xb0000204
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_IRQ_MASK_SET_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000204)
+
+#ifndef REG_NO_SHADOW
+#define R_USB_IRQ_MASK_SET_DEV__SADDR (REG_STYPECAST_UWORD (reg_shadow__hwregs.R_USB_IRQ_MASK_SET + 0))
+#define R_USB_IRQ_MASK_SET_DEV__IADDR (REG_STYPECAST_UWORD (reg_initiated__hwregs.R_USB_IRQ_MASK_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_USB_IRQ_MASK_SET_DEV__SADDR (REG_STYPECAST_UWORD (&reg_shadow__hwregs))
+#define R_USB_IRQ_MASK_SET_DEV__IADDR (REG_STYPECAST_UWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_USB_IRQ_MASK_SET_DEV__STYPECAST REG_STYPECAST_UWORD
+#define R_USB_IRQ_MASK_SET_DEV__SVAL REG_SVAL_SHADOW
+#define R_USB_IRQ_MASK_SET_DEV__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_IRQ_MASK_SET_DEV__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_IRQ_MASK_SET_DEV__TYPE (REG_UWORD)
+#define R_USB_IRQ_MASK_SET_DEV__GET REG_GET_WO
+#define R_USB_IRQ_MASK_SET_DEV__IGET REG_IGET_WO
+#define R_USB_IRQ_MASK_SET_DEV__SET REG_SET_WO
+#define R_USB_IRQ_MASK_SET_DEV__ISET REG_ISET_WO
+#define R_USB_IRQ_MASK_SET_DEV__SET_VAL REG_SET_VAL_WO
+#define R_USB_IRQ_MASK_SET_DEV__EQL REG_EQL_WO
+#define R_USB_IRQ_MASK_SET_DEV__IEQL REG_IEQL_WO
+#define R_USB_IRQ_MASK_SET_DEV__RD REG_RD_WO
+#define R_USB_IRQ_MASK_SET_DEV__IRD REG_IRD_WO
+#define R_USB_IRQ_MASK_SET_DEV__WR REG_WR_WO
+#define R_USB_IRQ_MASK_SET_DEV__IWR REG_IWR_WO
+
+#define R_USB_IRQ_MASK_SET_DEV__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__MASK 0x00001000U
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__MASK 0x00000008U
+#define R_USB_IRQ_MASK_SET_DEV__sof__sof__MASK 0x00000004U
+#define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__MASK 0x00000002U
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__MASK 0x00000001U
+
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__MAX 0x1
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__MAX 0x1
+#define R_USB_IRQ_MASK_SET_DEV__sof__MAX 0x1
+#define R_USB_IRQ_MASK_SET_DEV__port_status__MAX 0x1
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__MAX 0x1
+
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__MIN 0
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__MIN 0
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__MIN 0
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__MIN 0
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__MIN 0
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__MIN 0
+#define R_USB_IRQ_MASK_SET_DEV__sof__MIN 0
+#define R_USB_IRQ_MASK_SET_DEV__port_status__MIN 0
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__MIN 0
+
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0
+
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET_DEV__sof__sof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__VAL REG_VAL_ENUM
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM
+
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__out_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__ep3_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__ep2_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__ep1_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__ep0_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__epid_attn__set 1
+#define R_USB_IRQ_MASK_SET_DEV__sof__sof__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__sof__sof__set 1
+#define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__port_status__port_status__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__ctl_status__set 1
+
+#endif
+
+/*
+ * R_USB_IRQ_READ
+ * - type: RO
+ * - addr: 0xb0000206
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_IRQ_READ__ADDR (REG_TYPECAST_UWORD 0xb0000206)
+#define R_USB_IRQ_READ__SVAL REG_SVAL_SHADOW
+#define R_USB_IRQ_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_IRQ_READ__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_IRQ_READ__TYPE (REG_UWORD)
+#define R_USB_IRQ_READ__GET REG_GET_RO
+#define R_USB_IRQ_READ__IGET REG_IGET_RO
+#define R_USB_IRQ_READ__SET REG_SET_RO
+#define R_USB_IRQ_READ__ISET REG_ISET_RO
+#define R_USB_IRQ_READ__SET_VAL REG_SET_VAL_RO
+#define R_USB_IRQ_READ__EQL REG_EQL_RO
+#define R_USB_IRQ_READ__IEQL REG_IEQL_RO
+#define R_USB_IRQ_READ__RD REG_RD_RO
+#define R_USB_IRQ_READ__IRD REG_IRD_RO
+#define R_USB_IRQ_READ__WR REG_WR_RO
+#define R_USB_IRQ_READ__IWR REG_IWR_RO
+
+#define R_USB_IRQ_READ__READ(addr) \
+ (*(addr))
+
+#define R_USB_IRQ_READ__iso_eof__iso_eof__MASK 0x00002000U
+#define R_USB_IRQ_READ__intr_eof__intr_eof__MASK 0x00001000U
+#define R_USB_IRQ_READ__iso_eot__iso_eot__MASK 0x00000800U
+#define R_USB_IRQ_READ__intr_eot__intr_eot__MASK 0x00000400U
+#define R_USB_IRQ_READ__ctl_eot__ctl_eot__MASK 0x00000200U
+#define R_USB_IRQ_READ__bulk_eot__bulk_eot__MASK 0x00000100U
+#define R_USB_IRQ_READ__epid_attn__epid_attn__MASK 0x00000008U
+#define R_USB_IRQ_READ__sof__sof__MASK 0x00000004U
+#define R_USB_IRQ_READ__port_status__port_status__MASK 0x00000002U
+#define R_USB_IRQ_READ__ctl_status__ctl_status__MASK 0x00000001U
+
+#define R_USB_IRQ_READ__iso_eof__MAX 0x1
+#define R_USB_IRQ_READ__intr_eof__MAX 0x1
+#define R_USB_IRQ_READ__iso_eot__MAX 0x1
+#define R_USB_IRQ_READ__intr_eot__MAX 0x1
+#define R_USB_IRQ_READ__ctl_eot__MAX 0x1
+#define R_USB_IRQ_READ__bulk_eot__MAX 0x1
+#define R_USB_IRQ_READ__epid_attn__MAX 0x1
+#define R_USB_IRQ_READ__sof__MAX 0x1
+#define R_USB_IRQ_READ__port_status__MAX 0x1
+#define R_USB_IRQ_READ__ctl_status__MAX 0x1
+
+#define R_USB_IRQ_READ__iso_eof__MIN 0
+#define R_USB_IRQ_READ__intr_eof__MIN 0
+#define R_USB_IRQ_READ__iso_eot__MIN 0
+#define R_USB_IRQ_READ__intr_eot__MIN 0
+#define R_USB_IRQ_READ__ctl_eot__MIN 0
+#define R_USB_IRQ_READ__bulk_eot__MIN 0
+#define R_USB_IRQ_READ__epid_attn__MIN 0
+#define R_USB_IRQ_READ__sof__MIN 0
+#define R_USB_IRQ_READ__port_status__MIN 0
+#define R_USB_IRQ_READ__ctl_status__MIN 0
+
+#define R_USB_IRQ_READ__iso_eof__BITNR 13
+#define R_USB_IRQ_READ__intr_eof__BITNR 12
+#define R_USB_IRQ_READ__iso_eot__BITNR 11
+#define R_USB_IRQ_READ__intr_eot__BITNR 10
+#define R_USB_IRQ_READ__ctl_eot__BITNR 9
+#define R_USB_IRQ_READ__bulk_eot__BITNR 8
+#define R_USB_IRQ_READ__epid_attn__BITNR 3
+#define R_USB_IRQ_READ__sof__BITNR 2
+#define R_USB_IRQ_READ__port_status__BITNR 1
+#define R_USB_IRQ_READ__ctl_status__BITNR 0
+
+#define R_USB_IRQ_READ__iso_eof__iso_eof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__intr_eof__intr_eof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__iso_eot__iso_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__intr_eot__intr_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__ctl_eot__ctl_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__bulk_eot__bulk_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__epid_attn__epid_attn__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__sof__sof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__port_status__port_status__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ__ctl_status__ctl_status__VAL REG_VAL_ENUM
+
+#define R_USB_IRQ_READ__iso_eof__iso_eof__no_pend 0
+#define R_USB_IRQ_READ__iso_eof__iso_eof__pend 1
+#define R_USB_IRQ_READ__intr_eof__intr_eof__no_pend 0
+#define R_USB_IRQ_READ__intr_eof__intr_eof__pend 1
+#define R_USB_IRQ_READ__iso_eot__iso_eot__no_pend 0
+#define R_USB_IRQ_READ__iso_eot__iso_eot__pend 1
+#define R_USB_IRQ_READ__intr_eot__intr_eot__no_pend 0
+#define R_USB_IRQ_READ__intr_eot__intr_eot__pend 1
+#define R_USB_IRQ_READ__ctl_eot__ctl_eot__no_pend 0
+#define R_USB_IRQ_READ__ctl_eot__ctl_eot__pend 1
+#define R_USB_IRQ_READ__bulk_eot__bulk_eot__no_pend 0
+#define R_USB_IRQ_READ__bulk_eot__bulk_eot__pend 1
+#define R_USB_IRQ_READ__epid_attn__epid_attn__no_pend 0
+#define R_USB_IRQ_READ__epid_attn__epid_attn__pend 1
+#define R_USB_IRQ_READ__sof__sof__no_pend 0
+#define R_USB_IRQ_READ__sof__sof__pend 1
+#define R_USB_IRQ_READ__port_status__port_status__no_pend 0
+#define R_USB_IRQ_READ__port_status__port_status__pend 1
+#define R_USB_IRQ_READ__ctl_status__ctl_status__no_pend 0
+#define R_USB_IRQ_READ__ctl_status__ctl_status__pend 1
+
+#endif
+
+/*
+ * R_USB_IRQ_READ_DEV
+ * - type: RO
+ * - addr: 0xb0000206
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_IRQ_READ_DEV__ADDR (REG_TYPECAST_UWORD 0xb0000206)
+#define R_USB_IRQ_READ_DEV__SVAL REG_SVAL_SHADOW
+#define R_USB_IRQ_READ_DEV__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_IRQ_READ_DEV__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_IRQ_READ_DEV__TYPE (REG_UWORD)
+#define R_USB_IRQ_READ_DEV__GET REG_GET_RO
+#define R_USB_IRQ_READ_DEV__IGET REG_IGET_RO
+#define R_USB_IRQ_READ_DEV__SET REG_SET_RO
+#define R_USB_IRQ_READ_DEV__ISET REG_ISET_RO
+#define R_USB_IRQ_READ_DEV__SET_VAL REG_SET_VAL_RO
+#define R_USB_IRQ_READ_DEV__EQL REG_EQL_RO
+#define R_USB_IRQ_READ_DEV__IEQL REG_IEQL_RO
+#define R_USB_IRQ_READ_DEV__RD REG_RD_RO
+#define R_USB_IRQ_READ_DEV__IRD REG_IRD_RO
+#define R_USB_IRQ_READ_DEV__WR REG_WR_RO
+#define R_USB_IRQ_READ_DEV__IWR REG_IWR_RO
+
+#define R_USB_IRQ_READ_DEV__READ(addr) \
+ (*(addr))
+
+#define R_USB_IRQ_READ_DEV__out_eot__out_eot__MASK 0x00001000U
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__MASK 0x00000800U
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__MASK 0x00000400U
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__MASK 0x00000200U
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__MASK 0x00000100U
+#define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__MASK 0x00000008U
+#define R_USB_IRQ_READ_DEV__sof__sof__MASK 0x00000004U
+#define R_USB_IRQ_READ_DEV__port_status__port_status__MASK 0x00000002U
+#define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__MASK 0x00000001U
+
+#define R_USB_IRQ_READ_DEV__out_eot__MAX 0x1
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__MAX 0x1
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__MAX 0x1
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__MAX 0x1
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__MAX 0x1
+#define R_USB_IRQ_READ_DEV__epid_attn__MAX 0x1
+#define R_USB_IRQ_READ_DEV__sof__MAX 0x1
+#define R_USB_IRQ_READ_DEV__port_status__MAX 0x1
+#define R_USB_IRQ_READ_DEV__ctl_status__MAX 0x1
+
+#define R_USB_IRQ_READ_DEV__out_eot__MIN 0
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__MIN 0
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__MIN 0
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__MIN 0
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__MIN 0
+#define R_USB_IRQ_READ_DEV__epid_attn__MIN 0
+#define R_USB_IRQ_READ_DEV__sof__MIN 0
+#define R_USB_IRQ_READ_DEV__port_status__MIN 0
+#define R_USB_IRQ_READ_DEV__ctl_status__MIN 0
+
+#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_READ_DEV__sof__BITNR 2
+#define R_USB_IRQ_READ_DEV__port_status__BITNR 1
+#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0
+
+#define R_USB_IRQ_READ_DEV__out_eot__out_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ_DEV__sof__sof__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ_DEV__port_status__port_status__VAL REG_VAL_ENUM
+#define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__VAL REG_VAL_ENUM
+
+#define R_USB_IRQ_READ_DEV__out_eot__out_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__out_eot__out_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__ep3_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__ep2_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__ep1_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__ep0_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__no_pend 0
+#define R_USB_IRQ_READ_DEV__epid_attn__epid_attn__pend 1
+#define R_USB_IRQ_READ_DEV__sof__sof__no_pend 0
+#define R_USB_IRQ_READ_DEV__sof__sof__pend 1
+#define R_USB_IRQ_READ_DEV__port_status__port_status__no_pend 0
+#define R_USB_IRQ_READ_DEV__port_status__port_status__pend 1
+#define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__no_pend 0
+#define R_USB_IRQ_READ_DEV__ctl_status__ctl_status__pend 1
+
+#endif
+
+/*
+ * R_USB_PORT1_DISABLE
+ * - type: WO
+ * - addr: 0xb000006a
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_PORT1_DISABLE__ADDR (REG_TYPECAST_BYTE 0xb000006a)
+
+#ifndef REG_NO_SHADOW
+#define R_USB_PORT1_DISABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_SERIAL1_CTRL + 2))
+#define R_USB_PORT1_DISABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_SERIAL1_CTRL + 2))
+#else /* REG_NO_SHADOW */
+#define R_USB_PORT1_DISABLE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_USB_PORT1_DISABLE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_USB_PORT1_DISABLE__STYPECAST REG_STYPECAST_BYTE
+#define R_USB_PORT1_DISABLE__SVAL REG_SVAL_SHADOW
+#define R_USB_PORT1_DISABLE__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_PORT1_DISABLE__TYPECAST REG_TYPECAST_BYTE
+#define R_USB_PORT1_DISABLE__TYPE (REG_BYTE)
+#define R_USB_PORT1_DISABLE__GET REG_GET_WO
+#define R_USB_PORT1_DISABLE__IGET REG_IGET_WO
+#define R_USB_PORT1_DISABLE__SET REG_SET_WO
+#define R_USB_PORT1_DISABLE__ISET REG_ISET_WO
+#define R_USB_PORT1_DISABLE__SET_VAL REG_SET_VAL_WO
+#define R_USB_PORT1_DISABLE__EQL REG_EQL_WO
+#define R_USB_PORT1_DISABLE__IEQL REG_IEQL_WO
+#define R_USB_PORT1_DISABLE__RD REG_RD_WO
+#define R_USB_PORT1_DISABLE__IRD REG_IRD_WO
+#define R_USB_PORT1_DISABLE__WR REG_WR_WO
+#define R_USB_PORT1_DISABLE__IWR REG_IWR_WO
+
+#define R_USB_PORT1_DISABLE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_USB_PORT1_DISABLE__disable__disable__MASK 0x00000001U
+
+#define R_USB_PORT1_DISABLE__disable__MAX 0x1
+
+#define R_USB_PORT1_DISABLE__disable__MIN 0
+
+#define R_USB_PORT1_DISABLE__disable__BITNR 0
+
+#define R_USB_PORT1_DISABLE__disable__disable__VAL REG_VAL_ENUM
+
+#define R_USB_PORT1_DISABLE__disable__disable__no 1
+#define R_USB_PORT1_DISABLE__disable__disable__yes 0
+
+#endif
+
+/*
+ * R_USB_PORT2_DISABLE
+ * - type: WO
+ * - addr: 0xb0000052
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_PORT2_DISABLE__ADDR (REG_TYPECAST_BYTE 0xb0000052)
+
+#ifndef REG_NO_SHADOW
+#define R_USB_PORT2_DISABLE__SADDR (REG_STYPECAST_BYTE (reg_shadow__hwregs.R_PAR1_CTRL_DATA + 2))
+#define R_USB_PORT2_DISABLE__IADDR (REG_STYPECAST_BYTE (reg_initiated__hwregs.R_PAR1_CTRL_DATA + 2))
+#else /* REG_NO_SHADOW */
+#define R_USB_PORT2_DISABLE__SADDR (REG_STYPECAST_BYTE (&reg_shadow__hwregs))
+#define R_USB_PORT2_DISABLE__IADDR (REG_STYPECAST_BYTE (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_USB_PORT2_DISABLE__STYPECAST REG_STYPECAST_BYTE
+#define R_USB_PORT2_DISABLE__SVAL REG_SVAL_SHADOW
+#define R_USB_PORT2_DISABLE__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_PORT2_DISABLE__TYPECAST REG_TYPECAST_BYTE
+#define R_USB_PORT2_DISABLE__TYPE (REG_BYTE)
+#define R_USB_PORT2_DISABLE__GET REG_GET_WO
+#define R_USB_PORT2_DISABLE__IGET REG_IGET_WO
+#define R_USB_PORT2_DISABLE__SET REG_SET_WO
+#define R_USB_PORT2_DISABLE__ISET REG_ISET_WO
+#define R_USB_PORT2_DISABLE__SET_VAL REG_SET_VAL_WO
+#define R_USB_PORT2_DISABLE__EQL REG_EQL_WO
+#define R_USB_PORT2_DISABLE__IEQL REG_IEQL_WO
+#define R_USB_PORT2_DISABLE__RD REG_RD_WO
+#define R_USB_PORT2_DISABLE__IRD REG_IRD_WO
+#define R_USB_PORT2_DISABLE__WR REG_WR_WO
+#define R_USB_PORT2_DISABLE__IWR REG_IWR_WO
+
+#define R_USB_PORT2_DISABLE__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_USB_PORT2_DISABLE__disable__disable__MASK 0x00000001U
+
+#define R_USB_PORT2_DISABLE__disable__MAX 0x1
+
+#define R_USB_PORT2_DISABLE__disable__MIN 0
+
+#define R_USB_PORT2_DISABLE__disable__BITNR 0
+
+#define R_USB_PORT2_DISABLE__disable__disable__VAL REG_VAL_ENUM
+
+#define R_USB_PORT2_DISABLE__disable__disable__no 1
+#define R_USB_PORT2_DISABLE__disable__disable__yes 0
+
+#endif
+
+/*
+ * R_USB_REVISION
+ * - type: RO
+ * - addr: 0xb0000200
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_REVISION__ADDR (REG_TYPECAST_BYTE 0xb0000200)
+#define R_USB_REVISION__SVAL REG_SVAL_SHADOW
+#define R_USB_REVISION__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_REVISION__TYPECAST REG_TYPECAST_BYTE
+#define R_USB_REVISION__TYPE (REG_BYTE)
+#define R_USB_REVISION__GET REG_GET_RO
+#define R_USB_REVISION__IGET REG_IGET_RO
+#define R_USB_REVISION__SET REG_SET_RO
+#define R_USB_REVISION__ISET REG_ISET_RO
+#define R_USB_REVISION__SET_VAL REG_SET_VAL_RO
+#define R_USB_REVISION__EQL REG_EQL_RO
+#define R_USB_REVISION__IEQL REG_IEQL_RO
+#define R_USB_REVISION__RD REG_RD_RO
+#define R_USB_REVISION__IRD REG_IRD_RO
+#define R_USB_REVISION__WR REG_WR_RO
+#define R_USB_REVISION__IWR REG_IWR_RO
+
+#define R_USB_REVISION__READ(addr) \
+ (*(addr))
+
+#define R_USB_REVISION__major__major__MASK 0x000000f0U
+#define R_USB_REVISION__minor__minor__MASK 0x0000000fU
+
+#define R_USB_REVISION__major__MAX 0xf
+#define R_USB_REVISION__minor__MAX 0xf
+
+#define R_USB_REVISION__major__MIN 0
+#define R_USB_REVISION__minor__MIN 0
+
+#define R_USB_REVISION__major__BITNR 4
+#define R_USB_REVISION__minor__BITNR 0
+
+#define R_USB_REVISION__major__major__VAL REG_VAL_VAL
+#define R_USB_REVISION__minor__minor__VAL REG_VAL_ENUM
+
+#define R_USB_REVISION__minor__minor__v1_v2 1
+#define R_USB_REVISION__minor__minor__v3 0
+
+#endif
+
+/*
+ * R_USB_RH_PORT_STATUS_1
+ * - type: RO
+ * - addr: 0xb0000218
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_RH_PORT_STATUS_1__ADDR (REG_TYPECAST_UWORD 0xb0000218)
+#define R_USB_RH_PORT_STATUS_1__SVAL REG_SVAL_SHADOW
+#define R_USB_RH_PORT_STATUS_1__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_RH_PORT_STATUS_1__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_RH_PORT_STATUS_1__TYPE (REG_UWORD)
+#define R_USB_RH_PORT_STATUS_1__GET REG_GET_RO
+#define R_USB_RH_PORT_STATUS_1__IGET REG_IGET_RO
+#define R_USB_RH_PORT_STATUS_1__SET REG_SET_RO
+#define R_USB_RH_PORT_STATUS_1__ISET REG_ISET_RO
+#define R_USB_RH_PORT_STATUS_1__SET_VAL REG_SET_VAL_RO
+#define R_USB_RH_PORT_STATUS_1__EQL REG_EQL_RO
+#define R_USB_RH_PORT_STATUS_1__IEQL REG_IEQL_RO
+#define R_USB_RH_PORT_STATUS_1__RD REG_RD_RO
+#define R_USB_RH_PORT_STATUS_1__IRD REG_IRD_RO
+#define R_USB_RH_PORT_STATUS_1__WR REG_WR_RO
+#define R_USB_RH_PORT_STATUS_1__IWR REG_IWR_RO
+
+#define R_USB_RH_PORT_STATUS_1__READ(addr) \
+ (*(addr))
+
+#define R_USB_RH_PORT_STATUS_1__speed__speed__MASK 0x00000200U
+#define R_USB_RH_PORT_STATUS_1__power__power__MASK 0x00000100U
+#define R_USB_RH_PORT_STATUS_1__reset__reset__MASK 0x00000010U
+#define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__MASK 0x00000008U
+#define R_USB_RH_PORT_STATUS_1__suspended__suspended__MASK 0x00000004U
+#define R_USB_RH_PORT_STATUS_1__enabled__enabled__MASK 0x00000002U
+#define R_USB_RH_PORT_STATUS_1__connected__connected__MASK 0x00000001U
+
+#define R_USB_RH_PORT_STATUS_1__speed__MAX 0x1
+#define R_USB_RH_PORT_STATUS_1__power__MAX 0x1
+#define R_USB_RH_PORT_STATUS_1__reset__MAX 0x1
+#define R_USB_RH_PORT_STATUS_1__overcurrent__MAX 0x1
+#define R_USB_RH_PORT_STATUS_1__suspended__MAX 0x1
+#define R_USB_RH_PORT_STATUS_1__enabled__MAX 0x1
+#define R_USB_RH_PORT_STATUS_1__connected__MAX 0x1
+
+#define R_USB_RH_PORT_STATUS_1__speed__MIN 0
+#define R_USB_RH_PORT_STATUS_1__power__MIN 0
+#define R_USB_RH_PORT_STATUS_1__reset__MIN 0
+#define R_USB_RH_PORT_STATUS_1__overcurrent__MIN 0
+#define R_USB_RH_PORT_STATUS_1__suspended__MIN 0
+#define R_USB_RH_PORT_STATUS_1__enabled__MIN 0
+#define R_USB_RH_PORT_STATUS_1__connected__MIN 0
+
+#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9
+#define R_USB_RH_PORT_STATUS_1__power__BITNR 8
+#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4
+#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3
+#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2
+#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1
+#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0
+
+#define R_USB_RH_PORT_STATUS_1__speed__speed__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_1__power__power__VAL REG_VAL_VAL
+#define R_USB_RH_PORT_STATUS_1__reset__reset__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_1__suspended__suspended__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_1__enabled__enabled__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_1__connected__connected__VAL REG_VAL_ENUM
+
+#define R_USB_RH_PORT_STATUS_1__speed__speed__full 0
+#define R_USB_RH_PORT_STATUS_1__speed__speed__low 1
+#define R_USB_RH_PORT_STATUS_1__reset__reset__no 0
+#define R_USB_RH_PORT_STATUS_1__reset__reset__yes 1
+#define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__no 0
+#define R_USB_RH_PORT_STATUS_1__overcurrent__overcurrent__yes 1
+#define R_USB_RH_PORT_STATUS_1__suspended__suspended__no 0
+#define R_USB_RH_PORT_STATUS_1__suspended__suspended__yes 1
+#define R_USB_RH_PORT_STATUS_1__enabled__enabled__no 0
+#define R_USB_RH_PORT_STATUS_1__enabled__enabled__yes 1
+#define R_USB_RH_PORT_STATUS_1__connected__connected__no 0
+#define R_USB_RH_PORT_STATUS_1__connected__connected__yes 1
+
+#endif
+
+/*
+ * R_USB_RH_PORT_STATUS_2
+ * - type: RO
+ * - addr: 0xb000021a
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_RH_PORT_STATUS_2__ADDR (REG_TYPECAST_UWORD 0xb000021a)
+#define R_USB_RH_PORT_STATUS_2__SVAL REG_SVAL_SHADOW
+#define R_USB_RH_PORT_STATUS_2__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_RH_PORT_STATUS_2__TYPECAST REG_TYPECAST_UWORD
+#define R_USB_RH_PORT_STATUS_2__TYPE (REG_UWORD)
+#define R_USB_RH_PORT_STATUS_2__GET REG_GET_RO
+#define R_USB_RH_PORT_STATUS_2__IGET REG_IGET_RO
+#define R_USB_RH_PORT_STATUS_2__SET REG_SET_RO
+#define R_USB_RH_PORT_STATUS_2__ISET REG_ISET_RO
+#define R_USB_RH_PORT_STATUS_2__SET_VAL REG_SET_VAL_RO
+#define R_USB_RH_PORT_STATUS_2__EQL REG_EQL_RO
+#define R_USB_RH_PORT_STATUS_2__IEQL REG_IEQL_RO
+#define R_USB_RH_PORT_STATUS_2__RD REG_RD_RO
+#define R_USB_RH_PORT_STATUS_2__IRD REG_IRD_RO
+#define R_USB_RH_PORT_STATUS_2__WR REG_WR_RO
+#define R_USB_RH_PORT_STATUS_2__IWR REG_IWR_RO
+
+#define R_USB_RH_PORT_STATUS_2__READ(addr) \
+ (*(addr))
+
+#define R_USB_RH_PORT_STATUS_2__speed__speed__MASK 0x00000200U
+#define R_USB_RH_PORT_STATUS_2__power__power__MASK 0x00000100U
+#define R_USB_RH_PORT_STATUS_2__reset__reset__MASK 0x00000010U
+#define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__MASK 0x00000008U
+#define R_USB_RH_PORT_STATUS_2__suspended__suspended__MASK 0x00000004U
+#define R_USB_RH_PORT_STATUS_2__enabled__enabled__MASK 0x00000002U
+#define R_USB_RH_PORT_STATUS_2__connected__connected__MASK 0x00000001U
+
+#define R_USB_RH_PORT_STATUS_2__speed__MAX 0x1
+#define R_USB_RH_PORT_STATUS_2__power__MAX 0x1
+#define R_USB_RH_PORT_STATUS_2__reset__MAX 0x1
+#define R_USB_RH_PORT_STATUS_2__overcurrent__MAX 0x1
+#define R_USB_RH_PORT_STATUS_2__suspended__MAX 0x1
+#define R_USB_RH_PORT_STATUS_2__enabled__MAX 0x1
+#define R_USB_RH_PORT_STATUS_2__connected__MAX 0x1
+
+#define R_USB_RH_PORT_STATUS_2__speed__MIN 0
+#define R_USB_RH_PORT_STATUS_2__power__MIN 0
+#define R_USB_RH_PORT_STATUS_2__reset__MIN 0
+#define R_USB_RH_PORT_STATUS_2__overcurrent__MIN 0
+#define R_USB_RH_PORT_STATUS_2__suspended__MIN 0
+#define R_USB_RH_PORT_STATUS_2__enabled__MIN 0
+#define R_USB_RH_PORT_STATUS_2__connected__MIN 0
+
+#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9
+#define R_USB_RH_PORT_STATUS_2__power__BITNR 8
+#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4
+#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3
+#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2
+#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1
+#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0
+
+#define R_USB_RH_PORT_STATUS_2__speed__speed__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_2__power__power__VAL REG_VAL_VAL
+#define R_USB_RH_PORT_STATUS_2__reset__reset__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_2__suspended__suspended__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_2__enabled__enabled__VAL REG_VAL_ENUM
+#define R_USB_RH_PORT_STATUS_2__connected__connected__VAL REG_VAL_ENUM
+
+#define R_USB_RH_PORT_STATUS_2__speed__speed__full 0
+#define R_USB_RH_PORT_STATUS_2__speed__speed__low 1
+#define R_USB_RH_PORT_STATUS_2__reset__reset__no 0
+#define R_USB_RH_PORT_STATUS_2__reset__reset__yes 1
+#define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__no 0
+#define R_USB_RH_PORT_STATUS_2__overcurrent__overcurrent__yes 1
+#define R_USB_RH_PORT_STATUS_2__suspended__suspended__no 0
+#define R_USB_RH_PORT_STATUS_2__suspended__suspended__yes 1
+#define R_USB_RH_PORT_STATUS_2__enabled__enabled__no 0
+#define R_USB_RH_PORT_STATUS_2__enabled__enabled__yes 1
+#define R_USB_RH_PORT_STATUS_2__connected__connected__no 0
+#define R_USB_RH_PORT_STATUS_2__connected__connected__yes 1
+
+#endif
+
+/*
+ * R_USB_RH_STATUS
+ * - type: RO
+ * - addr: 0xb0000203
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_RH_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000203)
+#define R_USB_RH_STATUS__SVAL REG_SVAL_SHADOW
+#define R_USB_RH_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_RH_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_USB_RH_STATUS__TYPE (REG_BYTE)
+#define R_USB_RH_STATUS__GET REG_GET_RO
+#define R_USB_RH_STATUS__IGET REG_IGET_RO
+#define R_USB_RH_STATUS__SET REG_SET_RO
+#define R_USB_RH_STATUS__ISET REG_ISET_RO
+#define R_USB_RH_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_USB_RH_STATUS__EQL REG_EQL_RO
+#define R_USB_RH_STATUS__IEQL REG_IEQL_RO
+#define R_USB_RH_STATUS__RD REG_RD_RO
+#define R_USB_RH_STATUS__IRD REG_IRD_RO
+#define R_USB_RH_STATUS__WR REG_WR_RO
+#define R_USB_RH_STATUS__IWR REG_IWR_RO
+
+#define R_USB_RH_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_USB_RH_STATUS__babble2__babble2__MASK 0x00000080U
+#define R_USB_RH_STATUS__babble1__babble1__MASK 0x00000040U
+#define R_USB_RH_STATUS__bus1__bus1__MASK 0x00000030U
+#define R_USB_RH_STATUS__bus2__bus2__MASK 0x0000000cU
+#define R_USB_RH_STATUS__nports__nports__MASK 0x00000003U
+
+#define R_USB_RH_STATUS__babble2__MAX 0x1
+#define R_USB_RH_STATUS__babble1__MAX 0x1
+#define R_USB_RH_STATUS__bus1__MAX 0x3
+#define R_USB_RH_STATUS__bus2__MAX 0x3
+#define R_USB_RH_STATUS__nports__MAX 3
+
+#define R_USB_RH_STATUS__babble2__MIN 0
+#define R_USB_RH_STATUS__babble1__MIN 0
+#define R_USB_RH_STATUS__bus1__MIN 0
+#define R_USB_RH_STATUS__bus2__MIN 0
+#define R_USB_RH_STATUS__nports__MIN 0
+
+#define R_USB_RH_STATUS__babble2__BITNR 7
+#define R_USB_RH_STATUS__babble1__BITNR 6
+#define R_USB_RH_STATUS__bus1__BITNR 4
+#define R_USB_RH_STATUS__bus2__BITNR 2
+#define R_USB_RH_STATUS__nports__BITNR 0
+
+#define R_USB_RH_STATUS__babble2__babble2__VAL REG_VAL_ENUM
+#define R_USB_RH_STATUS__babble1__babble1__VAL REG_VAL_ENUM
+#define R_USB_RH_STATUS__bus1__bus1__VAL REG_VAL_ENUM
+#define R_USB_RH_STATUS__bus2__bus2__VAL REG_VAL_ENUM
+#define R_USB_RH_STATUS__nports__nports__VAL REG_VAL_VAL
+
+#define R_USB_RH_STATUS__babble2__babble2__no 0
+#define R_USB_RH_STATUS__babble2__babble2__yes 1
+#define R_USB_RH_STATUS__babble1__babble1__no 0
+#define R_USB_RH_STATUS__babble1__babble1__yes 1
+#define R_USB_RH_STATUS__bus1__bus1__Diff0 1
+#define R_USB_RH_STATUS__bus1__bus1__Diff1 2
+#define R_USB_RH_STATUS__bus1__bus1__SE0 0
+#define R_USB_RH_STATUS__bus1__bus1__SE1 3
+#define R_USB_RH_STATUS__bus2__bus2__Diff0 1
+#define R_USB_RH_STATUS__bus2__bus2__Diff1 2
+#define R_USB_RH_STATUS__bus2__bus2__SE0 0
+#define R_USB_RH_STATUS__bus2__bus2__SE1 3
+
+#endif
+
+/*
+ * R_USB_SNMP_TERROR
+ * - type: RW
+ * - addr: 0xb0000220
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_SNMP_TERROR__ADDR (REG_TYPECAST_UDWORD 0xb0000220)
+#define R_USB_SNMP_TERROR__SVAL REG_SVAL_SHADOW
+#define R_USB_SNMP_TERROR__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_SNMP_TERROR__TYPECAST REG_TYPECAST_UDWORD
+#define R_USB_SNMP_TERROR__TYPE (REG_UDWORD)
+#define R_USB_SNMP_TERROR__GET REG_GET_RW
+#define R_USB_SNMP_TERROR__IGET REG_IGET_RW
+#define R_USB_SNMP_TERROR__SET REG_SET_RW
+#define R_USB_SNMP_TERROR__ISET REG_ISET_RW
+#define R_USB_SNMP_TERROR__SET_VAL REG_SET_VAL_RW
+#define R_USB_SNMP_TERROR__EQL REG_EQL_RW
+#define R_USB_SNMP_TERROR__IEQL REG_IEQL_RW
+#define R_USB_SNMP_TERROR__RD REG_RD_RW
+#define R_USB_SNMP_TERROR__IRD REG_IRD_RW
+#define R_USB_SNMP_TERROR__WR REG_WR_RW
+#define R_USB_SNMP_TERROR__IWR REG_IWR_RW
+
+#define R_USB_SNMP_TERROR__WRITE(addr,value) \
+ (*(addr) = (value))
+#define R_USB_SNMP_TERROR__READ(addr) \
+ (*(addr))
+
+#define R_USB_SNMP_TERROR__value__value__MASK 0xffffffffU
+
+#define R_USB_SNMP_TERROR__value__MAX 0xffffffff
+
+#define R_USB_SNMP_TERROR__value__MIN 0
+
+#define R_USB_SNMP_TERROR__value__BITNR 0
+
+#define R_USB_SNMP_TERROR__value__value__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_USB_STATUS
+ * - type: RO
+ * - addr: 0xb0000202
+ * - group: USB interface control registers
+ */
+
+#if USE_GROUP__USB_interface_control_registers
+
+#define R_USB_STATUS__ADDR (REG_TYPECAST_BYTE 0xb0000202)
+#define R_USB_STATUS__SVAL REG_SVAL_SHADOW
+#define R_USB_STATUS__SVAL_I REG_SVAL_I_SHADOW
+#define R_USB_STATUS__TYPECAST REG_TYPECAST_BYTE
+#define R_USB_STATUS__TYPE (REG_BYTE)
+#define R_USB_STATUS__GET REG_GET_RO
+#define R_USB_STATUS__IGET REG_IGET_RO
+#define R_USB_STATUS__SET REG_SET_RO
+#define R_USB_STATUS__ISET REG_ISET_RO
+#define R_USB_STATUS__SET_VAL REG_SET_VAL_RO
+#define R_USB_STATUS__EQL REG_EQL_RO
+#define R_USB_STATUS__IEQL REG_IEQL_RO
+#define R_USB_STATUS__RD REG_RD_RO
+#define R_USB_STATUS__IRD REG_IRD_RO
+#define R_USB_STATUS__WR REG_WR_RO
+#define R_USB_STATUS__IWR REG_IWR_RO
+
+#define R_USB_STATUS__READ(addr) \
+ (*(addr))
+
+#define R_USB_STATUS__ourun__ourun__MASK 0x00000020U
+#define R_USB_STATUS__perror__perror__MASK 0x00000010U
+#define R_USB_STATUS__device_mode__device_mode__MASK 0x00000008U
+#define R_USB_STATUS__host_mode__host_mode__MASK 0x00000004U
+#define R_USB_STATUS__started__started__MASK 0x00000002U
+#define R_USB_STATUS__running__running__MASK 0x00000001U
+
+#define R_USB_STATUS__ourun__MAX 0x1
+#define R_USB_STATUS__perror__MAX 0x1
+#define R_USB_STATUS__device_mode__MAX 0x1
+#define R_USB_STATUS__host_mode__MAX 0x1
+#define R_USB_STATUS__started__MAX 0x1
+#define R_USB_STATUS__running__MAX 0x1
+
+#define R_USB_STATUS__ourun__MIN 0
+#define R_USB_STATUS__perror__MIN 0
+#define R_USB_STATUS__device_mode__MIN 0
+#define R_USB_STATUS__host_mode__MIN 0
+#define R_USB_STATUS__started__MIN 0
+#define R_USB_STATUS__running__MIN 0
+
+#define R_USB_STATUS__ourun__BITNR 5
+#define R_USB_STATUS__perror__BITNR 4
+#define R_USB_STATUS__device_mode__BITNR 3
+#define R_USB_STATUS__host_mode__BITNR 2
+#define R_USB_STATUS__started__BITNR 1
+#define R_USB_STATUS__running__BITNR 0
+
+#define R_USB_STATUS__ourun__ourun__VAL REG_VAL_ENUM
+#define R_USB_STATUS__perror__perror__VAL REG_VAL_ENUM
+#define R_USB_STATUS__device_mode__device_mode__VAL REG_VAL_ENUM
+#define R_USB_STATUS__host_mode__host_mode__VAL REG_VAL_ENUM
+#define R_USB_STATUS__started__started__VAL REG_VAL_ENUM
+#define R_USB_STATUS__running__running__VAL REG_VAL_ENUM
+
+#define R_USB_STATUS__ourun__ourun__no 0
+#define R_USB_STATUS__ourun__ourun__yes 1
+#define R_USB_STATUS__perror__perror__no 0
+#define R_USB_STATUS__perror__perror__yes 1
+#define R_USB_STATUS__device_mode__device_mode__no 0
+#define R_USB_STATUS__device_mode__device_mode__yes 1
+#define R_USB_STATUS__host_mode__host_mode__no 0
+#define R_USB_STATUS__host_mode__host_mode__yes 1
+#define R_USB_STATUS__started__started__no 0
+#define R_USB_STATUS__started__started__yes 1
+#define R_USB_STATUS__running__running__no 0
+#define R_USB_STATUS__running__running__yes 1
+
+#endif
+
+/*
+ * R_VECT_MASK_CLR
+ * - type: WO
+ * - addr: 0xb00000d8
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_VECT_MASK_CLR__ADDR (REG_TYPECAST_UDWORD 0xb00000d8)
+
+#ifndef REG_NO_SHADOW
+#define R_VECT_MASK_CLR__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_VECT_MASK_CLR + 0))
+#define R_VECT_MASK_CLR__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_VECT_MASK_CLR + 0))
+#else /* REG_NO_SHADOW */
+#define R_VECT_MASK_CLR__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_VECT_MASK_CLR__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_VECT_MASK_CLR__STYPECAST REG_STYPECAST_UDWORD
+#define R_VECT_MASK_CLR__SVAL REG_SVAL_ZERO
+#define R_VECT_MASK_CLR__SVAL_I REG_SVAL_I_ZERO
+#define R_VECT_MASK_CLR__TYPECAST REG_TYPECAST_UDWORD
+#define R_VECT_MASK_CLR__TYPE (REG_UDWORD)
+#define R_VECT_MASK_CLR__GET REG_GET_WO
+#define R_VECT_MASK_CLR__IGET REG_IGET_WO
+#define R_VECT_MASK_CLR__SET REG_SET_WO
+#define R_VECT_MASK_CLR__ISET REG_ISET_WO
+#define R_VECT_MASK_CLR__SET_VAL REG_SET_VAL_WO
+#define R_VECT_MASK_CLR__EQL REG_EQL_WO
+#define R_VECT_MASK_CLR__IEQL REG_IEQL_WO
+#define R_VECT_MASK_CLR__RD REG_RD_WO
+#define R_VECT_MASK_CLR__IRD REG_IRD_WO
+#define R_VECT_MASK_CLR__WR REG_WR_WO
+#define R_VECT_MASK_CLR__IWR REG_IWR_WO
+
+#define R_VECT_MASK_CLR__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_VECT_MASK_CLR__usb__usb__MASK 0x80000000U
+#define R_VECT_MASK_CLR__dma9__dma9__MASK 0x02000000U
+#define R_VECT_MASK_CLR__dma8__dma8__MASK 0x01000000U
+#define R_VECT_MASK_CLR__dma7__dma7__MASK 0x00800000U
+#define R_VECT_MASK_CLR__dma6__dma6__MASK 0x00400000U
+#define R_VECT_MASK_CLR__dma5__dma5__MASK 0x00200000U
+#define R_VECT_MASK_CLR__dma4__dma4__MASK 0x00100000U
+#define R_VECT_MASK_CLR__dma3__dma3__MASK 0x00080000U
+#define R_VECT_MASK_CLR__dma2__dma2__MASK 0x00040000U
+#define R_VECT_MASK_CLR__dma1__dma1__MASK 0x00020000U
+#define R_VECT_MASK_CLR__dma0__dma0__MASK 0x00010000U
+#define R_VECT_MASK_CLR__ext_dma1__ext_dma1__MASK 0x00002000U
+#define R_VECT_MASK_CLR__ext_dma0__ext_dma0__MASK 0x00001000U
+#define R_VECT_MASK_CLR__pa__pa__MASK 0x00000800U
+#define R_VECT_MASK_CLR__irq_intnr__irq_intnr__MASK 0x00000400U
+#define R_VECT_MASK_CLR__sw__sw__MASK 0x00000200U
+#define R_VECT_MASK_CLR__serial__serial__MASK 0x00000100U
+#define R_VECT_MASK_CLR__snmp__snmp__MASK 0x00000080U
+#define R_VECT_MASK_CLR__network__network__MASK 0x00000040U
+#define R_VECT_MASK_CLR__scsi1__scsi1__MASK 0x00000020U
+#define R_VECT_MASK_CLR__par1__par1__MASK 0x00000020U
+#define R_VECT_MASK_CLR__scsi1__par1__MASK 0x00000020U
+#define R_VECT_MASK_CLR__scsi0__scsi0__MASK 0x00000010U
+#define R_VECT_MASK_CLR__par0__par0__MASK 0x00000010U
+#define R_VECT_MASK_CLR__scsi0__par0__MASK 0x00000010U
+#define R_VECT_MASK_CLR__ata__ata__MASK 0x00000010U
+#define R_VECT_MASK_CLR__scsi0__ata__MASK 0x00000010U
+#define R_VECT_MASK_CLR__mio__mio__MASK 0x00000010U
+#define R_VECT_MASK_CLR__scsi0__mio__MASK 0x00000010U
+#define R_VECT_MASK_CLR__timer1__timer1__MASK 0x00000008U
+#define R_VECT_MASK_CLR__timer0__timer0__MASK 0x00000004U
+#define R_VECT_MASK_CLR__nmi__nmi__MASK 0x00000002U
+#define R_VECT_MASK_CLR__some__some__MASK 0x00000001U
+
+#define R_VECT_MASK_CLR__usb__MAX 0x1
+#define R_VECT_MASK_CLR__dma9__MAX 0x1
+#define R_VECT_MASK_CLR__dma8__MAX 0x1
+#define R_VECT_MASK_CLR__dma7__MAX 0x1
+#define R_VECT_MASK_CLR__dma6__MAX 0x1
+#define R_VECT_MASK_CLR__dma5__MAX 0x1
+#define R_VECT_MASK_CLR__dma4__MAX 0x1
+#define R_VECT_MASK_CLR__dma3__MAX 0x1
+#define R_VECT_MASK_CLR__dma2__MAX 0x1
+#define R_VECT_MASK_CLR__dma1__MAX 0x1
+#define R_VECT_MASK_CLR__dma0__MAX 0x1
+#define R_VECT_MASK_CLR__ext_dma1__MAX 0x1
+#define R_VECT_MASK_CLR__ext_dma0__MAX 0x1
+#define R_VECT_MASK_CLR__pa__MAX 0x1
+#define R_VECT_MASK_CLR__irq_intnr__MAX 0x1
+#define R_VECT_MASK_CLR__sw__MAX 0x1
+#define R_VECT_MASK_CLR__serial__MAX 0x1
+#define R_VECT_MASK_CLR__snmp__MAX 0x1
+#define R_VECT_MASK_CLR__network__MAX 0x1
+#define R_VECT_MASK_CLR__scsi1__MAX 0x1
+#define R_VECT_MASK_CLR__par1__MAX 0x1
+#define R_VECT_MASK_CLR__scsi0__MAX 0x1
+#define R_VECT_MASK_CLR__par0__MAX 0x1
+#define R_VECT_MASK_CLR__ata__MAX 0x1
+#define R_VECT_MASK_CLR__mio__MAX 0x1
+#define R_VECT_MASK_CLR__timer1__MAX 0x1
+#define R_VECT_MASK_CLR__timer0__MAX 0x1
+#define R_VECT_MASK_CLR__nmi__MAX 0x1
+#define R_VECT_MASK_CLR__some__MAX 0x1
+
+#define R_VECT_MASK_CLR__usb__MIN 0
+#define R_VECT_MASK_CLR__dma9__MIN 0
+#define R_VECT_MASK_CLR__dma8__MIN 0
+#define R_VECT_MASK_CLR__dma7__MIN 0
+#define R_VECT_MASK_CLR__dma6__MIN 0
+#define R_VECT_MASK_CLR__dma5__MIN 0
+#define R_VECT_MASK_CLR__dma4__MIN 0
+#define R_VECT_MASK_CLR__dma3__MIN 0
+#define R_VECT_MASK_CLR__dma2__MIN 0
+#define R_VECT_MASK_CLR__dma1__MIN 0
+#define R_VECT_MASK_CLR__dma0__MIN 0
+#define R_VECT_MASK_CLR__ext_dma1__MIN 0
+#define R_VECT_MASK_CLR__ext_dma0__MIN 0
+#define R_VECT_MASK_CLR__pa__MIN 0
+#define R_VECT_MASK_CLR__irq_intnr__MIN 0
+#define R_VECT_MASK_CLR__sw__MIN 0
+#define R_VECT_MASK_CLR__serial__MIN 0
+#define R_VECT_MASK_CLR__snmp__MIN 0
+#define R_VECT_MASK_CLR__network__MIN 0
+#define R_VECT_MASK_CLR__scsi1__MIN 0
+#define R_VECT_MASK_CLR__par1__MIN 0
+#define R_VECT_MASK_CLR__scsi0__MIN 0
+#define R_VECT_MASK_CLR__par0__MIN 0
+#define R_VECT_MASK_CLR__ata__MIN 0
+#define R_VECT_MASK_CLR__mio__MIN 0
+#define R_VECT_MASK_CLR__timer1__MIN 0
+#define R_VECT_MASK_CLR__timer0__MIN 0
+#define R_VECT_MASK_CLR__nmi__MIN 0
+#define R_VECT_MASK_CLR__some__MIN 0
+
+#define R_VECT_MASK_CLR__usb__BITNR 31
+#define R_VECT_MASK_CLR__dma9__BITNR 25
+#define R_VECT_MASK_CLR__dma8__BITNR 24
+#define R_VECT_MASK_CLR__dma7__BITNR 23
+#define R_VECT_MASK_CLR__dma6__BITNR 22
+#define R_VECT_MASK_CLR__dma5__BITNR 21
+#define R_VECT_MASK_CLR__dma4__BITNR 20
+#define R_VECT_MASK_CLR__dma3__BITNR 19
+#define R_VECT_MASK_CLR__dma2__BITNR 18
+#define R_VECT_MASK_CLR__dma1__BITNR 17
+#define R_VECT_MASK_CLR__dma0__BITNR 16
+#define R_VECT_MASK_CLR__ext_dma1__BITNR 13
+#define R_VECT_MASK_CLR__ext_dma0__BITNR 12
+#define R_VECT_MASK_CLR__pa__BITNR 11
+#define R_VECT_MASK_CLR__irq_intnr__BITNR 10
+#define R_VECT_MASK_CLR__sw__BITNR 9
+#define R_VECT_MASK_CLR__serial__BITNR 8
+#define R_VECT_MASK_CLR__snmp__BITNR 7
+#define R_VECT_MASK_CLR__network__BITNR 6
+#define R_VECT_MASK_CLR__scsi1__BITNR 5
+#define R_VECT_MASK_CLR__par1__BITNR 5
+#define R_VECT_MASK_CLR__scsi0__BITNR 4
+#define R_VECT_MASK_CLR__par0__BITNR 4
+#define R_VECT_MASK_CLR__ata__BITNR 4
+#define R_VECT_MASK_CLR__mio__BITNR 4
+#define R_VECT_MASK_CLR__timer1__BITNR 3
+#define R_VECT_MASK_CLR__timer0__BITNR 2
+#define R_VECT_MASK_CLR__nmi__BITNR 1
+#define R_VECT_MASK_CLR__some__BITNR 0
+
+#define R_VECT_MASK_CLR__usb__usb__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma9__dma9__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma8__dma8__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma7__dma7__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma6__dma6__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma5__dma5__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma4__dma4__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma3__dma3__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma2__dma2__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma1__dma1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__dma0__dma0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__pa__pa__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__irq_intnr__irq_intnr__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__sw__sw__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__serial__serial__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__snmp__snmp__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__network__network__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__par1__par1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__scsi1__par1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__par0__par0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__scsi0__par0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__ata__ata__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__scsi0__ata__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__mio__mio__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__scsi0__mio__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__timer1__timer1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__timer0__timer0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__nmi__nmi__VAL REG_VAL_ENUM
+#define R_VECT_MASK_CLR__some__some__VAL REG_VAL_ENUM
+
+#define R_VECT_MASK_CLR__usb__usb__clr 1
+#define R_VECT_MASK_CLR__usb__usb__nop 0
+#define R_VECT_MASK_CLR__dma9__dma9__clr 1
+#define R_VECT_MASK_CLR__dma9__dma9__nop 0
+#define R_VECT_MASK_CLR__dma8__dma8__clr 1
+#define R_VECT_MASK_CLR__dma8__dma8__nop 0
+#define R_VECT_MASK_CLR__dma7__dma7__clr 1
+#define R_VECT_MASK_CLR__dma7__dma7__nop 0
+#define R_VECT_MASK_CLR__dma6__dma6__clr 1
+#define R_VECT_MASK_CLR__dma6__dma6__nop 0
+#define R_VECT_MASK_CLR__dma5__dma5__clr 1
+#define R_VECT_MASK_CLR__dma5__dma5__nop 0
+#define R_VECT_MASK_CLR__dma4__dma4__clr 1
+#define R_VECT_MASK_CLR__dma4__dma4__nop 0
+#define R_VECT_MASK_CLR__dma3__dma3__clr 1
+#define R_VECT_MASK_CLR__dma3__dma3__nop 0
+#define R_VECT_MASK_CLR__dma2__dma2__clr 1
+#define R_VECT_MASK_CLR__dma2__dma2__nop 0
+#define R_VECT_MASK_CLR__dma1__dma1__clr 1
+#define R_VECT_MASK_CLR__dma1__dma1__nop 0
+#define R_VECT_MASK_CLR__dma0__dma0__clr 1
+#define R_VECT_MASK_CLR__dma0__dma0__nop 0
+#define R_VECT_MASK_CLR__ext_dma1__ext_dma1__clr 1
+#define R_VECT_MASK_CLR__ext_dma1__ext_dma1__nop 0
+#define R_VECT_MASK_CLR__ext_dma0__ext_dma0__clr 1
+#define R_VECT_MASK_CLR__ext_dma0__ext_dma0__nop 0
+#define R_VECT_MASK_CLR__pa__pa__clr 1
+#define R_VECT_MASK_CLR__pa__pa__nop 0
+#define R_VECT_MASK_CLR__irq_intnr__irq_intnr__clr 1
+#define R_VECT_MASK_CLR__irq_intnr__irq_intnr__nop 0
+#define R_VECT_MASK_CLR__sw__sw__clr 1
+#define R_VECT_MASK_CLR__sw__sw__nop 0
+#define R_VECT_MASK_CLR__serial__serial__clr 1
+#define R_VECT_MASK_CLR__serial__serial__nop 0
+#define R_VECT_MASK_CLR__snmp__snmp__clr 1
+#define R_VECT_MASK_CLR__snmp__snmp__nop 0
+#define R_VECT_MASK_CLR__network__network__clr 1
+#define R_VECT_MASK_CLR__network__network__nop 0
+#define R_VECT_MASK_CLR__scsi1__scsi1__clr 1
+#define R_VECT_MASK_CLR__scsi1__scsi1__nop 0
+#define R_VECT_MASK_CLR__par1__par1__clr 1
+#define R_VECT_MASK_CLR__par1__par1__nop 0
+#define R_VECT_MASK_CLR__scsi0__scsi0__clr 1
+#define R_VECT_MASK_CLR__scsi0__scsi0__nop 0
+#define R_VECT_MASK_CLR__par0__par0__clr 1
+#define R_VECT_MASK_CLR__par0__par0__nop 0
+#define R_VECT_MASK_CLR__ata__ata__clr 1
+#define R_VECT_MASK_CLR__ata__ata__nop 0
+#define R_VECT_MASK_CLR__mio__mio__clr 1
+#define R_VECT_MASK_CLR__mio__mio__nop 0
+#define R_VECT_MASK_CLR__timer1__timer1__clr 1
+#define R_VECT_MASK_CLR__timer1__timer1__nop 0
+#define R_VECT_MASK_CLR__timer0__timer0__clr 1
+#define R_VECT_MASK_CLR__timer0__timer0__nop 0
+#define R_VECT_MASK_CLR__nmi__nmi__clr 1
+#define R_VECT_MASK_CLR__nmi__nmi__nop 0
+#define R_VECT_MASK_CLR__some__some__clr 1
+#define R_VECT_MASK_CLR__some__some__nop 0
+
+#endif
+
+/*
+ * R_VECT_MASK_RD
+ * - type: RO
+ * - addr: 0xb00000d8
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_VECT_MASK_RD__ADDR (REG_TYPECAST_UDWORD 0xb00000d8)
+#define R_VECT_MASK_RD__SVAL REG_SVAL_SHADOW
+#define R_VECT_MASK_RD__SVAL_I REG_SVAL_I_SHADOW
+#define R_VECT_MASK_RD__TYPECAST REG_TYPECAST_UDWORD
+#define R_VECT_MASK_RD__TYPE (REG_UDWORD)
+#define R_VECT_MASK_RD__GET REG_GET_RO
+#define R_VECT_MASK_RD__IGET REG_IGET_RO
+#define R_VECT_MASK_RD__SET REG_SET_RO
+#define R_VECT_MASK_RD__ISET REG_ISET_RO
+#define R_VECT_MASK_RD__SET_VAL REG_SET_VAL_RO
+#define R_VECT_MASK_RD__EQL REG_EQL_RO
+#define R_VECT_MASK_RD__IEQL REG_IEQL_RO
+#define R_VECT_MASK_RD__RD REG_RD_RO
+#define R_VECT_MASK_RD__IRD REG_IRD_RO
+#define R_VECT_MASK_RD__WR REG_WR_RO
+#define R_VECT_MASK_RD__IWR REG_IWR_RO
+
+#define R_VECT_MASK_RD__READ(addr) \
+ (*(addr))
+
+#define R_VECT_MASK_RD__usb__usb__MASK 0x80000000U
+#define R_VECT_MASK_RD__dma9__dma9__MASK 0x02000000U
+#define R_VECT_MASK_RD__dma8__dma8__MASK 0x01000000U
+#define R_VECT_MASK_RD__dma7__dma7__MASK 0x00800000U
+#define R_VECT_MASK_RD__dma6__dma6__MASK 0x00400000U
+#define R_VECT_MASK_RD__dma5__dma5__MASK 0x00200000U
+#define R_VECT_MASK_RD__dma4__dma4__MASK 0x00100000U
+#define R_VECT_MASK_RD__dma3__dma3__MASK 0x00080000U
+#define R_VECT_MASK_RD__dma2__dma2__MASK 0x00040000U
+#define R_VECT_MASK_RD__dma1__dma1__MASK 0x00020000U
+#define R_VECT_MASK_RD__dma0__dma0__MASK 0x00010000U
+#define R_VECT_MASK_RD__ext_dma1__ext_dma1__MASK 0x00002000U
+#define R_VECT_MASK_RD__ext_dma0__ext_dma0__MASK 0x00001000U
+#define R_VECT_MASK_RD__pa__pa__MASK 0x00000800U
+#define R_VECT_MASK_RD__irq_intnr__irq_intnr__MASK 0x00000400U
+#define R_VECT_MASK_RD__sw__sw__MASK 0x00000200U
+#define R_VECT_MASK_RD__serial__serial__MASK 0x00000100U
+#define R_VECT_MASK_RD__snmp__snmp__MASK 0x00000080U
+#define R_VECT_MASK_RD__network__network__MASK 0x00000040U
+#define R_VECT_MASK_RD__scsi1__scsi1__MASK 0x00000020U
+#define R_VECT_MASK_RD__par1__par1__MASK 0x00000020U
+#define R_VECT_MASK_RD__scsi1__par1__MASK 0x00000020U
+#define R_VECT_MASK_RD__scsi0__scsi0__MASK 0x00000010U
+#define R_VECT_MASK_RD__par0__par0__MASK 0x00000010U
+#define R_VECT_MASK_RD__scsi0__par0__MASK 0x00000010U
+#define R_VECT_MASK_RD__ata__ata__MASK 0x00000010U
+#define R_VECT_MASK_RD__scsi0__ata__MASK 0x00000010U
+#define R_VECT_MASK_RD__mio__mio__MASK 0x00000010U
+#define R_VECT_MASK_RD__scsi0__mio__MASK 0x00000010U
+#define R_VECT_MASK_RD__timer1__timer1__MASK 0x00000008U
+#define R_VECT_MASK_RD__timer0__timer0__MASK 0x00000004U
+#define R_VECT_MASK_RD__nmi__nmi__MASK 0x00000002U
+#define R_VECT_MASK_RD__some__some__MASK 0x00000001U
+
+#define R_VECT_MASK_RD__usb__MAX 0x1
+#define R_VECT_MASK_RD__dma9__MAX 0x1
+#define R_VECT_MASK_RD__dma8__MAX 0x1
+#define R_VECT_MASK_RD__dma7__MAX 0x1
+#define R_VECT_MASK_RD__dma6__MAX 0x1
+#define R_VECT_MASK_RD__dma5__MAX 0x1
+#define R_VECT_MASK_RD__dma4__MAX 0x1
+#define R_VECT_MASK_RD__dma3__MAX 0x1
+#define R_VECT_MASK_RD__dma2__MAX 0x1
+#define R_VECT_MASK_RD__dma1__MAX 0x1
+#define R_VECT_MASK_RD__dma0__MAX 0x1
+#define R_VECT_MASK_RD__ext_dma1__MAX 0x1
+#define R_VECT_MASK_RD__ext_dma0__MAX 0x1
+#define R_VECT_MASK_RD__pa__MAX 0x1
+#define R_VECT_MASK_RD__irq_intnr__MAX 0x1
+#define R_VECT_MASK_RD__sw__MAX 0x1
+#define R_VECT_MASK_RD__serial__MAX 0x1
+#define R_VECT_MASK_RD__snmp__MAX 0x1
+#define R_VECT_MASK_RD__network__MAX 0x1
+#define R_VECT_MASK_RD__scsi1__MAX 0x1
+#define R_VECT_MASK_RD__par1__MAX 0x1
+#define R_VECT_MASK_RD__scsi0__MAX 0x1
+#define R_VECT_MASK_RD__par0__MAX 0x1
+#define R_VECT_MASK_RD__ata__MAX 0x1
+#define R_VECT_MASK_RD__mio__MAX 0x1
+#define R_VECT_MASK_RD__timer1__MAX 0x1
+#define R_VECT_MASK_RD__timer0__MAX 0x1
+#define R_VECT_MASK_RD__nmi__MAX 0x1
+#define R_VECT_MASK_RD__some__MAX 0x1
+
+#define R_VECT_MASK_RD__usb__MIN 0
+#define R_VECT_MASK_RD__dma9__MIN 0
+#define R_VECT_MASK_RD__dma8__MIN 0
+#define R_VECT_MASK_RD__dma7__MIN 0
+#define R_VECT_MASK_RD__dma6__MIN 0
+#define R_VECT_MASK_RD__dma5__MIN 0
+#define R_VECT_MASK_RD__dma4__MIN 0
+#define R_VECT_MASK_RD__dma3__MIN 0
+#define R_VECT_MASK_RD__dma2__MIN 0
+#define R_VECT_MASK_RD__dma1__MIN 0
+#define R_VECT_MASK_RD__dma0__MIN 0
+#define R_VECT_MASK_RD__ext_dma1__MIN 0
+#define R_VECT_MASK_RD__ext_dma0__MIN 0
+#define R_VECT_MASK_RD__pa__MIN 0
+#define R_VECT_MASK_RD__irq_intnr__MIN 0
+#define R_VECT_MASK_RD__sw__MIN 0
+#define R_VECT_MASK_RD__serial__MIN 0
+#define R_VECT_MASK_RD__snmp__MIN 0
+#define R_VECT_MASK_RD__network__MIN 0
+#define R_VECT_MASK_RD__scsi1__MIN 0
+#define R_VECT_MASK_RD__par1__MIN 0
+#define R_VECT_MASK_RD__scsi0__MIN 0
+#define R_VECT_MASK_RD__par0__MIN 0
+#define R_VECT_MASK_RD__ata__MIN 0
+#define R_VECT_MASK_RD__mio__MIN 0
+#define R_VECT_MASK_RD__timer1__MIN 0
+#define R_VECT_MASK_RD__timer0__MIN 0
+#define R_VECT_MASK_RD__nmi__MIN 0
+#define R_VECT_MASK_RD__some__MIN 0
+
+#define R_VECT_MASK_RD__usb__BITNR 31
+#define R_VECT_MASK_RD__dma9__BITNR 25
+#define R_VECT_MASK_RD__dma8__BITNR 24
+#define R_VECT_MASK_RD__dma7__BITNR 23
+#define R_VECT_MASK_RD__dma6__BITNR 22
+#define R_VECT_MASK_RD__dma5__BITNR 21
+#define R_VECT_MASK_RD__dma4__BITNR 20
+#define R_VECT_MASK_RD__dma3__BITNR 19
+#define R_VECT_MASK_RD__dma2__BITNR 18
+#define R_VECT_MASK_RD__dma1__BITNR 17
+#define R_VECT_MASK_RD__dma0__BITNR 16
+#define R_VECT_MASK_RD__ext_dma1__BITNR 13
+#define R_VECT_MASK_RD__ext_dma0__BITNR 12
+#define R_VECT_MASK_RD__pa__BITNR 11
+#define R_VECT_MASK_RD__irq_intnr__BITNR 10
+#define R_VECT_MASK_RD__sw__BITNR 9
+#define R_VECT_MASK_RD__serial__BITNR 8
+#define R_VECT_MASK_RD__snmp__BITNR 7
+#define R_VECT_MASK_RD__network__BITNR 6
+#define R_VECT_MASK_RD__scsi1__BITNR 5
+#define R_VECT_MASK_RD__par1__BITNR 5
+#define R_VECT_MASK_RD__scsi0__BITNR 4
+#define R_VECT_MASK_RD__par0__BITNR 4
+#define R_VECT_MASK_RD__ata__BITNR 4
+#define R_VECT_MASK_RD__mio__BITNR 4
+#define R_VECT_MASK_RD__timer1__BITNR 3
+#define R_VECT_MASK_RD__timer0__BITNR 2
+#define R_VECT_MASK_RD__nmi__BITNR 1
+#define R_VECT_MASK_RD__some__BITNR 0
+
+#define R_VECT_MASK_RD__usb__usb__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma9__dma9__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma8__dma8__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma7__dma7__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma6__dma6__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma5__dma5__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma4__dma4__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma3__dma3__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma2__dma2__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma1__dma1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__dma0__dma0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__pa__pa__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__irq_intnr__irq_intnr__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__sw__sw__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__serial__serial__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__snmp__snmp__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__network__network__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__par1__par1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__scsi1__par1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__par0__par0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__scsi0__par0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__ata__ata__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__scsi0__ata__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__mio__mio__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__scsi0__mio__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__timer1__timer1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__timer0__timer0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__nmi__nmi__VAL REG_VAL_ENUM
+#define R_VECT_MASK_RD__some__some__VAL REG_VAL_ENUM
+
+#define R_VECT_MASK_RD__usb__usb__active 1
+#define R_VECT_MASK_RD__usb__usb__inactive 0
+#define R_VECT_MASK_RD__dma9__dma9__active 1
+#define R_VECT_MASK_RD__dma9__dma9__inactive 0
+#define R_VECT_MASK_RD__dma8__dma8__active 1
+#define R_VECT_MASK_RD__dma8__dma8__inactive 0
+#define R_VECT_MASK_RD__dma7__dma7__active 1
+#define R_VECT_MASK_RD__dma7__dma7__inactive 0
+#define R_VECT_MASK_RD__dma6__dma6__active 1
+#define R_VECT_MASK_RD__dma6__dma6__inactive 0
+#define R_VECT_MASK_RD__dma5__dma5__active 1
+#define R_VECT_MASK_RD__dma5__dma5__inactive 0
+#define R_VECT_MASK_RD__dma4__dma4__active 1
+#define R_VECT_MASK_RD__dma4__dma4__inactive 0
+#define R_VECT_MASK_RD__dma3__dma3__active 1
+#define R_VECT_MASK_RD__dma3__dma3__inactive 0
+#define R_VECT_MASK_RD__dma2__dma2__active 1
+#define R_VECT_MASK_RD__dma2__dma2__inactive 0
+#define R_VECT_MASK_RD__dma1__dma1__active 1
+#define R_VECT_MASK_RD__dma1__dma1__inactive 0
+#define R_VECT_MASK_RD__dma0__dma0__active 1
+#define R_VECT_MASK_RD__dma0__dma0__inactive 0
+#define R_VECT_MASK_RD__ext_dma1__ext_dma1__active 1
+#define R_VECT_MASK_RD__ext_dma1__ext_dma1__inactive 0
+#define R_VECT_MASK_RD__ext_dma0__ext_dma0__active 1
+#define R_VECT_MASK_RD__ext_dma0__ext_dma0__inactive 0
+#define R_VECT_MASK_RD__pa__pa__active 1
+#define R_VECT_MASK_RD__pa__pa__inactive 0
+#define R_VECT_MASK_RD__irq_intnr__irq_intnr__active 1
+#define R_VECT_MASK_RD__irq_intnr__irq_intnr__inactive 0
+#define R_VECT_MASK_RD__sw__sw__active 1
+#define R_VECT_MASK_RD__sw__sw__inactive 0
+#define R_VECT_MASK_RD__serial__serial__active 1
+#define R_VECT_MASK_RD__serial__serial__inactive 0
+#define R_VECT_MASK_RD__snmp__snmp__active 1
+#define R_VECT_MASK_RD__snmp__snmp__inactive 0
+#define R_VECT_MASK_RD__network__network__active 1
+#define R_VECT_MASK_RD__network__network__inactive 0
+#define R_VECT_MASK_RD__scsi1__scsi1__active 1
+#define R_VECT_MASK_RD__scsi1__scsi1__inactive 0
+#define R_VECT_MASK_RD__par1__par1__active 1
+#define R_VECT_MASK_RD__par1__par1__inactive 0
+#define R_VECT_MASK_RD__scsi0__scsi0__active 1
+#define R_VECT_MASK_RD__scsi0__scsi0__inactive 0
+#define R_VECT_MASK_RD__par0__par0__active 1
+#define R_VECT_MASK_RD__par0__par0__inactive 0
+#define R_VECT_MASK_RD__ata__ata__active 1
+#define R_VECT_MASK_RD__ata__ata__inactive 0
+#define R_VECT_MASK_RD__mio__mio__active 1
+#define R_VECT_MASK_RD__mio__mio__inactive 0
+#define R_VECT_MASK_RD__timer1__timer1__active 1
+#define R_VECT_MASK_RD__timer1__timer1__inactive 0
+#define R_VECT_MASK_RD__timer0__timer0__active 1
+#define R_VECT_MASK_RD__timer0__timer0__inactive 0
+#define R_VECT_MASK_RD__nmi__nmi__active 1
+#define R_VECT_MASK_RD__nmi__nmi__inactive 0
+#define R_VECT_MASK_RD__some__some__active 1
+#define R_VECT_MASK_RD__some__some__inactive 0
+
+#endif
+
+/*
+ * R_VECT_MASK_SET
+ * - type: WO
+ * - addr: 0xb00000dc
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_VECT_MASK_SET__ADDR (REG_TYPECAST_UDWORD 0xb00000dc)
+
+#ifndef REG_NO_SHADOW
+#define R_VECT_MASK_SET__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_VECT_MASK_SET + 0))
+#define R_VECT_MASK_SET__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_VECT_MASK_SET + 0))
+#else /* REG_NO_SHADOW */
+#define R_VECT_MASK_SET__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_VECT_MASK_SET__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_VECT_MASK_SET__STYPECAST REG_STYPECAST_UDWORD
+#define R_VECT_MASK_SET__SVAL REG_SVAL_ZERO
+#define R_VECT_MASK_SET__SVAL_I REG_SVAL_I_ZERO
+#define R_VECT_MASK_SET__TYPECAST REG_TYPECAST_UDWORD
+#define R_VECT_MASK_SET__TYPE (REG_UDWORD)
+#define R_VECT_MASK_SET__GET REG_GET_WO
+#define R_VECT_MASK_SET__IGET REG_IGET_WO
+#define R_VECT_MASK_SET__SET REG_SET_WO
+#define R_VECT_MASK_SET__ISET REG_ISET_WO
+#define R_VECT_MASK_SET__SET_VAL REG_SET_VAL_WO
+#define R_VECT_MASK_SET__EQL REG_EQL_WO
+#define R_VECT_MASK_SET__IEQL REG_IEQL_WO
+#define R_VECT_MASK_SET__RD REG_RD_WO
+#define R_VECT_MASK_SET__IRD REG_IRD_WO
+#define R_VECT_MASK_SET__WR REG_WR_WO
+#define R_VECT_MASK_SET__IWR REG_IWR_WO
+
+#define R_VECT_MASK_SET__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_VECT_MASK_SET__usb__usb__MASK 0x80000000U
+#define R_VECT_MASK_SET__dma9__dma9__MASK 0x02000000U
+#define R_VECT_MASK_SET__dma8__dma8__MASK 0x01000000U
+#define R_VECT_MASK_SET__dma7__dma7__MASK 0x00800000U
+#define R_VECT_MASK_SET__dma6__dma6__MASK 0x00400000U
+#define R_VECT_MASK_SET__dma5__dma5__MASK 0x00200000U
+#define R_VECT_MASK_SET__dma4__dma4__MASK 0x00100000U
+#define R_VECT_MASK_SET__dma3__dma3__MASK 0x00080000U
+#define R_VECT_MASK_SET__dma2__dma2__MASK 0x00040000U
+#define R_VECT_MASK_SET__dma1__dma1__MASK 0x00020000U
+#define R_VECT_MASK_SET__dma0__dma0__MASK 0x00010000U
+#define R_VECT_MASK_SET__ext_dma1__ext_dma1__MASK 0x00002000U
+#define R_VECT_MASK_SET__ext_dma0__ext_dma0__MASK 0x00001000U
+#define R_VECT_MASK_SET__pa__pa__MASK 0x00000800U
+#define R_VECT_MASK_SET__irq_intnr__irq_intnr__MASK 0x00000400U
+#define R_VECT_MASK_SET__sw__sw__MASK 0x00000200U
+#define R_VECT_MASK_SET__serial__serial__MASK 0x00000100U
+#define R_VECT_MASK_SET__snmp__snmp__MASK 0x00000080U
+#define R_VECT_MASK_SET__network__network__MASK 0x00000040U
+#define R_VECT_MASK_SET__scsi1__scsi1__MASK 0x00000020U
+#define R_VECT_MASK_SET__par1__par1__MASK 0x00000020U
+#define R_VECT_MASK_SET__scsi1__par1__MASK 0x00000020U
+#define R_VECT_MASK_SET__scsi0__scsi0__MASK 0x00000010U
+#define R_VECT_MASK_SET__par0__par0__MASK 0x00000010U
+#define R_VECT_MASK_SET__scsi0__par0__MASK 0x00000010U
+#define R_VECT_MASK_SET__ata__ata__MASK 0x00000010U
+#define R_VECT_MASK_SET__scsi0__ata__MASK 0x00000010U
+#define R_VECT_MASK_SET__mio__mio__MASK 0x00000010U
+#define R_VECT_MASK_SET__scsi0__mio__MASK 0x00000010U
+#define R_VECT_MASK_SET__timer1__timer1__MASK 0x00000008U
+#define R_VECT_MASK_SET__timer0__timer0__MASK 0x00000004U
+#define R_VECT_MASK_SET__nmi__nmi__MASK 0x00000002U
+#define R_VECT_MASK_SET__some__some__MASK 0x00000001U
+
+#define R_VECT_MASK_SET__usb__MAX 0x1
+#define R_VECT_MASK_SET__dma9__MAX 0x1
+#define R_VECT_MASK_SET__dma8__MAX 0x1
+#define R_VECT_MASK_SET__dma7__MAX 0x1
+#define R_VECT_MASK_SET__dma6__MAX 0x1
+#define R_VECT_MASK_SET__dma5__MAX 0x1
+#define R_VECT_MASK_SET__dma4__MAX 0x1
+#define R_VECT_MASK_SET__dma3__MAX 0x1
+#define R_VECT_MASK_SET__dma2__MAX 0x1
+#define R_VECT_MASK_SET__dma1__MAX 0x1
+#define R_VECT_MASK_SET__dma0__MAX 0x1
+#define R_VECT_MASK_SET__ext_dma1__MAX 0x1
+#define R_VECT_MASK_SET__ext_dma0__MAX 0x1
+#define R_VECT_MASK_SET__pa__MAX 0x1
+#define R_VECT_MASK_SET__irq_intnr__MAX 0x1
+#define R_VECT_MASK_SET__sw__MAX 0x1
+#define R_VECT_MASK_SET__serial__MAX 0x1
+#define R_VECT_MASK_SET__snmp__MAX 0x1
+#define R_VECT_MASK_SET__network__MAX 0x1
+#define R_VECT_MASK_SET__scsi1__MAX 0x1
+#define R_VECT_MASK_SET__par1__MAX 0x1
+#define R_VECT_MASK_SET__scsi0__MAX 0x1
+#define R_VECT_MASK_SET__par0__MAX 0x1
+#define R_VECT_MASK_SET__ata__MAX 0x1
+#define R_VECT_MASK_SET__mio__MAX 0x1
+#define R_VECT_MASK_SET__timer1__MAX 0x1
+#define R_VECT_MASK_SET__timer0__MAX 0x1
+#define R_VECT_MASK_SET__nmi__MAX 0x1
+#define R_VECT_MASK_SET__some__MAX 0x1
+
+#define R_VECT_MASK_SET__usb__MIN 0
+#define R_VECT_MASK_SET__dma9__MIN 0
+#define R_VECT_MASK_SET__dma8__MIN 0
+#define R_VECT_MASK_SET__dma7__MIN 0
+#define R_VECT_MASK_SET__dma6__MIN 0
+#define R_VECT_MASK_SET__dma5__MIN 0
+#define R_VECT_MASK_SET__dma4__MIN 0
+#define R_VECT_MASK_SET__dma3__MIN 0
+#define R_VECT_MASK_SET__dma2__MIN 0
+#define R_VECT_MASK_SET__dma1__MIN 0
+#define R_VECT_MASK_SET__dma0__MIN 0
+#define R_VECT_MASK_SET__ext_dma1__MIN 0
+#define R_VECT_MASK_SET__ext_dma0__MIN 0
+#define R_VECT_MASK_SET__pa__MIN 0
+#define R_VECT_MASK_SET__irq_intnr__MIN 0
+#define R_VECT_MASK_SET__sw__MIN 0
+#define R_VECT_MASK_SET__serial__MIN 0
+#define R_VECT_MASK_SET__snmp__MIN 0
+#define R_VECT_MASK_SET__network__MIN 0
+#define R_VECT_MASK_SET__scsi1__MIN 0
+#define R_VECT_MASK_SET__par1__MIN 0
+#define R_VECT_MASK_SET__scsi0__MIN 0
+#define R_VECT_MASK_SET__par0__MIN 0
+#define R_VECT_MASK_SET__ata__MIN 0
+#define R_VECT_MASK_SET__mio__MIN 0
+#define R_VECT_MASK_SET__timer1__MIN 0
+#define R_VECT_MASK_SET__timer0__MIN 0
+#define R_VECT_MASK_SET__nmi__MIN 0
+#define R_VECT_MASK_SET__some__MIN 0
+
+#define R_VECT_MASK_SET__usb__BITNR 31
+#define R_VECT_MASK_SET__dma9__BITNR 25
+#define R_VECT_MASK_SET__dma8__BITNR 24
+#define R_VECT_MASK_SET__dma7__BITNR 23
+#define R_VECT_MASK_SET__dma6__BITNR 22
+#define R_VECT_MASK_SET__dma5__BITNR 21
+#define R_VECT_MASK_SET__dma4__BITNR 20
+#define R_VECT_MASK_SET__dma3__BITNR 19
+#define R_VECT_MASK_SET__dma2__BITNR 18
+#define R_VECT_MASK_SET__dma1__BITNR 17
+#define R_VECT_MASK_SET__dma0__BITNR 16
+#define R_VECT_MASK_SET__ext_dma1__BITNR 13
+#define R_VECT_MASK_SET__ext_dma0__BITNR 12
+#define R_VECT_MASK_SET__pa__BITNR 11
+#define R_VECT_MASK_SET__irq_intnr__BITNR 10
+#define R_VECT_MASK_SET__sw__BITNR 9
+#define R_VECT_MASK_SET__serial__BITNR 8
+#define R_VECT_MASK_SET__snmp__BITNR 7
+#define R_VECT_MASK_SET__network__BITNR 6
+#define R_VECT_MASK_SET__scsi1__BITNR 5
+#define R_VECT_MASK_SET__par1__BITNR 5
+#define R_VECT_MASK_SET__scsi0__BITNR 4
+#define R_VECT_MASK_SET__par0__BITNR 4
+#define R_VECT_MASK_SET__ata__BITNR 4
+#define R_VECT_MASK_SET__mio__BITNR 4
+#define R_VECT_MASK_SET__timer1__BITNR 3
+#define R_VECT_MASK_SET__timer0__BITNR 2
+#define R_VECT_MASK_SET__nmi__BITNR 1
+#define R_VECT_MASK_SET__some__BITNR 0
+
+#define R_VECT_MASK_SET__usb__usb__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma9__dma9__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma8__dma8__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma7__dma7__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma6__dma6__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma5__dma5__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma4__dma4__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma3__dma3__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma2__dma2__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma1__dma1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__dma0__dma0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__pa__pa__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__irq_intnr__irq_intnr__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__sw__sw__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__serial__serial__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__snmp__snmp__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__network__network__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__par1__par1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__scsi1__par1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__par0__par0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__scsi0__par0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__ata__ata__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__scsi0__ata__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__mio__mio__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__scsi0__mio__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__timer1__timer1__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__timer0__timer0__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__nmi__nmi__VAL REG_VAL_ENUM
+#define R_VECT_MASK_SET__some__some__VAL REG_VAL_ENUM
+
+#define R_VECT_MASK_SET__usb__usb__nop 0
+#define R_VECT_MASK_SET__usb__usb__set 1
+#define R_VECT_MASK_SET__dma9__dma9__nop 0
+#define R_VECT_MASK_SET__dma9__dma9__set 1
+#define R_VECT_MASK_SET__dma8__dma8__nop 0
+#define R_VECT_MASK_SET__dma8__dma8__set 1
+#define R_VECT_MASK_SET__dma7__dma7__nop 0
+#define R_VECT_MASK_SET__dma7__dma7__set 1
+#define R_VECT_MASK_SET__dma6__dma6__nop 0
+#define R_VECT_MASK_SET__dma6__dma6__set 1
+#define R_VECT_MASK_SET__dma5__dma5__nop 0
+#define R_VECT_MASK_SET__dma5__dma5__set 1
+#define R_VECT_MASK_SET__dma4__dma4__nop 0
+#define R_VECT_MASK_SET__dma4__dma4__set 1
+#define R_VECT_MASK_SET__dma3__dma3__nop 0
+#define R_VECT_MASK_SET__dma3__dma3__set 1
+#define R_VECT_MASK_SET__dma2__dma2__nop 0
+#define R_VECT_MASK_SET__dma2__dma2__set 1
+#define R_VECT_MASK_SET__dma1__dma1__nop 0
+#define R_VECT_MASK_SET__dma1__dma1__set 1
+#define R_VECT_MASK_SET__dma0__dma0__nop 0
+#define R_VECT_MASK_SET__dma0__dma0__set 1
+#define R_VECT_MASK_SET__ext_dma1__ext_dma1__nop 0
+#define R_VECT_MASK_SET__ext_dma1__ext_dma1__set 1
+#define R_VECT_MASK_SET__ext_dma0__ext_dma0__nop 0
+#define R_VECT_MASK_SET__ext_dma0__ext_dma0__set 1
+#define R_VECT_MASK_SET__pa__pa__nop 0
+#define R_VECT_MASK_SET__pa__pa__set 1
+#define R_VECT_MASK_SET__irq_intnr__irq_intnr__nop 0
+#define R_VECT_MASK_SET__irq_intnr__irq_intnr__set 1
+#define R_VECT_MASK_SET__sw__sw__nop 0
+#define R_VECT_MASK_SET__sw__sw__set 1
+#define R_VECT_MASK_SET__serial__serial__nop 0
+#define R_VECT_MASK_SET__serial__serial__set 1
+#define R_VECT_MASK_SET__snmp__snmp__nop 0
+#define R_VECT_MASK_SET__snmp__snmp__set 1
+#define R_VECT_MASK_SET__network__network__nop 0
+#define R_VECT_MASK_SET__network__network__set 1
+#define R_VECT_MASK_SET__scsi1__scsi1__nop 0
+#define R_VECT_MASK_SET__scsi1__scsi1__set 1
+#define R_VECT_MASK_SET__par1__par1__nop 0
+#define R_VECT_MASK_SET__par1__par1__set 1
+#define R_VECT_MASK_SET__scsi0__scsi0__nop 0
+#define R_VECT_MASK_SET__scsi0__scsi0__set 1
+#define R_VECT_MASK_SET__par0__par0__nop 0
+#define R_VECT_MASK_SET__par0__par0__set 1
+#define R_VECT_MASK_SET__ata__ata__nop 0
+#define R_VECT_MASK_SET__ata__ata__set 1
+#define R_VECT_MASK_SET__mio__mio__nop 0
+#define R_VECT_MASK_SET__mio__mio__set 1
+#define R_VECT_MASK_SET__timer1__timer1__nop 0
+#define R_VECT_MASK_SET__timer1__timer1__set 1
+#define R_VECT_MASK_SET__timer0__timer0__nop 0
+#define R_VECT_MASK_SET__timer0__timer0__set 1
+#define R_VECT_MASK_SET__nmi__nmi__nop 0
+#define R_VECT_MASK_SET__nmi__nmi__set 1
+#define R_VECT_MASK_SET__some__some__nop 0
+#define R_VECT_MASK_SET__some__some__set 1
+
+#endif
+
+/*
+ * R_VECT_READ
+ * - type: RO
+ * - addr: 0xb00000dc
+ * - group: Interrupt mask and status registers
+ */
+
+#if USE_GROUP__Interrupt_mask_and_status_registers
+
+#define R_VECT_READ__ADDR (REG_TYPECAST_UDWORD 0xb00000dc)
+#define R_VECT_READ__SVAL REG_SVAL_SHADOW
+#define R_VECT_READ__SVAL_I REG_SVAL_I_SHADOW
+#define R_VECT_READ__TYPECAST REG_TYPECAST_UDWORD
+#define R_VECT_READ__TYPE (REG_UDWORD)
+#define R_VECT_READ__GET REG_GET_RO
+#define R_VECT_READ__IGET REG_IGET_RO
+#define R_VECT_READ__SET REG_SET_RO
+#define R_VECT_READ__ISET REG_ISET_RO
+#define R_VECT_READ__SET_VAL REG_SET_VAL_RO
+#define R_VECT_READ__EQL REG_EQL_RO
+#define R_VECT_READ__IEQL REG_IEQL_RO
+#define R_VECT_READ__RD REG_RD_RO
+#define R_VECT_READ__IRD REG_IRD_RO
+#define R_VECT_READ__WR REG_WR_RO
+#define R_VECT_READ__IWR REG_IWR_RO
+
+#define R_VECT_READ__READ(addr) \
+ (*(addr))
+
+#define R_VECT_READ__usb__usb__MASK 0x80000000U
+#define R_VECT_READ__dma9__dma9__MASK 0x02000000U
+#define R_VECT_READ__dma8__dma8__MASK 0x01000000U
+#define R_VECT_READ__dma7__dma7__MASK 0x00800000U
+#define R_VECT_READ__dma6__dma6__MASK 0x00400000U
+#define R_VECT_READ__dma5__dma5__MASK 0x00200000U
+#define R_VECT_READ__dma4__dma4__MASK 0x00100000U
+#define R_VECT_READ__dma3__dma3__MASK 0x00080000U
+#define R_VECT_READ__dma2__dma2__MASK 0x00040000U
+#define R_VECT_READ__dma1__dma1__MASK 0x00020000U
+#define R_VECT_READ__dma0__dma0__MASK 0x00010000U
+#define R_VECT_READ__ext_dma1__ext_dma1__MASK 0x00002000U
+#define R_VECT_READ__ext_dma0__ext_dma0__MASK 0x00001000U
+#define R_VECT_READ__pa__pa__MASK 0x00000800U
+#define R_VECT_READ__irq_intnr__irq_intnr__MASK 0x00000400U
+#define R_VECT_READ__sw__sw__MASK 0x00000200U
+#define R_VECT_READ__serial__serial__MASK 0x00000100U
+#define R_VECT_READ__snmp__snmp__MASK 0x00000080U
+#define R_VECT_READ__network__network__MASK 0x00000040U
+#define R_VECT_READ__scsi1__scsi1__MASK 0x00000020U
+#define R_VECT_READ__par1__par1__MASK 0x00000020U
+#define R_VECT_READ__scsi1__par1__MASK 0x00000020U
+#define R_VECT_READ__scsi0__scsi0__MASK 0x00000010U
+#define R_VECT_READ__par0__par0__MASK 0x00000010U
+#define R_VECT_READ__scsi0__par0__MASK 0x00000010U
+#define R_VECT_READ__ata__ata__MASK 0x00000010U
+#define R_VECT_READ__scsi0__ata__MASK 0x00000010U
+#define R_VECT_READ__mio__mio__MASK 0x00000010U
+#define R_VECT_READ__scsi0__mio__MASK 0x00000010U
+#define R_VECT_READ__timer1__timer1__MASK 0x00000008U
+#define R_VECT_READ__timer0__timer0__MASK 0x00000004U
+#define R_VECT_READ__nmi__nmi__MASK 0x00000002U
+#define R_VECT_READ__some__some__MASK 0x00000001U
+
+#define R_VECT_READ__usb__MAX 0x1
+#define R_VECT_READ__dma9__MAX 0x1
+#define R_VECT_READ__dma8__MAX 0x1
+#define R_VECT_READ__dma7__MAX 0x1
+#define R_VECT_READ__dma6__MAX 0x1
+#define R_VECT_READ__dma5__MAX 0x1
+#define R_VECT_READ__dma4__MAX 0x1
+#define R_VECT_READ__dma3__MAX 0x1
+#define R_VECT_READ__dma2__MAX 0x1
+#define R_VECT_READ__dma1__MAX 0x1
+#define R_VECT_READ__dma0__MAX 0x1
+#define R_VECT_READ__ext_dma1__MAX 0x1
+#define R_VECT_READ__ext_dma0__MAX 0x1
+#define R_VECT_READ__pa__MAX 0x1
+#define R_VECT_READ__irq_intnr__MAX 0x1
+#define R_VECT_READ__sw__MAX 0x1
+#define R_VECT_READ__serial__MAX 0x1
+#define R_VECT_READ__snmp__MAX 0x1
+#define R_VECT_READ__network__MAX 0x1
+#define R_VECT_READ__scsi1__MAX 0x1
+#define R_VECT_READ__par1__MAX 0x1
+#define R_VECT_READ__scsi0__MAX 0x1
+#define R_VECT_READ__par0__MAX 0x1
+#define R_VECT_READ__ata__MAX 0x1
+#define R_VECT_READ__mio__MAX 0x1
+#define R_VECT_READ__timer1__MAX 0x1
+#define R_VECT_READ__timer0__MAX 0x1
+#define R_VECT_READ__nmi__MAX 0x1
+#define R_VECT_READ__some__MAX 0x1
+
+#define R_VECT_READ__usb__MIN 0
+#define R_VECT_READ__dma9__MIN 0
+#define R_VECT_READ__dma8__MIN 0
+#define R_VECT_READ__dma7__MIN 0
+#define R_VECT_READ__dma6__MIN 0
+#define R_VECT_READ__dma5__MIN 0
+#define R_VECT_READ__dma4__MIN 0
+#define R_VECT_READ__dma3__MIN 0
+#define R_VECT_READ__dma2__MIN 0
+#define R_VECT_READ__dma1__MIN 0
+#define R_VECT_READ__dma0__MIN 0
+#define R_VECT_READ__ext_dma1__MIN 0
+#define R_VECT_READ__ext_dma0__MIN 0
+#define R_VECT_READ__pa__MIN 0
+#define R_VECT_READ__irq_intnr__MIN 0
+#define R_VECT_READ__sw__MIN 0
+#define R_VECT_READ__serial__MIN 0
+#define R_VECT_READ__snmp__MIN 0
+#define R_VECT_READ__network__MIN 0
+#define R_VECT_READ__scsi1__MIN 0
+#define R_VECT_READ__par1__MIN 0
+#define R_VECT_READ__scsi0__MIN 0
+#define R_VECT_READ__par0__MIN 0
+#define R_VECT_READ__ata__MIN 0
+#define R_VECT_READ__mio__MIN 0
+#define R_VECT_READ__timer1__MIN 0
+#define R_VECT_READ__timer0__MIN 0
+#define R_VECT_READ__nmi__MIN 0
+#define R_VECT_READ__some__MIN 0
+
+#define R_VECT_READ__usb__BITNR 31
+#define R_VECT_READ__dma9__BITNR 25
+#define R_VECT_READ__dma8__BITNR 24
+#define R_VECT_READ__dma7__BITNR 23
+#define R_VECT_READ__dma6__BITNR 22
+#define R_VECT_READ__dma5__BITNR 21
+#define R_VECT_READ__dma4__BITNR 20
+#define R_VECT_READ__dma3__BITNR 19
+#define R_VECT_READ__dma2__BITNR 18
+#define R_VECT_READ__dma1__BITNR 17
+#define R_VECT_READ__dma0__BITNR 16
+#define R_VECT_READ__ext_dma1__BITNR 13
+#define R_VECT_READ__ext_dma0__BITNR 12
+#define R_VECT_READ__pa__BITNR 11
+#define R_VECT_READ__irq_intnr__BITNR 10
+#define R_VECT_READ__sw__BITNR 9
+#define R_VECT_READ__serial__BITNR 8
+#define R_VECT_READ__snmp__BITNR 7
+#define R_VECT_READ__network__BITNR 6
+#define R_VECT_READ__scsi1__BITNR 5
+#define R_VECT_READ__par1__BITNR 5
+#define R_VECT_READ__scsi0__BITNR 4
+#define R_VECT_READ__par0__BITNR 4
+#define R_VECT_READ__ata__BITNR 4
+#define R_VECT_READ__mio__BITNR 4
+#define R_VECT_READ__timer1__BITNR 3
+#define R_VECT_READ__timer0__BITNR 2
+#define R_VECT_READ__nmi__BITNR 1
+#define R_VECT_READ__some__BITNR 0
+
+#define R_VECT_READ__usb__usb__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma9__dma9__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma8__dma8__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma7__dma7__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma6__dma6__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma5__dma5__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma4__dma4__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma3__dma3__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma2__dma2__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma1__dma1__VAL REG_VAL_ENUM
+#define R_VECT_READ__dma0__dma0__VAL REG_VAL_ENUM
+#define R_VECT_READ__ext_dma1__ext_dma1__VAL REG_VAL_ENUM
+#define R_VECT_READ__ext_dma0__ext_dma0__VAL REG_VAL_ENUM
+#define R_VECT_READ__pa__pa__VAL REG_VAL_ENUM
+#define R_VECT_READ__irq_intnr__irq_intnr__VAL REG_VAL_ENUM
+#define R_VECT_READ__sw__sw__VAL REG_VAL_ENUM
+#define R_VECT_READ__serial__serial__VAL REG_VAL_ENUM
+#define R_VECT_READ__snmp__snmp__VAL REG_VAL_ENUM
+#define R_VECT_READ__network__network__VAL REG_VAL_ENUM
+#define R_VECT_READ__scsi1__scsi1__VAL REG_VAL_ENUM
+#define R_VECT_READ__par1__par1__VAL REG_VAL_ENUM
+#define R_VECT_READ__scsi1__par1__VAL REG_VAL_ENUM
+#define R_VECT_READ__scsi0__scsi0__VAL REG_VAL_ENUM
+#define R_VECT_READ__par0__par0__VAL REG_VAL_ENUM
+#define R_VECT_READ__scsi0__par0__VAL REG_VAL_ENUM
+#define R_VECT_READ__ata__ata__VAL REG_VAL_ENUM
+#define R_VECT_READ__scsi0__ata__VAL REG_VAL_ENUM
+#define R_VECT_READ__mio__mio__VAL REG_VAL_ENUM
+#define R_VECT_READ__scsi0__mio__VAL REG_VAL_ENUM
+#define R_VECT_READ__timer1__timer1__VAL REG_VAL_ENUM
+#define R_VECT_READ__timer0__timer0__VAL REG_VAL_ENUM
+#define R_VECT_READ__nmi__nmi__VAL REG_VAL_ENUM
+#define R_VECT_READ__some__some__VAL REG_VAL_ENUM
+
+#define R_VECT_READ__usb__usb__active 1
+#define R_VECT_READ__usb__usb__inactive 0
+#define R_VECT_READ__dma9__dma9__active 1
+#define R_VECT_READ__dma9__dma9__inactive 0
+#define R_VECT_READ__dma8__dma8__active 1
+#define R_VECT_READ__dma8__dma8__inactive 0
+#define R_VECT_READ__dma7__dma7__active 1
+#define R_VECT_READ__dma7__dma7__inactive 0
+#define R_VECT_READ__dma6__dma6__active 1
+#define R_VECT_READ__dma6__dma6__inactive 0
+#define R_VECT_READ__dma5__dma5__active 1
+#define R_VECT_READ__dma5__dma5__inactive 0
+#define R_VECT_READ__dma4__dma4__active 1
+#define R_VECT_READ__dma4__dma4__inactive 0
+#define R_VECT_READ__dma3__dma3__active 1
+#define R_VECT_READ__dma3__dma3__inactive 0
+#define R_VECT_READ__dma2__dma2__active 1
+#define R_VECT_READ__dma2__dma2__inactive 0
+#define R_VECT_READ__dma1__dma1__active 1
+#define R_VECT_READ__dma1__dma1__inactive 0
+#define R_VECT_READ__dma0__dma0__active 1
+#define R_VECT_READ__dma0__dma0__inactive 0
+#define R_VECT_READ__ext_dma1__ext_dma1__active 1
+#define R_VECT_READ__ext_dma1__ext_dma1__inactive 0
+#define R_VECT_READ__ext_dma0__ext_dma0__active 1
+#define R_VECT_READ__ext_dma0__ext_dma0__inactive 0
+#define R_VECT_READ__pa__pa__active 1
+#define R_VECT_READ__pa__pa__inactive 0
+#define R_VECT_READ__irq_intnr__irq_intnr__active 1
+#define R_VECT_READ__irq_intnr__irq_intnr__inactive 0
+#define R_VECT_READ__sw__sw__active 1
+#define R_VECT_READ__sw__sw__inactive 0
+#define R_VECT_READ__serial__serial__active 1
+#define R_VECT_READ__serial__serial__inactive 0
+#define R_VECT_READ__snmp__snmp__active 1
+#define R_VECT_READ__snmp__snmp__inactive 0
+#define R_VECT_READ__network__network__active 1
+#define R_VECT_READ__network__network__inactive 0
+#define R_VECT_READ__scsi1__scsi1__active 1
+#define R_VECT_READ__scsi1__scsi1__inactive 0
+#define R_VECT_READ__par1__par1__active 1
+#define R_VECT_READ__par1__par1__inactive 0
+#define R_VECT_READ__scsi0__scsi0__active 1
+#define R_VECT_READ__scsi0__scsi0__inactive 0
+#define R_VECT_READ__par0__par0__active 1
+#define R_VECT_READ__par0__par0__inactive 0
+#define R_VECT_READ__ata__ata__active 1
+#define R_VECT_READ__ata__ata__inactive 0
+#define R_VECT_READ__mio__mio__active 1
+#define R_VECT_READ__mio__mio__inactive 0
+#define R_VECT_READ__timer1__timer1__active 1
+#define R_VECT_READ__timer1__timer1__inactive 0
+#define R_VECT_READ__timer0__timer0__active 1
+#define R_VECT_READ__timer0__timer0__inactive 0
+#define R_VECT_READ__nmi__nmi__active 1
+#define R_VECT_READ__nmi__nmi__inactive 0
+#define R_VECT_READ__some__some__active 1
+#define R_VECT_READ__some__some__inactive 0
+
+#endif
+
+/*
+ * R_WAITSTATES
+ * - type: WO
+ * - addr: 0xb0000000
+ * - group: Bus interface configuration registers
+ */
+
+#if USE_GROUP__Bus_interface_configuration_registers
+
+#define R_WAITSTATES__ADDR (REG_TYPECAST_UDWORD 0xb0000000)
+
+#ifndef REG_NO_SHADOW
+#define R_WAITSTATES__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_WAITSTATES + 0))
+#define R_WAITSTATES__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_WAITSTATES + 0))
+#else /* REG_NO_SHADOW */
+#define R_WAITSTATES__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_WAITSTATES__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_WAITSTATES__STYPECAST REG_STYPECAST_UDWORD
+#define R_WAITSTATES__SVAL REG_SVAL_SHADOW
+#define R_WAITSTATES__SVAL_I REG_SVAL_I_SHADOW
+#define R_WAITSTATES__TYPECAST REG_TYPECAST_UDWORD
+#define R_WAITSTATES__TYPE (REG_UDWORD)
+#define R_WAITSTATES__GET REG_GET_WO
+#define R_WAITSTATES__IGET REG_IGET_WO
+#define R_WAITSTATES__SET REG_SET_WO
+#define R_WAITSTATES__ISET REG_ISET_WO
+#define R_WAITSTATES__SET_VAL REG_SET_VAL_WO
+#define R_WAITSTATES__EQL REG_EQL_WO
+#define R_WAITSTATES__IEQL REG_IEQL_WO
+#define R_WAITSTATES__RD REG_RD_WO
+#define R_WAITSTATES__IRD REG_IRD_WO
+#define R_WAITSTATES__WR REG_WR_WO
+#define R_WAITSTATES__IWR REG_IWR_WO
+
+#define R_WAITSTATES__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_WAITSTATES__pcs4_7_zw__pcs4_7_zw__MASK 0xc0000000U
+#define R_WAITSTATES__pcs4_7_ew__pcs4_7_ew__MASK 0x30000000U
+#define R_WAITSTATES__pcs4_7_lw__pcs4_7_lw__MASK 0x0f000000U
+#define R_WAITSTATES__pcs0_3_zw__pcs0_3_zw__MASK 0x00c00000U
+#define R_WAITSTATES__pcs0_3_ew__pcs0_3_ew__MASK 0x00300000U
+#define R_WAITSTATES__pcs0_3_lw__pcs0_3_lw__MASK 0x000f0000U
+#define R_WAITSTATES__sram_zw__sram_zw__MASK 0x0000c000U
+#define R_WAITSTATES__sram_ew__sram_ew__MASK 0x00003000U
+#define R_WAITSTATES__sram_lw__sram_lw__MASK 0x00000f00U
+#define R_WAITSTATES__flash_zw__flash_zw__MASK 0x000000c0U
+#define R_WAITSTATES__flash_ew__flash_ew__MASK 0x00000030U
+#define R_WAITSTATES__flash_lw__flash_lw__MASK 0x0000000fU
+
+#define R_WAITSTATES__pcs4_7_zw__MAX 3
+#define R_WAITSTATES__pcs4_7_ew__MAX 3
+#define R_WAITSTATES__pcs4_7_lw__MAX 15
+#define R_WAITSTATES__pcs0_3_zw__MAX 3
+#define R_WAITSTATES__pcs0_3_ew__MAX 3
+#define R_WAITSTATES__pcs0_3_lw__MAX 15
+#define R_WAITSTATES__sram_zw__MAX 3
+#define R_WAITSTATES__sram_ew__MAX 3
+#define R_WAITSTATES__sram_lw__MAX 15
+#define R_WAITSTATES__flash_zw__MAX 3
+#define R_WAITSTATES__flash_ew__MAX 3
+#define R_WAITSTATES__flash_lw__MAX 15
+
+#define R_WAITSTATES__pcs4_7_zw__MIN 0
+#define R_WAITSTATES__pcs4_7_ew__MIN 0
+#define R_WAITSTATES__pcs4_7_lw__MIN 0
+#define R_WAITSTATES__pcs0_3_zw__MIN 0
+#define R_WAITSTATES__pcs0_3_ew__MIN 0
+#define R_WAITSTATES__pcs0_3_lw__MIN 0
+#define R_WAITSTATES__sram_zw__MIN 0
+#define R_WAITSTATES__sram_ew__MIN 0
+#define R_WAITSTATES__sram_lw__MIN 0
+#define R_WAITSTATES__flash_zw__MIN 0
+#define R_WAITSTATES__flash_ew__MIN 0
+#define R_WAITSTATES__flash_lw__MIN 0
+
+#define R_WAITSTATES__pcs4_7_zw__BITNR 30
+#define R_WAITSTATES__pcs4_7_ew__BITNR 28
+#define R_WAITSTATES__pcs4_7_lw__BITNR 24
+#define R_WAITSTATES__pcs0_3_zw__BITNR 22
+#define R_WAITSTATES__pcs0_3_ew__BITNR 20
+#define R_WAITSTATES__pcs0_3_lw__BITNR 16
+#define R_WAITSTATES__sram_zw__BITNR 14
+#define R_WAITSTATES__sram_ew__BITNR 12
+#define R_WAITSTATES__sram_lw__BITNR 8
+#define R_WAITSTATES__flash_zw__BITNR 6
+#define R_WAITSTATES__flash_ew__BITNR 4
+#define R_WAITSTATES__flash_lw__BITNR 0
+
+#define R_WAITSTATES__pcs4_7_zw__pcs4_7_zw__VAL REG_VAL_VAL
+#define R_WAITSTATES__pcs4_7_ew__pcs4_7_ew__VAL REG_VAL_VAL
+#define R_WAITSTATES__pcs4_7_lw__pcs4_7_lw__VAL REG_VAL_VAL
+#define R_WAITSTATES__pcs0_3_zw__pcs0_3_zw__VAL REG_VAL_VAL
+#define R_WAITSTATES__pcs0_3_ew__pcs0_3_ew__VAL REG_VAL_VAL
+#define R_WAITSTATES__pcs0_3_lw__pcs0_3_lw__VAL REG_VAL_VAL
+#define R_WAITSTATES__sram_zw__sram_zw__VAL REG_VAL_VAL
+#define R_WAITSTATES__sram_ew__sram_ew__VAL REG_VAL_VAL
+#define R_WAITSTATES__sram_lw__sram_lw__VAL REG_VAL_VAL
+#define R_WAITSTATES__flash_zw__flash_zw__VAL REG_VAL_VAL
+#define R_WAITSTATES__flash_ew__flash_ew__VAL REG_VAL_VAL
+#define R_WAITSTATES__flash_lw__flash_lw__VAL REG_VAL_VAL
+
+
+#endif
+
+/*
+ * R_WATCHDOG
+ * - type: WO
+ * - addr: 0xb0000024
+ * - group: Timer registers
+ */
+
+#if USE_GROUP__Timer_registers
+
+#define R_WATCHDOG__ADDR (REG_TYPECAST_UDWORD 0xb0000024)
+
+#ifndef REG_NO_SHADOW
+#define R_WATCHDOG__SADDR (REG_STYPECAST_UDWORD (reg_shadow__hwregs.R_WATCHDOG + 0))
+#define R_WATCHDOG__IADDR (REG_STYPECAST_UDWORD (reg_initiated__hwregs.R_WATCHDOG + 0))
+#else /* REG_NO_SHADOW */
+#define R_WATCHDOG__SADDR (REG_STYPECAST_UDWORD (&reg_shadow__hwregs))
+#define R_WATCHDOG__IADDR (REG_STYPECAST_UDWORD (&reg_initiated__hwregs))
+#endif /* REG_NO_SHADOW */
+
+#define R_WATCHDOG__STYPECAST REG_STYPECAST_UDWORD
+#define R_WATCHDOG__SVAL REG_SVAL_SHADOW
+#define R_WATCHDOG__SVAL_I REG_SVAL_I_SHADOW
+#define R_WATCHDOG__TYPECAST REG_TYPECAST_UDWORD
+#define R_WATCHDOG__TYPE (REG_UDWORD)
+#define R_WATCHDOG__GET REG_GET_WO
+#define R_WATCHDOG__IGET REG_IGET_WO
+#define R_WATCHDOG__SET REG_SET_WO
+#define R_WATCHDOG__ISET REG_ISET_WO
+#define R_WATCHDOG__SET_VAL REG_SET_VAL_WO
+#define R_WATCHDOG__EQL REG_EQL_WO
+#define R_WATCHDOG__IEQL REG_IEQL_WO
+#define R_WATCHDOG__RD REG_RD_WO
+#define R_WATCHDOG__IRD REG_IRD_WO
+#define R_WATCHDOG__WR REG_WR_WO
+#define R_WATCHDOG__IWR REG_IWR_WO
+
+#define R_WATCHDOG__WRITE(addr,value) \
+ (*(addr) = (value))
+
+#define R_WATCHDOG__key__key__MASK 0x0000000eU
+#define R_WATCHDOG__enable__enable__MASK 0x00000001U
+
+#define R_WATCHDOG__key__MAX 7
+#define R_WATCHDOG__enable__MAX 0x1
+
+#define R_WATCHDOG__key__MIN 0
+#define R_WATCHDOG__enable__MIN 0
+
+#define R_WATCHDOG__key__BITNR 1
+#define R_WATCHDOG__enable__BITNR 0
+
+#define R_WATCHDOG__key__key__VAL REG_VAL_VAL
+#define R_WATCHDOG__enable__enable__VAL REG_VAL_ENUM
+
+#define R_WATCHDOG__enable__enable__start 1
+#define R_WATCHDOG__enable__enable__stop 0
+
+#endif
+
+#endif
diff --git a/package/etrax-tools/src/e100boot/cbl/src/ldscript b/package/etrax-tools/src/e100boot/cbl/src/ldscript
new file mode 100644
index 000000000..24c8a318a
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/ldscript
@@ -0,0 +1,38 @@
+SECTIONS
+{
+ . = 0x380000f0;
+ __Stext = .;
+
+ .text :
+ {
+ KEEP (*(.startup))
+ KEEP (*(.text))
+ *(.text.*)
+ KEEP (*(.rodata))
+ *(.rodata.*)
+ } =0
+
+ __Etext = .;
+
+ .data :
+ {
+ __Sdata = .;
+ KEEP (*(.data))
+ *(.data.*)
+ }
+
+ __Edata = .;
+ . = ALIGN (4);
+ __Sbss = .;
+ .bss :
+ {
+ /* The network crc will land in the first four bytes of the
+ bss. Move the variables out of the way. */
+ . = . + 12;
+ *(.bss.*)
+ *(COMMON)
+ }
+
+ __Ebss = .;
+
+}
diff --git a/package/etrax-tools/src/e100boot/cbl/src/net_init.c b/package/etrax-tools/src/e100boot/cbl/src/net_init.c
new file mode 100644
index 000000000..b6a56ad3a
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/net_init.c
@@ -0,0 +1,218 @@
+#define net_init init_interface
+#define handle_network_read handle_read
+#define send_network_ack send_ack
+#define send_network_string send_string
+#define send_network_hex send_hex
+
+#include "sv_addr_ag.h"
+#include "e100boot.h"
+
+static void start_network_trans(void);
+
+void
+net_init(void)
+{
+ *R_NETWORK_GA_1 = *R_NETWORK_GA_0 = 0;
+
+ SET_ETHER_ADDR(0x01,0x40,0x8c,0x00,0x01,0x00,
+ 0x01,0x40,0x8c,0x00,0x01,0x00);
+
+ *R_NETWORK_REC_CONFIG =
+ IO_STATE (R_NETWORK_REC_CONFIG, duplex, half) |
+ IO_STATE (R_NETWORK_REC_CONFIG, bad_crc, discard) |
+ IO_STATE (R_NETWORK_REC_CONFIG, oversize, discard) |
+ IO_STATE (R_NETWORK_REC_CONFIG, undersize, discard) |
+ IO_STATE (R_NETWORK_REC_CONFIG, all_roots, discard) |
+ IO_STATE (R_NETWORK_REC_CONFIG, broadcast, discard) |
+ IO_STATE (R_NETWORK_REC_CONFIG, individual, discard) |
+ IO_STATE (R_NETWORK_REC_CONFIG, ma1, disable) |
+ IO_STATE (R_NETWORK_REC_CONFIG, ma0, enable);
+
+ *R_NETWORK_MGM_CTRL =
+ IO_FIELD(R_NETWORK_MGM_CTRL, txd_pins, 0) |
+ IO_FIELD(R_NETWORK_MGM_CTRL, txer_pin, 0) |
+ IO_FIELD(R_NETWORK_MGM_CTRL, mdck, 0) |
+ IO_STATE(R_NETWORK_MGM_CTRL, mdoe, disable) |
+ IO_FIELD(R_NETWORK_MGM_CTRL, mdio, 0);
+
+ *R_NETWORK_TR_CTRL =
+ (IO_STATE (R_NETWORK_TR_CTRL, clr_error, clr) |
+ IO_STATE (R_NETWORK_TR_CTRL, delay, none) |
+ IO_STATE (R_NETWORK_TR_CTRL, cancel, dont) |
+ IO_STATE (R_NETWORK_TR_CTRL, cd, enable) |
+ IO_STATE (R_NETWORK_TR_CTRL, pad, enable) |
+ IO_STATE (R_NETWORK_TR_CTRL, crc, enable) |
+ IO_STATE (R_NETWORK_TR_CTRL, retry, enable));
+
+ *R_NETWORK_GEN_CONFIG =
+ IO_STATE (R_NETWORK_GEN_CONFIG, loopback, off) |
+ IO_STATE (R_NETWORK_GEN_CONFIG, frame, ether) |
+ IO_STATE (R_NETWORK_GEN_CONFIG, vg, off) |
+ IO_STATE (R_NETWORK_GEN_CONFIG, phy, mii_clk) |
+ IO_STATE (R_NETWORK_GEN_CONFIG, enable, on);
+
+ *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, reset);
+ *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, reset);
+
+ rx_descr.sw_len = NETWORK_HEADER_LENGTH;
+ rx_descr.ctrl = TX_CTRL;
+ rx_descr.next = (udword)&rx_descr2;
+ rx_descr.buf = (udword)&rx_header;
+
+ rx_descr2.sw_len = 1500;
+ rx_descr2.ctrl = TX_CTRL_EOP;
+ rx_descr2.buf = target_address;
+
+ /* Endian dependent, but saves a few bytes... */
+ *(udword*)&tx_header.src[0] = htonl(0x02408c00);
+ *(uword*)&tx_header.src[4] = htons(0x0100);
+ tx_header.length = htons(64);
+ tx_header.snap1 = htonl(0xaaaa0300);
+ tx_header.snap2 = htonl(0x408c8856);
+ tx_header.tag = htonl(0xfffffffe);
+ tx_header.seq = 0;
+ tx_header.type = 0;
+
+ tx_descr.sw_len = NETWORK_HEADER_LENGTH;
+ tx_descr.ctrl = TX_CTRL_EOP;
+ tx_descr.buf = (udword)&tx_header;
+
+ set_dest = FALSE;
+ seq = 0;
+
+ *R_DMA_CH1_FIRST = (udword)&rx_descr;
+ *R_DMA_CH1_CMD = IO_STATE(R_DMA_CH1_CMD, cmd, start);
+}
+
+int
+handle_network_read(void)
+{
+ if (!(rx_descr2.status & d_eop)) {
+ return FALSE;
+ }
+
+ /* Even if wasn't to us, we must do this... */
+ rx_descr2.status = 0;
+ *R_DMA_CH1_FIRST = (udword)&rx_descr;
+
+ /* Was it to me? */
+ if (ntohl(rx_header.seq) == (seq+1)) {
+ interface = NETWORK;
+ last_timeout = *R_TIMER_DATA >> IO_BITNR(R_TIMER_DATA, timer0);
+ nbr_read += rx_descr2.hw_len - CRC_LEN;
+ rx_descr2.buf += rx_descr2.hw_len - CRC_LEN;
+ rx_descr2.sw_len = bytes_to_read - nbr_read - CRC_LEN < 1500 ?
+ bytes_to_read - nbr_read + CRC_LEN: 1500; /* FIX!!!!! */
+ rx_descr2.sw_len = rx_descr2.sw_len + NETWORK_HEADER_LENGTH < 64
+ ? 64 - NETWORK_HEADER_LENGTH : rx_descr2.sw_len; /* Less than minimum eth packet? */
+
+ seq++;
+ send_network_ack();
+ }
+
+ return TRUE;
+}
+
+void
+send_network_ack(void)
+{
+/* send_serial_string(">send_network_ack.\r\n"); */
+
+ if (!set_dest) { /* Copy destination address from first received packet */
+ set_dest = TRUE;
+ /* If we have done a bootrom network boot, source address is in a different
+ place... */
+ if (((*R_BUS_STATUS & IO_MASK(R_BUS_STATUS, boot))
+ >> IO_BITNR(R_BUS_STATUS, boot)) - 1 == NETWORK) {
+ *(udword*)&tx_header.dest[0] = *(udword*)0x380000dc;
+ *(uword*)&tx_header.dest[4] = *(uword*)0x380000e0;
+ }
+ else {
+ *(udword*)&tx_header.dest[0] = *(udword*)&rx_header.src[0];
+ *(uword*)&tx_header.dest[4] = *(uword*)&rx_header.src[4];
+ }
+ }
+
+#if 1
+ tx_header.seq = htonl(seq);
+ tx_header.type = htonl(ACK);
+#else
+ tx_header.seq = htonl(seq);
+ tx_header.type = htonl(bytes_to_read);
+ tx_header.id = htonl(target_address);
+ /* tx_header.id already set in start(). */
+#endif
+
+ tx_descr.ctrl = TX_CTRL_EOP;
+ tx_descr.sw_len = NETWORK_HEADER_LENGTH;
+
+ start_network_trans();
+}
+
+void
+start_network_trans(void)
+{
+/* send_serial_string(">start_network_trans\r\n"); */
+
+ /* Clear possible underrun or excessive retry errors */
+/* *R_NETWORK_TR_CTRL = */
+/* (IO_STATE (R_NETWORK_TR_CTRL, clr_error, clr) | */
+/* IO_STATE (R_NETWORK_TR_CTRL, delay, none) | */
+/* IO_STATE (R_NETWORK_TR_CTRL, cancel, dont) | */
+/* IO_STATE (R_NETWORK_TR_CTRL, cd, enable) | */
+/* IO_STATE (R_NETWORK_TR_CTRL, pad, enable) | */
+/* IO_STATE (R_NETWORK_TR_CTRL, crc, enable) | */
+/* IO_STATE (R_NETWORK_TR_CTRL, retry, enable)); */
+
+ *R_DMA_CH0_FIRST = (udword)&tx_descr;
+ *R_DMA_CH0_CMD = IO_STATE(R_DMA_CH0_CMD, cmd, start);
+ while(*R_DMA_CH0_FIRST)
+ ;
+}
+
+void
+send_network_string(char *str)
+{
+ int i;
+
+ tx_descr.next = (udword)&tx_descr2;
+ tx_descr.ctrl = TX_CTRL;
+ for (i = 0; str[i]; i++) /* strlen */
+ ;
+
+ tx_header.type = STRING;
+
+ tx_descr2.ctrl = TX_CTRL_EOP;
+ tx_descr2.buf = (udword)str;
+ tx_descr2.sw_len = i+1;
+
+ start_network_trans();
+}
+
+void
+send_network_hex(udword v, byte nl)
+{
+ tx_descr.next = (udword)&tx_descr2;
+ tx_descr.ctrl = TX_CTRL;
+
+ tx_header.type = nl ? htonl(NET_INT_NL) : htonl(NET_INT);
+
+ /* Pause so we don't saturate network. */
+ /* Hehe, the asm will fool gcc to not remove the loop even though it
+ probably should. If we volatile i the code will be a few bytes
+ longer than this version. Well I really did it like this just
+ because it is possible... */
+ {
+ udword i;
+
+ for(i = 0; i != 16384; i++)
+ __asm__ ("");
+ }
+
+ v = htonl(v);
+ tx_descr2.ctrl = TX_CTRL_EOP;
+ tx_descr2.buf = (udword)&v;
+ tx_descr2.sw_len = (uword)sizeof(udword);
+
+ start_network_trans();
+}
diff --git a/package/etrax-tools/src/e100boot/cbl/src/project.h b/package/etrax-tools/src/e100boot/cbl/src/project.h
new file mode 100644
index 000000000..0d54f8fa6
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/project.h
@@ -0,0 +1,10 @@
+#define REG_NO_SHADOW 1
+#define REG_NO_INIT_SHADOW 1
+
+#define USE_GROUP__Serial_port_registers 1
+#define USE_GROUP__Network_interface_registers 1
+#define USE_GROUP__Parallel_printer_port_registers 1
+#define USE_GROUP__Timer_registers 1
+#define USE_GROUP__General_port_configuration_registers 1
+#define USE_GROUP__Bus_interface_configuration_registers 1
+#define USE_GROUP__DMA_registers 1
diff --git a/package/etrax-tools/src/e100boot/cbl/src/ser_init.c b/package/etrax-tools/src/e100boot/cbl/src/ser_init.c
new file mode 100644
index 000000000..2fcf4311c
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/ser_init.c
@@ -0,0 +1,117 @@
+#define ser_init init_interface
+#define handle_serial_read handle_read
+#define send_serial_ack send_ack
+#define send_serial_string send_string
+#define send_serial_hex send_hex
+
+#include "hwregs.h"
+#include "sv_addr_ag.h"
+#include "e100boot.h"
+
+void
+ser_init(void)
+{
+ REG_SET__R_SERIAL0_XOFF
+ (
+ tx_stop, enable,
+ auto_xoff, disable,
+ xoff_char, 0
+ );
+
+ REG_SET__R_SERIAL0_BAUD
+ (
+ tr_baud, c9600Hz,
+ rec_baud, c9600Hz
+ );
+
+ REG_SET__R_SERIAL0_REC_CTRL
+ (
+ dma_err, stop,
+ rec_enable, enable,
+ rts_, inactive,
+ sampling, middle,
+ rec_stick_par, normal,
+ rec_par, even,
+ rec_par_en, disable,
+ rec_bitnr, rec_8bit
+ );
+
+ REG_SET__R_SERIAL0_TR_CTRL
+ (
+ txd, 0,
+ tr_enable, enable,
+ auto_cts, disabled,
+ stop_bits, one_bit,
+ tr_stick_par, normal,
+ tr_par, even,
+ tr_par_en, disable,
+ tr_bitnr, tr_8bit
+ );
+
+ serial_up = TRUE;
+}
+
+#define SER_MASK (IO_MASK(R_SERIAL0_READ, data_avail) | IO_MASK(R_SERIAL0_READ, data_in))
+
+int
+handle_serial_read(void)
+{
+ udword status_and_data_in = *R_SERIAL0_READ & SER_MASK;
+
+ if (status_and_data_in & IO_STATE(R_SERIAL0_READ, data_avail, yes)) {
+ *(char*)(target_address + nbr_read++) = status_and_data_in & 0xff; /* ugly mask */
+ last_timeout = REG_GET(R_TIMER0_DATA, count);
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+void
+send_serial_ack(void)
+{
+ while (!REG_EQL(R_SERIAL0_STATUS, tr_ready, ready))
+ ;
+
+ REG_ISET(0, R_SERIAL0_TR_DATA, data_out, '+');
+}
+
+void
+send_serial_string(char *str)
+{
+ int i;
+
+ for (i = 0; str[i];) {
+ if (REG_IEQL(0, R_SERIAL0_STATUS, tr_ready, ready)) {
+ REG_ISET(0, R_SERIAL0_TR_DATA, data_out, str[i]);
+ i++;
+ }
+ }
+}
+
+void
+send_serial_hex(udword v, byte nl)
+{
+ int i;
+ byte buf[13];
+ byte nybble;
+
+ buf[0] = '0';
+ buf[1] = 'x';
+ buf[10] = '\r';
+ buf[11] = '\n';
+ buf[12] = '\0';
+
+ if (nl == FALSE) {
+ buf[10] = '\0';
+ }
+
+ for (i = 0; i != 8; i++) {
+ nybble = (v >> (i*4)) & 0xf;
+ if (nybble > 9) {
+ nybble += 7;
+ }
+ buf[7-i+2] = nybble + '0';
+ }
+ send_serial_string(buf);
+}
diff --git a/package/etrax-tools/src/e100boot/cbl/src/sv_addr.agh b/package/etrax-tools/src/e100boot/cbl/src/sv_addr.agh
new file mode 100644
index 000000000..99c5c691d
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/sv_addr.agh
@@ -0,0 +1,7323 @@
+/*
+!* This file was automatically generated by /n/asic/bin/reg_macro_gen
+!* from the file `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd', version 1.168.
+!* Editing within this file is thus not recommended,
+!* make the changes in `/n/asic/projects/etrax_ng/doc/work/etrax_ng_regs.rd' instead.
+!* Created: Wed Oct 2 22:32:57 2002 By: Id: reg_macro_gen,v 1.12 2002/09/18 14:08:01 stefanl Exp
+!*/
+
+
+/*
+!* Bus interface configuration registers
+!*/
+
+#define R_WAITSTATES (IO_TYPECAST_UDWORD 0xb0000000)
+#define R_WAITSTATES__pcs4_7_zw__BITNR 30
+#define R_WAITSTATES__pcs4_7_zw__WIDTH 2
+#define R_WAITSTATES__pcs4_7_ew__BITNR 28
+#define R_WAITSTATES__pcs4_7_ew__WIDTH 2
+#define R_WAITSTATES__pcs4_7_lw__BITNR 24
+#define R_WAITSTATES__pcs4_7_lw__WIDTH 4
+#define R_WAITSTATES__pcs0_3_zw__BITNR 22
+#define R_WAITSTATES__pcs0_3_zw__WIDTH 2
+#define R_WAITSTATES__pcs0_3_ew__BITNR 20
+#define R_WAITSTATES__pcs0_3_ew__WIDTH 2
+#define R_WAITSTATES__pcs0_3_lw__BITNR 16
+#define R_WAITSTATES__pcs0_3_lw__WIDTH 4
+#define R_WAITSTATES__sram_zw__BITNR 14
+#define R_WAITSTATES__sram_zw__WIDTH 2
+#define R_WAITSTATES__sram_ew__BITNR 12
+#define R_WAITSTATES__sram_ew__WIDTH 2
+#define R_WAITSTATES__sram_lw__BITNR 8
+#define R_WAITSTATES__sram_lw__WIDTH 4
+#define R_WAITSTATES__flash_zw__BITNR 6
+#define R_WAITSTATES__flash_zw__WIDTH 2
+#define R_WAITSTATES__flash_ew__BITNR 4
+#define R_WAITSTATES__flash_ew__WIDTH 2
+#define R_WAITSTATES__flash_lw__BITNR 0
+#define R_WAITSTATES__flash_lw__WIDTH 4
+
+#define R_BUS_CONFIG (IO_TYPECAST_UDWORD 0xb0000004)
+#define R_BUS_CONFIG__sram_type__BITNR 9
+#define R_BUS_CONFIG__sram_type__WIDTH 1
+#define R_BUS_CONFIG__sram_type__cwe 1
+#define R_BUS_CONFIG__sram_type__bwe 0
+#define R_BUS_CONFIG__dma_burst__BITNR 8
+#define R_BUS_CONFIG__dma_burst__WIDTH 1
+#define R_BUS_CONFIG__dma_burst__burst16 1
+#define R_BUS_CONFIG__dma_burst__burst32 0
+#define R_BUS_CONFIG__pcs4_7_wr__BITNR 7
+#define R_BUS_CONFIG__pcs4_7_wr__WIDTH 1
+#define R_BUS_CONFIG__pcs4_7_wr__ext 1
+#define R_BUS_CONFIG__pcs4_7_wr__norm 0
+#define R_BUS_CONFIG__pcs0_3_wr__BITNR 6
+#define R_BUS_CONFIG__pcs0_3_wr__WIDTH 1
+#define R_BUS_CONFIG__pcs0_3_wr__ext 1
+#define R_BUS_CONFIG__pcs0_3_wr__norm 0
+#define R_BUS_CONFIG__sram_wr__BITNR 5
+#define R_BUS_CONFIG__sram_wr__WIDTH 1
+#define R_BUS_CONFIG__sram_wr__ext 1
+#define R_BUS_CONFIG__sram_wr__norm 0
+#define R_BUS_CONFIG__flash_wr__BITNR 4
+#define R_BUS_CONFIG__flash_wr__WIDTH 1
+#define R_BUS_CONFIG__flash_wr__ext 1
+#define R_BUS_CONFIG__flash_wr__norm 0
+#define R_BUS_CONFIG__pcs4_7_bw__BITNR 3
+#define R_BUS_CONFIG__pcs4_7_bw__WIDTH 1
+#define R_BUS_CONFIG__pcs4_7_bw__bw32 1
+#define R_BUS_CONFIG__pcs4_7_bw__bw16 0
+#define R_BUS_CONFIG__pcs0_3_bw__BITNR 2
+#define R_BUS_CONFIG__pcs0_3_bw__WIDTH 1
+#define R_BUS_CONFIG__pcs0_3_bw__bw32 1
+#define R_BUS_CONFIG__pcs0_3_bw__bw16 0
+#define R_BUS_CONFIG__sram_bw__BITNR 1
+#define R_BUS_CONFIG__sram_bw__WIDTH 1
+#define R_BUS_CONFIG__sram_bw__bw32 1
+#define R_BUS_CONFIG__sram_bw__bw16 0
+#define R_BUS_CONFIG__flash_bw__BITNR 0
+#define R_BUS_CONFIG__flash_bw__WIDTH 1
+#define R_BUS_CONFIG__flash_bw__bw32 1
+#define R_BUS_CONFIG__flash_bw__bw16 0
+
+#define R_BUS_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000004)
+#define R_BUS_STATUS__pll_lock_tm__BITNR 5
+#define R_BUS_STATUS__pll_lock_tm__WIDTH 1
+#define R_BUS_STATUS__pll_lock_tm__expired 0
+#define R_BUS_STATUS__pll_lock_tm__counting 1
+#define R_BUS_STATUS__both_faults__BITNR 4
+#define R_BUS_STATUS__both_faults__WIDTH 1
+#define R_BUS_STATUS__both_faults__no 0
+#define R_BUS_STATUS__both_faults__yes 1
+#define R_BUS_STATUS__bsen___BITNR 3
+#define R_BUS_STATUS__bsen___WIDTH 1
+#define R_BUS_STATUS__bsen___enable 0
+#define R_BUS_STATUS__bsen___disable 1
+#define R_BUS_STATUS__boot__BITNR 1
+#define R_BUS_STATUS__boot__WIDTH 2
+#define R_BUS_STATUS__boot__uncached 0
+#define R_BUS_STATUS__boot__serial 1
+#define R_BUS_STATUS__boot__network 2
+#define R_BUS_STATUS__boot__parallel 3
+#define R_BUS_STATUS__flashw__BITNR 0
+#define R_BUS_STATUS__flashw__WIDTH 1
+#define R_BUS_STATUS__flashw__bw32 1
+#define R_BUS_STATUS__flashw__bw16 0
+
+#define R_DRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
+#define R_DRAM_TIMING__sdram__BITNR 31
+#define R_DRAM_TIMING__sdram__WIDTH 1
+#define R_DRAM_TIMING__sdram__enable 1
+#define R_DRAM_TIMING__sdram__disable 0
+#define R_DRAM_TIMING__ref__BITNR 14
+#define R_DRAM_TIMING__ref__WIDTH 2
+#define R_DRAM_TIMING__ref__e52us 0
+#define R_DRAM_TIMING__ref__e13us 1
+#define R_DRAM_TIMING__ref__e8700ns 2
+#define R_DRAM_TIMING__ref__disable 3
+#define R_DRAM_TIMING__rp__BITNR 12
+#define R_DRAM_TIMING__rp__WIDTH 2
+#define R_DRAM_TIMING__rs__BITNR 10
+#define R_DRAM_TIMING__rs__WIDTH 2
+#define R_DRAM_TIMING__rh__BITNR 8
+#define R_DRAM_TIMING__rh__WIDTH 2
+#define R_DRAM_TIMING__w__BITNR 7
+#define R_DRAM_TIMING__w__WIDTH 1
+#define R_DRAM_TIMING__w__norm 0
+#define R_DRAM_TIMING__w__ext 1
+#define R_DRAM_TIMING__c__BITNR 6
+#define R_DRAM_TIMING__c__WIDTH 1
+#define R_DRAM_TIMING__c__norm 0
+#define R_DRAM_TIMING__c__ext 1
+#define R_DRAM_TIMING__cz__BITNR 4
+#define R_DRAM_TIMING__cz__WIDTH 2
+#define R_DRAM_TIMING__cp__BITNR 2
+#define R_DRAM_TIMING__cp__WIDTH 2
+#define R_DRAM_TIMING__cw__BITNR 0
+#define R_DRAM_TIMING__cw__WIDTH 2
+
+#define R_SDRAM_TIMING (IO_TYPECAST_UDWORD 0xb0000008)
+#define R_SDRAM_TIMING__sdram__BITNR 31
+#define R_SDRAM_TIMING__sdram__WIDTH 1
+#define R_SDRAM_TIMING__sdram__enable 1
+#define R_SDRAM_TIMING__sdram__disable 0
+#define R_SDRAM_TIMING__mrs_data__BITNR 16
+#define R_SDRAM_TIMING__mrs_data__WIDTH 15
+#define R_SDRAM_TIMING__ref__BITNR 14
+#define R_SDRAM_TIMING__ref__WIDTH 2
+#define R_SDRAM_TIMING__ref__e52us 0
+#define R_SDRAM_TIMING__ref__e13us 1
+#define R_SDRAM_TIMING__ref__e6500ns 2
+#define R_SDRAM_TIMING__ref__disable 3
+#define R_SDRAM_TIMING__ddr__BITNR 13
+#define R_SDRAM_TIMING__ddr__WIDTH 1
+#define R_SDRAM_TIMING__ddr__on 1
+#define R_SDRAM_TIMING__ddr__off 0
+#define R_SDRAM_TIMING__clk100__BITNR 12
+#define R_SDRAM_TIMING__clk100__WIDTH 1
+#define R_SDRAM_TIMING__clk100__on 1
+#define R_SDRAM_TIMING__clk100__off 0
+#define R_SDRAM_TIMING__ps__BITNR 11
+#define R_SDRAM_TIMING__ps__WIDTH 1
+#define R_SDRAM_TIMING__ps__on 1
+#define R_SDRAM_TIMING__ps__off 0
+#define R_SDRAM_TIMING__cmd__BITNR 9
+#define R_SDRAM_TIMING__cmd__WIDTH 2
+#define R_SDRAM_TIMING__cmd__pre 3
+#define R_SDRAM_TIMING__cmd__ref 2
+#define R_SDRAM_TIMING__cmd__mrs 1
+#define R_SDRAM_TIMING__cmd__nop 0
+#define R_SDRAM_TIMING__pde__BITNR 8
+#define R_SDRAM_TIMING__pde__WIDTH 1
+#define R_SDRAM_TIMING__rc__BITNR 6
+#define R_SDRAM_TIMING__rc__WIDTH 2
+#define R_SDRAM_TIMING__rp__BITNR 4
+#define R_SDRAM_TIMING__rp__WIDTH 2
+#define R_SDRAM_TIMING__rcd__BITNR 2
+#define R_SDRAM_TIMING__rcd__WIDTH 2
+#define R_SDRAM_TIMING__cl__BITNR 0
+#define R_SDRAM_TIMING__cl__WIDTH 2
+
+#define R_DRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
+#define R_DRAM_CONFIG__wmm1__BITNR 31
+#define R_DRAM_CONFIG__wmm1__WIDTH 1
+#define R_DRAM_CONFIG__wmm1__wmm 1
+#define R_DRAM_CONFIG__wmm1__norm 0
+#define R_DRAM_CONFIG__wmm0__BITNR 30
+#define R_DRAM_CONFIG__wmm0__WIDTH 1
+#define R_DRAM_CONFIG__wmm0__wmm 1
+#define R_DRAM_CONFIG__wmm0__norm 0
+#define R_DRAM_CONFIG__sh1__BITNR 27
+#define R_DRAM_CONFIG__sh1__WIDTH 3
+#define R_DRAM_CONFIG__sh0__BITNR 24
+#define R_DRAM_CONFIG__sh0__WIDTH 3
+#define R_DRAM_CONFIG__w__BITNR 23
+#define R_DRAM_CONFIG__w__WIDTH 1
+#define R_DRAM_CONFIG__w__bw16 0
+#define R_DRAM_CONFIG__w__bw32 1
+#define R_DRAM_CONFIG__c__BITNR 22
+#define R_DRAM_CONFIG__c__WIDTH 1
+#define R_DRAM_CONFIG__c__byte 0
+#define R_DRAM_CONFIG__c__bank 1
+#define R_DRAM_CONFIG__e__BITNR 21
+#define R_DRAM_CONFIG__e__WIDTH 1
+#define R_DRAM_CONFIG__e__fast 0
+#define R_DRAM_CONFIG__e__edo 1
+#define R_DRAM_CONFIG__group_sel__BITNR 16
+#define R_DRAM_CONFIG__group_sel__WIDTH 5
+#define R_DRAM_CONFIG__group_sel__grp0 0
+#define R_DRAM_CONFIG__group_sel__grp1 1
+#define R_DRAM_CONFIG__group_sel__bit9 9
+#define R_DRAM_CONFIG__group_sel__bit10 10
+#define R_DRAM_CONFIG__group_sel__bit11 11
+#define R_DRAM_CONFIG__group_sel__bit12 12
+#define R_DRAM_CONFIG__group_sel__bit13 13
+#define R_DRAM_CONFIG__group_sel__bit14 14
+#define R_DRAM_CONFIG__group_sel__bit15 15
+#define R_DRAM_CONFIG__group_sel__bit16 16
+#define R_DRAM_CONFIG__group_sel__bit17 17
+#define R_DRAM_CONFIG__group_sel__bit18 18
+#define R_DRAM_CONFIG__group_sel__bit19 19
+#define R_DRAM_CONFIG__group_sel__bit20 20
+#define R_DRAM_CONFIG__group_sel__bit21 21
+#define R_DRAM_CONFIG__group_sel__bit22 22
+#define R_DRAM_CONFIG__group_sel__bit23 23
+#define R_DRAM_CONFIG__group_sel__bit24 24
+#define R_DRAM_CONFIG__group_sel__bit25 25
+#define R_DRAM_CONFIG__group_sel__bit26 26
+#define R_DRAM_CONFIG__group_sel__bit27 27
+#define R_DRAM_CONFIG__group_sel__bit28 28
+#define R_DRAM_CONFIG__group_sel__bit29 29
+#define R_DRAM_CONFIG__ca1__BITNR 13
+#define R_DRAM_CONFIG__ca1__WIDTH 3
+#define R_DRAM_CONFIG__bank23sel__BITNR 8
+#define R_DRAM_CONFIG__bank23sel__WIDTH 5
+#define R_DRAM_CONFIG__bank23sel__bank0 0
+#define R_DRAM_CONFIG__bank23sel__bank1 1
+#define R_DRAM_CONFIG__bank23sel__bit9 9
+#define R_DRAM_CONFIG__bank23sel__bit10 10
+#define R_DRAM_CONFIG__bank23sel__bit11 11
+#define R_DRAM_CONFIG__bank23sel__bit12 12
+#define R_DRAM_CONFIG__bank23sel__bit13 13
+#define R_DRAM_CONFIG__bank23sel__bit14 14
+#define R_DRAM_CONFIG__bank23sel__bit15 15
+#define R_DRAM_CONFIG__bank23sel__bit16 16
+#define R_DRAM_CONFIG__bank23sel__bit17 17
+#define R_DRAM_CONFIG__bank23sel__bit18 18
+#define R_DRAM_CONFIG__bank23sel__bit19 19
+#define R_DRAM_CONFIG__bank23sel__bit20 20
+#define R_DRAM_CONFIG__bank23sel__bit21 21
+#define R_DRAM_CONFIG__bank23sel__bit22 22
+#define R_DRAM_CONFIG__bank23sel__bit23 23
+#define R_DRAM_CONFIG__bank23sel__bit24 24
+#define R_DRAM_CONFIG__bank23sel__bit25 25
+#define R_DRAM_CONFIG__bank23sel__bit26 26
+#define R_DRAM_CONFIG__bank23sel__bit27 27
+#define R_DRAM_CONFIG__bank23sel__bit28 28
+#define R_DRAM_CONFIG__bank23sel__bit29 29
+#define R_DRAM_CONFIG__ca0__BITNR 5
+#define R_DRAM_CONFIG__ca0__WIDTH 3
+#define R_DRAM_CONFIG__bank01sel__BITNR 0
+#define R_DRAM_CONFIG__bank01sel__WIDTH 5
+#define R_DRAM_CONFIG__bank01sel__bank0 0
+#define R_DRAM_CONFIG__bank01sel__bank1 1
+#define R_DRAM_CONFIG__bank01sel__bit9 9
+#define R_DRAM_CONFIG__bank01sel__bit10 10
+#define R_DRAM_CONFIG__bank01sel__bit11 11
+#define R_DRAM_CONFIG__bank01sel__bit12 12
+#define R_DRAM_CONFIG__bank01sel__bit13 13
+#define R_DRAM_CONFIG__bank01sel__bit14 14
+#define R_DRAM_CONFIG__bank01sel__bit15 15
+#define R_DRAM_CONFIG__bank01sel__bit16 16
+#define R_DRAM_CONFIG__bank01sel__bit17 17
+#define R_DRAM_CONFIG__bank01sel__bit18 18
+#define R_DRAM_CONFIG__bank01sel__bit19 19
+#define R_DRAM_CONFIG__bank01sel__bit20 20
+#define R_DRAM_CONFIG__bank01sel__bit21 21
+#define R_DRAM_CONFIG__bank01sel__bit22 22
+#define R_DRAM_CONFIG__bank01sel__bit23 23
+#define R_DRAM_CONFIG__bank01sel__bit24 24
+#define R_DRAM_CONFIG__bank01sel__bit25 25
+#define R_DRAM_CONFIG__bank01sel__bit26 26
+#define R_DRAM_CONFIG__bank01sel__bit27 27
+#define R_DRAM_CONFIG__bank01sel__bit28 28
+#define R_DRAM_CONFIG__bank01sel__bit29 29
+
+#define R_SDRAM_CONFIG (IO_TYPECAST_UDWORD 0xb000000c)
+#define R_SDRAM_CONFIG__wmm1__BITNR 31
+#define R_SDRAM_CONFIG__wmm1__WIDTH 1
+#define R_SDRAM_CONFIG__wmm1__wmm 1
+#define R_SDRAM_CONFIG__wmm1__norm 0
+#define R_SDRAM_CONFIG__wmm0__BITNR 30
+#define R_SDRAM_CONFIG__wmm0__WIDTH 1
+#define R_SDRAM_CONFIG__wmm0__wmm 1
+#define R_SDRAM_CONFIG__wmm0__norm 0
+#define R_SDRAM_CONFIG__sh1__BITNR 27
+#define R_SDRAM_CONFIG__sh1__WIDTH 3
+#define R_SDRAM_CONFIG__sh0__BITNR 24
+#define R_SDRAM_CONFIG__sh0__WIDTH 3
+#define R_SDRAM_CONFIG__w__BITNR 23
+#define R_SDRAM_CONFIG__w__WIDTH 1
+#define R_SDRAM_CONFIG__w__bw16 0
+#define R_SDRAM_CONFIG__w__bw32 1
+#define R_SDRAM_CONFIG__type1__BITNR 22
+#define R_SDRAM_CONFIG__type1__WIDTH 1
+#define R_SDRAM_CONFIG__type1__bank2 0
+#define R_SDRAM_CONFIG__type1__bank4 1
+#define R_SDRAM_CONFIG__type0__BITNR 21
+#define R_SDRAM_CONFIG__type0__WIDTH 1
+#define R_SDRAM_CONFIG__type0__bank2 0
+#define R_SDRAM_CONFIG__type0__bank4 1
+#define R_SDRAM_CONFIG__group_sel__BITNR 16
+#define R_SDRAM_CONFIG__group_sel__WIDTH 5
+#define R_SDRAM_CONFIG__group_sel__grp0 0
+#define R_SDRAM_CONFIG__group_sel__grp1 1
+#define R_SDRAM_CONFIG__group_sel__bit9 9
+#define R_SDRAM_CONFIG__group_sel__bit10 10
+#define R_SDRAM_CONFIG__group_sel__bit11 11
+#define R_SDRAM_CONFIG__group_sel__bit12 12
+#define R_SDRAM_CONFIG__group_sel__bit13 13
+#define R_SDRAM_CONFIG__group_sel__bit14 14
+#define R_SDRAM_CONFIG__group_sel__bit15 15
+#define R_SDRAM_CONFIG__group_sel__bit16 16
+#define R_SDRAM_CONFIG__group_sel__bit17 17
+#define R_SDRAM_CONFIG__group_sel__bit18 18
+#define R_SDRAM_CONFIG__group_sel__bit19 19
+#define R_SDRAM_CONFIG__group_sel__bit20 20
+#define R_SDRAM_CONFIG__group_sel__bit21 21
+#define R_SDRAM_CONFIG__group_sel__bit22 22
+#define R_SDRAM_CONFIG__group_sel__bit23 23
+#define R_SDRAM_CONFIG__group_sel__bit24 24
+#define R_SDRAM_CONFIG__group_sel__bit25 25
+#define R_SDRAM_CONFIG__group_sel__bit26 26
+#define R_SDRAM_CONFIG__group_sel__bit27 27
+#define R_SDRAM_CONFIG__group_sel__bit28 28
+#define R_SDRAM_CONFIG__group_sel__bit29 29
+#define R_SDRAM_CONFIG__ca1__BITNR 13
+#define R_SDRAM_CONFIG__ca1__WIDTH 3
+#define R_SDRAM_CONFIG__bank_sel1__BITNR 8
+#define R_SDRAM_CONFIG__bank_sel1__WIDTH 5
+#define R_SDRAM_CONFIG__bank_sel1__bit9 9
+#define R_SDRAM_CONFIG__bank_sel1__bit10 10
+#define R_SDRAM_CONFIG__bank_sel1__bit11 11
+#define R_SDRAM_CONFIG__bank_sel1__bit12 12
+#define R_SDRAM_CONFIG__bank_sel1__bit13 13
+#define R_SDRAM_CONFIG__bank_sel1__bit14 14
+#define R_SDRAM_CONFIG__bank_sel1__bit15 15
+#define R_SDRAM_CONFIG__bank_sel1__bit16 16
+#define R_SDRAM_CONFIG__bank_sel1__bit17 17
+#define R_SDRAM_CONFIG__bank_sel1__bit18 18
+#define R_SDRAM_CONFIG__bank_sel1__bit19 19
+#define R_SDRAM_CONFIG__bank_sel1__bit20 20
+#define R_SDRAM_CONFIG__bank_sel1__bit21 21
+#define R_SDRAM_CONFIG__bank_sel1__bit22 22
+#define R_SDRAM_CONFIG__bank_sel1__bit23 23
+#define R_SDRAM_CONFIG__bank_sel1__bit24 24
+#define R_SDRAM_CONFIG__bank_sel1__bit25 25
+#define R_SDRAM_CONFIG__bank_sel1__bit26 26
+#define R_SDRAM_CONFIG__bank_sel1__bit27 27
+#define R_SDRAM_CONFIG__bank_sel1__bit28 28
+#define R_SDRAM_CONFIG__bank_sel1__bit29 29
+#define R_SDRAM_CONFIG__ca0__BITNR 5
+#define R_SDRAM_CONFIG__ca0__WIDTH 3
+#define R_SDRAM_CONFIG__bank_sel0__BITNR 0
+#define R_SDRAM_CONFIG__bank_sel0__WIDTH 5
+#define R_SDRAM_CONFIG__bank_sel0__bit9 9
+#define R_SDRAM_CONFIG__bank_sel0__bit10 10
+#define R_SDRAM_CONFIG__bank_sel0__bit11 11
+#define R_SDRAM_CONFIG__bank_sel0__bit12 12
+#define R_SDRAM_CONFIG__bank_sel0__bit13 13
+#define R_SDRAM_CONFIG__bank_sel0__bit14 14
+#define R_SDRAM_CONFIG__bank_sel0__bit15 15
+#define R_SDRAM_CONFIG__bank_sel0__bit16 16
+#define R_SDRAM_CONFIG__bank_sel0__bit17 17
+#define R_SDRAM_CONFIG__bank_sel0__bit18 18
+#define R_SDRAM_CONFIG__bank_sel0__bit19 19
+#define R_SDRAM_CONFIG__bank_sel0__bit20 20
+#define R_SDRAM_CONFIG__bank_sel0__bit21 21
+#define R_SDRAM_CONFIG__bank_sel0__bit22 22
+#define R_SDRAM_CONFIG__bank_sel0__bit23 23
+#define R_SDRAM_CONFIG__bank_sel0__bit24 24
+#define R_SDRAM_CONFIG__bank_sel0__bit25 25
+#define R_SDRAM_CONFIG__bank_sel0__bit26 26
+#define R_SDRAM_CONFIG__bank_sel0__bit27 27
+#define R_SDRAM_CONFIG__bank_sel0__bit28 28
+#define R_SDRAM_CONFIG__bank_sel0__bit29 29
+
+/*
+!* External DMA registers
+!*/
+
+#define R_EXT_DMA_0_CMD (IO_TYPECAST_UDWORD 0xb0000010)
+#define R_EXT_DMA_0_CMD__cnt__BITNR 23
+#define R_EXT_DMA_0_CMD__cnt__WIDTH 1
+#define R_EXT_DMA_0_CMD__cnt__enable 1
+#define R_EXT_DMA_0_CMD__cnt__disable 0
+#define R_EXT_DMA_0_CMD__rqpol__BITNR 22
+#define R_EXT_DMA_0_CMD__rqpol__WIDTH 1
+#define R_EXT_DMA_0_CMD__rqpol__ahigh 0
+#define R_EXT_DMA_0_CMD__rqpol__alow 1
+#define R_EXT_DMA_0_CMD__apol__BITNR 21
+#define R_EXT_DMA_0_CMD__apol__WIDTH 1
+#define R_EXT_DMA_0_CMD__apol__ahigh 0
+#define R_EXT_DMA_0_CMD__apol__alow 1
+#define R_EXT_DMA_0_CMD__rq_ack__BITNR 20
+#define R_EXT_DMA_0_CMD__rq_ack__WIDTH 1
+#define R_EXT_DMA_0_CMD__rq_ack__burst 0
+#define R_EXT_DMA_0_CMD__rq_ack__handsh 1
+#define R_EXT_DMA_0_CMD__wid__BITNR 18
+#define R_EXT_DMA_0_CMD__wid__WIDTH 2
+#define R_EXT_DMA_0_CMD__wid__byte 0
+#define R_EXT_DMA_0_CMD__wid__word 1
+#define R_EXT_DMA_0_CMD__wid__dword 2
+#define R_EXT_DMA_0_CMD__dir__BITNR 17
+#define R_EXT_DMA_0_CMD__dir__WIDTH 1
+#define R_EXT_DMA_0_CMD__dir__input 0
+#define R_EXT_DMA_0_CMD__dir__output 1
+#define R_EXT_DMA_0_CMD__run__BITNR 16
+#define R_EXT_DMA_0_CMD__run__WIDTH 1
+#define R_EXT_DMA_0_CMD__run__start 1
+#define R_EXT_DMA_0_CMD__run__stop 0
+#define R_EXT_DMA_0_CMD__trf_count__BITNR 0
+#define R_EXT_DMA_0_CMD__trf_count__WIDTH 16
+
+#define R_EXT_DMA_0_STAT (IO_TYPECAST_RO_UDWORD 0xb0000010)
+#define R_EXT_DMA_0_STAT__run__BITNR 16
+#define R_EXT_DMA_0_STAT__run__WIDTH 1
+#define R_EXT_DMA_0_STAT__run__start 1
+#define R_EXT_DMA_0_STAT__run__stop 0
+#define R_EXT_DMA_0_STAT__trf_count__BITNR 0
+#define R_EXT_DMA_0_STAT__trf_count__WIDTH 16
+
+#define R_EXT_DMA_0_ADDR (IO_TYPECAST_UDWORD 0xb0000014)
+#define R_EXT_DMA_0_ADDR__ext0_addr__BITNR 2
+#define R_EXT_DMA_0_ADDR__ext0_addr__WIDTH 28
+
+#define R_EXT_DMA_1_CMD (IO_TYPECAST_UDWORD 0xb0000018)
+#define R_EXT_DMA_1_CMD__cnt__BITNR 23
+#define R_EXT_DMA_1_CMD__cnt__WIDTH 1
+#define R_EXT_DMA_1_CMD__cnt__enable 1
+#define R_EXT_DMA_1_CMD__cnt__disable 0
+#define R_EXT_DMA_1_CMD__rqpol__BITNR 22
+#define R_EXT_DMA_1_CMD__rqpol__WIDTH 1
+#define R_EXT_DMA_1_CMD__rqpol__ahigh 0
+#define R_EXT_DMA_1_CMD__rqpol__alow 1
+#define R_EXT_DMA_1_CMD__apol__BITNR 21
+#define R_EXT_DMA_1_CMD__apol__WIDTH 1
+#define R_EXT_DMA_1_CMD__apol__ahigh 0
+#define R_EXT_DMA_1_CMD__apol__alow 1
+#define R_EXT_DMA_1_CMD__rq_ack__BITNR 20
+#define R_EXT_DMA_1_CMD__rq_ack__WIDTH 1
+#define R_EXT_DMA_1_CMD__rq_ack__burst 0
+#define R_EXT_DMA_1_CMD__rq_ack__handsh 1
+#define R_EXT_DMA_1_CMD__wid__BITNR 18
+#define R_EXT_DMA_1_CMD__wid__WIDTH 2
+#define R_EXT_DMA_1_CMD__wid__byte 0
+#define R_EXT_DMA_1_CMD__wid__word 1
+#define R_EXT_DMA_1_CMD__wid__dword 2
+#define R_EXT_DMA_1_CMD__dir__BITNR 17
+#define R_EXT_DMA_1_CMD__dir__WIDTH 1
+#define R_EXT_DMA_1_CMD__dir__input 0
+#define R_EXT_DMA_1_CMD__dir__output 1
+#define R_EXT_DMA_1_CMD__run__BITNR 16
+#define R_EXT_DMA_1_CMD__run__WIDTH 1
+#define R_EXT_DMA_1_CMD__run__start 1
+#define R_EXT_DMA_1_CMD__run__stop 0
+#define R_EXT_DMA_1_CMD__trf_count__BITNR 0
+#define R_EXT_DMA_1_CMD__trf_count__WIDTH 16
+
+#define R_EXT_DMA_1_STAT (IO_TYPECAST_RO_UDWORD 0xb0000018)
+#define R_EXT_DMA_1_STAT__run__BITNR 16
+#define R_EXT_DMA_1_STAT__run__WIDTH 1
+#define R_EXT_DMA_1_STAT__run__start 1
+#define R_EXT_DMA_1_STAT__run__stop 0
+#define R_EXT_DMA_1_STAT__trf_count__BITNR 0
+#define R_EXT_DMA_1_STAT__trf_count__WIDTH 16
+
+#define R_EXT_DMA_1_ADDR (IO_TYPECAST_UDWORD 0xb000001c)
+#define R_EXT_DMA_1_ADDR__ext0_addr__BITNR 2
+#define R_EXT_DMA_1_ADDR__ext0_addr__WIDTH 28
+
+/*
+!* Timer registers
+!*/
+
+#define R_TIMER_CTRL (IO_TYPECAST_UDWORD 0xb0000020)
+#define R_TIMER_CTRL__timerdiv1__BITNR 24
+#define R_TIMER_CTRL__timerdiv1__WIDTH 8
+#define R_TIMER_CTRL__timerdiv0__BITNR 16
+#define R_TIMER_CTRL__timerdiv0__WIDTH 8
+#define R_TIMER_CTRL__presc_timer1__BITNR 15
+#define R_TIMER_CTRL__presc_timer1__WIDTH 1
+#define R_TIMER_CTRL__presc_timer1__normal 0
+#define R_TIMER_CTRL__presc_timer1__prescale 1
+#define R_TIMER_CTRL__i1__BITNR 14
+#define R_TIMER_CTRL__i1__WIDTH 1
+#define R_TIMER_CTRL__i1__clr 1
+#define R_TIMER_CTRL__i1__nop 0
+#define R_TIMER_CTRL__tm1__BITNR 12
+#define R_TIMER_CTRL__tm1__WIDTH 2
+#define R_TIMER_CTRL__tm1__stop_ld 0
+#define R_TIMER_CTRL__tm1__freeze 1
+#define R_TIMER_CTRL__tm1__run 2
+#define R_TIMER_CTRL__tm1__reserved 3
+#define R_TIMER_CTRL__clksel1__BITNR 8
+#define R_TIMER_CTRL__clksel1__WIDTH 4
+#define R_TIMER_CTRL__clksel1__c300Hz 0
+#define R_TIMER_CTRL__clksel1__c600Hz 1
+#define R_TIMER_CTRL__clksel1__c1200Hz 2
+#define R_TIMER_CTRL__clksel1__c2400Hz 3
+#define R_TIMER_CTRL__clksel1__c4800Hz 4
+#define R_TIMER_CTRL__clksel1__c9600Hz 5
+#define R_TIMER_CTRL__clksel1__c19k2Hz 6
+#define R_TIMER_CTRL__clksel1__c38k4Hz 7
+#define R_TIMER_CTRL__clksel1__c57k6Hz 8
+#define R_TIMER_CTRL__clksel1__c115k2Hz 9
+#define R_TIMER_CTRL__clksel1__c230k4Hz 10
+#define R_TIMER_CTRL__clksel1__c460k8Hz 11
+#define R_TIMER_CTRL__clksel1__c921k6Hz 12
+#define R_TIMER_CTRL__clksel1__c1843k2Hz 13
+#define R_TIMER_CTRL__clksel1__c6250kHz 14
+#define R_TIMER_CTRL__clksel1__cascade0 15
+#define R_TIMER_CTRL__presc_ext__BITNR 7
+#define R_TIMER_CTRL__presc_ext__WIDTH 1
+#define R_TIMER_CTRL__presc_ext__prescale 0
+#define R_TIMER_CTRL__presc_ext__external 1
+#define R_TIMER_CTRL__i0__BITNR 6
+#define R_TIMER_CTRL__i0__WIDTH 1
+#define R_TIMER_CTRL__i0__clr 1
+#define R_TIMER_CTRL__i0__nop 0
+#define R_TIMER_CTRL__tm0__BITNR 4
+#define R_TIMER_CTRL__tm0__WIDTH 2
+#define R_TIMER_CTRL__tm0__stop_ld 0
+#define R_TIMER_CTRL__tm0__freeze 1
+#define R_TIMER_CTRL__tm0__run 2
+#define R_TIMER_CTRL__tm0__reserved 3
+#define R_TIMER_CTRL__clksel0__BITNR 0
+#define R_TIMER_CTRL__clksel0__WIDTH 4
+#define R_TIMER_CTRL__clksel0__c300Hz 0
+#define R_TIMER_CTRL__clksel0__c600Hz 1
+#define R_TIMER_CTRL__clksel0__c1200Hz 2
+#define R_TIMER_CTRL__clksel0__c2400Hz 3
+#define R_TIMER_CTRL__clksel0__c4800Hz 4
+#define R_TIMER_CTRL__clksel0__c9600Hz 5
+#define R_TIMER_CTRL__clksel0__c19k2Hz 6
+#define R_TIMER_CTRL__clksel0__c38k4Hz 7
+#define R_TIMER_CTRL__clksel0__c57k6Hz 8
+#define R_TIMER_CTRL__clksel0__c115k2Hz 9
+#define R_TIMER_CTRL__clksel0__c230k4Hz 10
+#define R_TIMER_CTRL__clksel0__c460k8Hz 11
+#define R_TIMER_CTRL__clksel0__c921k6Hz 12
+#define R_TIMER_CTRL__clksel0__c1843k2Hz 13
+#define R_TIMER_CTRL__clksel0__c6250kHz 14
+#define R_TIMER_CTRL__clksel0__flexible 15
+
+#define R_TIMER_DATA (IO_TYPECAST_RO_UDWORD 0xb0000020)
+#define R_TIMER_DATA__timer1__BITNR 24
+#define R_TIMER_DATA__timer1__WIDTH 8
+#define R_TIMER_DATA__timer0__BITNR 16
+#define R_TIMER_DATA__timer0__WIDTH 8
+#define R_TIMER_DATA__clkdiv_high__BITNR 8
+#define R_TIMER_DATA__clkdiv_high__WIDTH 8
+#define R_TIMER_DATA__clkdiv_low__BITNR 0
+#define R_TIMER_DATA__clkdiv_low__WIDTH 8
+
+#define R_TIMER01_DATA (IO_TYPECAST_RO_UWORD 0xb0000022)
+#define R_TIMER01_DATA__count__BITNR 0
+#define R_TIMER01_DATA__count__WIDTH 16
+
+#define R_TIMER0_DATA (IO_TYPECAST_RO_BYTE 0xb0000022)
+#define R_TIMER0_DATA__count__BITNR 0
+#define R_TIMER0_DATA__count__WIDTH 8
+
+#define R_TIMER1_DATA (IO_TYPECAST_RO_BYTE 0xb0000023)
+#define R_TIMER1_DATA__count__BITNR 0
+#define R_TIMER1_DATA__count__WIDTH 8
+
+#define R_WATCHDOG (IO_TYPECAST_UDWORD 0xb0000024)
+#define R_WATCHDOG__key__BITNR 1
+#define R_WATCHDOG__key__WIDTH 3
+#define R_WATCHDOG__enable__BITNR 0
+#define R_WATCHDOG__enable__WIDTH 1
+#define R_WATCHDOG__enable__stop 0
+#define R_WATCHDOG__enable__start 1
+
+#define R_CLOCK_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f0)
+#define R_CLOCK_PRESCALE__ser_presc__BITNR 16
+#define R_CLOCK_PRESCALE__ser_presc__WIDTH 16
+#define R_CLOCK_PRESCALE__tim_presc__BITNR 0
+#define R_CLOCK_PRESCALE__tim_presc__WIDTH 16
+
+#define R_SERIAL_PRESCALE (IO_TYPECAST_UWORD 0xb00000f2)
+#define R_SERIAL_PRESCALE__ser_presc__BITNR 0
+#define R_SERIAL_PRESCALE__ser_presc__WIDTH 16
+
+#define R_TIMER_PRESCALE (IO_TYPECAST_UWORD 0xb00000f0)
+#define R_TIMER_PRESCALE__tim_presc__BITNR 0
+#define R_TIMER_PRESCALE__tim_presc__WIDTH 16
+
+#define R_PRESCALE_STATUS (IO_TYPECAST_RO_UDWORD 0xb00000f0)
+#define R_PRESCALE_STATUS__ser_status__BITNR 16
+#define R_PRESCALE_STATUS__ser_status__WIDTH 16
+#define R_PRESCALE_STATUS__tim_status__BITNR 0
+#define R_PRESCALE_STATUS__tim_status__WIDTH 16
+
+#define R_SER_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f2)
+#define R_SER_PRESC_STATUS__ser_status__BITNR 0
+#define R_SER_PRESC_STATUS__ser_status__WIDTH 16
+
+#define R_TIM_PRESC_STATUS (IO_TYPECAST_RO_UWORD 0xb00000f0)
+#define R_TIM_PRESC_STATUS__tim_status__BITNR 0
+#define R_TIM_PRESC_STATUS__tim_status__WIDTH 16
+
+#define R_SYNC_SERIAL_PRESCALE (IO_TYPECAST_UDWORD 0xb00000f4)
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__BITNR 23
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__WIDTH 1
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__codec 0
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u3__baudrate 1
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__BITNR 22
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__WIDTH 1
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__external 0
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u3__internal 1
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__BITNR 21
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__WIDTH 1
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__codec 0
+#define R_SYNC_SERIAL_PRESCALE__clk_sel_u1__baudrate 1
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__BITNR 20
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__WIDTH 1
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__external 0
+#define R_SYNC_SERIAL_PRESCALE__word_stb_sel_u1__internal 1
+#define R_SYNC_SERIAL_PRESCALE__prescaler__BITNR 16
+#define R_SYNC_SERIAL_PRESCALE__prescaler__WIDTH 3
+#define R_SYNC_SERIAL_PRESCALE__prescaler__div1 0
+#define R_SYNC_SERIAL_PRESCALE__prescaler__div2 1
+#define R_SYNC_SERIAL_PRESCALE__prescaler__div4 2
+#define R_SYNC_SERIAL_PRESCALE__prescaler__div8 3
+#define R_SYNC_SERIAL_PRESCALE__prescaler__div16 4
+#define R_SYNC_SERIAL_PRESCALE__prescaler__div32 5
+#define R_SYNC_SERIAL_PRESCALE__prescaler__div64 6
+#define R_SYNC_SERIAL_PRESCALE__prescaler__div128 7
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__BITNR 15
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__WIDTH 1
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__normal 0
+#define R_SYNC_SERIAL_PRESCALE__warp_mode__enabled 1
+#define R_SYNC_SERIAL_PRESCALE__frame_rate__BITNR 11
+#define R_SYNC_SERIAL_PRESCALE__frame_rate__WIDTH 4
+#define R_SYNC_SERIAL_PRESCALE__word_rate__BITNR 0
+#define R_SYNC_SERIAL_PRESCALE__word_rate__WIDTH 10
+
+/*
+!* Shared RAM interface registers
+!*/
+
+#define R_SHARED_RAM_CONFIG (IO_TYPECAST_UDWORD 0xb0000040)
+#define R_SHARED_RAM_CONFIG__width__BITNR 3
+#define R_SHARED_RAM_CONFIG__width__WIDTH 1
+#define R_SHARED_RAM_CONFIG__width__byte 0
+#define R_SHARED_RAM_CONFIG__width__word 1
+#define R_SHARED_RAM_CONFIG__enable__BITNR 2
+#define R_SHARED_RAM_CONFIG__enable__WIDTH 1
+#define R_SHARED_RAM_CONFIG__enable__yes 1
+#define R_SHARED_RAM_CONFIG__enable__no 0
+#define R_SHARED_RAM_CONFIG__pint__BITNR 1
+#define R_SHARED_RAM_CONFIG__pint__WIDTH 1
+#define R_SHARED_RAM_CONFIG__pint__int 1
+#define R_SHARED_RAM_CONFIG__pint__nop 0
+#define R_SHARED_RAM_CONFIG__clri__BITNR 0
+#define R_SHARED_RAM_CONFIG__clri__WIDTH 1
+#define R_SHARED_RAM_CONFIG__clri__clr 1
+#define R_SHARED_RAM_CONFIG__clri__nop 0
+
+#define R_SHARED_RAM_ADDR (IO_TYPECAST_UDWORD 0xb0000044)
+#define R_SHARED_RAM_ADDR__base_addr__BITNR 8
+#define R_SHARED_RAM_ADDR__base_addr__WIDTH 22
+
+/*
+!* General config registers
+!*/
+
+#define R_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb000002c)
+#define R_GEN_CONFIG__par_w__BITNR 31
+#define R_GEN_CONFIG__par_w__WIDTH 1
+#define R_GEN_CONFIG__par_w__select 1
+#define R_GEN_CONFIG__par_w__disable 0
+#define R_GEN_CONFIG__usb2__BITNR 30
+#define R_GEN_CONFIG__usb2__WIDTH 1
+#define R_GEN_CONFIG__usb2__select 1
+#define R_GEN_CONFIG__usb2__disable 0
+#define R_GEN_CONFIG__usb1__BITNR 29
+#define R_GEN_CONFIG__usb1__WIDTH 1
+#define R_GEN_CONFIG__usb1__select 1
+#define R_GEN_CONFIG__usb1__disable 0
+#define R_GEN_CONFIG__g24dir__BITNR 27
+#define R_GEN_CONFIG__g24dir__WIDTH 1
+#define R_GEN_CONFIG__g24dir__in 0
+#define R_GEN_CONFIG__g24dir__out 1
+#define R_GEN_CONFIG__g16_23dir__BITNR 26
+#define R_GEN_CONFIG__g16_23dir__WIDTH 1
+#define R_GEN_CONFIG__g16_23dir__in 0
+#define R_GEN_CONFIG__g16_23dir__out 1
+#define R_GEN_CONFIG__g16_20dir__BITNR 26
+#define R_GEN_CONFIG__g16_20dir__WIDTH 1
+#define R_GEN_CONFIG__g16_20dir__in 0
+#define R_GEN_CONFIG__g16_20dir__out 1
+#define R_GEN_CONFIG__g8_15dir__BITNR 25
+#define R_GEN_CONFIG__g8_15dir__WIDTH 1
+#define R_GEN_CONFIG__g8_15dir__in 0
+#define R_GEN_CONFIG__g8_15dir__out 1
+#define R_GEN_CONFIG__g0dir__BITNR 24
+#define R_GEN_CONFIG__g0dir__WIDTH 1
+#define R_GEN_CONFIG__g0dir__in 0
+#define R_GEN_CONFIG__g0dir__out 1
+#define R_GEN_CONFIG__dma9__BITNR 23
+#define R_GEN_CONFIG__dma9__WIDTH 1
+#define R_GEN_CONFIG__dma9__usb 0
+#define R_GEN_CONFIG__dma9__serial1 1
+#define R_GEN_CONFIG__dma8__BITNR 22
+#define R_GEN_CONFIG__dma8__WIDTH 1
+#define R_GEN_CONFIG__dma8__usb 0
+#define R_GEN_CONFIG__dma8__serial1 1
+#define R_GEN_CONFIG__dma7__BITNR 20
+#define R_GEN_CONFIG__dma7__WIDTH 2
+#define R_GEN_CONFIG__dma7__unused 0
+#define R_GEN_CONFIG__dma7__serial0 1
+#define R_GEN_CONFIG__dma7__extdma1 2
+#define R_GEN_CONFIG__dma7__intdma6 3
+#define R_GEN_CONFIG__dma6__BITNR 18
+#define R_GEN_CONFIG__dma6__WIDTH 2
+#define R_GEN_CONFIG__dma6__unused 0
+#define R_GEN_CONFIG__dma6__serial0 1
+#define R_GEN_CONFIG__dma6__extdma1 2
+#define R_GEN_CONFIG__dma6__intdma7 3
+#define R_GEN_CONFIG__dma5__BITNR 16
+#define R_GEN_CONFIG__dma5__WIDTH 2
+#define R_GEN_CONFIG__dma5__par1 0
+#define R_GEN_CONFIG__dma5__scsi1 1
+#define R_GEN_CONFIG__dma5__serial3 2
+#define R_GEN_CONFIG__dma5__extdma0 3
+#define R_GEN_CONFIG__dma4__BITNR 14
+#define R_GEN_CONFIG__dma4__WIDTH 2
+#define R_GEN_CONFIG__dma4__par1 0
+#define R_GEN_CONFIG__dma4__scsi1 1
+#define R_GEN_CONFIG__dma4__serial3 2
+#define R_GEN_CONFIG__dma4__extdma0 3
+#define R_GEN_CONFIG__dma3__BITNR 12
+#define R_GEN_CONFIG__dma3__WIDTH 2
+#define R_GEN_CONFIG__dma3__par0 0
+#define R_GEN_CONFIG__dma3__scsi0 1
+#define R_GEN_CONFIG__dma3__serial2 2
+#define R_GEN_CONFIG__dma3__ata 3
+#define R_GEN_CONFIG__dma2__BITNR 10
+#define R_GEN_CONFIG__dma2__WIDTH 2
+#define R_GEN_CONFIG__dma2__par0 0
+#define R_GEN_CONFIG__dma2__scsi0 1
+#define R_GEN_CONFIG__dma2__serial2 2
+#define R_GEN_CONFIG__dma2__ata 3
+#define R_GEN_CONFIG__mio_w__BITNR 9
+#define R_GEN_CONFIG__mio_w__WIDTH 1
+#define R_GEN_CONFIG__mio_w__select 1
+#define R_GEN_CONFIG__mio_w__disable 0
+#define R_GEN_CONFIG__ser3__BITNR 8
+#define R_GEN_CONFIG__ser3__WIDTH 1
+#define R_GEN_CONFIG__ser3__select 1
+#define R_GEN_CONFIG__ser3__disable 0
+#define R_GEN_CONFIG__par1__BITNR 7
+#define R_GEN_CONFIG__par1__WIDTH 1
+#define R_GEN_CONFIG__par1__select 1
+#define R_GEN_CONFIG__par1__disable 0
+#define R_GEN_CONFIG__scsi0w__BITNR 6
+#define R_GEN_CONFIG__scsi0w__WIDTH 1
+#define R_GEN_CONFIG__scsi0w__select 1
+#define R_GEN_CONFIG__scsi0w__disable 0
+#define R_GEN_CONFIG__scsi1__BITNR 5
+#define R_GEN_CONFIG__scsi1__WIDTH 1
+#define R_GEN_CONFIG__scsi1__select 1
+#define R_GEN_CONFIG__scsi1__disable 0
+#define R_GEN_CONFIG__mio__BITNR 4
+#define R_GEN_CONFIG__mio__WIDTH 1
+#define R_GEN_CONFIG__mio__select 1
+#define R_GEN_CONFIG__mio__disable 0
+#define R_GEN_CONFIG__ser2__BITNR 3
+#define R_GEN_CONFIG__ser2__WIDTH 1
+#define R_GEN_CONFIG__ser2__select 1
+#define R_GEN_CONFIG__ser2__disable 0
+#define R_GEN_CONFIG__par0__BITNR 2
+#define R_GEN_CONFIG__par0__WIDTH 1
+#define R_GEN_CONFIG__par0__select 1
+#define R_GEN_CONFIG__par0__disable 0
+#define R_GEN_CONFIG__ata__BITNR 1
+#define R_GEN_CONFIG__ata__WIDTH 1
+#define R_GEN_CONFIG__ata__select 1
+#define R_GEN_CONFIG__ata__disable 0
+#define R_GEN_CONFIG__scsi0__BITNR 0
+#define R_GEN_CONFIG__scsi0__WIDTH 1
+#define R_GEN_CONFIG__scsi0__select 1
+#define R_GEN_CONFIG__scsi0__disable 0
+
+#define R_GEN_CONFIG_II (IO_TYPECAST_UDWORD 0xb0000034)
+#define R_GEN_CONFIG_II__sermode3__BITNR 6
+#define R_GEN_CONFIG_II__sermode3__WIDTH 1
+#define R_GEN_CONFIG_II__sermode3__async 0
+#define R_GEN_CONFIG_II__sermode3__sync 1
+#define R_GEN_CONFIG_II__sermode1__BITNR 4
+#define R_GEN_CONFIG_II__sermode1__WIDTH 1
+#define R_GEN_CONFIG_II__sermode1__async 0
+#define R_GEN_CONFIG_II__sermode1__sync 1
+#define R_GEN_CONFIG_II__ext_clk__BITNR 2
+#define R_GEN_CONFIG_II__ext_clk__WIDTH 1
+#define R_GEN_CONFIG_II__ext_clk__select 1
+#define R_GEN_CONFIG_II__ext_clk__disable 0
+#define R_GEN_CONFIG_II__ser3__BITNR 1
+#define R_GEN_CONFIG_II__ser3__WIDTH 1
+#define R_GEN_CONFIG_II__ser3__select 1
+#define R_GEN_CONFIG_II__ser3__disable 0
+#define R_GEN_CONFIG_II__ser2__BITNR 0
+#define R_GEN_CONFIG_II__ser2__WIDTH 1
+#define R_GEN_CONFIG_II__ser2__select 1
+#define R_GEN_CONFIG_II__ser2__disable 0
+
+#define R_PORT_G_DATA (IO_TYPECAST_UDWORD 0xb0000028)
+#define R_PORT_G_DATA__data__BITNR 0
+#define R_PORT_G_DATA__data__WIDTH 32
+
+/*
+!* General port configuration registers
+!*/
+
+#define R_PORT_PA_SET (IO_TYPECAST_UDWORD 0xb0000030)
+#define R_PORT_PA_SET__dir7__BITNR 15
+#define R_PORT_PA_SET__dir7__WIDTH 1
+#define R_PORT_PA_SET__dir7__input 0
+#define R_PORT_PA_SET__dir7__output 1
+#define R_PORT_PA_SET__dir6__BITNR 14
+#define R_PORT_PA_SET__dir6__WIDTH 1
+#define R_PORT_PA_SET__dir6__input 0
+#define R_PORT_PA_SET__dir6__output 1
+#define R_PORT_PA_SET__dir5__BITNR 13
+#define R_PORT_PA_SET__dir5__WIDTH 1
+#define R_PORT_PA_SET__dir5__input 0
+#define R_PORT_PA_SET__dir5__output 1
+#define R_PORT_PA_SET__dir4__BITNR 12
+#define R_PORT_PA_SET__dir4__WIDTH 1
+#define R_PORT_PA_SET__dir4__input 0
+#define R_PORT_PA_SET__dir4__output 1
+#define R_PORT_PA_SET__dir3__BITNR 11
+#define R_PORT_PA_SET__dir3__WIDTH 1
+#define R_PORT_PA_SET__dir3__input 0
+#define R_PORT_PA_SET__dir3__output 1
+#define R_PORT_PA_SET__dir2__BITNR 10
+#define R_PORT_PA_SET__dir2__WIDTH 1
+#define R_PORT_PA_SET__dir2__input 0
+#define R_PORT_PA_SET__dir2__output 1
+#define R_PORT_PA_SET__dir1__BITNR 9
+#define R_PORT_PA_SET__dir1__WIDTH 1
+#define R_PORT_PA_SET__dir1__input 0
+#define R_PORT_PA_SET__dir1__output 1
+#define R_PORT_PA_SET__dir0__BITNR 8
+#define R_PORT_PA_SET__dir0__WIDTH 1
+#define R_PORT_PA_SET__dir0__input 0
+#define R_PORT_PA_SET__dir0__output 1
+#define R_PORT_PA_SET__data_out__BITNR 0
+#define R_PORT_PA_SET__data_out__WIDTH 8
+
+#define R_PORT_PA_DATA (IO_TYPECAST_BYTE 0xb0000030)
+#define R_PORT_PA_DATA__data_out__BITNR 0
+#define R_PORT_PA_DATA__data_out__WIDTH 8
+
+#define R_PORT_PA_DIR (IO_TYPECAST_BYTE 0xb0000031)
+#define R_PORT_PA_DIR__dir7__BITNR 7
+#define R_PORT_PA_DIR__dir7__WIDTH 1
+#define R_PORT_PA_DIR__dir7__input 0
+#define R_PORT_PA_DIR__dir7__output 1
+#define R_PORT_PA_DIR__dir6__BITNR 6
+#define R_PORT_PA_DIR__dir6__WIDTH 1
+#define R_PORT_PA_DIR__dir6__input 0
+#define R_PORT_PA_DIR__dir6__output 1
+#define R_PORT_PA_DIR__dir5__BITNR 5
+#define R_PORT_PA_DIR__dir5__WIDTH 1
+#define R_PORT_PA_DIR__dir5__input 0
+#define R_PORT_PA_DIR__dir5__output 1
+#define R_PORT_PA_DIR__dir4__BITNR 4
+#define R_PORT_PA_DIR__dir4__WIDTH 1
+#define R_PORT_PA_DIR__dir4__input 0
+#define R_PORT_PA_DIR__dir4__output 1
+#define R_PORT_PA_DIR__dir3__BITNR 3
+#define R_PORT_PA_DIR__dir3__WIDTH 1
+#define R_PORT_PA_DIR__dir3__input 0
+#define R_PORT_PA_DIR__dir3__output 1
+#define R_PORT_PA_DIR__dir2__BITNR 2
+#define R_PORT_PA_DIR__dir2__WIDTH 1
+#define R_PORT_PA_DIR__dir2__input 0
+#define R_PORT_PA_DIR__dir2__output 1
+#define R_PORT_PA_DIR__dir1__BITNR 1
+#define R_PORT_PA_DIR__dir1__WIDTH 1
+#define R_PORT_PA_DIR__dir1__input 0
+#define R_PORT_PA_DIR__dir1__output 1
+#define R_PORT_PA_DIR__dir0__BITNR 0
+#define R_PORT_PA_DIR__dir0__WIDTH 1
+#define R_PORT_PA_DIR__dir0__input 0
+#define R_PORT_PA_DIR__dir0__output 1
+
+#define R_PORT_PA_READ (IO_TYPECAST_RO_UDWORD 0xb0000030)
+#define R_PORT_PA_READ__data_in__BITNR 0
+#define R_PORT_PA_READ__data_in__WIDTH 8
+
+#define R_PORT_PB_SET (IO_TYPECAST_UDWORD 0xb0000038)
+#define R_PORT_PB_SET__syncser3__BITNR 29
+#define R_PORT_PB_SET__syncser3__WIDTH 1
+#define R_PORT_PB_SET__syncser3__port_cs 0
+#define R_PORT_PB_SET__syncser3__ss3extra 1
+#define R_PORT_PB_SET__syncser1__BITNR 28
+#define R_PORT_PB_SET__syncser1__WIDTH 1
+#define R_PORT_PB_SET__syncser1__port_cs 0
+#define R_PORT_PB_SET__syncser1__ss1extra 1
+#define R_PORT_PB_SET__i2c_en__BITNR 27
+#define R_PORT_PB_SET__i2c_en__WIDTH 1
+#define R_PORT_PB_SET__i2c_en__off 0
+#define R_PORT_PB_SET__i2c_en__on 1
+#define R_PORT_PB_SET__i2c_d__BITNR 26
+#define R_PORT_PB_SET__i2c_d__WIDTH 1
+#define R_PORT_PB_SET__i2c_clk__BITNR 25
+#define R_PORT_PB_SET__i2c_clk__WIDTH 1
+#define R_PORT_PB_SET__i2c_oe___BITNR 24
+#define R_PORT_PB_SET__i2c_oe___WIDTH 1
+#define R_PORT_PB_SET__i2c_oe___enable 0
+#define R_PORT_PB_SET__i2c_oe___disable 1
+#define R_PORT_PB_SET__cs7__BITNR 23
+#define R_PORT_PB_SET__cs7__WIDTH 1
+#define R_PORT_PB_SET__cs7__port 0
+#define R_PORT_PB_SET__cs7__cs 1
+#define R_PORT_PB_SET__cs6__BITNR 22
+#define R_PORT_PB_SET__cs6__WIDTH 1
+#define R_PORT_PB_SET__cs6__port 0
+#define R_PORT_PB_SET__cs6__cs 1
+#define R_PORT_PB_SET__cs5__BITNR 21
+#define R_PORT_PB_SET__cs5__WIDTH 1
+#define R_PORT_PB_SET__cs5__port 0
+#define R_PORT_PB_SET__cs5__cs 1
+#define R_PORT_PB_SET__cs4__BITNR 20
+#define R_PORT_PB_SET__cs4__WIDTH 1
+#define R_PORT_PB_SET__cs4__port 0
+#define R_PORT_PB_SET__cs4__cs 1
+#define R_PORT_PB_SET__cs3__BITNR 19
+#define R_PORT_PB_SET__cs3__WIDTH 1
+#define R_PORT_PB_SET__cs3__port 0
+#define R_PORT_PB_SET__cs3__cs 1
+#define R_PORT_PB_SET__cs2__BITNR 18
+#define R_PORT_PB_SET__cs2__WIDTH 1
+#define R_PORT_PB_SET__cs2__port 0
+#define R_PORT_PB_SET__cs2__cs 1
+#define R_PORT_PB_SET__scsi1__BITNR 17
+#define R_PORT_PB_SET__scsi1__WIDTH 1
+#define R_PORT_PB_SET__scsi1__port_cs 0
+#define R_PORT_PB_SET__scsi1__enph 1
+#define R_PORT_PB_SET__scsi0__BITNR 16
+#define R_PORT_PB_SET__scsi0__WIDTH 1
+#define R_PORT_PB_SET__scsi0__port_cs 0
+#define R_PORT_PB_SET__scsi0__enph 1
+#define R_PORT_PB_SET__dir7__BITNR 15
+#define R_PORT_PB_SET__dir7__WIDTH 1
+#define R_PORT_PB_SET__dir7__input 0
+#define R_PORT_PB_SET__dir7__output 1
+#define R_PORT_PB_SET__dir6__BITNR 14
+#define R_PORT_PB_SET__dir6__WIDTH 1
+#define R_PORT_PB_SET__dir6__input 0
+#define R_PORT_PB_SET__dir6__output 1
+#define R_PORT_PB_SET__dir5__BITNR 13
+#define R_PORT_PB_SET__dir5__WIDTH 1
+#define R_PORT_PB_SET__dir5__input 0
+#define R_PORT_PB_SET__dir5__output 1
+#define R_PORT_PB_SET__dir4__BITNR 12
+#define R_PORT_PB_SET__dir4__WIDTH 1
+#define R_PORT_PB_SET__dir4__input 0
+#define R_PORT_PB_SET__dir4__output 1
+#define R_PORT_PB_SET__dir3__BITNR 11
+#define R_PORT_PB_SET__dir3__WIDTH 1
+#define R_PORT_PB_SET__dir3__input 0
+#define R_PORT_PB_SET__dir3__output 1
+#define R_PORT_PB_SET__dir2__BITNR 10
+#define R_PORT_PB_SET__dir2__WIDTH 1
+#define R_PORT_PB_SET__dir2__input 0
+#define R_PORT_PB_SET__dir2__output 1
+#define R_PORT_PB_SET__dir1__BITNR 9
+#define R_PORT_PB_SET__dir1__WIDTH 1
+#define R_PORT_PB_SET__dir1__input 0
+#define R_PORT_PB_SET__dir1__output 1
+#define R_PORT_PB_SET__dir0__BITNR 8
+#define R_PORT_PB_SET__dir0__WIDTH 1
+#define R_PORT_PB_SET__dir0__input 0
+#define R_PORT_PB_SET__dir0__output 1
+#define R_PORT_PB_SET__data_out__BITNR 0
+#define R_PORT_PB_SET__data_out__WIDTH 8
+
+#define R_PORT_PB_DATA (IO_TYPECAST_BYTE 0xb0000038)
+#define R_PORT_PB_DATA__data_out__BITNR 0
+#define R_PORT_PB_DATA__data_out__WIDTH 8
+
+#define R_PORT_PB_DIR (IO_TYPECAST_BYTE 0xb0000039)
+#define R_PORT_PB_DIR__dir7__BITNR 7
+#define R_PORT_PB_DIR__dir7__WIDTH 1
+#define R_PORT_PB_DIR__dir7__input 0
+#define R_PORT_PB_DIR__dir7__output 1
+#define R_PORT_PB_DIR__dir6__BITNR 6
+#define R_PORT_PB_DIR__dir6__WIDTH 1
+#define R_PORT_PB_DIR__dir6__input 0
+#define R_PORT_PB_DIR__dir6__output 1
+#define R_PORT_PB_DIR__dir5__BITNR 5
+#define R_PORT_PB_DIR__dir5__WIDTH 1
+#define R_PORT_PB_DIR__dir5__input 0
+#define R_PORT_PB_DIR__dir5__output 1
+#define R_PORT_PB_DIR__dir4__BITNR 4
+#define R_PORT_PB_DIR__dir4__WIDTH 1
+#define R_PORT_PB_DIR__dir4__input 0
+#define R_PORT_PB_DIR__dir4__output 1
+#define R_PORT_PB_DIR__dir3__BITNR 3
+#define R_PORT_PB_DIR__dir3__WIDTH 1
+#define R_PORT_PB_DIR__dir3__input 0
+#define R_PORT_PB_DIR__dir3__output 1
+#define R_PORT_PB_DIR__dir2__BITNR 2
+#define R_PORT_PB_DIR__dir2__WIDTH 1
+#define R_PORT_PB_DIR__dir2__input 0
+#define R_PORT_PB_DIR__dir2__output 1
+#define R_PORT_PB_DIR__dir1__BITNR 1
+#define R_PORT_PB_DIR__dir1__WIDTH 1
+#define R_PORT_PB_DIR__dir1__input 0
+#define R_PORT_PB_DIR__dir1__output 1
+#define R_PORT_PB_DIR__dir0__BITNR 0
+#define R_PORT_PB_DIR__dir0__WIDTH 1
+#define R_PORT_PB_DIR__dir0__input 0
+#define R_PORT_PB_DIR__dir0__output 1
+
+#define R_PORT_PB_CONFIG (IO_TYPECAST_BYTE 0xb000003a)
+#define R_PORT_PB_CONFIG__cs7__BITNR 7
+#define R_PORT_PB_CONFIG__cs7__WIDTH 1
+#define R_PORT_PB_CONFIG__cs7__port 0
+#define R_PORT_PB_CONFIG__cs7__cs 1
+#define R_PORT_PB_CONFIG__cs6__BITNR 6
+#define R_PORT_PB_CONFIG__cs6__WIDTH 1
+#define R_PORT_PB_CONFIG__cs6__port 0
+#define R_PORT_PB_CONFIG__cs6__cs 1
+#define R_PORT_PB_CONFIG__cs5__BITNR 5
+#define R_PORT_PB_CONFIG__cs5__WIDTH 1
+#define R_PORT_PB_CONFIG__cs5__port 0
+#define R_PORT_PB_CONFIG__cs5__cs 1
+#define R_PORT_PB_CONFIG__cs4__BITNR 4
+#define R_PORT_PB_CONFIG__cs4__WIDTH 1
+#define R_PORT_PB_CONFIG__cs4__port 0
+#define R_PORT_PB_CONFIG__cs4__cs 1
+#define R_PORT_PB_CONFIG__cs3__BITNR 3
+#define R_PORT_PB_CONFIG__cs3__WIDTH 1
+#define R_PORT_PB_CONFIG__cs3__port 0
+#define R_PORT_PB_CONFIG__cs3__cs 1
+#define R_PORT_PB_CONFIG__cs2__BITNR 2
+#define R_PORT_PB_CONFIG__cs2__WIDTH 1
+#define R_PORT_PB_CONFIG__cs2__port 0
+#define R_PORT_PB_CONFIG__cs2__cs 1
+#define R_PORT_PB_CONFIG__scsi1__BITNR 1
+#define R_PORT_PB_CONFIG__scsi1__WIDTH 1
+#define R_PORT_PB_CONFIG__scsi1__port_cs 0
+#define R_PORT_PB_CONFIG__scsi1__enph 1
+#define R_PORT_PB_CONFIG__scsi0__BITNR 0
+#define R_PORT_PB_CONFIG__scsi0__WIDTH 1
+#define R_PORT_PB_CONFIG__scsi0__port_cs 0
+#define R_PORT_PB_CONFIG__scsi0__enph 1
+
+#define R_PORT_PB_I2C (IO_TYPECAST_BYTE 0xb000003b)
+#define R_PORT_PB_I2C__syncser3__BITNR 5
+#define R_PORT_PB_I2C__syncser3__WIDTH 1
+#define R_PORT_PB_I2C__syncser3__port_cs 0
+#define R_PORT_PB_I2C__syncser3__ss3extra 1
+#define R_PORT_PB_I2C__syncser1__BITNR 4
+#define R_PORT_PB_I2C__syncser1__WIDTH 1
+#define R_PORT_PB_I2C__syncser1__port_cs 0
+#define R_PORT_PB_I2C__syncser1__ss1extra 1
+#define R_PORT_PB_I2C__i2c_en__BITNR 3
+#define R_PORT_PB_I2C__i2c_en__WIDTH 1
+#define R_PORT_PB_I2C__i2c_en__off 0
+#define R_PORT_PB_I2C__i2c_en__on 1
+#define R_PORT_PB_I2C__i2c_d__BITNR 2
+#define R_PORT_PB_I2C__i2c_d__WIDTH 1
+#define R_PORT_PB_I2C__i2c_clk__BITNR 1
+#define R_PORT_PB_I2C__i2c_clk__WIDTH 1
+#define R_PORT_PB_I2C__i2c_oe___BITNR 0
+#define R_PORT_PB_I2C__i2c_oe___WIDTH 1
+#define R_PORT_PB_I2C__i2c_oe___enable 0
+#define R_PORT_PB_I2C__i2c_oe___disable 1
+
+#define R_PORT_PB_READ (IO_TYPECAST_RO_UDWORD 0xb0000038)
+#define R_PORT_PB_READ__data_in__BITNR 0
+#define R_PORT_PB_READ__data_in__WIDTH 8
+
+/*
+!* Serial port registers
+!*/
+
+#define R_SERIAL0_CTRL (IO_TYPECAST_UDWORD 0xb0000060)
+#define R_SERIAL0_CTRL__tr_baud__BITNR 28
+#define R_SERIAL0_CTRL__tr_baud__WIDTH 4
+#define R_SERIAL0_CTRL__tr_baud__c300Hz 0
+#define R_SERIAL0_CTRL__tr_baud__c600Hz 1
+#define R_SERIAL0_CTRL__tr_baud__c1200Hz 2
+#define R_SERIAL0_CTRL__tr_baud__c2400Hz 3
+#define R_SERIAL0_CTRL__tr_baud__c4800Hz 4
+#define R_SERIAL0_CTRL__tr_baud__c9600Hz 5
+#define R_SERIAL0_CTRL__tr_baud__c19k2Hz 6
+#define R_SERIAL0_CTRL__tr_baud__c38k4Hz 7
+#define R_SERIAL0_CTRL__tr_baud__c57k6Hz 8
+#define R_SERIAL0_CTRL__tr_baud__c115k2Hz 9
+#define R_SERIAL0_CTRL__tr_baud__c230k4Hz 10
+#define R_SERIAL0_CTRL__tr_baud__c460k8Hz 11
+#define R_SERIAL0_CTRL__tr_baud__c921k6Hz 12
+#define R_SERIAL0_CTRL__tr_baud__c1843k2Hz 13
+#define R_SERIAL0_CTRL__tr_baud__c6250kHz 14
+#define R_SERIAL0_CTRL__tr_baud__reserved 15
+#define R_SERIAL0_CTRL__rec_baud__BITNR 24
+#define R_SERIAL0_CTRL__rec_baud__WIDTH 4
+#define R_SERIAL0_CTRL__rec_baud__c300Hz 0
+#define R_SERIAL0_CTRL__rec_baud__c600Hz 1
+#define R_SERIAL0_CTRL__rec_baud__c1200Hz 2
+#define R_SERIAL0_CTRL__rec_baud__c2400Hz 3
+#define R_SERIAL0_CTRL__rec_baud__c4800Hz 4
+#define R_SERIAL0_CTRL__rec_baud__c9600Hz 5
+#define R_SERIAL0_CTRL__rec_baud__c19k2Hz 6
+#define R_SERIAL0_CTRL__rec_baud__c38k4Hz 7
+#define R_SERIAL0_CTRL__rec_baud__c57k6Hz 8
+#define R_SERIAL0_CTRL__rec_baud__c115k2Hz 9
+#define R_SERIAL0_CTRL__rec_baud__c230k4Hz 10
+#define R_SERIAL0_CTRL__rec_baud__c460k8Hz 11
+#define R_SERIAL0_CTRL__rec_baud__c921k6Hz 12
+#define R_SERIAL0_CTRL__rec_baud__c1843k2Hz 13
+#define R_SERIAL0_CTRL__rec_baud__c6250kHz 14
+#define R_SERIAL0_CTRL__rec_baud__reserved 15
+#define R_SERIAL0_CTRL__dma_err__BITNR 23
+#define R_SERIAL0_CTRL__dma_err__WIDTH 1
+#define R_SERIAL0_CTRL__dma_err__stop 0
+#define R_SERIAL0_CTRL__dma_err__ignore 1
+#define R_SERIAL0_CTRL__rec_enable__BITNR 22
+#define R_SERIAL0_CTRL__rec_enable__WIDTH 1
+#define R_SERIAL0_CTRL__rec_enable__disable 0
+#define R_SERIAL0_CTRL__rec_enable__enable 1
+#define R_SERIAL0_CTRL__rts___BITNR 21
+#define R_SERIAL0_CTRL__rts___WIDTH 1
+#define R_SERIAL0_CTRL__rts___active 0
+#define R_SERIAL0_CTRL__rts___inactive 1
+#define R_SERIAL0_CTRL__sampling__BITNR 20
+#define R_SERIAL0_CTRL__sampling__WIDTH 1
+#define R_SERIAL0_CTRL__sampling__middle 0
+#define R_SERIAL0_CTRL__sampling__majority 1
+#define R_SERIAL0_CTRL__rec_stick_par__BITNR 19
+#define R_SERIAL0_CTRL__rec_stick_par__WIDTH 1
+#define R_SERIAL0_CTRL__rec_stick_par__normal 0
+#define R_SERIAL0_CTRL__rec_stick_par__stick 1
+#define R_SERIAL0_CTRL__rec_par__BITNR 18
+#define R_SERIAL0_CTRL__rec_par__WIDTH 1
+#define R_SERIAL0_CTRL__rec_par__even 0
+#define R_SERIAL0_CTRL__rec_par__odd 1
+#define R_SERIAL0_CTRL__rec_par_en__BITNR 17
+#define R_SERIAL0_CTRL__rec_par_en__WIDTH 1
+#define R_SERIAL0_CTRL__rec_par_en__disable 0
+#define R_SERIAL0_CTRL__rec_par_en__enable 1
+#define R_SERIAL0_CTRL__rec_bitnr__BITNR 16
+#define R_SERIAL0_CTRL__rec_bitnr__WIDTH 1
+#define R_SERIAL0_CTRL__rec_bitnr__rec_8bit 0
+#define R_SERIAL0_CTRL__rec_bitnr__rec_7bit 1
+#define R_SERIAL0_CTRL__txd__BITNR 15
+#define R_SERIAL0_CTRL__txd__WIDTH 1
+#define R_SERIAL0_CTRL__tr_enable__BITNR 14
+#define R_SERIAL0_CTRL__tr_enable__WIDTH 1
+#define R_SERIAL0_CTRL__tr_enable__disable 0
+#define R_SERIAL0_CTRL__tr_enable__enable 1
+#define R_SERIAL0_CTRL__auto_cts__BITNR 13
+#define R_SERIAL0_CTRL__auto_cts__WIDTH 1
+#define R_SERIAL0_CTRL__auto_cts__disabled 0
+#define R_SERIAL0_CTRL__auto_cts__active 1
+#define R_SERIAL0_CTRL__stop_bits__BITNR 12
+#define R_SERIAL0_CTRL__stop_bits__WIDTH 1
+#define R_SERIAL0_CTRL__stop_bits__one_bit 0
+#define R_SERIAL0_CTRL__stop_bits__two_bits 1
+#define R_SERIAL0_CTRL__tr_stick_par__BITNR 11
+#define R_SERIAL0_CTRL__tr_stick_par__WIDTH 1
+#define R_SERIAL0_CTRL__tr_stick_par__normal 0
+#define R_SERIAL0_CTRL__tr_stick_par__stick 1
+#define R_SERIAL0_CTRL__tr_par__BITNR 10
+#define R_SERIAL0_CTRL__tr_par__WIDTH 1
+#define R_SERIAL0_CTRL__tr_par__even 0
+#define R_SERIAL0_CTRL__tr_par__odd 1
+#define R_SERIAL0_CTRL__tr_par_en__BITNR 9
+#define R_SERIAL0_CTRL__tr_par_en__WIDTH 1
+#define R_SERIAL0_CTRL__tr_par_en__disable 0
+#define R_SERIAL0_CTRL__tr_par_en__enable 1
+#define R_SERIAL0_CTRL__tr_bitnr__BITNR 8
+#define R_SERIAL0_CTRL__tr_bitnr__WIDTH 1
+#define R_SERIAL0_CTRL__tr_bitnr__tr_8bit 0
+#define R_SERIAL0_CTRL__tr_bitnr__tr_7bit 1
+#define R_SERIAL0_CTRL__data_out__BITNR 0
+#define R_SERIAL0_CTRL__data_out__WIDTH 8
+
+#define R_SERIAL0_BAUD (IO_TYPECAST_BYTE 0xb0000063)
+#define R_SERIAL0_BAUD__tr_baud__BITNR 4
+#define R_SERIAL0_BAUD__tr_baud__WIDTH 4
+#define R_SERIAL0_BAUD__tr_baud__c300Hz 0
+#define R_SERIAL0_BAUD__tr_baud__c600Hz 1
+#define R_SERIAL0_BAUD__tr_baud__c1200Hz 2
+#define R_SERIAL0_BAUD__tr_baud__c2400Hz 3
+#define R_SERIAL0_BAUD__tr_baud__c4800Hz 4
+#define R_SERIAL0_BAUD__tr_baud__c9600Hz 5
+#define R_SERIAL0_BAUD__tr_baud__c19k2Hz 6
+#define R_SERIAL0_BAUD__tr_baud__c38k4Hz 7
+#define R_SERIAL0_BAUD__tr_baud__c57k6Hz 8
+#define R_SERIAL0_BAUD__tr_baud__c115k2Hz 9
+#define R_SERIAL0_BAUD__tr_baud__c230k4Hz 10
+#define R_SERIAL0_BAUD__tr_baud__c460k8Hz 11
+#define R_SERIAL0_BAUD__tr_baud__c921k6Hz 12
+#define R_SERIAL0_BAUD__tr_baud__c1843k2Hz 13
+#define R_SERIAL0_BAUD__tr_baud__c6250kHz 14
+#define R_SERIAL0_BAUD__tr_baud__reserved 15
+#define R_SERIAL0_BAUD__rec_baud__BITNR 0
+#define R_SERIAL0_BAUD__rec_baud__WIDTH 4
+#define R_SERIAL0_BAUD__rec_baud__c300Hz 0
+#define R_SERIAL0_BAUD__rec_baud__c600Hz 1
+#define R_SERIAL0_BAUD__rec_baud__c1200Hz 2
+#define R_SERIAL0_BAUD__rec_baud__c2400Hz 3
+#define R_SERIAL0_BAUD__rec_baud__c4800Hz 4
+#define R_SERIAL0_BAUD__rec_baud__c9600Hz 5
+#define R_SERIAL0_BAUD__rec_baud__c19k2Hz 6
+#define R_SERIAL0_BAUD__rec_baud__c38k4Hz 7
+#define R_SERIAL0_BAUD__rec_baud__c57k6Hz 8
+#define R_SERIAL0_BAUD__rec_baud__c115k2Hz 9
+#define R_SERIAL0_BAUD__rec_baud__c230k4Hz 10
+#define R_SERIAL0_BAUD__rec_baud__c460k8Hz 11
+#define R_SERIAL0_BAUD__rec_baud__c921k6Hz 12
+#define R_SERIAL0_BAUD__rec_baud__c1843k2Hz 13
+#define R_SERIAL0_BAUD__rec_baud__c6250kHz 14
+#define R_SERIAL0_BAUD__rec_baud__reserved 15
+
+#define R_SERIAL0_REC_CTRL (IO_TYPECAST_BYTE 0xb0000062)
+#define R_SERIAL0_REC_CTRL__dma_err__BITNR 7
+#define R_SERIAL0_REC_CTRL__dma_err__WIDTH 1
+#define R_SERIAL0_REC_CTRL__dma_err__stop 0
+#define R_SERIAL0_REC_CTRL__dma_err__ignore 1
+#define R_SERIAL0_REC_CTRL__rec_enable__BITNR 6
+#define R_SERIAL0_REC_CTRL__rec_enable__WIDTH 1
+#define R_SERIAL0_REC_CTRL__rec_enable__disable 0
+#define R_SERIAL0_REC_CTRL__rec_enable__enable 1
+#define R_SERIAL0_REC_CTRL__rts___BITNR 5
+#define R_SERIAL0_REC_CTRL__rts___WIDTH 1
+#define R_SERIAL0_REC_CTRL__rts___active 0
+#define R_SERIAL0_REC_CTRL__rts___inactive 1
+#define R_SERIAL0_REC_CTRL__sampling__BITNR 4
+#define R_SERIAL0_REC_CTRL__sampling__WIDTH 1
+#define R_SERIAL0_REC_CTRL__sampling__middle 0
+#define R_SERIAL0_REC_CTRL__sampling__majority 1
+#define R_SERIAL0_REC_CTRL__rec_stick_par__BITNR 3
+#define R_SERIAL0_REC_CTRL__rec_stick_par__WIDTH 1
+#define R_SERIAL0_REC_CTRL__rec_stick_par__normal 0
+#define R_SERIAL0_REC_CTRL__rec_stick_par__stick 1
+#define R_SERIAL0_REC_CTRL__rec_par__BITNR 2
+#define R_SERIAL0_REC_CTRL__rec_par__WIDTH 1
+#define R_SERIAL0_REC_CTRL__rec_par__even 0
+#define R_SERIAL0_REC_CTRL__rec_par__odd 1
+#define R_SERIAL0_REC_CTRL__rec_par_en__BITNR 1
+#define R_SERIAL0_REC_CTRL__rec_par_en__WIDTH 1
+#define R_SERIAL0_REC_CTRL__rec_par_en__disable 0
+#define R_SERIAL0_REC_CTRL__rec_par_en__enable 1
+#define R_SERIAL0_REC_CTRL__rec_bitnr__BITNR 0
+#define R_SERIAL0_REC_CTRL__rec_bitnr__WIDTH 1
+#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_8bit 0
+#define R_SERIAL0_REC_CTRL__rec_bitnr__rec_7bit 1
+
+#define R_SERIAL0_TR_CTRL (IO_TYPECAST_BYTE 0xb0000061)
+#define R_SERIAL0_TR_CTRL__txd__BITNR 7
+#define R_SERIAL0_TR_CTRL__txd__WIDTH 1
+#define R_SERIAL0_TR_CTRL__tr_enable__BITNR 6
+#define R_SERIAL0_TR_CTRL__tr_enable__WIDTH 1
+#define R_SERIAL0_TR_CTRL__tr_enable__disable 0
+#define R_SERIAL0_TR_CTRL__tr_enable__enable 1
+#define R_SERIAL0_TR_CTRL__auto_cts__BITNR 5
+#define R_SERIAL0_TR_CTRL__auto_cts__WIDTH 1
+#define R_SERIAL0_TR_CTRL__auto_cts__disabled 0
+#define R_SERIAL0_TR_CTRL__auto_cts__active 1
+#define R_SERIAL0_TR_CTRL__stop_bits__BITNR 4
+#define R_SERIAL0_TR_CTRL__stop_bits__WIDTH 1
+#define R_SERIAL0_TR_CTRL__stop_bits__one_bit 0
+#define R_SERIAL0_TR_CTRL__stop_bits__two_bits 1
+#define R_SERIAL0_TR_CTRL__tr_stick_par__BITNR 3
+#define R_SERIAL0_TR_CTRL__tr_stick_par__WIDTH 1
+#define R_SERIAL0_TR_CTRL__tr_stick_par__normal 0
+#define R_SERIAL0_TR_CTRL__tr_stick_par__stick 1
+#define R_SERIAL0_TR_CTRL__tr_par__BITNR 2
+#define R_SERIAL0_TR_CTRL__tr_par__WIDTH 1
+#define R_SERIAL0_TR_CTRL__tr_par__even 0
+#define R_SERIAL0_TR_CTRL__tr_par__odd 1
+#define R_SERIAL0_TR_CTRL__tr_par_en__BITNR 1
+#define R_SERIAL0_TR_CTRL__tr_par_en__WIDTH 1
+#define R_SERIAL0_TR_CTRL__tr_par_en__disable 0
+#define R_SERIAL0_TR_CTRL__tr_par_en__enable 1
+#define R_SERIAL0_TR_CTRL__tr_bitnr__BITNR 0
+#define R_SERIAL0_TR_CTRL__tr_bitnr__WIDTH 1
+#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_8bit 0
+#define R_SERIAL0_TR_CTRL__tr_bitnr__tr_7bit 1
+
+#define R_SERIAL0_TR_DATA (IO_TYPECAST_BYTE 0xb0000060)
+#define R_SERIAL0_TR_DATA__data_out__BITNR 0
+#define R_SERIAL0_TR_DATA__data_out__WIDTH 8
+
+#define R_SERIAL0_READ (IO_TYPECAST_RO_UDWORD 0xb0000060)
+#define R_SERIAL0_READ__xoff_detect__BITNR 15
+#define R_SERIAL0_READ__xoff_detect__WIDTH 1
+#define R_SERIAL0_READ__xoff_detect__no_xoff 0
+#define R_SERIAL0_READ__xoff_detect__xoff 1
+#define R_SERIAL0_READ__cts___BITNR 14
+#define R_SERIAL0_READ__cts___WIDTH 1
+#define R_SERIAL0_READ__cts___active 0
+#define R_SERIAL0_READ__cts___inactive 1
+#define R_SERIAL0_READ__tr_ready__BITNR 13
+#define R_SERIAL0_READ__tr_ready__WIDTH 1
+#define R_SERIAL0_READ__tr_ready__full 0
+#define R_SERIAL0_READ__tr_ready__ready 1
+#define R_SERIAL0_READ__rxd__BITNR 12
+#define R_SERIAL0_READ__rxd__WIDTH 1
+#define R_SERIAL0_READ__overrun__BITNR 11
+#define R_SERIAL0_READ__overrun__WIDTH 1
+#define R_SERIAL0_READ__overrun__no 0
+#define R_SERIAL0_READ__overrun__yes 1
+#define R_SERIAL0_READ__par_err__BITNR 10
+#define R_SERIAL0_READ__par_err__WIDTH 1
+#define R_SERIAL0_READ__par_err__no 0
+#define R_SERIAL0_READ__par_err__yes 1
+#define R_SERIAL0_READ__framing_err__BITNR 9
+#define R_SERIAL0_READ__framing_err__WIDTH 1
+#define R_SERIAL0_READ__framing_err__no 0
+#define R_SERIAL0_READ__framing_err__yes 1
+#define R_SERIAL0_READ__data_avail__BITNR 8
+#define R_SERIAL0_READ__data_avail__WIDTH 1
+#define R_SERIAL0_READ__data_avail__no 0
+#define R_SERIAL0_READ__data_avail__yes 1
+#define R_SERIAL0_READ__data_in__BITNR 0
+#define R_SERIAL0_READ__data_in__WIDTH 8
+
+#define R_SERIAL0_STATUS (IO_TYPECAST_RO_BYTE 0xb0000061)
+#define R_SERIAL0_STATUS__xoff_detect__BITNR 7
+#define R_SERIAL0_STATUS__xoff_detect__WIDTH 1
+#define R_SERIAL0_STATUS__xoff_detect__no_xoff 0
+#define R_SERIAL0_STATUS__xoff_detect__xoff 1
+#define R_SERIAL0_STATUS__cts___BITNR 6
+#define R_SERIAL0_STATUS__cts___WIDTH 1
+#define R_SERIAL0_STATUS__cts___active 0
+#define R_SERIAL0_STATUS__cts___inactive 1
+#define R_SERIAL0_STATUS__tr_ready__BITNR 5
+#define R_SERIAL0_STATUS__tr_ready__WIDTH 1
+#define R_SERIAL0_STATUS__tr_ready__full 0
+#define R_SERIAL0_STATUS__tr_ready__ready 1
+#define R_SERIAL0_STATUS__rxd__BITNR 4
+#define R_SERIAL0_STATUS__rxd__WIDTH 1
+#define R_SERIAL0_STATUS__overrun__BITNR 3
+#define R_SERIAL0_STATUS__overrun__WIDTH 1
+#define R_SERIAL0_STATUS__overrun__no 0
+#define R_SERIAL0_STATUS__overrun__yes 1
+#define R_SERIAL0_STATUS__par_err__BITNR 2
+#define R_SERIAL0_STATUS__par_err__WIDTH 1
+#define R_SERIAL0_STATUS__par_err__no 0
+#define R_SERIAL0_STATUS__par_err__yes 1
+#define R_SERIAL0_STATUS__framing_err__BITNR 1
+#define R_SERIAL0_STATUS__framing_err__WIDTH 1
+#define R_SERIAL0_STATUS__framing_err__no 0
+#define R_SERIAL0_STATUS__framing_err__yes 1
+#define R_SERIAL0_STATUS__data_avail__BITNR 0
+#define R_SERIAL0_STATUS__data_avail__WIDTH 1
+#define R_SERIAL0_STATUS__data_avail__no 0
+#define R_SERIAL0_STATUS__data_avail__yes 1
+
+#define R_SERIAL0_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000060)
+#define R_SERIAL0_REC_DATA__data_in__BITNR 0
+#define R_SERIAL0_REC_DATA__data_in__WIDTH 8
+
+#define R_SERIAL0_XOFF (IO_TYPECAST_UDWORD 0xb0000064)
+#define R_SERIAL0_XOFF__tx_stop__BITNR 9
+#define R_SERIAL0_XOFF__tx_stop__WIDTH 1
+#define R_SERIAL0_XOFF__tx_stop__enable 0
+#define R_SERIAL0_XOFF__tx_stop__stop 1
+#define R_SERIAL0_XOFF__auto_xoff__BITNR 8
+#define R_SERIAL0_XOFF__auto_xoff__WIDTH 1
+#define R_SERIAL0_XOFF__auto_xoff__disable 0
+#define R_SERIAL0_XOFF__auto_xoff__enable 1
+#define R_SERIAL0_XOFF__xoff_char__BITNR 0
+#define R_SERIAL0_XOFF__xoff_char__WIDTH 8
+
+#define R_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
+#define R_SERIAL1_CTRL__tr_baud__BITNR 28
+#define R_SERIAL1_CTRL__tr_baud__WIDTH 4
+#define R_SERIAL1_CTRL__tr_baud__c300Hz 0
+#define R_SERIAL1_CTRL__tr_baud__c600Hz 1
+#define R_SERIAL1_CTRL__tr_baud__c1200Hz 2
+#define R_SERIAL1_CTRL__tr_baud__c2400Hz 3
+#define R_SERIAL1_CTRL__tr_baud__c4800Hz 4
+#define R_SERIAL1_CTRL__tr_baud__c9600Hz 5
+#define R_SERIAL1_CTRL__tr_baud__c19k2Hz 6
+#define R_SERIAL1_CTRL__tr_baud__c38k4Hz 7
+#define R_SERIAL1_CTRL__tr_baud__c57k6Hz 8
+#define R_SERIAL1_CTRL__tr_baud__c115k2Hz 9
+#define R_SERIAL1_CTRL__tr_baud__c230k4Hz 10
+#define R_SERIAL1_CTRL__tr_baud__c460k8Hz 11
+#define R_SERIAL1_CTRL__tr_baud__c921k6Hz 12
+#define R_SERIAL1_CTRL__tr_baud__c1843k2Hz 13
+#define R_SERIAL1_CTRL__tr_baud__c6250kHz 14
+#define R_SERIAL1_CTRL__tr_baud__reserved 15
+#define R_SERIAL1_CTRL__rec_baud__BITNR 24
+#define R_SERIAL1_CTRL__rec_baud__WIDTH 4
+#define R_SERIAL1_CTRL__rec_baud__c300Hz 0
+#define R_SERIAL1_CTRL__rec_baud__c600Hz 1
+#define R_SERIAL1_CTRL__rec_baud__c1200Hz 2
+#define R_SERIAL1_CTRL__rec_baud__c2400Hz 3
+#define R_SERIAL1_CTRL__rec_baud__c4800Hz 4
+#define R_SERIAL1_CTRL__rec_baud__c9600Hz 5
+#define R_SERIAL1_CTRL__rec_baud__c19k2Hz 6
+#define R_SERIAL1_CTRL__rec_baud__c38k4Hz 7
+#define R_SERIAL1_CTRL__rec_baud__c57k6Hz 8
+#define R_SERIAL1_CTRL__rec_baud__c115k2Hz 9
+#define R_SERIAL1_CTRL__rec_baud__c230k4Hz 10
+#define R_SERIAL1_CTRL__rec_baud__c460k8Hz 11
+#define R_SERIAL1_CTRL__rec_baud__c921k6Hz 12
+#define R_SERIAL1_CTRL__rec_baud__c1843k2Hz 13
+#define R_SERIAL1_CTRL__rec_baud__c6250kHz 14
+#define R_SERIAL1_CTRL__rec_baud__reserved 15
+#define R_SERIAL1_CTRL__dma_err__BITNR 23
+#define R_SERIAL1_CTRL__dma_err__WIDTH 1
+#define R_SERIAL1_CTRL__dma_err__stop 0
+#define R_SERIAL1_CTRL__dma_err__ignore 1
+#define R_SERIAL1_CTRL__rec_enable__BITNR 22
+#define R_SERIAL1_CTRL__rec_enable__WIDTH 1
+#define R_SERIAL1_CTRL__rec_enable__disable 0
+#define R_SERIAL1_CTRL__rec_enable__enable 1
+#define R_SERIAL1_CTRL__rts___BITNR 21
+#define R_SERIAL1_CTRL__rts___WIDTH 1
+#define R_SERIAL1_CTRL__rts___active 0
+#define R_SERIAL1_CTRL__rts___inactive 1
+#define R_SERIAL1_CTRL__sampling__BITNR 20
+#define R_SERIAL1_CTRL__sampling__WIDTH 1
+#define R_SERIAL1_CTRL__sampling__middle 0
+#define R_SERIAL1_CTRL__sampling__majority 1
+#define R_SERIAL1_CTRL__rec_stick_par__BITNR 19
+#define R_SERIAL1_CTRL__rec_stick_par__WIDTH 1
+#define R_SERIAL1_CTRL__rec_stick_par__normal 0
+#define R_SERIAL1_CTRL__rec_stick_par__stick 1
+#define R_SERIAL1_CTRL__rec_par__BITNR 18
+#define R_SERIAL1_CTRL__rec_par__WIDTH 1
+#define R_SERIAL1_CTRL__rec_par__even 0
+#define R_SERIAL1_CTRL__rec_par__odd 1
+#define R_SERIAL1_CTRL__rec_par_en__BITNR 17
+#define R_SERIAL1_CTRL__rec_par_en__WIDTH 1
+#define R_SERIAL1_CTRL__rec_par_en__disable 0
+#define R_SERIAL1_CTRL__rec_par_en__enable 1
+#define R_SERIAL1_CTRL__rec_bitnr__BITNR 16
+#define R_SERIAL1_CTRL__rec_bitnr__WIDTH 1
+#define R_SERIAL1_CTRL__rec_bitnr__rec_8bit 0
+#define R_SERIAL1_CTRL__rec_bitnr__rec_7bit 1
+#define R_SERIAL1_CTRL__txd__BITNR 15
+#define R_SERIAL1_CTRL__txd__WIDTH 1
+#define R_SERIAL1_CTRL__tr_enable__BITNR 14
+#define R_SERIAL1_CTRL__tr_enable__WIDTH 1
+#define R_SERIAL1_CTRL__tr_enable__disable 0
+#define R_SERIAL1_CTRL__tr_enable__enable 1
+#define R_SERIAL1_CTRL__auto_cts__BITNR 13
+#define R_SERIAL1_CTRL__auto_cts__WIDTH 1
+#define R_SERIAL1_CTRL__auto_cts__disabled 0
+#define R_SERIAL1_CTRL__auto_cts__active 1
+#define R_SERIAL1_CTRL__stop_bits__BITNR 12
+#define R_SERIAL1_CTRL__stop_bits__WIDTH 1
+#define R_SERIAL1_CTRL__stop_bits__one_bit 0
+#define R_SERIAL1_CTRL__stop_bits__two_bits 1
+#define R_SERIAL1_CTRL__tr_stick_par__BITNR 11
+#define R_SERIAL1_CTRL__tr_stick_par__WIDTH 1
+#define R_SERIAL1_CTRL__tr_stick_par__normal 0
+#define R_SERIAL1_CTRL__tr_stick_par__stick 1
+#define R_SERIAL1_CTRL__tr_par__BITNR 10
+#define R_SERIAL1_CTRL__tr_par__WIDTH 1
+#define R_SERIAL1_CTRL__tr_par__even 0
+#define R_SERIAL1_CTRL__tr_par__odd 1
+#define R_SERIAL1_CTRL__tr_par_en__BITNR 9
+#define R_SERIAL1_CTRL__tr_par_en__WIDTH 1
+#define R_SERIAL1_CTRL__tr_par_en__disable 0
+#define R_SERIAL1_CTRL__tr_par_en__enable 1
+#define R_SERIAL1_CTRL__tr_bitnr__BITNR 8
+#define R_SERIAL1_CTRL__tr_bitnr__WIDTH 1
+#define R_SERIAL1_CTRL__tr_bitnr__tr_8bit 0
+#define R_SERIAL1_CTRL__tr_bitnr__tr_7bit 1
+#define R_SERIAL1_CTRL__data_out__BITNR 0
+#define R_SERIAL1_CTRL__data_out__WIDTH 8
+
+#define R_SERIAL1_BAUD (IO_TYPECAST_BYTE 0xb000006b)
+#define R_SERIAL1_BAUD__tr_baud__BITNR 4
+#define R_SERIAL1_BAUD__tr_baud__WIDTH 4
+#define R_SERIAL1_BAUD__tr_baud__c300Hz 0
+#define R_SERIAL1_BAUD__tr_baud__c600Hz 1
+#define R_SERIAL1_BAUD__tr_baud__c1200Hz 2
+#define R_SERIAL1_BAUD__tr_baud__c2400Hz 3
+#define R_SERIAL1_BAUD__tr_baud__c4800Hz 4
+#define R_SERIAL1_BAUD__tr_baud__c9600Hz 5
+#define R_SERIAL1_BAUD__tr_baud__c19k2Hz 6
+#define R_SERIAL1_BAUD__tr_baud__c38k4Hz 7
+#define R_SERIAL1_BAUD__tr_baud__c57k6Hz 8
+#define R_SERIAL1_BAUD__tr_baud__c115k2Hz 9
+#define R_SERIAL1_BAUD__tr_baud__c230k4Hz 10
+#define R_SERIAL1_BAUD__tr_baud__c460k8Hz 11
+#define R_SERIAL1_BAUD__tr_baud__c921k6Hz 12
+#define R_SERIAL1_BAUD__tr_baud__c1843k2Hz 13
+#define R_SERIAL1_BAUD__tr_baud__c6250kHz 14
+#define R_SERIAL1_BAUD__tr_baud__reserved 15
+#define R_SERIAL1_BAUD__rec_baud__BITNR 0
+#define R_SERIAL1_BAUD__rec_baud__WIDTH 4
+#define R_SERIAL1_BAUD__rec_baud__c300Hz 0
+#define R_SERIAL1_BAUD__rec_baud__c600Hz 1
+#define R_SERIAL1_BAUD__rec_baud__c1200Hz 2
+#define R_SERIAL1_BAUD__rec_baud__c2400Hz 3
+#define R_SERIAL1_BAUD__rec_baud__c4800Hz 4
+#define R_SERIAL1_BAUD__rec_baud__c9600Hz 5
+#define R_SERIAL1_BAUD__rec_baud__c19k2Hz 6
+#define R_SERIAL1_BAUD__rec_baud__c38k4Hz 7
+#define R_SERIAL1_BAUD__rec_baud__c57k6Hz 8
+#define R_SERIAL1_BAUD__rec_baud__c115k2Hz 9
+#define R_SERIAL1_BAUD__rec_baud__c230k4Hz 10
+#define R_SERIAL1_BAUD__rec_baud__c460k8Hz 11
+#define R_SERIAL1_BAUD__rec_baud__c921k6Hz 12
+#define R_SERIAL1_BAUD__rec_baud__c1843k2Hz 13
+#define R_SERIAL1_BAUD__rec_baud__c6250kHz 14
+#define R_SERIAL1_BAUD__rec_baud__reserved 15
+
+#define R_SERIAL1_REC_CTRL (IO_TYPECAST_BYTE 0xb000006a)
+#define R_SERIAL1_REC_CTRL__dma_err__BITNR 7
+#define R_SERIAL1_REC_CTRL__dma_err__WIDTH 1
+#define R_SERIAL1_REC_CTRL__dma_err__stop 0
+#define R_SERIAL1_REC_CTRL__dma_err__ignore 1
+#define R_SERIAL1_REC_CTRL__rec_enable__BITNR 6
+#define R_SERIAL1_REC_CTRL__rec_enable__WIDTH 1
+#define R_SERIAL1_REC_CTRL__rec_enable__disable 0
+#define R_SERIAL1_REC_CTRL__rec_enable__enable 1
+#define R_SERIAL1_REC_CTRL__rts___BITNR 5
+#define R_SERIAL1_REC_CTRL__rts___WIDTH 1
+#define R_SERIAL1_REC_CTRL__rts___active 0
+#define R_SERIAL1_REC_CTRL__rts___inactive 1
+#define R_SERIAL1_REC_CTRL__sampling__BITNR 4
+#define R_SERIAL1_REC_CTRL__sampling__WIDTH 1
+#define R_SERIAL1_REC_CTRL__sampling__middle 0
+#define R_SERIAL1_REC_CTRL__sampling__majority 1
+#define R_SERIAL1_REC_CTRL__rec_stick_par__BITNR 3
+#define R_SERIAL1_REC_CTRL__rec_stick_par__WIDTH 1
+#define R_SERIAL1_REC_CTRL__rec_stick_par__normal 0
+#define R_SERIAL1_REC_CTRL__rec_stick_par__stick 1
+#define R_SERIAL1_REC_CTRL__rec_par__BITNR 2
+#define R_SERIAL1_REC_CTRL__rec_par__WIDTH 1
+#define R_SERIAL1_REC_CTRL__rec_par__even 0
+#define R_SERIAL1_REC_CTRL__rec_par__odd 1
+#define R_SERIAL1_REC_CTRL__rec_par_en__BITNR 1
+#define R_SERIAL1_REC_CTRL__rec_par_en__WIDTH 1
+#define R_SERIAL1_REC_CTRL__rec_par_en__disable 0
+#define R_SERIAL1_REC_CTRL__rec_par_en__enable 1
+#define R_SERIAL1_REC_CTRL__rec_bitnr__BITNR 0
+#define R_SERIAL1_REC_CTRL__rec_bitnr__WIDTH 1
+#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_8bit 0
+#define R_SERIAL1_REC_CTRL__rec_bitnr__rec_7bit 1
+
+#define R_SERIAL1_TR_CTRL (IO_TYPECAST_BYTE 0xb0000069)
+#define R_SERIAL1_TR_CTRL__txd__BITNR 7
+#define R_SERIAL1_TR_CTRL__txd__WIDTH 1
+#define R_SERIAL1_TR_CTRL__tr_enable__BITNR 6
+#define R_SERIAL1_TR_CTRL__tr_enable__WIDTH 1
+#define R_SERIAL1_TR_CTRL__tr_enable__disable 0
+#define R_SERIAL1_TR_CTRL__tr_enable__enable 1
+#define R_SERIAL1_TR_CTRL__auto_cts__BITNR 5
+#define R_SERIAL1_TR_CTRL__auto_cts__WIDTH 1
+#define R_SERIAL1_TR_CTRL__auto_cts__disabled 0
+#define R_SERIAL1_TR_CTRL__auto_cts__active 1
+#define R_SERIAL1_TR_CTRL__stop_bits__BITNR 4
+#define R_SERIAL1_TR_CTRL__stop_bits__WIDTH 1
+#define R_SERIAL1_TR_CTRL__stop_bits__one_bit 0
+#define R_SERIAL1_TR_CTRL__stop_bits__two_bits 1
+#define R_SERIAL1_TR_CTRL__tr_stick_par__BITNR 3
+#define R_SERIAL1_TR_CTRL__tr_stick_par__WIDTH 1
+#define R_SERIAL1_TR_CTRL__tr_stick_par__normal 0
+#define R_SERIAL1_TR_CTRL__tr_stick_par__stick 1
+#define R_SERIAL1_TR_CTRL__tr_par__BITNR 2
+#define R_SERIAL1_TR_CTRL__tr_par__WIDTH 1
+#define R_SERIAL1_TR_CTRL__tr_par__even 0
+#define R_SERIAL1_TR_CTRL__tr_par__odd 1
+#define R_SERIAL1_TR_CTRL__tr_par_en__BITNR 1
+#define R_SERIAL1_TR_CTRL__tr_par_en__WIDTH 1
+#define R_SERIAL1_TR_CTRL__tr_par_en__disable 0
+#define R_SERIAL1_TR_CTRL__tr_par_en__enable 1
+#define R_SERIAL1_TR_CTRL__tr_bitnr__BITNR 0
+#define R_SERIAL1_TR_CTRL__tr_bitnr__WIDTH 1
+#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_8bit 0
+#define R_SERIAL1_TR_CTRL__tr_bitnr__tr_7bit 1
+
+#define R_SERIAL1_TR_DATA (IO_TYPECAST_BYTE 0xb0000068)
+#define R_SERIAL1_TR_DATA__data_out__BITNR 0
+#define R_SERIAL1_TR_DATA__data_out__WIDTH 8
+
+#define R_SERIAL1_READ (IO_TYPECAST_RO_UDWORD 0xb0000068)
+#define R_SERIAL1_READ__xoff_detect__BITNR 15
+#define R_SERIAL1_READ__xoff_detect__WIDTH 1
+#define R_SERIAL1_READ__xoff_detect__no_xoff 0
+#define R_SERIAL1_READ__xoff_detect__xoff 1
+#define R_SERIAL1_READ__cts___BITNR 14
+#define R_SERIAL1_READ__cts___WIDTH 1
+#define R_SERIAL1_READ__cts___active 0
+#define R_SERIAL1_READ__cts___inactive 1
+#define R_SERIAL1_READ__tr_ready__BITNR 13
+#define R_SERIAL1_READ__tr_ready__WIDTH 1
+#define R_SERIAL1_READ__tr_ready__full 0
+#define R_SERIAL1_READ__tr_ready__ready 1
+#define R_SERIAL1_READ__rxd__BITNR 12
+#define R_SERIAL1_READ__rxd__WIDTH 1
+#define R_SERIAL1_READ__overrun__BITNR 11
+#define R_SERIAL1_READ__overrun__WIDTH 1
+#define R_SERIAL1_READ__overrun__no 0
+#define R_SERIAL1_READ__overrun__yes 1
+#define R_SERIAL1_READ__par_err__BITNR 10
+#define R_SERIAL1_READ__par_err__WIDTH 1
+#define R_SERIAL1_READ__par_err__no 0
+#define R_SERIAL1_READ__par_err__yes 1
+#define R_SERIAL1_READ__framing_err__BITNR 9
+#define R_SERIAL1_READ__framing_err__WIDTH 1
+#define R_SERIAL1_READ__framing_err__no 0
+#define R_SERIAL1_READ__framing_err__yes 1
+#define R_SERIAL1_READ__data_avail__BITNR 8
+#define R_SERIAL1_READ__data_avail__WIDTH 1
+#define R_SERIAL1_READ__data_avail__no 0
+#define R_SERIAL1_READ__data_avail__yes 1
+#define R_SERIAL1_READ__data_in__BITNR 0
+#define R_SERIAL1_READ__data_in__WIDTH 8
+
+#define R_SERIAL1_STATUS (IO_TYPECAST_RO_BYTE 0xb0000069)
+#define R_SERIAL1_STATUS__xoff_detect__BITNR 7
+#define R_SERIAL1_STATUS__xoff_detect__WIDTH 1
+#define R_SERIAL1_STATUS__xoff_detect__no_xoff 0
+#define R_SERIAL1_STATUS__xoff_detect__xoff 1
+#define R_SERIAL1_STATUS__cts___BITNR 6
+#define R_SERIAL1_STATUS__cts___WIDTH 1
+#define R_SERIAL1_STATUS__cts___active 0
+#define R_SERIAL1_STATUS__cts___inactive 1
+#define R_SERIAL1_STATUS__tr_ready__BITNR 5
+#define R_SERIAL1_STATUS__tr_ready__WIDTH 1
+#define R_SERIAL1_STATUS__tr_ready__full 0
+#define R_SERIAL1_STATUS__tr_ready__ready 1
+#define R_SERIAL1_STATUS__rxd__BITNR 4
+#define R_SERIAL1_STATUS__rxd__WIDTH 1
+#define R_SERIAL1_STATUS__overrun__BITNR 3
+#define R_SERIAL1_STATUS__overrun__WIDTH 1
+#define R_SERIAL1_STATUS__overrun__no 0
+#define R_SERIAL1_STATUS__overrun__yes 1
+#define R_SERIAL1_STATUS__par_err__BITNR 2
+#define R_SERIAL1_STATUS__par_err__WIDTH 1
+#define R_SERIAL1_STATUS__par_err__no 0
+#define R_SERIAL1_STATUS__par_err__yes 1
+#define R_SERIAL1_STATUS__framing_err__BITNR 1
+#define R_SERIAL1_STATUS__framing_err__WIDTH 1
+#define R_SERIAL1_STATUS__framing_err__no 0
+#define R_SERIAL1_STATUS__framing_err__yes 1
+#define R_SERIAL1_STATUS__data_avail__BITNR 0
+#define R_SERIAL1_STATUS__data_avail__WIDTH 1
+#define R_SERIAL1_STATUS__data_avail__no 0
+#define R_SERIAL1_STATUS__data_avail__yes 1
+
+#define R_SERIAL1_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000068)
+#define R_SERIAL1_REC_DATA__data_in__BITNR 0
+#define R_SERIAL1_REC_DATA__data_in__WIDTH 8
+
+#define R_SERIAL1_XOFF (IO_TYPECAST_UDWORD 0xb000006c)
+#define R_SERIAL1_XOFF__tx_stop__BITNR 9
+#define R_SERIAL1_XOFF__tx_stop__WIDTH 1
+#define R_SERIAL1_XOFF__tx_stop__enable 0
+#define R_SERIAL1_XOFF__tx_stop__stop 1
+#define R_SERIAL1_XOFF__auto_xoff__BITNR 8
+#define R_SERIAL1_XOFF__auto_xoff__WIDTH 1
+#define R_SERIAL1_XOFF__auto_xoff__disable 0
+#define R_SERIAL1_XOFF__auto_xoff__enable 1
+#define R_SERIAL1_XOFF__xoff_char__BITNR 0
+#define R_SERIAL1_XOFF__xoff_char__WIDTH 8
+
+#define R_SERIAL2_CTRL (IO_TYPECAST_UDWORD 0xb0000070)
+#define R_SERIAL2_CTRL__tr_baud__BITNR 28
+#define R_SERIAL2_CTRL__tr_baud__WIDTH 4
+#define R_SERIAL2_CTRL__tr_baud__c300Hz 0
+#define R_SERIAL2_CTRL__tr_baud__c600Hz 1
+#define R_SERIAL2_CTRL__tr_baud__c1200Hz 2
+#define R_SERIAL2_CTRL__tr_baud__c2400Hz 3
+#define R_SERIAL2_CTRL__tr_baud__c4800Hz 4
+#define R_SERIAL2_CTRL__tr_baud__c9600Hz 5
+#define R_SERIAL2_CTRL__tr_baud__c19k2Hz 6
+#define R_SERIAL2_CTRL__tr_baud__c38k4Hz 7
+#define R_SERIAL2_CTRL__tr_baud__c57k6Hz 8
+#define R_SERIAL2_CTRL__tr_baud__c115k2Hz 9
+#define R_SERIAL2_CTRL__tr_baud__c230k4Hz 10
+#define R_SERIAL2_CTRL__tr_baud__c460k8Hz 11
+#define R_SERIAL2_CTRL__tr_baud__c921k6Hz 12
+#define R_SERIAL2_CTRL__tr_baud__c1843k2Hz 13
+#define R_SERIAL2_CTRL__tr_baud__c6250kHz 14
+#define R_SERIAL2_CTRL__tr_baud__reserved 15
+#define R_SERIAL2_CTRL__rec_baud__BITNR 24
+#define R_SERIAL2_CTRL__rec_baud__WIDTH 4
+#define R_SERIAL2_CTRL__rec_baud__c300Hz 0
+#define R_SERIAL2_CTRL__rec_baud__c600Hz 1
+#define R_SERIAL2_CTRL__rec_baud__c1200Hz 2
+#define R_SERIAL2_CTRL__rec_baud__c2400Hz 3
+#define R_SERIAL2_CTRL__rec_baud__c4800Hz 4
+#define R_SERIAL2_CTRL__rec_baud__c9600Hz 5
+#define R_SERIAL2_CTRL__rec_baud__c19k2Hz 6
+#define R_SERIAL2_CTRL__rec_baud__c38k4Hz 7
+#define R_SERIAL2_CTRL__rec_baud__c57k6Hz 8
+#define R_SERIAL2_CTRL__rec_baud__c115k2Hz 9
+#define R_SERIAL2_CTRL__rec_baud__c230k4Hz 10
+#define R_SERIAL2_CTRL__rec_baud__c460k8Hz 11
+#define R_SERIAL2_CTRL__rec_baud__c921k6Hz 12
+#define R_SERIAL2_CTRL__rec_baud__c1843k2Hz 13
+#define R_SERIAL2_CTRL__rec_baud__c6250kHz 14
+#define R_SERIAL2_CTRL__rec_baud__reserved 15
+#define R_SERIAL2_CTRL__dma_err__BITNR 23
+#define R_SERIAL2_CTRL__dma_err__WIDTH 1
+#define R_SERIAL2_CTRL__dma_err__stop 0
+#define R_SERIAL2_CTRL__dma_err__ignore 1
+#define R_SERIAL2_CTRL__rec_enable__BITNR 22
+#define R_SERIAL2_CTRL__rec_enable__WIDTH 1
+#define R_SERIAL2_CTRL__rec_enable__disable 0
+#define R_SERIAL2_CTRL__rec_enable__enable 1
+#define R_SERIAL2_CTRL__rts___BITNR 21
+#define R_SERIAL2_CTRL__rts___WIDTH 1
+#define R_SERIAL2_CTRL__rts___active 0
+#define R_SERIAL2_CTRL__rts___inactive 1
+#define R_SERIAL2_CTRL__sampling__BITNR 20
+#define R_SERIAL2_CTRL__sampling__WIDTH 1
+#define R_SERIAL2_CTRL__sampling__middle 0
+#define R_SERIAL2_CTRL__sampling__majority 1
+#define R_SERIAL2_CTRL__rec_stick_par__BITNR 19
+#define R_SERIAL2_CTRL__rec_stick_par__WIDTH 1
+#define R_SERIAL2_CTRL__rec_stick_par__normal 0
+#define R_SERIAL2_CTRL__rec_stick_par__stick 1
+#define R_SERIAL2_CTRL__rec_par__BITNR 18
+#define R_SERIAL2_CTRL__rec_par__WIDTH 1
+#define R_SERIAL2_CTRL__rec_par__even 0
+#define R_SERIAL2_CTRL__rec_par__odd 1
+#define R_SERIAL2_CTRL__rec_par_en__BITNR 17
+#define R_SERIAL2_CTRL__rec_par_en__WIDTH 1
+#define R_SERIAL2_CTRL__rec_par_en__disable 0
+#define R_SERIAL2_CTRL__rec_par_en__enable 1
+#define R_SERIAL2_CTRL__rec_bitnr__BITNR 16
+#define R_SERIAL2_CTRL__rec_bitnr__WIDTH 1
+#define R_SERIAL2_CTRL__rec_bitnr__rec_8bit 0
+#define R_SERIAL2_CTRL__rec_bitnr__rec_7bit 1
+#define R_SERIAL2_CTRL__txd__BITNR 15
+#define R_SERIAL2_CTRL__txd__WIDTH 1
+#define R_SERIAL2_CTRL__tr_enable__BITNR 14
+#define R_SERIAL2_CTRL__tr_enable__WIDTH 1
+#define R_SERIAL2_CTRL__tr_enable__disable 0
+#define R_SERIAL2_CTRL__tr_enable__enable 1
+#define R_SERIAL2_CTRL__auto_cts__BITNR 13
+#define R_SERIAL2_CTRL__auto_cts__WIDTH 1
+#define R_SERIAL2_CTRL__auto_cts__disabled 0
+#define R_SERIAL2_CTRL__auto_cts__active 1
+#define R_SERIAL2_CTRL__stop_bits__BITNR 12
+#define R_SERIAL2_CTRL__stop_bits__WIDTH 1
+#define R_SERIAL2_CTRL__stop_bits__one_bit 0
+#define R_SERIAL2_CTRL__stop_bits__two_bits 1
+#define R_SERIAL2_CTRL__tr_stick_par__BITNR 11
+#define R_SERIAL2_CTRL__tr_stick_par__WIDTH 1
+#define R_SERIAL2_CTRL__tr_stick_par__normal 0
+#define R_SERIAL2_CTRL__tr_stick_par__stick 1
+#define R_SERIAL2_CTRL__tr_par__BITNR 10
+#define R_SERIAL2_CTRL__tr_par__WIDTH 1
+#define R_SERIAL2_CTRL__tr_par__even 0
+#define R_SERIAL2_CTRL__tr_par__odd 1
+#define R_SERIAL2_CTRL__tr_par_en__BITNR 9
+#define R_SERIAL2_CTRL__tr_par_en__WIDTH 1
+#define R_SERIAL2_CTRL__tr_par_en__disable 0
+#define R_SERIAL2_CTRL__tr_par_en__enable 1
+#define R_SERIAL2_CTRL__tr_bitnr__BITNR 8
+#define R_SERIAL2_CTRL__tr_bitnr__WIDTH 1
+#define R_SERIAL2_CTRL__tr_bitnr__tr_8bit 0
+#define R_SERIAL2_CTRL__tr_bitnr__tr_7bit 1
+#define R_SERIAL2_CTRL__data_out__BITNR 0
+#define R_SERIAL2_CTRL__data_out__WIDTH 8
+
+#define R_SERIAL2_BAUD (IO_TYPECAST_BYTE 0xb0000073)
+#define R_SERIAL2_BAUD__tr_baud__BITNR 4
+#define R_SERIAL2_BAUD__tr_baud__WIDTH 4
+#define R_SERIAL2_BAUD__tr_baud__c300Hz 0
+#define R_SERIAL2_BAUD__tr_baud__c600Hz 1
+#define R_SERIAL2_BAUD__tr_baud__c1200Hz 2
+#define R_SERIAL2_BAUD__tr_baud__c2400Hz 3
+#define R_SERIAL2_BAUD__tr_baud__c4800Hz 4
+#define R_SERIAL2_BAUD__tr_baud__c9600Hz 5
+#define R_SERIAL2_BAUD__tr_baud__c19k2Hz 6
+#define R_SERIAL2_BAUD__tr_baud__c38k4Hz 7
+#define R_SERIAL2_BAUD__tr_baud__c57k6Hz 8
+#define R_SERIAL2_BAUD__tr_baud__c115k2Hz 9
+#define R_SERIAL2_BAUD__tr_baud__c230k4Hz 10
+#define R_SERIAL2_BAUD__tr_baud__c460k8Hz 11
+#define R_SERIAL2_BAUD__tr_baud__c921k6Hz 12
+#define R_SERIAL2_BAUD__tr_baud__c1843k2Hz 13
+#define R_SERIAL2_BAUD__tr_baud__c6250kHz 14
+#define R_SERIAL2_BAUD__tr_baud__reserved 15
+#define R_SERIAL2_BAUD__rec_baud__BITNR 0
+#define R_SERIAL2_BAUD__rec_baud__WIDTH 4
+#define R_SERIAL2_BAUD__rec_baud__c300Hz 0
+#define R_SERIAL2_BAUD__rec_baud__c600Hz 1
+#define R_SERIAL2_BAUD__rec_baud__c1200Hz 2
+#define R_SERIAL2_BAUD__rec_baud__c2400Hz 3
+#define R_SERIAL2_BAUD__rec_baud__c4800Hz 4
+#define R_SERIAL2_BAUD__rec_baud__c9600Hz 5
+#define R_SERIAL2_BAUD__rec_baud__c19k2Hz 6
+#define R_SERIAL2_BAUD__rec_baud__c38k4Hz 7
+#define R_SERIAL2_BAUD__rec_baud__c57k6Hz 8
+#define R_SERIAL2_BAUD__rec_baud__c115k2Hz 9
+#define R_SERIAL2_BAUD__rec_baud__c230k4Hz 10
+#define R_SERIAL2_BAUD__rec_baud__c460k8Hz 11
+#define R_SERIAL2_BAUD__rec_baud__c921k6Hz 12
+#define R_SERIAL2_BAUD__rec_baud__c1843k2Hz 13
+#define R_SERIAL2_BAUD__rec_baud__c6250kHz 14
+#define R_SERIAL2_BAUD__rec_baud__reserved 15
+
+#define R_SERIAL2_REC_CTRL (IO_TYPECAST_BYTE 0xb0000072)
+#define R_SERIAL2_REC_CTRL__dma_err__BITNR 7
+#define R_SERIAL2_REC_CTRL__dma_err__WIDTH 1
+#define R_SERIAL2_REC_CTRL__dma_err__stop 0
+#define R_SERIAL2_REC_CTRL__dma_err__ignore 1
+#define R_SERIAL2_REC_CTRL__rec_enable__BITNR 6
+#define R_SERIAL2_REC_CTRL__rec_enable__WIDTH 1
+#define R_SERIAL2_REC_CTRL__rec_enable__disable 0
+#define R_SERIAL2_REC_CTRL__rec_enable__enable 1
+#define R_SERIAL2_REC_CTRL__rts___BITNR 5
+#define R_SERIAL2_REC_CTRL__rts___WIDTH 1
+#define R_SERIAL2_REC_CTRL__rts___active 0
+#define R_SERIAL2_REC_CTRL__rts___inactive 1
+#define R_SERIAL2_REC_CTRL__sampling__BITNR 4
+#define R_SERIAL2_REC_CTRL__sampling__WIDTH 1
+#define R_SERIAL2_REC_CTRL__sampling__middle 0
+#define R_SERIAL2_REC_CTRL__sampling__majority 1
+#define R_SERIAL2_REC_CTRL__rec_stick_par__BITNR 3
+#define R_SERIAL2_REC_CTRL__rec_stick_par__WIDTH 1
+#define R_SERIAL2_REC_CTRL__rec_stick_par__normal 0
+#define R_SERIAL2_REC_CTRL__rec_stick_par__stick 1
+#define R_SERIAL2_REC_CTRL__rec_par__BITNR 2
+#define R_SERIAL2_REC_CTRL__rec_par__WIDTH 1
+#define R_SERIAL2_REC_CTRL__rec_par__even 0
+#define R_SERIAL2_REC_CTRL__rec_par__odd 1
+#define R_SERIAL2_REC_CTRL__rec_par_en__BITNR 1
+#define R_SERIAL2_REC_CTRL__rec_par_en__WIDTH 1
+#define R_SERIAL2_REC_CTRL__rec_par_en__disable 0
+#define R_SERIAL2_REC_CTRL__rec_par_en__enable 1
+#define R_SERIAL2_REC_CTRL__rec_bitnr__BITNR 0
+#define R_SERIAL2_REC_CTRL__rec_bitnr__WIDTH 1
+#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_8bit 0
+#define R_SERIAL2_REC_CTRL__rec_bitnr__rec_7bit 1
+
+#define R_SERIAL2_TR_CTRL (IO_TYPECAST_BYTE 0xb0000071)
+#define R_SERIAL2_TR_CTRL__txd__BITNR 7
+#define R_SERIAL2_TR_CTRL__txd__WIDTH 1
+#define R_SERIAL2_TR_CTRL__tr_enable__BITNR 6
+#define R_SERIAL2_TR_CTRL__tr_enable__WIDTH 1
+#define R_SERIAL2_TR_CTRL__tr_enable__disable 0
+#define R_SERIAL2_TR_CTRL__tr_enable__enable 1
+#define R_SERIAL2_TR_CTRL__auto_cts__BITNR 5
+#define R_SERIAL2_TR_CTRL__auto_cts__WIDTH 1
+#define R_SERIAL2_TR_CTRL__auto_cts__disabled 0
+#define R_SERIAL2_TR_CTRL__auto_cts__active 1
+#define R_SERIAL2_TR_CTRL__stop_bits__BITNR 4
+#define R_SERIAL2_TR_CTRL__stop_bits__WIDTH 1
+#define R_SERIAL2_TR_CTRL__stop_bits__one_bit 0
+#define R_SERIAL2_TR_CTRL__stop_bits__two_bits 1
+#define R_SERIAL2_TR_CTRL__tr_stick_par__BITNR 3
+#define R_SERIAL2_TR_CTRL__tr_stick_par__WIDTH 1
+#define R_SERIAL2_TR_CTRL__tr_stick_par__normal 0
+#define R_SERIAL2_TR_CTRL__tr_stick_par__stick 1
+#define R_SERIAL2_TR_CTRL__tr_par__BITNR 2
+#define R_SERIAL2_TR_CTRL__tr_par__WIDTH 1
+#define R_SERIAL2_TR_CTRL__tr_par__even 0
+#define R_SERIAL2_TR_CTRL__tr_par__odd 1
+#define R_SERIAL2_TR_CTRL__tr_par_en__BITNR 1
+#define R_SERIAL2_TR_CTRL__tr_par_en__WIDTH 1
+#define R_SERIAL2_TR_CTRL__tr_par_en__disable 0
+#define R_SERIAL2_TR_CTRL__tr_par_en__enable 1
+#define R_SERIAL2_TR_CTRL__tr_bitnr__BITNR 0
+#define R_SERIAL2_TR_CTRL__tr_bitnr__WIDTH 1
+#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_8bit 0
+#define R_SERIAL2_TR_CTRL__tr_bitnr__tr_7bit 1
+
+#define R_SERIAL2_TR_DATA (IO_TYPECAST_BYTE 0xb0000070)
+#define R_SERIAL2_TR_DATA__data_out__BITNR 0
+#define R_SERIAL2_TR_DATA__data_out__WIDTH 8
+
+#define R_SERIAL2_READ (IO_TYPECAST_RO_UDWORD 0xb0000070)
+#define R_SERIAL2_READ__xoff_detect__BITNR 15
+#define R_SERIAL2_READ__xoff_detect__WIDTH 1
+#define R_SERIAL2_READ__xoff_detect__no_xoff 0
+#define R_SERIAL2_READ__xoff_detect__xoff 1
+#define R_SERIAL2_READ__cts___BITNR 14
+#define R_SERIAL2_READ__cts___WIDTH 1
+#define R_SERIAL2_READ__cts___active 0
+#define R_SERIAL2_READ__cts___inactive 1
+#define R_SERIAL2_READ__tr_ready__BITNR 13
+#define R_SERIAL2_READ__tr_ready__WIDTH 1
+#define R_SERIAL2_READ__tr_ready__full 0
+#define R_SERIAL2_READ__tr_ready__ready 1
+#define R_SERIAL2_READ__rxd__BITNR 12
+#define R_SERIAL2_READ__rxd__WIDTH 1
+#define R_SERIAL2_READ__overrun__BITNR 11
+#define R_SERIAL2_READ__overrun__WIDTH 1
+#define R_SERIAL2_READ__overrun__no 0
+#define R_SERIAL2_READ__overrun__yes 1
+#define R_SERIAL2_READ__par_err__BITNR 10
+#define R_SERIAL2_READ__par_err__WIDTH 1
+#define R_SERIAL2_READ__par_err__no 0
+#define R_SERIAL2_READ__par_err__yes 1
+#define R_SERIAL2_READ__framing_err__BITNR 9
+#define R_SERIAL2_READ__framing_err__WIDTH 1
+#define R_SERIAL2_READ__framing_err__no 0
+#define R_SERIAL2_READ__framing_err__yes 1
+#define R_SERIAL2_READ__data_avail__BITNR 8
+#define R_SERIAL2_READ__data_avail__WIDTH 1
+#define R_SERIAL2_READ__data_avail__no 0
+#define R_SERIAL2_READ__data_avail__yes 1
+#define R_SERIAL2_READ__data_in__BITNR 0
+#define R_SERIAL2_READ__data_in__WIDTH 8
+
+#define R_SERIAL2_STATUS (IO_TYPECAST_RO_BYTE 0xb0000071)
+#define R_SERIAL2_STATUS__xoff_detect__BITNR 7
+#define R_SERIAL2_STATUS__xoff_detect__WIDTH 1
+#define R_SERIAL2_STATUS__xoff_detect__no_xoff 0
+#define R_SERIAL2_STATUS__xoff_detect__xoff 1
+#define R_SERIAL2_STATUS__cts___BITNR 6
+#define R_SERIAL2_STATUS__cts___WIDTH 1
+#define R_SERIAL2_STATUS__cts___active 0
+#define R_SERIAL2_STATUS__cts___inactive 1
+#define R_SERIAL2_STATUS__tr_ready__BITNR 5
+#define R_SERIAL2_STATUS__tr_ready__WIDTH 1
+#define R_SERIAL2_STATUS__tr_ready__full 0
+#define R_SERIAL2_STATUS__tr_ready__ready 1
+#define R_SERIAL2_STATUS__rxd__BITNR 4
+#define R_SERIAL2_STATUS__rxd__WIDTH 1
+#define R_SERIAL2_STATUS__overrun__BITNR 3
+#define R_SERIAL2_STATUS__overrun__WIDTH 1
+#define R_SERIAL2_STATUS__overrun__no 0
+#define R_SERIAL2_STATUS__overrun__yes 1
+#define R_SERIAL2_STATUS__par_err__BITNR 2
+#define R_SERIAL2_STATUS__par_err__WIDTH 1
+#define R_SERIAL2_STATUS__par_err__no 0
+#define R_SERIAL2_STATUS__par_err__yes 1
+#define R_SERIAL2_STATUS__framing_err__BITNR 1
+#define R_SERIAL2_STATUS__framing_err__WIDTH 1
+#define R_SERIAL2_STATUS__framing_err__no 0
+#define R_SERIAL2_STATUS__framing_err__yes 1
+#define R_SERIAL2_STATUS__data_avail__BITNR 0
+#define R_SERIAL2_STATUS__data_avail__WIDTH 1
+#define R_SERIAL2_STATUS__data_avail__no 0
+#define R_SERIAL2_STATUS__data_avail__yes 1
+
+#define R_SERIAL2_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000070)
+#define R_SERIAL2_REC_DATA__data_in__BITNR 0
+#define R_SERIAL2_REC_DATA__data_in__WIDTH 8
+
+#define R_SERIAL2_XOFF (IO_TYPECAST_UDWORD 0xb0000074)
+#define R_SERIAL2_XOFF__tx_stop__BITNR 9
+#define R_SERIAL2_XOFF__tx_stop__WIDTH 1
+#define R_SERIAL2_XOFF__tx_stop__enable 0
+#define R_SERIAL2_XOFF__tx_stop__stop 1
+#define R_SERIAL2_XOFF__auto_xoff__BITNR 8
+#define R_SERIAL2_XOFF__auto_xoff__WIDTH 1
+#define R_SERIAL2_XOFF__auto_xoff__disable 0
+#define R_SERIAL2_XOFF__auto_xoff__enable 1
+#define R_SERIAL2_XOFF__xoff_char__BITNR 0
+#define R_SERIAL2_XOFF__xoff_char__WIDTH 8
+
+#define R_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
+#define R_SERIAL3_CTRL__tr_baud__BITNR 28
+#define R_SERIAL3_CTRL__tr_baud__WIDTH 4
+#define R_SERIAL3_CTRL__tr_baud__c300Hz 0
+#define R_SERIAL3_CTRL__tr_baud__c600Hz 1
+#define R_SERIAL3_CTRL__tr_baud__c1200Hz 2
+#define R_SERIAL3_CTRL__tr_baud__c2400Hz 3
+#define R_SERIAL3_CTRL__tr_baud__c4800Hz 4
+#define R_SERIAL3_CTRL__tr_baud__c9600Hz 5
+#define R_SERIAL3_CTRL__tr_baud__c19k2Hz 6
+#define R_SERIAL3_CTRL__tr_baud__c38k4Hz 7
+#define R_SERIAL3_CTRL__tr_baud__c57k6Hz 8
+#define R_SERIAL3_CTRL__tr_baud__c115k2Hz 9
+#define R_SERIAL3_CTRL__tr_baud__c230k4Hz 10
+#define R_SERIAL3_CTRL__tr_baud__c460k8Hz 11
+#define R_SERIAL3_CTRL__tr_baud__c921k6Hz 12
+#define R_SERIAL3_CTRL__tr_baud__c1843k2Hz 13
+#define R_SERIAL3_CTRL__tr_baud__c6250kHz 14
+#define R_SERIAL3_CTRL__tr_baud__reserved 15
+#define R_SERIAL3_CTRL__rec_baud__BITNR 24
+#define R_SERIAL3_CTRL__rec_baud__WIDTH 4
+#define R_SERIAL3_CTRL__rec_baud__c300Hz 0
+#define R_SERIAL3_CTRL__rec_baud__c600Hz 1
+#define R_SERIAL3_CTRL__rec_baud__c1200Hz 2
+#define R_SERIAL3_CTRL__rec_baud__c2400Hz 3
+#define R_SERIAL3_CTRL__rec_baud__c4800Hz 4
+#define R_SERIAL3_CTRL__rec_baud__c9600Hz 5
+#define R_SERIAL3_CTRL__rec_baud__c19k2Hz 6
+#define R_SERIAL3_CTRL__rec_baud__c38k4Hz 7
+#define R_SERIAL3_CTRL__rec_baud__c57k6Hz 8
+#define R_SERIAL3_CTRL__rec_baud__c115k2Hz 9
+#define R_SERIAL3_CTRL__rec_baud__c230k4Hz 10
+#define R_SERIAL3_CTRL__rec_baud__c460k8Hz 11
+#define R_SERIAL3_CTRL__rec_baud__c921k6Hz 12
+#define R_SERIAL3_CTRL__rec_baud__c1843k2Hz 13
+#define R_SERIAL3_CTRL__rec_baud__c6250kHz 14
+#define R_SERIAL3_CTRL__rec_baud__reserved 15
+#define R_SERIAL3_CTRL__dma_err__BITNR 23
+#define R_SERIAL3_CTRL__dma_err__WIDTH 1
+#define R_SERIAL3_CTRL__dma_err__stop 0
+#define R_SERIAL3_CTRL__dma_err__ignore 1
+#define R_SERIAL3_CTRL__rec_enable__BITNR 22
+#define R_SERIAL3_CTRL__rec_enable__WIDTH 1
+#define R_SERIAL3_CTRL__rec_enable__disable 0
+#define R_SERIAL3_CTRL__rec_enable__enable 1
+#define R_SERIAL3_CTRL__rts___BITNR 21
+#define R_SERIAL3_CTRL__rts___WIDTH 1
+#define R_SERIAL3_CTRL__rts___active 0
+#define R_SERIAL3_CTRL__rts___inactive 1
+#define R_SERIAL3_CTRL__sampling__BITNR 20
+#define R_SERIAL3_CTRL__sampling__WIDTH 1
+#define R_SERIAL3_CTRL__sampling__middle 0
+#define R_SERIAL3_CTRL__sampling__majority 1
+#define R_SERIAL3_CTRL__rec_stick_par__BITNR 19
+#define R_SERIAL3_CTRL__rec_stick_par__WIDTH 1
+#define R_SERIAL3_CTRL__rec_stick_par__normal 0
+#define R_SERIAL3_CTRL__rec_stick_par__stick 1
+#define R_SERIAL3_CTRL__rec_par__BITNR 18
+#define R_SERIAL3_CTRL__rec_par__WIDTH 1
+#define R_SERIAL3_CTRL__rec_par__even 0
+#define R_SERIAL3_CTRL__rec_par__odd 1
+#define R_SERIAL3_CTRL__rec_par_en__BITNR 17
+#define R_SERIAL3_CTRL__rec_par_en__WIDTH 1
+#define R_SERIAL3_CTRL__rec_par_en__disable 0
+#define R_SERIAL3_CTRL__rec_par_en__enable 1
+#define R_SERIAL3_CTRL__rec_bitnr__BITNR 16
+#define R_SERIAL3_CTRL__rec_bitnr__WIDTH 1
+#define R_SERIAL3_CTRL__rec_bitnr__rec_8bit 0
+#define R_SERIAL3_CTRL__rec_bitnr__rec_7bit 1
+#define R_SERIAL3_CTRL__txd__BITNR 15
+#define R_SERIAL3_CTRL__txd__WIDTH 1
+#define R_SERIAL3_CTRL__tr_enable__BITNR 14
+#define R_SERIAL3_CTRL__tr_enable__WIDTH 1
+#define R_SERIAL3_CTRL__tr_enable__disable 0
+#define R_SERIAL3_CTRL__tr_enable__enable 1
+#define R_SERIAL3_CTRL__auto_cts__BITNR 13
+#define R_SERIAL3_CTRL__auto_cts__WIDTH 1
+#define R_SERIAL3_CTRL__auto_cts__disabled 0
+#define R_SERIAL3_CTRL__auto_cts__active 1
+#define R_SERIAL3_CTRL__stop_bits__BITNR 12
+#define R_SERIAL3_CTRL__stop_bits__WIDTH 1
+#define R_SERIAL3_CTRL__stop_bits__one_bit 0
+#define R_SERIAL3_CTRL__stop_bits__two_bits 1
+#define R_SERIAL3_CTRL__tr_stick_par__BITNR 11
+#define R_SERIAL3_CTRL__tr_stick_par__WIDTH 1
+#define R_SERIAL3_CTRL__tr_stick_par__normal 0
+#define R_SERIAL3_CTRL__tr_stick_par__stick 1
+#define R_SERIAL3_CTRL__tr_par__BITNR 10
+#define R_SERIAL3_CTRL__tr_par__WIDTH 1
+#define R_SERIAL3_CTRL__tr_par__even 0
+#define R_SERIAL3_CTRL__tr_par__odd 1
+#define R_SERIAL3_CTRL__tr_par_en__BITNR 9
+#define R_SERIAL3_CTRL__tr_par_en__WIDTH 1
+#define R_SERIAL3_CTRL__tr_par_en__disable 0
+#define R_SERIAL3_CTRL__tr_par_en__enable 1
+#define R_SERIAL3_CTRL__tr_bitnr__BITNR 8
+#define R_SERIAL3_CTRL__tr_bitnr__WIDTH 1
+#define R_SERIAL3_CTRL__tr_bitnr__tr_8bit 0
+#define R_SERIAL3_CTRL__tr_bitnr__tr_7bit 1
+#define R_SERIAL3_CTRL__data_out__BITNR 0
+#define R_SERIAL3_CTRL__data_out__WIDTH 8
+
+#define R_SERIAL3_BAUD (IO_TYPECAST_BYTE 0xb000007b)
+#define R_SERIAL3_BAUD__tr_baud__BITNR 4
+#define R_SERIAL3_BAUD__tr_baud__WIDTH 4
+#define R_SERIAL3_BAUD__tr_baud__c300Hz 0
+#define R_SERIAL3_BAUD__tr_baud__c600Hz 1
+#define R_SERIAL3_BAUD__tr_baud__c1200Hz 2
+#define R_SERIAL3_BAUD__tr_baud__c2400Hz 3
+#define R_SERIAL3_BAUD__tr_baud__c4800Hz 4
+#define R_SERIAL3_BAUD__tr_baud__c9600Hz 5
+#define R_SERIAL3_BAUD__tr_baud__c19k2Hz 6
+#define R_SERIAL3_BAUD__tr_baud__c38k4Hz 7
+#define R_SERIAL3_BAUD__tr_baud__c57k6Hz 8
+#define R_SERIAL3_BAUD__tr_baud__c115k2Hz 9
+#define R_SERIAL3_BAUD__tr_baud__c230k4Hz 10
+#define R_SERIAL3_BAUD__tr_baud__c460k8Hz 11
+#define R_SERIAL3_BAUD__tr_baud__c921k6Hz 12
+#define R_SERIAL3_BAUD__tr_baud__c1843k2Hz 13
+#define R_SERIAL3_BAUD__tr_baud__c6250kHz 14
+#define R_SERIAL3_BAUD__tr_baud__reserved 15
+#define R_SERIAL3_BAUD__rec_baud__BITNR 0
+#define R_SERIAL3_BAUD__rec_baud__WIDTH 4
+#define R_SERIAL3_BAUD__rec_baud__c300Hz 0
+#define R_SERIAL3_BAUD__rec_baud__c600Hz 1
+#define R_SERIAL3_BAUD__rec_baud__c1200Hz 2
+#define R_SERIAL3_BAUD__rec_baud__c2400Hz 3
+#define R_SERIAL3_BAUD__rec_baud__c4800Hz 4
+#define R_SERIAL3_BAUD__rec_baud__c9600Hz 5
+#define R_SERIAL3_BAUD__rec_baud__c19k2Hz 6
+#define R_SERIAL3_BAUD__rec_baud__c38k4Hz 7
+#define R_SERIAL3_BAUD__rec_baud__c57k6Hz 8
+#define R_SERIAL3_BAUD__rec_baud__c115k2Hz 9
+#define R_SERIAL3_BAUD__rec_baud__c230k4Hz 10
+#define R_SERIAL3_BAUD__rec_baud__c460k8Hz 11
+#define R_SERIAL3_BAUD__rec_baud__c921k6Hz 12
+#define R_SERIAL3_BAUD__rec_baud__c1843k2Hz 13
+#define R_SERIAL3_BAUD__rec_baud__c6250kHz 14
+#define R_SERIAL3_BAUD__rec_baud__reserved 15
+
+#define R_SERIAL3_REC_CTRL (IO_TYPECAST_BYTE 0xb000007a)
+#define R_SERIAL3_REC_CTRL__dma_err__BITNR 7
+#define R_SERIAL3_REC_CTRL__dma_err__WIDTH 1
+#define R_SERIAL3_REC_CTRL__dma_err__stop 0
+#define R_SERIAL3_REC_CTRL__dma_err__ignore 1
+#define R_SERIAL3_REC_CTRL__rec_enable__BITNR 6
+#define R_SERIAL3_REC_CTRL__rec_enable__WIDTH 1
+#define R_SERIAL3_REC_CTRL__rec_enable__disable 0
+#define R_SERIAL3_REC_CTRL__rec_enable__enable 1
+#define R_SERIAL3_REC_CTRL__rts___BITNR 5
+#define R_SERIAL3_REC_CTRL__rts___WIDTH 1
+#define R_SERIAL3_REC_CTRL__rts___active 0
+#define R_SERIAL3_REC_CTRL__rts___inactive 1
+#define R_SERIAL3_REC_CTRL__sampling__BITNR 4
+#define R_SERIAL3_REC_CTRL__sampling__WIDTH 1
+#define R_SERIAL3_REC_CTRL__sampling__middle 0
+#define R_SERIAL3_REC_CTRL__sampling__majority 1
+#define R_SERIAL3_REC_CTRL__rec_stick_par__BITNR 3
+#define R_SERIAL3_REC_CTRL__rec_stick_par__WIDTH 1
+#define R_SERIAL3_REC_CTRL__rec_stick_par__normal 0
+#define R_SERIAL3_REC_CTRL__rec_stick_par__stick 1
+#define R_SERIAL3_REC_CTRL__rec_par__BITNR 2
+#define R_SERIAL3_REC_CTRL__rec_par__WIDTH 1
+#define R_SERIAL3_REC_CTRL__rec_par__even 0
+#define R_SERIAL3_REC_CTRL__rec_par__odd 1
+#define R_SERIAL3_REC_CTRL__rec_par_en__BITNR 1
+#define R_SERIAL3_REC_CTRL__rec_par_en__WIDTH 1
+#define R_SERIAL3_REC_CTRL__rec_par_en__disable 0
+#define R_SERIAL3_REC_CTRL__rec_par_en__enable 1
+#define R_SERIAL3_REC_CTRL__rec_bitnr__BITNR 0
+#define R_SERIAL3_REC_CTRL__rec_bitnr__WIDTH 1
+#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_8bit 0
+#define R_SERIAL3_REC_CTRL__rec_bitnr__rec_7bit 1
+
+#define R_SERIAL3_TR_CTRL (IO_TYPECAST_BYTE 0xb0000079)
+#define R_SERIAL3_TR_CTRL__txd__BITNR 7
+#define R_SERIAL3_TR_CTRL__txd__WIDTH 1
+#define R_SERIAL3_TR_CTRL__tr_enable__BITNR 6
+#define R_SERIAL3_TR_CTRL__tr_enable__WIDTH 1
+#define R_SERIAL3_TR_CTRL__tr_enable__disable 0
+#define R_SERIAL3_TR_CTRL__tr_enable__enable 1
+#define R_SERIAL3_TR_CTRL__auto_cts__BITNR 5
+#define R_SERIAL3_TR_CTRL__auto_cts__WIDTH 1
+#define R_SERIAL3_TR_CTRL__auto_cts__disabled 0
+#define R_SERIAL3_TR_CTRL__auto_cts__active 1
+#define R_SERIAL3_TR_CTRL__stop_bits__BITNR 4
+#define R_SERIAL3_TR_CTRL__stop_bits__WIDTH 1
+#define R_SERIAL3_TR_CTRL__stop_bits__one_bit 0
+#define R_SERIAL3_TR_CTRL__stop_bits__two_bits 1
+#define R_SERIAL3_TR_CTRL__tr_stick_par__BITNR 3
+#define R_SERIAL3_TR_CTRL__tr_stick_par__WIDTH 1
+#define R_SERIAL3_TR_CTRL__tr_stick_par__normal 0
+#define R_SERIAL3_TR_CTRL__tr_stick_par__stick 1
+#define R_SERIAL3_TR_CTRL__tr_par__BITNR 2
+#define R_SERIAL3_TR_CTRL__tr_par__WIDTH 1
+#define R_SERIAL3_TR_CTRL__tr_par__even 0
+#define R_SERIAL3_TR_CTRL__tr_par__odd 1
+#define R_SERIAL3_TR_CTRL__tr_par_en__BITNR 1
+#define R_SERIAL3_TR_CTRL__tr_par_en__WIDTH 1
+#define R_SERIAL3_TR_CTRL__tr_par_en__disable 0
+#define R_SERIAL3_TR_CTRL__tr_par_en__enable 1
+#define R_SERIAL3_TR_CTRL__tr_bitnr__BITNR 0
+#define R_SERIAL3_TR_CTRL__tr_bitnr__WIDTH 1
+#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_8bit 0
+#define R_SERIAL3_TR_CTRL__tr_bitnr__tr_7bit 1
+
+#define R_SERIAL3_TR_DATA (IO_TYPECAST_BYTE 0xb0000078)
+#define R_SERIAL3_TR_DATA__data_out__BITNR 0
+#define R_SERIAL3_TR_DATA__data_out__WIDTH 8
+
+#define R_SERIAL3_READ (IO_TYPECAST_RO_UDWORD 0xb0000078)
+#define R_SERIAL3_READ__xoff_detect__BITNR 15
+#define R_SERIAL3_READ__xoff_detect__WIDTH 1
+#define R_SERIAL3_READ__xoff_detect__no_xoff 0
+#define R_SERIAL3_READ__xoff_detect__xoff 1
+#define R_SERIAL3_READ__cts___BITNR 14
+#define R_SERIAL3_READ__cts___WIDTH 1
+#define R_SERIAL3_READ__cts___active 0
+#define R_SERIAL3_READ__cts___inactive 1
+#define R_SERIAL3_READ__tr_ready__BITNR 13
+#define R_SERIAL3_READ__tr_ready__WIDTH 1
+#define R_SERIAL3_READ__tr_ready__full 0
+#define R_SERIAL3_READ__tr_ready__ready 1
+#define R_SERIAL3_READ__rxd__BITNR 12
+#define R_SERIAL3_READ__rxd__WIDTH 1
+#define R_SERIAL3_READ__overrun__BITNR 11
+#define R_SERIAL3_READ__overrun__WIDTH 1
+#define R_SERIAL3_READ__overrun__no 0
+#define R_SERIAL3_READ__overrun__yes 1
+#define R_SERIAL3_READ__par_err__BITNR 10
+#define R_SERIAL3_READ__par_err__WIDTH 1
+#define R_SERIAL3_READ__par_err__no 0
+#define R_SERIAL3_READ__par_err__yes 1
+#define R_SERIAL3_READ__framing_err__BITNR 9
+#define R_SERIAL3_READ__framing_err__WIDTH 1
+#define R_SERIAL3_READ__framing_err__no 0
+#define R_SERIAL3_READ__framing_err__yes 1
+#define R_SERIAL3_READ__data_avail__BITNR 8
+#define R_SERIAL3_READ__data_avail__WIDTH 1
+#define R_SERIAL3_READ__data_avail__no 0
+#define R_SERIAL3_READ__data_avail__yes 1
+#define R_SERIAL3_READ__data_in__BITNR 0
+#define R_SERIAL3_READ__data_in__WIDTH 8
+
+#define R_SERIAL3_STATUS (IO_TYPECAST_RO_BYTE 0xb0000079)
+#define R_SERIAL3_STATUS__xoff_detect__BITNR 7
+#define R_SERIAL3_STATUS__xoff_detect__WIDTH 1
+#define R_SERIAL3_STATUS__xoff_detect__no_xoff 0
+#define R_SERIAL3_STATUS__xoff_detect__xoff 1
+#define R_SERIAL3_STATUS__cts___BITNR 6
+#define R_SERIAL3_STATUS__cts___WIDTH 1
+#define R_SERIAL3_STATUS__cts___active 0
+#define R_SERIAL3_STATUS__cts___inactive 1
+#define R_SERIAL3_STATUS__tr_ready__BITNR 5
+#define R_SERIAL3_STATUS__tr_ready__WIDTH 1
+#define R_SERIAL3_STATUS__tr_ready__full 0
+#define R_SERIAL3_STATUS__tr_ready__ready 1
+#define R_SERIAL3_STATUS__rxd__BITNR 4
+#define R_SERIAL3_STATUS__rxd__WIDTH 1
+#define R_SERIAL3_STATUS__overrun__BITNR 3
+#define R_SERIAL3_STATUS__overrun__WIDTH 1
+#define R_SERIAL3_STATUS__overrun__no 0
+#define R_SERIAL3_STATUS__overrun__yes 1
+#define R_SERIAL3_STATUS__par_err__BITNR 2
+#define R_SERIAL3_STATUS__par_err__WIDTH 1
+#define R_SERIAL3_STATUS__par_err__no 0
+#define R_SERIAL3_STATUS__par_err__yes 1
+#define R_SERIAL3_STATUS__framing_err__BITNR 1
+#define R_SERIAL3_STATUS__framing_err__WIDTH 1
+#define R_SERIAL3_STATUS__framing_err__no 0
+#define R_SERIAL3_STATUS__framing_err__yes 1
+#define R_SERIAL3_STATUS__data_avail__BITNR 0
+#define R_SERIAL3_STATUS__data_avail__WIDTH 1
+#define R_SERIAL3_STATUS__data_avail__no 0
+#define R_SERIAL3_STATUS__data_avail__yes 1
+
+#define R_SERIAL3_REC_DATA (IO_TYPECAST_RO_BYTE 0xb0000078)
+#define R_SERIAL3_REC_DATA__data_in__BITNR 0
+#define R_SERIAL3_REC_DATA__data_in__WIDTH 8
+
+#define R_SERIAL3_XOFF (IO_TYPECAST_UDWORD 0xb000007c)
+#define R_SERIAL3_XOFF__tx_stop__BITNR 9
+#define R_SERIAL3_XOFF__tx_stop__WIDTH 1
+#define R_SERIAL3_XOFF__tx_stop__enable 0
+#define R_SERIAL3_XOFF__tx_stop__stop 1
+#define R_SERIAL3_XOFF__auto_xoff__BITNR 8
+#define R_SERIAL3_XOFF__auto_xoff__WIDTH 1
+#define R_SERIAL3_XOFF__auto_xoff__disable 0
+#define R_SERIAL3_XOFF__auto_xoff__enable 1
+#define R_SERIAL3_XOFF__xoff_char__BITNR 0
+#define R_SERIAL3_XOFF__xoff_char__WIDTH 8
+
+#define R_ALT_SER_BAUDRATE (IO_TYPECAST_UDWORD 0xb000005c)
+#define R_ALT_SER_BAUDRATE__ser3_tr__BITNR 28
+#define R_ALT_SER_BAUDRATE__ser3_tr__WIDTH 2
+#define R_ALT_SER_BAUDRATE__ser3_tr__normal 0
+#define R_ALT_SER_BAUDRATE__ser3_tr__prescale 1
+#define R_ALT_SER_BAUDRATE__ser3_tr__extern 2
+#define R_ALT_SER_BAUDRATE__ser3_tr__timer 3
+#define R_ALT_SER_BAUDRATE__ser3_rec__BITNR 24
+#define R_ALT_SER_BAUDRATE__ser3_rec__WIDTH 2
+#define R_ALT_SER_BAUDRATE__ser3_rec__normal 0
+#define R_ALT_SER_BAUDRATE__ser3_rec__prescale 1
+#define R_ALT_SER_BAUDRATE__ser3_rec__extern 2
+#define R_ALT_SER_BAUDRATE__ser3_rec__timer 3
+#define R_ALT_SER_BAUDRATE__ser2_tr__BITNR 20
+#define R_ALT_SER_BAUDRATE__ser2_tr__WIDTH 2
+#define R_ALT_SER_BAUDRATE__ser2_tr__normal 0
+#define R_ALT_SER_BAUDRATE__ser2_tr__prescale 1
+#define R_ALT_SER_BAUDRATE__ser2_tr__extern 2
+#define R_ALT_SER_BAUDRATE__ser2_tr__timer 3
+#define R_ALT_SER_BAUDRATE__ser2_rec__BITNR 16
+#define R_ALT_SER_BAUDRATE__ser2_rec__WIDTH 2
+#define R_ALT_SER_BAUDRATE__ser2_rec__normal 0
+#define R_ALT_SER_BAUDRATE__ser2_rec__prescale 1
+#define R_ALT_SER_BAUDRATE__ser2_rec__extern 2
+#define R_ALT_SER_BAUDRATE__ser2_rec__timer 3
+#define R_ALT_SER_BAUDRATE__ser1_tr__BITNR 12
+#define R_ALT_SER_BAUDRATE__ser1_tr__WIDTH 2
+#define R_ALT_SER_BAUDRATE__ser1_tr__normal 0
+#define R_ALT_SER_BAUDRATE__ser1_tr__prescale 1
+#define R_ALT_SER_BAUDRATE__ser1_tr__extern 2
+#define R_ALT_SER_BAUDRATE__ser1_tr__timer 3
+#define R_ALT_SER_BAUDRATE__ser1_rec__BITNR 8
+#define R_ALT_SER_BAUDRATE__ser1_rec__WIDTH 2
+#define R_ALT_SER_BAUDRATE__ser1_rec__normal 0
+#define R_ALT_SER_BAUDRATE__ser1_rec__prescale 1
+#define R_ALT_SER_BAUDRATE__ser1_rec__extern 2
+#define R_ALT_SER_BAUDRATE__ser1_rec__timer 3
+#define R_ALT_SER_BAUDRATE__ser0_tr__BITNR 4
+#define R_ALT_SER_BAUDRATE__ser0_tr__WIDTH 2
+#define R_ALT_SER_BAUDRATE__ser0_tr__normal 0
+#define R_ALT_SER_BAUDRATE__ser0_tr__prescale 1
+#define R_ALT_SER_BAUDRATE__ser0_tr__extern 2
+#define R_ALT_SER_BAUDRATE__ser0_tr__timer 3
+#define R_ALT_SER_BAUDRATE__ser0_rec__BITNR 0
+#define R_ALT_SER_BAUDRATE__ser0_rec__WIDTH 2
+#define R_ALT_SER_BAUDRATE__ser0_rec__normal 0
+#define R_ALT_SER_BAUDRATE__ser0_rec__prescale 1
+#define R_ALT_SER_BAUDRATE__ser0_rec__extern 2
+#define R_ALT_SER_BAUDRATE__ser0_rec__timer 3
+
+/*
+!* Network interface registers
+!*/
+
+#define R_NETWORK_SA_0 (IO_TYPECAST_UDWORD 0xb0000080)
+#define R_NETWORK_SA_0__ma0_low__BITNR 0
+#define R_NETWORK_SA_0__ma0_low__WIDTH 32
+
+#define R_NETWORK_SA_1 (IO_TYPECAST_UDWORD 0xb0000084)
+#define R_NETWORK_SA_1__ma1_low__BITNR 16
+#define R_NETWORK_SA_1__ma1_low__WIDTH 16
+#define R_NETWORK_SA_1__ma0_high__BITNR 0
+#define R_NETWORK_SA_1__ma0_high__WIDTH 16
+
+#define R_NETWORK_SA_2 (IO_TYPECAST_UDWORD 0xb0000088)
+#define R_NETWORK_SA_2__ma1_high__BITNR 0
+#define R_NETWORK_SA_2__ma1_high__WIDTH 32
+
+#define R_NETWORK_GA_0 (IO_TYPECAST_UDWORD 0xb000008c)
+#define R_NETWORK_GA_0__ga_low__BITNR 0
+#define R_NETWORK_GA_0__ga_low__WIDTH 32
+
+#define R_NETWORK_GA_1 (IO_TYPECAST_UDWORD 0xb0000090)
+#define R_NETWORK_GA_1__ga_high__BITNR 0
+#define R_NETWORK_GA_1__ga_high__WIDTH 32
+
+#define R_NETWORK_REC_CONFIG (IO_TYPECAST_UDWORD 0xb0000094)
+#define R_NETWORK_REC_CONFIG__max_size__BITNR 10
+#define R_NETWORK_REC_CONFIG__max_size__WIDTH 1
+#define R_NETWORK_REC_CONFIG__max_size__size1518 0
+#define R_NETWORK_REC_CONFIG__max_size__size1522 1
+#define R_NETWORK_REC_CONFIG__duplex__BITNR 9
+#define R_NETWORK_REC_CONFIG__duplex__WIDTH 1
+#define R_NETWORK_REC_CONFIG__duplex__full 1
+#define R_NETWORK_REC_CONFIG__duplex__half 0
+#define R_NETWORK_REC_CONFIG__bad_crc__BITNR 8
+#define R_NETWORK_REC_CONFIG__bad_crc__WIDTH 1
+#define R_NETWORK_REC_CONFIG__bad_crc__receive 1
+#define R_NETWORK_REC_CONFIG__bad_crc__discard 0
+#define R_NETWORK_REC_CONFIG__oversize__BITNR 7
+#define R_NETWORK_REC_CONFIG__oversize__WIDTH 1
+#define R_NETWORK_REC_CONFIG__oversize__receive 1
+#define R_NETWORK_REC_CONFIG__oversize__discard 0
+#define R_NETWORK_REC_CONFIG__undersize__BITNR 6
+#define R_NETWORK_REC_CONFIG__undersize__WIDTH 1
+#define R_NETWORK_REC_CONFIG__undersize__receive 1
+#define R_NETWORK_REC_CONFIG__undersize__discard 0
+#define R_NETWORK_REC_CONFIG__all_roots__BITNR 5
+#define R_NETWORK_REC_CONFIG__all_roots__WIDTH 1
+#define R_NETWORK_REC_CONFIG__all_roots__receive 1
+#define R_NETWORK_REC_CONFIG__all_roots__discard 0
+#define R_NETWORK_REC_CONFIG__tr_broadcast__BITNR 4
+#define R_NETWORK_REC_CONFIG__tr_broadcast__WIDTH 1
+#define R_NETWORK_REC_CONFIG__tr_broadcast__receive 1
+#define R_NETWORK_REC_CONFIG__tr_broadcast__discard 0
+#define R_NETWORK_REC_CONFIG__broadcast__BITNR 3
+#define R_NETWORK_REC_CONFIG__broadcast__WIDTH 1
+#define R_NETWORK_REC_CONFIG__broadcast__receive 1
+#define R_NETWORK_REC_CONFIG__broadcast__discard 0
+#define R_NETWORK_REC_CONFIG__individual__BITNR 2
+#define R_NETWORK_REC_CONFIG__individual__WIDTH 1
+#define R_NETWORK_REC_CONFIG__individual__receive 1
+#define R_NETWORK_REC_CONFIG__individual__discard 0
+#define R_NETWORK_REC_CONFIG__ma1__BITNR 1
+#define R_NETWORK_REC_CONFIG__ma1__WIDTH 1
+#define R_NETWORK_REC_CONFIG__ma1__enable 1
+#define R_NETWORK_REC_CONFIG__ma1__disable 0
+#define R_NETWORK_REC_CONFIG__ma0__BITNR 0
+#define R_NETWORK_REC_CONFIG__ma0__WIDTH 1
+#define R_NETWORK_REC_CONFIG__ma0__enable 1
+#define R_NETWORK_REC_CONFIG__ma0__disable 0
+
+#define R_NETWORK_GEN_CONFIG (IO_TYPECAST_UDWORD 0xb0000098)
+#define R_NETWORK_GEN_CONFIG__loopback__BITNR 5
+#define R_NETWORK_GEN_CONFIG__loopback__WIDTH 1
+#define R_NETWORK_GEN_CONFIG__loopback__on 1
+#define R_NETWORK_GEN_CONFIG__loopback__off 0
+#define R_NETWORK_GEN_CONFIG__frame__BITNR 4
+#define R_NETWORK_GEN_CONFIG__frame__WIDTH 1
+#define R_NETWORK_GEN_CONFIG__frame__tokenr 1
+#define R_NETWORK_GEN_CONFIG__frame__ether 0
+#define R_NETWORK_GEN_CONFIG__vg__BITNR 3
+#define R_NETWORK_GEN_CONFIG__vg__WIDTH 1
+#define R_NETWORK_GEN_CONFIG__vg__on 1
+#define R_NETWORK_GEN_CONFIG__vg__off 0
+#define R_NETWORK_GEN_CONFIG__phy__BITNR 1
+#define R_NETWORK_GEN_CONFIG__phy__WIDTH 2
+#define R_NETWORK_GEN_CONFIG__phy__sni 0
+#define R_NETWORK_GEN_CONFIG__phy__mii_clk 1
+#define R_NETWORK_GEN_CONFIG__phy__mii_err 2
+#define R_NETWORK_GEN_CONFIG__phy__mii_req 3
+#define R_NETWORK_GEN_CONFIG__enable__BITNR 0
+#define R_NETWORK_GEN_CONFIG__enable__WIDTH 1
+#define R_NETWORK_GEN_CONFIG__enable__on 1
+#define R_NETWORK_GEN_CONFIG__enable__off 0
+
+#define R_NETWORK_TR_CTRL (IO_TYPECAST_UDWORD 0xb000009c)
+#define R_NETWORK_TR_CTRL__clr_error__BITNR 8
+#define R_NETWORK_TR_CTRL__clr_error__WIDTH 1
+#define R_NETWORK_TR_CTRL__clr_error__clr 1
+#define R_NETWORK_TR_CTRL__clr_error__nop 0
+#define R_NETWORK_TR_CTRL__delay__BITNR 5
+#define R_NETWORK_TR_CTRL__delay__WIDTH 1
+#define R_NETWORK_TR_CTRL__delay__d2us 1
+#define R_NETWORK_TR_CTRL__delay__none 0
+#define R_NETWORK_TR_CTRL__cancel__BITNR 4
+#define R_NETWORK_TR_CTRL__cancel__WIDTH 1
+#define R_NETWORK_TR_CTRL__cancel__do 1
+#define R_NETWORK_TR_CTRL__cancel__dont 0
+#define R_NETWORK_TR_CTRL__cd__BITNR 3
+#define R_NETWORK_TR_CTRL__cd__WIDTH 1
+#define R_NETWORK_TR_CTRL__cd__enable 0
+#define R_NETWORK_TR_CTRL__cd__disable 1
+#define R_NETWORK_TR_CTRL__cd__ack_col 0
+#define R_NETWORK_TR_CTRL__cd__ack_crs 1
+#define R_NETWORK_TR_CTRL__retry__BITNR 2
+#define R_NETWORK_TR_CTRL__retry__WIDTH 1
+#define R_NETWORK_TR_CTRL__retry__enable 0
+#define R_NETWORK_TR_CTRL__retry__disable 1
+#define R_NETWORK_TR_CTRL__pad__BITNR 1
+#define R_NETWORK_TR_CTRL__pad__WIDTH 1
+#define R_NETWORK_TR_CTRL__pad__enable 1
+#define R_NETWORK_TR_CTRL__pad__disable 0
+#define R_NETWORK_TR_CTRL__crc__BITNR 0
+#define R_NETWORK_TR_CTRL__crc__WIDTH 1
+#define R_NETWORK_TR_CTRL__crc__enable 0
+#define R_NETWORK_TR_CTRL__crc__disable 1
+
+#define R_NETWORK_MGM_CTRL (IO_TYPECAST_UDWORD 0xb00000a0)
+#define R_NETWORK_MGM_CTRL__txd_pins__BITNR 4
+#define R_NETWORK_MGM_CTRL__txd_pins__WIDTH 4
+#define R_NETWORK_MGM_CTRL__txer_pin__BITNR 3
+#define R_NETWORK_MGM_CTRL__txer_pin__WIDTH 1
+#define R_NETWORK_MGM_CTRL__mdck__BITNR 2
+#define R_NETWORK_MGM_CTRL__mdck__WIDTH 1
+#define R_NETWORK_MGM_CTRL__mdoe__BITNR 1
+#define R_NETWORK_MGM_CTRL__mdoe__WIDTH 1
+#define R_NETWORK_MGM_CTRL__mdoe__enable 1
+#define R_NETWORK_MGM_CTRL__mdoe__disable 0
+#define R_NETWORK_MGM_CTRL__mdio__BITNR 0
+#define R_NETWORK_MGM_CTRL__mdio__WIDTH 1
+
+#define R_NETWORK_STAT (IO_TYPECAST_RO_UDWORD 0xb00000a0)
+#define R_NETWORK_STAT__rxd_pins__BITNR 4
+#define R_NETWORK_STAT__rxd_pins__WIDTH 4
+#define R_NETWORK_STAT__rxer__BITNR 3
+#define R_NETWORK_STAT__rxer__WIDTH 1
+#define R_NETWORK_STAT__underrun__BITNR 2
+#define R_NETWORK_STAT__underrun__WIDTH 1
+#define R_NETWORK_STAT__underrun__yes 1
+#define R_NETWORK_STAT__underrun__no 0
+#define R_NETWORK_STAT__exc_col__BITNR 1
+#define R_NETWORK_STAT__exc_col__WIDTH 1
+#define R_NETWORK_STAT__exc_col__yes 1
+#define R_NETWORK_STAT__exc_col__no 0
+#define R_NETWORK_STAT__mdio__BITNR 0
+#define R_NETWORK_STAT__mdio__WIDTH 1
+
+#define R_REC_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a4)
+#define R_REC_COUNTERS__congestion__BITNR 24
+#define R_REC_COUNTERS__congestion__WIDTH 8
+#define R_REC_COUNTERS__oversize__BITNR 16
+#define R_REC_COUNTERS__oversize__WIDTH 8
+#define R_REC_COUNTERS__alignment_error__BITNR 8
+#define R_REC_COUNTERS__alignment_error__WIDTH 8
+#define R_REC_COUNTERS__crc_error__BITNR 0
+#define R_REC_COUNTERS__crc_error__WIDTH 8
+
+#define R_TR_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000a8)
+#define R_TR_COUNTERS__deferred__BITNR 24
+#define R_TR_COUNTERS__deferred__WIDTH 8
+#define R_TR_COUNTERS__late_col__BITNR 16
+#define R_TR_COUNTERS__late_col__WIDTH 8
+#define R_TR_COUNTERS__multiple_col__BITNR 8
+#define R_TR_COUNTERS__multiple_col__WIDTH 8
+#define R_TR_COUNTERS__single_col__BITNR 0
+#define R_TR_COUNTERS__single_col__WIDTH 8
+
+#define R_PHY_COUNTERS (IO_TYPECAST_RO_UDWORD 0xb00000ac)
+#define R_PHY_COUNTERS__sqe_test_error__BITNR 8
+#define R_PHY_COUNTERS__sqe_test_error__WIDTH 8
+#define R_PHY_COUNTERS__carrier_loss__BITNR 0
+#define R_PHY_COUNTERS__carrier_loss__WIDTH 8
+
+/*
+!* Parallel printer port registers
+!*/
+
+#define R_PAR0_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
+#define R_PAR0_CTRL_DATA__peri_int__BITNR 24
+#define R_PAR0_CTRL_DATA__peri_int__WIDTH 1
+#define R_PAR0_CTRL_DATA__peri_int__ack 1
+#define R_PAR0_CTRL_DATA__peri_int__nop 0
+#define R_PAR0_CTRL_DATA__oe__BITNR 20
+#define R_PAR0_CTRL_DATA__oe__WIDTH 1
+#define R_PAR0_CTRL_DATA__oe__enable 1
+#define R_PAR0_CTRL_DATA__oe__disable 0
+#define R_PAR0_CTRL_DATA__seli__BITNR 19
+#define R_PAR0_CTRL_DATA__seli__WIDTH 1
+#define R_PAR0_CTRL_DATA__seli__active 1
+#define R_PAR0_CTRL_DATA__seli__inactive 0
+#define R_PAR0_CTRL_DATA__autofd__BITNR 18
+#define R_PAR0_CTRL_DATA__autofd__WIDTH 1
+#define R_PAR0_CTRL_DATA__autofd__active 1
+#define R_PAR0_CTRL_DATA__autofd__inactive 0
+#define R_PAR0_CTRL_DATA__strb__BITNR 17
+#define R_PAR0_CTRL_DATA__strb__WIDTH 1
+#define R_PAR0_CTRL_DATA__strb__active 1
+#define R_PAR0_CTRL_DATA__strb__inactive 0
+#define R_PAR0_CTRL_DATA__init__BITNR 16
+#define R_PAR0_CTRL_DATA__init__WIDTH 1
+#define R_PAR0_CTRL_DATA__init__active 1
+#define R_PAR0_CTRL_DATA__init__inactive 0
+#define R_PAR0_CTRL_DATA__ecp_cmd__BITNR 8
+#define R_PAR0_CTRL_DATA__ecp_cmd__WIDTH 1
+#define R_PAR0_CTRL_DATA__ecp_cmd__command 1
+#define R_PAR0_CTRL_DATA__ecp_cmd__data 0
+#define R_PAR0_CTRL_DATA__data__BITNR 0
+#define R_PAR0_CTRL_DATA__data__WIDTH 8
+
+#define R_PAR0_CTRL (IO_TYPECAST_BYTE 0xb0000042)
+#define R_PAR0_CTRL__ctrl__BITNR 0
+#define R_PAR0_CTRL__ctrl__WIDTH 5
+
+#define R_PAR0_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
+#define R_PAR0_STATUS_DATA__mode__BITNR 29
+#define R_PAR0_STATUS_DATA__mode__WIDTH 3
+#define R_PAR0_STATUS_DATA__mode__manual 0
+#define R_PAR0_STATUS_DATA__mode__centronics 1
+#define R_PAR0_STATUS_DATA__mode__fastbyte 2
+#define R_PAR0_STATUS_DATA__mode__nibble 3
+#define R_PAR0_STATUS_DATA__mode__byte 4
+#define R_PAR0_STATUS_DATA__mode__ecp_fwd 5
+#define R_PAR0_STATUS_DATA__mode__ecp_rev 6
+#define R_PAR0_STATUS_DATA__mode__off 7
+#define R_PAR0_STATUS_DATA__mode__epp_wr1 5
+#define R_PAR0_STATUS_DATA__mode__epp_wr2 6
+#define R_PAR0_STATUS_DATA__mode__epp_wr3 7
+#define R_PAR0_STATUS_DATA__mode__epp_rd 0
+#define R_PAR0_STATUS_DATA__perr__BITNR 28
+#define R_PAR0_STATUS_DATA__perr__WIDTH 1
+#define R_PAR0_STATUS_DATA__perr__active 1
+#define R_PAR0_STATUS_DATA__perr__inactive 0
+#define R_PAR0_STATUS_DATA__ack__BITNR 27
+#define R_PAR0_STATUS_DATA__ack__WIDTH 1
+#define R_PAR0_STATUS_DATA__ack__active 0
+#define R_PAR0_STATUS_DATA__ack__inactive 1
+#define R_PAR0_STATUS_DATA__busy__BITNR 26
+#define R_PAR0_STATUS_DATA__busy__WIDTH 1
+#define R_PAR0_STATUS_DATA__busy__active 1
+#define R_PAR0_STATUS_DATA__busy__inactive 0
+#define R_PAR0_STATUS_DATA__fault__BITNR 25
+#define R_PAR0_STATUS_DATA__fault__WIDTH 1
+#define R_PAR0_STATUS_DATA__fault__active 0
+#define R_PAR0_STATUS_DATA__fault__inactive 1
+#define R_PAR0_STATUS_DATA__sel__BITNR 24
+#define R_PAR0_STATUS_DATA__sel__WIDTH 1
+#define R_PAR0_STATUS_DATA__sel__active 1
+#define R_PAR0_STATUS_DATA__sel__inactive 0
+#define R_PAR0_STATUS_DATA__ext_mode__BITNR 23
+#define R_PAR0_STATUS_DATA__ext_mode__WIDTH 1
+#define R_PAR0_STATUS_DATA__ext_mode__enable 1
+#define R_PAR0_STATUS_DATA__ext_mode__disable 0
+#define R_PAR0_STATUS_DATA__ecp_16__BITNR 22
+#define R_PAR0_STATUS_DATA__ecp_16__WIDTH 1
+#define R_PAR0_STATUS_DATA__ecp_16__active 1
+#define R_PAR0_STATUS_DATA__ecp_16__inactive 0
+#define R_PAR0_STATUS_DATA__tr_rdy__BITNR 17
+#define R_PAR0_STATUS_DATA__tr_rdy__WIDTH 1
+#define R_PAR0_STATUS_DATA__tr_rdy__ready 1
+#define R_PAR0_STATUS_DATA__tr_rdy__busy 0
+#define R_PAR0_STATUS_DATA__dav__BITNR 16
+#define R_PAR0_STATUS_DATA__dav__WIDTH 1
+#define R_PAR0_STATUS_DATA__dav__data 1
+#define R_PAR0_STATUS_DATA__dav__nodata 0
+#define R_PAR0_STATUS_DATA__ecp_cmd__BITNR 8
+#define R_PAR0_STATUS_DATA__ecp_cmd__WIDTH 1
+#define R_PAR0_STATUS_DATA__ecp_cmd__command 1
+#define R_PAR0_STATUS_DATA__ecp_cmd__data 0
+#define R_PAR0_STATUS_DATA__data__BITNR 0
+#define R_PAR0_STATUS_DATA__data__WIDTH 8
+
+#define R_PAR0_STATUS (IO_TYPECAST_RO_UWORD 0xb0000042)
+#define R_PAR0_STATUS__mode__BITNR 13
+#define R_PAR0_STATUS__mode__WIDTH 3
+#define R_PAR0_STATUS__mode__manual 0
+#define R_PAR0_STATUS__mode__centronics 1
+#define R_PAR0_STATUS__mode__fastbyte 2
+#define R_PAR0_STATUS__mode__nibble 3
+#define R_PAR0_STATUS__mode__byte 4
+#define R_PAR0_STATUS__mode__ecp_fwd 5
+#define R_PAR0_STATUS__mode__ecp_rev 6
+#define R_PAR0_STATUS__mode__off 7
+#define R_PAR0_STATUS__mode__epp_wr1 5
+#define R_PAR0_STATUS__mode__epp_wr2 6
+#define R_PAR0_STATUS__mode__epp_wr3 7
+#define R_PAR0_STATUS__mode__epp_rd 0
+#define R_PAR0_STATUS__perr__BITNR 12
+#define R_PAR0_STATUS__perr__WIDTH 1
+#define R_PAR0_STATUS__perr__active 1
+#define R_PAR0_STATUS__perr__inactive 0
+#define R_PAR0_STATUS__ack__BITNR 11
+#define R_PAR0_STATUS__ack__WIDTH 1
+#define R_PAR0_STATUS__ack__active 0
+#define R_PAR0_STATUS__ack__inactive 1
+#define R_PAR0_STATUS__busy__BITNR 10
+#define R_PAR0_STATUS__busy__WIDTH 1
+#define R_PAR0_STATUS__busy__active 1
+#define R_PAR0_STATUS__busy__inactive 0
+#define R_PAR0_STATUS__fault__BITNR 9
+#define R_PAR0_STATUS__fault__WIDTH 1
+#define R_PAR0_STATUS__fault__active 0
+#define R_PAR0_STATUS__fault__inactive 1
+#define R_PAR0_STATUS__sel__BITNR 8
+#define R_PAR0_STATUS__sel__WIDTH 1
+#define R_PAR0_STATUS__sel__active 1
+#define R_PAR0_STATUS__sel__inactive 0
+#define R_PAR0_STATUS__ext_mode__BITNR 7
+#define R_PAR0_STATUS__ext_mode__WIDTH 1
+#define R_PAR0_STATUS__ext_mode__enable 1
+#define R_PAR0_STATUS__ext_mode__disable 0
+#define R_PAR0_STATUS__ecp_16__BITNR 6
+#define R_PAR0_STATUS__ecp_16__WIDTH 1
+#define R_PAR0_STATUS__ecp_16__active 1
+#define R_PAR0_STATUS__ecp_16__inactive 0
+#define R_PAR0_STATUS__tr_rdy__BITNR 1
+#define R_PAR0_STATUS__tr_rdy__WIDTH 1
+#define R_PAR0_STATUS__tr_rdy__ready 1
+#define R_PAR0_STATUS__tr_rdy__busy 0
+#define R_PAR0_STATUS__dav__BITNR 0
+#define R_PAR0_STATUS__dav__WIDTH 1
+#define R_PAR0_STATUS__dav__data 1
+#define R_PAR0_STATUS__dav__nodata 0
+
+#define R_PAR_ECP16_DATA (IO_TYPECAST_UWORD 0xb0000040)
+#define R_PAR_ECP16_DATA__data__BITNR 0
+#define R_PAR_ECP16_DATA__data__WIDTH 16
+
+#define R_PAR0_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
+#define R_PAR0_CONFIG__ioe__BITNR 25
+#define R_PAR0_CONFIG__ioe__WIDTH 1
+#define R_PAR0_CONFIG__ioe__inv 1
+#define R_PAR0_CONFIG__ioe__noninv 0
+#define R_PAR0_CONFIG__iseli__BITNR 24
+#define R_PAR0_CONFIG__iseli__WIDTH 1
+#define R_PAR0_CONFIG__iseli__inv 1
+#define R_PAR0_CONFIG__iseli__noninv 0
+#define R_PAR0_CONFIG__iautofd__BITNR 23
+#define R_PAR0_CONFIG__iautofd__WIDTH 1
+#define R_PAR0_CONFIG__iautofd__inv 1
+#define R_PAR0_CONFIG__iautofd__noninv 0
+#define R_PAR0_CONFIG__istrb__BITNR 22
+#define R_PAR0_CONFIG__istrb__WIDTH 1
+#define R_PAR0_CONFIG__istrb__inv 1
+#define R_PAR0_CONFIG__istrb__noninv 0
+#define R_PAR0_CONFIG__iinit__BITNR 21
+#define R_PAR0_CONFIG__iinit__WIDTH 1
+#define R_PAR0_CONFIG__iinit__inv 1
+#define R_PAR0_CONFIG__iinit__noninv 0
+#define R_PAR0_CONFIG__iperr__BITNR 20
+#define R_PAR0_CONFIG__iperr__WIDTH 1
+#define R_PAR0_CONFIG__iperr__inv 1
+#define R_PAR0_CONFIG__iperr__noninv 0
+#define R_PAR0_CONFIG__iack__BITNR 19
+#define R_PAR0_CONFIG__iack__WIDTH 1
+#define R_PAR0_CONFIG__iack__inv 1
+#define R_PAR0_CONFIG__iack__noninv 0
+#define R_PAR0_CONFIG__ibusy__BITNR 18
+#define R_PAR0_CONFIG__ibusy__WIDTH 1
+#define R_PAR0_CONFIG__ibusy__inv 1
+#define R_PAR0_CONFIG__ibusy__noninv 0
+#define R_PAR0_CONFIG__ifault__BITNR 17
+#define R_PAR0_CONFIG__ifault__WIDTH 1
+#define R_PAR0_CONFIG__ifault__inv 1
+#define R_PAR0_CONFIG__ifault__noninv 0
+#define R_PAR0_CONFIG__isel__BITNR 16
+#define R_PAR0_CONFIG__isel__WIDTH 1
+#define R_PAR0_CONFIG__isel__inv 1
+#define R_PAR0_CONFIG__isel__noninv 0
+#define R_PAR0_CONFIG__ext_mode__BITNR 11
+#define R_PAR0_CONFIG__ext_mode__WIDTH 1
+#define R_PAR0_CONFIG__ext_mode__enable 1
+#define R_PAR0_CONFIG__ext_mode__disable 0
+#define R_PAR0_CONFIG__wide__BITNR 10
+#define R_PAR0_CONFIG__wide__WIDTH 1
+#define R_PAR0_CONFIG__wide__enable 1
+#define R_PAR0_CONFIG__wide__disable 0
+#define R_PAR0_CONFIG__dma__BITNR 9
+#define R_PAR0_CONFIG__dma__WIDTH 1
+#define R_PAR0_CONFIG__dma__enable 1
+#define R_PAR0_CONFIG__dma__disable 0
+#define R_PAR0_CONFIG__rle_in__BITNR 8
+#define R_PAR0_CONFIG__rle_in__WIDTH 1
+#define R_PAR0_CONFIG__rle_in__enable 1
+#define R_PAR0_CONFIG__rle_in__disable 0
+#define R_PAR0_CONFIG__rle_out__BITNR 7
+#define R_PAR0_CONFIG__rle_out__WIDTH 1
+#define R_PAR0_CONFIG__rle_out__enable 1
+#define R_PAR0_CONFIG__rle_out__disable 0
+#define R_PAR0_CONFIG__enable__BITNR 6
+#define R_PAR0_CONFIG__enable__WIDTH 1
+#define R_PAR0_CONFIG__enable__on 1
+#define R_PAR0_CONFIG__enable__reset 0
+#define R_PAR0_CONFIG__force__BITNR 5
+#define R_PAR0_CONFIG__force__WIDTH 1
+#define R_PAR0_CONFIG__force__on 1
+#define R_PAR0_CONFIG__force__off 0
+#define R_PAR0_CONFIG__ign_ack__BITNR 4
+#define R_PAR0_CONFIG__ign_ack__WIDTH 1
+#define R_PAR0_CONFIG__ign_ack__ignore 1
+#define R_PAR0_CONFIG__ign_ack__wait 0
+#define R_PAR0_CONFIG__oe_ack__BITNR 3
+#define R_PAR0_CONFIG__oe_ack__WIDTH 1
+#define R_PAR0_CONFIG__oe_ack__wait_oe 1
+#define R_PAR0_CONFIG__oe_ack__dont_wait 0
+#define R_PAR0_CONFIG__oe_ack__epp_addr 1
+#define R_PAR0_CONFIG__oe_ack__epp_data 0
+#define R_PAR0_CONFIG__epp_addr_data__BITNR 3
+#define R_PAR0_CONFIG__epp_addr_data__WIDTH 1
+#define R_PAR0_CONFIG__epp_addr_data__wait_oe 1
+#define R_PAR0_CONFIG__epp_addr_data__dont_wait 0
+#define R_PAR0_CONFIG__epp_addr_data__epp_addr 1
+#define R_PAR0_CONFIG__epp_addr_data__epp_data 0
+#define R_PAR0_CONFIG__mode__BITNR 0
+#define R_PAR0_CONFIG__mode__WIDTH 3
+#define R_PAR0_CONFIG__mode__manual 0
+#define R_PAR0_CONFIG__mode__centronics 1
+#define R_PAR0_CONFIG__mode__fastbyte 2
+#define R_PAR0_CONFIG__mode__nibble 3
+#define R_PAR0_CONFIG__mode__byte 4
+#define R_PAR0_CONFIG__mode__ecp_fwd 5
+#define R_PAR0_CONFIG__mode__ecp_rev 6
+#define R_PAR0_CONFIG__mode__off 7
+#define R_PAR0_CONFIG__mode__epp_wr1 5
+#define R_PAR0_CONFIG__mode__epp_wr2 6
+#define R_PAR0_CONFIG__mode__epp_wr3 7
+#define R_PAR0_CONFIG__mode__epp_rd 0
+
+#define R_PAR0_DELAY (IO_TYPECAST_UDWORD 0xb0000048)
+#define R_PAR0_DELAY__fine_hold__BITNR 21
+#define R_PAR0_DELAY__fine_hold__WIDTH 3
+#define R_PAR0_DELAY__hold__BITNR 16
+#define R_PAR0_DELAY__hold__WIDTH 5
+#define R_PAR0_DELAY__fine_strb__BITNR 13
+#define R_PAR0_DELAY__fine_strb__WIDTH 3
+#define R_PAR0_DELAY__strobe__BITNR 8
+#define R_PAR0_DELAY__strobe__WIDTH 5
+#define R_PAR0_DELAY__fine_setup__BITNR 5
+#define R_PAR0_DELAY__fine_setup__WIDTH 3
+#define R_PAR0_DELAY__setup__BITNR 0
+#define R_PAR0_DELAY__setup__WIDTH 5
+
+#define R_PAR1_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000050)
+#define R_PAR1_CTRL_DATA__peri_int__BITNR 24
+#define R_PAR1_CTRL_DATA__peri_int__WIDTH 1
+#define R_PAR1_CTRL_DATA__peri_int__ack 1
+#define R_PAR1_CTRL_DATA__peri_int__nop 0
+#define R_PAR1_CTRL_DATA__oe__BITNR 20
+#define R_PAR1_CTRL_DATA__oe__WIDTH 1
+#define R_PAR1_CTRL_DATA__oe__enable 1
+#define R_PAR1_CTRL_DATA__oe__disable 0
+#define R_PAR1_CTRL_DATA__seli__BITNR 19
+#define R_PAR1_CTRL_DATA__seli__WIDTH 1
+#define R_PAR1_CTRL_DATA__seli__active 1
+#define R_PAR1_CTRL_DATA__seli__inactive 0
+#define R_PAR1_CTRL_DATA__autofd__BITNR 18
+#define R_PAR1_CTRL_DATA__autofd__WIDTH 1
+#define R_PAR1_CTRL_DATA__autofd__active 1
+#define R_PAR1_CTRL_DATA__autofd__inactive 0
+#define R_PAR1_CTRL_DATA__strb__BITNR 17
+#define R_PAR1_CTRL_DATA__strb__WIDTH 1
+#define R_PAR1_CTRL_DATA__strb__active 1
+#define R_PAR1_CTRL_DATA__strb__inactive 0
+#define R_PAR1_CTRL_DATA__init__BITNR 16
+#define R_PAR1_CTRL_DATA__init__WIDTH 1
+#define R_PAR1_CTRL_DATA__init__active 1
+#define R_PAR1_CTRL_DATA__init__inactive 0
+#define R_PAR1_CTRL_DATA__ecp_cmd__BITNR 8
+#define R_PAR1_CTRL_DATA__ecp_cmd__WIDTH 1
+#define R_PAR1_CTRL_DATA__ecp_cmd__command 1
+#define R_PAR1_CTRL_DATA__ecp_cmd__data 0
+#define R_PAR1_CTRL_DATA__data__BITNR 0
+#define R_PAR1_CTRL_DATA__data__WIDTH 8
+
+#define R_PAR1_CTRL (IO_TYPECAST_BYTE 0xb0000052)
+#define R_PAR1_CTRL__ctrl__BITNR 0
+#define R_PAR1_CTRL__ctrl__WIDTH 5
+
+#define R_PAR1_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000050)
+#define R_PAR1_STATUS_DATA__mode__BITNR 29
+#define R_PAR1_STATUS_DATA__mode__WIDTH 3
+#define R_PAR1_STATUS_DATA__mode__manual 0
+#define R_PAR1_STATUS_DATA__mode__centronics 1
+#define R_PAR1_STATUS_DATA__mode__fastbyte 2
+#define R_PAR1_STATUS_DATA__mode__nibble 3
+#define R_PAR1_STATUS_DATA__mode__byte 4
+#define R_PAR1_STATUS_DATA__mode__ecp_fwd 5
+#define R_PAR1_STATUS_DATA__mode__ecp_rev 6
+#define R_PAR1_STATUS_DATA__mode__off 7
+#define R_PAR1_STATUS_DATA__mode__epp_wr1 5
+#define R_PAR1_STATUS_DATA__mode__epp_wr2 6
+#define R_PAR1_STATUS_DATA__mode__epp_wr3 7
+#define R_PAR1_STATUS_DATA__mode__epp_rd 0
+#define R_PAR1_STATUS_DATA__perr__BITNR 28
+#define R_PAR1_STATUS_DATA__perr__WIDTH 1
+#define R_PAR1_STATUS_DATA__perr__active 1
+#define R_PAR1_STATUS_DATA__perr__inactive 0
+#define R_PAR1_STATUS_DATA__ack__BITNR 27
+#define R_PAR1_STATUS_DATA__ack__WIDTH 1
+#define R_PAR1_STATUS_DATA__ack__active 0
+#define R_PAR1_STATUS_DATA__ack__inactive 1
+#define R_PAR1_STATUS_DATA__busy__BITNR 26
+#define R_PAR1_STATUS_DATA__busy__WIDTH 1
+#define R_PAR1_STATUS_DATA__busy__active 1
+#define R_PAR1_STATUS_DATA__busy__inactive 0
+#define R_PAR1_STATUS_DATA__fault__BITNR 25
+#define R_PAR1_STATUS_DATA__fault__WIDTH 1
+#define R_PAR1_STATUS_DATA__fault__active 0
+#define R_PAR1_STATUS_DATA__fault__inactive 1
+#define R_PAR1_STATUS_DATA__sel__BITNR 24
+#define R_PAR1_STATUS_DATA__sel__WIDTH 1
+#define R_PAR1_STATUS_DATA__sel__active 1
+#define R_PAR1_STATUS_DATA__sel__inactive 0
+#define R_PAR1_STATUS_DATA__ext_mode__BITNR 23
+#define R_PAR1_STATUS_DATA__ext_mode__WIDTH 1
+#define R_PAR1_STATUS_DATA__ext_mode__enable 1
+#define R_PAR1_STATUS_DATA__ext_mode__disable 0
+#define R_PAR1_STATUS_DATA__tr_rdy__BITNR 17
+#define R_PAR1_STATUS_DATA__tr_rdy__WIDTH 1
+#define R_PAR1_STATUS_DATA__tr_rdy__ready 1
+#define R_PAR1_STATUS_DATA__tr_rdy__busy 0
+#define R_PAR1_STATUS_DATA__dav__BITNR 16
+#define R_PAR1_STATUS_DATA__dav__WIDTH 1
+#define R_PAR1_STATUS_DATA__dav__data 1
+#define R_PAR1_STATUS_DATA__dav__nodata 0
+#define R_PAR1_STATUS_DATA__ecp_cmd__BITNR 8
+#define R_PAR1_STATUS_DATA__ecp_cmd__WIDTH 1
+#define R_PAR1_STATUS_DATA__ecp_cmd__command 1
+#define R_PAR1_STATUS_DATA__ecp_cmd__data 0
+#define R_PAR1_STATUS_DATA__data__BITNR 0
+#define R_PAR1_STATUS_DATA__data__WIDTH 8
+
+#define R_PAR1_STATUS (IO_TYPECAST_RO_UWORD 0xb0000052)
+#define R_PAR1_STATUS__mode__BITNR 13
+#define R_PAR1_STATUS__mode__WIDTH 3
+#define R_PAR1_STATUS__mode__manual 0
+#define R_PAR1_STATUS__mode__centronics 1
+#define R_PAR1_STATUS__mode__fastbyte 2
+#define R_PAR1_STATUS__mode__nibble 3
+#define R_PAR1_STATUS__mode__byte 4
+#define R_PAR1_STATUS__mode__ecp_fwd 5
+#define R_PAR1_STATUS__mode__ecp_rev 6
+#define R_PAR1_STATUS__mode__off 7
+#define R_PAR1_STATUS__mode__epp_wr1 5
+#define R_PAR1_STATUS__mode__epp_wr2 6
+#define R_PAR1_STATUS__mode__epp_wr3 7
+#define R_PAR1_STATUS__mode__epp_rd 0
+#define R_PAR1_STATUS__perr__BITNR 12
+#define R_PAR1_STATUS__perr__WIDTH 1
+#define R_PAR1_STATUS__perr__active 1
+#define R_PAR1_STATUS__perr__inactive 0
+#define R_PAR1_STATUS__ack__BITNR 11
+#define R_PAR1_STATUS__ack__WIDTH 1
+#define R_PAR1_STATUS__ack__active 0
+#define R_PAR1_STATUS__ack__inactive 1
+#define R_PAR1_STATUS__busy__BITNR 10
+#define R_PAR1_STATUS__busy__WIDTH 1
+#define R_PAR1_STATUS__busy__active 1
+#define R_PAR1_STATUS__busy__inactive 0
+#define R_PAR1_STATUS__fault__BITNR 9
+#define R_PAR1_STATUS__fault__WIDTH 1
+#define R_PAR1_STATUS__fault__active 0
+#define R_PAR1_STATUS__fault__inactive 1
+#define R_PAR1_STATUS__sel__BITNR 8
+#define R_PAR1_STATUS__sel__WIDTH 1
+#define R_PAR1_STATUS__sel__active 1
+#define R_PAR1_STATUS__sel__inactive 0
+#define R_PAR1_STATUS__ext_mode__BITNR 7
+#define R_PAR1_STATUS__ext_mode__WIDTH 1
+#define R_PAR1_STATUS__ext_mode__enable 1
+#define R_PAR1_STATUS__ext_mode__disable 0
+#define R_PAR1_STATUS__tr_rdy__BITNR 1
+#define R_PAR1_STATUS__tr_rdy__WIDTH 1
+#define R_PAR1_STATUS__tr_rdy__ready 1
+#define R_PAR1_STATUS__tr_rdy__busy 0
+#define R_PAR1_STATUS__dav__BITNR 0
+#define R_PAR1_STATUS__dav__WIDTH 1
+#define R_PAR1_STATUS__dav__data 1
+#define R_PAR1_STATUS__dav__nodata 0
+
+#define R_PAR1_CONFIG (IO_TYPECAST_UDWORD 0xb0000054)
+#define R_PAR1_CONFIG__ioe__BITNR 25
+#define R_PAR1_CONFIG__ioe__WIDTH 1
+#define R_PAR1_CONFIG__ioe__inv 1
+#define R_PAR1_CONFIG__ioe__noninv 0
+#define R_PAR1_CONFIG__iseli__BITNR 24
+#define R_PAR1_CONFIG__iseli__WIDTH 1
+#define R_PAR1_CONFIG__iseli__inv 1
+#define R_PAR1_CONFIG__iseli__noninv 0
+#define R_PAR1_CONFIG__iautofd__BITNR 23
+#define R_PAR1_CONFIG__iautofd__WIDTH 1
+#define R_PAR1_CONFIG__iautofd__inv 1
+#define R_PAR1_CONFIG__iautofd__noninv 0
+#define R_PAR1_CONFIG__istrb__BITNR 22
+#define R_PAR1_CONFIG__istrb__WIDTH 1
+#define R_PAR1_CONFIG__istrb__inv 1
+#define R_PAR1_CONFIG__istrb__noninv 0
+#define R_PAR1_CONFIG__iinit__BITNR 21
+#define R_PAR1_CONFIG__iinit__WIDTH 1
+#define R_PAR1_CONFIG__iinit__inv 1
+#define R_PAR1_CONFIG__iinit__noninv 0
+#define R_PAR1_CONFIG__iperr__BITNR 20
+#define R_PAR1_CONFIG__iperr__WIDTH 1
+#define R_PAR1_CONFIG__iperr__inv 1
+#define R_PAR1_CONFIG__iperr__noninv 0
+#define R_PAR1_CONFIG__iack__BITNR 19
+#define R_PAR1_CONFIG__iack__WIDTH 1
+#define R_PAR1_CONFIG__iack__inv 1
+#define R_PAR1_CONFIG__iack__noninv 0
+#define R_PAR1_CONFIG__ibusy__BITNR 18
+#define R_PAR1_CONFIG__ibusy__WIDTH 1
+#define R_PAR1_CONFIG__ibusy__inv 1
+#define R_PAR1_CONFIG__ibusy__noninv 0
+#define R_PAR1_CONFIG__ifault__BITNR 17
+#define R_PAR1_CONFIG__ifault__WIDTH 1
+#define R_PAR1_CONFIG__ifault__inv 1
+#define R_PAR1_CONFIG__ifault__noninv 0
+#define R_PAR1_CONFIG__isel__BITNR 16
+#define R_PAR1_CONFIG__isel__WIDTH 1
+#define R_PAR1_CONFIG__isel__inv 1
+#define R_PAR1_CONFIG__isel__noninv 0
+#define R_PAR1_CONFIG__ext_mode__BITNR 11
+#define R_PAR1_CONFIG__ext_mode__WIDTH 1
+#define R_PAR1_CONFIG__ext_mode__enable 1
+#define R_PAR1_CONFIG__ext_mode__disable 0
+#define R_PAR1_CONFIG__dma__BITNR 9
+#define R_PAR1_CONFIG__dma__WIDTH 1
+#define R_PAR1_CONFIG__dma__enable 1
+#define R_PAR1_CONFIG__dma__disable 0
+#define R_PAR1_CONFIG__rle_in__BITNR 8
+#define R_PAR1_CONFIG__rle_in__WIDTH 1
+#define R_PAR1_CONFIG__rle_in__enable 1
+#define R_PAR1_CONFIG__rle_in__disable 0
+#define R_PAR1_CONFIG__rle_out__BITNR 7
+#define R_PAR1_CONFIG__rle_out__WIDTH 1
+#define R_PAR1_CONFIG__rle_out__enable 1
+#define R_PAR1_CONFIG__rle_out__disable 0
+#define R_PAR1_CONFIG__enable__BITNR 6
+#define R_PAR1_CONFIG__enable__WIDTH 1
+#define R_PAR1_CONFIG__enable__on 1
+#define R_PAR1_CONFIG__enable__reset 0
+#define R_PAR1_CONFIG__force__BITNR 5
+#define R_PAR1_CONFIG__force__WIDTH 1
+#define R_PAR1_CONFIG__force__on 1
+#define R_PAR1_CONFIG__force__off 0
+#define R_PAR1_CONFIG__ign_ack__BITNR 4
+#define R_PAR1_CONFIG__ign_ack__WIDTH 1
+#define R_PAR1_CONFIG__ign_ack__ignore 1
+#define R_PAR1_CONFIG__ign_ack__wait 0
+#define R_PAR1_CONFIG__oe_ack__BITNR 3
+#define R_PAR1_CONFIG__oe_ack__WIDTH 1
+#define R_PAR1_CONFIG__oe_ack__wait_oe 1
+#define R_PAR1_CONFIG__oe_ack__dont_wait 0
+#define R_PAR1_CONFIG__oe_ack__epp_addr 1
+#define R_PAR1_CONFIG__oe_ack__epp_data 0
+#define R_PAR1_CONFIG__epp_addr_data__BITNR 3
+#define R_PAR1_CONFIG__epp_addr_data__WIDTH 1
+#define R_PAR1_CONFIG__epp_addr_data__wait_oe 1
+#define R_PAR1_CONFIG__epp_addr_data__dont_wait 0
+#define R_PAR1_CONFIG__epp_addr_data__epp_addr 1
+#define R_PAR1_CONFIG__epp_addr_data__epp_data 0
+#define R_PAR1_CONFIG__mode__BITNR 0
+#define R_PAR1_CONFIG__mode__WIDTH 3
+#define R_PAR1_CONFIG__mode__manual 0
+#define R_PAR1_CONFIG__mode__centronics 1
+#define R_PAR1_CONFIG__mode__fastbyte 2
+#define R_PAR1_CONFIG__mode__nibble 3
+#define R_PAR1_CONFIG__mode__byte 4
+#define R_PAR1_CONFIG__mode__ecp_fwd 5
+#define R_PAR1_CONFIG__mode__ecp_rev 6
+#define R_PAR1_CONFIG__mode__off 7
+#define R_PAR1_CONFIG__mode__epp_wr1 5
+#define R_PAR1_CONFIG__mode__epp_wr2 6
+#define R_PAR1_CONFIG__mode__epp_wr3 7
+#define R_PAR1_CONFIG__mode__epp_rd 0
+
+#define R_PAR1_DELAY (IO_TYPECAST_UDWORD 0xb0000058)
+#define R_PAR1_DELAY__fine_hold__BITNR 21
+#define R_PAR1_DELAY__fine_hold__WIDTH 3
+#define R_PAR1_DELAY__hold__BITNR 16
+#define R_PAR1_DELAY__hold__WIDTH 5
+#define R_PAR1_DELAY__fine_strb__BITNR 13
+#define R_PAR1_DELAY__fine_strb__WIDTH 3
+#define R_PAR1_DELAY__strobe__BITNR 8
+#define R_PAR1_DELAY__strobe__WIDTH 5
+#define R_PAR1_DELAY__fine_setup__BITNR 5
+#define R_PAR1_DELAY__fine_setup__WIDTH 3
+#define R_PAR1_DELAY__setup__BITNR 0
+#define R_PAR1_DELAY__setup__WIDTH 5
+
+/*
+!* ATA interface registers
+!*/
+
+#define R_ATA_CTRL_DATA (IO_TYPECAST_UDWORD 0xb0000040)
+#define R_ATA_CTRL_DATA__sel__BITNR 30
+#define R_ATA_CTRL_DATA__sel__WIDTH 2
+#define R_ATA_CTRL_DATA__cs1__BITNR 29
+#define R_ATA_CTRL_DATA__cs1__WIDTH 1
+#define R_ATA_CTRL_DATA__cs1__active 1
+#define R_ATA_CTRL_DATA__cs1__inactive 0
+#define R_ATA_CTRL_DATA__cs0__BITNR 28
+#define R_ATA_CTRL_DATA__cs0__WIDTH 1
+#define R_ATA_CTRL_DATA__cs0__active 1
+#define R_ATA_CTRL_DATA__cs0__inactive 0
+#define R_ATA_CTRL_DATA__addr__BITNR 25
+#define R_ATA_CTRL_DATA__addr__WIDTH 3
+#define R_ATA_CTRL_DATA__rw__BITNR 24
+#define R_ATA_CTRL_DATA__rw__WIDTH 1
+#define R_ATA_CTRL_DATA__rw__read 1
+#define R_ATA_CTRL_DATA__rw__write 0
+#define R_ATA_CTRL_DATA__src_dst__BITNR 23
+#define R_ATA_CTRL_DATA__src_dst__WIDTH 1
+#define R_ATA_CTRL_DATA__src_dst__dma 1
+#define R_ATA_CTRL_DATA__src_dst__register 0
+#define R_ATA_CTRL_DATA__handsh__BITNR 22
+#define R_ATA_CTRL_DATA__handsh__WIDTH 1
+#define R_ATA_CTRL_DATA__handsh__dma 1
+#define R_ATA_CTRL_DATA__handsh__pio 0
+#define R_ATA_CTRL_DATA__multi__BITNR 21
+#define R_ATA_CTRL_DATA__multi__WIDTH 1
+#define R_ATA_CTRL_DATA__multi__on 1
+#define R_ATA_CTRL_DATA__multi__off 0
+#define R_ATA_CTRL_DATA__dma_size__BITNR 20
+#define R_ATA_CTRL_DATA__dma_size__WIDTH 1
+#define R_ATA_CTRL_DATA__dma_size__byte 1
+#define R_ATA_CTRL_DATA__dma_size__word 0
+#define R_ATA_CTRL_DATA__data__BITNR 0
+#define R_ATA_CTRL_DATA__data__WIDTH 16
+
+#define R_ATA_STATUS_DATA (IO_TYPECAST_RO_UDWORD 0xb0000040)
+#define R_ATA_STATUS_DATA__busy__BITNR 18
+#define R_ATA_STATUS_DATA__busy__WIDTH 1
+#define R_ATA_STATUS_DATA__busy__yes 1
+#define R_ATA_STATUS_DATA__busy__no 0
+#define R_ATA_STATUS_DATA__tr_rdy__BITNR 17
+#define R_ATA_STATUS_DATA__tr_rdy__WIDTH 1
+#define R_ATA_STATUS_DATA__tr_rdy__ready 1
+#define R_ATA_STATUS_DATA__tr_rdy__busy 0
+#define R_ATA_STATUS_DATA__dav__BITNR 16
+#define R_ATA_STATUS_DATA__dav__WIDTH 1
+#define R_ATA_STATUS_DATA__dav__data 1
+#define R_ATA_STATUS_DATA__dav__nodata 0
+#define R_ATA_STATUS_DATA__data__BITNR 0
+#define R_ATA_STATUS_DATA__data__WIDTH 16
+
+#define R_ATA_CONFIG (IO_TYPECAST_UDWORD 0xb0000044)
+#define R_ATA_CONFIG__enable__BITNR 25
+#define R_ATA_CONFIG__enable__WIDTH 1
+#define R_ATA_CONFIG__enable__on 1
+#define R_ATA_CONFIG__enable__off 0
+#define R_ATA_CONFIG__dma_strobe__BITNR 20
+#define R_ATA_CONFIG__dma_strobe__WIDTH 5
+#define R_ATA_CONFIG__dma_hold__BITNR 15
+#define R_ATA_CONFIG__dma_hold__WIDTH 5
+#define R_ATA_CONFIG__pio_setup__BITNR 10
+#define R_ATA_CONFIG__pio_setup__WIDTH 5
+#define R_ATA_CONFIG__pio_strobe__BITNR 5
+#define R_ATA_CONFIG__pio_strobe__WIDTH 5
+#define R_ATA_CONFIG__pio_hold__BITNR 0
+#define R_ATA_CONFIG__pio_hold__WIDTH 5
+
+#define R_ATA_TRANSFER_CNT (IO_TYPECAST_UDWORD 0xb0000048)
+#define R_ATA_TRANSFER_CNT__count__BITNR 0
+#define R_ATA_TRANSFER_CNT__count__WIDTH 17
+
+/*
+!* SCSI registers
+!*/
+
+#define R_SCSI0_CTRL (IO_TYPECAST_UDWORD 0xb0000044)
+#define R_SCSI0_CTRL__id_type__BITNR 31
+#define R_SCSI0_CTRL__id_type__WIDTH 1
+#define R_SCSI0_CTRL__id_type__software 1
+#define R_SCSI0_CTRL__id_type__hardware 0
+#define R_SCSI0_CTRL__sel_timeout__BITNR 24
+#define R_SCSI0_CTRL__sel_timeout__WIDTH 7
+#define R_SCSI0_CTRL__synch_per__BITNR 16
+#define R_SCSI0_CTRL__synch_per__WIDTH 8
+#define R_SCSI0_CTRL__rst__BITNR 15
+#define R_SCSI0_CTRL__rst__WIDTH 1
+#define R_SCSI0_CTRL__rst__yes 1
+#define R_SCSI0_CTRL__rst__no 0
+#define R_SCSI0_CTRL__atn__BITNR 14
+#define R_SCSI0_CTRL__atn__WIDTH 1
+#define R_SCSI0_CTRL__atn__yes 1
+#define R_SCSI0_CTRL__atn__no 0
+#define R_SCSI0_CTRL__my_id__BITNR 9
+#define R_SCSI0_CTRL__my_id__WIDTH 4
+#define R_SCSI0_CTRL__target_id__BITNR 4
+#define R_SCSI0_CTRL__target_id__WIDTH 4
+#define R_SCSI0_CTRL__fast_20__BITNR 3
+#define R_SCSI0_CTRL__fast_20__WIDTH 1
+#define R_SCSI0_CTRL__fast_20__yes 1
+#define R_SCSI0_CTRL__fast_20__no 0
+#define R_SCSI0_CTRL__bus_width__BITNR 2
+#define R_SCSI0_CTRL__bus_width__WIDTH 1
+#define R_SCSI0_CTRL__bus_width__wide 1
+#define R_SCSI0_CTRL__bus_width__narrow 0
+#define R_SCSI0_CTRL__synch__BITNR 1
+#define R_SCSI0_CTRL__synch__WIDTH 1
+#define R_SCSI0_CTRL__synch__synch 1
+#define R_SCSI0_CTRL__synch__asynch 0
+#define R_SCSI0_CTRL__enable__BITNR 0
+#define R_SCSI0_CTRL__enable__WIDTH 1
+#define R_SCSI0_CTRL__enable__on 1
+#define R_SCSI0_CTRL__enable__off 0
+
+#define R_SCSI0_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000040)
+#define R_SCSI0_CMD_DATA__parity_in__BITNR 26
+#define R_SCSI0_CMD_DATA__parity_in__WIDTH 1
+#define R_SCSI0_CMD_DATA__parity_in__on 0
+#define R_SCSI0_CMD_DATA__parity_in__off 1
+#define R_SCSI0_CMD_DATA__skip__BITNR 25
+#define R_SCSI0_CMD_DATA__skip__WIDTH 1
+#define R_SCSI0_CMD_DATA__skip__on 1
+#define R_SCSI0_CMD_DATA__skip__off 0
+#define R_SCSI0_CMD_DATA__clr_status__BITNR 24
+#define R_SCSI0_CMD_DATA__clr_status__WIDTH 1
+#define R_SCSI0_CMD_DATA__clr_status__yes 1
+#define R_SCSI0_CMD_DATA__clr_status__nop 0
+#define R_SCSI0_CMD_DATA__asynch_setup__BITNR 20
+#define R_SCSI0_CMD_DATA__asynch_setup__WIDTH 4
+#define R_SCSI0_CMD_DATA__command__BITNR 16
+#define R_SCSI0_CMD_DATA__command__WIDTH 4
+#define R_SCSI0_CMD_DATA__command__full_din_1 0
+#define R_SCSI0_CMD_DATA__command__full_dout_1 1
+#define R_SCSI0_CMD_DATA__command__full_stat_1 2
+#define R_SCSI0_CMD_DATA__command__resel_din 3
+#define R_SCSI0_CMD_DATA__command__resel_dout 4
+#define R_SCSI0_CMD_DATA__command__resel_stat 5
+#define R_SCSI0_CMD_DATA__command__arb_only 6
+#define R_SCSI0_CMD_DATA__command__full_din_3 8
+#define R_SCSI0_CMD_DATA__command__full_dout_3 9
+#define R_SCSI0_CMD_DATA__command__full_stat_3 10
+#define R_SCSI0_CMD_DATA__command__man_data_in 11
+#define R_SCSI0_CMD_DATA__command__man_data_out 12
+#define R_SCSI0_CMD_DATA__command__man_rat 13
+#define R_SCSI0_CMD_DATA__data_out__BITNR 0
+#define R_SCSI0_CMD_DATA__data_out__WIDTH 16
+
+#define R_SCSI0_DATA (IO_TYPECAST_UWORD 0xb0000040)
+#define R_SCSI0_DATA__data_out__BITNR 0
+#define R_SCSI0_DATA__data_out__WIDTH 16
+
+#define R_SCSI0_CMD (IO_TYPECAST_BYTE 0xb0000042)
+#define R_SCSI0_CMD__asynch_setup__BITNR 4
+#define R_SCSI0_CMD__asynch_setup__WIDTH 4
+#define R_SCSI0_CMD__command__BITNR 0
+#define R_SCSI0_CMD__command__WIDTH 4
+#define R_SCSI0_CMD__command__full_din_1 0
+#define R_SCSI0_CMD__command__full_dout_1 1
+#define R_SCSI0_CMD__command__full_stat_1 2
+#define R_SCSI0_CMD__command__resel_din 3
+#define R_SCSI0_CMD__command__resel_dout 4
+#define R_SCSI0_CMD__command__resel_stat 5
+#define R_SCSI0_CMD__command__arb_only 6
+#define R_SCSI0_CMD__command__full_din_3 8
+#define R_SCSI0_CMD__command__full_dout_3 9
+#define R_SCSI0_CMD__command__full_stat_3 10
+#define R_SCSI0_CMD__command__man_data_in 11
+#define R_SCSI0_CMD__command__man_data_out 12
+#define R_SCSI0_CMD__command__man_rat 13
+
+#define R_SCSI0_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000043)
+#define R_SCSI0_STATUS_CTRL__parity_in__BITNR 2
+#define R_SCSI0_STATUS_CTRL__parity_in__WIDTH 1
+#define R_SCSI0_STATUS_CTRL__parity_in__on 0
+#define R_SCSI0_STATUS_CTRL__parity_in__off 1
+#define R_SCSI0_STATUS_CTRL__skip__BITNR 1
+#define R_SCSI0_STATUS_CTRL__skip__WIDTH 1
+#define R_SCSI0_STATUS_CTRL__skip__on 1
+#define R_SCSI0_STATUS_CTRL__skip__off 0
+#define R_SCSI0_STATUS_CTRL__clr_status__BITNR 0
+#define R_SCSI0_STATUS_CTRL__clr_status__WIDTH 1
+#define R_SCSI0_STATUS_CTRL__clr_status__yes 1
+#define R_SCSI0_STATUS_CTRL__clr_status__nop 0
+
+#define R_SCSI0_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000048)
+#define R_SCSI0_STATUS__tst_arb_won__BITNR 23
+#define R_SCSI0_STATUS__tst_arb_won__WIDTH 1
+#define R_SCSI0_STATUS__tst_resel__BITNR 22
+#define R_SCSI0_STATUS__tst_resel__WIDTH 1
+#define R_SCSI0_STATUS__parity_error__BITNR 21
+#define R_SCSI0_STATUS__parity_error__WIDTH 1
+#define R_SCSI0_STATUS__bus_reset__BITNR 20
+#define R_SCSI0_STATUS__bus_reset__WIDTH 1
+#define R_SCSI0_STATUS__bus_reset__yes 1
+#define R_SCSI0_STATUS__bus_reset__no 0
+#define R_SCSI0_STATUS__resel_target__BITNR 15
+#define R_SCSI0_STATUS__resel_target__WIDTH 4
+#define R_SCSI0_STATUS__resel__BITNR 14
+#define R_SCSI0_STATUS__resel__WIDTH 1
+#define R_SCSI0_STATUS__resel__yes 1
+#define R_SCSI0_STATUS__resel__no 0
+#define R_SCSI0_STATUS__curr_phase__BITNR 11
+#define R_SCSI0_STATUS__curr_phase__WIDTH 3
+#define R_SCSI0_STATUS__curr_phase__ph_undef 0
+#define R_SCSI0_STATUS__curr_phase__ph_msg_in 7
+#define R_SCSI0_STATUS__curr_phase__ph_msg_out 6
+#define R_SCSI0_STATUS__curr_phase__ph_status 3
+#define R_SCSI0_STATUS__curr_phase__ph_command 2
+#define R_SCSI0_STATUS__curr_phase__ph_data_in 5
+#define R_SCSI0_STATUS__curr_phase__ph_data_out 4
+#define R_SCSI0_STATUS__curr_phase__ph_resel 1
+#define R_SCSI0_STATUS__last_seq_step__BITNR 6
+#define R_SCSI0_STATUS__last_seq_step__WIDTH 5
+#define R_SCSI0_STATUS__last_seq_step__st_bus_free 24
+#define R_SCSI0_STATUS__last_seq_step__st_arbitrate 8
+#define R_SCSI0_STATUS__last_seq_step__st_resel_req 29
+#define R_SCSI0_STATUS__last_seq_step__st_msg_1 2
+#define R_SCSI0_STATUS__last_seq_step__st_manual 28
+#define R_SCSI0_STATUS__last_seq_step__st_transf_cmd 30
+#define R_SCSI0_STATUS__last_seq_step__st_msg_2 6
+#define R_SCSI0_STATUS__last_seq_step__st_msg_3 22
+#define R_SCSI0_STATUS__last_seq_step__st_answer 3
+#define R_SCSI0_STATUS__last_seq_step__st_synch_din_perr 1
+#define R_SCSI0_STATUS__last_seq_step__st_transfer_done 15
+#define R_SCSI0_STATUS__last_seq_step__st_synch_dout 0
+#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout 25
+#define R_SCSI0_STATUS__last_seq_step__st_synch_din 13
+#define R_SCSI0_STATUS__last_seq_step__st_asynch_din 9
+#define R_SCSI0_STATUS__last_seq_step__st_synch_dout_ack 4
+#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack 12
+#define R_SCSI0_STATUS__last_seq_step__st_synch_din_ack_perr 5
+#define R_SCSI0_STATUS__last_seq_step__st_asynch_dout_end 11
+#define R_SCSI0_STATUS__last_seq_step__st_iwr 27
+#define R_SCSI0_STATUS__last_seq_step__st_wait_free_disc 21
+#define R_SCSI0_STATUS__last_seq_step__st_sdp_disc 7
+#define R_SCSI0_STATUS__last_seq_step__st_cc 31
+#define R_SCSI0_STATUS__last_seq_step__st_iwr_good 14
+#define R_SCSI0_STATUS__last_seq_step__st_iwr_cc 23
+#define R_SCSI0_STATUS__last_seq_step__st_wait_free_iwr_cc 17
+#define R_SCSI0_STATUS__last_seq_step__st_wait_free_cc 20
+#define R_SCSI0_STATUS__last_seq_step__st_wait_free_sdp_disc 16
+#define R_SCSI0_STATUS__last_seq_step__st_manual_req 10
+#define R_SCSI0_STATUS__last_seq_step__st_manual_din_prot 18
+#define R_SCSI0_STATUS__valid_status__BITNR 5
+#define R_SCSI0_STATUS__valid_status__WIDTH 1
+#define R_SCSI0_STATUS__valid_status__yes 1
+#define R_SCSI0_STATUS__valid_status__no 0
+#define R_SCSI0_STATUS__seq_status__BITNR 0
+#define R_SCSI0_STATUS__seq_status__WIDTH 5
+#define R_SCSI0_STATUS__seq_status__info_seq_complete 0
+#define R_SCSI0_STATUS__seq_status__info_parity_error 1
+#define R_SCSI0_STATUS__seq_status__info_unhandled_msg_in 2
+#define R_SCSI0_STATUS__seq_status__info_unexp_ph_change 3
+#define R_SCSI0_STATUS__seq_status__info_arb_lost 4
+#define R_SCSI0_STATUS__seq_status__info_sel_timeout 5
+#define R_SCSI0_STATUS__seq_status__info_unexp_bf 6
+#define R_SCSI0_STATUS__seq_status__info_illegal_op 7
+#define R_SCSI0_STATUS__seq_status__info_rec_recvd 8
+#define R_SCSI0_STATUS__seq_status__info_reselected 9
+#define R_SCSI0_STATUS__seq_status__info_unhandled_status 10
+#define R_SCSI0_STATUS__seq_status__info_bus_reset 11
+#define R_SCSI0_STATUS__seq_status__info_illegal_bf 12
+#define R_SCSI0_STATUS__seq_status__info_bus_free 13
+
+#define R_SCSI0_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000040)
+#define R_SCSI0_DATA_IN__data_in__BITNR 0
+#define R_SCSI0_DATA_IN__data_in__WIDTH 16
+
+#define R_SCSI1_CTRL (IO_TYPECAST_UDWORD 0xb0000054)
+#define R_SCSI1_CTRL__id_type__BITNR 31
+#define R_SCSI1_CTRL__id_type__WIDTH 1
+#define R_SCSI1_CTRL__id_type__software 1
+#define R_SCSI1_CTRL__id_type__hardware 0
+#define R_SCSI1_CTRL__sel_timeout__BITNR 24
+#define R_SCSI1_CTRL__sel_timeout__WIDTH 7
+#define R_SCSI1_CTRL__synch_per__BITNR 16
+#define R_SCSI1_CTRL__synch_per__WIDTH 8
+#define R_SCSI1_CTRL__rst__BITNR 15
+#define R_SCSI1_CTRL__rst__WIDTH 1
+#define R_SCSI1_CTRL__rst__yes 1
+#define R_SCSI1_CTRL__rst__no 0
+#define R_SCSI1_CTRL__atn__BITNR 14
+#define R_SCSI1_CTRL__atn__WIDTH 1
+#define R_SCSI1_CTRL__atn__yes 1
+#define R_SCSI1_CTRL__atn__no 0
+#define R_SCSI1_CTRL__my_id__BITNR 9
+#define R_SCSI1_CTRL__my_id__WIDTH 4
+#define R_SCSI1_CTRL__target_id__BITNR 4
+#define R_SCSI1_CTRL__target_id__WIDTH 4
+#define R_SCSI1_CTRL__fast_20__BITNR 3
+#define R_SCSI1_CTRL__fast_20__WIDTH 1
+#define R_SCSI1_CTRL__fast_20__yes 1
+#define R_SCSI1_CTRL__fast_20__no 0
+#define R_SCSI1_CTRL__bus_width__BITNR 2
+#define R_SCSI1_CTRL__bus_width__WIDTH 1
+#define R_SCSI1_CTRL__bus_width__wide 1
+#define R_SCSI1_CTRL__bus_width__narrow 0
+#define R_SCSI1_CTRL__synch__BITNR 1
+#define R_SCSI1_CTRL__synch__WIDTH 1
+#define R_SCSI1_CTRL__synch__synch 1
+#define R_SCSI1_CTRL__synch__asynch 0
+#define R_SCSI1_CTRL__enable__BITNR 0
+#define R_SCSI1_CTRL__enable__WIDTH 1
+#define R_SCSI1_CTRL__enable__on 1
+#define R_SCSI1_CTRL__enable__off 0
+
+#define R_SCSI1_CMD_DATA (IO_TYPECAST_UDWORD 0xb0000050)
+#define R_SCSI1_CMD_DATA__parity_in__BITNR 26
+#define R_SCSI1_CMD_DATA__parity_in__WIDTH 1
+#define R_SCSI1_CMD_DATA__parity_in__on 0
+#define R_SCSI1_CMD_DATA__parity_in__off 1
+#define R_SCSI1_CMD_DATA__skip__BITNR 25
+#define R_SCSI1_CMD_DATA__skip__WIDTH 1
+#define R_SCSI1_CMD_DATA__skip__on 1
+#define R_SCSI1_CMD_DATA__skip__off 0
+#define R_SCSI1_CMD_DATA__clr_status__BITNR 24
+#define R_SCSI1_CMD_DATA__clr_status__WIDTH 1
+#define R_SCSI1_CMD_DATA__clr_status__yes 1
+#define R_SCSI1_CMD_DATA__clr_status__nop 0
+#define R_SCSI1_CMD_DATA__asynch_setup__BITNR 20
+#define R_SCSI1_CMD_DATA__asynch_setup__WIDTH 4
+#define R_SCSI1_CMD_DATA__command__BITNR 16
+#define R_SCSI1_CMD_DATA__command__WIDTH 4
+#define R_SCSI1_CMD_DATA__command__full_din_1 0
+#define R_SCSI1_CMD_DATA__command__full_dout_1 1
+#define R_SCSI1_CMD_DATA__command__full_stat_1 2
+#define R_SCSI1_CMD_DATA__command__resel_din 3
+#define R_SCSI1_CMD_DATA__command__resel_dout 4
+#define R_SCSI1_CMD_DATA__command__resel_stat 5
+#define R_SCSI1_CMD_DATA__command__arb_only 6
+#define R_SCSI1_CMD_DATA__command__full_din_3 8
+#define R_SCSI1_CMD_DATA__command__full_dout_3 9
+#define R_SCSI1_CMD_DATA__command__full_stat_3 10
+#define R_SCSI1_CMD_DATA__command__man_data_in 11
+#define R_SCSI1_CMD_DATA__command__man_data_out 12
+#define R_SCSI1_CMD_DATA__command__man_rat 13
+#define R_SCSI1_CMD_DATA__data_out__BITNR 0
+#define R_SCSI1_CMD_DATA__data_out__WIDTH 16
+
+#define R_SCSI1_DATA (IO_TYPECAST_UWORD 0xb0000050)
+#define R_SCSI1_DATA__data_out__BITNR 0
+#define R_SCSI1_DATA__data_out__WIDTH 16
+
+#define R_SCSI1_CMD (IO_TYPECAST_BYTE 0xb0000052)
+#define R_SCSI1_CMD__asynch_setup__BITNR 4
+#define R_SCSI1_CMD__asynch_setup__WIDTH 4
+#define R_SCSI1_CMD__command__BITNR 0
+#define R_SCSI1_CMD__command__WIDTH 4
+#define R_SCSI1_CMD__command__full_din_1 0
+#define R_SCSI1_CMD__command__full_dout_1 1
+#define R_SCSI1_CMD__command__full_stat_1 2
+#define R_SCSI1_CMD__command__resel_din 3
+#define R_SCSI1_CMD__command__resel_dout 4
+#define R_SCSI1_CMD__command__resel_stat 5
+#define R_SCSI1_CMD__command__arb_only 6
+#define R_SCSI1_CMD__command__full_din_3 8
+#define R_SCSI1_CMD__command__full_dout_3 9
+#define R_SCSI1_CMD__command__full_stat_3 10
+#define R_SCSI1_CMD__command__man_data_in 11
+#define R_SCSI1_CMD__command__man_data_out 12
+#define R_SCSI1_CMD__command__man_rat 13
+
+#define R_SCSI1_STATUS_CTRL (IO_TYPECAST_BYTE 0xb0000053)
+#define R_SCSI1_STATUS_CTRL__parity_in__BITNR 2
+#define R_SCSI1_STATUS_CTRL__parity_in__WIDTH 1
+#define R_SCSI1_STATUS_CTRL__parity_in__on 0
+#define R_SCSI1_STATUS_CTRL__parity_in__off 1
+#define R_SCSI1_STATUS_CTRL__skip__BITNR 1
+#define R_SCSI1_STATUS_CTRL__skip__WIDTH 1
+#define R_SCSI1_STATUS_CTRL__skip__on 1
+#define R_SCSI1_STATUS_CTRL__skip__off 0
+#define R_SCSI1_STATUS_CTRL__clr_status__BITNR 0
+#define R_SCSI1_STATUS_CTRL__clr_status__WIDTH 1
+#define R_SCSI1_STATUS_CTRL__clr_status__yes 1
+#define R_SCSI1_STATUS_CTRL__clr_status__nop 0
+
+#define R_SCSI1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000058)
+#define R_SCSI1_STATUS__tst_arb_won__BITNR 23
+#define R_SCSI1_STATUS__tst_arb_won__WIDTH 1
+#define R_SCSI1_STATUS__tst_resel__BITNR 22
+#define R_SCSI1_STATUS__tst_resel__WIDTH 1
+#define R_SCSI1_STATUS__parity_error__BITNR 21
+#define R_SCSI1_STATUS__parity_error__WIDTH 1
+#define R_SCSI1_STATUS__bus_reset__BITNR 20
+#define R_SCSI1_STATUS__bus_reset__WIDTH 1
+#define R_SCSI1_STATUS__bus_reset__yes 1
+#define R_SCSI1_STATUS__bus_reset__no 0
+#define R_SCSI1_STATUS__resel_target__BITNR 15
+#define R_SCSI1_STATUS__resel_target__WIDTH 4
+#define R_SCSI1_STATUS__resel__BITNR 14
+#define R_SCSI1_STATUS__resel__WIDTH 1
+#define R_SCSI1_STATUS__resel__yes 1
+#define R_SCSI1_STATUS__resel__no 0
+#define R_SCSI1_STATUS__curr_phase__BITNR 11
+#define R_SCSI1_STATUS__curr_phase__WIDTH 3
+#define R_SCSI1_STATUS__curr_phase__ph_undef 0
+#define R_SCSI1_STATUS__curr_phase__ph_msg_in 7
+#define R_SCSI1_STATUS__curr_phase__ph_msg_out 6
+#define R_SCSI1_STATUS__curr_phase__ph_status 3
+#define R_SCSI1_STATUS__curr_phase__ph_command 2
+#define R_SCSI1_STATUS__curr_phase__ph_data_in 5
+#define R_SCSI1_STATUS__curr_phase__ph_data_out 4
+#define R_SCSI1_STATUS__curr_phase__ph_resel 1
+#define R_SCSI1_STATUS__last_seq_step__BITNR 6
+#define R_SCSI1_STATUS__last_seq_step__WIDTH 5
+#define R_SCSI1_STATUS__last_seq_step__st_bus_free 24
+#define R_SCSI1_STATUS__last_seq_step__st_arbitrate 8
+#define R_SCSI1_STATUS__last_seq_step__st_resel_req 29
+#define R_SCSI1_STATUS__last_seq_step__st_msg_1 2
+#define R_SCSI1_STATUS__last_seq_step__st_manual 28
+#define R_SCSI1_STATUS__last_seq_step__st_transf_cmd 30
+#define R_SCSI1_STATUS__last_seq_step__st_msg_2 6
+#define R_SCSI1_STATUS__last_seq_step__st_msg_3 22
+#define R_SCSI1_STATUS__last_seq_step__st_answer 3
+#define R_SCSI1_STATUS__last_seq_step__st_synch_din_perr 1
+#define R_SCSI1_STATUS__last_seq_step__st_transfer_done 15
+#define R_SCSI1_STATUS__last_seq_step__st_synch_dout 0
+#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout 25
+#define R_SCSI1_STATUS__last_seq_step__st_synch_din 13
+#define R_SCSI1_STATUS__last_seq_step__st_asynch_din 9
+#define R_SCSI1_STATUS__last_seq_step__st_synch_dout_ack 4
+#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack 12
+#define R_SCSI1_STATUS__last_seq_step__st_synch_din_ack_perr 5
+#define R_SCSI1_STATUS__last_seq_step__st_asynch_dout_end 11
+#define R_SCSI1_STATUS__last_seq_step__st_iwr 27
+#define R_SCSI1_STATUS__last_seq_step__st_wait_free_disc 21
+#define R_SCSI1_STATUS__last_seq_step__st_sdp_disc 7
+#define R_SCSI1_STATUS__last_seq_step__st_cc 31
+#define R_SCSI1_STATUS__last_seq_step__st_iwr_good 14
+#define R_SCSI1_STATUS__last_seq_step__st_iwr_cc 23
+#define R_SCSI1_STATUS__last_seq_step__st_wait_free_iwr_cc 17
+#define R_SCSI1_STATUS__last_seq_step__st_wait_free_cc 20
+#define R_SCSI1_STATUS__last_seq_step__st_wait_free_sdp_disc 16
+#define R_SCSI1_STATUS__last_seq_step__st_manual_req 10
+#define R_SCSI1_STATUS__last_seq_step__st_manual_din_prot 18
+#define R_SCSI1_STATUS__valid_status__BITNR 5
+#define R_SCSI1_STATUS__valid_status__WIDTH 1
+#define R_SCSI1_STATUS__valid_status__yes 1
+#define R_SCSI1_STATUS__valid_status__no 0
+#define R_SCSI1_STATUS__seq_status__BITNR 0
+#define R_SCSI1_STATUS__seq_status__WIDTH 5
+#define R_SCSI1_STATUS__seq_status__info_seq_complete 0
+#define R_SCSI1_STATUS__seq_status__info_parity_error 1
+#define R_SCSI1_STATUS__seq_status__info_unhandled_msg_in 2
+#define R_SCSI1_STATUS__seq_status__info_unexp_ph_change 3
+#define R_SCSI1_STATUS__seq_status__info_arb_lost 4
+#define R_SCSI1_STATUS__seq_status__info_sel_timeout 5
+#define R_SCSI1_STATUS__seq_status__info_unexp_bf 6
+#define R_SCSI1_STATUS__seq_status__info_illegal_op 7
+#define R_SCSI1_STATUS__seq_status__info_rec_recvd 8
+#define R_SCSI1_STATUS__seq_status__info_reselected 9
+#define R_SCSI1_STATUS__seq_status__info_unhandled_status 10
+#define R_SCSI1_STATUS__seq_status__info_bus_reset 11
+#define R_SCSI1_STATUS__seq_status__info_illegal_bf 12
+#define R_SCSI1_STATUS__seq_status__info_bus_free 13
+
+#define R_SCSI1_DATA_IN (IO_TYPECAST_RO_UWORD 0xb0000050)
+#define R_SCSI1_DATA_IN__data_in__BITNR 0
+#define R_SCSI1_DATA_IN__data_in__WIDTH 16
+
+/*
+!* Interrupt mask and status registers
+!*/
+
+#define R_IRQ_MASK0_RD (IO_TYPECAST_RO_UDWORD 0xb00000c0)
+#define R_IRQ_MASK0_RD__nmi_pin__BITNR 31
+#define R_IRQ_MASK0_RD__nmi_pin__WIDTH 1
+#define R_IRQ_MASK0_RD__nmi_pin__active 1
+#define R_IRQ_MASK0_RD__nmi_pin__inactive 0
+#define R_IRQ_MASK0_RD__watchdog_nmi__BITNR 30
+#define R_IRQ_MASK0_RD__watchdog_nmi__WIDTH 1
+#define R_IRQ_MASK0_RD__watchdog_nmi__active 1
+#define R_IRQ_MASK0_RD__watchdog_nmi__inactive 0
+#define R_IRQ_MASK0_RD__sqe_test_error__BITNR 29
+#define R_IRQ_MASK0_RD__sqe_test_error__WIDTH 1
+#define R_IRQ_MASK0_RD__sqe_test_error__active 1
+#define R_IRQ_MASK0_RD__sqe_test_error__inactive 0
+#define R_IRQ_MASK0_RD__carrier_loss__BITNR 28
+#define R_IRQ_MASK0_RD__carrier_loss__WIDTH 1
+#define R_IRQ_MASK0_RD__carrier_loss__active 1
+#define R_IRQ_MASK0_RD__carrier_loss__inactive 0
+#define R_IRQ_MASK0_RD__deferred__BITNR 27
+#define R_IRQ_MASK0_RD__deferred__WIDTH 1
+#define R_IRQ_MASK0_RD__deferred__active 1
+#define R_IRQ_MASK0_RD__deferred__inactive 0
+#define R_IRQ_MASK0_RD__late_col__BITNR 26
+#define R_IRQ_MASK0_RD__late_col__WIDTH 1
+#define R_IRQ_MASK0_RD__late_col__active 1
+#define R_IRQ_MASK0_RD__late_col__inactive 0
+#define R_IRQ_MASK0_RD__multiple_col__BITNR 25
+#define R_IRQ_MASK0_RD__multiple_col__WIDTH 1
+#define R_IRQ_MASK0_RD__multiple_col__active 1
+#define R_IRQ_MASK0_RD__multiple_col__inactive 0
+#define R_IRQ_MASK0_RD__single_col__BITNR 24
+#define R_IRQ_MASK0_RD__single_col__WIDTH 1
+#define R_IRQ_MASK0_RD__single_col__active 1
+#define R_IRQ_MASK0_RD__single_col__inactive 0
+#define R_IRQ_MASK0_RD__congestion__BITNR 23
+#define R_IRQ_MASK0_RD__congestion__WIDTH 1
+#define R_IRQ_MASK0_RD__congestion__active 1
+#define R_IRQ_MASK0_RD__congestion__inactive 0
+#define R_IRQ_MASK0_RD__oversize__BITNR 22
+#define R_IRQ_MASK0_RD__oversize__WIDTH 1
+#define R_IRQ_MASK0_RD__oversize__active 1
+#define R_IRQ_MASK0_RD__oversize__inactive 0
+#define R_IRQ_MASK0_RD__alignment_error__BITNR 21
+#define R_IRQ_MASK0_RD__alignment_error__WIDTH 1
+#define R_IRQ_MASK0_RD__alignment_error__active 1
+#define R_IRQ_MASK0_RD__alignment_error__inactive 0
+#define R_IRQ_MASK0_RD__crc_error__BITNR 20
+#define R_IRQ_MASK0_RD__crc_error__WIDTH 1
+#define R_IRQ_MASK0_RD__crc_error__active 1
+#define R_IRQ_MASK0_RD__crc_error__inactive 0
+#define R_IRQ_MASK0_RD__overrun__BITNR 19
+#define R_IRQ_MASK0_RD__overrun__WIDTH 1
+#define R_IRQ_MASK0_RD__overrun__active 1
+#define R_IRQ_MASK0_RD__overrun__inactive 0
+#define R_IRQ_MASK0_RD__underrun__BITNR 18
+#define R_IRQ_MASK0_RD__underrun__WIDTH 1
+#define R_IRQ_MASK0_RD__underrun__active 1
+#define R_IRQ_MASK0_RD__underrun__inactive 0
+#define R_IRQ_MASK0_RD__excessive_col__BITNR 17
+#define R_IRQ_MASK0_RD__excessive_col__WIDTH 1
+#define R_IRQ_MASK0_RD__excessive_col__active 1
+#define R_IRQ_MASK0_RD__excessive_col__inactive 0
+#define R_IRQ_MASK0_RD__mdio__BITNR 16
+#define R_IRQ_MASK0_RD__mdio__WIDTH 1
+#define R_IRQ_MASK0_RD__mdio__active 1
+#define R_IRQ_MASK0_RD__mdio__inactive 0
+#define R_IRQ_MASK0_RD__ata_drq3__BITNR 15
+#define R_IRQ_MASK0_RD__ata_drq3__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_drq3__active 1
+#define R_IRQ_MASK0_RD__ata_drq3__inactive 0
+#define R_IRQ_MASK0_RD__ata_drq2__BITNR 14
+#define R_IRQ_MASK0_RD__ata_drq2__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_drq2__active 1
+#define R_IRQ_MASK0_RD__ata_drq2__inactive 0
+#define R_IRQ_MASK0_RD__ata_drq1__BITNR 13
+#define R_IRQ_MASK0_RD__ata_drq1__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_drq1__active 1
+#define R_IRQ_MASK0_RD__ata_drq1__inactive 0
+#define R_IRQ_MASK0_RD__ata_drq0__BITNR 12
+#define R_IRQ_MASK0_RD__ata_drq0__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_drq0__active 1
+#define R_IRQ_MASK0_RD__ata_drq0__inactive 0
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__BITNR 11
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__WIDTH 1
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__active 1
+#define R_IRQ_MASK0_RD__par0_ecp_cmd__inactive 0
+#define R_IRQ_MASK0_RD__ata_irq3__BITNR 11
+#define R_IRQ_MASK0_RD__ata_irq3__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_irq3__active 1
+#define R_IRQ_MASK0_RD__ata_irq3__inactive 0
+#define R_IRQ_MASK0_RD__par0_peri__BITNR 10
+#define R_IRQ_MASK0_RD__par0_peri__WIDTH 1
+#define R_IRQ_MASK0_RD__par0_peri__active 1
+#define R_IRQ_MASK0_RD__par0_peri__inactive 0
+#define R_IRQ_MASK0_RD__ata_irq2__BITNR 10
+#define R_IRQ_MASK0_RD__ata_irq2__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_irq2__active 1
+#define R_IRQ_MASK0_RD__ata_irq2__inactive 0
+#define R_IRQ_MASK0_RD__par0_data__BITNR 9
+#define R_IRQ_MASK0_RD__par0_data__WIDTH 1
+#define R_IRQ_MASK0_RD__par0_data__active 1
+#define R_IRQ_MASK0_RD__par0_data__inactive 0
+#define R_IRQ_MASK0_RD__ata_irq1__BITNR 9
+#define R_IRQ_MASK0_RD__ata_irq1__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_irq1__active 1
+#define R_IRQ_MASK0_RD__ata_irq1__inactive 0
+#define R_IRQ_MASK0_RD__par0_ready__BITNR 8
+#define R_IRQ_MASK0_RD__par0_ready__WIDTH 1
+#define R_IRQ_MASK0_RD__par0_ready__active 1
+#define R_IRQ_MASK0_RD__par0_ready__inactive 0
+#define R_IRQ_MASK0_RD__ata_irq0__BITNR 8
+#define R_IRQ_MASK0_RD__ata_irq0__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_irq0__active 1
+#define R_IRQ_MASK0_RD__ata_irq0__inactive 0
+#define R_IRQ_MASK0_RD__mio__BITNR 8
+#define R_IRQ_MASK0_RD__mio__WIDTH 1
+#define R_IRQ_MASK0_RD__mio__active 1
+#define R_IRQ_MASK0_RD__mio__inactive 0
+#define R_IRQ_MASK0_RD__scsi0__BITNR 8
+#define R_IRQ_MASK0_RD__scsi0__WIDTH 1
+#define R_IRQ_MASK0_RD__scsi0__active 1
+#define R_IRQ_MASK0_RD__scsi0__inactive 0
+#define R_IRQ_MASK0_RD__ata_dmaend__BITNR 7
+#define R_IRQ_MASK0_RD__ata_dmaend__WIDTH 1
+#define R_IRQ_MASK0_RD__ata_dmaend__active 1
+#define R_IRQ_MASK0_RD__ata_dmaend__inactive 0
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__BITNR 5
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__WIDTH 1
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__active 1
+#define R_IRQ_MASK0_RD__irq_ext_vector_nr__inactive 0
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__BITNR 4
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__WIDTH 1
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__active 1
+#define R_IRQ_MASK0_RD__irq_int_vector_nr__inactive 0
+#define R_IRQ_MASK0_RD__ext_dma1__BITNR 3
+#define R_IRQ_MASK0_RD__ext_dma1__WIDTH 1
+#define R_IRQ_MASK0_RD__ext_dma1__active 1
+#define R_IRQ_MASK0_RD__ext_dma1__inactive 0
+#define R_IRQ_MASK0_RD__ext_dma0__BITNR 2
+#define R_IRQ_MASK0_RD__ext_dma0__WIDTH 1
+#define R_IRQ_MASK0_RD__ext_dma0__active 1
+#define R_IRQ_MASK0_RD__ext_dma0__inactive 0
+#define R_IRQ_MASK0_RD__timer1__BITNR 1
+#define R_IRQ_MASK0_RD__timer1__WIDTH 1
+#define R_IRQ_MASK0_RD__timer1__active 1
+#define R_IRQ_MASK0_RD__timer1__inactive 0
+#define R_IRQ_MASK0_RD__timer0__BITNR 0
+#define R_IRQ_MASK0_RD__timer0__WIDTH 1
+#define R_IRQ_MASK0_RD__timer0__active 1
+#define R_IRQ_MASK0_RD__timer0__inactive 0
+
+#define R_IRQ_MASK0_CLR (IO_TYPECAST_UDWORD 0xb00000c0)
+#define R_IRQ_MASK0_CLR__nmi_pin__BITNR 31
+#define R_IRQ_MASK0_CLR__nmi_pin__WIDTH 1
+#define R_IRQ_MASK0_CLR__nmi_pin__clr 1
+#define R_IRQ_MASK0_CLR__nmi_pin__nop 0
+#define R_IRQ_MASK0_CLR__watchdog_nmi__BITNR 30
+#define R_IRQ_MASK0_CLR__watchdog_nmi__WIDTH 1
+#define R_IRQ_MASK0_CLR__watchdog_nmi__clr 1
+#define R_IRQ_MASK0_CLR__watchdog_nmi__nop 0
+#define R_IRQ_MASK0_CLR__sqe_test_error__BITNR 29
+#define R_IRQ_MASK0_CLR__sqe_test_error__WIDTH 1
+#define R_IRQ_MASK0_CLR__sqe_test_error__clr 1
+#define R_IRQ_MASK0_CLR__sqe_test_error__nop 0
+#define R_IRQ_MASK0_CLR__carrier_loss__BITNR 28
+#define R_IRQ_MASK0_CLR__carrier_loss__WIDTH 1
+#define R_IRQ_MASK0_CLR__carrier_loss__clr 1
+#define R_IRQ_MASK0_CLR__carrier_loss__nop 0
+#define R_IRQ_MASK0_CLR__deferred__BITNR 27
+#define R_IRQ_MASK0_CLR__deferred__WIDTH 1
+#define R_IRQ_MASK0_CLR__deferred__clr 1
+#define R_IRQ_MASK0_CLR__deferred__nop 0
+#define R_IRQ_MASK0_CLR__late_col__BITNR 26
+#define R_IRQ_MASK0_CLR__late_col__WIDTH 1
+#define R_IRQ_MASK0_CLR__late_col__clr 1
+#define R_IRQ_MASK0_CLR__late_col__nop 0
+#define R_IRQ_MASK0_CLR__multiple_col__BITNR 25
+#define R_IRQ_MASK0_CLR__multiple_col__WIDTH 1
+#define R_IRQ_MASK0_CLR__multiple_col__clr 1
+#define R_IRQ_MASK0_CLR__multiple_col__nop 0
+#define R_IRQ_MASK0_CLR__single_col__BITNR 24
+#define R_IRQ_MASK0_CLR__single_col__WIDTH 1
+#define R_IRQ_MASK0_CLR__single_col__clr 1
+#define R_IRQ_MASK0_CLR__single_col__nop 0
+#define R_IRQ_MASK0_CLR__congestion__BITNR 23
+#define R_IRQ_MASK0_CLR__congestion__WIDTH 1
+#define R_IRQ_MASK0_CLR__congestion__clr 1
+#define R_IRQ_MASK0_CLR__congestion__nop 0
+#define R_IRQ_MASK0_CLR__oversize__BITNR 22
+#define R_IRQ_MASK0_CLR__oversize__WIDTH 1
+#define R_IRQ_MASK0_CLR__oversize__clr 1
+#define R_IRQ_MASK0_CLR__oversize__nop 0
+#define R_IRQ_MASK0_CLR__alignment_error__BITNR 21
+#define R_IRQ_MASK0_CLR__alignment_error__WIDTH 1
+#define R_IRQ_MASK0_CLR__alignment_error__clr 1
+#define R_IRQ_MASK0_CLR__alignment_error__nop 0
+#define R_IRQ_MASK0_CLR__crc_error__BITNR 20
+#define R_IRQ_MASK0_CLR__crc_error__WIDTH 1
+#define R_IRQ_MASK0_CLR__crc_error__clr 1
+#define R_IRQ_MASK0_CLR__crc_error__nop 0
+#define R_IRQ_MASK0_CLR__overrun__BITNR 19
+#define R_IRQ_MASK0_CLR__overrun__WIDTH 1
+#define R_IRQ_MASK0_CLR__overrun__clr 1
+#define R_IRQ_MASK0_CLR__overrun__nop 0
+#define R_IRQ_MASK0_CLR__underrun__BITNR 18
+#define R_IRQ_MASK0_CLR__underrun__WIDTH 1
+#define R_IRQ_MASK0_CLR__underrun__clr 1
+#define R_IRQ_MASK0_CLR__underrun__nop 0
+#define R_IRQ_MASK0_CLR__excessive_col__BITNR 17
+#define R_IRQ_MASK0_CLR__excessive_col__WIDTH 1
+#define R_IRQ_MASK0_CLR__excessive_col__clr 1
+#define R_IRQ_MASK0_CLR__excessive_col__nop 0
+#define R_IRQ_MASK0_CLR__mdio__BITNR 16
+#define R_IRQ_MASK0_CLR__mdio__WIDTH 1
+#define R_IRQ_MASK0_CLR__mdio__clr 1
+#define R_IRQ_MASK0_CLR__mdio__nop 0
+#define R_IRQ_MASK0_CLR__ata_drq3__BITNR 15
+#define R_IRQ_MASK0_CLR__ata_drq3__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_drq3__clr 1
+#define R_IRQ_MASK0_CLR__ata_drq3__nop 0
+#define R_IRQ_MASK0_CLR__ata_drq2__BITNR 14
+#define R_IRQ_MASK0_CLR__ata_drq2__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_drq2__clr 1
+#define R_IRQ_MASK0_CLR__ata_drq2__nop 0
+#define R_IRQ_MASK0_CLR__ata_drq1__BITNR 13
+#define R_IRQ_MASK0_CLR__ata_drq1__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_drq1__clr 1
+#define R_IRQ_MASK0_CLR__ata_drq1__nop 0
+#define R_IRQ_MASK0_CLR__ata_drq0__BITNR 12
+#define R_IRQ_MASK0_CLR__ata_drq0__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_drq0__clr 1
+#define R_IRQ_MASK0_CLR__ata_drq0__nop 0
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__BITNR 11
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__WIDTH 1
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__clr 1
+#define R_IRQ_MASK0_CLR__par0_ecp_cmd__nop 0
+#define R_IRQ_MASK0_CLR__ata_irq3__BITNR 11
+#define R_IRQ_MASK0_CLR__ata_irq3__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_irq3__clr 1
+#define R_IRQ_MASK0_CLR__ata_irq3__nop 0
+#define R_IRQ_MASK0_CLR__par0_peri__BITNR 10
+#define R_IRQ_MASK0_CLR__par0_peri__WIDTH 1
+#define R_IRQ_MASK0_CLR__par0_peri__clr 1
+#define R_IRQ_MASK0_CLR__par0_peri__nop 0
+#define R_IRQ_MASK0_CLR__ata_irq2__BITNR 10
+#define R_IRQ_MASK0_CLR__ata_irq2__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_irq2__clr 1
+#define R_IRQ_MASK0_CLR__ata_irq2__nop 0
+#define R_IRQ_MASK0_CLR__par0_data__BITNR 9
+#define R_IRQ_MASK0_CLR__par0_data__WIDTH 1
+#define R_IRQ_MASK0_CLR__par0_data__clr 1
+#define R_IRQ_MASK0_CLR__par0_data__nop 0
+#define R_IRQ_MASK0_CLR__ata_irq1__BITNR 9
+#define R_IRQ_MASK0_CLR__ata_irq1__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_irq1__clr 1
+#define R_IRQ_MASK0_CLR__ata_irq1__nop 0
+#define R_IRQ_MASK0_CLR__par0_ready__BITNR 8
+#define R_IRQ_MASK0_CLR__par0_ready__WIDTH 1
+#define R_IRQ_MASK0_CLR__par0_ready__clr 1
+#define R_IRQ_MASK0_CLR__par0_ready__nop 0
+#define R_IRQ_MASK0_CLR__ata_irq0__BITNR 8
+#define R_IRQ_MASK0_CLR__ata_irq0__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_irq0__clr 1
+#define R_IRQ_MASK0_CLR__ata_irq0__nop 0
+#define R_IRQ_MASK0_CLR__mio__BITNR 8
+#define R_IRQ_MASK0_CLR__mio__WIDTH 1
+#define R_IRQ_MASK0_CLR__mio__clr 1
+#define R_IRQ_MASK0_CLR__mio__nop 0
+#define R_IRQ_MASK0_CLR__scsi0__BITNR 8
+#define R_IRQ_MASK0_CLR__scsi0__WIDTH 1
+#define R_IRQ_MASK0_CLR__scsi0__clr 1
+#define R_IRQ_MASK0_CLR__scsi0__nop 0
+#define R_IRQ_MASK0_CLR__ata_dmaend__BITNR 7
+#define R_IRQ_MASK0_CLR__ata_dmaend__WIDTH 1
+#define R_IRQ_MASK0_CLR__ata_dmaend__clr 1
+#define R_IRQ_MASK0_CLR__ata_dmaend__nop 0
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__BITNR 5
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__WIDTH 1
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__clr 1
+#define R_IRQ_MASK0_CLR__irq_ext_vector_nr__nop 0
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__BITNR 4
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__WIDTH 1
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__clr 1
+#define R_IRQ_MASK0_CLR__irq_int_vector_nr__nop 0
+#define R_IRQ_MASK0_CLR__ext_dma1__BITNR 3
+#define R_IRQ_MASK0_CLR__ext_dma1__WIDTH 1
+#define R_IRQ_MASK0_CLR__ext_dma1__clr 1
+#define R_IRQ_MASK0_CLR__ext_dma1__nop 0
+#define R_IRQ_MASK0_CLR__ext_dma0__BITNR 2
+#define R_IRQ_MASK0_CLR__ext_dma0__WIDTH 1
+#define R_IRQ_MASK0_CLR__ext_dma0__clr 1
+#define R_IRQ_MASK0_CLR__ext_dma0__nop 0
+#define R_IRQ_MASK0_CLR__timer1__BITNR 1
+#define R_IRQ_MASK0_CLR__timer1__WIDTH 1
+#define R_IRQ_MASK0_CLR__timer1__clr 1
+#define R_IRQ_MASK0_CLR__timer1__nop 0
+#define R_IRQ_MASK0_CLR__timer0__BITNR 0
+#define R_IRQ_MASK0_CLR__timer0__WIDTH 1
+#define R_IRQ_MASK0_CLR__timer0__clr 1
+#define R_IRQ_MASK0_CLR__timer0__nop 0
+
+#define R_IRQ_READ0 (IO_TYPECAST_RO_UDWORD 0xb00000c4)
+#define R_IRQ_READ0__nmi_pin__BITNR 31
+#define R_IRQ_READ0__nmi_pin__WIDTH 1
+#define R_IRQ_READ0__nmi_pin__active 1
+#define R_IRQ_READ0__nmi_pin__inactive 0
+#define R_IRQ_READ0__watchdog_nmi__BITNR 30
+#define R_IRQ_READ0__watchdog_nmi__WIDTH 1
+#define R_IRQ_READ0__watchdog_nmi__active 1
+#define R_IRQ_READ0__watchdog_nmi__inactive 0
+#define R_IRQ_READ0__sqe_test_error__BITNR 29
+#define R_IRQ_READ0__sqe_test_error__WIDTH 1
+#define R_IRQ_READ0__sqe_test_error__active 1
+#define R_IRQ_READ0__sqe_test_error__inactive 0
+#define R_IRQ_READ0__carrier_loss__BITNR 28
+#define R_IRQ_READ0__carrier_loss__WIDTH 1
+#define R_IRQ_READ0__carrier_loss__active 1
+#define R_IRQ_READ0__carrier_loss__inactive 0
+#define R_IRQ_READ0__deferred__BITNR 27
+#define R_IRQ_READ0__deferred__WIDTH 1
+#define R_IRQ_READ0__deferred__active 1
+#define R_IRQ_READ0__deferred__inactive 0
+#define R_IRQ_READ0__late_col__BITNR 26
+#define R_IRQ_READ0__late_col__WIDTH 1
+#define R_IRQ_READ0__late_col__active 1
+#define R_IRQ_READ0__late_col__inactive 0
+#define R_IRQ_READ0__multiple_col__BITNR 25
+#define R_IRQ_READ0__multiple_col__WIDTH 1
+#define R_IRQ_READ0__multiple_col__active 1
+#define R_IRQ_READ0__multiple_col__inactive 0
+#define R_IRQ_READ0__single_col__BITNR 24
+#define R_IRQ_READ0__single_col__WIDTH 1
+#define R_IRQ_READ0__single_col__active 1
+#define R_IRQ_READ0__single_col__inactive 0
+#define R_IRQ_READ0__congestion__BITNR 23
+#define R_IRQ_READ0__congestion__WIDTH 1
+#define R_IRQ_READ0__congestion__active 1
+#define R_IRQ_READ0__congestion__inactive 0
+#define R_IRQ_READ0__oversize__BITNR 22
+#define R_IRQ_READ0__oversize__WIDTH 1
+#define R_IRQ_READ0__oversize__active 1
+#define R_IRQ_READ0__oversize__inactive 0
+#define R_IRQ_READ0__alignment_error__BITNR 21
+#define R_IRQ_READ0__alignment_error__WIDTH 1
+#define R_IRQ_READ0__alignment_error__active 1
+#define R_IRQ_READ0__alignment_error__inactive 0
+#define R_IRQ_READ0__crc_error__BITNR 20
+#define R_IRQ_READ0__crc_error__WIDTH 1
+#define R_IRQ_READ0__crc_error__active 1
+#define R_IRQ_READ0__crc_error__inactive 0
+#define R_IRQ_READ0__overrun__BITNR 19
+#define R_IRQ_READ0__overrun__WIDTH 1
+#define R_IRQ_READ0__overrun__active 1
+#define R_IRQ_READ0__overrun__inactive 0
+#define R_IRQ_READ0__underrun__BITNR 18
+#define R_IRQ_READ0__underrun__WIDTH 1
+#define R_IRQ_READ0__underrun__active 1
+#define R_IRQ_READ0__underrun__inactive 0
+#define R_IRQ_READ0__excessive_col__BITNR 17
+#define R_IRQ_READ0__excessive_col__WIDTH 1
+#define R_IRQ_READ0__excessive_col__active 1
+#define R_IRQ_READ0__excessive_col__inactive 0
+#define R_IRQ_READ0__mdio__BITNR 16
+#define R_IRQ_READ0__mdio__WIDTH 1
+#define R_IRQ_READ0__mdio__active 1
+#define R_IRQ_READ0__mdio__inactive 0
+#define R_IRQ_READ0__ata_drq3__BITNR 15
+#define R_IRQ_READ0__ata_drq3__WIDTH 1
+#define R_IRQ_READ0__ata_drq3__active 1
+#define R_IRQ_READ0__ata_drq3__inactive 0
+#define R_IRQ_READ0__ata_drq2__BITNR 14
+#define R_IRQ_READ0__ata_drq2__WIDTH 1
+#define R_IRQ_READ0__ata_drq2__active 1
+#define R_IRQ_READ0__ata_drq2__inactive 0
+#define R_IRQ_READ0__ata_drq1__BITNR 13
+#define R_IRQ_READ0__ata_drq1__WIDTH 1
+#define R_IRQ_READ0__ata_drq1__active 1
+#define R_IRQ_READ0__ata_drq1__inactive 0
+#define R_IRQ_READ0__ata_drq0__BITNR 12
+#define R_IRQ_READ0__ata_drq0__WIDTH 1
+#define R_IRQ_READ0__ata_drq0__active 1
+#define R_IRQ_READ0__ata_drq0__inactive 0
+#define R_IRQ_READ0__par0_ecp_cmd__BITNR 11
+#define R_IRQ_READ0__par0_ecp_cmd__WIDTH 1
+#define R_IRQ_READ0__par0_ecp_cmd__active 1
+#define R_IRQ_READ0__par0_ecp_cmd__inactive 0
+#define R_IRQ_READ0__ata_irq3__BITNR 11
+#define R_IRQ_READ0__ata_irq3__WIDTH 1
+#define R_IRQ_READ0__ata_irq3__active 1
+#define R_IRQ_READ0__ata_irq3__inactive 0
+#define R_IRQ_READ0__par0_peri__BITNR 10
+#define R_IRQ_READ0__par0_peri__WIDTH 1
+#define R_IRQ_READ0__par0_peri__active 1
+#define R_IRQ_READ0__par0_peri__inactive 0
+#define R_IRQ_READ0__ata_irq2__BITNR 10
+#define R_IRQ_READ0__ata_irq2__WIDTH 1
+#define R_IRQ_READ0__ata_irq2__active 1
+#define R_IRQ_READ0__ata_irq2__inactive 0
+#define R_IRQ_READ0__par0_data__BITNR 9
+#define R_IRQ_READ0__par0_data__WIDTH 1
+#define R_IRQ_READ0__par0_data__active 1
+#define R_IRQ_READ0__par0_data__inactive 0
+#define R_IRQ_READ0__ata_irq1__BITNR 9
+#define R_IRQ_READ0__ata_irq1__WIDTH 1
+#define R_IRQ_READ0__ata_irq1__active 1
+#define R_IRQ_READ0__ata_irq1__inactive 0
+#define R_IRQ_READ0__par0_ready__BITNR 8
+#define R_IRQ_READ0__par0_ready__WIDTH 1
+#define R_IRQ_READ0__par0_ready__active 1
+#define R_IRQ_READ0__par0_ready__inactive 0
+#define R_IRQ_READ0__ata_irq0__BITNR 8
+#define R_IRQ_READ0__ata_irq0__WIDTH 1
+#define R_IRQ_READ0__ata_irq0__active 1
+#define R_IRQ_READ0__ata_irq0__inactive 0
+#define R_IRQ_READ0__mio__BITNR 8
+#define R_IRQ_READ0__mio__WIDTH 1
+#define R_IRQ_READ0__mio__active 1
+#define R_IRQ_READ0__mio__inactive 0
+#define R_IRQ_READ0__scsi0__BITNR 8
+#define R_IRQ_READ0__scsi0__WIDTH 1
+#define R_IRQ_READ0__scsi0__active 1
+#define R_IRQ_READ0__scsi0__inactive 0
+#define R_IRQ_READ0__ata_dmaend__BITNR 7
+#define R_IRQ_READ0__ata_dmaend__WIDTH 1
+#define R_IRQ_READ0__ata_dmaend__active 1
+#define R_IRQ_READ0__ata_dmaend__inactive 0
+#define R_IRQ_READ0__irq_ext_vector_nr__BITNR 5
+#define R_IRQ_READ0__irq_ext_vector_nr__WIDTH 1
+#define R_IRQ_READ0__irq_ext_vector_nr__active 1
+#define R_IRQ_READ0__irq_ext_vector_nr__inactive 0
+#define R_IRQ_READ0__irq_int_vector_nr__BITNR 4
+#define R_IRQ_READ0__irq_int_vector_nr__WIDTH 1
+#define R_IRQ_READ0__irq_int_vector_nr__active 1
+#define R_IRQ_READ0__irq_int_vector_nr__inactive 0
+#define R_IRQ_READ0__ext_dma1__BITNR 3
+#define R_IRQ_READ0__ext_dma1__WIDTH 1
+#define R_IRQ_READ0__ext_dma1__active 1
+#define R_IRQ_READ0__ext_dma1__inactive 0
+#define R_IRQ_READ0__ext_dma0__BITNR 2
+#define R_IRQ_READ0__ext_dma0__WIDTH 1
+#define R_IRQ_READ0__ext_dma0__active 1
+#define R_IRQ_READ0__ext_dma0__inactive 0
+#define R_IRQ_READ0__timer1__BITNR 1
+#define R_IRQ_READ0__timer1__WIDTH 1
+#define R_IRQ_READ0__timer1__active 1
+#define R_IRQ_READ0__timer1__inactive 0
+#define R_IRQ_READ0__timer0__BITNR 0
+#define R_IRQ_READ0__timer0__WIDTH 1
+#define R_IRQ_READ0__timer0__active 1
+#define R_IRQ_READ0__timer0__inactive 0
+
+#define R_IRQ_MASK0_SET (IO_TYPECAST_UDWORD 0xb00000c4)
+#define R_IRQ_MASK0_SET__nmi_pin__BITNR 31
+#define R_IRQ_MASK0_SET__nmi_pin__WIDTH 1
+#define R_IRQ_MASK0_SET__nmi_pin__set 1
+#define R_IRQ_MASK0_SET__nmi_pin__nop 0
+#define R_IRQ_MASK0_SET__watchdog_nmi__BITNR 30
+#define R_IRQ_MASK0_SET__watchdog_nmi__WIDTH 1
+#define R_IRQ_MASK0_SET__watchdog_nmi__set 1
+#define R_IRQ_MASK0_SET__watchdog_nmi__nop 0
+#define R_IRQ_MASK0_SET__sqe_test_error__BITNR 29
+#define R_IRQ_MASK0_SET__sqe_test_error__WIDTH 1
+#define R_IRQ_MASK0_SET__sqe_test_error__set 1
+#define R_IRQ_MASK0_SET__sqe_test_error__nop 0
+#define R_IRQ_MASK0_SET__carrier_loss__BITNR 28
+#define R_IRQ_MASK0_SET__carrier_loss__WIDTH 1
+#define R_IRQ_MASK0_SET__carrier_loss__set 1
+#define R_IRQ_MASK0_SET__carrier_loss__nop 0
+#define R_IRQ_MASK0_SET__deferred__BITNR 27
+#define R_IRQ_MASK0_SET__deferred__WIDTH 1
+#define R_IRQ_MASK0_SET__deferred__set 1
+#define R_IRQ_MASK0_SET__deferred__nop 0
+#define R_IRQ_MASK0_SET__late_col__BITNR 26
+#define R_IRQ_MASK0_SET__late_col__WIDTH 1
+#define R_IRQ_MASK0_SET__late_col__set 1
+#define R_IRQ_MASK0_SET__late_col__nop 0
+#define R_IRQ_MASK0_SET__multiple_col__BITNR 25
+#define R_IRQ_MASK0_SET__multiple_col__WIDTH 1
+#define R_IRQ_MASK0_SET__multiple_col__set 1
+#define R_IRQ_MASK0_SET__multiple_col__nop 0
+#define R_IRQ_MASK0_SET__single_col__BITNR 24
+#define R_IRQ_MASK0_SET__single_col__WIDTH 1
+#define R_IRQ_MASK0_SET__single_col__set 1
+#define R_IRQ_MASK0_SET__single_col__nop 0
+#define R_IRQ_MASK0_SET__congestion__BITNR 23
+#define R_IRQ_MASK0_SET__congestion__WIDTH 1
+#define R_IRQ_MASK0_SET__congestion__set 1
+#define R_IRQ_MASK0_SET__congestion__nop 0
+#define R_IRQ_MASK0_SET__oversize__BITNR 22
+#define R_IRQ_MASK0_SET__oversize__WIDTH 1
+#define R_IRQ_MASK0_SET__oversize__set 1
+#define R_IRQ_MASK0_SET__oversize__nop 0
+#define R_IRQ_MASK0_SET__alignment_error__BITNR 21
+#define R_IRQ_MASK0_SET__alignment_error__WIDTH 1
+#define R_IRQ_MASK0_SET__alignment_error__set 1
+#define R_IRQ_MASK0_SET__alignment_error__nop 0
+#define R_IRQ_MASK0_SET__crc_error__BITNR 20
+#define R_IRQ_MASK0_SET__crc_error__WIDTH 1
+#define R_IRQ_MASK0_SET__crc_error__set 1
+#define R_IRQ_MASK0_SET__crc_error__nop 0
+#define R_IRQ_MASK0_SET__overrun__BITNR 19
+#define R_IRQ_MASK0_SET__overrun__WIDTH 1
+#define R_IRQ_MASK0_SET__overrun__set 1
+#define R_IRQ_MASK0_SET__overrun__nop 0
+#define R_IRQ_MASK0_SET__underrun__BITNR 18
+#define R_IRQ_MASK0_SET__underrun__WIDTH 1
+#define R_IRQ_MASK0_SET__underrun__set 1
+#define R_IRQ_MASK0_SET__underrun__nop 0
+#define R_IRQ_MASK0_SET__excessive_col__BITNR 17
+#define R_IRQ_MASK0_SET__excessive_col__WIDTH 1
+#define R_IRQ_MASK0_SET__excessive_col__set 1
+#define R_IRQ_MASK0_SET__excessive_col__nop 0
+#define R_IRQ_MASK0_SET__mdio__BITNR 16
+#define R_IRQ_MASK0_SET__mdio__WIDTH 1
+#define R_IRQ_MASK0_SET__mdio__set 1
+#define R_IRQ_MASK0_SET__mdio__nop 0
+#define R_IRQ_MASK0_SET__ata_drq3__BITNR 15
+#define R_IRQ_MASK0_SET__ata_drq3__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_drq3__set 1
+#define R_IRQ_MASK0_SET__ata_drq3__nop 0
+#define R_IRQ_MASK0_SET__ata_drq2__BITNR 14
+#define R_IRQ_MASK0_SET__ata_drq2__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_drq2__set 1
+#define R_IRQ_MASK0_SET__ata_drq2__nop 0
+#define R_IRQ_MASK0_SET__ata_drq1__BITNR 13
+#define R_IRQ_MASK0_SET__ata_drq1__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_drq1__set 1
+#define R_IRQ_MASK0_SET__ata_drq1__nop 0
+#define R_IRQ_MASK0_SET__ata_drq0__BITNR 12
+#define R_IRQ_MASK0_SET__ata_drq0__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_drq0__set 1
+#define R_IRQ_MASK0_SET__ata_drq0__nop 0
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__BITNR 11
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__WIDTH 1
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__set 1
+#define R_IRQ_MASK0_SET__par0_ecp_cmd__nop 0
+#define R_IRQ_MASK0_SET__ata_irq3__BITNR 11
+#define R_IRQ_MASK0_SET__ata_irq3__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_irq3__set 1
+#define R_IRQ_MASK0_SET__ata_irq3__nop 0
+#define R_IRQ_MASK0_SET__par0_peri__BITNR 10
+#define R_IRQ_MASK0_SET__par0_peri__WIDTH 1
+#define R_IRQ_MASK0_SET__par0_peri__set 1
+#define R_IRQ_MASK0_SET__par0_peri__nop 0
+#define R_IRQ_MASK0_SET__ata_irq2__BITNR 10
+#define R_IRQ_MASK0_SET__ata_irq2__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_irq2__set 1
+#define R_IRQ_MASK0_SET__ata_irq2__nop 0
+#define R_IRQ_MASK0_SET__par0_data__BITNR 9
+#define R_IRQ_MASK0_SET__par0_data__WIDTH 1
+#define R_IRQ_MASK0_SET__par0_data__set 1
+#define R_IRQ_MASK0_SET__par0_data__nop 0
+#define R_IRQ_MASK0_SET__ata_irq1__BITNR 9
+#define R_IRQ_MASK0_SET__ata_irq1__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_irq1__set 1
+#define R_IRQ_MASK0_SET__ata_irq1__nop 0
+#define R_IRQ_MASK0_SET__par0_ready__BITNR 8
+#define R_IRQ_MASK0_SET__par0_ready__WIDTH 1
+#define R_IRQ_MASK0_SET__par0_ready__set 1
+#define R_IRQ_MASK0_SET__par0_ready__nop 0
+#define R_IRQ_MASK0_SET__ata_irq0__BITNR 8
+#define R_IRQ_MASK0_SET__ata_irq0__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_irq0__set 1
+#define R_IRQ_MASK0_SET__ata_irq0__nop 0
+#define R_IRQ_MASK0_SET__mio__BITNR 8
+#define R_IRQ_MASK0_SET__mio__WIDTH 1
+#define R_IRQ_MASK0_SET__mio__set 1
+#define R_IRQ_MASK0_SET__mio__nop 0
+#define R_IRQ_MASK0_SET__scsi0__BITNR 8
+#define R_IRQ_MASK0_SET__scsi0__WIDTH 1
+#define R_IRQ_MASK0_SET__scsi0__set 1
+#define R_IRQ_MASK0_SET__scsi0__nop 0
+#define R_IRQ_MASK0_SET__ata_dmaend__BITNR 7
+#define R_IRQ_MASK0_SET__ata_dmaend__WIDTH 1
+#define R_IRQ_MASK0_SET__ata_dmaend__set 1
+#define R_IRQ_MASK0_SET__ata_dmaend__nop 0
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__BITNR 5
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__WIDTH 1
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__set 1
+#define R_IRQ_MASK0_SET__irq_ext_vector_nr__nop 0
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__BITNR 4
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__WIDTH 1
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__set 1
+#define R_IRQ_MASK0_SET__irq_int_vector_nr__nop 0
+#define R_IRQ_MASK0_SET__ext_dma1__BITNR 3
+#define R_IRQ_MASK0_SET__ext_dma1__WIDTH 1
+#define R_IRQ_MASK0_SET__ext_dma1__set 1
+#define R_IRQ_MASK0_SET__ext_dma1__nop 0
+#define R_IRQ_MASK0_SET__ext_dma0__BITNR 2
+#define R_IRQ_MASK0_SET__ext_dma0__WIDTH 1
+#define R_IRQ_MASK0_SET__ext_dma0__set 1
+#define R_IRQ_MASK0_SET__ext_dma0__nop 0
+#define R_IRQ_MASK0_SET__timer1__BITNR 1
+#define R_IRQ_MASK0_SET__timer1__WIDTH 1
+#define R_IRQ_MASK0_SET__timer1__set 1
+#define R_IRQ_MASK0_SET__timer1__nop 0
+#define R_IRQ_MASK0_SET__timer0__BITNR 0
+#define R_IRQ_MASK0_SET__timer0__WIDTH 1
+#define R_IRQ_MASK0_SET__timer0__set 1
+#define R_IRQ_MASK0_SET__timer0__nop 0
+
+#define R_IRQ_MASK1_RD (IO_TYPECAST_RO_UDWORD 0xb00000c8)
+#define R_IRQ_MASK1_RD__sw_int7__BITNR 31
+#define R_IRQ_MASK1_RD__sw_int7__WIDTH 1
+#define R_IRQ_MASK1_RD__sw_int7__active 1
+#define R_IRQ_MASK1_RD__sw_int7__inactive 0
+#define R_IRQ_MASK1_RD__sw_int6__BITNR 30
+#define R_IRQ_MASK1_RD__sw_int6__WIDTH 1
+#define R_IRQ_MASK1_RD__sw_int6__active 1
+#define R_IRQ_MASK1_RD__sw_int6__inactive 0
+#define R_IRQ_MASK1_RD__sw_int5__BITNR 29
+#define R_IRQ_MASK1_RD__sw_int5__WIDTH 1
+#define R_IRQ_MASK1_RD__sw_int5__active 1
+#define R_IRQ_MASK1_RD__sw_int5__inactive 0
+#define R_IRQ_MASK1_RD__sw_int4__BITNR 28
+#define R_IRQ_MASK1_RD__sw_int4__WIDTH 1
+#define R_IRQ_MASK1_RD__sw_int4__active 1
+#define R_IRQ_MASK1_RD__sw_int4__inactive 0
+#define R_IRQ_MASK1_RD__sw_int3__BITNR 27
+#define R_IRQ_MASK1_RD__sw_int3__WIDTH 1
+#define R_IRQ_MASK1_RD__sw_int3__active 1
+#define R_IRQ_MASK1_RD__sw_int3__inactive 0
+#define R_IRQ_MASK1_RD__sw_int2__BITNR 26
+#define R_IRQ_MASK1_RD__sw_int2__WIDTH 1
+#define R_IRQ_MASK1_RD__sw_int2__active 1
+#define R_IRQ_MASK1_RD__sw_int2__inactive 0
+#define R_IRQ_MASK1_RD__sw_int1__BITNR 25
+#define R_IRQ_MASK1_RD__sw_int1__WIDTH 1
+#define R_IRQ_MASK1_RD__sw_int1__active 1
+#define R_IRQ_MASK1_RD__sw_int1__inactive 0
+#define R_IRQ_MASK1_RD__sw_int0__BITNR 24
+#define R_IRQ_MASK1_RD__sw_int0__WIDTH 1
+#define R_IRQ_MASK1_RD__sw_int0__active 1
+#define R_IRQ_MASK1_RD__sw_int0__inactive 0
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__BITNR 19
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__WIDTH 1
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__active 1
+#define R_IRQ_MASK1_RD__par1_ecp_cmd__inactive 0
+#define R_IRQ_MASK1_RD__par1_peri__BITNR 18
+#define R_IRQ_MASK1_RD__par1_peri__WIDTH 1
+#define R_IRQ_MASK1_RD__par1_peri__active 1
+#define R_IRQ_MASK1_RD__par1_peri__inactive 0
+#define R_IRQ_MASK1_RD__par1_data__BITNR 17
+#define R_IRQ_MASK1_RD__par1_data__WIDTH 1
+#define R_IRQ_MASK1_RD__par1_data__active 1
+#define R_IRQ_MASK1_RD__par1_data__inactive 0
+#define R_IRQ_MASK1_RD__par1_ready__BITNR 16
+#define R_IRQ_MASK1_RD__par1_ready__WIDTH 1
+#define R_IRQ_MASK1_RD__par1_ready__active 1
+#define R_IRQ_MASK1_RD__par1_ready__inactive 0
+#define R_IRQ_MASK1_RD__scsi1__BITNR 16
+#define R_IRQ_MASK1_RD__scsi1__WIDTH 1
+#define R_IRQ_MASK1_RD__scsi1__active 1
+#define R_IRQ_MASK1_RD__scsi1__inactive 0
+#define R_IRQ_MASK1_RD__ser3_ready__BITNR 15
+#define R_IRQ_MASK1_RD__ser3_ready__WIDTH 1
+#define R_IRQ_MASK1_RD__ser3_ready__active 1
+#define R_IRQ_MASK1_RD__ser3_ready__inactive 0
+#define R_IRQ_MASK1_RD__ser3_data__BITNR 14
+#define R_IRQ_MASK1_RD__ser3_data__WIDTH 1
+#define R_IRQ_MASK1_RD__ser3_data__active 1
+#define R_IRQ_MASK1_RD__ser3_data__inactive 0
+#define R_IRQ_MASK1_RD__ser2_ready__BITNR 13
+#define R_IRQ_MASK1_RD__ser2_ready__WIDTH 1
+#define R_IRQ_MASK1_RD__ser2_ready__active 1
+#define R_IRQ_MASK1_RD__ser2_ready__inactive 0
+#define R_IRQ_MASK1_RD__ser2_data__BITNR 12
+#define R_IRQ_MASK1_RD__ser2_data__WIDTH 1
+#define R_IRQ_MASK1_RD__ser2_data__active 1
+#define R_IRQ_MASK1_RD__ser2_data__inactive 0
+#define R_IRQ_MASK1_RD__ser1_ready__BITNR 11
+#define R_IRQ_MASK1_RD__ser1_ready__WIDTH 1
+#define R_IRQ_MASK1_RD__ser1_ready__active 1
+#define R_IRQ_MASK1_RD__ser1_ready__inactive 0
+#define R_IRQ_MASK1_RD__ser1_data__BITNR 10
+#define R_IRQ_MASK1_RD__ser1_data__WIDTH 1
+#define R_IRQ_MASK1_RD__ser1_data__active 1
+#define R_IRQ_MASK1_RD__ser1_data__inactive 0
+#define R_IRQ_MASK1_RD__ser0_ready__BITNR 9
+#define R_IRQ_MASK1_RD__ser0_ready__WIDTH 1
+#define R_IRQ_MASK1_RD__ser0_ready__active 1
+#define R_IRQ_MASK1_RD__ser0_ready__inactive 0
+#define R_IRQ_MASK1_RD__ser0_data__BITNR 8
+#define R_IRQ_MASK1_RD__ser0_data__WIDTH 1
+#define R_IRQ_MASK1_RD__ser0_data__active 1
+#define R_IRQ_MASK1_RD__ser0_data__inactive 0
+#define R_IRQ_MASK1_RD__pa7__BITNR 7
+#define R_IRQ_MASK1_RD__pa7__WIDTH 1
+#define R_IRQ_MASK1_RD__pa7__active 1
+#define R_IRQ_MASK1_RD__pa7__inactive 0
+#define R_IRQ_MASK1_RD__pa6__BITNR 6
+#define R_IRQ_MASK1_RD__pa6__WIDTH 1
+#define R_IRQ_MASK1_RD__pa6__active 1
+#define R_IRQ_MASK1_RD__pa6__inactive 0
+#define R_IRQ_MASK1_RD__pa5__BITNR 5
+#define R_IRQ_MASK1_RD__pa5__WIDTH 1
+#define R_IRQ_MASK1_RD__pa5__active 1
+#define R_IRQ_MASK1_RD__pa5__inactive 0
+#define R_IRQ_MASK1_RD__pa4__BITNR 4
+#define R_IRQ_MASK1_RD__pa4__WIDTH 1
+#define R_IRQ_MASK1_RD__pa4__active 1
+#define R_IRQ_MASK1_RD__pa4__inactive 0
+#define R_IRQ_MASK1_RD__pa3__BITNR 3
+#define R_IRQ_MASK1_RD__pa3__WIDTH 1
+#define R_IRQ_MASK1_RD__pa3__active 1
+#define R_IRQ_MASK1_RD__pa3__inactive 0
+#define R_IRQ_MASK1_RD__pa2__BITNR 2
+#define R_IRQ_MASK1_RD__pa2__WIDTH 1
+#define R_IRQ_MASK1_RD__pa2__active 1
+#define R_IRQ_MASK1_RD__pa2__inactive 0
+#define R_IRQ_MASK1_RD__pa1__BITNR 1
+#define R_IRQ_MASK1_RD__pa1__WIDTH 1
+#define R_IRQ_MASK1_RD__pa1__active 1
+#define R_IRQ_MASK1_RD__pa1__inactive 0
+#define R_IRQ_MASK1_RD__pa0__BITNR 0
+#define R_IRQ_MASK1_RD__pa0__WIDTH 1
+#define R_IRQ_MASK1_RD__pa0__active 1
+#define R_IRQ_MASK1_RD__pa0__inactive 0
+
+#define R_IRQ_MASK1_CLR (IO_TYPECAST_UDWORD 0xb00000c8)
+#define R_IRQ_MASK1_CLR__sw_int7__BITNR 31
+#define R_IRQ_MASK1_CLR__sw_int7__WIDTH 1
+#define R_IRQ_MASK1_CLR__sw_int7__clr 1
+#define R_IRQ_MASK1_CLR__sw_int7__nop 0
+#define R_IRQ_MASK1_CLR__sw_int6__BITNR 30
+#define R_IRQ_MASK1_CLR__sw_int6__WIDTH 1
+#define R_IRQ_MASK1_CLR__sw_int6__clr 1
+#define R_IRQ_MASK1_CLR__sw_int6__nop 0
+#define R_IRQ_MASK1_CLR__sw_int5__BITNR 29
+#define R_IRQ_MASK1_CLR__sw_int5__WIDTH 1
+#define R_IRQ_MASK1_CLR__sw_int5__clr 1
+#define R_IRQ_MASK1_CLR__sw_int5__nop 0
+#define R_IRQ_MASK1_CLR__sw_int4__BITNR 28
+#define R_IRQ_MASK1_CLR__sw_int4__WIDTH 1
+#define R_IRQ_MASK1_CLR__sw_int4__clr 1
+#define R_IRQ_MASK1_CLR__sw_int4__nop 0
+#define R_IRQ_MASK1_CLR__sw_int3__BITNR 27
+#define R_IRQ_MASK1_CLR__sw_int3__WIDTH 1
+#define R_IRQ_MASK1_CLR__sw_int3__clr 1
+#define R_IRQ_MASK1_CLR__sw_int3__nop 0
+#define R_IRQ_MASK1_CLR__sw_int2__BITNR 26
+#define R_IRQ_MASK1_CLR__sw_int2__WIDTH 1
+#define R_IRQ_MASK1_CLR__sw_int2__clr 1
+#define R_IRQ_MASK1_CLR__sw_int2__nop 0
+#define R_IRQ_MASK1_CLR__sw_int1__BITNR 25
+#define R_IRQ_MASK1_CLR__sw_int1__WIDTH 1
+#define R_IRQ_MASK1_CLR__sw_int1__clr 1
+#define R_IRQ_MASK1_CLR__sw_int1__nop 0
+#define R_IRQ_MASK1_CLR__sw_int0__BITNR 24
+#define R_IRQ_MASK1_CLR__sw_int0__WIDTH 1
+#define R_IRQ_MASK1_CLR__sw_int0__clr 1
+#define R_IRQ_MASK1_CLR__sw_int0__nop 0
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__BITNR 19
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__WIDTH 1
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__clr 1
+#define R_IRQ_MASK1_CLR__par1_ecp_cmd__nop 0
+#define R_IRQ_MASK1_CLR__par1_peri__BITNR 18
+#define R_IRQ_MASK1_CLR__par1_peri__WIDTH 1
+#define R_IRQ_MASK1_CLR__par1_peri__clr 1
+#define R_IRQ_MASK1_CLR__par1_peri__nop 0
+#define R_IRQ_MASK1_CLR__par1_data__BITNR 17
+#define R_IRQ_MASK1_CLR__par1_data__WIDTH 1
+#define R_IRQ_MASK1_CLR__par1_data__clr 1
+#define R_IRQ_MASK1_CLR__par1_data__nop 0
+#define R_IRQ_MASK1_CLR__par1_ready__BITNR 16
+#define R_IRQ_MASK1_CLR__par1_ready__WIDTH 1
+#define R_IRQ_MASK1_CLR__par1_ready__clr 1
+#define R_IRQ_MASK1_CLR__par1_ready__nop 0
+#define R_IRQ_MASK1_CLR__scsi1__BITNR 16
+#define R_IRQ_MASK1_CLR__scsi1__WIDTH 1
+#define R_IRQ_MASK1_CLR__scsi1__clr 1
+#define R_IRQ_MASK1_CLR__scsi1__nop 0
+#define R_IRQ_MASK1_CLR__ser3_ready__BITNR 15
+#define R_IRQ_MASK1_CLR__ser3_ready__WIDTH 1
+#define R_IRQ_MASK1_CLR__ser3_ready__clr 1
+#define R_IRQ_MASK1_CLR__ser3_ready__nop 0
+#define R_IRQ_MASK1_CLR__ser3_data__BITNR 14
+#define R_IRQ_MASK1_CLR__ser3_data__WIDTH 1
+#define R_IRQ_MASK1_CLR__ser3_data__clr 1
+#define R_IRQ_MASK1_CLR__ser3_data__nop 0
+#define R_IRQ_MASK1_CLR__ser2_ready__BITNR 13
+#define R_IRQ_MASK1_CLR__ser2_ready__WIDTH 1
+#define R_IRQ_MASK1_CLR__ser2_ready__clr 1
+#define R_IRQ_MASK1_CLR__ser2_ready__nop 0
+#define R_IRQ_MASK1_CLR__ser2_data__BITNR 12
+#define R_IRQ_MASK1_CLR__ser2_data__WIDTH 1
+#define R_IRQ_MASK1_CLR__ser2_data__clr 1
+#define R_IRQ_MASK1_CLR__ser2_data__nop 0
+#define R_IRQ_MASK1_CLR__ser1_ready__BITNR 11
+#define R_IRQ_MASK1_CLR__ser1_ready__WIDTH 1
+#define R_IRQ_MASK1_CLR__ser1_ready__clr 1
+#define R_IRQ_MASK1_CLR__ser1_ready__nop 0
+#define R_IRQ_MASK1_CLR__ser1_data__BITNR 10
+#define R_IRQ_MASK1_CLR__ser1_data__WIDTH 1
+#define R_IRQ_MASK1_CLR__ser1_data__clr 1
+#define R_IRQ_MASK1_CLR__ser1_data__nop 0
+#define R_IRQ_MASK1_CLR__ser0_ready__BITNR 9
+#define R_IRQ_MASK1_CLR__ser0_ready__WIDTH 1
+#define R_IRQ_MASK1_CLR__ser0_ready__clr 1
+#define R_IRQ_MASK1_CLR__ser0_ready__nop 0
+#define R_IRQ_MASK1_CLR__ser0_data__BITNR 8
+#define R_IRQ_MASK1_CLR__ser0_data__WIDTH 1
+#define R_IRQ_MASK1_CLR__ser0_data__clr 1
+#define R_IRQ_MASK1_CLR__ser0_data__nop 0
+#define R_IRQ_MASK1_CLR__pa7__BITNR 7
+#define R_IRQ_MASK1_CLR__pa7__WIDTH 1
+#define R_IRQ_MASK1_CLR__pa7__clr 1
+#define R_IRQ_MASK1_CLR__pa7__nop 0
+#define R_IRQ_MASK1_CLR__pa6__BITNR 6
+#define R_IRQ_MASK1_CLR__pa6__WIDTH 1
+#define R_IRQ_MASK1_CLR__pa6__clr 1
+#define R_IRQ_MASK1_CLR__pa6__nop 0
+#define R_IRQ_MASK1_CLR__pa5__BITNR 5
+#define R_IRQ_MASK1_CLR__pa5__WIDTH 1
+#define R_IRQ_MASK1_CLR__pa5__clr 1
+#define R_IRQ_MASK1_CLR__pa5__nop 0
+#define R_IRQ_MASK1_CLR__pa4__BITNR 4
+#define R_IRQ_MASK1_CLR__pa4__WIDTH 1
+#define R_IRQ_MASK1_CLR__pa4__clr 1
+#define R_IRQ_MASK1_CLR__pa4__nop 0
+#define R_IRQ_MASK1_CLR__pa3__BITNR 3
+#define R_IRQ_MASK1_CLR__pa3__WIDTH 1
+#define R_IRQ_MASK1_CLR__pa3__clr 1
+#define R_IRQ_MASK1_CLR__pa3__nop 0
+#define R_IRQ_MASK1_CLR__pa2__BITNR 2
+#define R_IRQ_MASK1_CLR__pa2__WIDTH 1
+#define R_IRQ_MASK1_CLR__pa2__clr 1
+#define R_IRQ_MASK1_CLR__pa2__nop 0
+#define R_IRQ_MASK1_CLR__pa1__BITNR 1
+#define R_IRQ_MASK1_CLR__pa1__WIDTH 1
+#define R_IRQ_MASK1_CLR__pa1__clr 1
+#define R_IRQ_MASK1_CLR__pa1__nop 0
+#define R_IRQ_MASK1_CLR__pa0__BITNR 0
+#define R_IRQ_MASK1_CLR__pa0__WIDTH 1
+#define R_IRQ_MASK1_CLR__pa0__clr 1
+#define R_IRQ_MASK1_CLR__pa0__nop 0
+
+#define R_IRQ_READ1 (IO_TYPECAST_RO_UDWORD 0xb00000cc)
+#define R_IRQ_READ1__sw_int7__BITNR 31
+#define R_IRQ_READ1__sw_int7__WIDTH 1
+#define R_IRQ_READ1__sw_int7__active 1
+#define R_IRQ_READ1__sw_int7__inactive 0
+#define R_IRQ_READ1__sw_int6__BITNR 30
+#define R_IRQ_READ1__sw_int6__WIDTH 1
+#define R_IRQ_READ1__sw_int6__active 1
+#define R_IRQ_READ1__sw_int6__inactive 0
+#define R_IRQ_READ1__sw_int5__BITNR 29
+#define R_IRQ_READ1__sw_int5__WIDTH 1
+#define R_IRQ_READ1__sw_int5__active 1
+#define R_IRQ_READ1__sw_int5__inactive 0
+#define R_IRQ_READ1__sw_int4__BITNR 28
+#define R_IRQ_READ1__sw_int4__WIDTH 1
+#define R_IRQ_READ1__sw_int4__active 1
+#define R_IRQ_READ1__sw_int4__inactive 0
+#define R_IRQ_READ1__sw_int3__BITNR 27
+#define R_IRQ_READ1__sw_int3__WIDTH 1
+#define R_IRQ_READ1__sw_int3__active 1
+#define R_IRQ_READ1__sw_int3__inactive 0
+#define R_IRQ_READ1__sw_int2__BITNR 26
+#define R_IRQ_READ1__sw_int2__WIDTH 1
+#define R_IRQ_READ1__sw_int2__active 1
+#define R_IRQ_READ1__sw_int2__inactive 0
+#define R_IRQ_READ1__sw_int1__BITNR 25
+#define R_IRQ_READ1__sw_int1__WIDTH 1
+#define R_IRQ_READ1__sw_int1__active 1
+#define R_IRQ_READ1__sw_int1__inactive 0
+#define R_IRQ_READ1__sw_int0__BITNR 24
+#define R_IRQ_READ1__sw_int0__WIDTH 1
+#define R_IRQ_READ1__sw_int0__active 1
+#define R_IRQ_READ1__sw_int0__inactive 0
+#define R_IRQ_READ1__par1_ecp_cmd__BITNR 19
+#define R_IRQ_READ1__par1_ecp_cmd__WIDTH 1
+#define R_IRQ_READ1__par1_ecp_cmd__active 1
+#define R_IRQ_READ1__par1_ecp_cmd__inactive 0
+#define R_IRQ_READ1__par1_peri__BITNR 18
+#define R_IRQ_READ1__par1_peri__WIDTH 1
+#define R_IRQ_READ1__par1_peri__active 1
+#define R_IRQ_READ1__par1_peri__inactive 0
+#define R_IRQ_READ1__par1_data__BITNR 17
+#define R_IRQ_READ1__par1_data__WIDTH 1
+#define R_IRQ_READ1__par1_data__active 1
+#define R_IRQ_READ1__par1_data__inactive 0
+#define R_IRQ_READ1__par1_ready__BITNR 16
+#define R_IRQ_READ1__par1_ready__WIDTH 1
+#define R_IRQ_READ1__par1_ready__active 1
+#define R_IRQ_READ1__par1_ready__inactive 0
+#define R_IRQ_READ1__scsi1__BITNR 16
+#define R_IRQ_READ1__scsi1__WIDTH 1
+#define R_IRQ_READ1__scsi1__active 1
+#define R_IRQ_READ1__scsi1__inactive 0
+#define R_IRQ_READ1__ser3_ready__BITNR 15
+#define R_IRQ_READ1__ser3_ready__WIDTH 1
+#define R_IRQ_READ1__ser3_ready__active 1
+#define R_IRQ_READ1__ser3_ready__inactive 0
+#define R_IRQ_READ1__ser3_data__BITNR 14
+#define R_IRQ_READ1__ser3_data__WIDTH 1
+#define R_IRQ_READ1__ser3_data__active 1
+#define R_IRQ_READ1__ser3_data__inactive 0
+#define R_IRQ_READ1__ser2_ready__BITNR 13
+#define R_IRQ_READ1__ser2_ready__WIDTH 1
+#define R_IRQ_READ1__ser2_ready__active 1
+#define R_IRQ_READ1__ser2_ready__inactive 0
+#define R_IRQ_READ1__ser2_data__BITNR 12
+#define R_IRQ_READ1__ser2_data__WIDTH 1
+#define R_IRQ_READ1__ser2_data__active 1
+#define R_IRQ_READ1__ser2_data__inactive 0
+#define R_IRQ_READ1__ser1_ready__BITNR 11
+#define R_IRQ_READ1__ser1_ready__WIDTH 1
+#define R_IRQ_READ1__ser1_ready__active 1
+#define R_IRQ_READ1__ser1_ready__inactive 0
+#define R_IRQ_READ1__ser1_data__BITNR 10
+#define R_IRQ_READ1__ser1_data__WIDTH 1
+#define R_IRQ_READ1__ser1_data__active 1
+#define R_IRQ_READ1__ser1_data__inactive 0
+#define R_IRQ_READ1__ser0_ready__BITNR 9
+#define R_IRQ_READ1__ser0_ready__WIDTH 1
+#define R_IRQ_READ1__ser0_ready__active 1
+#define R_IRQ_READ1__ser0_ready__inactive 0
+#define R_IRQ_READ1__ser0_data__BITNR 8
+#define R_IRQ_READ1__ser0_data__WIDTH 1
+#define R_IRQ_READ1__ser0_data__active 1
+#define R_IRQ_READ1__ser0_data__inactive 0
+#define R_IRQ_READ1__pa7__BITNR 7
+#define R_IRQ_READ1__pa7__WIDTH 1
+#define R_IRQ_READ1__pa7__active 1
+#define R_IRQ_READ1__pa7__inactive 0
+#define R_IRQ_READ1__pa6__BITNR 6
+#define R_IRQ_READ1__pa6__WIDTH 1
+#define R_IRQ_READ1__pa6__active 1
+#define R_IRQ_READ1__pa6__inactive 0
+#define R_IRQ_READ1__pa5__BITNR 5
+#define R_IRQ_READ1__pa5__WIDTH 1
+#define R_IRQ_READ1__pa5__active 1
+#define R_IRQ_READ1__pa5__inactive 0
+#define R_IRQ_READ1__pa4__BITNR 4
+#define R_IRQ_READ1__pa4__WIDTH 1
+#define R_IRQ_READ1__pa4__active 1
+#define R_IRQ_READ1__pa4__inactive 0
+#define R_IRQ_READ1__pa3__BITNR 3
+#define R_IRQ_READ1__pa3__WIDTH 1
+#define R_IRQ_READ1__pa3__active 1
+#define R_IRQ_READ1__pa3__inactive 0
+#define R_IRQ_READ1__pa2__BITNR 2
+#define R_IRQ_READ1__pa2__WIDTH 1
+#define R_IRQ_READ1__pa2__active 1
+#define R_IRQ_READ1__pa2__inactive 0
+#define R_IRQ_READ1__pa1__BITNR 1
+#define R_IRQ_READ1__pa1__WIDTH 1
+#define R_IRQ_READ1__pa1__active 1
+#define R_IRQ_READ1__pa1__inactive 0
+#define R_IRQ_READ1__pa0__BITNR 0
+#define R_IRQ_READ1__pa0__WIDTH 1
+#define R_IRQ_READ1__pa0__active 1
+#define R_IRQ_READ1__pa0__inactive 0
+
+#define R_IRQ_MASK1_SET (IO_TYPECAST_UDWORD 0xb00000cc)
+#define R_IRQ_MASK1_SET__sw_int7__BITNR 31
+#define R_IRQ_MASK1_SET__sw_int7__WIDTH 1
+#define R_IRQ_MASK1_SET__sw_int7__set 1
+#define R_IRQ_MASK1_SET__sw_int7__nop 0
+#define R_IRQ_MASK1_SET__sw_int6__BITNR 30
+#define R_IRQ_MASK1_SET__sw_int6__WIDTH 1
+#define R_IRQ_MASK1_SET__sw_int6__set 1
+#define R_IRQ_MASK1_SET__sw_int6__nop 0
+#define R_IRQ_MASK1_SET__sw_int5__BITNR 29
+#define R_IRQ_MASK1_SET__sw_int5__WIDTH 1
+#define R_IRQ_MASK1_SET__sw_int5__set 1
+#define R_IRQ_MASK1_SET__sw_int5__nop 0
+#define R_IRQ_MASK1_SET__sw_int4__BITNR 28
+#define R_IRQ_MASK1_SET__sw_int4__WIDTH 1
+#define R_IRQ_MASK1_SET__sw_int4__set 1
+#define R_IRQ_MASK1_SET__sw_int4__nop 0
+#define R_IRQ_MASK1_SET__sw_int3__BITNR 27
+#define R_IRQ_MASK1_SET__sw_int3__WIDTH 1
+#define R_IRQ_MASK1_SET__sw_int3__set 1
+#define R_IRQ_MASK1_SET__sw_int3__nop 0
+#define R_IRQ_MASK1_SET__sw_int2__BITNR 26
+#define R_IRQ_MASK1_SET__sw_int2__WIDTH 1
+#define R_IRQ_MASK1_SET__sw_int2__set 1
+#define R_IRQ_MASK1_SET__sw_int2__nop 0
+#define R_IRQ_MASK1_SET__sw_int1__BITNR 25
+#define R_IRQ_MASK1_SET__sw_int1__WIDTH 1
+#define R_IRQ_MASK1_SET__sw_int1__set 1
+#define R_IRQ_MASK1_SET__sw_int1__nop 0
+#define R_IRQ_MASK1_SET__sw_int0__BITNR 24
+#define R_IRQ_MASK1_SET__sw_int0__WIDTH 1
+#define R_IRQ_MASK1_SET__sw_int0__set 1
+#define R_IRQ_MASK1_SET__sw_int0__nop 0
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__BITNR 19
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__WIDTH 1
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__set 1
+#define R_IRQ_MASK1_SET__par1_ecp_cmd__nop 0
+#define R_IRQ_MASK1_SET__par1_peri__BITNR 18
+#define R_IRQ_MASK1_SET__par1_peri__WIDTH 1
+#define R_IRQ_MASK1_SET__par1_peri__set 1
+#define R_IRQ_MASK1_SET__par1_peri__nop 0
+#define R_IRQ_MASK1_SET__par1_data__BITNR 17
+#define R_IRQ_MASK1_SET__par1_data__WIDTH 1
+#define R_IRQ_MASK1_SET__par1_data__set 1
+#define R_IRQ_MASK1_SET__par1_data__nop 0
+#define R_IRQ_MASK1_SET__par1_ready__BITNR 16
+#define R_IRQ_MASK1_SET__par1_ready__WIDTH 1
+#define R_IRQ_MASK1_SET__par1_ready__set 1
+#define R_IRQ_MASK1_SET__par1_ready__nop 0
+#define R_IRQ_MASK1_SET__scsi1__BITNR 16
+#define R_IRQ_MASK1_SET__scsi1__WIDTH 1
+#define R_IRQ_MASK1_SET__scsi1__set 1
+#define R_IRQ_MASK1_SET__scsi1__nop 0
+#define R_IRQ_MASK1_SET__ser3_ready__BITNR 15
+#define R_IRQ_MASK1_SET__ser3_ready__WIDTH 1
+#define R_IRQ_MASK1_SET__ser3_ready__set 1
+#define R_IRQ_MASK1_SET__ser3_ready__nop 0
+#define R_IRQ_MASK1_SET__ser3_data__BITNR 14
+#define R_IRQ_MASK1_SET__ser3_data__WIDTH 1
+#define R_IRQ_MASK1_SET__ser3_data__set 1
+#define R_IRQ_MASK1_SET__ser3_data__nop 0
+#define R_IRQ_MASK1_SET__ser2_ready__BITNR 13
+#define R_IRQ_MASK1_SET__ser2_ready__WIDTH 1
+#define R_IRQ_MASK1_SET__ser2_ready__set 1
+#define R_IRQ_MASK1_SET__ser2_ready__nop 0
+#define R_IRQ_MASK1_SET__ser2_data__BITNR 12
+#define R_IRQ_MASK1_SET__ser2_data__WIDTH 1
+#define R_IRQ_MASK1_SET__ser2_data__set 1
+#define R_IRQ_MASK1_SET__ser2_data__nop 0
+#define R_IRQ_MASK1_SET__ser1_ready__BITNR 11
+#define R_IRQ_MASK1_SET__ser1_ready__WIDTH 1
+#define R_IRQ_MASK1_SET__ser1_ready__set 1
+#define R_IRQ_MASK1_SET__ser1_ready__nop 0
+#define R_IRQ_MASK1_SET__ser1_data__BITNR 10
+#define R_IRQ_MASK1_SET__ser1_data__WIDTH 1
+#define R_IRQ_MASK1_SET__ser1_data__set 1
+#define R_IRQ_MASK1_SET__ser1_data__nop 0
+#define R_IRQ_MASK1_SET__ser0_ready__BITNR 9
+#define R_IRQ_MASK1_SET__ser0_ready__WIDTH 1
+#define R_IRQ_MASK1_SET__ser0_ready__set 1
+#define R_IRQ_MASK1_SET__ser0_ready__nop 0
+#define R_IRQ_MASK1_SET__ser0_data__BITNR 8
+#define R_IRQ_MASK1_SET__ser0_data__WIDTH 1
+#define R_IRQ_MASK1_SET__ser0_data__set 1
+#define R_IRQ_MASK1_SET__ser0_data__nop 0
+#define R_IRQ_MASK1_SET__pa7__BITNR 7
+#define R_IRQ_MASK1_SET__pa7__WIDTH 1
+#define R_IRQ_MASK1_SET__pa7__set 1
+#define R_IRQ_MASK1_SET__pa7__nop 0
+#define R_IRQ_MASK1_SET__pa6__BITNR 6
+#define R_IRQ_MASK1_SET__pa6__WIDTH 1
+#define R_IRQ_MASK1_SET__pa6__set 1
+#define R_IRQ_MASK1_SET__pa6__nop 0
+#define R_IRQ_MASK1_SET__pa5__BITNR 5
+#define R_IRQ_MASK1_SET__pa5__WIDTH 1
+#define R_IRQ_MASK1_SET__pa5__set 1
+#define R_IRQ_MASK1_SET__pa5__nop 0
+#define R_IRQ_MASK1_SET__pa4__BITNR 4
+#define R_IRQ_MASK1_SET__pa4__WIDTH 1
+#define R_IRQ_MASK1_SET__pa4__set 1
+#define R_IRQ_MASK1_SET__pa4__nop 0
+#define R_IRQ_MASK1_SET__pa3__BITNR 3
+#define R_IRQ_MASK1_SET__pa3__WIDTH 1
+#define R_IRQ_MASK1_SET__pa3__set 1
+#define R_IRQ_MASK1_SET__pa3__nop 0
+#define R_IRQ_MASK1_SET__pa2__BITNR 2
+#define R_IRQ_MASK1_SET__pa2__WIDTH 1
+#define R_IRQ_MASK1_SET__pa2__set 1
+#define R_IRQ_MASK1_SET__pa2__nop 0
+#define R_IRQ_MASK1_SET__pa1__BITNR 1
+#define R_IRQ_MASK1_SET__pa1__WIDTH 1
+#define R_IRQ_MASK1_SET__pa1__set 1
+#define R_IRQ_MASK1_SET__pa1__nop 0
+#define R_IRQ_MASK1_SET__pa0__BITNR 0
+#define R_IRQ_MASK1_SET__pa0__WIDTH 1
+#define R_IRQ_MASK1_SET__pa0__set 1
+#define R_IRQ_MASK1_SET__pa0__nop 0
+
+#define R_IRQ_MASK2_RD (IO_TYPECAST_RO_UDWORD 0xb00000d0)
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__BITNR 23
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_sub3_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__BITNR 22
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_sub2_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__BITNR 21
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_sub1_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__BITNR 20
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_sub0_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma9_eop__BITNR 19
+#define R_IRQ_MASK2_RD__dma9_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma9_eop__active 1
+#define R_IRQ_MASK2_RD__dma9_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma9_descr__BITNR 18
+#define R_IRQ_MASK2_RD__dma9_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma9_descr__active 1
+#define R_IRQ_MASK2_RD__dma9_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma8_eop__BITNR 17
+#define R_IRQ_MASK2_RD__dma8_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma8_eop__active 1
+#define R_IRQ_MASK2_RD__dma8_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma8_descr__BITNR 16
+#define R_IRQ_MASK2_RD__dma8_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma8_descr__active 1
+#define R_IRQ_MASK2_RD__dma8_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma7_eop__BITNR 15
+#define R_IRQ_MASK2_RD__dma7_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma7_eop__active 1
+#define R_IRQ_MASK2_RD__dma7_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma7_descr__BITNR 14
+#define R_IRQ_MASK2_RD__dma7_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma7_descr__active 1
+#define R_IRQ_MASK2_RD__dma7_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma6_eop__BITNR 13
+#define R_IRQ_MASK2_RD__dma6_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma6_eop__active 1
+#define R_IRQ_MASK2_RD__dma6_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma6_descr__BITNR 12
+#define R_IRQ_MASK2_RD__dma6_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma6_descr__active 1
+#define R_IRQ_MASK2_RD__dma6_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma5_eop__BITNR 11
+#define R_IRQ_MASK2_RD__dma5_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma5_eop__active 1
+#define R_IRQ_MASK2_RD__dma5_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma5_descr__BITNR 10
+#define R_IRQ_MASK2_RD__dma5_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma5_descr__active 1
+#define R_IRQ_MASK2_RD__dma5_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma4_eop__BITNR 9
+#define R_IRQ_MASK2_RD__dma4_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma4_eop__active 1
+#define R_IRQ_MASK2_RD__dma4_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma4_descr__BITNR 8
+#define R_IRQ_MASK2_RD__dma4_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma4_descr__active 1
+#define R_IRQ_MASK2_RD__dma4_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma3_eop__BITNR 7
+#define R_IRQ_MASK2_RD__dma3_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma3_eop__active 1
+#define R_IRQ_MASK2_RD__dma3_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma3_descr__BITNR 6
+#define R_IRQ_MASK2_RD__dma3_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma3_descr__active 1
+#define R_IRQ_MASK2_RD__dma3_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma2_eop__BITNR 5
+#define R_IRQ_MASK2_RD__dma2_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma2_eop__active 1
+#define R_IRQ_MASK2_RD__dma2_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma2_descr__BITNR 4
+#define R_IRQ_MASK2_RD__dma2_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma2_descr__active 1
+#define R_IRQ_MASK2_RD__dma2_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma1_eop__BITNR 3
+#define R_IRQ_MASK2_RD__dma1_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma1_eop__active 1
+#define R_IRQ_MASK2_RD__dma1_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma1_descr__BITNR 2
+#define R_IRQ_MASK2_RD__dma1_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma1_descr__active 1
+#define R_IRQ_MASK2_RD__dma1_descr__inactive 0
+#define R_IRQ_MASK2_RD__dma0_eop__BITNR 1
+#define R_IRQ_MASK2_RD__dma0_eop__WIDTH 1
+#define R_IRQ_MASK2_RD__dma0_eop__active 1
+#define R_IRQ_MASK2_RD__dma0_eop__inactive 0
+#define R_IRQ_MASK2_RD__dma0_descr__BITNR 0
+#define R_IRQ_MASK2_RD__dma0_descr__WIDTH 1
+#define R_IRQ_MASK2_RD__dma0_descr__active 1
+#define R_IRQ_MASK2_RD__dma0_descr__inactive 0
+
+#define R_IRQ_MASK2_CLR (IO_TYPECAST_UDWORD 0xb00000d0)
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__BITNR 23
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_sub3_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__BITNR 22
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_sub2_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__BITNR 21
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_sub1_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__BITNR 20
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_sub0_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma9_eop__BITNR 19
+#define R_IRQ_MASK2_CLR__dma9_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma9_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma9_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma9_descr__BITNR 18
+#define R_IRQ_MASK2_CLR__dma9_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma9_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma9_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma8_eop__BITNR 17
+#define R_IRQ_MASK2_CLR__dma8_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma8_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma8_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma8_descr__BITNR 16
+#define R_IRQ_MASK2_CLR__dma8_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma8_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma8_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma7_eop__BITNR 15
+#define R_IRQ_MASK2_CLR__dma7_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma7_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma7_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma7_descr__BITNR 14
+#define R_IRQ_MASK2_CLR__dma7_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma7_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma7_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma6_eop__BITNR 13
+#define R_IRQ_MASK2_CLR__dma6_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma6_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma6_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma6_descr__BITNR 12
+#define R_IRQ_MASK2_CLR__dma6_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma6_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma6_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma5_eop__BITNR 11
+#define R_IRQ_MASK2_CLR__dma5_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma5_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma5_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma5_descr__BITNR 10
+#define R_IRQ_MASK2_CLR__dma5_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma5_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma5_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma4_eop__BITNR 9
+#define R_IRQ_MASK2_CLR__dma4_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma4_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma4_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma4_descr__BITNR 8
+#define R_IRQ_MASK2_CLR__dma4_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma4_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma4_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma3_eop__BITNR 7
+#define R_IRQ_MASK2_CLR__dma3_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma3_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma3_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma3_descr__BITNR 6
+#define R_IRQ_MASK2_CLR__dma3_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma3_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma3_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma2_eop__BITNR 5
+#define R_IRQ_MASK2_CLR__dma2_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma2_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma2_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma2_descr__BITNR 4
+#define R_IRQ_MASK2_CLR__dma2_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma2_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma2_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma1_eop__BITNR 3
+#define R_IRQ_MASK2_CLR__dma1_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma1_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma1_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma1_descr__BITNR 2
+#define R_IRQ_MASK2_CLR__dma1_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma1_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma1_descr__nop 0
+#define R_IRQ_MASK2_CLR__dma0_eop__BITNR 1
+#define R_IRQ_MASK2_CLR__dma0_eop__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma0_eop__clr 1
+#define R_IRQ_MASK2_CLR__dma0_eop__nop 0
+#define R_IRQ_MASK2_CLR__dma0_descr__BITNR 0
+#define R_IRQ_MASK2_CLR__dma0_descr__WIDTH 1
+#define R_IRQ_MASK2_CLR__dma0_descr__clr 1
+#define R_IRQ_MASK2_CLR__dma0_descr__nop 0
+
+#define R_IRQ_READ2 (IO_TYPECAST_RO_UDWORD 0xb00000d4)
+#define R_IRQ_READ2__dma8_sub3_descr__BITNR 23
+#define R_IRQ_READ2__dma8_sub3_descr__WIDTH 1
+#define R_IRQ_READ2__dma8_sub3_descr__active 1
+#define R_IRQ_READ2__dma8_sub3_descr__inactive 0
+#define R_IRQ_READ2__dma8_sub2_descr__BITNR 22
+#define R_IRQ_READ2__dma8_sub2_descr__WIDTH 1
+#define R_IRQ_READ2__dma8_sub2_descr__active 1
+#define R_IRQ_READ2__dma8_sub2_descr__inactive 0
+#define R_IRQ_READ2__dma8_sub1_descr__BITNR 21
+#define R_IRQ_READ2__dma8_sub1_descr__WIDTH 1
+#define R_IRQ_READ2__dma8_sub1_descr__active 1
+#define R_IRQ_READ2__dma8_sub1_descr__inactive 0
+#define R_IRQ_READ2__dma8_sub0_descr__BITNR 20
+#define R_IRQ_READ2__dma8_sub0_descr__WIDTH 1
+#define R_IRQ_READ2__dma8_sub0_descr__active 1
+#define R_IRQ_READ2__dma8_sub0_descr__inactive 0
+#define R_IRQ_READ2__dma9_eop__BITNR 19
+#define R_IRQ_READ2__dma9_eop__WIDTH 1
+#define R_IRQ_READ2__dma9_eop__active 1
+#define R_IRQ_READ2__dma9_eop__inactive 0
+#define R_IRQ_READ2__dma9_descr__BITNR 18
+#define R_IRQ_READ2__dma9_descr__WIDTH 1
+#define R_IRQ_READ2__dma9_descr__active 1
+#define R_IRQ_READ2__dma9_descr__inactive 0
+#define R_IRQ_READ2__dma8_eop__BITNR 17
+#define R_IRQ_READ2__dma8_eop__WIDTH 1
+#define R_IRQ_READ2__dma8_eop__active 1
+#define R_IRQ_READ2__dma8_eop__inactive 0
+#define R_IRQ_READ2__dma8_descr__BITNR 16
+#define R_IRQ_READ2__dma8_descr__WIDTH 1
+#define R_IRQ_READ2__dma8_descr__active 1
+#define R_IRQ_READ2__dma8_descr__inactive 0
+#define R_IRQ_READ2__dma7_eop__BITNR 15
+#define R_IRQ_READ2__dma7_eop__WIDTH 1
+#define R_IRQ_READ2__dma7_eop__active 1
+#define R_IRQ_READ2__dma7_eop__inactive 0
+#define R_IRQ_READ2__dma7_descr__BITNR 14
+#define R_IRQ_READ2__dma7_descr__WIDTH 1
+#define R_IRQ_READ2__dma7_descr__active 1
+#define R_IRQ_READ2__dma7_descr__inactive 0
+#define R_IRQ_READ2__dma6_eop__BITNR 13
+#define R_IRQ_READ2__dma6_eop__WIDTH 1
+#define R_IRQ_READ2__dma6_eop__active 1
+#define R_IRQ_READ2__dma6_eop__inactive 0
+#define R_IRQ_READ2__dma6_descr__BITNR 12
+#define R_IRQ_READ2__dma6_descr__WIDTH 1
+#define R_IRQ_READ2__dma6_descr__active 1
+#define R_IRQ_READ2__dma6_descr__inactive 0
+#define R_IRQ_READ2__dma5_eop__BITNR 11
+#define R_IRQ_READ2__dma5_eop__WIDTH 1
+#define R_IRQ_READ2__dma5_eop__active 1
+#define R_IRQ_READ2__dma5_eop__inactive 0
+#define R_IRQ_READ2__dma5_descr__BITNR 10
+#define R_IRQ_READ2__dma5_descr__WIDTH 1
+#define R_IRQ_READ2__dma5_descr__active 1
+#define R_IRQ_READ2__dma5_descr__inactive 0
+#define R_IRQ_READ2__dma4_eop__BITNR 9
+#define R_IRQ_READ2__dma4_eop__WIDTH 1
+#define R_IRQ_READ2__dma4_eop__active 1
+#define R_IRQ_READ2__dma4_eop__inactive 0
+#define R_IRQ_READ2__dma4_descr__BITNR 8
+#define R_IRQ_READ2__dma4_descr__WIDTH 1
+#define R_IRQ_READ2__dma4_descr__active 1
+#define R_IRQ_READ2__dma4_descr__inactive 0
+#define R_IRQ_READ2__dma3_eop__BITNR 7
+#define R_IRQ_READ2__dma3_eop__WIDTH 1
+#define R_IRQ_READ2__dma3_eop__active 1
+#define R_IRQ_READ2__dma3_eop__inactive 0
+#define R_IRQ_READ2__dma3_descr__BITNR 6
+#define R_IRQ_READ2__dma3_descr__WIDTH 1
+#define R_IRQ_READ2__dma3_descr__active 1
+#define R_IRQ_READ2__dma3_descr__inactive 0
+#define R_IRQ_READ2__dma2_eop__BITNR 5
+#define R_IRQ_READ2__dma2_eop__WIDTH 1
+#define R_IRQ_READ2__dma2_eop__active 1
+#define R_IRQ_READ2__dma2_eop__inactive 0
+#define R_IRQ_READ2__dma2_descr__BITNR 4
+#define R_IRQ_READ2__dma2_descr__WIDTH 1
+#define R_IRQ_READ2__dma2_descr__active 1
+#define R_IRQ_READ2__dma2_descr__inactive 0
+#define R_IRQ_READ2__dma1_eop__BITNR 3
+#define R_IRQ_READ2__dma1_eop__WIDTH 1
+#define R_IRQ_READ2__dma1_eop__active 1
+#define R_IRQ_READ2__dma1_eop__inactive 0
+#define R_IRQ_READ2__dma1_descr__BITNR 2
+#define R_IRQ_READ2__dma1_descr__WIDTH 1
+#define R_IRQ_READ2__dma1_descr__active 1
+#define R_IRQ_READ2__dma1_descr__inactive 0
+#define R_IRQ_READ2__dma0_eop__BITNR 1
+#define R_IRQ_READ2__dma0_eop__WIDTH 1
+#define R_IRQ_READ2__dma0_eop__active 1
+#define R_IRQ_READ2__dma0_eop__inactive 0
+#define R_IRQ_READ2__dma0_descr__BITNR 0
+#define R_IRQ_READ2__dma0_descr__WIDTH 1
+#define R_IRQ_READ2__dma0_descr__active 1
+#define R_IRQ_READ2__dma0_descr__inactive 0
+
+#define R_IRQ_MASK2_SET (IO_TYPECAST_UDWORD 0xb00000d4)
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__BITNR 23
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_sub3_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__BITNR 22
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_sub2_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__BITNR 21
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_sub1_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__BITNR 20
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_sub0_descr__nop 0
+#define R_IRQ_MASK2_SET__dma9_eop__BITNR 19
+#define R_IRQ_MASK2_SET__dma9_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma9_eop__set 1
+#define R_IRQ_MASK2_SET__dma9_eop__nop 0
+#define R_IRQ_MASK2_SET__dma9_descr__BITNR 18
+#define R_IRQ_MASK2_SET__dma9_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma9_descr__set 1
+#define R_IRQ_MASK2_SET__dma9_descr__nop 0
+#define R_IRQ_MASK2_SET__dma8_eop__BITNR 17
+#define R_IRQ_MASK2_SET__dma8_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma8_eop__set 1
+#define R_IRQ_MASK2_SET__dma8_eop__nop 0
+#define R_IRQ_MASK2_SET__dma8_descr__BITNR 16
+#define R_IRQ_MASK2_SET__dma8_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma8_descr__set 1
+#define R_IRQ_MASK2_SET__dma8_descr__nop 0
+#define R_IRQ_MASK2_SET__dma7_eop__BITNR 15
+#define R_IRQ_MASK2_SET__dma7_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma7_eop__set 1
+#define R_IRQ_MASK2_SET__dma7_eop__nop 0
+#define R_IRQ_MASK2_SET__dma7_descr__BITNR 14
+#define R_IRQ_MASK2_SET__dma7_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma7_descr__set 1
+#define R_IRQ_MASK2_SET__dma7_descr__nop 0
+#define R_IRQ_MASK2_SET__dma6_eop__BITNR 13
+#define R_IRQ_MASK2_SET__dma6_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma6_eop__set 1
+#define R_IRQ_MASK2_SET__dma6_eop__nop 0
+#define R_IRQ_MASK2_SET__dma6_descr__BITNR 12
+#define R_IRQ_MASK2_SET__dma6_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma6_descr__set 1
+#define R_IRQ_MASK2_SET__dma6_descr__nop 0
+#define R_IRQ_MASK2_SET__dma5_eop__BITNR 11
+#define R_IRQ_MASK2_SET__dma5_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma5_eop__set 1
+#define R_IRQ_MASK2_SET__dma5_eop__nop 0
+#define R_IRQ_MASK2_SET__dma5_descr__BITNR 10
+#define R_IRQ_MASK2_SET__dma5_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma5_descr__set 1
+#define R_IRQ_MASK2_SET__dma5_descr__nop 0
+#define R_IRQ_MASK2_SET__dma4_eop__BITNR 9
+#define R_IRQ_MASK2_SET__dma4_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma4_eop__set 1
+#define R_IRQ_MASK2_SET__dma4_eop__nop 0
+#define R_IRQ_MASK2_SET__dma4_descr__BITNR 8
+#define R_IRQ_MASK2_SET__dma4_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma4_descr__set 1
+#define R_IRQ_MASK2_SET__dma4_descr__nop 0
+#define R_IRQ_MASK2_SET__dma3_eop__BITNR 7
+#define R_IRQ_MASK2_SET__dma3_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma3_eop__set 1
+#define R_IRQ_MASK2_SET__dma3_eop__nop 0
+#define R_IRQ_MASK2_SET__dma3_descr__BITNR 6
+#define R_IRQ_MASK2_SET__dma3_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma3_descr__set 1
+#define R_IRQ_MASK2_SET__dma3_descr__nop 0
+#define R_IRQ_MASK2_SET__dma2_eop__BITNR 5
+#define R_IRQ_MASK2_SET__dma2_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma2_eop__set 1
+#define R_IRQ_MASK2_SET__dma2_eop__nop 0
+#define R_IRQ_MASK2_SET__dma2_descr__BITNR 4
+#define R_IRQ_MASK2_SET__dma2_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma2_descr__set 1
+#define R_IRQ_MASK2_SET__dma2_descr__nop 0
+#define R_IRQ_MASK2_SET__dma1_eop__BITNR 3
+#define R_IRQ_MASK2_SET__dma1_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma1_eop__set 1
+#define R_IRQ_MASK2_SET__dma1_eop__nop 0
+#define R_IRQ_MASK2_SET__dma1_descr__BITNR 2
+#define R_IRQ_MASK2_SET__dma1_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma1_descr__set 1
+#define R_IRQ_MASK2_SET__dma1_descr__nop 0
+#define R_IRQ_MASK2_SET__dma0_eop__BITNR 1
+#define R_IRQ_MASK2_SET__dma0_eop__WIDTH 1
+#define R_IRQ_MASK2_SET__dma0_eop__set 1
+#define R_IRQ_MASK2_SET__dma0_eop__nop 0
+#define R_IRQ_MASK2_SET__dma0_descr__BITNR 0
+#define R_IRQ_MASK2_SET__dma0_descr__WIDTH 1
+#define R_IRQ_MASK2_SET__dma0_descr__set 1
+#define R_IRQ_MASK2_SET__dma0_descr__nop 0
+
+#define R_VECT_MASK_RD (IO_TYPECAST_RO_UDWORD 0xb00000d8)
+#define R_VECT_MASK_RD__usb__BITNR 31
+#define R_VECT_MASK_RD__usb__WIDTH 1
+#define R_VECT_MASK_RD__usb__active 1
+#define R_VECT_MASK_RD__usb__inactive 0
+#define R_VECT_MASK_RD__dma9__BITNR 25
+#define R_VECT_MASK_RD__dma9__WIDTH 1
+#define R_VECT_MASK_RD__dma9__active 1
+#define R_VECT_MASK_RD__dma9__inactive 0
+#define R_VECT_MASK_RD__dma8__BITNR 24
+#define R_VECT_MASK_RD__dma8__WIDTH 1
+#define R_VECT_MASK_RD__dma8__active 1
+#define R_VECT_MASK_RD__dma8__inactive 0
+#define R_VECT_MASK_RD__dma7__BITNR 23
+#define R_VECT_MASK_RD__dma7__WIDTH 1
+#define R_VECT_MASK_RD__dma7__active 1
+#define R_VECT_MASK_RD__dma7__inactive 0
+#define R_VECT_MASK_RD__dma6__BITNR 22
+#define R_VECT_MASK_RD__dma6__WIDTH 1
+#define R_VECT_MASK_RD__dma6__active 1
+#define R_VECT_MASK_RD__dma6__inactive 0
+#define R_VECT_MASK_RD__dma5__BITNR 21
+#define R_VECT_MASK_RD__dma5__WIDTH 1
+#define R_VECT_MASK_RD__dma5__active 1
+#define R_VECT_MASK_RD__dma5__inactive 0
+#define R_VECT_MASK_RD__dma4__BITNR 20
+#define R_VECT_MASK_RD__dma4__WIDTH 1
+#define R_VECT_MASK_RD__dma4__active 1
+#define R_VECT_MASK_RD__dma4__inactive 0
+#define R_VECT_MASK_RD__dma3__BITNR 19
+#define R_VECT_MASK_RD__dma3__WIDTH 1
+#define R_VECT_MASK_RD__dma3__active 1
+#define R_VECT_MASK_RD__dma3__inactive 0
+#define R_VECT_MASK_RD__dma2__BITNR 18
+#define R_VECT_MASK_RD__dma2__WIDTH 1
+#define R_VECT_MASK_RD__dma2__active 1
+#define R_VECT_MASK_RD__dma2__inactive 0
+#define R_VECT_MASK_RD__dma1__BITNR 17
+#define R_VECT_MASK_RD__dma1__WIDTH 1
+#define R_VECT_MASK_RD__dma1__active 1
+#define R_VECT_MASK_RD__dma1__inactive 0
+#define R_VECT_MASK_RD__dma0__BITNR 16
+#define R_VECT_MASK_RD__dma0__WIDTH 1
+#define R_VECT_MASK_RD__dma0__active 1
+#define R_VECT_MASK_RD__dma0__inactive 0
+#define R_VECT_MASK_RD__ext_dma1__BITNR 13
+#define R_VECT_MASK_RD__ext_dma1__WIDTH 1
+#define R_VECT_MASK_RD__ext_dma1__active 1
+#define R_VECT_MASK_RD__ext_dma1__inactive 0
+#define R_VECT_MASK_RD__ext_dma0__BITNR 12
+#define R_VECT_MASK_RD__ext_dma0__WIDTH 1
+#define R_VECT_MASK_RD__ext_dma0__active 1
+#define R_VECT_MASK_RD__ext_dma0__inactive 0
+#define R_VECT_MASK_RD__pa__BITNR 11
+#define R_VECT_MASK_RD__pa__WIDTH 1
+#define R_VECT_MASK_RD__pa__active 1
+#define R_VECT_MASK_RD__pa__inactive 0
+#define R_VECT_MASK_RD__irq_intnr__BITNR 10
+#define R_VECT_MASK_RD__irq_intnr__WIDTH 1
+#define R_VECT_MASK_RD__irq_intnr__active 1
+#define R_VECT_MASK_RD__irq_intnr__inactive 0
+#define R_VECT_MASK_RD__sw__BITNR 9
+#define R_VECT_MASK_RD__sw__WIDTH 1
+#define R_VECT_MASK_RD__sw__active 1
+#define R_VECT_MASK_RD__sw__inactive 0
+#define R_VECT_MASK_RD__serial__BITNR 8
+#define R_VECT_MASK_RD__serial__WIDTH 1
+#define R_VECT_MASK_RD__serial__active 1
+#define R_VECT_MASK_RD__serial__inactive 0
+#define R_VECT_MASK_RD__snmp__BITNR 7
+#define R_VECT_MASK_RD__snmp__WIDTH 1
+#define R_VECT_MASK_RD__snmp__active 1
+#define R_VECT_MASK_RD__snmp__inactive 0
+#define R_VECT_MASK_RD__network__BITNR 6
+#define R_VECT_MASK_RD__network__WIDTH 1
+#define R_VECT_MASK_RD__network__active 1
+#define R_VECT_MASK_RD__network__inactive 0
+#define R_VECT_MASK_RD__scsi1__BITNR 5
+#define R_VECT_MASK_RD__scsi1__WIDTH 1
+#define R_VECT_MASK_RD__scsi1__active 1
+#define R_VECT_MASK_RD__scsi1__inactive 0
+#define R_VECT_MASK_RD__par1__BITNR 5
+#define R_VECT_MASK_RD__par1__WIDTH 1
+#define R_VECT_MASK_RD__par1__active 1
+#define R_VECT_MASK_RD__par1__inactive 0
+#define R_VECT_MASK_RD__scsi0__BITNR 4
+#define R_VECT_MASK_RD__scsi0__WIDTH 1
+#define R_VECT_MASK_RD__scsi0__active 1
+#define R_VECT_MASK_RD__scsi0__inactive 0
+#define R_VECT_MASK_RD__par0__BITNR 4
+#define R_VECT_MASK_RD__par0__WIDTH 1
+#define R_VECT_MASK_RD__par0__active 1
+#define R_VECT_MASK_RD__par0__inactive 0
+#define R_VECT_MASK_RD__ata__BITNR 4
+#define R_VECT_MASK_RD__ata__WIDTH 1
+#define R_VECT_MASK_RD__ata__active 1
+#define R_VECT_MASK_RD__ata__inactive 0
+#define R_VECT_MASK_RD__mio__BITNR 4
+#define R_VECT_MASK_RD__mio__WIDTH 1
+#define R_VECT_MASK_RD__mio__active 1
+#define R_VECT_MASK_RD__mio__inactive 0
+#define R_VECT_MASK_RD__timer1__BITNR 3
+#define R_VECT_MASK_RD__timer1__WIDTH 1
+#define R_VECT_MASK_RD__timer1__active 1
+#define R_VECT_MASK_RD__timer1__inactive 0
+#define R_VECT_MASK_RD__timer0__BITNR 2
+#define R_VECT_MASK_RD__timer0__WIDTH 1
+#define R_VECT_MASK_RD__timer0__active 1
+#define R_VECT_MASK_RD__timer0__inactive 0
+#define R_VECT_MASK_RD__nmi__BITNR 1
+#define R_VECT_MASK_RD__nmi__WIDTH 1
+#define R_VECT_MASK_RD__nmi__active 1
+#define R_VECT_MASK_RD__nmi__inactive 0
+#define R_VECT_MASK_RD__some__BITNR 0
+#define R_VECT_MASK_RD__some__WIDTH 1
+#define R_VECT_MASK_RD__some__active 1
+#define R_VECT_MASK_RD__some__inactive 0
+
+#define R_VECT_MASK_CLR (IO_TYPECAST_UDWORD 0xb00000d8)
+#define R_VECT_MASK_CLR__usb__BITNR 31
+#define R_VECT_MASK_CLR__usb__WIDTH 1
+#define R_VECT_MASK_CLR__usb__clr 1
+#define R_VECT_MASK_CLR__usb__nop 0
+#define R_VECT_MASK_CLR__dma9__BITNR 25
+#define R_VECT_MASK_CLR__dma9__WIDTH 1
+#define R_VECT_MASK_CLR__dma9__clr 1
+#define R_VECT_MASK_CLR__dma9__nop 0
+#define R_VECT_MASK_CLR__dma8__BITNR 24
+#define R_VECT_MASK_CLR__dma8__WIDTH 1
+#define R_VECT_MASK_CLR__dma8__clr 1
+#define R_VECT_MASK_CLR__dma8__nop 0
+#define R_VECT_MASK_CLR__dma7__BITNR 23
+#define R_VECT_MASK_CLR__dma7__WIDTH 1
+#define R_VECT_MASK_CLR__dma7__clr 1
+#define R_VECT_MASK_CLR__dma7__nop 0
+#define R_VECT_MASK_CLR__dma6__BITNR 22
+#define R_VECT_MASK_CLR__dma6__WIDTH 1
+#define R_VECT_MASK_CLR__dma6__clr 1
+#define R_VECT_MASK_CLR__dma6__nop 0
+#define R_VECT_MASK_CLR__dma5__BITNR 21
+#define R_VECT_MASK_CLR__dma5__WIDTH 1
+#define R_VECT_MASK_CLR__dma5__clr 1
+#define R_VECT_MASK_CLR__dma5__nop 0
+#define R_VECT_MASK_CLR__dma4__BITNR 20
+#define R_VECT_MASK_CLR__dma4__WIDTH 1
+#define R_VECT_MASK_CLR__dma4__clr 1
+#define R_VECT_MASK_CLR__dma4__nop 0
+#define R_VECT_MASK_CLR__dma3__BITNR 19
+#define R_VECT_MASK_CLR__dma3__WIDTH 1
+#define R_VECT_MASK_CLR__dma3__clr 1
+#define R_VECT_MASK_CLR__dma3__nop 0
+#define R_VECT_MASK_CLR__dma2__BITNR 18
+#define R_VECT_MASK_CLR__dma2__WIDTH 1
+#define R_VECT_MASK_CLR__dma2__clr 1
+#define R_VECT_MASK_CLR__dma2__nop 0
+#define R_VECT_MASK_CLR__dma1__BITNR 17
+#define R_VECT_MASK_CLR__dma1__WIDTH 1
+#define R_VECT_MASK_CLR__dma1__clr 1
+#define R_VECT_MASK_CLR__dma1__nop 0
+#define R_VECT_MASK_CLR__dma0__BITNR 16
+#define R_VECT_MASK_CLR__dma0__WIDTH 1
+#define R_VECT_MASK_CLR__dma0__clr 1
+#define R_VECT_MASK_CLR__dma0__nop 0
+#define R_VECT_MASK_CLR__ext_dma1__BITNR 13
+#define R_VECT_MASK_CLR__ext_dma1__WIDTH 1
+#define R_VECT_MASK_CLR__ext_dma1__clr 1
+#define R_VECT_MASK_CLR__ext_dma1__nop 0
+#define R_VECT_MASK_CLR__ext_dma0__BITNR 12
+#define R_VECT_MASK_CLR__ext_dma0__WIDTH 1
+#define R_VECT_MASK_CLR__ext_dma0__clr 1
+#define R_VECT_MASK_CLR__ext_dma0__nop 0
+#define R_VECT_MASK_CLR__pa__BITNR 11
+#define R_VECT_MASK_CLR__pa__WIDTH 1
+#define R_VECT_MASK_CLR__pa__clr 1
+#define R_VECT_MASK_CLR__pa__nop 0
+#define R_VECT_MASK_CLR__irq_intnr__BITNR 10
+#define R_VECT_MASK_CLR__irq_intnr__WIDTH 1
+#define R_VECT_MASK_CLR__irq_intnr__clr 1
+#define R_VECT_MASK_CLR__irq_intnr__nop 0
+#define R_VECT_MASK_CLR__sw__BITNR 9
+#define R_VECT_MASK_CLR__sw__WIDTH 1
+#define R_VECT_MASK_CLR__sw__clr 1
+#define R_VECT_MASK_CLR__sw__nop 0
+#define R_VECT_MASK_CLR__serial__BITNR 8
+#define R_VECT_MASK_CLR__serial__WIDTH 1
+#define R_VECT_MASK_CLR__serial__clr 1
+#define R_VECT_MASK_CLR__serial__nop 0
+#define R_VECT_MASK_CLR__snmp__BITNR 7
+#define R_VECT_MASK_CLR__snmp__WIDTH 1
+#define R_VECT_MASK_CLR__snmp__clr 1
+#define R_VECT_MASK_CLR__snmp__nop 0
+#define R_VECT_MASK_CLR__network__BITNR 6
+#define R_VECT_MASK_CLR__network__WIDTH 1
+#define R_VECT_MASK_CLR__network__clr 1
+#define R_VECT_MASK_CLR__network__nop 0
+#define R_VECT_MASK_CLR__scsi1__BITNR 5
+#define R_VECT_MASK_CLR__scsi1__WIDTH 1
+#define R_VECT_MASK_CLR__scsi1__clr 1
+#define R_VECT_MASK_CLR__scsi1__nop 0
+#define R_VECT_MASK_CLR__par1__BITNR 5
+#define R_VECT_MASK_CLR__par1__WIDTH 1
+#define R_VECT_MASK_CLR__par1__clr 1
+#define R_VECT_MASK_CLR__par1__nop 0
+#define R_VECT_MASK_CLR__scsi0__BITNR 4
+#define R_VECT_MASK_CLR__scsi0__WIDTH 1
+#define R_VECT_MASK_CLR__scsi0__clr 1
+#define R_VECT_MASK_CLR__scsi0__nop 0
+#define R_VECT_MASK_CLR__par0__BITNR 4
+#define R_VECT_MASK_CLR__par0__WIDTH 1
+#define R_VECT_MASK_CLR__par0__clr 1
+#define R_VECT_MASK_CLR__par0__nop 0
+#define R_VECT_MASK_CLR__ata__BITNR 4
+#define R_VECT_MASK_CLR__ata__WIDTH 1
+#define R_VECT_MASK_CLR__ata__clr 1
+#define R_VECT_MASK_CLR__ata__nop 0
+#define R_VECT_MASK_CLR__mio__BITNR 4
+#define R_VECT_MASK_CLR__mio__WIDTH 1
+#define R_VECT_MASK_CLR__mio__clr 1
+#define R_VECT_MASK_CLR__mio__nop 0
+#define R_VECT_MASK_CLR__timer1__BITNR 3
+#define R_VECT_MASK_CLR__timer1__WIDTH 1
+#define R_VECT_MASK_CLR__timer1__clr 1
+#define R_VECT_MASK_CLR__timer1__nop 0
+#define R_VECT_MASK_CLR__timer0__BITNR 2
+#define R_VECT_MASK_CLR__timer0__WIDTH 1
+#define R_VECT_MASK_CLR__timer0__clr 1
+#define R_VECT_MASK_CLR__timer0__nop 0
+#define R_VECT_MASK_CLR__nmi__BITNR 1
+#define R_VECT_MASK_CLR__nmi__WIDTH 1
+#define R_VECT_MASK_CLR__nmi__clr 1
+#define R_VECT_MASK_CLR__nmi__nop 0
+#define R_VECT_MASK_CLR__some__BITNR 0
+#define R_VECT_MASK_CLR__some__WIDTH 1
+#define R_VECT_MASK_CLR__some__clr 1
+#define R_VECT_MASK_CLR__some__nop 0
+
+#define R_VECT_READ (IO_TYPECAST_RO_UDWORD 0xb00000dc)
+#define R_VECT_READ__usb__BITNR 31
+#define R_VECT_READ__usb__WIDTH 1
+#define R_VECT_READ__usb__active 1
+#define R_VECT_READ__usb__inactive 0
+#define R_VECT_READ__dma9__BITNR 25
+#define R_VECT_READ__dma9__WIDTH 1
+#define R_VECT_READ__dma9__active 1
+#define R_VECT_READ__dma9__inactive 0
+#define R_VECT_READ__dma8__BITNR 24
+#define R_VECT_READ__dma8__WIDTH 1
+#define R_VECT_READ__dma8__active 1
+#define R_VECT_READ__dma8__inactive 0
+#define R_VECT_READ__dma7__BITNR 23
+#define R_VECT_READ__dma7__WIDTH 1
+#define R_VECT_READ__dma7__active 1
+#define R_VECT_READ__dma7__inactive 0
+#define R_VECT_READ__dma6__BITNR 22
+#define R_VECT_READ__dma6__WIDTH 1
+#define R_VECT_READ__dma6__active 1
+#define R_VECT_READ__dma6__inactive 0
+#define R_VECT_READ__dma5__BITNR 21
+#define R_VECT_READ__dma5__WIDTH 1
+#define R_VECT_READ__dma5__active 1
+#define R_VECT_READ__dma5__inactive 0
+#define R_VECT_READ__dma4__BITNR 20
+#define R_VECT_READ__dma4__WIDTH 1
+#define R_VECT_READ__dma4__active 1
+#define R_VECT_READ__dma4__inactive 0
+#define R_VECT_READ__dma3__BITNR 19
+#define R_VECT_READ__dma3__WIDTH 1
+#define R_VECT_READ__dma3__active 1
+#define R_VECT_READ__dma3__inactive 0
+#define R_VECT_READ__dma2__BITNR 18
+#define R_VECT_READ__dma2__WIDTH 1
+#define R_VECT_READ__dma2__active 1
+#define R_VECT_READ__dma2__inactive 0
+#define R_VECT_READ__dma1__BITNR 17
+#define R_VECT_READ__dma1__WIDTH 1
+#define R_VECT_READ__dma1__active 1
+#define R_VECT_READ__dma1__inactive 0
+#define R_VECT_READ__dma0__BITNR 16
+#define R_VECT_READ__dma0__WIDTH 1
+#define R_VECT_READ__dma0__active 1
+#define R_VECT_READ__dma0__inactive 0
+#define R_VECT_READ__ext_dma1__BITNR 13
+#define R_VECT_READ__ext_dma1__WIDTH 1
+#define R_VECT_READ__ext_dma1__active 1
+#define R_VECT_READ__ext_dma1__inactive 0
+#define R_VECT_READ__ext_dma0__BITNR 12
+#define R_VECT_READ__ext_dma0__WIDTH 1
+#define R_VECT_READ__ext_dma0__active 1
+#define R_VECT_READ__ext_dma0__inactive 0
+#define R_VECT_READ__pa__BITNR 11
+#define R_VECT_READ__pa__WIDTH 1
+#define R_VECT_READ__pa__active 1
+#define R_VECT_READ__pa__inactive 0
+#define R_VECT_READ__irq_intnr__BITNR 10
+#define R_VECT_READ__irq_intnr__WIDTH 1
+#define R_VECT_READ__irq_intnr__active 1
+#define R_VECT_READ__irq_intnr__inactive 0
+#define R_VECT_READ__sw__BITNR 9
+#define R_VECT_READ__sw__WIDTH 1
+#define R_VECT_READ__sw__active 1
+#define R_VECT_READ__sw__inactive 0
+#define R_VECT_READ__serial__BITNR 8
+#define R_VECT_READ__serial__WIDTH 1
+#define R_VECT_READ__serial__active 1
+#define R_VECT_READ__serial__inactive 0
+#define R_VECT_READ__snmp__BITNR 7
+#define R_VECT_READ__snmp__WIDTH 1
+#define R_VECT_READ__snmp__active 1
+#define R_VECT_READ__snmp__inactive 0
+#define R_VECT_READ__network__BITNR 6
+#define R_VECT_READ__network__WIDTH 1
+#define R_VECT_READ__network__active 1
+#define R_VECT_READ__network__inactive 0
+#define R_VECT_READ__scsi1__BITNR 5
+#define R_VECT_READ__scsi1__WIDTH 1
+#define R_VECT_READ__scsi1__active 1
+#define R_VECT_READ__scsi1__inactive 0
+#define R_VECT_READ__par1__BITNR 5
+#define R_VECT_READ__par1__WIDTH 1
+#define R_VECT_READ__par1__active 1
+#define R_VECT_READ__par1__inactive 0
+#define R_VECT_READ__scsi0__BITNR 4
+#define R_VECT_READ__scsi0__WIDTH 1
+#define R_VECT_READ__scsi0__active 1
+#define R_VECT_READ__scsi0__inactive 0
+#define R_VECT_READ__par0__BITNR 4
+#define R_VECT_READ__par0__WIDTH 1
+#define R_VECT_READ__par0__active 1
+#define R_VECT_READ__par0__inactive 0
+#define R_VECT_READ__ata__BITNR 4
+#define R_VECT_READ__ata__WIDTH 1
+#define R_VECT_READ__ata__active 1
+#define R_VECT_READ__ata__inactive 0
+#define R_VECT_READ__mio__BITNR 4
+#define R_VECT_READ__mio__WIDTH 1
+#define R_VECT_READ__mio__active 1
+#define R_VECT_READ__mio__inactive 0
+#define R_VECT_READ__timer1__BITNR 3
+#define R_VECT_READ__timer1__WIDTH 1
+#define R_VECT_READ__timer1__active 1
+#define R_VECT_READ__timer1__inactive 0
+#define R_VECT_READ__timer0__BITNR 2
+#define R_VECT_READ__timer0__WIDTH 1
+#define R_VECT_READ__timer0__active 1
+#define R_VECT_READ__timer0__inactive 0
+#define R_VECT_READ__nmi__BITNR 1
+#define R_VECT_READ__nmi__WIDTH 1
+#define R_VECT_READ__nmi__active 1
+#define R_VECT_READ__nmi__inactive 0
+#define R_VECT_READ__some__BITNR 0
+#define R_VECT_READ__some__WIDTH 1
+#define R_VECT_READ__some__active 1
+#define R_VECT_READ__some__inactive 0
+
+#define R_VECT_MASK_SET (IO_TYPECAST_UDWORD 0xb00000dc)
+#define R_VECT_MASK_SET__usb__BITNR 31
+#define R_VECT_MASK_SET__usb__WIDTH 1
+#define R_VECT_MASK_SET__usb__set 1
+#define R_VECT_MASK_SET__usb__nop 0
+#define R_VECT_MASK_SET__dma9__BITNR 25
+#define R_VECT_MASK_SET__dma9__WIDTH 1
+#define R_VECT_MASK_SET__dma9__set 1
+#define R_VECT_MASK_SET__dma9__nop 0
+#define R_VECT_MASK_SET__dma8__BITNR 24
+#define R_VECT_MASK_SET__dma8__WIDTH 1
+#define R_VECT_MASK_SET__dma8__set 1
+#define R_VECT_MASK_SET__dma8__nop 0
+#define R_VECT_MASK_SET__dma7__BITNR 23
+#define R_VECT_MASK_SET__dma7__WIDTH 1
+#define R_VECT_MASK_SET__dma7__set 1
+#define R_VECT_MASK_SET__dma7__nop 0
+#define R_VECT_MASK_SET__dma6__BITNR 22
+#define R_VECT_MASK_SET__dma6__WIDTH 1
+#define R_VECT_MASK_SET__dma6__set 1
+#define R_VECT_MASK_SET__dma6__nop 0
+#define R_VECT_MASK_SET__dma5__BITNR 21
+#define R_VECT_MASK_SET__dma5__WIDTH 1
+#define R_VECT_MASK_SET__dma5__set 1
+#define R_VECT_MASK_SET__dma5__nop 0
+#define R_VECT_MASK_SET__dma4__BITNR 20
+#define R_VECT_MASK_SET__dma4__WIDTH 1
+#define R_VECT_MASK_SET__dma4__set 1
+#define R_VECT_MASK_SET__dma4__nop 0
+#define R_VECT_MASK_SET__dma3__BITNR 19
+#define R_VECT_MASK_SET__dma3__WIDTH 1
+#define R_VECT_MASK_SET__dma3__set 1
+#define R_VECT_MASK_SET__dma3__nop 0
+#define R_VECT_MASK_SET__dma2__BITNR 18
+#define R_VECT_MASK_SET__dma2__WIDTH 1
+#define R_VECT_MASK_SET__dma2__set 1
+#define R_VECT_MASK_SET__dma2__nop 0
+#define R_VECT_MASK_SET__dma1__BITNR 17
+#define R_VECT_MASK_SET__dma1__WIDTH 1
+#define R_VECT_MASK_SET__dma1__set 1
+#define R_VECT_MASK_SET__dma1__nop 0
+#define R_VECT_MASK_SET__dma0__BITNR 16
+#define R_VECT_MASK_SET__dma0__WIDTH 1
+#define R_VECT_MASK_SET__dma0__set 1
+#define R_VECT_MASK_SET__dma0__nop 0
+#define R_VECT_MASK_SET__ext_dma1__BITNR 13
+#define R_VECT_MASK_SET__ext_dma1__WIDTH 1
+#define R_VECT_MASK_SET__ext_dma1__set 1
+#define R_VECT_MASK_SET__ext_dma1__nop 0
+#define R_VECT_MASK_SET__ext_dma0__BITNR 12
+#define R_VECT_MASK_SET__ext_dma0__WIDTH 1
+#define R_VECT_MASK_SET__ext_dma0__set 1
+#define R_VECT_MASK_SET__ext_dma0__nop 0
+#define R_VECT_MASK_SET__pa__BITNR 11
+#define R_VECT_MASK_SET__pa__WIDTH 1
+#define R_VECT_MASK_SET__pa__set 1
+#define R_VECT_MASK_SET__pa__nop 0
+#define R_VECT_MASK_SET__irq_intnr__BITNR 10
+#define R_VECT_MASK_SET__irq_intnr__WIDTH 1
+#define R_VECT_MASK_SET__irq_intnr__set 1
+#define R_VECT_MASK_SET__irq_intnr__nop 0
+#define R_VECT_MASK_SET__sw__BITNR 9
+#define R_VECT_MASK_SET__sw__WIDTH 1
+#define R_VECT_MASK_SET__sw__set 1
+#define R_VECT_MASK_SET__sw__nop 0
+#define R_VECT_MASK_SET__serial__BITNR 8
+#define R_VECT_MASK_SET__serial__WIDTH 1
+#define R_VECT_MASK_SET__serial__set 1
+#define R_VECT_MASK_SET__serial__nop 0
+#define R_VECT_MASK_SET__snmp__BITNR 7
+#define R_VECT_MASK_SET__snmp__WIDTH 1
+#define R_VECT_MASK_SET__snmp__set 1
+#define R_VECT_MASK_SET__snmp__nop 0
+#define R_VECT_MASK_SET__network__BITNR 6
+#define R_VECT_MASK_SET__network__WIDTH 1
+#define R_VECT_MASK_SET__network__set 1
+#define R_VECT_MASK_SET__network__nop 0
+#define R_VECT_MASK_SET__scsi1__BITNR 5
+#define R_VECT_MASK_SET__scsi1__WIDTH 1
+#define R_VECT_MASK_SET__scsi1__set 1
+#define R_VECT_MASK_SET__scsi1__nop 0
+#define R_VECT_MASK_SET__par1__BITNR 5
+#define R_VECT_MASK_SET__par1__WIDTH 1
+#define R_VECT_MASK_SET__par1__set 1
+#define R_VECT_MASK_SET__par1__nop 0
+#define R_VECT_MASK_SET__scsi0__BITNR 4
+#define R_VECT_MASK_SET__scsi0__WIDTH 1
+#define R_VECT_MASK_SET__scsi0__set 1
+#define R_VECT_MASK_SET__scsi0__nop 0
+#define R_VECT_MASK_SET__par0__BITNR 4
+#define R_VECT_MASK_SET__par0__WIDTH 1
+#define R_VECT_MASK_SET__par0__set 1
+#define R_VECT_MASK_SET__par0__nop 0
+#define R_VECT_MASK_SET__ata__BITNR 4
+#define R_VECT_MASK_SET__ata__WIDTH 1
+#define R_VECT_MASK_SET__ata__set 1
+#define R_VECT_MASK_SET__ata__nop 0
+#define R_VECT_MASK_SET__mio__BITNR 4
+#define R_VECT_MASK_SET__mio__WIDTH 1
+#define R_VECT_MASK_SET__mio__set 1
+#define R_VECT_MASK_SET__mio__nop 0
+#define R_VECT_MASK_SET__timer1__BITNR 3
+#define R_VECT_MASK_SET__timer1__WIDTH 1
+#define R_VECT_MASK_SET__timer1__set 1
+#define R_VECT_MASK_SET__timer1__nop 0
+#define R_VECT_MASK_SET__timer0__BITNR 2
+#define R_VECT_MASK_SET__timer0__WIDTH 1
+#define R_VECT_MASK_SET__timer0__set 1
+#define R_VECT_MASK_SET__timer0__nop 0
+#define R_VECT_MASK_SET__nmi__BITNR 1
+#define R_VECT_MASK_SET__nmi__WIDTH 1
+#define R_VECT_MASK_SET__nmi__set 1
+#define R_VECT_MASK_SET__nmi__nop 0
+#define R_VECT_MASK_SET__some__BITNR 0
+#define R_VECT_MASK_SET__some__WIDTH 1
+#define R_VECT_MASK_SET__some__set 1
+#define R_VECT_MASK_SET__some__nop 0
+
+/*
+!* DMA registers
+!*/
+
+#define R_SET_EOP (IO_TYPECAST_UDWORD 0xb000003c)
+#define R_SET_EOP__ch9_eop__BITNR 3
+#define R_SET_EOP__ch9_eop__WIDTH 1
+#define R_SET_EOP__ch9_eop__set 1
+#define R_SET_EOP__ch9_eop__nop 0
+#define R_SET_EOP__ch7_eop__BITNR 2
+#define R_SET_EOP__ch7_eop__WIDTH 1
+#define R_SET_EOP__ch7_eop__set 1
+#define R_SET_EOP__ch7_eop__nop 0
+#define R_SET_EOP__ch5_eop__BITNR 1
+#define R_SET_EOP__ch5_eop__WIDTH 1
+#define R_SET_EOP__ch5_eop__set 1
+#define R_SET_EOP__ch5_eop__nop 0
+#define R_SET_EOP__ch3_eop__BITNR 0
+#define R_SET_EOP__ch3_eop__WIDTH 1
+#define R_SET_EOP__ch3_eop__set 1
+#define R_SET_EOP__ch3_eop__nop 0
+
+#define R_DMA_CH0_HWSW (IO_TYPECAST_UDWORD 0xb0000100)
+#define R_DMA_CH0_HWSW__hw__BITNR 16
+#define R_DMA_CH0_HWSW__hw__WIDTH 16
+#define R_DMA_CH0_HWSW__sw__BITNR 0
+#define R_DMA_CH0_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH0_DESCR (IO_TYPECAST_UDWORD 0xb000010c)
+#define R_DMA_CH0_DESCR__descr__BITNR 0
+#define R_DMA_CH0_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH0_NEXT (IO_TYPECAST_UDWORD 0xb0000104)
+#define R_DMA_CH0_NEXT__next__BITNR 0
+#define R_DMA_CH0_NEXT__next__WIDTH 32
+
+#define R_DMA_CH0_BUF (IO_TYPECAST_UDWORD 0xb0000108)
+#define R_DMA_CH0_BUF__buf__BITNR 0
+#define R_DMA_CH0_BUF__buf__WIDTH 32
+
+#define R_DMA_CH0_FIRST (IO_TYPECAST_UDWORD 0xb00001a0)
+#define R_DMA_CH0_FIRST__first__BITNR 0
+#define R_DMA_CH0_FIRST__first__WIDTH 32
+
+#define R_DMA_CH0_CMD (IO_TYPECAST_BYTE 0xb00001d0)
+#define R_DMA_CH0_CMD__cmd__BITNR 0
+#define R_DMA_CH0_CMD__cmd__WIDTH 3
+#define R_DMA_CH0_CMD__cmd__hold 0
+#define R_DMA_CH0_CMD__cmd__start 1
+#define R_DMA_CH0_CMD__cmd__restart 3
+#define R_DMA_CH0_CMD__cmd__continue 3
+#define R_DMA_CH0_CMD__cmd__reset 4
+
+#define R_DMA_CH0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d1)
+#define R_DMA_CH0_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH0_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH0_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH0_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH0_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH0_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH0_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH0_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH0_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d2)
+#define R_DMA_CH0_STATUS__avail__BITNR 0
+#define R_DMA_CH0_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH1_HWSW (IO_TYPECAST_UDWORD 0xb0000110)
+#define R_DMA_CH1_HWSW__hw__BITNR 16
+#define R_DMA_CH1_HWSW__hw__WIDTH 16
+#define R_DMA_CH1_HWSW__sw__BITNR 0
+#define R_DMA_CH1_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH1_DESCR (IO_TYPECAST_UDWORD 0xb000011c)
+#define R_DMA_CH1_DESCR__descr__BITNR 0
+#define R_DMA_CH1_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH1_NEXT (IO_TYPECAST_UDWORD 0xb0000114)
+#define R_DMA_CH1_NEXT__next__BITNR 0
+#define R_DMA_CH1_NEXT__next__WIDTH 32
+
+#define R_DMA_CH1_BUF (IO_TYPECAST_UDWORD 0xb0000118)
+#define R_DMA_CH1_BUF__buf__BITNR 0
+#define R_DMA_CH1_BUF__buf__WIDTH 32
+
+#define R_DMA_CH1_FIRST (IO_TYPECAST_UDWORD 0xb00001a4)
+#define R_DMA_CH1_FIRST__first__BITNR 0
+#define R_DMA_CH1_FIRST__first__WIDTH 32
+
+#define R_DMA_CH1_CMD (IO_TYPECAST_BYTE 0xb00001d4)
+#define R_DMA_CH1_CMD__cmd__BITNR 0
+#define R_DMA_CH1_CMD__cmd__WIDTH 3
+#define R_DMA_CH1_CMD__cmd__hold 0
+#define R_DMA_CH1_CMD__cmd__start 1
+#define R_DMA_CH1_CMD__cmd__restart 3
+#define R_DMA_CH1_CMD__cmd__continue 3
+#define R_DMA_CH1_CMD__cmd__reset 4
+
+#define R_DMA_CH1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d5)
+#define R_DMA_CH1_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH1_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH1_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH1_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH1_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH1_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH1_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH1_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH1_STATUS (IO_TYPECAST_RO_BYTE 0xb00001d6)
+#define R_DMA_CH1_STATUS__avail__BITNR 0
+#define R_DMA_CH1_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH2_HWSW (IO_TYPECAST_UDWORD 0xb0000120)
+#define R_DMA_CH2_HWSW__hw__BITNR 16
+#define R_DMA_CH2_HWSW__hw__WIDTH 16
+#define R_DMA_CH2_HWSW__sw__BITNR 0
+#define R_DMA_CH2_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH2_DESCR (IO_TYPECAST_UDWORD 0xb000012c)
+#define R_DMA_CH2_DESCR__descr__BITNR 0
+#define R_DMA_CH2_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH2_NEXT (IO_TYPECAST_UDWORD 0xb0000124)
+#define R_DMA_CH2_NEXT__next__BITNR 0
+#define R_DMA_CH2_NEXT__next__WIDTH 32
+
+#define R_DMA_CH2_BUF (IO_TYPECAST_UDWORD 0xb0000128)
+#define R_DMA_CH2_BUF__buf__BITNR 0
+#define R_DMA_CH2_BUF__buf__WIDTH 32
+
+#define R_DMA_CH2_FIRST (IO_TYPECAST_UDWORD 0xb00001a8)
+#define R_DMA_CH2_FIRST__first__BITNR 0
+#define R_DMA_CH2_FIRST__first__WIDTH 32
+
+#define R_DMA_CH2_CMD (IO_TYPECAST_BYTE 0xb00001d8)
+#define R_DMA_CH2_CMD__cmd__BITNR 0
+#define R_DMA_CH2_CMD__cmd__WIDTH 3
+#define R_DMA_CH2_CMD__cmd__hold 0
+#define R_DMA_CH2_CMD__cmd__start 1
+#define R_DMA_CH2_CMD__cmd__restart 3
+#define R_DMA_CH2_CMD__cmd__continue 3
+#define R_DMA_CH2_CMD__cmd__reset 4
+
+#define R_DMA_CH2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001d9)
+#define R_DMA_CH2_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH2_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH2_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH2_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH2_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH2_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH2_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH2_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH2_STATUS (IO_TYPECAST_RO_BYTE 0xb00001da)
+#define R_DMA_CH2_STATUS__avail__BITNR 0
+#define R_DMA_CH2_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH3_HWSW (IO_TYPECAST_UDWORD 0xb0000130)
+#define R_DMA_CH3_HWSW__hw__BITNR 16
+#define R_DMA_CH3_HWSW__hw__WIDTH 16
+#define R_DMA_CH3_HWSW__sw__BITNR 0
+#define R_DMA_CH3_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH3_DESCR (IO_TYPECAST_UDWORD 0xb000013c)
+#define R_DMA_CH3_DESCR__descr__BITNR 0
+#define R_DMA_CH3_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH3_NEXT (IO_TYPECAST_UDWORD 0xb0000134)
+#define R_DMA_CH3_NEXT__next__BITNR 0
+#define R_DMA_CH3_NEXT__next__WIDTH 32
+
+#define R_DMA_CH3_BUF (IO_TYPECAST_UDWORD 0xb0000138)
+#define R_DMA_CH3_BUF__buf__BITNR 0
+#define R_DMA_CH3_BUF__buf__WIDTH 32
+
+#define R_DMA_CH3_FIRST (IO_TYPECAST_UDWORD 0xb00001ac)
+#define R_DMA_CH3_FIRST__first__BITNR 0
+#define R_DMA_CH3_FIRST__first__WIDTH 32
+
+#define R_DMA_CH3_CMD (IO_TYPECAST_BYTE 0xb00001dc)
+#define R_DMA_CH3_CMD__cmd__BITNR 0
+#define R_DMA_CH3_CMD__cmd__WIDTH 3
+#define R_DMA_CH3_CMD__cmd__hold 0
+#define R_DMA_CH3_CMD__cmd__start 1
+#define R_DMA_CH3_CMD__cmd__restart 3
+#define R_DMA_CH3_CMD__cmd__continue 3
+#define R_DMA_CH3_CMD__cmd__reset 4
+
+#define R_DMA_CH3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001dd)
+#define R_DMA_CH3_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH3_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH3_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH3_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH3_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH3_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH3_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH3_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH3_STATUS (IO_TYPECAST_RO_BYTE 0xb00001de)
+#define R_DMA_CH3_STATUS__avail__BITNR 0
+#define R_DMA_CH3_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH4_HWSW (IO_TYPECAST_UDWORD 0xb0000140)
+#define R_DMA_CH4_HWSW__hw__BITNR 16
+#define R_DMA_CH4_HWSW__hw__WIDTH 16
+#define R_DMA_CH4_HWSW__sw__BITNR 0
+#define R_DMA_CH4_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH4_DESCR (IO_TYPECAST_UDWORD 0xb000014c)
+#define R_DMA_CH4_DESCR__descr__BITNR 0
+#define R_DMA_CH4_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH4_NEXT (IO_TYPECAST_UDWORD 0xb0000144)
+#define R_DMA_CH4_NEXT__next__BITNR 0
+#define R_DMA_CH4_NEXT__next__WIDTH 32
+
+#define R_DMA_CH4_BUF (IO_TYPECAST_UDWORD 0xb0000148)
+#define R_DMA_CH4_BUF__buf__BITNR 0
+#define R_DMA_CH4_BUF__buf__WIDTH 32
+
+#define R_DMA_CH4_FIRST (IO_TYPECAST_UDWORD 0xb00001b0)
+#define R_DMA_CH4_FIRST__first__BITNR 0
+#define R_DMA_CH4_FIRST__first__WIDTH 32
+
+#define R_DMA_CH4_CMD (IO_TYPECAST_BYTE 0xb00001e0)
+#define R_DMA_CH4_CMD__cmd__BITNR 0
+#define R_DMA_CH4_CMD__cmd__WIDTH 3
+#define R_DMA_CH4_CMD__cmd__hold 0
+#define R_DMA_CH4_CMD__cmd__start 1
+#define R_DMA_CH4_CMD__cmd__restart 3
+#define R_DMA_CH4_CMD__cmd__continue 3
+#define R_DMA_CH4_CMD__cmd__reset 4
+
+#define R_DMA_CH4_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e1)
+#define R_DMA_CH4_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH4_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH4_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH4_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH4_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH4_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH4_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH4_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH4_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e2)
+#define R_DMA_CH4_STATUS__avail__BITNR 0
+#define R_DMA_CH4_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH5_HWSW (IO_TYPECAST_UDWORD 0xb0000150)
+#define R_DMA_CH5_HWSW__hw__BITNR 16
+#define R_DMA_CH5_HWSW__hw__WIDTH 16
+#define R_DMA_CH5_HWSW__sw__BITNR 0
+#define R_DMA_CH5_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH5_DESCR (IO_TYPECAST_UDWORD 0xb000015c)
+#define R_DMA_CH5_DESCR__descr__BITNR 0
+#define R_DMA_CH5_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH5_NEXT (IO_TYPECAST_UDWORD 0xb0000154)
+#define R_DMA_CH5_NEXT__next__BITNR 0
+#define R_DMA_CH5_NEXT__next__WIDTH 32
+
+#define R_DMA_CH5_BUF (IO_TYPECAST_UDWORD 0xb0000158)
+#define R_DMA_CH5_BUF__buf__BITNR 0
+#define R_DMA_CH5_BUF__buf__WIDTH 32
+
+#define R_DMA_CH5_FIRST (IO_TYPECAST_UDWORD 0xb00001b4)
+#define R_DMA_CH5_FIRST__first__BITNR 0
+#define R_DMA_CH5_FIRST__first__WIDTH 32
+
+#define R_DMA_CH5_CMD (IO_TYPECAST_BYTE 0xb00001e4)
+#define R_DMA_CH5_CMD__cmd__BITNR 0
+#define R_DMA_CH5_CMD__cmd__WIDTH 3
+#define R_DMA_CH5_CMD__cmd__hold 0
+#define R_DMA_CH5_CMD__cmd__start 1
+#define R_DMA_CH5_CMD__cmd__restart 3
+#define R_DMA_CH5_CMD__cmd__continue 3
+#define R_DMA_CH5_CMD__cmd__reset 4
+
+#define R_DMA_CH5_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e5)
+#define R_DMA_CH5_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH5_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH5_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH5_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH5_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH5_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH5_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH5_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH5_STATUS (IO_TYPECAST_RO_BYTE 0xb00001e6)
+#define R_DMA_CH5_STATUS__avail__BITNR 0
+#define R_DMA_CH5_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH6_HWSW (IO_TYPECAST_UDWORD 0xb0000160)
+#define R_DMA_CH6_HWSW__hw__BITNR 16
+#define R_DMA_CH6_HWSW__hw__WIDTH 16
+#define R_DMA_CH6_HWSW__sw__BITNR 0
+#define R_DMA_CH6_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH6_DESCR (IO_TYPECAST_UDWORD 0xb000016c)
+#define R_DMA_CH6_DESCR__descr__BITNR 0
+#define R_DMA_CH6_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH6_NEXT (IO_TYPECAST_UDWORD 0xb0000164)
+#define R_DMA_CH6_NEXT__next__BITNR 0
+#define R_DMA_CH6_NEXT__next__WIDTH 32
+
+#define R_DMA_CH6_BUF (IO_TYPECAST_UDWORD 0xb0000168)
+#define R_DMA_CH6_BUF__buf__BITNR 0
+#define R_DMA_CH6_BUF__buf__WIDTH 32
+
+#define R_DMA_CH6_FIRST (IO_TYPECAST_UDWORD 0xb00001b8)
+#define R_DMA_CH6_FIRST__first__BITNR 0
+#define R_DMA_CH6_FIRST__first__WIDTH 32
+
+#define R_DMA_CH6_CMD (IO_TYPECAST_BYTE 0xb00001e8)
+#define R_DMA_CH6_CMD__cmd__BITNR 0
+#define R_DMA_CH6_CMD__cmd__WIDTH 3
+#define R_DMA_CH6_CMD__cmd__hold 0
+#define R_DMA_CH6_CMD__cmd__start 1
+#define R_DMA_CH6_CMD__cmd__restart 3
+#define R_DMA_CH6_CMD__cmd__continue 3
+#define R_DMA_CH6_CMD__cmd__reset 4
+
+#define R_DMA_CH6_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e9)
+#define R_DMA_CH6_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH6_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH6_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH6_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH6_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH6_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH6_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH6_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH6_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ea)
+#define R_DMA_CH6_STATUS__avail__BITNR 0
+#define R_DMA_CH6_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH7_HWSW (IO_TYPECAST_UDWORD 0xb0000170)
+#define R_DMA_CH7_HWSW__hw__BITNR 16
+#define R_DMA_CH7_HWSW__hw__WIDTH 16
+#define R_DMA_CH7_HWSW__sw__BITNR 0
+#define R_DMA_CH7_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH7_DESCR (IO_TYPECAST_UDWORD 0xb000017c)
+#define R_DMA_CH7_DESCR__descr__BITNR 0
+#define R_DMA_CH7_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH7_NEXT (IO_TYPECAST_UDWORD 0xb0000174)
+#define R_DMA_CH7_NEXT__next__BITNR 0
+#define R_DMA_CH7_NEXT__next__WIDTH 32
+
+#define R_DMA_CH7_BUF (IO_TYPECAST_UDWORD 0xb0000178)
+#define R_DMA_CH7_BUF__buf__BITNR 0
+#define R_DMA_CH7_BUF__buf__WIDTH 32
+
+#define R_DMA_CH7_FIRST (IO_TYPECAST_UDWORD 0xb00001bc)
+#define R_DMA_CH7_FIRST__first__BITNR 0
+#define R_DMA_CH7_FIRST__first__WIDTH 32
+
+#define R_DMA_CH7_CMD (IO_TYPECAST_BYTE 0xb00001ec)
+#define R_DMA_CH7_CMD__cmd__BITNR 0
+#define R_DMA_CH7_CMD__cmd__WIDTH 3
+#define R_DMA_CH7_CMD__cmd__hold 0
+#define R_DMA_CH7_CMD__cmd__start 1
+#define R_DMA_CH7_CMD__cmd__restart 3
+#define R_DMA_CH7_CMD__cmd__continue 3
+#define R_DMA_CH7_CMD__cmd__reset 4
+
+#define R_DMA_CH7_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ed)
+#define R_DMA_CH7_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH7_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH7_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH7_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH7_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH7_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH7_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH7_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH7_STATUS (IO_TYPECAST_RO_BYTE 0xb00001ee)
+#define R_DMA_CH7_STATUS__avail__BITNR 0
+#define R_DMA_CH7_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH8_HWSW (IO_TYPECAST_UDWORD 0xb0000180)
+#define R_DMA_CH8_HWSW__hw__BITNR 16
+#define R_DMA_CH8_HWSW__hw__WIDTH 16
+#define R_DMA_CH8_HWSW__sw__BITNR 0
+#define R_DMA_CH8_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH8_DESCR (IO_TYPECAST_UDWORD 0xb000018c)
+#define R_DMA_CH8_DESCR__descr__BITNR 0
+#define R_DMA_CH8_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH8_NEXT (IO_TYPECAST_UDWORD 0xb0000184)
+#define R_DMA_CH8_NEXT__next__BITNR 0
+#define R_DMA_CH8_NEXT__next__WIDTH 32
+
+#define R_DMA_CH8_BUF (IO_TYPECAST_UDWORD 0xb0000188)
+#define R_DMA_CH8_BUF__buf__BITNR 0
+#define R_DMA_CH8_BUF__buf__WIDTH 32
+
+#define R_DMA_CH8_FIRST (IO_TYPECAST_UDWORD 0xb00001c0)
+#define R_DMA_CH8_FIRST__first__BITNR 0
+#define R_DMA_CH8_FIRST__first__WIDTH 32
+
+#define R_DMA_CH8_CMD (IO_TYPECAST_BYTE 0xb00001f0)
+#define R_DMA_CH8_CMD__cmd__BITNR 0
+#define R_DMA_CH8_CMD__cmd__WIDTH 3
+#define R_DMA_CH8_CMD__cmd__hold 0
+#define R_DMA_CH8_CMD__cmd__start 1
+#define R_DMA_CH8_CMD__cmd__restart 3
+#define R_DMA_CH8_CMD__cmd__continue 3
+#define R_DMA_CH8_CMD__cmd__reset 4
+
+#define R_DMA_CH8_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f1)
+#define R_DMA_CH8_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH8_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH8_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH8_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH8_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH8_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH8_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH8_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH8_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f2)
+#define R_DMA_CH8_STATUS__avail__BITNR 0
+#define R_DMA_CH8_STATUS__avail__WIDTH 7
+
+#define R_DMA_CH8_SUB (IO_TYPECAST_UDWORD 0xb000018c)
+#define R_DMA_CH8_SUB__sub__BITNR 0
+#define R_DMA_CH8_SUB__sub__WIDTH 32
+
+#define R_DMA_CH8_NEP (IO_TYPECAST_UDWORD 0xb00001c0)
+#define R_DMA_CH8_NEP__nep__BITNR 0
+#define R_DMA_CH8_NEP__nep__WIDTH 32
+
+#define R_DMA_CH8_SUB0_EP (IO_TYPECAST_UDWORD 0xb00001c8)
+#define R_DMA_CH8_SUB0_EP__ep__BITNR 0
+#define R_DMA_CH8_SUB0_EP__ep__WIDTH 32
+
+#define R_DMA_CH8_SUB0_CMD (IO_TYPECAST_BYTE 0xb00001d3)
+#define R_DMA_CH8_SUB0_CMD__cmd__BITNR 0
+#define R_DMA_CH8_SUB0_CMD__cmd__WIDTH 1
+#define R_DMA_CH8_SUB0_CMD__cmd__stop 0
+#define R_DMA_CH8_SUB0_CMD__cmd__start 1
+
+#define R_DMA_CH8_SUB0_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e3)
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__dont 0
+#define R_DMA_CH8_SUB0_CLR_INTR__clr_descr__do 1
+
+#define R_DMA_CH8_SUB1_EP (IO_TYPECAST_UDWORD 0xb00001cc)
+#define R_DMA_CH8_SUB1_EP__ep__BITNR 0
+#define R_DMA_CH8_SUB1_EP__ep__WIDTH 32
+
+#define R_DMA_CH8_SUB1_CMD (IO_TYPECAST_BYTE 0xb00001d7)
+#define R_DMA_CH8_SUB1_CMD__cmd__BITNR 0
+#define R_DMA_CH8_SUB1_CMD__cmd__WIDTH 1
+#define R_DMA_CH8_SUB1_CMD__cmd__stop 0
+#define R_DMA_CH8_SUB1_CMD__cmd__start 1
+
+#define R_DMA_CH8_SUB1_CLR_INTR (IO_TYPECAST_BYTE 0xb00001e7)
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__dont 0
+#define R_DMA_CH8_SUB1_CLR_INTR__clr_descr__do 1
+
+#define R_DMA_CH8_SUB2_EP (IO_TYPECAST_UDWORD 0xb00001f8)
+#define R_DMA_CH8_SUB2_EP__ep__BITNR 0
+#define R_DMA_CH8_SUB2_EP__ep__WIDTH 32
+
+#define R_DMA_CH8_SUB2_CMD (IO_TYPECAST_BYTE 0xb00001db)
+#define R_DMA_CH8_SUB2_CMD__cmd__BITNR 0
+#define R_DMA_CH8_SUB2_CMD__cmd__WIDTH 1
+#define R_DMA_CH8_SUB2_CMD__cmd__stop 0
+#define R_DMA_CH8_SUB2_CMD__cmd__start 1
+
+#define R_DMA_CH8_SUB2_CLR_INTR (IO_TYPECAST_BYTE 0xb00001eb)
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__dont 0
+#define R_DMA_CH8_SUB2_CLR_INTR__clr_descr__do 1
+
+#define R_DMA_CH8_SUB3_EP (IO_TYPECAST_UDWORD 0xb00001fc)
+#define R_DMA_CH8_SUB3_EP__ep__BITNR 0
+#define R_DMA_CH8_SUB3_EP__ep__WIDTH 32
+
+#define R_DMA_CH8_SUB3_CMD (IO_TYPECAST_BYTE 0xb00001df)
+#define R_DMA_CH8_SUB3_CMD__cmd__BITNR 0
+#define R_DMA_CH8_SUB3_CMD__cmd__WIDTH 1
+#define R_DMA_CH8_SUB3_CMD__cmd__stop 0
+#define R_DMA_CH8_SUB3_CMD__cmd__start 1
+
+#define R_DMA_CH8_SUB3_CLR_INTR (IO_TYPECAST_BYTE 0xb00001ef)
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__dont 0
+#define R_DMA_CH8_SUB3_CLR_INTR__clr_descr__do 1
+
+#define R_DMA_CH9_HWSW (IO_TYPECAST_UDWORD 0xb0000190)
+#define R_DMA_CH9_HWSW__hw__BITNR 16
+#define R_DMA_CH9_HWSW__hw__WIDTH 16
+#define R_DMA_CH9_HWSW__sw__BITNR 0
+#define R_DMA_CH9_HWSW__sw__WIDTH 16
+
+#define R_DMA_CH9_DESCR (IO_TYPECAST_UDWORD 0xb000019c)
+#define R_DMA_CH9_DESCR__descr__BITNR 0
+#define R_DMA_CH9_DESCR__descr__WIDTH 32
+
+#define R_DMA_CH9_NEXT (IO_TYPECAST_UDWORD 0xb0000194)
+#define R_DMA_CH9_NEXT__next__BITNR 0
+#define R_DMA_CH9_NEXT__next__WIDTH 32
+
+#define R_DMA_CH9_BUF (IO_TYPECAST_UDWORD 0xb0000198)
+#define R_DMA_CH9_BUF__buf__BITNR 0
+#define R_DMA_CH9_BUF__buf__WIDTH 32
+
+#define R_DMA_CH9_FIRST (IO_TYPECAST_UDWORD 0xb00001c4)
+#define R_DMA_CH9_FIRST__first__BITNR 0
+#define R_DMA_CH9_FIRST__first__WIDTH 32
+
+#define R_DMA_CH9_CMD (IO_TYPECAST_BYTE 0xb00001f4)
+#define R_DMA_CH9_CMD__cmd__BITNR 0
+#define R_DMA_CH9_CMD__cmd__WIDTH 3
+#define R_DMA_CH9_CMD__cmd__hold 0
+#define R_DMA_CH9_CMD__cmd__start 1
+#define R_DMA_CH9_CMD__cmd__restart 3
+#define R_DMA_CH9_CMD__cmd__continue 3
+#define R_DMA_CH9_CMD__cmd__reset 4
+
+#define R_DMA_CH9_CLR_INTR (IO_TYPECAST_BYTE 0xb00001f5)
+#define R_DMA_CH9_CLR_INTR__clr_eop__BITNR 1
+#define R_DMA_CH9_CLR_INTR__clr_eop__WIDTH 1
+#define R_DMA_CH9_CLR_INTR__clr_eop__do 1
+#define R_DMA_CH9_CLR_INTR__clr_eop__dont 0
+#define R_DMA_CH9_CLR_INTR__clr_descr__BITNR 0
+#define R_DMA_CH9_CLR_INTR__clr_descr__WIDTH 1
+#define R_DMA_CH9_CLR_INTR__clr_descr__do 1
+#define R_DMA_CH9_CLR_INTR__clr_descr__dont 0
+
+#define R_DMA_CH9_STATUS (IO_TYPECAST_RO_BYTE 0xb00001f6)
+#define R_DMA_CH9_STATUS__avail__BITNR 0
+#define R_DMA_CH9_STATUS__avail__WIDTH 7
+
+/*
+!* Test mode registers
+!*/
+
+#define R_TEST_MODE (IO_TYPECAST_UDWORD 0xb00000fc)
+#define R_TEST_MODE__single_step__BITNR 19
+#define R_TEST_MODE__single_step__WIDTH 1
+#define R_TEST_MODE__single_step__on 1
+#define R_TEST_MODE__single_step__off 0
+#define R_TEST_MODE__step_wr__BITNR 18
+#define R_TEST_MODE__step_wr__WIDTH 1
+#define R_TEST_MODE__step_wr__on 1
+#define R_TEST_MODE__step_wr__off 0
+#define R_TEST_MODE__step_rd__BITNR 17
+#define R_TEST_MODE__step_rd__WIDTH 1
+#define R_TEST_MODE__step_rd__on 1
+#define R_TEST_MODE__step_rd__off 0
+#define R_TEST_MODE__step_fetch__BITNR 16
+#define R_TEST_MODE__step_fetch__WIDTH 1
+#define R_TEST_MODE__step_fetch__on 1
+#define R_TEST_MODE__step_fetch__off 0
+#define R_TEST_MODE__mmu_test__BITNR 12
+#define R_TEST_MODE__mmu_test__WIDTH 1
+#define R_TEST_MODE__mmu_test__on 1
+#define R_TEST_MODE__mmu_test__off 0
+#define R_TEST_MODE__usb_test__BITNR 11
+#define R_TEST_MODE__usb_test__WIDTH 1
+#define R_TEST_MODE__usb_test__on 1
+#define R_TEST_MODE__usb_test__off 0
+#define R_TEST_MODE__scsi_timer_test__BITNR 10
+#define R_TEST_MODE__scsi_timer_test__WIDTH 1
+#define R_TEST_MODE__scsi_timer_test__on 1
+#define R_TEST_MODE__scsi_timer_test__off 0
+#define R_TEST_MODE__backoff__BITNR 9
+#define R_TEST_MODE__backoff__WIDTH 1
+#define R_TEST_MODE__backoff__on 1
+#define R_TEST_MODE__backoff__off 0
+#define R_TEST_MODE__snmp_test__BITNR 8
+#define R_TEST_MODE__snmp_test__WIDTH 1
+#define R_TEST_MODE__snmp_test__on 1
+#define R_TEST_MODE__snmp_test__off 0
+#define R_TEST_MODE__snmp_inc__BITNR 7
+#define R_TEST_MODE__snmp_inc__WIDTH 1
+#define R_TEST_MODE__snmp_inc__do 1
+#define R_TEST_MODE__snmp_inc__dont 0
+#define R_TEST_MODE__ser_loop__BITNR 6
+#define R_TEST_MODE__ser_loop__WIDTH 1
+#define R_TEST_MODE__ser_loop__on 1
+#define R_TEST_MODE__ser_loop__off 0
+#define R_TEST_MODE__baudrate__BITNR 5
+#define R_TEST_MODE__baudrate__WIDTH 1
+#define R_TEST_MODE__baudrate__on 1
+#define R_TEST_MODE__baudrate__off 0
+#define R_TEST_MODE__timer__BITNR 3
+#define R_TEST_MODE__timer__WIDTH 2
+#define R_TEST_MODE__timer__off 0
+#define R_TEST_MODE__timer__even 1
+#define R_TEST_MODE__timer__odd 2
+#define R_TEST_MODE__timer__all 3
+#define R_TEST_MODE__cache_test__BITNR 2
+#define R_TEST_MODE__cache_test__WIDTH 1
+#define R_TEST_MODE__cache_test__normal 0
+#define R_TEST_MODE__cache_test__test 1
+#define R_TEST_MODE__tag_test__BITNR 1
+#define R_TEST_MODE__tag_test__WIDTH 1
+#define R_TEST_MODE__tag_test__normal 0
+#define R_TEST_MODE__tag_test__test 1
+#define R_TEST_MODE__cache_enable__BITNR 0
+#define R_TEST_MODE__cache_enable__WIDTH 1
+#define R_TEST_MODE__cache_enable__enable 1
+#define R_TEST_MODE__cache_enable__disable 0
+
+#define R_SINGLE_STEP (IO_TYPECAST_BYTE 0xb00000fe)
+#define R_SINGLE_STEP__single_step__BITNR 3
+#define R_SINGLE_STEP__single_step__WIDTH 1
+#define R_SINGLE_STEP__single_step__on 1
+#define R_SINGLE_STEP__single_step__off 0
+#define R_SINGLE_STEP__step_wr__BITNR 2
+#define R_SINGLE_STEP__step_wr__WIDTH 1
+#define R_SINGLE_STEP__step_wr__on 1
+#define R_SINGLE_STEP__step_wr__off 0
+#define R_SINGLE_STEP__step_rd__BITNR 1
+#define R_SINGLE_STEP__step_rd__WIDTH 1
+#define R_SINGLE_STEP__step_rd__on 1
+#define R_SINGLE_STEP__step_rd__off 0
+#define R_SINGLE_STEP__step_fetch__BITNR 0
+#define R_SINGLE_STEP__step_fetch__WIDTH 1
+#define R_SINGLE_STEP__step_fetch__on 1
+#define R_SINGLE_STEP__step_fetch__off 0
+
+/*
+!* USB interface control registers
+!*/
+
+#define R_USB_REVISION (IO_TYPECAST_RO_BYTE 0xb0000200)
+#define R_USB_REVISION__major__BITNR 4
+#define R_USB_REVISION__major__WIDTH 4
+#define R_USB_REVISION__minor__BITNR 0
+#define R_USB_REVISION__minor__WIDTH 4
+#define R_USB_REVISION__minor__v1_v2 1
+#define R_USB_REVISION__minor__v3 0
+
+#define R_USB_COMMAND (IO_TYPECAST_BYTE 0xb0000201)
+#define R_USB_COMMAND__port_sel__BITNR 6
+#define R_USB_COMMAND__port_sel__WIDTH 2
+#define R_USB_COMMAND__port_sel__nop 0
+#define R_USB_COMMAND__port_sel__port1 1
+#define R_USB_COMMAND__port_sel__port2 2
+#define R_USB_COMMAND__port_sel__both 3
+#define R_USB_COMMAND__port_cmd__BITNR 4
+#define R_USB_COMMAND__port_cmd__WIDTH 2
+#define R_USB_COMMAND__port_cmd__reset 0
+#define R_USB_COMMAND__port_cmd__disable 1
+#define R_USB_COMMAND__port_cmd__suspend 2
+#define R_USB_COMMAND__port_cmd__resume 3
+#define R_USB_COMMAND__busy__BITNR 3
+#define R_USB_COMMAND__busy__WIDTH 1
+#define R_USB_COMMAND__busy__no 0
+#define R_USB_COMMAND__busy__yes 1
+#define R_USB_COMMAND__ctrl_cmd__BITNR 0
+#define R_USB_COMMAND__ctrl_cmd__WIDTH 3
+#define R_USB_COMMAND__ctrl_cmd__nop 0
+#define R_USB_COMMAND__ctrl_cmd__reset 1
+#define R_USB_COMMAND__ctrl_cmd__deconfig 2
+#define R_USB_COMMAND__ctrl_cmd__host_config 3
+#define R_USB_COMMAND__ctrl_cmd__dev_config 4
+#define R_USB_COMMAND__ctrl_cmd__host_nop 5
+#define R_USB_COMMAND__ctrl_cmd__host_run 6
+#define R_USB_COMMAND__ctrl_cmd__host_stop 7
+
+#define R_USB_COMMAND_DEV (IO_TYPECAST_BYTE 0xb0000201)
+#define R_USB_COMMAND_DEV__port_sel__BITNR 6
+#define R_USB_COMMAND_DEV__port_sel__WIDTH 2
+#define R_USB_COMMAND_DEV__port_sel__nop 0
+#define R_USB_COMMAND_DEV__port_sel__dummy1 1
+#define R_USB_COMMAND_DEV__port_sel__dummy2 2
+#define R_USB_COMMAND_DEV__port_sel__any 3
+#define R_USB_COMMAND_DEV__port_cmd__BITNR 4
+#define R_USB_COMMAND_DEV__port_cmd__WIDTH 2
+#define R_USB_COMMAND_DEV__port_cmd__active 0
+#define R_USB_COMMAND_DEV__port_cmd__passive 1
+#define R_USB_COMMAND_DEV__port_cmd__nop 2
+#define R_USB_COMMAND_DEV__port_cmd__wakeup 3
+#define R_USB_COMMAND_DEV__busy__BITNR 3
+#define R_USB_COMMAND_DEV__busy__WIDTH 1
+#define R_USB_COMMAND_DEV__busy__no 0
+#define R_USB_COMMAND_DEV__busy__yes 1
+#define R_USB_COMMAND_DEV__ctrl_cmd__BITNR 0
+#define R_USB_COMMAND_DEV__ctrl_cmd__WIDTH 3
+#define R_USB_COMMAND_DEV__ctrl_cmd__nop 0
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop 1
+#define R_USB_COMMAND_DEV__ctrl_cmd__deconfig 2
+#define R_USB_COMMAND_DEV__ctrl_cmd__host_config 3
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_config 4
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop2 5
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop3 6
+#define R_USB_COMMAND_DEV__ctrl_cmd__dev_nop4 7
+
+#define R_USB_STATUS (IO_TYPECAST_RO_BYTE 0xb0000202)
+#define R_USB_STATUS__ourun__BITNR 5
+#define R_USB_STATUS__ourun__WIDTH 1
+#define R_USB_STATUS__ourun__no 0
+#define R_USB_STATUS__ourun__yes 1
+#define R_USB_STATUS__perror__BITNR 4
+#define R_USB_STATUS__perror__WIDTH 1
+#define R_USB_STATUS__perror__no 0
+#define R_USB_STATUS__perror__yes 1
+#define R_USB_STATUS__device_mode__BITNR 3
+#define R_USB_STATUS__device_mode__WIDTH 1
+#define R_USB_STATUS__device_mode__no 0
+#define R_USB_STATUS__device_mode__yes 1
+#define R_USB_STATUS__host_mode__BITNR 2
+#define R_USB_STATUS__host_mode__WIDTH 1
+#define R_USB_STATUS__host_mode__no 0
+#define R_USB_STATUS__host_mode__yes 1
+#define R_USB_STATUS__started__BITNR 1
+#define R_USB_STATUS__started__WIDTH 1
+#define R_USB_STATUS__started__no 0
+#define R_USB_STATUS__started__yes 1
+#define R_USB_STATUS__running__BITNR 0
+#define R_USB_STATUS__running__WIDTH 1
+#define R_USB_STATUS__running__no 0
+#define R_USB_STATUS__running__yes 1
+
+#define R_USB_IRQ_MASK_SET (IO_TYPECAST_UWORD 0xb0000204)
+#define R_USB_IRQ_MASK_SET__iso_eof__BITNR 13
+#define R_USB_IRQ_MASK_SET__iso_eof__WIDTH 1
+#define R_USB_IRQ_MASK_SET__iso_eof__nop 0
+#define R_USB_IRQ_MASK_SET__iso_eof__set 1
+#define R_USB_IRQ_MASK_SET__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_SET__intr_eof__WIDTH 1
+#define R_USB_IRQ_MASK_SET__intr_eof__nop 0
+#define R_USB_IRQ_MASK_SET__intr_eof__set 1
+#define R_USB_IRQ_MASK_SET__iso_eot__BITNR 11
+#define R_USB_IRQ_MASK_SET__iso_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET__iso_eot__nop 0
+#define R_USB_IRQ_MASK_SET__iso_eot__set 1
+#define R_USB_IRQ_MASK_SET__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_SET__intr_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET__intr_eot__nop 0
+#define R_USB_IRQ_MASK_SET__intr_eot__set 1
+#define R_USB_IRQ_MASK_SET__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_SET__ctl_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET__ctl_eot__nop 0
+#define R_USB_IRQ_MASK_SET__ctl_eot__set 1
+#define R_USB_IRQ_MASK_SET__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_SET__bulk_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET__bulk_eot__nop 0
+#define R_USB_IRQ_MASK_SET__bulk_eot__set 1
+#define R_USB_IRQ_MASK_SET__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_SET__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_SET__epid_attn__nop 0
+#define R_USB_IRQ_MASK_SET__epid_attn__set 1
+#define R_USB_IRQ_MASK_SET__sof__BITNR 2
+#define R_USB_IRQ_MASK_SET__sof__WIDTH 1
+#define R_USB_IRQ_MASK_SET__sof__nop 0
+#define R_USB_IRQ_MASK_SET__sof__set 1
+#define R_USB_IRQ_MASK_SET__port_status__BITNR 1
+#define R_USB_IRQ_MASK_SET__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_SET__port_status__nop 0
+#define R_USB_IRQ_MASK_SET__port_status__set 1
+#define R_USB_IRQ_MASK_SET__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_SET__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_SET__ctl_status__nop 0
+#define R_USB_IRQ_MASK_SET__ctl_status__set 1
+
+#define R_USB_IRQ_MASK_READ (IO_TYPECAST_RO_UWORD 0xb0000204)
+#define R_USB_IRQ_MASK_READ__iso_eof__BITNR 13
+#define R_USB_IRQ_MASK_READ__iso_eof__WIDTH 1
+#define R_USB_IRQ_MASK_READ__iso_eof__no_pend 0
+#define R_USB_IRQ_MASK_READ__iso_eof__pend 1
+#define R_USB_IRQ_MASK_READ__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_READ__intr_eof__WIDTH 1
+#define R_USB_IRQ_MASK_READ__intr_eof__no_pend 0
+#define R_USB_IRQ_MASK_READ__intr_eof__pend 1
+#define R_USB_IRQ_MASK_READ__iso_eot__BITNR 11
+#define R_USB_IRQ_MASK_READ__iso_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ__iso_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__iso_eot__pend 1
+#define R_USB_IRQ_MASK_READ__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_READ__intr_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ__intr_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__intr_eot__pend 1
+#define R_USB_IRQ_MASK_READ__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_READ__ctl_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ__ctl_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__ctl_eot__pend 1
+#define R_USB_IRQ_MASK_READ__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_READ__bulk_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ__bulk_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ__bulk_eot__pend 1
+#define R_USB_IRQ_MASK_READ__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_READ__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_READ__epid_attn__no_pend 0
+#define R_USB_IRQ_MASK_READ__epid_attn__pend 1
+#define R_USB_IRQ_MASK_READ__sof__BITNR 2
+#define R_USB_IRQ_MASK_READ__sof__WIDTH 1
+#define R_USB_IRQ_MASK_READ__sof__no_pend 0
+#define R_USB_IRQ_MASK_READ__sof__pend 1
+#define R_USB_IRQ_MASK_READ__port_status__BITNR 1
+#define R_USB_IRQ_MASK_READ__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_READ__port_status__no_pend 0
+#define R_USB_IRQ_MASK_READ__port_status__pend 1
+#define R_USB_IRQ_MASK_READ__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_READ__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_READ__ctl_status__no_pend 0
+#define R_USB_IRQ_MASK_READ__ctl_status__pend 1
+
+#define R_USB_IRQ_MASK_CLR (IO_TYPECAST_UWORD 0xb0000206)
+#define R_USB_IRQ_MASK_CLR__iso_eof__BITNR 13
+#define R_USB_IRQ_MASK_CLR__iso_eof__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__iso_eof__nop 0
+#define R_USB_IRQ_MASK_CLR__iso_eof__clr 1
+#define R_USB_IRQ_MASK_CLR__intr_eof__BITNR 12
+#define R_USB_IRQ_MASK_CLR__intr_eof__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__intr_eof__nop 0
+#define R_USB_IRQ_MASK_CLR__intr_eof__clr 1
+#define R_USB_IRQ_MASK_CLR__iso_eot__BITNR 11
+#define R_USB_IRQ_MASK_CLR__iso_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__iso_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__iso_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__intr_eot__BITNR 10
+#define R_USB_IRQ_MASK_CLR__intr_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__intr_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__intr_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__ctl_eot__BITNR 9
+#define R_USB_IRQ_MASK_CLR__ctl_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__ctl_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__ctl_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__bulk_eot__BITNR 8
+#define R_USB_IRQ_MASK_CLR__bulk_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__bulk_eot__nop 0
+#define R_USB_IRQ_MASK_CLR__bulk_eot__clr 1
+#define R_USB_IRQ_MASK_CLR__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_CLR__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__epid_attn__nop 0
+#define R_USB_IRQ_MASK_CLR__epid_attn__clr 1
+#define R_USB_IRQ_MASK_CLR__sof__BITNR 2
+#define R_USB_IRQ_MASK_CLR__sof__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__sof__nop 0
+#define R_USB_IRQ_MASK_CLR__sof__clr 1
+#define R_USB_IRQ_MASK_CLR__port_status__BITNR 1
+#define R_USB_IRQ_MASK_CLR__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__port_status__nop 0
+#define R_USB_IRQ_MASK_CLR__port_status__clr 1
+#define R_USB_IRQ_MASK_CLR__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_CLR__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_CLR__ctl_status__nop 0
+#define R_USB_IRQ_MASK_CLR__ctl_status__clr 1
+
+#define R_USB_IRQ_READ (IO_TYPECAST_RO_UWORD 0xb0000206)
+#define R_USB_IRQ_READ__iso_eof__BITNR 13
+#define R_USB_IRQ_READ__iso_eof__WIDTH 1
+#define R_USB_IRQ_READ__iso_eof__no_pend 0
+#define R_USB_IRQ_READ__iso_eof__pend 1
+#define R_USB_IRQ_READ__intr_eof__BITNR 12
+#define R_USB_IRQ_READ__intr_eof__WIDTH 1
+#define R_USB_IRQ_READ__intr_eof__no_pend 0
+#define R_USB_IRQ_READ__intr_eof__pend 1
+#define R_USB_IRQ_READ__iso_eot__BITNR 11
+#define R_USB_IRQ_READ__iso_eot__WIDTH 1
+#define R_USB_IRQ_READ__iso_eot__no_pend 0
+#define R_USB_IRQ_READ__iso_eot__pend 1
+#define R_USB_IRQ_READ__intr_eot__BITNR 10
+#define R_USB_IRQ_READ__intr_eot__WIDTH 1
+#define R_USB_IRQ_READ__intr_eot__no_pend 0
+#define R_USB_IRQ_READ__intr_eot__pend 1
+#define R_USB_IRQ_READ__ctl_eot__BITNR 9
+#define R_USB_IRQ_READ__ctl_eot__WIDTH 1
+#define R_USB_IRQ_READ__ctl_eot__no_pend 0
+#define R_USB_IRQ_READ__ctl_eot__pend 1
+#define R_USB_IRQ_READ__bulk_eot__BITNR 8
+#define R_USB_IRQ_READ__bulk_eot__WIDTH 1
+#define R_USB_IRQ_READ__bulk_eot__no_pend 0
+#define R_USB_IRQ_READ__bulk_eot__pend 1
+#define R_USB_IRQ_READ__epid_attn__BITNR 3
+#define R_USB_IRQ_READ__epid_attn__WIDTH 1
+#define R_USB_IRQ_READ__epid_attn__no_pend 0
+#define R_USB_IRQ_READ__epid_attn__pend 1
+#define R_USB_IRQ_READ__sof__BITNR 2
+#define R_USB_IRQ_READ__sof__WIDTH 1
+#define R_USB_IRQ_READ__sof__no_pend 0
+#define R_USB_IRQ_READ__sof__pend 1
+#define R_USB_IRQ_READ__port_status__BITNR 1
+#define R_USB_IRQ_READ__port_status__WIDTH 1
+#define R_USB_IRQ_READ__port_status__no_pend 0
+#define R_USB_IRQ_READ__port_status__pend 1
+#define R_USB_IRQ_READ__ctl_status__BITNR 0
+#define R_USB_IRQ_READ__ctl_status__WIDTH 1
+#define R_USB_IRQ_READ__ctl_status__no_pend 0
+#define R_USB_IRQ_READ__ctl_status__pend 1
+
+#define R_USB_IRQ_MASK_SET_DEV (IO_TYPECAST_UWORD 0xb0000204)
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__out_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep3_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep2_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep1_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ep0_in_eot__set 1
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__epid_attn__set 1
+#define R_USB_IRQ_MASK_SET_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_SET_DEV__sof__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__sof__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__sof__set 1
+#define R_USB_IRQ_MASK_SET_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_SET_DEV__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__port_status__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__port_status__set 1
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__nop 0
+#define R_USB_IRQ_MASK_SET_DEV__ctl_status__set 1
+
+#define R_USB_IRQ_MASK_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000204)
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__out_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep3_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep2_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep1_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ep0_in_eot__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__epid_attn__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_READ_DEV__sof__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__sof__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__sof__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_READ_DEV__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__port_status__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__port_status__pend 1
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__no_pend 0
+#define R_USB_IRQ_MASK_READ_DEV__ctl_status__pend 1
+
+#define R_USB_IRQ_MASK_CLR_DEV (IO_TYPECAST_UWORD 0xb0000206)
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__out_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep3_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep2_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep1_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ep0_in_eot__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__epid_attn__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__sof__BITNR 2
+#define R_USB_IRQ_MASK_CLR_DEV__sof__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__sof__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__sof__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__BITNR 1
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__port_status__clr 1
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__BITNR 0
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__WIDTH 1
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__nop 0
+#define R_USB_IRQ_MASK_CLR_DEV__ctl_status__clr 1
+
+#define R_USB_IRQ_READ_DEV (IO_TYPECAST_RO_UWORD 0xb0000206)
+#define R_USB_IRQ_READ_DEV__out_eot__BITNR 12
+#define R_USB_IRQ_READ_DEV__out_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__out_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__out_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__BITNR 11
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep3_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__BITNR 10
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep2_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__BITNR 9
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep1_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__BITNR 8
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__no_pend 0
+#define R_USB_IRQ_READ_DEV__ep0_in_eot__pend 1
+#define R_USB_IRQ_READ_DEV__epid_attn__BITNR 3
+#define R_USB_IRQ_READ_DEV__epid_attn__WIDTH 1
+#define R_USB_IRQ_READ_DEV__epid_attn__no_pend 0
+#define R_USB_IRQ_READ_DEV__epid_attn__pend 1
+#define R_USB_IRQ_READ_DEV__sof__BITNR 2
+#define R_USB_IRQ_READ_DEV__sof__WIDTH 1
+#define R_USB_IRQ_READ_DEV__sof__no_pend 0
+#define R_USB_IRQ_READ_DEV__sof__pend 1
+#define R_USB_IRQ_READ_DEV__port_status__BITNR 1
+#define R_USB_IRQ_READ_DEV__port_status__WIDTH 1
+#define R_USB_IRQ_READ_DEV__port_status__no_pend 0
+#define R_USB_IRQ_READ_DEV__port_status__pend 1
+#define R_USB_IRQ_READ_DEV__ctl_status__BITNR 0
+#define R_USB_IRQ_READ_DEV__ctl_status__WIDTH 1
+#define R_USB_IRQ_READ_DEV__ctl_status__no_pend 0
+#define R_USB_IRQ_READ_DEV__ctl_status__pend 1
+
+#define R_USB_FM_NUMBER (IO_TYPECAST_UDWORD 0xb000020c)
+#define R_USB_FM_NUMBER__value__BITNR 0
+#define R_USB_FM_NUMBER__value__WIDTH 32
+
+#define R_USB_FM_NUMBER_DEV (IO_TYPECAST_UDWORD 0xb000020c)
+#define R_USB_FM_NUMBER_DEV__sign__BITNR 31
+#define R_USB_FM_NUMBER_DEV__sign__WIDTH 1
+#define R_USB_FM_NUMBER_DEV__sign__early 0
+#define R_USB_FM_NUMBER_DEV__sign__late 1
+#define R_USB_FM_NUMBER_DEV__deviation__BITNR 24
+#define R_USB_FM_NUMBER_DEV__deviation__WIDTH 7
+#define R_USB_FM_NUMBER_DEV__fm_number__BITNR 0
+#define R_USB_FM_NUMBER_DEV__fm_number__WIDTH 11
+
+#define R_USB_FM_INTERVAL (IO_TYPECAST_UWORD 0xb0000210)
+#define R_USB_FM_INTERVAL__fixed__BITNR 6
+#define R_USB_FM_INTERVAL__fixed__WIDTH 8
+#define R_USB_FM_INTERVAL__adj__BITNR 0
+#define R_USB_FM_INTERVAL__adj__WIDTH 6
+
+#define R_USB_FM_REMAINING (IO_TYPECAST_RO_UWORD 0xb0000212)
+#define R_USB_FM_REMAINING__value__BITNR 0
+#define R_USB_FM_REMAINING__value__WIDTH 14
+
+#define R_USB_FM_PSTART (IO_TYPECAST_UWORD 0xb0000214)
+#define R_USB_FM_PSTART__value__BITNR 0
+#define R_USB_FM_PSTART__value__WIDTH 14
+
+#define R_USB_RH_STATUS (IO_TYPECAST_RO_BYTE 0xb0000203)
+#define R_USB_RH_STATUS__babble2__BITNR 7
+#define R_USB_RH_STATUS__babble2__WIDTH 1
+#define R_USB_RH_STATUS__babble2__no 0
+#define R_USB_RH_STATUS__babble2__yes 1
+#define R_USB_RH_STATUS__babble1__BITNR 6
+#define R_USB_RH_STATUS__babble1__WIDTH 1
+#define R_USB_RH_STATUS__babble1__no 0
+#define R_USB_RH_STATUS__babble1__yes 1
+#define R_USB_RH_STATUS__bus1__BITNR 4
+#define R_USB_RH_STATUS__bus1__WIDTH 2
+#define R_USB_RH_STATUS__bus1__SE0 0
+#define R_USB_RH_STATUS__bus1__Diff0 1
+#define R_USB_RH_STATUS__bus1__Diff1 2
+#define R_USB_RH_STATUS__bus1__SE1 3
+#define R_USB_RH_STATUS__bus2__BITNR 2
+#define R_USB_RH_STATUS__bus2__WIDTH 2
+#define R_USB_RH_STATUS__bus2__SE0 0
+#define R_USB_RH_STATUS__bus2__Diff0 1
+#define R_USB_RH_STATUS__bus2__Diff1 2
+#define R_USB_RH_STATUS__bus2__SE1 3
+#define R_USB_RH_STATUS__nports__BITNR 0
+#define R_USB_RH_STATUS__nports__WIDTH 2
+
+#define R_USB_RH_PORT_STATUS_1 (IO_TYPECAST_RO_UWORD 0xb0000218)
+#define R_USB_RH_PORT_STATUS_1__speed__BITNR 9
+#define R_USB_RH_PORT_STATUS_1__speed__WIDTH 1
+#define R_USB_RH_PORT_STATUS_1__speed__full 0
+#define R_USB_RH_PORT_STATUS_1__speed__low 1
+#define R_USB_RH_PORT_STATUS_1__power__BITNR 8
+#define R_USB_RH_PORT_STATUS_1__power__WIDTH 1
+#define R_USB_RH_PORT_STATUS_1__reset__BITNR 4
+#define R_USB_RH_PORT_STATUS_1__reset__WIDTH 1
+#define R_USB_RH_PORT_STATUS_1__reset__no 0
+#define R_USB_RH_PORT_STATUS_1__reset__yes 1
+#define R_USB_RH_PORT_STATUS_1__overcurrent__BITNR 3
+#define R_USB_RH_PORT_STATUS_1__overcurrent__WIDTH 1
+#define R_USB_RH_PORT_STATUS_1__overcurrent__no 0
+#define R_USB_RH_PORT_STATUS_1__overcurrent__yes 1
+#define R_USB_RH_PORT_STATUS_1__suspended__BITNR 2
+#define R_USB_RH_PORT_STATUS_1__suspended__WIDTH 1
+#define R_USB_RH_PORT_STATUS_1__suspended__no 0
+#define R_USB_RH_PORT_STATUS_1__suspended__yes 1
+#define R_USB_RH_PORT_STATUS_1__enabled__BITNR 1
+#define R_USB_RH_PORT_STATUS_1__enabled__WIDTH 1
+#define R_USB_RH_PORT_STATUS_1__enabled__no 0
+#define R_USB_RH_PORT_STATUS_1__enabled__yes 1
+#define R_USB_RH_PORT_STATUS_1__connected__BITNR 0
+#define R_USB_RH_PORT_STATUS_1__connected__WIDTH 1
+#define R_USB_RH_PORT_STATUS_1__connected__no 0
+#define R_USB_RH_PORT_STATUS_1__connected__yes 1
+
+#define R_USB_RH_PORT_STATUS_2 (IO_TYPECAST_RO_UWORD 0xb000021a)
+#define R_USB_RH_PORT_STATUS_2__speed__BITNR 9
+#define R_USB_RH_PORT_STATUS_2__speed__WIDTH 1
+#define R_USB_RH_PORT_STATUS_2__speed__full 0
+#define R_USB_RH_PORT_STATUS_2__speed__low 1
+#define R_USB_RH_PORT_STATUS_2__power__BITNR 8
+#define R_USB_RH_PORT_STATUS_2__power__WIDTH 1
+#define R_USB_RH_PORT_STATUS_2__reset__BITNR 4
+#define R_USB_RH_PORT_STATUS_2__reset__WIDTH 1
+#define R_USB_RH_PORT_STATUS_2__reset__no 0
+#define R_USB_RH_PORT_STATUS_2__reset__yes 1
+#define R_USB_RH_PORT_STATUS_2__overcurrent__BITNR 3
+#define R_USB_RH_PORT_STATUS_2__overcurrent__WIDTH 1
+#define R_USB_RH_PORT_STATUS_2__overcurrent__no 0
+#define R_USB_RH_PORT_STATUS_2__overcurrent__yes 1
+#define R_USB_RH_PORT_STATUS_2__suspended__BITNR 2
+#define R_USB_RH_PORT_STATUS_2__suspended__WIDTH 1
+#define R_USB_RH_PORT_STATUS_2__suspended__no 0
+#define R_USB_RH_PORT_STATUS_2__suspended__yes 1
+#define R_USB_RH_PORT_STATUS_2__enabled__BITNR 1
+#define R_USB_RH_PORT_STATUS_2__enabled__WIDTH 1
+#define R_USB_RH_PORT_STATUS_2__enabled__no 0
+#define R_USB_RH_PORT_STATUS_2__enabled__yes 1
+#define R_USB_RH_PORT_STATUS_2__connected__BITNR 0
+#define R_USB_RH_PORT_STATUS_2__connected__WIDTH 1
+#define R_USB_RH_PORT_STATUS_2__connected__no 0
+#define R_USB_RH_PORT_STATUS_2__connected__yes 1
+
+#define R_USB_EPT_INDEX (IO_TYPECAST_BYTE 0xb0000208)
+#define R_USB_EPT_INDEX__value__BITNR 0
+#define R_USB_EPT_INDEX__value__WIDTH 5
+
+#define R_USB_EPT_DATA (IO_TYPECAST_UDWORD 0xb000021c)
+#define R_USB_EPT_DATA__valid__BITNR 31
+#define R_USB_EPT_DATA__valid__WIDTH 1
+#define R_USB_EPT_DATA__valid__no 0
+#define R_USB_EPT_DATA__valid__yes 1
+#define R_USB_EPT_DATA__hold__BITNR 30
+#define R_USB_EPT_DATA__hold__WIDTH 1
+#define R_USB_EPT_DATA__hold__no 0
+#define R_USB_EPT_DATA__hold__yes 1
+#define R_USB_EPT_DATA__error_count_in__BITNR 28
+#define R_USB_EPT_DATA__error_count_in__WIDTH 2
+#define R_USB_EPT_DATA__t_in__BITNR 27
+#define R_USB_EPT_DATA__t_in__WIDTH 1
+#define R_USB_EPT_DATA__low_speed__BITNR 26
+#define R_USB_EPT_DATA__low_speed__WIDTH 1
+#define R_USB_EPT_DATA__low_speed__no 0
+#define R_USB_EPT_DATA__low_speed__yes 1
+#define R_USB_EPT_DATA__port__BITNR 24
+#define R_USB_EPT_DATA__port__WIDTH 2
+#define R_USB_EPT_DATA__port__any 0
+#define R_USB_EPT_DATA__port__p1 1
+#define R_USB_EPT_DATA__port__p2 2
+#define R_USB_EPT_DATA__port__undef 3
+#define R_USB_EPT_DATA__error_code__BITNR 22
+#define R_USB_EPT_DATA__error_code__WIDTH 2
+#define R_USB_EPT_DATA__error_code__no_error 0
+#define R_USB_EPT_DATA__error_code__stall 1
+#define R_USB_EPT_DATA__error_code__bus_error 2
+#define R_USB_EPT_DATA__error_code__buffer_error 3
+#define R_USB_EPT_DATA__t_out__BITNR 21
+#define R_USB_EPT_DATA__t_out__WIDTH 1
+#define R_USB_EPT_DATA__error_count_out__BITNR 19
+#define R_USB_EPT_DATA__error_count_out__WIDTH 2
+#define R_USB_EPT_DATA__max_len__BITNR 11
+#define R_USB_EPT_DATA__max_len__WIDTH 7
+#define R_USB_EPT_DATA__ep__BITNR 7
+#define R_USB_EPT_DATA__ep__WIDTH 4
+#define R_USB_EPT_DATA__dev__BITNR 0
+#define R_USB_EPT_DATA__dev__WIDTH 7
+
+#define R_USB_EPT_DATA_ISO (IO_TYPECAST_UDWORD 0xb000021c)
+#define R_USB_EPT_DATA_ISO__valid__BITNR 31
+#define R_USB_EPT_DATA_ISO__valid__WIDTH 1
+#define R_USB_EPT_DATA_ISO__valid__no 0
+#define R_USB_EPT_DATA_ISO__valid__yes 1
+#define R_USB_EPT_DATA_ISO__port__BITNR 24
+#define R_USB_EPT_DATA_ISO__port__WIDTH 2
+#define R_USB_EPT_DATA_ISO__port__any 0
+#define R_USB_EPT_DATA_ISO__port__p1 1
+#define R_USB_EPT_DATA_ISO__port__p2 2
+#define R_USB_EPT_DATA_ISO__port__undef 3
+#define R_USB_EPT_DATA_ISO__error_code__BITNR 22
+#define R_USB_EPT_DATA_ISO__error_code__WIDTH 2
+#define R_USB_EPT_DATA_ISO__error_code__no_error 0
+#define R_USB_EPT_DATA_ISO__error_code__stall 1
+#define R_USB_EPT_DATA_ISO__error_code__bus_error 2
+#define R_USB_EPT_DATA_ISO__error_code__TBD3 3
+#define R_USB_EPT_DATA_ISO__max_len__BITNR 11
+#define R_USB_EPT_DATA_ISO__max_len__WIDTH 10
+#define R_USB_EPT_DATA_ISO__ep__BITNR 7
+#define R_USB_EPT_DATA_ISO__ep__WIDTH 4
+#define R_USB_EPT_DATA_ISO__dev__BITNR 0
+#define R_USB_EPT_DATA_ISO__dev__WIDTH 7
+
+#define R_USB_EPT_DATA_DEV (IO_TYPECAST_UDWORD 0xb000021c)
+#define R_USB_EPT_DATA_DEV__valid__BITNR 31
+#define R_USB_EPT_DATA_DEV__valid__WIDTH 1
+#define R_USB_EPT_DATA_DEV__valid__no 0
+#define R_USB_EPT_DATA_DEV__valid__yes 1
+#define R_USB_EPT_DATA_DEV__hold__BITNR 30
+#define R_USB_EPT_DATA_DEV__hold__WIDTH 1
+#define R_USB_EPT_DATA_DEV__hold__no 0
+#define R_USB_EPT_DATA_DEV__hold__yes 1
+#define R_USB_EPT_DATA_DEV__stall__BITNR 29
+#define R_USB_EPT_DATA_DEV__stall__WIDTH 1
+#define R_USB_EPT_DATA_DEV__stall__no 0
+#define R_USB_EPT_DATA_DEV__stall__yes 1
+#define R_USB_EPT_DATA_DEV__iso_resp__BITNR 28
+#define R_USB_EPT_DATA_DEV__iso_resp__WIDTH 1
+#define R_USB_EPT_DATA_DEV__iso_resp__quiet 0
+#define R_USB_EPT_DATA_DEV__iso_resp__yes 1
+#define R_USB_EPT_DATA_DEV__ctrl__BITNR 27
+#define R_USB_EPT_DATA_DEV__ctrl__WIDTH 1
+#define R_USB_EPT_DATA_DEV__ctrl__no 0
+#define R_USB_EPT_DATA_DEV__ctrl__yes 1
+#define R_USB_EPT_DATA_DEV__iso__BITNR 26
+#define R_USB_EPT_DATA_DEV__iso__WIDTH 1
+#define R_USB_EPT_DATA_DEV__iso__no 0
+#define R_USB_EPT_DATA_DEV__iso__yes 1
+#define R_USB_EPT_DATA_DEV__port__BITNR 24
+#define R_USB_EPT_DATA_DEV__port__WIDTH 2
+#define R_USB_EPT_DATA_DEV__control_phase__BITNR 22
+#define R_USB_EPT_DATA_DEV__control_phase__WIDTH 1
+#define R_USB_EPT_DATA_DEV__t__BITNR 21
+#define R_USB_EPT_DATA_DEV__t__WIDTH 1
+#define R_USB_EPT_DATA_DEV__max_len__BITNR 11
+#define R_USB_EPT_DATA_DEV__max_len__WIDTH 10
+#define R_USB_EPT_DATA_DEV__ep__BITNR 7
+#define R_USB_EPT_DATA_DEV__ep__WIDTH 4
+#define R_USB_EPT_DATA_DEV__dev__BITNR 0
+#define R_USB_EPT_DATA_DEV__dev__WIDTH 7
+
+#define R_USB_SNMP_TERROR (IO_TYPECAST_UDWORD 0xb0000220)
+#define R_USB_SNMP_TERROR__value__BITNR 0
+#define R_USB_SNMP_TERROR__value__WIDTH 32
+
+#define R_USB_EPID_ATTN (IO_TYPECAST_RO_UDWORD 0xb0000224)
+#define R_USB_EPID_ATTN__value__BITNR 0
+#define R_USB_EPID_ATTN__value__WIDTH 32
+
+#define R_USB_PORT1_DISABLE (IO_TYPECAST_BYTE 0xb000006a)
+#define R_USB_PORT1_DISABLE__disable__BITNR 0
+#define R_USB_PORT1_DISABLE__disable__WIDTH 1
+#define R_USB_PORT1_DISABLE__disable__yes 0
+#define R_USB_PORT1_DISABLE__disable__no 1
+
+#define R_USB_PORT2_DISABLE (IO_TYPECAST_BYTE 0xb0000052)
+#define R_USB_PORT2_DISABLE__disable__BITNR 0
+#define R_USB_PORT2_DISABLE__disable__WIDTH 1
+#define R_USB_PORT2_DISABLE__disable__yes 0
+#define R_USB_PORT2_DISABLE__disable__no 1
+
+/*
+!* MMU registers
+!*/
+
+#define R_MMU_CONFIG (IO_TYPECAST_UDWORD 0xb0000240)
+#define R_MMU_CONFIG__mmu_enable__BITNR 31
+#define R_MMU_CONFIG__mmu_enable__WIDTH 1
+#define R_MMU_CONFIG__mmu_enable__enable 1
+#define R_MMU_CONFIG__mmu_enable__disable 0
+#define R_MMU_CONFIG__inv_excp__BITNR 18
+#define R_MMU_CONFIG__inv_excp__WIDTH 1
+#define R_MMU_CONFIG__inv_excp__enable 1
+#define R_MMU_CONFIG__inv_excp__disable 0
+#define R_MMU_CONFIG__acc_excp__BITNR 17
+#define R_MMU_CONFIG__acc_excp__WIDTH 1
+#define R_MMU_CONFIG__acc_excp__enable 1
+#define R_MMU_CONFIG__acc_excp__disable 0
+#define R_MMU_CONFIG__we_excp__BITNR 16
+#define R_MMU_CONFIG__we_excp__WIDTH 1
+#define R_MMU_CONFIG__we_excp__enable 1
+#define R_MMU_CONFIG__we_excp__disable 0
+#define R_MMU_CONFIG__seg_f__BITNR 15
+#define R_MMU_CONFIG__seg_f__WIDTH 1
+#define R_MMU_CONFIG__seg_f__seg 1
+#define R_MMU_CONFIG__seg_f__page 0
+#define R_MMU_CONFIG__seg_e__BITNR 14
+#define R_MMU_CONFIG__seg_e__WIDTH 1
+#define R_MMU_CONFIG__seg_e__seg 1
+#define R_MMU_CONFIG__seg_e__page 0
+#define R_MMU_CONFIG__seg_d__BITNR 13
+#define R_MMU_CONFIG__seg_d__WIDTH 1
+#define R_MMU_CONFIG__seg_d__seg 1
+#define R_MMU_CONFIG__seg_d__page 0
+#define R_MMU_CONFIG__seg_c__BITNR 12
+#define R_MMU_CONFIG__seg_c__WIDTH 1
+#define R_MMU_CONFIG__seg_c__seg 1
+#define R_MMU_CONFIG__seg_c__page 0
+#define R_MMU_CONFIG__seg_b__BITNR 11
+#define R_MMU_CONFIG__seg_b__WIDTH 1
+#define R_MMU_CONFIG__seg_b__seg 1
+#define R_MMU_CONFIG__seg_b__page 0
+#define R_MMU_CONFIG__seg_a__BITNR 10
+#define R_MMU_CONFIG__seg_a__WIDTH 1
+#define R_MMU_CONFIG__seg_a__seg 1
+#define R_MMU_CONFIG__seg_a__page 0
+#define R_MMU_CONFIG__seg_9__BITNR 9
+#define R_MMU_CONFIG__seg_9__WIDTH 1
+#define R_MMU_CONFIG__seg_9__seg 1
+#define R_MMU_CONFIG__seg_9__page 0
+#define R_MMU_CONFIG__seg_8__BITNR 8
+#define R_MMU_CONFIG__seg_8__WIDTH 1
+#define R_MMU_CONFIG__seg_8__seg 1
+#define R_MMU_CONFIG__seg_8__page 0
+#define R_MMU_CONFIG__seg_7__BITNR 7
+#define R_MMU_CONFIG__seg_7__WIDTH 1
+#define R_MMU_CONFIG__seg_7__seg 1
+#define R_MMU_CONFIG__seg_7__page 0
+#define R_MMU_CONFIG__seg_6__BITNR 6
+#define R_MMU_CONFIG__seg_6__WIDTH 1
+#define R_MMU_CONFIG__seg_6__seg 1
+#define R_MMU_CONFIG__seg_6__page 0
+#define R_MMU_CONFIG__seg_5__BITNR 5
+#define R_MMU_CONFIG__seg_5__WIDTH 1
+#define R_MMU_CONFIG__seg_5__seg 1
+#define R_MMU_CONFIG__seg_5__page 0
+#define R_MMU_CONFIG__seg_4__BITNR 4
+#define R_MMU_CONFIG__seg_4__WIDTH 1
+#define R_MMU_CONFIG__seg_4__seg 1
+#define R_MMU_CONFIG__seg_4__page 0
+#define R_MMU_CONFIG__seg_3__BITNR 3
+#define R_MMU_CONFIG__seg_3__WIDTH 1
+#define R_MMU_CONFIG__seg_3__seg 1
+#define R_MMU_CONFIG__seg_3__page 0
+#define R_MMU_CONFIG__seg_2__BITNR 2
+#define R_MMU_CONFIG__seg_2__WIDTH 1
+#define R_MMU_CONFIG__seg_2__seg 1
+#define R_MMU_CONFIG__seg_2__page 0
+#define R_MMU_CONFIG__seg_1__BITNR 1
+#define R_MMU_CONFIG__seg_1__WIDTH 1
+#define R_MMU_CONFIG__seg_1__seg 1
+#define R_MMU_CONFIG__seg_1__page 0
+#define R_MMU_CONFIG__seg_0__BITNR 0
+#define R_MMU_CONFIG__seg_0__WIDTH 1
+#define R_MMU_CONFIG__seg_0__seg 1
+#define R_MMU_CONFIG__seg_0__page 0
+
+#define R_MMU_KSEG (IO_TYPECAST_UWORD 0xb0000240)
+#define R_MMU_KSEG__seg_f__BITNR 15
+#define R_MMU_KSEG__seg_f__WIDTH 1
+#define R_MMU_KSEG__seg_f__seg 1
+#define R_MMU_KSEG__seg_f__page 0
+#define R_MMU_KSEG__seg_e__BITNR 14
+#define R_MMU_KSEG__seg_e__WIDTH 1
+#define R_MMU_KSEG__seg_e__seg 1
+#define R_MMU_KSEG__seg_e__page 0
+#define R_MMU_KSEG__seg_d__BITNR 13
+#define R_MMU_KSEG__seg_d__WIDTH 1
+#define R_MMU_KSEG__seg_d__seg 1
+#define R_MMU_KSEG__seg_d__page 0
+#define R_MMU_KSEG__seg_c__BITNR 12
+#define R_MMU_KSEG__seg_c__WIDTH 1
+#define R_MMU_KSEG__seg_c__seg 1
+#define R_MMU_KSEG__seg_c__page 0
+#define R_MMU_KSEG__seg_b__BITNR 11
+#define R_MMU_KSEG__seg_b__WIDTH 1
+#define R_MMU_KSEG__seg_b__seg 1
+#define R_MMU_KSEG__seg_b__page 0
+#define R_MMU_KSEG__seg_a__BITNR 10
+#define R_MMU_KSEG__seg_a__WIDTH 1
+#define R_MMU_KSEG__seg_a__seg 1
+#define R_MMU_KSEG__seg_a__page 0
+#define R_MMU_KSEG__seg_9__BITNR 9
+#define R_MMU_KSEG__seg_9__WIDTH 1
+#define R_MMU_KSEG__seg_9__seg 1
+#define R_MMU_KSEG__seg_9__page 0
+#define R_MMU_KSEG__seg_8__BITNR 8
+#define R_MMU_KSEG__seg_8__WIDTH 1
+#define R_MMU_KSEG__seg_8__seg 1
+#define R_MMU_KSEG__seg_8__page 0
+#define R_MMU_KSEG__seg_7__BITNR 7
+#define R_MMU_KSEG__seg_7__WIDTH 1
+#define R_MMU_KSEG__seg_7__seg 1
+#define R_MMU_KSEG__seg_7__page 0
+#define R_MMU_KSEG__seg_6__BITNR 6
+#define R_MMU_KSEG__seg_6__WIDTH 1
+#define R_MMU_KSEG__seg_6__seg 1
+#define R_MMU_KSEG__seg_6__page 0
+#define R_MMU_KSEG__seg_5__BITNR 5
+#define R_MMU_KSEG__seg_5__WIDTH 1
+#define R_MMU_KSEG__seg_5__seg 1
+#define R_MMU_KSEG__seg_5__page 0
+#define R_MMU_KSEG__seg_4__BITNR 4
+#define R_MMU_KSEG__seg_4__WIDTH 1
+#define R_MMU_KSEG__seg_4__seg 1
+#define R_MMU_KSEG__seg_4__page 0
+#define R_MMU_KSEG__seg_3__BITNR 3
+#define R_MMU_KSEG__seg_3__WIDTH 1
+#define R_MMU_KSEG__seg_3__seg 1
+#define R_MMU_KSEG__seg_3__page 0
+#define R_MMU_KSEG__seg_2__BITNR 2
+#define R_MMU_KSEG__seg_2__WIDTH 1
+#define R_MMU_KSEG__seg_2__seg 1
+#define R_MMU_KSEG__seg_2__page 0
+#define R_MMU_KSEG__seg_1__BITNR 1
+#define R_MMU_KSEG__seg_1__WIDTH 1
+#define R_MMU_KSEG__seg_1__seg 1
+#define R_MMU_KSEG__seg_1__page 0
+#define R_MMU_KSEG__seg_0__BITNR 0
+#define R_MMU_KSEG__seg_0__WIDTH 1
+#define R_MMU_KSEG__seg_0__seg 1
+#define R_MMU_KSEG__seg_0__page 0
+
+#define R_MMU_CTRL (IO_TYPECAST_BYTE 0xb0000242)
+#define R_MMU_CTRL__inv_excp__BITNR 2
+#define R_MMU_CTRL__inv_excp__WIDTH 1
+#define R_MMU_CTRL__inv_excp__enable 1
+#define R_MMU_CTRL__inv_excp__disable 0
+#define R_MMU_CTRL__acc_excp__BITNR 1
+#define R_MMU_CTRL__acc_excp__WIDTH 1
+#define R_MMU_CTRL__acc_excp__enable 1
+#define R_MMU_CTRL__acc_excp__disable 0
+#define R_MMU_CTRL__we_excp__BITNR 0
+#define R_MMU_CTRL__we_excp__WIDTH 1
+#define R_MMU_CTRL__we_excp__enable 1
+#define R_MMU_CTRL__we_excp__disable 0
+
+#define R_MMU_ENABLE (IO_TYPECAST_BYTE 0xb0000243)
+#define R_MMU_ENABLE__mmu_enable__BITNR 7
+#define R_MMU_ENABLE__mmu_enable__WIDTH 1
+#define R_MMU_ENABLE__mmu_enable__enable 1
+#define R_MMU_ENABLE__mmu_enable__disable 0
+
+#define R_MMU_KBASE_LO (IO_TYPECAST_UDWORD 0xb0000244)
+#define R_MMU_KBASE_LO__base_7__BITNR 28
+#define R_MMU_KBASE_LO__base_7__WIDTH 4
+#define R_MMU_KBASE_LO__base_6__BITNR 24
+#define R_MMU_KBASE_LO__base_6__WIDTH 4
+#define R_MMU_KBASE_LO__base_5__BITNR 20
+#define R_MMU_KBASE_LO__base_5__WIDTH 4
+#define R_MMU_KBASE_LO__base_4__BITNR 16
+#define R_MMU_KBASE_LO__base_4__WIDTH 4
+#define R_MMU_KBASE_LO__base_3__BITNR 12
+#define R_MMU_KBASE_LO__base_3__WIDTH 4
+#define R_MMU_KBASE_LO__base_2__BITNR 8
+#define R_MMU_KBASE_LO__base_2__WIDTH 4
+#define R_MMU_KBASE_LO__base_1__BITNR 4
+#define R_MMU_KBASE_LO__base_1__WIDTH 4
+#define R_MMU_KBASE_LO__base_0__BITNR 0
+#define R_MMU_KBASE_LO__base_0__WIDTH 4
+
+#define R_MMU_KBASE_HI (IO_TYPECAST_UDWORD 0xb0000248)
+#define R_MMU_KBASE_HI__base_f__BITNR 28
+#define R_MMU_KBASE_HI__base_f__WIDTH 4
+#define R_MMU_KBASE_HI__base_e__BITNR 24
+#define R_MMU_KBASE_HI__base_e__WIDTH 4
+#define R_MMU_KBASE_HI__base_d__BITNR 20
+#define R_MMU_KBASE_HI__base_d__WIDTH 4
+#define R_MMU_KBASE_HI__base_c__BITNR 16
+#define R_MMU_KBASE_HI__base_c__WIDTH 4
+#define R_MMU_KBASE_HI__base_b__BITNR 12
+#define R_MMU_KBASE_HI__base_b__WIDTH 4
+#define R_MMU_KBASE_HI__base_a__BITNR 8
+#define R_MMU_KBASE_HI__base_a__WIDTH 4
+#define R_MMU_KBASE_HI__base_9__BITNR 4
+#define R_MMU_KBASE_HI__base_9__WIDTH 4
+#define R_MMU_KBASE_HI__base_8__BITNR 0
+#define R_MMU_KBASE_HI__base_8__WIDTH 4
+
+#define R_MMU_CONTEXT (IO_TYPECAST_BYTE 0xb000024c)
+#define R_MMU_CONTEXT__page_id__BITNR 0
+#define R_MMU_CONTEXT__page_id__WIDTH 6
+
+#define R_MMU_CAUSE (IO_TYPECAST_RO_UDWORD 0xb0000250)
+#define R_MMU_CAUSE__vpn__BITNR 13
+#define R_MMU_CAUSE__vpn__WIDTH 19
+#define R_MMU_CAUSE__miss_excp__BITNR 12
+#define R_MMU_CAUSE__miss_excp__WIDTH 1
+#define R_MMU_CAUSE__miss_excp__yes 1
+#define R_MMU_CAUSE__miss_excp__no 0
+#define R_MMU_CAUSE__inv_excp__BITNR 11
+#define R_MMU_CAUSE__inv_excp__WIDTH 1
+#define R_MMU_CAUSE__inv_excp__yes 1
+#define R_MMU_CAUSE__inv_excp__no 0
+#define R_MMU_CAUSE__acc_excp__BITNR 10
+#define R_MMU_CAUSE__acc_excp__WIDTH 1
+#define R_MMU_CAUSE__acc_excp__yes 1
+#define R_MMU_CAUSE__acc_excp__no 0
+#define R_MMU_CAUSE__we_excp__BITNR 9
+#define R_MMU_CAUSE__we_excp__WIDTH 1
+#define R_MMU_CAUSE__we_excp__yes 1
+#define R_MMU_CAUSE__we_excp__no 0
+#define R_MMU_CAUSE__wr_rd__BITNR 8
+#define R_MMU_CAUSE__wr_rd__WIDTH 1
+#define R_MMU_CAUSE__wr_rd__write 1
+#define R_MMU_CAUSE__wr_rd__read 0
+#define R_MMU_CAUSE__page_id__BITNR 0
+#define R_MMU_CAUSE__page_id__WIDTH 6
+
+#define R_TLB_SELECT (IO_TYPECAST_BYTE 0xb0000254)
+#define R_TLB_SELECT__index__BITNR 0
+#define R_TLB_SELECT__index__WIDTH 6
+
+#define R_TLB_LO (IO_TYPECAST_UDWORD 0xb0000258)
+#define R_TLB_LO__pfn__BITNR 13
+#define R_TLB_LO__pfn__WIDTH 19
+#define R_TLB_LO__global__BITNR 3
+#define R_TLB_LO__global__WIDTH 1
+#define R_TLB_LO__global__yes 1
+#define R_TLB_LO__global__no 0
+#define R_TLB_LO__valid__BITNR 2
+#define R_TLB_LO__valid__WIDTH 1
+#define R_TLB_LO__valid__yes 1
+#define R_TLB_LO__valid__no 0
+#define R_TLB_LO__kernel__BITNR 1
+#define R_TLB_LO__kernel__WIDTH 1
+#define R_TLB_LO__kernel__yes 1
+#define R_TLB_LO__kernel__no 0
+#define R_TLB_LO__we__BITNR 0
+#define R_TLB_LO__we__WIDTH 1
+#define R_TLB_LO__we__yes 1
+#define R_TLB_LO__we__no 0
+
+#define R_TLB_HI (IO_TYPECAST_UDWORD 0xb000025c)
+#define R_TLB_HI__vpn__BITNR 13
+#define R_TLB_HI__vpn__WIDTH 19
+#define R_TLB_HI__page_id__BITNR 0
+#define R_TLB_HI__page_id__WIDTH 6
+
+/*
+!* Syncrounous serial port registers
+!*/
+
+#define R_SYNC_SERIAL1_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000006c)
+#define R_SYNC_SERIAL1_REC_DATA__data_in__BITNR 0
+#define R_SYNC_SERIAL1_REC_DATA__data_in__WIDTH 32
+
+#define R_SYNC_SERIAL1_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000006c)
+#define R_SYNC_SERIAL1_REC_WORD__data_in__BITNR 0
+#define R_SYNC_SERIAL1_REC_WORD__data_in__WIDTH 16
+
+#define R_SYNC_SERIAL1_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000006c)
+#define R_SYNC_SERIAL1_REC_BYTE__data_in__BITNR 0
+#define R_SYNC_SERIAL1_REC_BYTE__data_in__WIDTH 8
+
+#define R_SYNC_SERIAL1_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000068)
+#define R_SYNC_SERIAL1_STATUS__rec_status__BITNR 15
+#define R_SYNC_SERIAL1_STATUS__rec_status__WIDTH 1
+#define R_SYNC_SERIAL1_STATUS__rec_status__running 0
+#define R_SYNC_SERIAL1_STATUS__rec_status__idle 1
+#define R_SYNC_SERIAL1_STATUS__tr_empty__BITNR 14
+#define R_SYNC_SERIAL1_STATUS__tr_empty__WIDTH 1
+#define R_SYNC_SERIAL1_STATUS__tr_empty__empty 1
+#define R_SYNC_SERIAL1_STATUS__tr_empty__not_empty 0
+#define R_SYNC_SERIAL1_STATUS__tr_ready__BITNR 13
+#define R_SYNC_SERIAL1_STATUS__tr_ready__WIDTH 1
+#define R_SYNC_SERIAL1_STATUS__tr_ready__full 0
+#define R_SYNC_SERIAL1_STATUS__tr_ready__ready 1
+#define R_SYNC_SERIAL1_STATUS__pin_1__BITNR 12
+#define R_SYNC_SERIAL1_STATUS__pin_1__WIDTH 1
+#define R_SYNC_SERIAL1_STATUS__pin_1__low 0
+#define R_SYNC_SERIAL1_STATUS__pin_1__high 1
+#define R_SYNC_SERIAL1_STATUS__pin_0__BITNR 11
+#define R_SYNC_SERIAL1_STATUS__pin_0__WIDTH 1
+#define R_SYNC_SERIAL1_STATUS__pin_0__low 0
+#define R_SYNC_SERIAL1_STATUS__pin_0__high 1
+#define R_SYNC_SERIAL1_STATUS__underflow__BITNR 10
+#define R_SYNC_SERIAL1_STATUS__underflow__WIDTH 1
+#define R_SYNC_SERIAL1_STATUS__underflow__no 0
+#define R_SYNC_SERIAL1_STATUS__underflow__yes 1
+#define R_SYNC_SERIAL1_STATUS__overrun__BITNR 9
+#define R_SYNC_SERIAL1_STATUS__overrun__WIDTH 1
+#define R_SYNC_SERIAL1_STATUS__overrun__no 0
+#define R_SYNC_SERIAL1_STATUS__overrun__yes 1
+#define R_SYNC_SERIAL1_STATUS__data_avail__BITNR 8
+#define R_SYNC_SERIAL1_STATUS__data_avail__WIDTH 1
+#define R_SYNC_SERIAL1_STATUS__data_avail__no 0
+#define R_SYNC_SERIAL1_STATUS__data_avail__yes 1
+#define R_SYNC_SERIAL1_STATUS__data__BITNR 0
+#define R_SYNC_SERIAL1_STATUS__data__WIDTH 8
+
+#define R_SYNC_SERIAL1_TR_DATA (IO_TYPECAST_UDWORD 0xb000006c)
+#define R_SYNC_SERIAL1_TR_DATA__data_out__BITNR 0
+#define R_SYNC_SERIAL1_TR_DATA__data_out__WIDTH 32
+
+#define R_SYNC_SERIAL1_TR_WORD (IO_TYPECAST_UWORD 0xb000006c)
+#define R_SYNC_SERIAL1_TR_WORD__data_out__BITNR 0
+#define R_SYNC_SERIAL1_TR_WORD__data_out__WIDTH 16
+
+#define R_SYNC_SERIAL1_TR_BYTE (IO_TYPECAST_BYTE 0xb000006c)
+#define R_SYNC_SERIAL1_TR_BYTE__data_out__BITNR 0
+#define R_SYNC_SERIAL1_TR_BYTE__data_out__WIDTH 8
+
+#define R_SYNC_SERIAL1_CTRL (IO_TYPECAST_UDWORD 0xb0000068)
+#define R_SYNC_SERIAL1_CTRL__tr_baud__BITNR 28
+#define R_SYNC_SERIAL1_CTRL__tr_baud__WIDTH 4
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c150Hz 0
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c300Hz 1
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c600Hz 2
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c1200Hz 3
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c2400Hz 4
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c4800Hz 5
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c9600Hz 6
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c19k2Hz 7
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c28k8Hz 8
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c57k6Hz 9
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c115k2Hz 10
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c230k4Hz 11
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c460k8Hz 12
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c921k6Hz 13
+#define R_SYNC_SERIAL1_CTRL__tr_baud__c3125kHz 14
+#define R_SYNC_SERIAL1_CTRL__tr_baud__reserved 15
+#define R_SYNC_SERIAL1_CTRL__dma_enable__BITNR 27
+#define R_SYNC_SERIAL1_CTRL__dma_enable__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__dma_enable__on 1
+#define R_SYNC_SERIAL1_CTRL__dma_enable__off 0
+#define R_SYNC_SERIAL1_CTRL__mode__BITNR 24
+#define R_SYNC_SERIAL1_CTRL__mode__WIDTH 3
+#define R_SYNC_SERIAL1_CTRL__mode__master_output 0
+#define R_SYNC_SERIAL1_CTRL__mode__slave_output 1
+#define R_SYNC_SERIAL1_CTRL__mode__master_input 2
+#define R_SYNC_SERIAL1_CTRL__mode__slave_input 3
+#define R_SYNC_SERIAL1_CTRL__mode__master_bidir 4
+#define R_SYNC_SERIAL1_CTRL__mode__slave_bidir 5
+#define R_SYNC_SERIAL1_CTRL__error__BITNR 23
+#define R_SYNC_SERIAL1_CTRL__error__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__error__normal 0
+#define R_SYNC_SERIAL1_CTRL__error__ignore 1
+#define R_SYNC_SERIAL1_CTRL__rec_enable__BITNR 22
+#define R_SYNC_SERIAL1_CTRL__rec_enable__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__rec_enable__disable 0
+#define R_SYNC_SERIAL1_CTRL__rec_enable__enable 1
+#define R_SYNC_SERIAL1_CTRL__f_synctype__BITNR 21
+#define R_SYNC_SERIAL1_CTRL__f_synctype__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__f_synctype__normal 0
+#define R_SYNC_SERIAL1_CTRL__f_synctype__early 1
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__BITNR 19
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__WIDTH 2
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__bit 0
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__word 1
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__extended 2
+#define R_SYNC_SERIAL1_CTRL__f_syncsize__reserved 3
+#define R_SYNC_SERIAL1_CTRL__f_sync__BITNR 18
+#define R_SYNC_SERIAL1_CTRL__f_sync__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__f_sync__on 0
+#define R_SYNC_SERIAL1_CTRL__f_sync__off 1
+#define R_SYNC_SERIAL1_CTRL__clk_mode__BITNR 17
+#define R_SYNC_SERIAL1_CTRL__clk_mode__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__clk_mode__normal 0
+#define R_SYNC_SERIAL1_CTRL__clk_mode__gated 1
+#define R_SYNC_SERIAL1_CTRL__clk_halt__BITNR 16
+#define R_SYNC_SERIAL1_CTRL__clk_halt__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__clk_halt__running 0
+#define R_SYNC_SERIAL1_CTRL__clk_halt__stopped 1
+#define R_SYNC_SERIAL1_CTRL__bitorder__BITNR 15
+#define R_SYNC_SERIAL1_CTRL__bitorder__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__bitorder__lsb 0
+#define R_SYNC_SERIAL1_CTRL__bitorder__msb 1
+#define R_SYNC_SERIAL1_CTRL__tr_enable__BITNR 14
+#define R_SYNC_SERIAL1_CTRL__tr_enable__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__tr_enable__disable 0
+#define R_SYNC_SERIAL1_CTRL__tr_enable__enable 1
+#define R_SYNC_SERIAL1_CTRL__wordsize__BITNR 11
+#define R_SYNC_SERIAL1_CTRL__wordsize__WIDTH 3
+#define R_SYNC_SERIAL1_CTRL__wordsize__size8bit 0
+#define R_SYNC_SERIAL1_CTRL__wordsize__size12bit 1
+#define R_SYNC_SERIAL1_CTRL__wordsize__size16bit 2
+#define R_SYNC_SERIAL1_CTRL__wordsize__size24bit 3
+#define R_SYNC_SERIAL1_CTRL__wordsize__size32bit 4
+#define R_SYNC_SERIAL1_CTRL__buf_empty__BITNR 10
+#define R_SYNC_SERIAL1_CTRL__buf_empty__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_8 0
+#define R_SYNC_SERIAL1_CTRL__buf_empty__lmt_0 1
+#define R_SYNC_SERIAL1_CTRL__buf_full__BITNR 9
+#define R_SYNC_SERIAL1_CTRL__buf_full__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_32 0
+#define R_SYNC_SERIAL1_CTRL__buf_full__lmt_8 1
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__BITNR 8
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__disabled 0
+#define R_SYNC_SERIAL1_CTRL__flow_ctrl__enabled 1
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__BITNR 6
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__pos 0
+#define R_SYNC_SERIAL1_CTRL__clk_polarity__neg 1
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__BITNR 5
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__normal 0
+#define R_SYNC_SERIAL1_CTRL__frame_polarity__inverted 1
+#define R_SYNC_SERIAL1_CTRL__status_polarity__BITNR 4
+#define R_SYNC_SERIAL1_CTRL__status_polarity__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__status_polarity__normal 0
+#define R_SYNC_SERIAL1_CTRL__status_polarity__inverted 1
+#define R_SYNC_SERIAL1_CTRL__clk_driver__BITNR 3
+#define R_SYNC_SERIAL1_CTRL__clk_driver__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__clk_driver__normal 0
+#define R_SYNC_SERIAL1_CTRL__clk_driver__inverted 1
+#define R_SYNC_SERIAL1_CTRL__frame_driver__BITNR 2
+#define R_SYNC_SERIAL1_CTRL__frame_driver__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__frame_driver__normal 0
+#define R_SYNC_SERIAL1_CTRL__frame_driver__inverted 1
+#define R_SYNC_SERIAL1_CTRL__status_driver__BITNR 1
+#define R_SYNC_SERIAL1_CTRL__status_driver__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__status_driver__normal 0
+#define R_SYNC_SERIAL1_CTRL__status_driver__inverted 1
+#define R_SYNC_SERIAL1_CTRL__def_out0__BITNR 0
+#define R_SYNC_SERIAL1_CTRL__def_out0__WIDTH 1
+#define R_SYNC_SERIAL1_CTRL__def_out0__high 1
+#define R_SYNC_SERIAL1_CTRL__def_out0__low 0
+
+#define R_SYNC_SERIAL3_REC_DATA (IO_TYPECAST_RO_UDWORD 0xb000007c)
+#define R_SYNC_SERIAL3_REC_DATA__data_in__BITNR 0
+#define R_SYNC_SERIAL3_REC_DATA__data_in__WIDTH 32
+
+#define R_SYNC_SERIAL3_REC_WORD (IO_TYPECAST_RO_UWORD 0xb000007c)
+#define R_SYNC_SERIAL3_REC_WORD__data_in__BITNR 0
+#define R_SYNC_SERIAL3_REC_WORD__data_in__WIDTH 16
+
+#define R_SYNC_SERIAL3_REC_BYTE (IO_TYPECAST_RO_BYTE 0xb000007c)
+#define R_SYNC_SERIAL3_REC_BYTE__data_in__BITNR 0
+#define R_SYNC_SERIAL3_REC_BYTE__data_in__WIDTH 8
+
+#define R_SYNC_SERIAL3_STATUS (IO_TYPECAST_RO_UDWORD 0xb0000078)
+#define R_SYNC_SERIAL3_STATUS__rec_status__BITNR 15
+#define R_SYNC_SERIAL3_STATUS__rec_status__WIDTH 1
+#define R_SYNC_SERIAL3_STATUS__rec_status__running 0
+#define R_SYNC_SERIAL3_STATUS__rec_status__idle 1
+#define R_SYNC_SERIAL3_STATUS__tr_empty__BITNR 14
+#define R_SYNC_SERIAL3_STATUS__tr_empty__WIDTH 1
+#define R_SYNC_SERIAL3_STATUS__tr_empty__empty 1
+#define R_SYNC_SERIAL3_STATUS__tr_empty__not_empty 0
+#define R_SYNC_SERIAL3_STATUS__tr_ready__BITNR 13
+#define R_SYNC_SERIAL3_STATUS__tr_ready__WIDTH 1
+#define R_SYNC_SERIAL3_STATUS__tr_ready__full 0
+#define R_SYNC_SERIAL3_STATUS__tr_ready__ready 1
+#define R_SYNC_SERIAL3_STATUS__pin_1__BITNR 12
+#define R_SYNC_SERIAL3_STATUS__pin_1__WIDTH 1
+#define R_SYNC_SERIAL3_STATUS__pin_1__low 0
+#define R_SYNC_SERIAL3_STATUS__pin_1__high 1
+#define R_SYNC_SERIAL3_STATUS__pin_0__BITNR 11
+#define R_SYNC_SERIAL3_STATUS__pin_0__WIDTH 1
+#define R_SYNC_SERIAL3_STATUS__pin_0__low 0
+#define R_SYNC_SERIAL3_STATUS__pin_0__high 1
+#define R_SYNC_SERIAL3_STATUS__underflow__BITNR 10
+#define R_SYNC_SERIAL3_STATUS__underflow__WIDTH 1
+#define R_SYNC_SERIAL3_STATUS__underflow__no 0
+#define R_SYNC_SERIAL3_STATUS__underflow__yes 1
+#define R_SYNC_SERIAL3_STATUS__overrun__BITNR 9
+#define R_SYNC_SERIAL3_STATUS__overrun__WIDTH 1
+#define R_SYNC_SERIAL3_STATUS__overrun__no 0
+#define R_SYNC_SERIAL3_STATUS__overrun__yes 1
+#define R_SYNC_SERIAL3_STATUS__data_avail__BITNR 8
+#define R_SYNC_SERIAL3_STATUS__data_avail__WIDTH 1
+#define R_SYNC_SERIAL3_STATUS__data_avail__no 0
+#define R_SYNC_SERIAL3_STATUS__data_avail__yes 1
+#define R_SYNC_SERIAL3_STATUS__data__BITNR 0
+#define R_SYNC_SERIAL3_STATUS__data__WIDTH 8
+
+#define R_SYNC_SERIAL3_TR_DATA (IO_TYPECAST_UDWORD 0xb000007c)
+#define R_SYNC_SERIAL3_TR_DATA__data_out__BITNR 0
+#define R_SYNC_SERIAL3_TR_DATA__data_out__WIDTH 32
+
+#define R_SYNC_SERIAL3_TR_WORD (IO_TYPECAST_UWORD 0xb000007c)
+#define R_SYNC_SERIAL3_TR_WORD__data_out__BITNR 0
+#define R_SYNC_SERIAL3_TR_WORD__data_out__WIDTH 16
+
+#define R_SYNC_SERIAL3_TR_BYTE (IO_TYPECAST_BYTE 0xb000007c)
+#define R_SYNC_SERIAL3_TR_BYTE__data_out__BITNR 0
+#define R_SYNC_SERIAL3_TR_BYTE__data_out__WIDTH 8
+
+#define R_SYNC_SERIAL3_CTRL (IO_TYPECAST_UDWORD 0xb0000078)
+#define R_SYNC_SERIAL3_CTRL__tr_baud__BITNR 28
+#define R_SYNC_SERIAL3_CTRL__tr_baud__WIDTH 4
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c150Hz 0
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c300Hz 1
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c600Hz 2
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c1200Hz 3
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c2400Hz 4
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c4800Hz 5
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c9600Hz 6
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c19k2Hz 7
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c28k8Hz 8
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c57k6Hz 9
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c115k2Hz 10
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c230k4Hz 11
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c460k8Hz 12
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c921k6Hz 13
+#define R_SYNC_SERIAL3_CTRL__tr_baud__c3125kHz 14
+#define R_SYNC_SERIAL3_CTRL__tr_baud__reserved 15
+#define R_SYNC_SERIAL3_CTRL__dma_enable__BITNR 27
+#define R_SYNC_SERIAL3_CTRL__dma_enable__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__dma_enable__on 1
+#define R_SYNC_SERIAL3_CTRL__dma_enable__off 0
+#define R_SYNC_SERIAL3_CTRL__mode__BITNR 24
+#define R_SYNC_SERIAL3_CTRL__mode__WIDTH 3
+#define R_SYNC_SERIAL3_CTRL__mode__master_output 0
+#define R_SYNC_SERIAL3_CTRL__mode__slave_output 1
+#define R_SYNC_SERIAL3_CTRL__mode__master_input 2
+#define R_SYNC_SERIAL3_CTRL__mode__slave_input 3
+#define R_SYNC_SERIAL3_CTRL__mode__master_bidir 4
+#define R_SYNC_SERIAL3_CTRL__mode__slave_bidir 5
+#define R_SYNC_SERIAL3_CTRL__error__BITNR 23
+#define R_SYNC_SERIAL3_CTRL__error__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__error__normal 0
+#define R_SYNC_SERIAL3_CTRL__error__ignore 1
+#define R_SYNC_SERIAL3_CTRL__rec_enable__BITNR 22
+#define R_SYNC_SERIAL3_CTRL__rec_enable__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__rec_enable__disable 0
+#define R_SYNC_SERIAL3_CTRL__rec_enable__enable 1
+#define R_SYNC_SERIAL3_CTRL__f_synctype__BITNR 21
+#define R_SYNC_SERIAL3_CTRL__f_synctype__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__f_synctype__normal 0
+#define R_SYNC_SERIAL3_CTRL__f_synctype__early 1
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__BITNR 19
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__WIDTH 2
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__bit 0
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__word 1
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__extended 2
+#define R_SYNC_SERIAL3_CTRL__f_syncsize__reserved 3
+#define R_SYNC_SERIAL3_CTRL__f_sync__BITNR 18
+#define R_SYNC_SERIAL3_CTRL__f_sync__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__f_sync__on 0
+#define R_SYNC_SERIAL3_CTRL__f_sync__off 1
+#define R_SYNC_SERIAL3_CTRL__clk_mode__BITNR 17
+#define R_SYNC_SERIAL3_CTRL__clk_mode__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__clk_mode__normal 0
+#define R_SYNC_SERIAL3_CTRL__clk_mode__gated 1
+#define R_SYNC_SERIAL3_CTRL__clk_halt__BITNR 16
+#define R_SYNC_SERIAL3_CTRL__clk_halt__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__clk_halt__running 0
+#define R_SYNC_SERIAL3_CTRL__clk_halt__stopped 1
+#define R_SYNC_SERIAL3_CTRL__bitorder__BITNR 15
+#define R_SYNC_SERIAL3_CTRL__bitorder__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__bitorder__lsb 0
+#define R_SYNC_SERIAL3_CTRL__bitorder__msb 1
+#define R_SYNC_SERIAL3_CTRL__tr_enable__BITNR 14
+#define R_SYNC_SERIAL3_CTRL__tr_enable__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__tr_enable__disable 0
+#define R_SYNC_SERIAL3_CTRL__tr_enable__enable 1
+#define R_SYNC_SERIAL3_CTRL__wordsize__BITNR 11
+#define R_SYNC_SERIAL3_CTRL__wordsize__WIDTH 3
+#define R_SYNC_SERIAL3_CTRL__wordsize__size8bit 0
+#define R_SYNC_SERIAL3_CTRL__wordsize__size12bit 1
+#define R_SYNC_SERIAL3_CTRL__wordsize__size16bit 2
+#define R_SYNC_SERIAL3_CTRL__wordsize__size24bit 3
+#define R_SYNC_SERIAL3_CTRL__wordsize__size32bit 4
+#define R_SYNC_SERIAL3_CTRL__buf_empty__BITNR 10
+#define R_SYNC_SERIAL3_CTRL__buf_empty__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_8 0
+#define R_SYNC_SERIAL3_CTRL__buf_empty__lmt_0 1
+#define R_SYNC_SERIAL3_CTRL__buf_full__BITNR 9
+#define R_SYNC_SERIAL3_CTRL__buf_full__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_32 0
+#define R_SYNC_SERIAL3_CTRL__buf_full__lmt_8 1
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__BITNR 8
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__disabled 0
+#define R_SYNC_SERIAL3_CTRL__flow_ctrl__enabled 1
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__BITNR 6
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__pos 0
+#define R_SYNC_SERIAL3_CTRL__clk_polarity__neg 1
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__BITNR 5
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__normal 0
+#define R_SYNC_SERIAL3_CTRL__frame_polarity__inverted 1
+#define R_SYNC_SERIAL3_CTRL__status_polarity__BITNR 4
+#define R_SYNC_SERIAL3_CTRL__status_polarity__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__status_polarity__normal 0
+#define R_SYNC_SERIAL3_CTRL__status_polarity__inverted 1
+#define R_SYNC_SERIAL3_CTRL__clk_driver__BITNR 3
+#define R_SYNC_SERIAL3_CTRL__clk_driver__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__clk_driver__normal 0
+#define R_SYNC_SERIAL3_CTRL__clk_driver__inverted 1
+#define R_SYNC_SERIAL3_CTRL__frame_driver__BITNR 2
+#define R_SYNC_SERIAL3_CTRL__frame_driver__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__frame_driver__normal 0
+#define R_SYNC_SERIAL3_CTRL__frame_driver__inverted 1
+#define R_SYNC_SERIAL3_CTRL__status_driver__BITNR 1
+#define R_SYNC_SERIAL3_CTRL__status_driver__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__status_driver__normal 0
+#define R_SYNC_SERIAL3_CTRL__status_driver__inverted 1
+#define R_SYNC_SERIAL3_CTRL__def_out0__BITNR 0
+#define R_SYNC_SERIAL3_CTRL__def_out0__WIDTH 1
+#define R_SYNC_SERIAL3_CTRL__def_out0__high 1
+#define R_SYNC_SERIAL3_CTRL__def_out0__low 0
+
diff --git a/package/etrax-tools/src/e100boot/cbl/src/sv_addr_ag.h b/package/etrax-tools/src/e100boot/cbl/src/sv_addr_ag.h
new file mode 100644
index 000000000..140f73875
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/cbl/src/sv_addr_ag.h
@@ -0,0 +1,137 @@
+/*!**************************************************************************
+*!
+*! MACROS:
+*! IO_MASK(reg,field)
+*! IO_STATE(reg,field,state)
+*! IO_EXTRACT(reg,field,val)
+*! IO_STATE_VALUE(reg,field,state)
+*! IO_BITNR(reg,field)
+*! IO_WIDTH(reg,field)
+*! IO_FIELD(reg,field,val)
+*! IO_RD(reg)
+*! All moderegister addresses and fields of these.
+*!
+*!**************************************************************************/
+
+#ifndef __sv_addr_ag_h__
+#define __sv_addr_ag_h__
+
+
+#define __test_sv_addr__ 0
+
+/*------------------------------------------------------------
+!* General macros to manipulate moderegisters.
+!*-----------------------------------------------------------*/
+
+/* IO_MASK returns a mask for a specified bitfield in a register.
+ Note that this macro doesn't work when field width is 32 bits. */
+#define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_)
+#define IO_MASK_(reg_, field_) \
+ ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR )
+
+/* IO_STATE returns a constant corresponding to a one of the symbolic
+ states that the bitfield can have. (Shifted to correct position) */
+#define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state)
+#define IO_STATE_(reg_, field_, _state) \
+ ( reg_##_##field_##_state << reg_##_##field_##_BITNR )
+
+/* IO_EXTRACT returns the masked and shifted value corresponding to the
+ bitfield can have. */
+#define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val)
+#define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \
+ - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR )
+
+/* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic
+ states that the bitfield can have. (Not shifted) */
+#define IO_STATE_VALUE(reg, field, state) \
+ IO_STATE_VALUE_ (reg##_, field##_, _##state)
+#define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state )
+
+/* IO_FIELD shifts the val parameter to be aligned with the bitfield
+ specified. */
+#define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val)
+#define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR)
+
+/* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is
+ LSB and the returned bitnumber is LSB of the field. */
+#define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_)
+#define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR)
+
+/* IO_WIDTH returns the width, in bits, of a bitfield. */
+#define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_)
+#define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH)
+
+/*--- Obsolete. Kept for backw compatibility. ---*/
+/* Reads (or writes) a byte/uword/udword from the specified mode
+ register. */
+#define IO_RD(reg) (*(volatile udword*)(reg))
+#define IO_RD_B(reg) (*(volatile byte*)(reg))
+#define IO_RD_W(reg) (*(volatile uword*)(reg))
+#define IO_RD_D(reg) (*(volatile udword*)(reg))
+
+/*------------------------------------------------------------
+!* Start addresses of the different memory areas.
+!*-----------------------------------------------------------*/
+
+#define MEM_CSE0_START (0x00000000)
+#define MEM_CSE1_START (0x04000000)
+#define MEM_CSR0_START (0x08000000)
+#define MEM_CSR1_START (0x0c000000)
+#define MEM_CSP0_START (0x10000000)
+#define MEM_CSP1_START (0x14000000)
+#define MEM_CSP2_START (0x18000000)
+#define MEM_CSP3_START (0x1c000000)
+#define MEM_CSP4_START (0x20000000)
+#define MEM_CSP5_START (0x24000000)
+#define MEM_CSP6_START (0x28000000)
+#define MEM_CSP7_START (0x2c000000)
+#define MEM_DRAM_START (0x40000000)
+
+#define MEM_NON_CACHEABLE (0x80000000)
+
+/*------------------------------------------------------------
+!* Type casts used in mode register macros, making pointer
+!* dereferencing possible. Empty in assembler.
+!*-----------------------------------------------------------*/
+
+#ifndef __ASSEMBLER__
+# define IO_TYPECAST_UDWORD (volatile udword*)
+# define IO_TYPECAST_RO_UDWORD (const volatile udword*)
+# define IO_TYPECAST_UWORD (volatile uword*)
+# define IO_TYPECAST_RO_UWORD (const volatile uword*)
+# define IO_TYPECAST_BYTE (volatile byte*)
+# define IO_TYPECAST_RO_BYTE (const volatile byte*)
+#else
+# define IO_TYPECAST_UDWORD
+# define IO_TYPECAST_RO_UDWORD
+# define IO_TYPECAST_UWORD
+# define IO_TYPECAST_RO_UWORD
+# define IO_TYPECAST_BYTE
+# define IO_TYPECAST_RO_BYTE
+#endif
+
+/*------------------------------------------------------------*/
+
+#include "sv_addr.agh"
+
+#if __test_sv_addr__
+/* IO_MASK( R_BUS_CONFIG , CE ) */
+IO_MASK( R_WAITSTATES , SRAM_WS )
+IO_MASK( R_TEST , W32 )
+
+IO_STATE( R_BUS_CONFIG, CE, DISABLE )
+IO_STATE( R_BUS_CONFIG, CE, ENABLE )
+
+IO_STATE( R_DRAM_TIMING, REF, IVAL2 )
+
+IO_MASK( R_DRAM_TIMING, REF )
+
+IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT )
+
+IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S )
+ == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED )
+#endif
+
+
+#endif /* ifndef __sv_addr_ag_h__ */
+
diff --git a/package/etrax-tools/src/e100boot/doc/Makefile b/package/etrax-tools/src/e100boot/doc/Makefile
new file mode 100644
index 000000000..df6076b8e
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/doc/Makefile
@@ -0,0 +1,17 @@
+OBJS=e100boot.1 e100boot.html
+
+all: $(OBJS)
+
+%.1: %.pod
+ pod2man $< > $@
+
+%.html: %.pod
+ pod2html $< > $@
+ @rm -f pod2htmd.x~~ pod2htmi.x~~
+
+clean:
+ rm -f *cache *~
+
+# The 'clean' doesn't remove the generated documentation as we want
+# them in the distribution.
+
diff --git a/package/etrax-tools/src/e100boot/doc/e100boot.1 b/package/etrax-tools/src/e100boot/doc/e100boot.1
new file mode 100644
index 000000000..116b9e577
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/doc/e100boot.1
@@ -0,0 +1,401 @@
+.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.32
+.\"
+.\" Standard preamble:
+.\" ========================================================================
+.de Sh \" Subsection heading
+.br
+.if t .Sp
+.ne 5
+.PP
+\fB\\$1\fR
+.PP
+..
+.de Sp \" Vertical space (when we can't use .PP)
+.if t .sp .5v
+.if n .sp
+..
+.de Vb \" Begin verbatim text
+.ft CW
+.nf
+.ne \\$1
+..
+.de Ve \" End verbatim text
+.ft R
+.fi
+..
+.\" Set up some character translations and predefined strings. \*(-- will
+.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left
+.\" double quote, and \*(R" will give a right double quote. \*(C+ will
+.\" give a nicer C++. Capital omega is used to do unbreakable dashes and
+.\" therefore won't be available. \*(C` and \*(C' expand to `' in nroff,
+.\" nothing in troff, for use with C<>.
+.tr \(*W-
+.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p'
+.ie n \{\
+. ds -- \(*W-
+. ds PI pi
+. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch
+. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch
+. ds L" ""
+. ds R" ""
+. ds C` ""
+. ds C' ""
+'br\}
+.el\{\
+. ds -- \|\(em\|
+. ds PI \(*p
+. ds L" ``
+. ds R" ''
+'br\}
+.\"
+.\" If the F register is turned on, we'll generate index entries on stderr for
+.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index
+.\" entries marked with X<> in POD. Of course, you'll have to process the
+.\" output yourself in some meaningful fashion.
+.if \nF \{\
+. de IX
+. tm Index:\\$1\t\\n%\t"\\$2"
+..
+. nr % 0
+. rr F
+.\}
+.\"
+.\" For nroff, turn off justification. Always turn off hyphenation; it makes
+.\" way too many mistakes in technical documents.
+.hy 0
+.if n .na
+.\"
+.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2).
+.\" Fear. Run. Save yourself. No user-serviceable parts.
+. \" fudge factors for nroff and troff
+.if n \{\
+. ds #H 0
+. ds #V .8m
+. ds #F .3m
+. ds #[ \f1
+. ds #] \fP
+.\}
+.if t \{\
+. ds #H ((1u-(\\\\n(.fu%2u))*.13m)
+. ds #V .6m
+. ds #F 0
+. ds #[ \&
+. ds #] \&
+.\}
+. \" simple accents for nroff and troff
+.if n \{\
+. ds ' \&
+. ds ` \&
+. ds ^ \&
+. ds , \&
+. ds ~ ~
+. ds /
+.\}
+.if t \{\
+. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u"
+. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u'
+. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u'
+. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u'
+. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u'
+. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u'
+.\}
+. \" troff and (daisy-wheel) nroff accents
+.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V'
+.ds 8 \h'\*(#H'\(*b\h'-\*(#H'
+.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#]
+.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H'
+.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u'
+.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#]
+.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#]
+.ds ae a\h'-(\w'a'u*4/10)'e
+.ds Ae A\h'-(\w'A'u*4/10)'E
+. \" corrections for vroff
+.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u'
+.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u'
+. \" for low resolution devices (crt and lpr)
+.if \n(.H>23 .if \n(.V>19 \
+\{\
+. ds : e
+. ds 8 ss
+. ds o a
+. ds d- d\h'-1'\(ga
+. ds D- D\h'-1'\(hy
+. ds th \o'bp'
+. ds Th \o'LP'
+. ds ae ae
+. ds Ae AE
+.\}
+.rm #[ #] #H #V #F C
+.\" ========================================================================
+.\"
+.IX Title "E100BOOT 1"
+.TH E100BOOT 1 "2003-12-16" "perl v5.8.8" "User Contributed Perl Documentation"
+.SH "NAME"
+e100boot \- Network and serial port bootloader for the ETRAX100 CPU.
+.SH "SYNOPSIS"
+.IX Header "SYNOPSIS"
+\&\fBe100boot\fR [\fB\-\-device\fR \fIdevicename\fR]
+[\fB\-\-file\fR \fIfilename\fR|\- \fIaddr\fR [\fIsize\fR]]
+[\fB\-\-flash\fR \fIram-source\fR \fIflash-offset\fR \fIsize\fR] [\fB\-\-pause\fR \fIiter\fR]
+[\fB\-\-memtest\fR \fIaddr\fR \fIaddr\fR] [\fB\-\-memclear\fR \fIaddr\fR \fIaddr\fR]
+[\fB\-\-memdump\fR \fIaddr\fR \fIaddr\fR] [\fB\-\-setreg\fR \fIaddr\fR|\fIregname\fR \fIval\fR]
+[\fB\-\-getreg\fR \fIaddr\fR|\fIregname\fR] [\fB\-\-verify\fR \fIaddr\fR \fIval\fR]
+[\fB\-\-label\fR \fIlabel\fR] [\fB\-\-loop\fR \fIaddr\fR \fIlabel\fR] [\fB\-\-5400\fR] [\fB\-\-5600\fR]
+[\fB\-\-testcard\fR] [\fB\-\-devboard\fR] [\fB\-\-testcardlx\fR] [\fB\-\-network\fR] [\fB\-\-serial\fR]
+[\fB\-\-baudrate\fR \fIbaudrate\fR] [\fB\-\-bootfile\fR \fIfile\fR] [\fB\-\-jump\fR \fIaddr\fR]
+[\fB\-\-tofiles\fR] [\fB\-\-cmdsonly\fR] [\fB\-\-images\fR] [\fB\-\-noleds\fR] [\fB\-\-help\fR]
+.SH "DESCRIPTION"
+.IX Header "DESCRIPTION"
+This boot loader facilitates loading of files over the network or a
+serial port to an \s-1ETRAX100\s0. It can also be used for fairly extensive
+hardware debugging as you can read and write to any memory addresses,
+including the \s-1ETRAX100\s0 registers. You can also perform memory checks
+and dumps and copy data to flash memories.
+.PP
+The first packet (or the first 784 bytes in the case of serial boot)
+sent to Etrax100 is loaded into the cache. The code in this packet is
+executed and loads the rest of the boot loader into the cache. The
+cache is the only thing we can be sure of exists on all \s-1ETRAX100\s0
+products, so the boot loader is limited to the size of the cache,
+8KB. If further boot loading code is needed you have to set up
+external memory and load another boot loader into it, but this is
+rarely needed.
+.PP
+Two programs are involved in this boot loading, one is the program on
+your workstation that sends the packets to \s-1ETRAX100\s0, this is called
+the server boot loader or \s-1SBL\s0. The other program is the one in
+\&\s-1ETRAX100\s0 that receives packets from the \s-1SBL\s0 and acts upon the data
+therein, this is called the client boot loader or \s-1CBL\s0.
+.PP
+We don't want to edit and recompile the \s-1CBL\s0 each time we want to load
+level two to different parts of memory, like we do on different
+products. We also want to change things like the setup of external
+memory before we load data into it. To make the boot loading as
+flexible as possible and separate the \s-1CBL\s0 from level two we send a
+configuration packet to it. After this packet we load other files, if
+we want to.
+.PP
+The configuration packet can contain information to the \s-1CBL\s0 which lets
+you: initialize external memory, read and write to all \s-1ETRAX100\s0
+registers, read and write to any part of memory, load as many other
+files as you like to any part of memory you like, etc. The
+configuration packet is generated on the fly by the \s-1SBL\s0.
+.PP
+Since the \s-1CBL\s0 is unaware of which product it will be loaded on, it
+doesn't do product specific initialization like setting up the
+memory. This must be done with the configuration packet.
+.Sh "Debugging printout"
+.IX Subsection "Debugging printout"
+When doing network boot the debugging printout from the \s-1CBL\s0 in \s-1ETRAX\s0
+is transmitted back over the network and printed by e100boot. When
+doing serial boot that interface will be used. So in either case you
+will not need any other software or hardware to receive the debugging
+printout.
+.Sh "Creating binaries"
+.IX Subsection "Creating binaries"
+The files containing code to be loaded on the \s-1ETRAX100\s0 must be
+stripped using the standard \s-1GCC\s0 binutils.
+.Sh "How it works, things you don't want to know."
+.IX Subsection "How it works, things you don't want to know."
+ack, timeout bla, bla... \s-1RTFS\s0.
+.Sh "Compilation and code"
+.IX Subsection "Compilation and code"
+Noteworthy is that two separate \s-1ETRAX100\s0 binaries are created, one for
+network boot and one for serial boot. They actually contain exactly
+the same code, but linked in different order. This is because the code
+to load the rest of the bootloader over a specific interface must be
+contained in the first data sent to the \s-1ETRAX100\s0 and it is too
+difficult to cram the code for both interfaces in the beginning of the
+same binary. Hence two files.
+.PP
+Other stuff you don't want to know is that the cache is mapped from
+0x380000f0 to 0x380020f0. Code starts at the first address followed by
+data up to the symbol \fIEbss\fR. At the other end is the buffer for boot
+commands (addresses defined by \fI\s-1IO_BUF_START\s0\fR and \fI\s-1IO_BUF_END\s0\fR below
+which the stack lies and hopefully the stack and \fIEbss\fR will never
+meet...
+.PP
+The serial data is loaded from 0x380000f0 to 0x380003ff before
+execution starts.
+.SH "OPTIONS"
+.IX Header "OPTIONS"
+The options are done in the order specified on the command line, so
+you probably want to do any memory setup before loading a file to the
+memory, and you probably do not want to perform a memory test after
+you have loaded a file to that memory.
+.PP
+All addresses and sizes must be in hex with optional '0x' prefix, or a
+\&\s-1ETRAX100\s0 register name. Since the \fB\-\-setreg\fR and \fB\-\-getreg\fR options
+only can be performed on dword aligned dwords only the registers that
+conform to this can be named.
+.PP
+Note also that all addresses must be in uncached memory (bit 31 set),
+as the bootloader lies in the cache. If you access any uncached
+address during boot, the bootloader will be destroyed without warning.
+.PP
+It is also possible to specify an address as \fI+address\fR, in which
+case it is considered to be relative to \fI\s-1IO_BUF_START\s0\fR. This is
+especially useful in combination with the \fB\-\-loop\fR option below.
+.IP "\fB\-\-baudrate\fR \fIbaudrate\fR" 4
+.IX Item "--baudrate baudrate"
+Set baudrate for files loaded after the boot loader.
+.IP "\fB\-\-bootfile\fR \fIfilename\fR" 4
+.IX Item "--bootfile filename"
+Which boot image to send to \s-1ETRAX\s0 instead of the default ones.
+.IP "\fB\-\-cmdsonly\fR" 4
+.IX Item "--cmdsonly"
+Write the commands to file e100boot.cmds.
+.IP "\fB\-\-devboard\fR" 4
+.IX Item "--devboard"
+Sets registers for the developer board.
+.IP "\fB\-\-device\fR \fIdevicename\fR" 4
+.IX Item "--device devicename"
+Which device to send packets on. For network boot the default is
+eth0. For serial boot it is ttyS0.
+.IP "\fB\-\-file\fR \fIfilename\fR|\- \fIaddress\fR [\fIsize\fR]" 4
+.IX Item "--file filename|- address [size]"
+The file to load and the address to load it to. If file is loaded on
+stdin, specify filename '\-' followed by a size. Size need only be
+given in this case. You can load as many files as you want, each
+specified with a \fB\-\-file\fR.
+.IP "\fB\-\-flash\fR \fIram-source flash-offset size\fR" 4
+.IX Item "--flash ram-source flash-offset size"
+Copies the specified \s-1RAM\s0 area to the flash.
+.IP "\fB\-\-getreg\fR \fIaddress\fR|\fIregname\fR" 4
+.IX Item "--getreg address|regname"
+Print value of memory location. Must be uncached address.
+.IP "\fB\-\-help\fR" 4
+.IX Item "--help"
+Print the help information.
+.IP "\fB\-\-images\fR" 4
+.IX Item "--images"
+Print information about the internal boot images, then exit.
+.IP "\fB\-\-jump\fR \fIaddress\fR" 4
+.IX Item "--jump address"
+Jump to specified address.
+.IP "\fB\-\-label\fR \fIlabel\fR" 4
+.IX Item "--label label"
+Define a label to be used as target by the \fB\-\-loop\fR command. This
+command is only used by the \s-1SBL\s0 to calculate the address for the
+\&\fB\-\-loop\fR and does not take up any space in the configuration packet.
+.IP "\fB\-\-loop\fR \fIcheck-address label\fR" 4
+.IX Item "--loop check-address label"
+If the contents of check-address is nonzero it is decremented and the
+command parser continues parsing at the label.
+.Sp
+If no external memory is initialized yet it can be convenient to use
+an address in the area occupied by the configuration packet. Run
+e100boot with \fB\-\-help\fR to see which addresses the commands are stored
+at. The size of the commands are four bytes for each command plus four
+bytes per argument to the command.
+.IP "\fB\-\-memclear\fR \fIstart-address end-address\fR" 4
+.IX Item "--memclear start-address end-address"
+Clears the specified memory area.
+.IP "\fB\-\-memdump\fR \fIstart-address end-address\fR" 4
+.IX Item "--memdump start-address end-address"
+Prints the contents of the specified memory area.
+.IP "\fB\-\-memtest\fR \fIstart-address end-address\fR" 4
+.IX Item "--memtest start-address end-address"
+Does a fairly extensive test of the specified memory area. Not only
+catches defect memories but also catches things like wrong memory
+setups where memory addresses are mirrored onto each other.
+.IP "\fB\-\-network\fR" 4
+.IX Item "--network"
+Perform a network boot.
+.IP "\fB\-\-noleds\fR" 4
+.IX Item "--noleds"
+When using the internal images use a version that does not toggle
+general port \s-1PA\s0 or \s-1PB\s0 in \s-1ETRAX\s0 during the boot procedure.
+.IP "\fB\-\-pause\fR \fIiterations\fR" 4
+.IX Item "--pause iterations"
+How many \fIiterations\fR to do of an empty loop.
+.IP "\fB\-\-serial\fR" 4
+.IX Item "--serial"
+Do a serial boot.
+.IP "\fB\-\-setreg\fR \fIaddress\fR|\fIregname\fR \fIvalue\fR" 4
+.IX Item "--setreg address|regname value"
+Load dword to dword aligned memory location.
+.IP "\fB\-\-testcard\fR" 4
+.IX Item "--testcard"
+Configures the memories for the \s-1ETRAX\s0 100 testcard.
+.IP "\fB\-\-testcardlx\fR" 4
+.IX Item "--testcardlx"
+Configures the memories for the \s-1ETRAX100\s0 \s-1LX\s0 testcard.
+.IP "\fB\-\-tofiles\fR" 4
+.IX Item "--tofiles"
+Write packets to files e100boot.seq[0..]. Does not transmit the data.
+.IP "\fB\-\-verify\fR \fIaddress value\fR" 4
+.IX Item "--verify address value"
+Verify that memory contains dword. If not loader will stop. This is to
+avoid booting the wrong unit. If you have the units ethernet address
+in the flash memory you can check for that.
+.IP "\fB\-\-5400\fR" 4
+.IX Item "--5400"
+Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5400
+printserver.
+.IP "\fB\-\-5600\fR" 4
+.IX Item "--5600"
+Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5600
+printserver.
+.SH "EXAMPLES"
+.IX Header "EXAMPLES"
+If you have a stripped binary (file.ima) linked to 0x08000000 that you want
+to boot via the network, do this:
+.PP
+\&\fBe100boot \-\-file file.ima 88000000 \-\-jump 08000000\fR
+.PP
+Or something like this. Sets waitstates to zero and loads two files,
+the first from stdin:
+.PP
+\&\fBcat file.ima | e100boot \-\-memtest 88000000 8801ffff \-\-memclear
+88000000 8801ffff \-\-setreg b0000000 0 \-\-getreg b0000000 \-\-file \-
+88000000 a000 \-\-file file2.ima 88010000 \-\-memdump 88000000 880000ff
+\&\-\-jump 08000000\fR
+.PP
+Or this, enables 16 bit parallel port and flashes the led on \s-1PA0:\s0
+.PP
+\&\fBe100boot \-\-testcardlx \-\-setreg R_PORT_PA_SET 0x00000000 \-\-setreg
+R_GEN_CONFIG 0x80000004 \-\-setreg R_PAR0_CONFIG 0x00000200 \-\-setreg
+R_PORT_G_DATA 0x00000000 \-\-pause 0x02000000 \-\-setreg R_PORT_G_DATA
+0xffffffff \-\-pause 0x02000000 \-\-setreg R_PORT_G_DATA 0x00000000 \-\-loop
+0x38001e0b 0x38001e60\fR
+.PP
+Setup the memory, test the \s-1SRAM\s0, print the contents of the first 256
+bytes of \s-1SRAM\s0, clear \s-1SRAM\s0, test the \s-1DRAM\s0, print R_DMA_CH0_CMD, load a
+file to \s-1SRAM\s0, load another file to \s-1SRAM\s0, load file to \s-1DRAM\s0, jump to
+code in \s-1SRAM\s0.
+.PP
+\&\fBe100boot \-\-setreg b0000000 1000 \-\-setreg b0000008 00006543 \-\-setreg
+b000000c 12966060 \-\-memtest 88000000 80000 \-\-memdump 88000000 880000ff
+\&\-\-memclear 88000000 80000 \-\-memtest c0000000 400000 \-\-getreg b00001d0
+\&\-\-file file1.ima 88000000 \-\-file file2.ima 88010000 \-\-file file3.ima
+c0000000 \-\-jump 88000000\fR
+.PP
+Boot Linux on the testcard.
+.PP
+\&\fBe100boot \-\-setreg b0000000 1000 \-\-setreg b0000008 6557 \-\-setreg
+b000000c 1b988080 \-\-file timage c0000500 \-\-jump 40000500\fR
+.PP
+Booting over serial port and using labels to flash the leds on port
+\&\s-1PA\s0.
+.PP
+\&\fBe100boot \-\-serial \-\-device /dev/ttyS1 \-\-baudrate 9600 \-\-label first
+\&\-\-setreg 0x380020e0 00000001 \-\-setreg R_PORT_PA_SET 0x0000ff00 \-\-pause
+0x02000000 \-\-setreg R_PORT_PA_SET 0x0000ffff \-\-pause 0x02000000 \-\-loop
+0x380020e0 first\fR
+.SH "BUGS"
+.IX Header "BUGS"
+You're kidding, right? Check \s-1AUTHOR\s0 below. The only thing
+would be the hubris of the author, but that I consider a feature. If
+you find any other 'features' report them to
+technology@axis.com. Don't bother the author directly, he is busy
+playing PlayStation2.
+.SH "COPYING"
+.IX Header "COPYING"
+Copyright © 1996\-2002 Axis Communications \s-1AB\s0.
+.SH "AUTHOR"
+.IX Header "AUTHOR"
+Written by Ronny Ranerup.
+.SH "SEE ALSO"
+.IX Header "SEE ALSO"
+The fine source, which you can get at http://developer.axis.com.
diff --git a/package/etrax-tools/src/e100boot/doc/e100boot.html b/package/etrax-tools/src/e100boot/doc/e100boot.html
new file mode 100644
index 000000000..15e23966d
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/doc/e100boot.html
@@ -0,0 +1,395 @@
+<?xml version="1.0" ?>
+<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Strict//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
+<html xmlns="http://www.w3.org/1999/xhtml">
+<head>
+<title>e100boot - Network and serial port bootloader for the ETRAX100 CPU.</title>
+<meta http-equiv="content-type" content="text/html; charset=utf-8" />
+<link rev="made" href="mailto:root@localhost" />
+</head>
+
+<body style="background-color: white">
+
+<p><a name="__index__"></a></p>
+<!-- INDEX BEGIN -->
+
+<ul>
+
+ <li><a href="#name">NAME</a></li>
+ <li><a href="#synopsis">SYNOPSIS</a></li>
+ <li><a href="#description">DESCRIPTION</a></li>
+ <ul>
+
+ <li><a href="#debugging_printout">Debugging printout</a></li>
+ <li><a href="#creating_binaries">Creating binaries</a></li>
+ <li><a href="#how_it_works__things_you_don_t_want_to_know_">How it works, things you don't want to know.</a></li>
+ <li><a href="#compilation_and_code">Compilation and code</a></li>
+ </ul>
+
+ <li><a href="#options">OPTIONS</a></li>
+ <li><a href="#examples">EXAMPLES</a></li>
+ <li><a href="#bugs">BUGS</a></li>
+ <li><a href="#copying">COPYING</a></li>
+ <li><a href="#author">AUTHOR</a></li>
+ <li><a href="#see_also">SEE ALSO</a></li>
+</ul>
+<!-- INDEX END -->
+
+<hr />
+<p>
+</p>
+<h1><a name="name">NAME</a></h1>
+<p>e100boot - Network and serial port bootloader for the ETRAX100 CPU.</p>
+<p>
+</p>
+<hr />
+<h1><a name="synopsis">SYNOPSIS</a></h1>
+<p><strong>e100boot</strong> [<strong>--device</strong> <em>devicename</em>]
+[<strong>--file</strong> <em>filename</em>|- <em>addr</em> [<em>size</em>]]
+[<strong>--flash</strong> <em>ram-source</em> <em>flash-offset</em> <em>size</em>] [<strong>--pause</strong> <em>iter</em>]
+[<strong>--memtest</strong> <em>addr</em> <em>addr</em>] [<strong>--memclear</strong> <em>addr</em> <em>addr</em>]
+[<strong>--memdump</strong> <em>addr</em> <em>addr</em>] [<strong>--setreg</strong> <em>addr</em>|<em>regname</em> <em>val</em>]
+[<strong>--getreg</strong> <em>addr</em>|<em>regname</em>] [<strong>--verify</strong> <em>addr</em> <em>val</em>]
+[<strong>--label</strong> <em>label</em>] [<strong>--loop</strong> <em>addr</em> <em>label</em>] [<strong>--5400</strong>] [<strong>--5600</strong>]
+[<strong>--testcard</strong>] [<strong>--devboard</strong>] [<strong>--testcardlx</strong>] [<strong>--network</strong>] [<strong>--serial</strong>]
+[<strong>--baudrate</strong> <em>baudrate</em>] [<strong>--bootfile</strong> <em>file</em>] [<strong>--jump</strong> <em>addr</em>]
+[<strong>--tofiles</strong>] [<strong>--cmdsonly</strong>] [<strong>--images</strong>] [<strong>--noleds</strong>] [<strong>--help</strong>]</p>
+<p>
+</p>
+<hr />
+<h1><a name="description">DESCRIPTION</a></h1>
+<p>This boot loader facilitates loading of files over the network or a
+serial port to an ETRAX100. It can also be used for fairly extensive
+hardware debugging as you can read and write to any memory addresses,
+including the ETRAX100 registers. You can also perform memory checks
+and dumps and copy data to flash memories.</p>
+<p>The first packet (or the first 784 bytes in the case of serial boot)
+sent to Etrax100 is loaded into the cache. The code in this packet is
+executed and loads the rest of the boot loader into the cache. The
+cache is the only thing we can be sure of exists on all ETRAX100
+products, so the boot loader is limited to the size of the cache,
+8KB. If further boot loading code is needed you have to set up
+external memory and load another boot loader into it, but this is
+rarely needed.</p>
+<p>Two programs are involved in this boot loading, one is the program on
+your workstation that sends the packets to ETRAX100, this is called
+the server boot loader or SBL. The other program is the one in
+ETRAX100 that receives packets from the SBL and acts upon the data
+therein, this is called the client boot loader or CBL.</p>
+<p>We don't want to edit and recompile the CBL each time we want to load
+level two to different parts of memory, like we do on different
+products. We also want to change things like the setup of external
+memory before we load data into it. To make the boot loading as
+flexible as possible and separate the CBL from level two we send a
+configuration packet to it. After this packet we load other files, if
+we want to.</p>
+<p>The configuration packet can contain information to the CBL which lets
+you: initialize external memory, read and write to all ETRAX100
+registers, read and write to any part of memory, load as many other
+files as you like to any part of memory you like, etc. The
+configuration packet is generated on the fly by the SBL.</p>
+<p>Since the CBL is unaware of which product it will be loaded on, it
+doesn't do product specific initialization like setting up the
+memory. This must be done with the configuration packet.</p>
+<p>
+</p>
+<h2><a name="debugging_printout">Debugging printout</a></h2>
+<p>When doing network boot the debugging printout from the CBL in ETRAX
+is transmitted back over the network and printed by e100boot. When
+doing serial boot that interface will be used. So in either case you
+will not need any other software or hardware to receive the debugging
+printout.</p>
+<p>
+</p>
+<h2><a name="creating_binaries">Creating binaries</a></h2>
+<p>The files containing code to be loaded on the ETRAX100 must be
+stripped using the standard GCC binutils.</p>
+<p>
+</p>
+<h2><a name="how_it_works__things_you_don_t_want_to_know_">How it works, things you don't want to know.</a></h2>
+<p>ack, timeout bla, bla... RTFS.</p>
+<p>
+</p>
+<h2><a name="compilation_and_code">Compilation and code</a></h2>
+<p>Noteworthy is that two separate ETRAX100 binaries are created, one for
+network boot and one for serial boot. They actually contain exactly
+the same code, but linked in different order. This is because the code
+to load the rest of the bootloader over a specific interface must be
+contained in the first data sent to the ETRAX100 and it is too
+difficult to cram the code for both interfaces in the beginning of the
+same binary. Hence two files.</p>
+<p>Other stuff you don't want to know is that the cache is mapped from
+0x380000f0 to 0x380020f0. Code starts at the first address followed by
+data up to the symbol <em>Ebss</em>. At the other end is the buffer for boot
+commands (addresses defined by <em>IO_BUF_START</em> and <em>IO_BUF_END</em> below
+which the stack lies and hopefully the stack and <em>Ebss</em> will never
+meet...</p>
+<p>The serial data is loaded from 0x380000f0 to 0x380003ff before
+execution starts.</p>
+<p>
+</p>
+<hr />
+<h1><a name="options">OPTIONS</a></h1>
+<p>The options are done in the order specified on the command line, so
+you probably want to do any memory setup before loading a file to the
+memory, and you probably do not want to perform a memory test after
+you have loaded a file to that memory.</p>
+<p>All addresses and sizes must be in hex with optional '0x' prefix, or a
+ETRAX100 register name. Since the <strong>--setreg</strong> and <strong>--getreg</strong> options
+only can be performed on dword aligned dwords only the registers that
+conform to this can be named.</p>
+<p>Note also that all addresses must be in uncached memory (bit 31 set),
+as the bootloader lies in the cache. If you access any uncached
+address during boot, the bootloader will be destroyed without warning.</p>
+<p>It is also possible to specify an address as <em>+address</em>, in which
+case it is considered to be relative to <em>IO_BUF_START</em>. This is
+especially useful in combination with the <strong>--loop</strong> option below.</p>
+<dl>
+<dt><strong><a name="item__2d_2dbaudrate_baudrate"><strong>--baudrate</strong> <em>baudrate</em></a></strong>
+
+<dd>
+<p>Set baudrate for files loaded after the boot loader.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dbootfile_filename"><strong>--bootfile</strong> <em>filename</em></a></strong>
+
+<dd>
+<p>Which boot image to send to ETRAX instead of the default ones.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dcmdsonly"><strong>--cmdsonly</strong></a></strong>
+
+<dd>
+<p>Write the commands to file e100boot.cmds.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2ddevboard"><strong>--devboard</strong></a></strong>
+
+<dd>
+<p>Sets registers for the developer board.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2ddevice_devicename"><strong>--device</strong> <em>devicename</em></a></strong>
+
+<dd>
+<p>Which device to send packets on. For network boot the default is
+eth0. For serial boot it is ttyS0.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dfile_filename_7c_2d_address__5bsize_5d"><strong>--file</strong> <em>filename</em>|- <em>address</em> [<em>size</em>]</a></strong>
+
+<dd>
+<p>The file to load and the address to load it to. If file is loaded on
+stdin, specify filename '-' followed by a size. Size need only be
+given in this case. You can load as many files as you want, each
+specified with a <strong>--file</strong>.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dflash_ram_2dsource_flash_2doffset_size"><strong>--flash</strong> <em>ram-source flash-offset size</em></a></strong>
+
+<dd>
+<p>Copies the specified RAM area to the flash.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dgetreg_address_7cregname"><strong>--getreg</strong> <em>address</em>|<em>regname</em></a></strong>
+
+<dd>
+<p>Print value of memory location. Must be uncached address.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dhelp"><strong>--help</strong></a></strong>
+
+<dd>
+<p>Print the help information.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dimages"><strong>--images</strong></a></strong>
+
+<dd>
+<p>Print information about the internal boot images, then exit.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2djump_address"><strong>--jump</strong> <em>address</em></a></strong>
+
+<dd>
+<p>Jump to specified address.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dlabel_label"><strong>--label</strong> <em>label</em></a></strong>
+
+<dd>
+<p>Define a label to be used as target by the <strong>--loop</strong> command. This
+command is only used by the SBL to calculate the address for the
+<strong>--loop</strong> and does not take up any space in the configuration packet.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dloop_check_2daddress_label"><strong>--loop</strong> <em>check-address label</em></a></strong>
+
+<dd>
+<p>If the contents of check-address is nonzero it is decremented and the
+command parser continues parsing at the label.</p>
+</dd>
+<dd>
+<p>If no external memory is initialized yet it can be convenient to use
+an address in the area occupied by the configuration packet. Run
+e100boot with <strong>--help</strong> to see which addresses the commands are stored
+at. The size of the commands are four bytes for each command plus four
+bytes per argument to the command.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dmemclear_start_2daddress_end_2daddress"><strong>--memclear</strong> <em>start-address end-address</em></a></strong>
+
+<dd>
+<p>Clears the specified memory area.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dmemdump_start_2daddress_end_2daddress"><strong>--memdump</strong> <em>start-address end-address</em></a></strong>
+
+<dd>
+<p>Prints the contents of the specified memory area.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dmemtest_start_2daddress_end_2daddress"><strong>--memtest</strong> <em>start-address end-address</em></a></strong>
+
+<dd>
+<p>Does a fairly extensive test of the specified memory area. Not only
+catches defect memories but also catches things like wrong memory
+setups where memory addresses are mirrored onto each other.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dnetwork"><strong>--network</strong></a></strong>
+
+<dd>
+<p>Perform a network boot.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dnoleds"><strong>--noleds</strong></a></strong>
+
+<dd>
+<p>When using the internal images use a version that does not toggle
+general port PA or PB in ETRAX during the boot procedure.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dpause_iterations"><strong>--pause</strong> <em>iterations</em></a></strong>
+
+<dd>
+<p>How many <em>iterations</em> to do of an empty loop.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dserial"><strong>--serial</strong></a></strong>
+
+<dd>
+<p>Do a serial boot.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dsetreg_address_7cregname_value"><strong>--setreg</strong> <em>address</em>|<em>regname</em> <em>value</em></a></strong>
+
+<dd>
+<p>Load dword to dword aligned memory location.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dtestcard"><strong>--testcard</strong></a></strong>
+
+<dd>
+<p>Configures the memories for the ETRAX 100 testcard.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dtestcardlx"><strong>--testcardlx</strong></a></strong>
+
+<dd>
+<p>Configures the memories for the ETRAX100 LX testcard.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dtofiles"><strong>--tofiles</strong></a></strong>
+
+<dd>
+<p>Write packets to files e100boot.seq[0..]. Does not transmit the data.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2dverify_address_value"><strong>--verify</strong> <em>address value</em></a></strong>
+
+<dd>
+<p>Verify that memory contains dword. If not loader will stop. This is to
+avoid booting the wrong unit. If you have the units ethernet address
+in the flash memory you can check for that.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2d5400"><strong>--5400</strong></a></strong>
+
+<dd>
+<p>Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5400
+printserver.</p>
+</dd>
+</li>
+<dt><strong><a name="item__2d_2d5600"><strong>--5600</strong></a></strong>
+
+<dd>
+<p>Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5600
+printserver.</p>
+</dd>
+</li>
+</dl>
+<p>
+</p>
+<hr />
+<h1><a name="examples">EXAMPLES</a></h1>
+<p>If you have a stripped binary (file.ima) linked to 0x08000000 that you want
+to boot via the network, do this:</p>
+<p><strong>e100boot --file file.ima 88000000 --jump 08000000</strong></p>
+<p>Or something like this. Sets waitstates to zero and loads two files,
+the first from stdin:</p>
+<p><strong>cat file.ima | e100boot --memtest 88000000 8801ffff --memclear
+88000000 8801ffff --setreg b0000000 0 --getreg b0000000 --file -
+88000000 a000 --file file2.ima 88010000 --memdump 88000000 880000ff
+--jump 08000000</strong></p>
+<p>Or this, enables 16 bit parallel port and flashes the led on PA0:</p>
+<p><strong>e100boot --testcardlx --setreg R_PORT_PA_SET 0x00000000 --setreg
+R_GEN_CONFIG 0x80000004 --setreg R_PAR0_CONFIG 0x00000200 --setreg
+R_PORT_G_DATA 0x00000000 --pause 0x02000000 --setreg R_PORT_G_DATA
+0xffffffff --pause 0x02000000 --setreg R_PORT_G_DATA 0x00000000 --loop
+0x38001e0b 0x38001e60</strong></p>
+<p>Setup the memory, test the SRAM, print the contents of the first 256
+bytes of SRAM, clear SRAM, test the DRAM, print R_DMA_CH0_CMD, load a
+file to SRAM, load another file to SRAM, load file to DRAM, jump to
+code in SRAM.</p>
+<p><strong>e100boot --setreg b0000000 1000 --setreg b0000008 00006543 --setreg
+b000000c 12966060 --memtest 88000000 80000 --memdump 88000000 880000ff
+--memclear 88000000 80000 --memtest c0000000 400000 --getreg b00001d0
+--file file1.ima 88000000 --file file2.ima 88010000 --file file3.ima
+c0000000 --jump 88000000</strong></p>
+<p>Boot Linux on the testcard.</p>
+<p><strong>e100boot --setreg b0000000 1000 --setreg b0000008 6557 --setreg
+b000000c 1b988080 --file timage c0000500 --jump 40000500</strong></p>
+<p>Booting over serial port and using labels to flash the leds on port
+PA.</p>
+<p><strong>e100boot --serial --device /dev/ttyS1 --baudrate 9600 --label first
+--setreg 0x380020e0 00000001 --setreg R_PORT_PA_SET 0x0000ff00 --pause
+0x02000000 --setreg R_PORT_PA_SET 0x0000ffff --pause 0x02000000 --loop
+0x380020e0 first</strong></p>
+<p>
+</p>
+<hr />
+<h1><a name="bugs">BUGS</a></h1>
+<p>You're kidding, right? Check <a href="#author">AUTHOR</a> below. The only thing
+would be the hubris of the author, but that I consider a feature. If
+you find any other 'features' report them to
+<a href="mailto:technology@axis.com.">technology@axis.com.</a> Don't bother the author directly, he is busy
+playing PlayStation2.</p>
+<p>
+</p>
+<hr />
+<h1><a name="copying">COPYING</a></h1>
+<p>Copyright © 1996-2002 Axis Communications AB.</p>
+<p>
+</p>
+<hr />
+<h1><a name="author">AUTHOR</a></h1>
+<p>Written by Ronny Ranerup.</p>
+<p>
+</p>
+<hr />
+<h1><a name="see_also">SEE ALSO</a></h1>
+<p>The fine source, which you can get at <a href="http://developer.axis.com.">http://developer.axis.com.</a></p>
+
+</body>
+
+</html>
diff --git a/package/etrax-tools/src/e100boot/doc/e100boot.pod b/package/etrax-tools/src/e100boot/doc/e100boot.pod
new file mode 100644
index 000000000..8ff514c6b
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/doc/e100boot.pod
@@ -0,0 +1,314 @@
+=head1 NAME
+
+e100boot - Network and serial port bootloader for the ETRAX100 CPU.
+
+=head1 SYNOPSIS
+
+B<e100boot> [B<--device> I<devicename>]
+[B<--file> I<filename>|- I<addr> [I<size>]]
+[B<--flash> I<ram-source> I<flash-offset> I<size>] [B<--pause> I<iter>]
+[B<--memtest> I<addr> I<addr>] [B<--memclear> I<addr> I<addr>]
+[B<--memdump> I<addr> I<addr>] [B<--setreg> I<addr>|I<regname> I<val>]
+[B<--getreg> I<addr>|I<regname>] [B<--verify> I<addr> I<val>]
+[B<--label> I<label>] [B<--loop> I<addr> I<label>] [B<--5400>] [B<--5600>]
+[B<--testcard>] [B<--devboard>] [B<--testcardlx>] [B<--network>] [B<--serial>]
+[B<--baudrate> I<baudrate>] [B<--bootfile> I<file>] [B<--jump> I<addr>]
+[B<--tofiles>] [B<--cmdsonly>] [B<--images>] [B<--noleds>] [B<--help>]
+
+=head1 DESCRIPTION
+
+This boot loader facilitates loading of files over the network or a
+serial port to an ETRAX100. It can also be used for fairly extensive
+hardware debugging as you can read and write to any memory addresses,
+including the ETRAX100 registers. You can also perform memory checks
+and dumps and copy data to flash memories.
+
+The first packet (or the first 784 bytes in the case of serial boot)
+sent to Etrax100 is loaded into the cache. The code in this packet is
+executed and loads the rest of the boot loader into the cache. The
+cache is the only thing we can be sure of exists on all ETRAX100
+products, so the boot loader is limited to the size of the cache,
+8KB. If further boot loading code is needed you have to set up
+external memory and load another boot loader into it, but this is
+rarely needed.
+
+Two programs are involved in this boot loading, one is the program on
+your workstation that sends the packets to ETRAX100, this is called
+the server boot loader or SBL. The other program is the one in
+ETRAX100 that receives packets from the SBL and acts upon the data
+therein, this is called the client boot loader or CBL.
+
+We don't want to edit and recompile the CBL each time we want to load
+level two to different parts of memory, like we do on different
+products. We also want to change things like the setup of external
+memory before we load data into it. To make the boot loading as
+flexible as possible and separate the CBL from level two we send a
+configuration packet to it. After this packet we load other files, if
+we want to.
+
+The configuration packet can contain information to the CBL which lets
+you: initialize external memory, read and write to all ETRAX100
+registers, read and write to any part of memory, load as many other
+files as you like to any part of memory you like, etc. The
+configuration packet is generated on the fly by the SBL.
+
+Since the CBL is unaware of which product it will be loaded on, it
+doesn't do product specific initialization like setting up the
+memory. This must be done with the configuration packet.
+
+=head2 Debugging printout
+
+When doing network boot the debugging printout from the CBL in ETRAX
+is transmitted back over the network and printed by e100boot. When
+doing serial boot that interface will be used. So in either case you
+will not need any other software or hardware to receive the debugging
+printout.
+
+=head2 Creating binaries
+
+The files containing code to be loaded on the ETRAX100 must be
+stripped using the standard GCC binutils.
+
+=head2 How it works, things you don't want to know.
+
+ack, timeout bla, bla... RTFS.
+
+=head2 Compilation and code
+
+Noteworthy is that two separate ETRAX100 binaries are created, one for
+network boot and one for serial boot. They actually contain exactly
+the same code, but linked in different order. This is because the code
+to load the rest of the bootloader over a specific interface must be
+contained in the first data sent to the ETRAX100 and it is too
+difficult to cram the code for both interfaces in the beginning of the
+same binary. Hence two files.
+
+Other stuff you don't want to know is that the cache is mapped from
+0x380000f0 to 0x380020f0. Code starts at the first address followed by
+data up to the symbol I<Ebss>. At the other end is the buffer for boot
+commands (addresses defined by I<IO_BUF_START> and I<IO_BUF_END> below
+which the stack lies and hopefully the stack and I<Ebss> will never
+meet...
+
+The serial data is loaded from 0x380000f0 to 0x380003ff before
+execution starts.
+
+=head1 OPTIONS
+
+The options are done in the order specified on the command line, so
+you probably want to do any memory setup before loading a file to the
+memory, and you probably do not want to perform a memory test after
+you have loaded a file to that memory.
+
+All addresses and sizes must be in hex with optional '0x' prefix, or a
+ETRAX100 register name. Since the B<--setreg> and B<--getreg> options
+only can be performed on dword aligned dwords only the registers that
+conform to this can be named.
+
+Note also that all addresses must be in uncached memory (bit 31 set),
+as the bootloader lies in the cache. If you access any uncached
+address during boot, the bootloader will be destroyed without warning.
+
+It is also possible to specify an address as I<+address>, in which
+case it is considered to be relative to I<IO_BUF_START>. This is
+especially useful in combination with the B<--loop> option below.
+
+=over 4
+
+=item B<--baudrate> I<baudrate>
+
+Set baudrate for files loaded after the boot loader.
+
+=item B<--bootfile> I<filename>
+
+Which boot image to send to ETRAX instead of the default ones.
+
+=item B<--cmdsonly>
+
+Write the commands to file e100boot.cmds.
+
+=item B<--devboard>
+
+Sets registers for the developer board.
+
+=item B<--device> I<devicename>
+
+Which device to send packets on. For network boot the default is
+eth0. For serial boot it is ttyS0.
+
+=item B<--file> I<filename>|- I<address> [I<size>]
+
+The file to load and the address to load it to. If file is loaded on
+stdin, specify filename '-' followed by a size. Size need only be
+given in this case. You can load as many files as you want, each
+specified with a B<--file>.
+
+=item B<--flash> I<ram-source flash-offset size>
+
+Copies the specified RAM area to the flash.
+
+=item B<--getreg> I<address>|I<regname>
+
+Print value of memory location. Must be uncached address.
+
+=item B<--help>
+
+Print the help information.
+
+=item B<--images>
+
+Print information about the internal boot images, then exit.
+
+=item B<--jump> I<address>
+
+Jump to specified address.
+
+=item B<--label> I<label>
+
+Define a label to be used as target by the B<--loop> command. This
+command is only used by the SBL to calculate the address for the
+B<--loop> and does not take up any space in the configuration packet.
+
+=item B<--loop> I<check-address label>
+
+If the contents of check-address is nonzero it is decremented and the
+command parser continues parsing at the label.
+
+If no external memory is initialized yet it can be convenient to use
+an address in the area occupied by the configuration packet. Run
+e100boot with B<--help> to see which addresses the commands are stored
+at. The size of the commands are four bytes for each command plus four
+bytes per argument to the command.
+
+=item B<--memclear> I<start-address end-address>
+
+Clears the specified memory area.
+
+=item B<--memdump> I<start-address end-address>
+
+Prints the contents of the specified memory area.
+
+=item B<--memtest> I<start-address end-address>
+
+Does a fairly extensive test of the specified memory area. Not only
+catches defect memories but also catches things like wrong memory
+setups where memory addresses are mirrored onto each other.
+
+=item B<--network>
+
+Perform a network boot.
+
+=item B<--noleds>
+
+When using the internal images use a version that does not toggle
+general port PA or PB in ETRAX during the boot procedure.
+
+=item B<--pause> I<iterations>
+
+How many I<iterations> to do of an empty loop.
+
+=item B<--serial>
+
+Do a serial boot.
+
+=item B<--setreg> I<address>|I<regname> I<value>
+
+Load dword to dword aligned memory location.
+
+=item B<--testcard>
+
+Configures the memories for the ETRAX 100 testcard.
+
+=item B<--testcardlx>
+
+Configures the memories for the ETRAX100 LX testcard.
+
+=item B<--tofiles>
+
+Write packets to files e100boot.seq[0..]. Does not transmit the data.
+
+=item B<--verify> I<address value>
+
+Verify that memory contains dword. If not loader will stop. This is to
+avoid booting the wrong unit. If you have the units ethernet address
+in the flash memory you can check for that.
+
+=item B<--5400>
+
+Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5400
+printserver.
+
+=item B<--5600>
+
+Sets R_WAITSTATES, R_DRAM_TIMING and R_DRAM_CONFIG for the 5600
+printserver.
+
+=back
+
+=head1 EXAMPLES
+
+If you have a stripped binary (file.ima) linked to 0x08000000 that you want
+to boot via the network, do this:
+
+B<e100boot --file file.ima 88000000 --jump 08000000>
+
+Or something like this. Sets waitstates to zero and loads two files,
+the first from stdin:
+
+B<cat file.ima | e100boot --memtest 88000000 8801ffff --memclear
+88000000 8801ffff --setreg b0000000 0 --getreg b0000000 --file -
+88000000 a000 --file file2.ima 88010000 --memdump 88000000 880000ff
+--jump 08000000>
+
+Or this, enables 16 bit parallel port and flashes the led on PA0:
+
+B<e100boot --testcardlx --setreg R_PORT_PA_SET 0x00000000 --setreg
+R_GEN_CONFIG 0x80000004 --setreg R_PAR0_CONFIG 0x00000200 --setreg
+R_PORT_G_DATA 0x00000000 --pause 0x02000000 --setreg R_PORT_G_DATA
+0xffffffff --pause 0x02000000 --setreg R_PORT_G_DATA 0x00000000 --loop
+0x38001e0b 0x38001e60>
+
+Setup the memory, test the SRAM, print the contents of the first 256
+bytes of SRAM, clear SRAM, test the DRAM, print R_DMA_CH0_CMD, load a
+file to SRAM, load another file to SRAM, load file to DRAM, jump to
+code in SRAM.
+
+B<e100boot --setreg b0000000 1000 --setreg b0000008 00006543 --setreg
+b000000c 12966060 --memtest 88000000 80000 --memdump 88000000 880000ff
+--memclear 88000000 80000 --memtest c0000000 400000 --getreg b00001d0
+--file file1.ima 88000000 --file file2.ima 88010000 --file file3.ima
+c0000000 --jump 88000000>
+
+Boot Linux on the testcard.
+
+B<e100boot --setreg b0000000 1000 --setreg b0000008 6557 --setreg
+b000000c 1b988080 --file timage c0000500 --jump 40000500>
+
+Booting over serial port and using labels to flash the leds on port
+PA.
+
+B<e100boot --serial --device /dev/ttyS1 --baudrate 9600 --label first
+--setreg 0x380020e0 00000001 --setreg R_PORT_PA_SET 0x0000ff00 --pause
+0x02000000 --setreg R_PORT_PA_SET 0x0000ffff --pause 0x02000000 --loop
+0x380020e0 first>
+
+=head1 BUGS
+
+You're kidding, right? Check L<AUTHOR|"AUTHOR"> below. The only thing
+would be the hubris of the author, but that I consider a feature. If
+you find any other 'features' report them to
+technology@axis.com. Don't bother the author directly, he is busy
+playing PlayStation2.
+
+=head1 COPYING
+
+Copyright © 1996-2002 Axis Communications AB.
+
+=head1 AUTHOR
+
+Written by Ronny Ranerup.
+
+=head1 SEE ALSO
+
+The fine source, which you can get at http://developer.axis.com.
+
diff --git a/package/etrax-tools/src/e100boot/doc/pod2htmd.tmp b/package/etrax-tools/src/e100boot/doc/pod2htmd.tmp
new file mode 100644
index 000000000..61e86d9f1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/doc/pod2htmd.tmp
@@ -0,0 +1,2 @@
+
+.
diff --git a/package/etrax-tools/src/e100boot/doc/pod2htmi.tmp b/package/etrax-tools/src/e100boot/doc/pod2htmi.tmp
new file mode 100644
index 000000000..61e86d9f1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/doc/pod2htmi.tmp
@@ -0,0 +1,2 @@
+
+.
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/CHANGES b/package/etrax-tools/src/e100boot/libpcap-0.4/CHANGES
new file mode 100644
index 000000000..b2c18326d
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/CHANGES
@@ -0,0 +1,267 @@
+@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/CHANGES,v 1.1 1999/08/26 10:05:17 johana Exp $ (LBL)
+
+v0.4 Sat Jul 25 12:40:09 PDT 1998
+
+- Fix endian problem with DLT_NULL devices. From FreeBSD via Bill
+ Fenner (fenner@parc.xerox.com)
+
+- Fix alignment problem with FDDI under DLPI. This was causing core
+ dumps under Solaris.
+
+- Added configure options to disable flex and bison. Resulted from a
+ bug report by barnett@grymoire.crd.ge.com (Bruce Barnett). Also added
+ options to disable gcc and to force a particular packet capture type.
+
+- Added support for Fore ATM interfaces (qaa and fa) under IRIX. Thanks
+ to John Hawkinson (jhawk@mit.edu)
+
+- Change Linux PPP and SLIP to use DLT_RAW since the kernel does not
+ supply any "link layer" data.
+
+- Change Linux to use SIOCGIFHWADDR ioctl to determine link layer type.
+ Thanks to Thomas Sailer (sailer@ife.ee.ethz.ch)
+
+- Change IRIX PPP to use DLT_RAW since the kernel does not supply any
+ "link layer" data.
+
+- Modified to support the new BSD/OS 2.1 PPP and SLIP link layer header
+ formats.
+
+- Added some new SGI snoop interface types. Thanks to Steve Alexander
+ (sca@refugee.engr.sgi.com)
+
+- Fixes for HP-UX 10.20 (which is similar to HP-UX 9). Thanks to
+ Richard Allen (ra@hp.is) and Steinar Haug (sthaug@nethelp.no)
+
+- Fddi supports broadcast as reported by Jeff Macdonald
+ (jeff@iacnet.com). Also correct ieee802 and arcnet.
+
+- Determine Linux pcap buffer size at run time or else it might not be
+ big enough for some interface types (e.g. FDDI). Thanks to Jes
+ Sorensen (Jes.Sorensen@cern.ch)
+
+- Fix some linux alignment problems.
+
+- Document promisc argument to pcap_open_live(). Reported by Ian Marsh
+ (ianm@sics.se)
+
+- Support Metricom radio packets under Linux. Thanks to Kevin Lai
+ (laik@gunpowder.stanford.edu)
+
+- Bind to interface name under Linux to avoid packets from multiple
+ interfaces on multi-homed hosts. Thanks to Kevin Lai
+ (laik@gunpowder.stanford.edu)
+
+- Change L_SET to SEEK_SET for HP-UX. Thanks to Roland Roberts
+ (rroberts@muller.com)
+
+- Fixed an uninitialized memory reference found by Kent Vander Velden
+ (graphix@iastate.edu)
+
+- Fixed lex pattern for IDs to allow leading digits. As reported by
+ Theo de Raadt (deraadt@cvs.openbsd.org)
+
+- Fixed Linux include file problems when using GNU libc.
+
+- Ifdef ARPHRD_FDDI since not all versions of the Linux kernel have it.
+ Reported reported by Eric Jacksch (jacksch@tenebris.ca)
+
+- Fixed bug in pcap_dispatch() that kept it from returning on packet
+ timeouts.
+
+- Changed ISLOOPBACK() macro when IFF_LOOPBACK isn't available to check
+ for "lo" followed by an eos or digit (newer versions of Linux
+ apparently call the loopback "lo" instead of "lo0").
+
+- Fixed Linux networking include files to use ints instead of longs to
+ avoid problems with 64 bit longs on the alpha. Thanks to Cristian
+ Gafton (gafton@redhat.com)
+
+v0.3 Sat Nov 30 20:56:27 PST 1996
+
+- Added Linux support.
+
+- Fixed savefile bugs.
+
+- Solaris x86 fix from Tim Rylance (t.rylance@elsevier.nl)
+
+- Add support for bpf kernel port filters.
+
+- Remove duplicate atalk protocol table entry. Thanks to Christian
+ Hopps (chopps@water.emich.edu)
+
+- Fixed pcap_lookupdev() to ignore nonexistent devices. This was
+ reported to happen under BSD/OS by David Vincenzetti
+ (vince@cryptonet.it)
+
+- Avoid solaris compiler warnings. Thanks to Bruce Barnett
+ (barnett@grymoire.crd.ge.com)
+
+v0.2.1 Sun Jul 14 03:02:26 PDT 1996
+
+- Fixes for HP-UX 10. Thanks in part to to Thomas Wolfram
+ (wolf@prz.tu-berlin.de) and Rick Jones (raj@hpisrdq.cup.hp.com)
+
+- Added support for SINIX. Thanks to Andrej Borsenkow
+ (borsenkow.msk@sni.de)
+
+- Fixes for AIX (although this system is not yet supported). Thanks to
+ John Hawkinson (jhawk@mit.edu)
+
+- Use autoconf's idea of the top level directory in install targets.
+ Thanks to John Hawkinson.
+
+- Add missing autoconf packet capture result message. Thanks to Bill
+ Fenner (fenner@parc.xerox.com)
+
+- Fixed padding problems in the pf module.
+
+- Fixed some more alignment problems on the alpha.
+
+- Added explicit netmask support. Thanks to Steve Nuchia
+ (steve@research.oknet.com)
+
+- Fixed to handle raw ip addresses such as 0.0.0.1 without "left
+ justifing"
+
+- Add "sca" keyword (for DEC cluster services) as suggested by Terry
+ Kennedy (terry@spcvxa.spc.edu)
+
+- Add "atalk" keyword as suggested by John Hawkinson.
+
+- Add "igrp" keyword.
+
+- Fixed HID definition in grammar.y to be a string, not a value.
+
+- Use $CC when checking gcc version. Thanks to Carl Lindberg
+ (carl_lindberg@blacksmith.com)
+
+- Removed obsolete reference to pcap_immediate() from the man page.
+ Michael Stolarchuk (mts@terminator.rs.itd.umich.edu)
+
+- DLT_NULL has a 4 byte family header. Thanks to Jeffrey Honig
+ (jch@bsdi.com)
+
+v0.2 Sun Jun 23 02:28:42 PDT 1996
+
+- Add support for HP-UX. Resulted from code contributed by Tom Murray
+ (tmurray@hpindck.cup.hp.com) and Philippe-Andri Prindeville
+ (philipp@res.enst.fr)
+
+- Update INSTALL with a reminder to install include files. Thanks to
+ Mark Andrews (mandrews@aw.sgi.com)
+
+- Fix bpf compiler alignment bug on the alpha.
+
+- Use autoconf to detect architectures that can't handle misaligned
+ accesses.
+
+- Added loopback support for snoop. Resulted from report Steve
+ Alexander (sca@engr.sgi.com)
+
+v0.1 Fri Apr 28 18:11:03 PDT 1995
+
+- Fixed compiler and optimizer bugs. The BPF filter engine uses unsigned
+ comparison operators, while the code generator and optimizer assumed
+ signed semantics in several places. Thanks to Charlie Slater
+ (cslater@imatek.com) for pointing this out.
+
+- Removed FDDI ifdef's, they aren't really needed. Resulted from report
+ by Gary Veum (veum@boa.gsfc.nasa.gov).
+
+- Add pcap-null.c which allows offline use of libpcap on systems that
+ don't support live package capture. This feature resulting from a
+ request from Jan van Oorschot (j.p.m.voorschot@et.tudelft.nl).
+
+- Make bpf_compile() reentrant. Fix thanks to Pascal Hennequin
+ (Pascal.Hennequin@hugo.int-evry.fr).
+
+- Port to GNU autoconf.
+
+- Fix pcap-dlpi.c to work with isdn. Resulted from report by Flemming
+ Johansen (fsj@csd.cri.dk).
+
+- Handle multi-digit interface unit numbers (aka ppa's) under dlpi.
+ Resulted from report by Daniel Ehrlich (ehrlich@cse.psu.edu).
+
+- Fix pcap-dlpi.c to work in non-promiscuous mode. Resulted from report
+ by Jeff Murphy (jcmurphy@acsu.buffalo.edu).
+
+- Add support for "long jumps". Thanks to Jeffrey Mogul
+ (mogul@pa.dec.com).
+
+- Fix minor problems when compiling with BDEBUG as noticed by Scott
+ Bertilson (scott@unet.umn.edu).
+
+- Declare sys_errlist "const char *const" to avoid problems under
+ FreeBSD. Resulted from report by jher@eden.com.
+
+v0.0.6 Fri Apr 28 04:07:13 PDT 1995
+
+- Add missing variable declaration missing from 0.0.6
+
+v0.0.5 Fri Apr 28 00:22:21 PDT 1995
+
+- Workaround for problems when pcap_read() returns 0 due to the timeout
+ expiring.
+
+v0.0.4 Thu Apr 20 20:41:48 PDT 1995
+
+- Change configuration to not use gcc v2 flags with gcc v1.
+
+- Fixed a bug in pcap_next(); if pcap_dispatch() returns 0, pcap_next()
+ should also return 0. Thanks to Richard Stevens (rstevens@noao.edu).
+
+- Fixed configure to test for snoop before dlpi to avoid problems under
+ IRIX 5. Thanks to J. Eric Townsend (jet@abulafia.genmagic.com).
+
+- Hack around deficiency in Ultrix's make.
+
+- Fix two bugs related to the Solaris pre-5.3.2 bufmod bug; handle
+ savefiles that have more than snapshot bytes of data in them (so we
+ can read old savefiles) and avoid writing such files.
+
+- Added checkioctl which is used with gcc to check that the
+ "fixincludes" script has been run.
+
+v0.0.3 Tue Oct 18 18:13:46 PDT 1994
+
+- Fixed configure to test for snoop before dlpi to avoid problems under
+ IRIX 5. Thanks to J. Eric Townsend (jet@abulafia.genmagic.com).
+
+v0.0.2 Wed Oct 12 20:56:37 PDT 1994
+
+- Implement timeout in the dlpi pcap_open_live(). Thanks to Richard
+ Stevens.
+
+- Determine pcap link type from dlpi media type. Resulted from report
+ by Mahesh Jethanandani (mahesh@npix.com).
+
+v0.0.1 Fri Jun 24 14:50:57 PDT 1994
+
+- Fixed bug in nit_setflags() in pcap-snit.c. The streams ioctl timeout
+ wasn't being initialized sometimes resulting in an "NIOCSFLAGS:
+ Invalid argument" error under OSF/1. Reported by Matt Day
+ (mday@artisoft.com) and Danny Mitzel (dmitzel@whitney.hitc.com).
+
+- Turn on FDDI support by default.
+
+v0.0 Mon Jun 20 19:20:16 PDT 1994
+
+- Initial release.
+
+- Fixed bug with greater/less keywords, reported by Mark Andrews
+ (mandrews@alias.com).
+
+- Fix bug where '|' was defined as BPF_AND instead of BPF_OR, reported
+ by Elan Amir (elan@leeb.cs.berkeley.edu).
+
+- Machines with little-endian byte ordering are supported thanks to
+ Jeff Mogul.
+
+- Add hack for version 2.3 savefiles which don't have caplen and len
+ swapped thanks to Vern Paxson.
+
+- Added "&&" and "||" aliases for "and" and "or" thanks to Vern Paxson.
+
+- Added length, inbound and outbound keywords.
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/FILES b/package/etrax-tools/src/e100boot/libpcap-0.4/FILES
new file mode 100644
index 000000000..daad279eb
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/FILES
@@ -0,0 +1,50 @@
+CHANGES
+FILES
+INSTALL
+Makefile.in
+README
+SUNOS4
+VERSION
+aclocal.m4
+bpf/net/bpf.h
+bpf/net/bpf_filter.c
+bpf_image.c
+config.guess
+config.sub
+configure
+configure.in
+etherent.c
+ethertype.h
+gencode.c
+gencode.h
+grammar.y
+inet.c
+install-sh
+lbl/gnuc.h
+lbl/os-solaris2.h
+lbl/os-sunos4.h
+lbl/os-ultrix4.h
+linux-include/netinet/if_ether.h
+linux-include/netinet/ip_var.h
+mkdep
+nametoaddr.c
+optimize.c
+pcap-bpf.c
+pcap-dlpi.c
+pcap-enet.c
+pcap-int.h
+pcap-linux.c
+pcap-namedb.h
+pcap-nit.c
+pcap-nit.h
+pcap-null.c
+pcap-pf.c
+pcap-pf.h
+pcap-snit.c
+pcap-snoop.c
+pcap.3
+pcap.c
+pcap.h
+ppp.h
+savefile.c
+scanner.l
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/INSTALL b/package/etrax-tools/src/e100boot/libpcap-0.4/INSTALL
new file mode 100644
index 000000000..e10859751
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/INSTALL
@@ -0,0 +1,328 @@
+@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/INSTALL,v 1.1 1999/08/26 10:05:18 johana Exp $ (LBL)
+
+To build libpcap, first customize any paths in Makefile.in, then run
+"./configure" (a shell script). The configure script will determine
+your system attributes and generate an appropriate Makefile from
+Makefile.in. Next run "make". If everything goes well you can su to
+root and run "make install", "make install-incl" and "make
+install-man". However, you need not install libpcap if you just want to
+build tcpdump; just make sure the tcpdump and libpcap directory trees
+have the same parent directory.
+
+If configure says:
+
+ configure: warning: cannot determine packet capture interface
+ configure: warning: (see INSTALL for more info)
+
+then your system either does not support packet capture or your system
+does support packet capture but libpcap does not support that
+particular type. (If you have HP-UX, see below.) If your system uses a
+packet capture not supported by libpcap, please send us patches; don't
+forget to include an autoconf fragment suitable for use in
+configure.in.
+
+It is possible to override the default packet capture type, although
+the circumstance where this works are limited. For example if you have
+installed bpf under SunOS 4 and wish to build a snit libpcap:
+
+ ./configure --with-pcap=snit
+
+Another example is to force a supported packet capture type in the case
+where the configure scripts fails to detect it.
+
+You will need an ANSI C compiler to build libpcap. The configure script
+will abort if your compiler is not ANSI compliant. If this happens, use
+the GNU C compiler, available via anonymous ftp:
+
+ ftp://prep.ai.mit.edu/pub/gnu/gcc-*.tar.gz
+
+Note well: If you use gcc, you may need to run its "fixincludes"
+script. Running fixincludes is not required with later versions of gcc
+and in some cases (e.g. Solaris 2.5) causes problems when run. The
+configure script will abort with:
+
+ checking for ANSI ioctl definitions... yes
+ configure: error: see the INSTALL for more info
+
+if it detects if the fixincludes needs to be run. If the fixincludes
+test in configure passes, you're probably ok.
+
+If you use flex, you must use version 2.4.6 or higher. The configure
+script automatically detects the version of flex and will not use it
+unless it is new enough. You can use "flex -V" to see what version you
+have (unless it's really old). The current version of flex is available
+via anonymous ftp:
+
+ ftp://ftp.ee.lbl.gov/flex-*.tar.Z
+
+As of this writing, the current version is 2.5.4.
+
+If you use bison, you must use flex (and visa versa). The configure
+script automatically falls back to lex and yacc if both flex and bison
+are not found.
+
+Sometimes the stock C compiler does not interact well with flex and
+bison. The list of problems includes undefined references for alloca.
+You can get around this by installing gcc or manually disabling flex
+and bison with:
+
+ ./configure --without-flex --without-bison
+
+If your system only has AT&T lex, this is okay unless your libpcap
+program uses other lex/yacc generated code. (Although it's possible to
+map the yy* identifiers with a script, we use flex and bison so we
+don't feel this is necessary.)
+
+Some systems support the Berkeley Packet Filter natively; for example
+out of the box OSF and BSD/OS have bpf. If your system does not support
+bpf, you will need to pick up:
+
+ ftp://ftp.ee.lbl.gov/bpf-*.tar.Z
+
+Note well: you MUST have kernel source for your operating system in
+order to install bpf. An exception is SunOS 4; the bpf distribution
+includes replacement kernel objects for some of the standard SunOS 4
+network device drivers. See the bpf INSTALL document for more
+information.
+
+If you use Solaris, there is a bug with bufmod(7) that is fixed in
+Solaris 2.3.2 (aka SunOS 5.3.2). Setting a snapshot length with the
+broken bufmod(7) results in data be truncated from the FRONT of the
+packet instead of the end. The work around is to not set a snapshot
+length but this results in performance problems since the entire packet
+is copied to user space. If you must run an older version of Solaris,
+there is a patch available from Sun; ask for bugid 1149065. After
+installing the patch, use "setenv BUFMOD_FIXED" to enable use of
+bufmod(7). However, we recommend you run a more current release of
+Solaris.
+
+If you use the SPARCompiler, you must be careful to not use the
+/usr/ucb/cc interface. If you do, you will get bogus warnings and
+perhaps errors. Either make sure your path has /opt/SUNWspro/bin
+before /usr/ucb or else:
+
+ setenv CC /opt/SUNWspro/bin/cc
+
+before running configure. (You might have to do a "make distclean"
+if you already ran configure once).
+
+Also note that "make depend" won't work; while all of the known
+universe uses -M, the SPARCompiler uses -xM to generate makefile
+dependencies.
+
+If you are trying to do packet capture with a FORE ATM card, you may or
+may not be able to. They usually only release their driver in object
+code so unless their driver supports packet capture, there's not much
+libpcap can do.
+
+If you get an error like:
+
+ tcpdump: recv_ack: bind error 0x???
+
+when using DLPI, look for the DL_ERROR_ACK error return values, usually
+in /usr/include/sys/dlpi.h, and find the corresponding value.
+
+Under OSF, packet capture must be enabled before it can be used. For
+instructions on how to enable packet filter support, see:
+
+ ftp://ftp.digital.com/pub/Digital/dec-faq/Digital-UNIX
+
+Once you enable packet filter support, your OSF system will support bpf
+natively.
+
+Under Ultrix, packet capture must be enabled before it can be used. For
+instructions on how to enable packet filter support, see:
+
+ ftp://ftp.digital.com/pub/Digital/dec-faq/ultrix
+
+If you use HP-UX, you must have at least version 9 and either the
+version of cc that supports ANSI C (cc -Aa) or else use the GNU C
+compiler. You must also buy the optional streams package. If you don't
+have:
+
+ /usr/include/sys/dlpi.h
+ /usr/include/sys/dlpi_ext.h
+
+then you don't have the streams package. In addition, we believe you
+need to install the "9.X LAN and DLPI drivers cumulative" patch
+(PHNE_6855) to make the version 9 DLPI work with libpcap.
+
+It's been reported that the DLPI streams package is standard starting
+with HP-UX 10.
+
+The HP implementation of DLPI is a little bit eccentric. Unlike
+Solaris, you must attach /dev/dlpi instead of the specific /dev/*
+network pseudo device entry in order to capture packets. The ppa is
+based on the ifnet "index" number. Under HP-UX 9, it is necessary to
+read /dev/kmem and the kernel symbol file (/hp-ux). Under HP-UX 10,
+dlpi can provide information for determining the ppa. It does not seem
+to be possible to trace the loopback interface. Unlike other DLPI
+implementations, PHYS implies MULTI and SAP and you get an error if you
+try to enable more than one promiscous more than one promiscuous mode
+at a time. Finally, testing shows that there can't be more than one
+simultaneous dlpi user per network interface and you cannot capture
+outbound packets.
+
+If you use Linux, this version of libpcap is known to compile and run
+under Red Hat 4.0 with the 2.0.25 kernel. It may work with earlier 2.X
+versions but is guaranteed not to work with 1.X kernels. Running more
+than one libpcap program at a time can cause problems since promiscuous
+mode is implemented by twiddlin the interface flags from the libpcap
+application. Also, packet timestamps aren't very good. This appears to
+be due to haphazard handling of the timestamp in the kernel.
+
+Note well: there is rumoured to be a version of tcpdump floating around
+called 3.0.3 that includes libpcap and is supposed to support Linux.
+You should be advised that the Network Research Group at LBNL never
+generated a release with this version number. We note with interest
+that a standard cracker trick to get people to install trojans is to
+distribute bogus packages that have a version number higher than the
+current release. We also note with annoyance that 90% of the Linux
+related bug reports we get are due to changes made to unofficial
+versions of our page. If you are having trouble but aren't using a
+version that came from ftp.ee.lbl.gov, please try that before
+submitting a bug report!
+
+If you use AIX, you may not be able to build libpcap from this release.
+Although AIX 4 ships with tcpdump, it is an old version that predates
+libpcap. We do not have an AIX system in house so it's impossible for
+us to test AIX patches submitted to us. We are told that you must link
+against /lib/pse.exp, that you must use AIX cc or a GNU C compiler
+newer than 2.7.2 and that you may need to run strload before running a
+libpcap application. Also, it may be necessary to run the configure
+script as root in order for it to detect that bpf is available. Another
+workaround is to use:
+
+ ./configure --with-pcap=bpf
+
+If you use NeXTSTEP, you will not be able to build libpcap from this
+release. We hope to support this operating system in some future
+release of libpcap.
+
+If you use SINIX, you should be able to build libpcap from this
+release. It is known to compile and run on SINIX-Y/N 5.42 with the C-DS
+V1.0 or V1.1 compiler. But note that in some releases of SINIX, yacc
+emits incorrect code; if grammar.y fails to compile, change every
+occurence of:
+
+ #ifdef YYDEBUG
+
+to:
+ #if YYDEBUG
+
+Another workaround is to use flex and bison.
+
+If you use SCO, you might have trouble building libpcap from this
+release. We do not have a machine running SCO and have not had reports
+of anyone successfully building on it. Since SCO apparently supports
+dlpi, it's possible the current version works. Meanwhile, sco provides
+a tcpdump binary as part of their "Network/Security Tools" package:
+
+ http://www.sco.com/technology/internet/goodies/#SECURITY
+
+There is also a README that explains how to enable packet capture.
+
+If you use UnixWare, you will not be able to build libpcap from this
+release. We hope to support this operating system in some future
+release of libpcap. Meanwhile, there appears to be an UnixWare port of
+libpcap 0.0 (and tcpdump 3.0) in:
+
+ ftp://ftp1.freebird.org/pub/mirror/freebird/internet/systools/
+
+UnixWare appears to use a hacked version of DLPI.
+
+If linking tcpdump fails with "Undefined: _alloca" when using bison on
+a Sun4, your version of bison is broken. In any case version 1.16 or
+higher is recommended (1.14 is known to cause problems 1.16 is known to
+work). Either pick up a current version from:
+
+ ftp://prep.ai.mit.edu/pub/gnu/bison.tar.gz
+
+or hack around it by inserting the lines:
+
+ #ifdef __GNUC__
+ #define alloca __builtin_alloca
+ #else
+ #ifdef sparc
+ #include <alloca.h>
+ #else
+ char *alloca ();
+ #endif
+ #endif
+
+right after the (100 line!) GNU license comment in bison.simple, remove
+grammar.[co] and fire up make again.
+
+If you use SunOS 4, your kernel must support streams NIT. If you run a
+libpcap program and it dies with:
+
+ /dev/nit: No such device
+
+You must add streams NIT support to your kernel configuration, run
+config and boot the new kernel.
+
+If you are running a version of SunOS earlier than 4.1, you will need
+to replace the Sun supplied /sys/sun{3,4,4c}/OBJ/nit_if.o with the
+appropriate version from this distribution's SUNOS4 subdirectory and
+build a new kernel:
+
+ nit_if.o.sun3-sunos4 (any flavor of sun3)
+ nit_if.o.sun4c-sunos4.0.3c (SS1, SS1+, IPC, SLC, etc.)
+ nit_if.o.sun4-sunos4 (Sun4's not covered by
+ nit_if.o.sun4c-sunos4.0.3c)
+
+These nit replacements fix a bug that makes nit essentially unusable in
+pre-SunOS 4.1. In addition, our sun4c-sunos4.0.3c nit gives you
+timestamps to the resolution of the SS-1 clock (1 us) rather than the
+lousy 20ms timestamps Sun gives you (tcpdump will print out the full
+timestamp resolution if it finds it's running on a SS-1).
+
+FILES
+-----
+CHANGES - description of differences between releases
+FILES - list of files exported as part of the distribution
+INSTALL - this file
+Makefile.in - compilation rules (input to the configure script)
+README - description of distribution
+SUNOS4 - pre-SunOS 4.1 replacement kernel nit modules
+VERSION - version of this release
+aclocal.m4 - autoconf macros
+bpf/net - copies of bpf_filter.c and bpf.h
+bpf_filter.c - symlink to bpf/net/bpf_filter.c
+bpf_image.c - bpf disassembly routine
+config.guess - autoconf support
+config.sub - autoconf support
+configure - configure script (run this first)
+configure.in - configure script source
+etherent.c - /etc/ethers support routines
+ethertype.h - ethernet protocol types and names definitions
+gencode.c - bpf code generation routines
+gencode.h - bpf code generation definitions
+grammar.y - filter string grammar
+inet.c - network routines
+install-sh - BSD style install script
+lbl/gnuc.h - gcc macros and defines
+lbl/os-*.h - os dependent defines and prototypes
+linux-include/* - network include files missing on Linux
+mkdep - construct Makefile dependency list
+nametoaddr.c - hostname to address routines
+net - symlink to bpf/net
+optimize.c - bpf optimization routines
+pcap-bpf.c - BSD Packet Filter support
+pcap-dlpi.c - Data Link Provider Interface support
+pcap-enet.c - enet support
+pcap-int.h - internal libpcap definitions
+pcap-namedb.h - public libpcap name database definitions
+pcap-nit.c - Network Interface Tap support
+pcap-nit.h - Network Interface Tap definitions
+pcap-null.c - dummy monitor support (allows offline use of libpcap)
+pcap-pf.c - Packet Filter support
+pcap-pf.h - Packet Filter definitions
+pcap-snit.c - Streams based Network Interface Tap support
+pcap-snoop.c - Snoop network monitoring support
+pcap.3 - manual entry
+pcap.c - pcap utility routines
+pcap.h - public libpcap definitions
+ppp.h - Point to Point Protocol definitions
+savefile.c - offline support
+scanner.l - filter string scanner
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile b/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile
new file mode 100644
index 000000000..188a9b80e
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile
@@ -0,0 +1,173 @@
+# Generated automatically from Makefile.in by configure.
+# $Id: Makefile.in,v 1.7 2002/09/18 15:29:46 pkj Exp $
+# Copyright (c) 1993, 1994, 1995, 1996
+# The Regents of the University of California. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that: (1) source code distributions
+# retain the above copyright notice and this paragraph in its entirety, (2)
+# distributions including binary code include the above copyright notice and
+# this paragraph in its entirety in the documentation or other materials
+# provided with the distribution, and (3) all advertising materials mentioning
+# features or use of this software display the following acknowledgement:
+# ``This product includes software developed by the University of California,
+# Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+# the University nor the names of its contributors may be used to endorse
+# or promote products derived from this software without specific prior
+# written permission.
+# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+#
+# @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/Makefile.in,v 1.7 2002/09/18 15:29:46 pkj Exp $ (LBL)
+
+#
+# Various configurable paths (remember to edit Makefile.in, not Makefile)
+#
+
+# Top level hierarchy
+prefix = /usr/local
+exec_prefix = ${prefix}
+# Pathname of directory to install the include files
+INCLDEST = ${prefix}/include
+# Pathname of directory to install the library
+LIBDEST = ${exec_prefix}/lib
+# Pathname of directory to install the man page
+MANDEST = ${prefix}/man
+
+# VPATH
+srcdir = .
+
+#
+# You shouldn't need to edit anything below.
+#
+CFLAGS =
+CC = gcc
+AR = ar
+INSTALL = install_elinux -p
+RANLIB = ranlib
+
+prefix =
+AXIS_USABLE_LIBS = UCLIBC GLIBC
+-include $(AXIS_TOP_DIR)/tools/build/Rules.axis
+ifndef AXIS_BUILDTYPE
+prefix = /usr/local
+endif
+
+CCOPT = -O2
+INCLS = -I. -Ilinux-include
+DEFS = -DHAVE_MALLOC_H=1 -DHAVE_ETHER_HOSTTON=1 -DHAVE_STRERROR=1 -DHAVE_NET_IF_ARP_H=1
+
+# Standard CFLAGS
+CFLAGS += $(CCOPT) $(INCLS) $(DEFS)
+
+
+#
+# Flex and bison allow you to specify the prefixes of the global symbols
+# used by the generated parser. This allows programs to use lex/yacc
+# and link against libpcap. If you don't have flex or bison, get them.
+#
+LEX = flex -Ppcap_
+YACC = bison -y -p pcap_
+
+# Explicitly define compilation rule since SunOS 4's make doesn't like gcc.
+# Also, gcc does not remove the .o before forking 'as', which can be a
+# problem if you don't own the file but can write to the directory.
+.c.o:
+ @rm -f $@
+ $(CC) $(CFLAGS) -c $(srcdir)/$*.c
+
+PSRC = pcap-linux.c
+CSRC = pcap.c inet.c gencode.c optimize.c nametoaddr.c \
+ etherent.c savefile.c bpf_filter.c bpf_image.c
+GENSRC = scanner.c grammar.c version.c
+
+SRC = $(PSRC) $(CSRC) $(GENSRC)
+
+# We would like to say "OBJ = $(SRC:.c=.o)" but Ultrix's make cannot
+# hack the extra indirection
+OBJ = $(PSRC:.c=.o) $(CSRC:.c=.o) $(GENSRC:.c=.o)
+HDR = pcap.h pcap-int.h pcap-namedb.h pcap-nit.h pcap-pf.h \
+ ethertype.h gencode.h gnuc.h
+GENHDR = \
+ tokdefs.h
+
+TAGHDR = \
+ bpf/net/bpf.h
+
+TAGFILES = \
+ $(SRC) $(HDR) $(TAGHDR)
+
+CLEANFILES = $(OBJ) libpcap.a $(GENSRC) $(GENHDR) lex.yy.c
+
+all: libpcap.a
+
+libpcap.a: $(OBJ)
+ @rm -f $@
+ $(AR) rc $@ $(OBJ)
+ $(RANLIB) $@
+
+scanner.c: $(srcdir)/scanner.l
+ @rm -f $@
+ $(LEX) -t $< > $$$$.$@; mv $$$$.$@ $@
+
+scanner.o: scanner.c tokdefs.h
+tokdefs.h: grammar.c
+grammar.c: $(srcdir)/grammar.y
+ @rm -f grammar.c tokdefs.h
+ $(YACC) -d $<
+ mv y.tab.c grammar.c
+ mv y.tab.h tokdefs.h
+
+grammar.o: grammar.c
+ @rm -f $@
+ $(CC) $(CFLAGS) -Dyylval=pcap_lval -c grammar.c
+
+version.o: version.c
+version.c: $(srcdir)/VERSION
+ @rm -f $@
+ sed -e 's/.*/char pcap_version[] = "&";/' $(srcdir)/VERSION > $@
+
+install: force
+ $(INSTALL) -m 444 -o bin -g bin libpcap.a $(DESTDIR)$(LIBDEST)/libpcap.a
+ $(RANLIB) $(DESTDIR)$(LIBDEST)/libpcap.a
+
+install-incl: force
+ $(INSTALL) -m 444 -o bin -g bin $(srcdir)/pcap.h \
+ $(DESTDIR)$(INCLDEST)/pcap.h
+ $(INSTALL) -m 444 -o bin -g bin $(srcdir)/pcap-namedb.h \
+ $(DESTDIR)$(INCLDEST)/pcap-namedb.h
+ $(INSTALL) -m 444 -o bin -g bin $(srcdir)/net/bpf.h \
+ $(DESTDIR)$(INCLDEST)/net/bpf.h
+
+install-man: force
+ $(INSTALL) -m 444 -o bin -g bin $(srcdir)/pcap.3 \
+ $(DESTDIR)$(MANDEST)/man3/pcap.3
+
+clean:
+ rm -f $(CLEANFILES)
+
+distclean:
+ rm -f $(CLEANFILES) Makefile config.cache config.log config.status \
+ gnuc.h os-proto.h bpf_filter.c net
+
+tags: $(TAGFILES)
+ ctags -wtd $(TAGFILES)
+
+tar: force
+ @cwd=`pwd` ; dir=`basename $$cwd` ; name=libpcap-`cat VERSION` ; \
+ list="" ; tar="tar chFFf" ; \
+ for i in `cat FILES` ; do list="$$list $$name/$$i" ; done; \
+ echo \
+ "rm -f ../$$name; ln -s $$dir ../$$name" ; \
+ rm -f ../$$name; ln -s $$dir ../$$name ; \
+ echo \
+ "(cd .. ; $$tar - [lots of files]) | compress > /tmp/$$name.tar.Z" ; \
+ (cd .. ; $$tar - $$list) | compress > /tmp/$$name.tar.Z ; \
+ echo \
+ "rm -f ../$$name" ; \
+ rm -f ../$$name
+
+force: /tmp
+depend: $(GENSRC) force
+ ./mkdep -c $(CC) $(DEFS) $(INCLS) $(SRC)
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile.conf b/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile.conf
new file mode 100644
index 000000000..576df5c1e
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile.conf
@@ -0,0 +1,2 @@
+conf:
+ ./configure
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile.in b/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile.in
new file mode 100644
index 000000000..8abcded86
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/Makefile.in
@@ -0,0 +1,173 @@
+# $Id: Makefile.in,v 1.7 2002/09/18 15:29:46 pkj Exp $
+# Copyright (c) 1993, 1994, 1995, 1996
+# The Regents of the University of California. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that: (1) source code distributions
+# retain the above copyright notice and this paragraph in its entirety, (2)
+# distributions including binary code include the above copyright notice and
+# this paragraph in its entirety in the documentation or other materials
+# provided with the distribution, and (3) all advertising materials mentioning
+# features or use of this software display the following acknowledgement:
+# ``This product includes software developed by the University of California,
+# Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+# the University nor the names of its contributors may be used to endorse
+# or promote products derived from this software without specific prior
+# written permission.
+# THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+# WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+#
+# @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/Makefile.in,v 1.7 2002/09/18 15:29:46 pkj Exp $ (LBL)
+
+#
+# Various configurable paths (remember to edit Makefile.in, not Makefile)
+#
+
+# Top level hierarchy
+prefix = @prefix@
+exec_prefix = @exec_prefix@
+# Pathname of directory to install the include files
+INCLDEST = @includedir@
+# Pathname of directory to install the library
+LIBDEST = @libdir@
+# Pathname of directory to install the man page
+MANDEST = @mandir@
+
+# VPATH
+srcdir = @srcdir@
+VPATH = @srcdir@
+
+#
+# You shouldn't need to edit anything below.
+#
+CFLAGS =
+CC = @CC@
+AR = ar
+INSTALL = @INSTALL@
+RANLIB = @V_RANLIB@
+
+prefix =
+AXIS_USABLE_LIBS = UCLIBC GLIBC
+-include $(AXIS_TOP_DIR)/tools/build/Rules.axis
+ifndef AXIS_BUILDTYPE
+prefix = @prefix@
+endif
+
+CCOPT = @V_CCOPT@
+INCLS = -I. @V_INCLS@
+DEFS = @DEFS@
+
+# Standard CFLAGS
+CFLAGS += $(CCOPT) $(INCLS) $(DEFS)
+
+
+#
+# Flex and bison allow you to specify the prefixes of the global symbols
+# used by the generated parser. This allows programs to use lex/yacc
+# and link against libpcap. If you don't have flex or bison, get them.
+#
+LEX = @V_LEX@
+YACC = @V_YACC@
+
+# Explicitly define compilation rule since SunOS 4's make doesn't like gcc.
+# Also, gcc does not remove the .o before forking 'as', which can be a
+# problem if you don't own the file but can write to the directory.
+.c.o:
+ @rm -f $@
+ $(CC) $(CFLAGS) -c $(srcdir)/$*.c
+
+PSRC = pcap-@V_PCAP@.c
+CSRC = pcap.c inet.c gencode.c optimize.c nametoaddr.c \
+ etherent.c savefile.c bpf_filter.c bpf_image.c
+GENSRC = scanner.c grammar.c version.c
+
+SRC = $(PSRC) $(CSRC) $(GENSRC)
+
+# We would like to say "OBJ = $(SRC:.c=.o)" but Ultrix's make cannot
+# hack the extra indirection
+OBJ = $(PSRC:.c=.o) $(CSRC:.c=.o) $(GENSRC:.c=.o)
+HDR = pcap.h pcap-int.h pcap-namedb.h pcap-nit.h pcap-pf.h \
+ ethertype.h gencode.h gnuc.h
+GENHDR = \
+ tokdefs.h
+
+TAGHDR = \
+ bpf/net/bpf.h
+
+TAGFILES = \
+ $(SRC) $(HDR) $(TAGHDR)
+
+CLEANFILES = $(OBJ) libpcap.a $(GENSRC) $(GENHDR) lex.yy.c
+
+all: libpcap.a
+
+libpcap.a: $(OBJ)
+ @rm -f $@
+ $(AR) rc $@ $(OBJ)
+ $(RANLIB) $@
+
+scanner.c: $(srcdir)/scanner.l
+ @rm -f $@
+ $(LEX) -t $< > $$$$.$@; mv $$$$.$@ $@
+
+scanner.o: scanner.c tokdefs.h
+tokdefs.h: grammar.c
+grammar.c: $(srcdir)/grammar.y
+ @rm -f grammar.c tokdefs.h
+ $(YACC) -d $<
+ mv y.tab.c grammar.c
+ mv y.tab.h tokdefs.h
+
+grammar.o: grammar.c
+ @rm -f $@
+ $(CC) $(CFLAGS) -Dyylval=pcap_lval -c grammar.c
+
+version.o: version.c
+version.c: $(srcdir)/VERSION
+ @rm -f $@
+ sed -e 's/.*/char pcap_version[] = "&";/' $(srcdir)/VERSION > $@
+
+install: force
+ $(INSTALL) -m 444 -o bin -g bin libpcap.a $(DESTDIR)$(LIBDEST)/libpcap.a
+ $(RANLIB) $(DESTDIR)$(LIBDEST)/libpcap.a
+
+install-incl: force
+ $(INSTALL) -m 444 -o bin -g bin $(srcdir)/pcap.h \
+ $(DESTDIR)$(INCLDEST)/pcap.h
+ $(INSTALL) -m 444 -o bin -g bin $(srcdir)/pcap-namedb.h \
+ $(DESTDIR)$(INCLDEST)/pcap-namedb.h
+ $(INSTALL) -m 444 -o bin -g bin $(srcdir)/net/bpf.h \
+ $(DESTDIR)$(INCLDEST)/net/bpf.h
+
+install-man: force
+ $(INSTALL) -m 444 -o bin -g bin $(srcdir)/pcap.3 \
+ $(DESTDIR)$(MANDEST)/man3/pcap.3
+
+clean:
+ rm -f $(CLEANFILES)
+
+distclean:
+ rm -f $(CLEANFILES) Makefile config.cache config.log config.status \
+ gnuc.h os-proto.h bpf_filter.c net
+
+tags: $(TAGFILES)
+ ctags -wtd $(TAGFILES)
+
+tar: force
+ @cwd=`pwd` ; dir=`basename $$cwd` ; name=libpcap-`cat VERSION` ; \
+ list="" ; tar="tar chFFf" ; \
+ for i in `cat FILES` ; do list="$$list $$name/$$i" ; done; \
+ echo \
+ "rm -f ../$$name; ln -s $$dir ../$$name" ; \
+ rm -f ../$$name; ln -s $$dir ../$$name ; \
+ echo \
+ "(cd .. ; $$tar - [lots of files]) | compress > /tmp/$$name.tar.Z" ; \
+ (cd .. ; $$tar - $$list) | compress > /tmp/$$name.tar.Z ; \
+ echo \
+ "rm -f ../$$name" ; \
+ rm -f ../$$name
+
+force: /tmp
+depend: $(GENSRC) force
+ ./mkdep -c $(CC) $(DEFS) $(INCLS) $(SRC)
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/README b/package/etrax-tools/src/e100boot/libpcap-0.4/README
new file mode 100644
index 000000000..67fce85da
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/README
@@ -0,0 +1,49 @@
+@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/README,v 1.1 1999/08/26 10:05:19 johana Exp $ (LBL)
+
+LIBPCAP 0.4
+Lawrence Berkeley National Laboratory
+Network Research Group
+libpcap@ee.lbl.gov
+ftp://ftp.ee.lbl.gov/libpcap.tar.Z
+
+This directory contains source code for libpcap, a system-independent
+interface for user-level packet capture. libpcap provides a portable
+framework for low-level network monitoring. Applications include
+network statistics collection, security monitoring, network debugging,
+etc. Since almost every system vendor provides a different interface
+for packet capture, and since we've developed several tools that
+require this functionality, we've created this system-independent API
+to ease in porting and to alleviate the need for several
+system-dependent packet capture modules in each application.
+
+Note well: this interface is new and is likely to change.
+
+The libpcap interface supports a filtering mechanism based on the
+architecture in the BSD packet filter. BPF is described in the 1993
+Winter Usenix paper ``The BSD Packet Filter: A New Architecture for
+User-level Packet Capture''. A compressed postscript version is in:
+
+ ftp://ftp.ee.lbl.gov/papers/bpf-usenix93.ps.Z.
+
+Although most packet capture interfaces support in-kernel filtering,
+libpcap utilizes in-kernel filtering only for the BPF interface.
+On systems that don't have BPF, all packets are read into user-space
+and the BPF filters are evaluated in the libpcap library, incurring
+added overhead (especially, for selective filters). Ideally, libpcap
+would translate BPF filters into a filter program that is compatible
+with the underlying kernel subsystem, but this is not yet implemented.
+
+BPF is standard in 4.4BSD, BSD/386, NetBSD, and FreeBSD. DEC OSF/1
+uses the packetfilter interface but has been extended to accept BPF
+filters (which libpcap utilizes). Also, you can add BPF filter support
+to Ultrix using the kernel source and/or object patches available in:
+
+ ftp://gatekeeper.dec.com/pub/DEC/net/bpfext42.tar.Z.
+
+Problems, bugs, questions, desirable enhancements, source code
+contributions, etc., should be sent to the email address
+"libpcap@ee.lbl.gov".
+
+ - Steve McCanne
+ Craig Leres
+ Van Jacobson
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sparc b/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sparc
new file mode 100644
index 000000000..d05073eac
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sparc
Binary files differ
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sun3 b/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sun3
new file mode 100644
index 000000000..c393fc6ec
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sun3
Binary files differ
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sun4c.4.0.3c b/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sun4c.4.0.3c
new file mode 100644
index 000000000..35df47aa6
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/SUNOS4/nit_if.o.sun4c.4.0.3c
Binary files differ
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/VERSION b/package/etrax-tools/src/e100boot/libpcap-0.4/VERSION
new file mode 100644
index 000000000..bd73f4707
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/VERSION
@@ -0,0 +1 @@
+0.4
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/aclocal.m4 b/package/etrax-tools/src/e100boot/libpcap-0.4/aclocal.m4
new file mode 100644
index 000000000..085f9fe18
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/aclocal.m4
@@ -0,0 +1,706 @@
+dnl @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/aclocal.m4,v 1.1 1999/08/26 10:05:19 johana Exp $ (LBL)
+dnl
+dnl Copyright (c) 1995, 1996, 1997, 1998
+dnl The Regents of the University of California. All rights reserved.
+dnl
+dnl Redistribution and use in source and binary forms, with or without
+dnl modification, are permitted provided that: (1) source code distributions
+dnl retain the above copyright notice and this paragraph in its entirety, (2)
+dnl distributions including binary code include the above copyright notice and
+dnl this paragraph in its entirety in the documentation or other materials
+dnl provided with the distribution, and (3) all advertising materials mentioning
+dnl features or use of this software display the following acknowledgement:
+dnl ``This product includes software developed by the University of California,
+dnl Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+dnl the University nor the names of its contributors may be used to endorse
+dnl or promote products derived from this software without specific prior
+dnl written permission.
+dnl THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+dnl WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+dnl MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+dnl
+dnl LBL autoconf macros
+dnl
+
+dnl
+dnl Determine which compiler we're using (cc or gcc)
+dnl If using gcc, determine the version number
+dnl If using cc, require that it support ansi prototypes
+dnl If using gcc, use -O2 (otherwise use -O)
+dnl If using cc, explicitly specify /usr/local/include
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_C_INIT(copt, incls)
+dnl
+dnl results:
+dnl
+dnl $1 (copt set)
+dnl $2 (incls set)
+dnl CC
+dnl LDFLAGS
+dnl ac_cv_lbl_gcc_vers
+dnl LBL_CFLAGS
+dnl
+AC_DEFUN(AC_LBL_C_INIT,
+ [AC_PREREQ(2.12)
+ AC_BEFORE([$0], [AC_PROG_CC])
+ AC_BEFORE([$0], [AC_LBL_FIXINCLUDES])
+ AC_BEFORE([$0], [AC_LBL_DEVEL])
+ AC_ARG_WITH(gcc, [ --without-gcc don't use gcc])
+ $1="-O"
+ $2=""
+ if test "${srcdir}" != "." ; then
+ $2="-I\$\(srcdir\)"
+ fi
+ if test "${CFLAGS+set}" = set; then
+ LBL_CFLAGS="$CFLAGS"
+ fi
+ if test -z "$CC" ; then
+ case "$target_os" in
+
+ bsdi*)
+ AC_CHECK_PROG(SHLICC2, shlicc2, yes, no)
+ if test $SHLICC2 = yes ; then
+ CC=shlicc2
+ export CC
+ fi
+ ;;
+ esac
+ fi
+ if test -z "$CC" -a "$with_gcc" = no ; then
+ CC=cc
+ export CC
+ fi
+ AC_PROG_CC
+ if test "$GCC" = yes ; then
+ if test "$SHLICC2" = yes ; then
+ ac_cv_lbl_gcc_vers=2
+ $1="-O2"
+ else
+ AC_MSG_CHECKING(gcc version)
+ AC_CACHE_VAL(ac_cv_lbl_gcc_vers,
+ ac_cv_lbl_gcc_vers=`$CC -v 2>&1 | \
+ sed -e '/^gcc version /!d' \
+ -e 's/^gcc version //' \
+ -e 's/ .*//' -e 's/^[[[^0-9]]]*//' \
+ -e 's/\..*//'`)
+ AC_MSG_RESULT($ac_cv_lbl_gcc_vers)
+ if test $ac_cv_lbl_gcc_vers -gt 1 ; then
+ $1="-O2"
+ fi
+ fi
+ else
+ AC_MSG_CHECKING(that $CC handles ansi prototypes)
+ AC_CACHE_VAL(ac_cv_lbl_cc_ansi_prototypes,
+ AC_TRY_COMPILE(
+ [#include <sys/types.h>],
+ [int frob(int, char *)],
+ ac_cv_lbl_cc_ansi_prototypes=yes,
+ ac_cv_lbl_cc_ansi_prototypes=no))
+ AC_MSG_RESULT($ac_cv_lbl_cc_ansi_prototypes)
+ if test $ac_cv_lbl_cc_ansi_prototypes = no ; then
+ case "$target_os" in
+
+ hpux*)
+ AC_MSG_CHECKING(for HP-UX ansi compiler ($CC -Aa -D_HPUX_SOURCE))
+ savedcflags="$CFLAGS"
+ CFLAGS="-Aa -D_HPUX_SOURCE $CFLAGS"
+ AC_CACHE_VAL(ac_cv_lbl_cc_hpux_cc_aa,
+ AC_TRY_COMPILE(
+ [#include <sys/types.h>],
+ [int frob(int, char *)],
+ ac_cv_lbl_cc_hpux_cc_aa=yes,
+ ac_cv_lbl_cc_hpux_cc_aa=no))
+ AC_MSG_RESULT($ac_cv_lbl_cc_hpux_cc_aa)
+ if test $ac_cv_lbl_cc_hpux_cc_aa = no ; then
+ AC_MSG_ERROR(see the INSTALL doc for more info)
+ fi
+ CFLAGS="$savedcflags"
+ V_CCOPT="-Aa $V_CCOPT"
+ AC_DEFINE(_HPUX_SOURCE)
+ ;;
+
+ *)
+ AC_MSG_ERROR(see the INSTALL doc for more info)
+ ;;
+ esac
+ fi
+ $2="$$2 -I/usr/local/include"
+ LDFLAGS="$LDFLAGS -L/usr/local/lib"
+
+ case "$target_os" in
+
+ irix*)
+ V_CCOPT="$V_CCOPT -xansi -signed -g3"
+ ;;
+
+ osf*)
+ V_CCOPT="$V_CCOPT -std1 -g3"
+ ;;
+
+ ultrix*)
+ AC_MSG_CHECKING(that Ultrix $CC hacks const in prototypes)
+ AC_CACHE_VAL(ac_cv_lbl_cc_const_proto,
+ AC_TRY_COMPILE(
+ [#include <sys/types.h>],
+ [struct a { int b; };
+ void c(const struct a *)],
+ ac_cv_lbl_cc_const_proto=yes,
+ ac_cv_lbl_cc_const_proto=no))
+ AC_MSG_RESULT($ac_cv_lbl_cc_const_proto)
+ if test $ac_cv_lbl_cc_const_proto = no ; then
+ AC_DEFINE(const,)
+ fi
+ ;;
+ esac
+ fi
+])
+
+dnl
+dnl Use pfopen.c if available and pfopen() not in standard libraries
+dnl Require libpcap
+dnl Look for libpcap in ..
+dnl Use the installed libpcap if there is no local version
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_LIBPCAP(pcapdep, incls)
+dnl
+dnl results:
+dnl
+dnl $1 (pcapdep set)
+dnl $2 (incls appended)
+dnl LIBS
+dnl LBL_LIBS
+dnl
+AC_DEFUN(AC_LBL_LIBPCAP,
+ [AC_REQUIRE([AC_LBL_LIBRARY_NET])
+ dnl
+ dnl save a copy before locating libpcap.a
+ dnl
+ LBL_LIBS="$LIBS"
+ pfopen=/usr/examples/packetfilter/pfopen.c
+ if test -f $pfopen ; then
+ AC_CHECK_FUNCS(pfopen)
+ if test $ac_cv_func_pfopen = "no" ; then
+ AC_MSG_RESULT(Using $pfopen)
+ LIBS="$LIBS $pfopen"
+ fi
+ fi
+ AC_MSG_CHECKING(for local pcap library)
+ libpcap=FAIL
+ lastdir=FAIL
+ places=`ls .. | sed -e 's,/$,,' -e 's,^,../,' | \
+ egrep '/libpcap-[[0-9]]*\.[[0-9]]*(\.[[0-9]]*)?([[ab]][[0-9]]*)?$'`
+ for dir in $places ../libpcap libpcap ; do
+ basedir=`echo $dir | sed -e 's/[[ab]][[0-9]]*$//'`
+ if test $lastdir = $basedir ; then
+ dnl skip alphas when an actual release is present
+ continue;
+ fi
+ lastdir=$dir
+ if test -r $dir/pcap.c ; then
+ libpcap=$dir/libpcap.a
+ d=$dir
+ dnl continue and select the last one that exists
+ fi
+ done
+ if test $libpcap = FAIL ; then
+ AC_MSG_RESULT(not found)
+ AC_CHECK_LIB(pcap, main, libpcap="-lpcap")
+ if test $libpcap = FAIL ; then
+ AC_MSG_ERROR(see the INSTALL doc for more info)
+ fi
+ else
+ $1=$libpcap
+ $2="-I$d $$2"
+ AC_MSG_RESULT($libpcap)
+ fi
+ LIBS="$libpcap $LIBS"
+ case "$target_os" in
+
+ aix*)
+ pseexe="/lib/pse.exp"
+ AC_MSG_CHECKING(for $pseexe)
+ if test -f $pseexe ; then
+ AC_MSG_RESULT(yes)
+ LIBS="$LIBS -I:$pseexe"
+ fi
+ ;;
+ esac])
+
+dnl
+dnl Define RETSIGTYPE and RETSIGVAL
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_TYPE_SIGNAL
+dnl
+dnl results:
+dnl
+dnl RETSIGTYPE (defined)
+dnl RETSIGVAL (defined)
+dnl
+AC_DEFUN(AC_LBL_TYPE_SIGNAL,
+ [AC_BEFORE([$0], [AC_LBL_LIBPCAP])
+ AC_TYPE_SIGNAL
+ if test "$ac_cv_type_signal" = void ; then
+ AC_DEFINE(RETSIGVAL,)
+ else
+ AC_DEFINE(RETSIGVAL,(0))
+ fi
+ case "$target_os" in
+
+ irix*)
+ AC_DEFINE(_BSD_SIGNALS)
+ ;;
+
+ *)
+ dnl prefer sigset() to sigaction()
+ AC_CHECK_FUNCS(sigset)
+ if test $ac_cv_func_sigset = no ; then
+ AC_CHECK_FUNCS(sigaction)
+ fi
+ ;;
+ esac])
+
+dnl
+dnl If using gcc, make sure we have ANSI ioctl definitions
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_FIXINCLUDES
+dnl
+AC_DEFUN(AC_LBL_FIXINCLUDES,
+ [if test "$GCC" = yes ; then
+ AC_MSG_CHECKING(for ANSI ioctl definitions)
+ AC_CACHE_VAL(ac_cv_lbl_gcc_fixincludes,
+ AC_TRY_COMPILE(
+ [/*
+ * This generates a "duplicate case value" when fixincludes
+ * has not be run.
+ */
+# include <sys/types.h>
+# include <sys/time.h>
+# include <sys/ioctl.h>
+# ifdef HAVE_SYS_IOCCOM_H
+# include <sys/ioccom.h>
+# endif],
+ [switch (0) {
+ case _IO('A', 1):;
+ case _IO('B', 1):;
+ }],
+ ac_cv_lbl_gcc_fixincludes=yes,
+ ac_cv_lbl_gcc_fixincludes=no))
+ AC_MSG_RESULT($ac_cv_lbl_gcc_fixincludes)
+ if test $ac_cv_lbl_gcc_fixincludes = no ; then
+ # Don't cache failure
+ unset ac_cv_lbl_gcc_fixincludes
+ AC_MSG_ERROR(see the INSTALL for more info)
+ fi
+ fi])
+
+dnl
+dnl Check for flex, default to lex
+dnl Require flex 2.4 or higher
+dnl Check for bison, default to yacc
+dnl Default to lex/yacc if both flex and bison are not available
+dnl Define the yy prefix string if using flex and bison
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_LEX_AND_YACC(lex, yacc, yyprefix)
+dnl
+dnl results:
+dnl
+dnl $1 (lex set)
+dnl $2 (yacc appended)
+dnl $3 (optional flex and bison -P prefix)
+dnl
+AC_DEFUN(AC_LBL_LEX_AND_YACC,
+ [AC_ARG_WITH(flex, [ --without-flex don't use flex])
+ AC_ARG_WITH(bison, [ --without-bison don't use bison])
+ if test "$with_flex" = no ; then
+ $1=lex
+ else
+ AC_CHECK_PROGS($1, flex, lex)
+ fi
+ if test "$$1" = flex ; then
+ # The -V flag was added in 2.4
+ AC_MSG_CHECKING(for flex 2.4 or higher)
+ AC_CACHE_VAL(ac_cv_lbl_flex_v24,
+ if flex -V >/dev/null 2>&1; then
+ ac_cv_lbl_flex_v24=yes
+ else
+ ac_cv_lbl_flex_v24=no
+ fi)
+ AC_MSG_RESULT($ac_cv_lbl_flex_v24)
+ if test $ac_cv_lbl_flex_v24 = no ; then
+ s="2.4 or higher required"
+ AC_MSG_WARN(ignoring obsolete flex executable ($s))
+ $1=lex
+ fi
+ fi
+ if test "$with_bison" = no ; then
+ $2=yacc
+ else
+ AC_CHECK_PROGS($2, bison, yacc)
+ fi
+ if test "$$2" = bison ; then
+ $2="$$2 -y"
+ fi
+ if test "$$1" != lex -a "$$2" = yacc -o "$$1" = lex -a "$$2" != yacc ; then
+ AC_MSG_WARN(don't have both flex and bison; reverting to lex/yacc)
+ $1=lex
+ $2=yacc
+ fi
+ if test "$$1" = flex -a -n "$3" ; then
+ $1="$$1 -P$3"
+ $2="$$2 -p $3"
+ fi])
+
+dnl
+dnl Checks to see if union wait is used with WEXITSTATUS()
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_UNION_WAIT
+dnl
+dnl results:
+dnl
+dnl DECLWAITSTATUS (defined)
+dnl
+AC_DEFUN(AC_LBL_UNION_WAIT,
+ [AC_MSG_CHECKING(if union wait is used)
+ AC_CACHE_VAL(ac_cv_lbl_union_wait,
+ AC_TRY_COMPILE([
+# include <sys/types.h>
+# include <sys/wait.h>],
+ [int status;
+ u_int i = WEXITSTATUS(status);
+ u_int j = waitpid(0, &status, 0);],
+ ac_cv_lbl_union_wait=no,
+ ac_cv_lbl_union_wait=yes))
+ AC_MSG_RESULT($ac_cv_lbl_union_wait)
+ if test $ac_cv_lbl_union_wait = yes ; then
+ AC_DEFINE(DECLWAITSTATUS,union wait)
+ else
+ AC_DEFINE(DECLWAITSTATUS,int)
+ fi])
+
+dnl
+dnl Checks to see if the sockaddr struct has the 4.4 BSD sa_len member
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_SOCKADDR_SA_LEN
+dnl
+dnl results:
+dnl
+dnl HAVE_SOCKADDR_SA_LEN (defined)
+dnl
+AC_DEFUN(AC_LBL_SOCKADDR_SA_LEN,
+ [AC_MSG_CHECKING(if sockaddr struct has sa_len member)
+ AC_CACHE_VAL(ac_cv_lbl_sockaddr_has_sa_len,
+ AC_TRY_COMPILE([
+# include <sys/types.h>
+# include <sys/socket.h>],
+ [u_int i = sizeof(((struct sockaddr *)0)->sa_len)],
+ ac_cv_lbl_sockaddr_has_sa_len=yes,
+ ac_cv_lbl_sockaddr_has_sa_len=no))
+ AC_MSG_RESULT($ac_cv_lbl_sockaddr_has_sa_len)
+ if test $ac_cv_lbl_sockaddr_has_sa_len = yes ; then
+ AC_DEFINE(HAVE_SOCKADDR_SA_LEN)
+ fi])
+
+dnl
+dnl Checks to see if -R is used
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_HAVE_RUN_PATH
+dnl
+dnl results:
+dnl
+dnl ac_cv_lbl_have_run_path (yes or no)
+dnl
+AC_DEFUN(AC_LBL_HAVE_RUN_PATH,
+ [AC_MSG_CHECKING(for ${CC-cc} -R)
+ AC_CACHE_VAL(ac_cv_lbl_have_run_path,
+ [echo 'main(){}' > conftest.c
+ ${CC-cc} -o conftest conftest.c -R/a1/b2/c3 >conftest.out 2>&1
+ if test ! -s conftest.out ; then
+ ac_cv_lbl_have_run_path=yes
+ else
+ ac_cv_lbl_have_run_path=no
+ fi
+ rm -f conftest*])
+ AC_MSG_RESULT($ac_cv_lbl_have_run_path)
+ ])
+
+dnl
+dnl Due to the stupid way it's implemented, AC_CHECK_TYPE is nearly useless.
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_CHECK_TYPE
+dnl
+dnl results:
+dnl
+dnl int32_t (defined)
+dnl u_int32_t (defined)
+dnl
+AC_DEFUN(AC_LBL_CHECK_TYPE,
+ [AC_MSG_CHECKING(for $1 using $CC)
+ AC_CACHE_VAL(ac_cv_lbl_have_$1,
+ AC_TRY_COMPILE([
+# include "confdefs.h"
+# include <sys/types.h>
+# if STDC_HEADERS
+# include <stdlib.h>
+# include <stddef.h>
+# endif],
+ [$1 i],
+ ac_cv_lbl_have_$1=yes,
+ ac_cv_lbl_have_$1=no))
+ AC_MSG_RESULT($ac_cv_lbl_have_$1)
+ if test $ac_cv_lbl_have_$1 = no ; then
+ AC_DEFINE($1, $2)
+ fi])
+
+dnl
+dnl Checks to see if unaligned memory accesses fail
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_UNALIGNED_ACCESS
+dnl
+dnl results:
+dnl
+dnl LBL_ALIGN (DEFINED)
+dnl
+AC_DEFUN(AC_LBL_UNALIGNED_ACCESS,
+ [AC_MSG_CHECKING(if unaligned accesses fail)
+ AC_CACHE_VAL(ac_cv_lbl_unaligned_fail,
+ [case "$target_cpu" in
+
+ alpha|hp*|mips|sparc)
+ ac_cv_lbl_unaligned_fail=yes
+ ;;
+
+ *)
+ cat >conftest.c <<EOF
+# include <sys/types.h>
+# include <sys/wait.h>
+# include <stdio.h>
+ unsigned char a[[5]] = { 1, 2, 3, 4, 5 };
+ main() {
+ unsigned int i;
+ pid_t pid;
+ int status;
+ /* avoid "core dumped" message */
+ pid = fork();
+ if (pid < 0)
+ exit(2);
+ if (pid > 0) {
+ /* parent */
+ pid = waitpid(pid, &status, 0);
+ if (pid < 0)
+ exit(3);
+ exit(!WIFEXITED(status));
+ }
+ /* child */
+ i = *(unsigned int *)&a[[1]];
+ printf("%d\n", i);
+ exit(0);
+ }
+EOF
+ ${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS \
+ conftest.c $LIBS >/dev/null 2>&1
+ if test ! -x conftest ; then
+ dnl failed to compile for some reason
+ ac_cv_lbl_unaligned_fail=yes
+ else
+ ./conftest >conftest.out
+ if test ! -s conftest.out ; then
+ ac_cv_lbl_unaligned_fail=yes
+ else
+ ac_cv_lbl_unaligned_fail=no
+ fi
+ fi
+ rm -f conftest* core core.conftest
+ ;;
+ esac])
+ AC_MSG_RESULT($ac_cv_lbl_unaligned_fail)
+ if test $ac_cv_lbl_unaligned_fail = yes ; then
+ AC_DEFINE(LBL_ALIGN)
+ fi])
+
+dnl
+dnl If using gcc and the file .devel exists:
+dnl Compile with -g (if supported) and -Wall
+dnl If using gcc 2, do extra prototype checking
+dnl If an os prototype include exists, symlink os-proto.h to it
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_DEVEL(copt)
+dnl
+dnl results:
+dnl
+dnl $1 (copt appended)
+dnl HAVE_OS_PROTO_H (defined)
+dnl os-proto.h (symlinked)
+dnl
+AC_DEFUN(AC_LBL_DEVEL,
+ [rm -f os-proto.h
+ if test "${LBL_CFLAGS+set}" = set; then
+ $1="$$1 ${LBL_CFLAGS}"
+ fi
+ if test -f .devel ; then
+ if test "$GCC" = yes ; then
+ if test "${LBL_CFLAGS+set}" != set; then
+ if test "$ac_cv_prog_cc_g" = yes ; then
+ $1="-g $$1"
+ fi
+ $1="$$1 -Wall"
+ if test $ac_cv_lbl_gcc_vers -gt 1 ; then
+ $1="$$1 -Wmissing-prototypes -Wstrict-prototypes"
+ fi
+ fi
+ else
+ case "$target_os" in
+
+ irix6*)
+ V_CCOPT="$V_CCOPT -n32"
+ ;;
+
+ *)
+ ;;
+ esac
+ fi
+ os=`echo $target_os | sed -e 's/\([[0-9]][[0-9]]*\)[[^0-9]].*$/\1/'`
+ name="lbl/os-$os.h"
+ if test -f $name ; then
+ ln -s $name os-proto.h
+ AC_DEFINE(HAVE_OS_PROTO_H)
+ else
+ AC_MSG_WARN(can't find $name)
+ fi
+ fi])
+
+dnl
+dnl Improved version of AC_CHECK_LIB
+dnl
+dnl Thanks to John Hawkinson (jhawk@mit.edu)
+dnl
+dnl usage:
+dnl
+dnl AC_LBL_CHECK_LIB(LIBRARY, FUNCTION [, ACTION-IF-FOUND [,
+dnl ACTION-IF-NOT-FOUND [, OTHER-LIBRARIES]]])
+dnl
+dnl results:
+dnl
+dnl LIBS
+dnl
+
+define(AC_LBL_CHECK_LIB,
+[AC_MSG_CHECKING([for $2 in -l$1])
+dnl Use a cache variable name containing both the library and function name,
+dnl because the test really is for library $1 defining function $2, not
+dnl just for library $1. Separate tests with the same $1 and different $2's
+dnl may have different results.
+ac_lib_var=`echo $1['_']$2['_']$5 | sed 'y%./+- %__p__%'`
+AC_CACHE_VAL(ac_cv_lbl_lib_$ac_lib_var,
+[ac_save_LIBS="$LIBS"
+LIBS="-l$1 $5 $LIBS"
+AC_TRY_LINK(dnl
+ifelse([$2], [main], , dnl Avoid conflicting decl of main.
+[/* Override any gcc2 internal prototype to avoid an error. */
+]ifelse(AC_LANG, CPLUSPLUS, [#ifdef __cplusplus
+extern "C"
+#endif
+])dnl
+[/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $2();
+]),
+ [$2()],
+ eval "ac_cv_lbl_lib_$ac_lib_var=yes",
+ eval "ac_cv_lbl_lib_$ac_lib_var=no")
+LIBS="$ac_save_LIBS"
+])dnl
+if eval "test \"`echo '$ac_cv_lbl_lib_'$ac_lib_var`\" = yes"; then
+ AC_MSG_RESULT(yes)
+ ifelse([$3], ,
+[changequote(, )dnl
+ ac_tr_lib=HAVE_LIB`echo $1 | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+ -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+changequote([, ])dnl
+ AC_DEFINE_UNQUOTED($ac_tr_lib)
+ LIBS="-l$1 $LIBS"
+], [$3])
+else
+ AC_MSG_RESULT(no)
+ifelse([$4], , , [$4
+])dnl
+fi
+])
+
+dnl
+dnl AC_LBL_LIBRARY_NET
+dnl
+dnl This test is for network applications that need socket() and
+dnl gethostbyname() -ish functions. Under Solaris, those applications
+dnl need to link with "-lsocket -lnsl". Under IRIX, they need to link
+dnl with "-lnsl" but should *not* link with "-lsocket" because
+dnl libsocket.a breaks a number of things (for instance:
+dnl gethostbyname() under IRIX 5.2, and snoop sockets under most
+dnl versions of IRIX).
+dnl
+dnl Unfortunately, many application developers are not aware of this,
+dnl and mistakenly write tests that cause -lsocket to be used under
+dnl IRIX. It is also easy to write tests that cause -lnsl to be used
+dnl under operating systems where neither are necessary (or useful),
+dnl such as SunOS 4.1.4, which uses -lnsl for TLI.
+dnl
+dnl This test exists so that every application developer does not test
+dnl this in a different, and subtly broken fashion.
+
+dnl It has been argued that this test should be broken up into two
+dnl seperate tests, one for the resolver libraries, and one for the
+dnl libraries necessary for using Sockets API. Unfortunately, the two
+dnl are carefully intertwined and allowing the autoconf user to use
+dnl them independantly potentially results in unfortunate ordering
+dnl dependancies -- as such, such component macros would have to
+dnl carefully use indirection and be aware if the other components were
+dnl executed. Since other autoconf macros do not go to this trouble,
+dnl and almost no applications use sockets without the resolver, this
+dnl complexity has not been implemented.
+dnl
+dnl The check for libresolv is in case you are attempting to link
+dnl statically and happen to have a libresolv.a lying around (and no
+dnl libnsl.a).
+dnl
+AC_DEFUN(AC_LBL_LIBRARY_NET, [
+ # Most operating systems have gethostbyname() in the default searched
+ # libraries (i.e. libc):
+ AC_CHECK_FUNC(gethostbyname, ,
+ # Some OSes (eg. Solaris) place it in libnsl:
+ AC_LBL_CHECK_LIB(nsl, gethostbyname, ,
+ # Some strange OSes (SINIX) have it in libsocket:
+ AC_LBL_CHECK_LIB(socket, gethostbyname, ,
+ # Unfortunately libsocket sometimes depends on libnsl.
+ # AC_CHECK_LIB's API is essentially broken so the
+ # following ugliness is necessary:
+ AC_LBL_CHECK_LIB(socket, gethostbyname,
+ LIBS="-lsocket -lnsl $LIBS",
+ AC_CHECK_LIB(resolv, gethostbyname),
+ -lnsl))))
+ AC_CHECK_FUNC(socket, , AC_CHECK_LIB(socket, socket, ,
+ AC_LBL_CHECK_LIB(socket, socket, LIBS="-lsocket -lnsl $LIBS", ,
+ -lnsl)))
+ # DLPI needs putmsg under HPUX so test for -lstr while we're at it
+ AC_CHECK_LIB(str, putmsg)
+ ])
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/bpf/net/bpf.h b/package/etrax-tools/src/e100boot/libpcap-0.4/bpf/net/bpf.h
new file mode 100644
index 000000000..9ff7ab704
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/bpf/net/bpf.h
@@ -0,0 +1,264 @@
+/*-
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from the Stanford/CMU enet packet filter,
+ * (net/enet.c) distributed as part of 4.3BSD, and code contributed
+ * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence
+ * Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)bpf.h 7.1 (Berkeley) 5/7/91
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/bpf/net/bpf.h,v 1.1 1999/08/26 10:07:57 johana Exp $ (LBL)
+ */
+
+#ifndef BPF_MAJOR_VERSION
+
+/* BSD style release date */
+#define BPF_RELEASE 199606
+
+typedef int bpf_int32;
+typedef u_int bpf_u_int32;
+
+/*
+ * Alignment macros. BPF_WORDALIGN rounds up to the next
+ * even multiple of BPF_ALIGNMENT.
+ */
+#define BPF_ALIGNMENT sizeof(bpf_int32)
+#define BPF_WORDALIGN(x) (((x)+(BPF_ALIGNMENT-1))&~(BPF_ALIGNMENT-1))
+
+#define BPF_MAXINSNS 512
+#define BPF_MAXBUFSIZE 0x8000
+#define BPF_MINBUFSIZE 32
+
+/*
+ * Structure for BIOCSETF.
+ */
+struct bpf_program {
+ u_int bf_len;
+ struct bpf_insn *bf_insns;
+};
+
+/*
+ * Struct returned by BIOCGSTATS.
+ */
+struct bpf_stat {
+ u_int bs_recv; /* number of packets received */
+ u_int bs_drop; /* number of packets dropped */
+};
+
+/*
+ * Struct return by BIOCVERSION. This represents the version number of
+ * the filter language described by the instruction encodings below.
+ * bpf understands a program iff kernel_major == filter_major &&
+ * kernel_minor >= filter_minor, that is, if the value returned by the
+ * running kernel has the same major number and a minor number equal
+ * equal to or less than the filter being downloaded. Otherwise, the
+ * results are undefined, meaning an error may be returned or packets
+ * may be accepted haphazardly.
+ * It has nothing to do with the source code version.
+ */
+struct bpf_version {
+ u_short bv_major;
+ u_short bv_minor;
+};
+/* Current version number of filter architecture. */
+#define BPF_MAJOR_VERSION 1
+#define BPF_MINOR_VERSION 1
+
+/*
+ * BPF ioctls
+ *
+ * The first set is for compatibility with Sun's pcc style
+ * header files. If your using gcc, we assume that you
+ * have run fixincludes so the latter set should work.
+ */
+#if (defined(sun) || defined(ibm032)) && !defined(__GNUC__)
+#define BIOCGBLEN _IOR(B,102, u_int)
+#define BIOCSBLEN _IOWR(B,102, u_int)
+#define BIOCSETF _IOW(B,103, struct bpf_program)
+#define BIOCFLUSH _IO(B,104)
+#define BIOCPROMISC _IO(B,105)
+#define BIOCGDLT _IOR(B,106, u_int)
+#define BIOCGETIF _IOR(B,107, struct ifreq)
+#define BIOCSETIF _IOW(B,108, struct ifreq)
+#define BIOCSRTIMEOUT _IOW(B,109, struct timeval)
+#define BIOCGRTIMEOUT _IOR(B,110, struct timeval)
+#define BIOCGSTATS _IOR(B,111, struct bpf_stat)
+#define BIOCIMMEDIATE _IOW(B,112, u_int)
+#define BIOCVERSION _IOR(B,113, struct bpf_version)
+#define BIOCSTCPF _IOW(B,114, struct bpf_program)
+#define BIOCSUDPF _IOW(B,115, struct bpf_program)
+#else
+#define BIOCGBLEN _IOR('B',102, u_int)
+#define BIOCSBLEN _IOWR('B',102, u_int)
+#define BIOCSETF _IOW('B',103, struct bpf_program)
+#define BIOCFLUSH _IO('B',104)
+#define BIOCPROMISC _IO('B',105)
+#define BIOCGDLT _IOR('B',106, u_int)
+#define BIOCGETIF _IOR('B',107, struct ifreq)
+#define BIOCSETIF _IOW('B',108, struct ifreq)
+#define BIOCSRTIMEOUT _IOW('B',109, struct timeval)
+#define BIOCGRTIMEOUT _IOR('B',110, struct timeval)
+#define BIOCGSTATS _IOR('B',111, struct bpf_stat)
+#define BIOCIMMEDIATE _IOW('B',112, u_int)
+#define BIOCVERSION _IOR('B',113, struct bpf_version)
+#define BIOCSTCPF _IOW('B',114, struct bpf_program)
+#define BIOCSUDPF _IOW('B',115, struct bpf_program)
+#endif
+
+/*
+ * Structure prepended to each packet.
+ */
+struct bpf_hdr {
+ struct timeval bh_tstamp; /* time stamp */
+ bpf_u_int32 bh_caplen; /* length of captured portion */
+ bpf_u_int32 bh_datalen; /* original length of packet */
+ u_short bh_hdrlen; /* length of bpf header (this struct
+ plus alignment padding) */
+};
+/*
+ * Because the structure above is not a multiple of 4 bytes, some compilers
+ * will insist on inserting padding; hence, sizeof(struct bpf_hdr) won't work.
+ * Only the kernel needs to know about it; applications use bh_hdrlen.
+ */
+#ifdef KERNEL
+#define SIZEOF_BPF_HDR 18
+#endif
+
+/*
+ * Data-link level type codes.
+ */
+#define DLT_NULL 0 /* no link-layer encapsulation */
+#define DLT_EN10MB 1 /* Ethernet (10Mb) */
+#define DLT_EN3MB 2 /* Experimental Ethernet (3Mb) */
+#define DLT_AX25 3 /* Amateur Radio AX.25 */
+#define DLT_PRONET 4 /* Proteon ProNET Token Ring */
+#define DLT_CHAOS 5 /* Chaos */
+#define DLT_IEEE802 6 /* IEEE 802 Networks */
+#define DLT_ARCNET 7 /* ARCNET */
+#define DLT_SLIP 8 /* Serial Line IP */
+#define DLT_PPP 9 /* Point-to-point Protocol */
+#define DLT_FDDI 10 /* FDDI */
+#define DLT_ATM_RFC1483 11 /* LLC/SNAP encapsulated atm */
+#define DLT_RAW 12 /* raw IP */
+#define DLT_SLIP_BSDOS 13 /* BSD/OS Serial Line IP */
+#define DLT_PPP_BSDOS 14 /* BSD/OS Point-to-point Protocol */
+
+/*
+ * The instruction encondings.
+ */
+/* instruction classes */
+#define BPF_CLASS(code) ((code) & 0x07)
+#define BPF_LD 0x00
+#define BPF_LDX 0x01
+#define BPF_ST 0x02
+#define BPF_STX 0x03
+#define BPF_ALU 0x04
+#define BPF_JMP 0x05
+#define BPF_RET 0x06
+#define BPF_MISC 0x07
+
+/* ld/ldx fields */
+#define BPF_SIZE(code) ((code) & 0x18)
+#define BPF_W 0x00
+#define BPF_H 0x08
+#define BPF_B 0x10
+#define BPF_MODE(code) ((code) & 0xe0)
+#define BPF_IMM 0x00
+#define BPF_ABS 0x20
+#define BPF_IND 0x40
+#define BPF_MEM 0x60
+#define BPF_LEN 0x80
+#define BPF_MSH 0xa0
+
+/* alu/jmp fields */
+#define BPF_OP(code) ((code) & 0xf0)
+#define BPF_ADD 0x00
+#define BPF_SUB 0x10
+#define BPF_MUL 0x20
+#define BPF_DIV 0x30
+#define BPF_OR 0x40
+#define BPF_AND 0x50
+#define BPF_LSH 0x60
+#define BPF_RSH 0x70
+#define BPF_NEG 0x80
+#define BPF_JA 0x00
+#define BPF_JEQ 0x10
+#define BPF_JGT 0x20
+#define BPF_JGE 0x30
+#define BPF_JSET 0x40
+#define BPF_SRC(code) ((code) & 0x08)
+#define BPF_K 0x00
+#define BPF_X 0x08
+
+/* ret - BPF_K and BPF_X also apply */
+#define BPF_RVAL(code) ((code) & 0x18)
+#define BPF_A 0x10
+
+/* misc */
+#define BPF_MISCOP(code) ((code) & 0xf8)
+#define BPF_TAX 0x00
+#define BPF_TXA 0x80
+
+/*
+ * The instruction data structure.
+ */
+struct bpf_insn {
+ u_short code;
+ u_char jt;
+ u_char jf;
+ bpf_int32 k;
+};
+
+/*
+ * Macros for insn array initializers.
+ */
+#define BPF_STMT(code, k) { (u_short)(code), 0, 0, k }
+#define BPF_JUMP(code, k, jt, jf) { (u_short)(code), jt, jf, k }
+
+#ifdef KERNEL
+extern u_int bpf_filter();
+extern void bpfattach();
+extern void bpf_tap();
+extern void bpf_mtap();
+#else
+#if __STDC__
+extern u_int bpf_filter(struct bpf_insn *, u_char *, u_int, u_int);
+#endif
+#endif
+
+/*
+ * Number of scratch memory words (for BPF_LD|BPF_MEM and BPF_ST).
+ */
+#define BPF_MEMWORDS 16
+
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/bpf/net/bpf_filter.c b/package/etrax-tools/src/e100boot/libpcap-0.4/bpf/net/bpf_filter.c
new file mode 100644
index 000000000..d3dcc689a
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/bpf/net/bpf_filter.c
@@ -0,0 +1,532 @@
+/*-
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * This code is derived from the Stanford/CMU enet packet filter,
+ * (net/enet.c) distributed as part of 4.3BSD, and code contributed
+ * to Berkeley by Steven McCanne and Van Jacobson both of Lawrence
+ * Berkeley Laboratory.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)bpf.c 7.5 (Berkeley) 7/15/91
+ */
+
+#if !(defined(lint) || defined(KERNEL))
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/bpf/net/bpf_filter.c,v 1.1 1999/08/26 10:07:57 johana Exp $ (LBL)";
+#endif
+
+#include <sys/param.h>
+#include <sys/types.h>
+#include <sys/time.h>
+#include <net/bpf.h>
+
+#ifndef KERNEL
+#include <stdlib.h>
+#endif
+
+#define int32 bpf_int32
+#define u_int32 bpf_u_int32
+
+#ifndef LBL_ALIGN
+#if defined(sparc) || defined(mips) || defined(ibm032) || \
+ defined(__alpha) || defined(__hpux)
+#define LBL_ALIGN
+#endif
+#endif
+
+#ifndef LBL_ALIGN
+#include <netinet/in.h>
+
+#define EXTRACT_SHORT(p) ((u_short)ntohs(*(u_short *)p))
+#define EXTRACT_LONG(p) (ntohl(*(u_int32 *)p))
+#else
+#define EXTRACT_SHORT(p)\
+ ((u_short)\
+ ((u_short)*((u_char *)p+0)<<8|\
+ (u_short)*((u_char *)p+1)<<0))
+#define EXTRACT_LONG(p)\
+ ((u_int32)*((u_char *)p+0)<<24|\
+ (u_int32)*((u_char *)p+1)<<16|\
+ (u_int32)*((u_char *)p+2)<<8|\
+ (u_int32)*((u_char *)p+3)<<0)
+#endif
+
+#ifdef KERNEL
+#include <sys/mbuf.h>
+#define MINDEX(len, m, k) \
+{ \
+ len = m->m_len; \
+ while (k >= len) { \
+ k -= len; \
+ m = m->m_next; \
+ if (m == 0) \
+ return 0; \
+ len = m->m_len; \
+ } \
+}
+
+static int
+m_xword(m, k, err)
+ register struct mbuf *m;
+ register int k, *err;
+{
+ register int len;
+ register u_char *cp, *np;
+ register struct mbuf *m0;
+
+ MINDEX(len, m, k);
+ cp = mtod(m, u_char *) + k;
+ if (len - k >= 4) {
+ *err = 0;
+ return EXTRACT_LONG(cp);
+ }
+ m0 = m->m_next;
+ if (m0 == 0 || m0->m_len + len - k < 4)
+ goto bad;
+ *err = 0;
+ np = mtod(m0, u_char *);
+ switch (len - k) {
+
+ case 1:
+ return (cp[0] << 24) | (np[0] << 16) | (np[1] << 8) | np[2];
+
+ case 2:
+ return (cp[0] << 24) | (cp[1] << 16) | (np[0] << 8) | np[1];
+
+ default:
+ return (cp[0] << 24) | (cp[1] << 16) | (cp[2] << 8) | np[0];
+ }
+ bad:
+ *err = 1;
+ return 0;
+}
+
+static int
+m_xhalf(m, k, err)
+ register struct mbuf *m;
+ register int k, *err;
+{
+ register int len;
+ register u_char *cp;
+ register struct mbuf *m0;
+
+ MINDEX(len, m, k);
+ cp = mtod(m, u_char *) + k;
+ if (len - k >= 2) {
+ *err = 0;
+ return EXTRACT_SHORT(cp);
+ }
+ m0 = m->m_next;
+ if (m0 == 0)
+ goto bad;
+ *err = 0;
+ return (cp[0] << 8) | mtod(m0, u_char *)[0];
+ bad:
+ *err = 1;
+ return 0;
+}
+#endif
+
+/*
+ * Execute the filter program starting at pc on the packet p
+ * wirelen is the length of the original packet
+ * buflen is the amount of data present
+ */
+u_int
+bpf_filter(pc, p, wirelen, buflen)
+ register struct bpf_insn *pc;
+ register u_char *p;
+ u_int wirelen;
+ register u_int buflen;
+{
+ register u_int32 A, X;
+ register int k;
+ int32 mem[BPF_MEMWORDS];
+
+ if (pc == 0)
+ /*
+ * No filter means accept all.
+ */
+ return (u_int)-1;
+ A = 0;
+ X = 0;
+ --pc;
+ while (1) {
+ ++pc;
+ switch (pc->code) {
+
+ default:
+#ifdef KERNEL
+ return 0;
+#else
+ abort();
+#endif
+ case BPF_RET|BPF_K:
+ return (u_int)pc->k;
+
+ case BPF_RET|BPF_A:
+ return (u_int)A;
+
+ case BPF_LD|BPF_W|BPF_ABS:
+ k = pc->k;
+ if (k + sizeof(int32) > buflen) {
+#ifdef KERNEL
+ int merr;
+
+ if (buflen != 0)
+ return 0;
+ A = m_xword((struct mbuf *)p, k, &merr);
+ if (merr != 0)
+ return 0;
+ continue;
+#else
+ return 0;
+#endif
+ }
+ A = EXTRACT_LONG(&p[k]);
+ continue;
+
+ case BPF_LD|BPF_H|BPF_ABS:
+ k = pc->k;
+ if (k + sizeof(short) > buflen) {
+#ifdef KERNEL
+ int merr;
+
+ if (buflen != 0)
+ return 0;
+ A = m_xhalf((struct mbuf *)p, k, &merr);
+ continue;
+#else
+ return 0;
+#endif
+ }
+ A = EXTRACT_SHORT(&p[k]);
+ continue;
+
+ case BPF_LD|BPF_B|BPF_ABS:
+ k = pc->k;
+ if (k >= buflen) {
+#ifdef KERNEL
+ register struct mbuf *m;
+ register int len;
+
+ if (buflen != 0)
+ return 0;
+ m = (struct mbuf *)p;
+ MINDEX(len, m, k);
+ A = mtod(m, u_char *)[k];
+ continue;
+#else
+ return 0;
+#endif
+ }
+ A = p[k];
+ continue;
+
+ case BPF_LD|BPF_W|BPF_LEN:
+ A = wirelen;
+ continue;
+
+ case BPF_LDX|BPF_W|BPF_LEN:
+ X = wirelen;
+ continue;
+
+ case BPF_LD|BPF_W|BPF_IND:
+ k = X + pc->k;
+ if (k + sizeof(int32) > buflen) {
+#ifdef KERNEL
+ int merr;
+
+ if (buflen != 0)
+ return 0;
+ A = m_xword((struct mbuf *)p, k, &merr);
+ if (merr != 0)
+ return 0;
+ continue;
+#else
+ return 0;
+#endif
+ }
+ A = EXTRACT_LONG(&p[k]);
+ continue;
+
+ case BPF_LD|BPF_H|BPF_IND:
+ k = X + pc->k;
+ if (k + sizeof(short) > buflen) {
+#ifdef KERNEL
+ int merr;
+
+ if (buflen != 0)
+ return 0;
+ A = m_xhalf((struct mbuf *)p, k, &merr);
+ if (merr != 0)
+ return 0;
+ continue;
+#else
+ return 0;
+#endif
+ }
+ A = EXTRACT_SHORT(&p[k]);
+ continue;
+
+ case BPF_LD|BPF_B|BPF_IND:
+ k = X + pc->k;
+ if (k >= buflen) {
+#ifdef KERNEL
+ register struct mbuf *m;
+ register int len;
+
+ if (buflen != 0)
+ return 0;
+ m = (struct mbuf *)p;
+ MINDEX(len, m, k);
+ A = mtod(m, u_char *)[k];
+ continue;
+#else
+ return 0;
+#endif
+ }
+ A = p[k];
+ continue;
+
+ case BPF_LDX|BPF_MSH|BPF_B:
+ k = pc->k;
+ if (k >= buflen) {
+#ifdef KERNEL
+ register struct mbuf *m;
+ register int len;
+
+ if (buflen != 0)
+ return 0;
+ m = (struct mbuf *)p;
+ MINDEX(len, m, k);
+ X = (mtod(m, char *)[k] & 0xf) << 2;
+ continue;
+#else
+ return 0;
+#endif
+ }
+ X = (p[pc->k] & 0xf) << 2;
+ continue;
+
+ case BPF_LD|BPF_IMM:
+ A = pc->k;
+ continue;
+
+ case BPF_LDX|BPF_IMM:
+ X = pc->k;
+ continue;
+
+ case BPF_LD|BPF_MEM:
+ A = mem[pc->k];
+ continue;
+
+ case BPF_LDX|BPF_MEM:
+ X = mem[pc->k];
+ continue;
+
+ case BPF_ST:
+ mem[pc->k] = A;
+ continue;
+
+ case BPF_STX:
+ mem[pc->k] = X;
+ continue;
+
+ case BPF_JMP|BPF_JA:
+ pc += pc->k;
+ continue;
+
+ case BPF_JMP|BPF_JGT|BPF_K:
+ pc += (A > pc->k) ? pc->jt : pc->jf;
+ continue;
+
+ case BPF_JMP|BPF_JGE|BPF_K:
+ pc += (A >= pc->k) ? pc->jt : pc->jf;
+ continue;
+
+ case BPF_JMP|BPF_JEQ|BPF_K:
+ pc += (A == pc->k) ? pc->jt : pc->jf;
+ continue;
+
+ case BPF_JMP|BPF_JSET|BPF_K:
+ pc += (A & pc->k) ? pc->jt : pc->jf;
+ continue;
+
+ case BPF_JMP|BPF_JGT|BPF_X:
+ pc += (A > X) ? pc->jt : pc->jf;
+ continue;
+
+ case BPF_JMP|BPF_JGE|BPF_X:
+ pc += (A >= X) ? pc->jt : pc->jf;
+ continue;
+
+ case BPF_JMP|BPF_JEQ|BPF_X:
+ pc += (A == X) ? pc->jt : pc->jf;
+ continue;
+
+ case BPF_JMP|BPF_JSET|BPF_X:
+ pc += (A & X) ? pc->jt : pc->jf;
+ continue;
+
+ case BPF_ALU|BPF_ADD|BPF_X:
+ A += X;
+ continue;
+
+ case BPF_ALU|BPF_SUB|BPF_X:
+ A -= X;
+ continue;
+
+ case BPF_ALU|BPF_MUL|BPF_X:
+ A *= X;
+ continue;
+
+ case BPF_ALU|BPF_DIV|BPF_X:
+ if (X == 0)
+ return 0;
+ A /= X;
+ continue;
+
+ case BPF_ALU|BPF_AND|BPF_X:
+ A &= X;
+ continue;
+
+ case BPF_ALU|BPF_OR|BPF_X:
+ A |= X;
+ continue;
+
+ case BPF_ALU|BPF_LSH|BPF_X:
+ A <<= X;
+ continue;
+
+ case BPF_ALU|BPF_RSH|BPF_X:
+ A >>= X;
+ continue;
+
+ case BPF_ALU|BPF_ADD|BPF_K:
+ A += pc->k;
+ continue;
+
+ case BPF_ALU|BPF_SUB|BPF_K:
+ A -= pc->k;
+ continue;
+
+ case BPF_ALU|BPF_MUL|BPF_K:
+ A *= pc->k;
+ continue;
+
+ case BPF_ALU|BPF_DIV|BPF_K:
+ A /= pc->k;
+ continue;
+
+ case BPF_ALU|BPF_AND|BPF_K:
+ A &= pc->k;
+ continue;
+
+ case BPF_ALU|BPF_OR|BPF_K:
+ A |= pc->k;
+ continue;
+
+ case BPF_ALU|BPF_LSH|BPF_K:
+ A <<= pc->k;
+ continue;
+
+ case BPF_ALU|BPF_RSH|BPF_K:
+ A >>= pc->k;
+ continue;
+
+ case BPF_ALU|BPF_NEG:
+ A = -A;
+ continue;
+
+ case BPF_MISC|BPF_TAX:
+ X = A;
+ continue;
+
+ case BPF_MISC|BPF_TXA:
+ A = X;
+ continue;
+ }
+ }
+}
+
+#ifdef KERNEL
+/*
+ * Return true if the 'fcode' is a valid filter program.
+ * The constraints are that each jump be forward and to a valid
+ * code. The code must terminate with either an accept or reject.
+ * 'valid' is an array for use by the routine (it must be at least
+ * 'len' bytes long).
+ *
+ * The kernel needs to be able to verify an application's filter code.
+ * Otherwise, a bogus program could easily crash the system.
+ */
+int
+bpf_validate(f, len)
+ struct bpf_insn *f;
+ int len;
+{
+ register int i;
+ register struct bpf_insn *p;
+
+ for (i = 0; i < len; ++i) {
+ /*
+ * Check that that jumps are forward, and within
+ * the code block.
+ */
+ p = &f[i];
+ if (BPF_CLASS(p->code) == BPF_JMP) {
+ register int from = i + 1;
+
+ if (BPF_OP(p->code) == BPF_JA) {
+ if (from + p->k >= (unsigned)len)
+ return 0;
+ }
+ else if (from + p->jt >= len || from + p->jf >= len)
+ return 0;
+ }
+ /*
+ * Check that memory operations use valid addresses.
+ */
+ if ((BPF_CLASS(p->code) == BPF_ST ||
+ (BPF_CLASS(p->code) == BPF_LD &&
+ (p->code & 0xe0) == BPF_MEM)) &&
+ (p->k >= BPF_MEMWORDS || p->k < 0))
+ return 0;
+ /*
+ * Check for constant division by 0.
+ */
+ if (p->code == (BPF_ALU|BPF_DIV|BPF_K) && p->k == 0)
+ return 0;
+ }
+ return BPF_CLASS(f[len - 1].code) == BPF_RET;
+}
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/bpf_filter.c b/package/etrax-tools/src/e100boot/libpcap-0.4/bpf_filter.c
new file mode 120000
index 000000000..6ad8a2d22
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/bpf_filter.c
@@ -0,0 +1 @@
+bpf/net/bpf_filter.c \ No newline at end of file
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/bpf_image.c b/package/etrax-tools/src/e100boot/libpcap-0.4/bpf_image.c
new file mode 100644
index 000000000..7f63fb395
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/bpf_image.c
@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 1990, 1991, 1992, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/bpf_image.c,v 1.1 1999/08/26 10:05:20 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+
+#include <stdio.h>
+#include <string.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+char *
+bpf_image(p, n)
+ struct bpf_insn *p;
+ int n;
+{
+ int v;
+ char *fmt, *op;
+ static char image[256];
+ char operand[64];
+
+ v = p->k;
+ switch (p->code) {
+
+ default:
+ op = "unimp";
+ fmt = "0x%x";
+ v = p->code;
+ break;
+
+ case BPF_RET|BPF_K:
+ op = "ret";
+ fmt = "#%d";
+ break;
+
+ case BPF_RET|BPF_A:
+ op = "ret";
+ fmt = "";
+ break;
+
+ case BPF_LD|BPF_W|BPF_ABS:
+ op = "ld";
+ fmt = "[%d]";
+ break;
+
+ case BPF_LD|BPF_H|BPF_ABS:
+ op = "ldh";
+ fmt = "[%d]";
+ break;
+
+ case BPF_LD|BPF_B|BPF_ABS:
+ op = "ldb";
+ fmt = "[%d]";
+ break;
+
+ case BPF_LD|BPF_W|BPF_LEN:
+ op = "ld";
+ fmt = "#pktlen";
+ break;
+
+ case BPF_LD|BPF_W|BPF_IND:
+ op = "ld";
+ fmt = "[x + %d]";
+ break;
+
+ case BPF_LD|BPF_H|BPF_IND:
+ op = "ldh";
+ fmt = "[x + %d]";
+ break;
+
+ case BPF_LD|BPF_B|BPF_IND:
+ op = "ldb";
+ fmt = "[x + %d]";
+ break;
+
+ case BPF_LD|BPF_IMM:
+ op = "ld";
+ fmt = "#0x%x";
+ break;
+
+ case BPF_LDX|BPF_IMM:
+ op = "ldx";
+ fmt = "#0x%x";
+ break;
+
+ case BPF_LDX|BPF_MSH|BPF_B:
+ op = "ldxb";
+ fmt = "4*([%d]&0xf)";
+ break;
+
+ case BPF_LD|BPF_MEM:
+ op = "ld";
+ fmt = "M[%d]";
+ break;
+
+ case BPF_LDX|BPF_MEM:
+ op = "ldx";
+ fmt = "M[%d]";
+ break;
+
+ case BPF_ST:
+ op = "st";
+ fmt = "M[%d]";
+ break;
+
+ case BPF_STX:
+ op = "stx";
+ fmt = "M[%d]";
+ break;
+
+ case BPF_JMP|BPF_JA:
+ op = "ja";
+ fmt = "%d";
+ v = n + 1 + p->k;
+ break;
+
+ case BPF_JMP|BPF_JGT|BPF_K:
+ op = "jgt";
+ fmt = "#0x%x";
+ break;
+
+ case BPF_JMP|BPF_JGE|BPF_K:
+ op = "jge";
+ fmt = "#0x%x";
+ break;
+
+ case BPF_JMP|BPF_JEQ|BPF_K:
+ op = "jeq";
+ fmt = "#0x%x";
+ break;
+
+ case BPF_JMP|BPF_JSET|BPF_K:
+ op = "jset";
+ fmt = "#0x%x";
+ break;
+
+ case BPF_JMP|BPF_JGT|BPF_X:
+ op = "jgt";
+ fmt = "x";
+ break;
+
+ case BPF_JMP|BPF_JGE|BPF_X:
+ op = "jge";
+ fmt = "x";
+ break;
+
+ case BPF_JMP|BPF_JEQ|BPF_X:
+ op = "jeq";
+ fmt = "x";
+ break;
+
+ case BPF_JMP|BPF_JSET|BPF_X:
+ op = "jset";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_ADD|BPF_X:
+ op = "add";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_SUB|BPF_X:
+ op = "sub";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_MUL|BPF_X:
+ op = "mul";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_DIV|BPF_X:
+ op = "div";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_AND|BPF_X:
+ op = "and";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_OR|BPF_X:
+ op = "or";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_LSH|BPF_X:
+ op = "lsh";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_RSH|BPF_X:
+ op = "rsh";
+ fmt = "x";
+ break;
+
+ case BPF_ALU|BPF_ADD|BPF_K:
+ op = "add";
+ fmt = "#%d";
+ break;
+
+ case BPF_ALU|BPF_SUB|BPF_K:
+ op = "sub";
+ fmt = "#%d";
+ break;
+
+ case BPF_ALU|BPF_MUL|BPF_K:
+ op = "mul";
+ fmt = "#%d";
+ break;
+
+ case BPF_ALU|BPF_DIV|BPF_K:
+ op = "div";
+ fmt = "#%d";
+ break;
+
+ case BPF_ALU|BPF_AND|BPF_K:
+ op = "and";
+ fmt = "#0x%x";
+ break;
+
+ case BPF_ALU|BPF_OR|BPF_K:
+ op = "or";
+ fmt = "#0x%x";
+ break;
+
+ case BPF_ALU|BPF_LSH|BPF_K:
+ op = "lsh";
+ fmt = "#%d";
+ break;
+
+ case BPF_ALU|BPF_RSH|BPF_K:
+ op = "rsh";
+ fmt = "#%d";
+ break;
+
+ case BPF_ALU|BPF_NEG:
+ op = "neg";
+ fmt = "";
+ break;
+
+ case BPF_MISC|BPF_TAX:
+ op = "tax";
+ fmt = "";
+ break;
+
+ case BPF_MISC|BPF_TXA:
+ op = "txa";
+ fmt = "";
+ break;
+ }
+ (void)sprintf(operand, fmt, v);
+ (void)sprintf(image,
+ (BPF_CLASS(p->code) == BPF_JMP &&
+ BPF_OP(p->code) != BPF_JA) ?
+ "(%03d) %-8s %-16s jt %d\tjf %d"
+ : "(%03d) %-8s %s",
+ n, op, operand, n + 1 + p->jt, n + 1 + p->jf);
+ return image;
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/config.cache b/package/etrax-tools/src/e100boot/libpcap-0.4/config.cache
new file mode 100644
index 000000000..c72e7d7a2
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/config.cache
@@ -0,0 +1,35 @@
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs. It is not useful on other systems.
+# If it contains results you don't want to keep, you may remove or edit it.
+#
+# By default, configure uses ./config.cache as the cache file,
+# creating it if it does not exist already. You can give configure
+# the --cache-file=FILE option to use a different cache file; that is
+# what configure does when it calls configure scripts in
+# subdirectories, so they share the cache.
+# Giving --cache-file=/dev/null disables caching, for debugging configure.
+# config.status only pays attention to the cache file if you give it the
+# --recheck option to rerun configure.
+#
+ac_cv_func_ether_hostton=${ac_cv_func_ether_hostton=yes}
+ac_cv_func_strerror=${ac_cv_func_strerror=yes}
+ac_cv_header_malloc_h=${ac_cv_header_malloc_h=yes}
+ac_cv_header_net_if_arp_h=${ac_cv_header_net_if_arp_h=yes}
+ac_cv_header_sys_ioccom_h=${ac_cv_header_sys_ioccom_h=no}
+ac_cv_header_sys_sockio_h=${ac_cv_header_sys_sockio_h=no}
+ac_cv_lbl_flex_v24=${ac_cv_lbl_flex_v24=yes}
+ac_cv_lbl_gcc_fixincludes=${ac_cv_lbl_gcc_fixincludes=yes}
+ac_cv_lbl_gcc_vers=${ac_cv_lbl_gcc_vers=4}
+ac_cv_lbl_sockaddr_has_sa_len=${ac_cv_lbl_sockaddr_has_sa_len=no}
+ac_cv_lbl_unaligned_fail=${ac_cv_lbl_unaligned_fail=no}
+ac_cv_linux_vers=${ac_cv_linux_vers=2}
+ac_cv_prog_CC=${ac_cv_prog_CC=gcc}
+ac_cv_prog_CPP=${ac_cv_prog_CPP='gcc -E'}
+ac_cv_prog_V_LEX=${ac_cv_prog_V_LEX=flex}
+ac_cv_prog_V_RANLIB=${ac_cv_prog_V_RANLIB=ranlib}
+ac_cv_prog_V_YACC=${ac_cv_prog_V_YACC=bison}
+ac_cv_prog_cc_cross=${ac_cv_prog_cc_cross=no}
+ac_cv_prog_cc_g=${ac_cv_prog_cc_g=yes}
+ac_cv_prog_cc_works=${ac_cv_prog_cc_works=yes}
+ac_cv_prog_gcc=${ac_cv_prog_gcc=yes}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/config.guess b/package/etrax-tools/src/e100boot/libpcap-0.4/config.guess
new file mode 100755
index 000000000..e9e44559f
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/config.guess
@@ -0,0 +1,693 @@
+#! /bin/sh
+# Attempt to guess a canonical system name.
+# Copyright (C) 1992, 93, 94, 95, 1996 Free Software Foundation, Inc.
+#
+# This file is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+#
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that program.
+
+# Written by Per Bothner <bothner@cygnus.com>.
+# The master version of this file is at the FSF in /home/gd/gnu/lib.
+#
+# This script attempts to guess a canonical system name similar to
+# config.sub. If it succeeds, it prints the system name on stdout, and
+# exits with 0. Otherwise, it exits with 1.
+#
+# The plan is that this can be called by configure scripts if you
+# don't specify an explicit system type (host/target name).
+#
+# Only a few systems have been added to this list; please add others
+# (but try to keep the structure clean).
+#
+
+# This is needed to find uname on a Pyramid OSx when run in the BSD universe.
+# (ghazi@noc.rutgers.edu 8/24/94.)
+if (test -f /.attbin/uname) >/dev/null 2>&1 ; then
+ PATH=$PATH:/.attbin ; export PATH
+fi
+
+UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown
+UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown
+UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown
+UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown
+
+trap 'rm -f dummy.c dummy.o dummy; exit 1' 1 2 15
+
+# Note: order is significant - the case branches are not exclusive.
+
+case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in
+ alpha:OSF1:*:*)
+ # A Vn.n version is a released version.
+ # A Tn.n version is a released field test version.
+ # A Xn.n version is an unreleased experimental baselevel.
+ # 1.2 uses "1.2" for uname -r.
+ echo alpha-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[VTX]//'`
+ exit 0 ;;
+ 21064:Windows_NT:50:3)
+ echo alpha-dec-winnt3.5
+ exit 0 ;;
+ Amiga*:UNIX_System_V:4.0:*)
+ echo m68k-cbm-sysv4
+ exit 0;;
+ amiga:NetBSD:*:*)
+ echo m68k-cbm-netbsd${UNAME_RELEASE}
+ exit 0 ;;
+ amiga:OpenBSD:*:*)
+ echo m68k-cbm-openbsd${UNAME_RELEASE}
+ exit 0 ;;
+ arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*)
+ echo arm-acorn-riscix${UNAME_RELEASE}
+ exit 0;;
+ Pyramid*:OSx*:*:*|MIS*:OSx*:*:*)
+ # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE.
+ if test "`(/bin/universe) 2>/dev/null`" = att ; then
+ echo pyramid-pyramid-sysv3
+ else
+ echo pyramid-pyramid-bsd
+ fi
+ exit 0 ;;
+ NILE:*:*:dcosx)
+ echo pyramid-pyramid-svr4
+ exit 0 ;;
+ sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*)
+ echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+ exit 0 ;;
+ i86pc:SunOS:5.*:*)
+ echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+ exit 0 ;;
+ sun4*:SunOS:6*:*)
+ # According to config.sub, this is the proper way to canonicalize
+ # SunOS6. Hard to guess exactly what SunOS6 will be like, but
+ # it's likely to be more like Solaris than SunOS4.
+ echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+ exit 0 ;;
+ sun4*:SunOS:*:*)
+ case "`/usr/bin/arch -k`" in
+ Series*|S4*)
+ UNAME_RELEASE=`uname -v`
+ ;;
+ esac
+ # Japanese Language versions have a version number like `4.1.3-JL'.
+ echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'`
+ exit 0 ;;
+ sun3*:SunOS:*:*)
+ echo m68k-sun-sunos${UNAME_RELEASE}
+ exit 0 ;;
+ aushp:SunOS:*:*)
+ echo sparc-auspex-sunos${UNAME_RELEASE}
+ exit 0 ;;
+ atari*:NetBSD:*:*)
+ echo m68k-atari-netbsd${UNAME_RELEASE}
+ exit 0 ;;
+ atari*:OpenBSD:*:*)
+ echo m68k-atari-openbsd${UNAME_RELEASE}
+ exit 0 ;;
+ sun3*:NetBSD:*:*)
+ echo m68k-sun-netbsd${UNAME_RELEASE}
+ exit 0 ;;
+ sun3*:OpenBSD:*:*)
+ echo m68k-sun-openbsd${UNAME_RELEASE}
+ exit 0 ;;
+ mac68k:NetBSD:*:*)
+ echo m68k-apple-netbsd${UNAME_RELEASE}
+ exit 0 ;;
+ mac68k:OpenBSD:*:*)
+ echo m68k-apple-openbsd${UNAME_RELEASE}
+ exit 0 ;;
+ powerpc:machten:*:*)
+ echo powerpc-apple-machten${UNAME_RELEASE}
+ exit 0 ;;
+ RISC*:Mach:*:*)
+ echo mips-dec-mach_bsd4.3
+ exit 0 ;;
+ RISC*:ULTRIX:*:*)
+ echo mips-dec-ultrix${UNAME_RELEASE}
+ exit 0 ;;
+ VAX*:ULTRIX*:*:*)
+ echo vax-dec-ultrix${UNAME_RELEASE}
+ exit 0 ;;
+ mips:*:*:UMIPS | mips:*:*:RISCos)
+ sed 's/^ //' << EOF >dummy.c
+ int main (argc, argv) int argc; char **argv; {
+ #if defined (host_mips) && defined (MIPSEB)
+ #if defined (SYSTYPE_SYSV)
+ printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0);
+ #endif
+ #if defined (SYSTYPE_SVR4)
+ printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0);
+ #endif
+ #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD)
+ printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0);
+ #endif
+ #endif
+ exit (-1);
+ }
+EOF
+ ${CC-cc} dummy.c -o dummy \
+ && ./dummy `echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` \
+ && rm dummy.c dummy && exit 0
+ rm -f dummy.c dummy
+ echo mips-mips-riscos${UNAME_RELEASE}
+ exit 0 ;;
+ Night_Hawk:Power_UNIX:*:*)
+ echo powerpc-harris-powerunix
+ exit 0 ;;
+ m88k:CX/UX:7*:*)
+ echo m88k-harris-cxux7
+ exit 0 ;;
+ m88k:*:4*:R4*)
+ echo m88k-motorola-sysv4
+ exit 0 ;;
+ m88k:*:3*:R3*)
+ echo m88k-motorola-sysv3
+ exit 0 ;;
+ AViiON:dgux:*:*)
+ # DG/UX returns AViiON for all architectures
+ UNAME_PROCESSOR=`/usr/bin/uname -p`
+ if [ $UNAME_PROCESSOR = mc88100 -o $UNAME_PROCESSOR = mc88110 ] ; then
+ if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx \
+ -o ${TARGET_BINARY_INTERFACE}x = x ] ; then
+ echo m88k-dg-dgux${UNAME_RELEASE}
+ else
+ echo m88k-dg-dguxbcs${UNAME_RELEASE}
+ fi
+ else echo i586-dg-dgux${UNAME_RELEASE}
+ fi
+ exit 0 ;;
+ M88*:DolphinOS:*:*) # DolphinOS (SVR3)
+ echo m88k-dolphin-sysv3
+ exit 0 ;;
+ M88*:*:R3*:*)
+ # Delta 88k system running SVR3
+ echo m88k-motorola-sysv3
+ exit 0 ;;
+ XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3)
+ echo m88k-tektronix-sysv3
+ exit 0 ;;
+ Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD)
+ echo m68k-tektronix-bsd
+ exit 0 ;;
+ *:IRIX*:*:*)
+ echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'`
+ exit 0 ;;
+ ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX.
+ echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id
+ exit 0 ;; # Note that: echo "'`uname -s`'" gives 'AIX '
+ i?86:AIX:*:*)
+ echo i386-ibm-aix
+ exit 0 ;;
+ *:AIX:2:3)
+ if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then
+ sed 's/^ //' << EOF >dummy.c
+ #include <sys/systemcfg.h>
+
+ main()
+ {
+ if (!__power_pc())
+ exit(1);
+ puts("powerpc-ibm-aix3.2.5");
+ exit(0);
+ }
+EOF
+ ${CC-cc} dummy.c -o dummy && ./dummy && rm dummy.c dummy && exit 0
+ rm -f dummy.c dummy
+ echo rs6000-ibm-aix3.2.5
+ elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then
+ echo rs6000-ibm-aix3.2.4
+ else
+ echo rs6000-ibm-aix3.2
+ fi
+ exit 0 ;;
+ *:AIX:*:4)
+ if /usr/sbin/lsattr -EHl proc0 | grep POWER >/dev/null 2>&1; then
+ IBM_ARCH=rs6000
+ else
+ IBM_ARCH=powerpc
+ fi
+ if [ -x /usr/bin/oslevel ] ; then
+ IBM_REV=`/usr/bin/oslevel`
+ else
+ IBM_REV=4.${UNAME_RELEASE}
+ fi
+ echo ${IBM_ARCH}-ibm-aix${IBM_REV}
+ exit 0 ;;
+ *:AIX:*:*)
+ echo rs6000-ibm-aix
+ exit 0 ;;
+ ibmrt:4.4BSD:*|romp-ibm:BSD:*)
+ echo romp-ibm-bsd4.4
+ exit 0 ;;
+ ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC NetBSD and
+ echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to
+ exit 0 ;; # report: romp-ibm BSD 4.3
+ *:BOSX:*:*)
+ echo rs6000-bull-bosx
+ exit 0 ;;
+ DPX/2?00:B.O.S.:*:*)
+ echo m68k-bull-sysv3
+ exit 0 ;;
+ 9000/[34]??:4.3bsd:1.*:*)
+ echo m68k-hp-bsd
+ exit 0 ;;
+ hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*)
+ echo m68k-hp-bsd4.4
+ exit 0 ;;
+ 9000/[3478]??:HP-UX:*:*)
+ case "${UNAME_MACHINE}" in
+ 9000/31? ) HP_ARCH=m68000 ;;
+ 9000/[34]?? ) HP_ARCH=m68k ;;
+ 9000/7?? | 9000/8?[1679] ) HP_ARCH=hppa1.1 ;;
+ 9000/8?? ) HP_ARCH=hppa1.0 ;;
+ esac
+ HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'`
+ echo ${HP_ARCH}-hp-hpux${HPUX_REV}
+ exit 0 ;;
+ 3050*:HI-UX:*:*)
+ sed 's/^ //' << EOF >dummy.c
+ #include <unistd.h>
+ int
+ main ()
+ {
+ long cpu = sysconf (_SC_CPU_VERSION);
+ /* The order matters, because CPU_IS_HP_MC68K erroneously returns
+ true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct
+ results, however. */
+ if (CPU_IS_PA_RISC (cpu))
+ {
+ switch (cpu)
+ {
+ case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break;
+ case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break;
+ case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break;
+ default: puts ("hppa-hitachi-hiuxwe2"); break;
+ }
+ }
+ else if (CPU_IS_HP_MC68K (cpu))
+ puts ("m68k-hitachi-hiuxwe2");
+ else puts ("unknown-hitachi-hiuxwe2");
+ exit (0);
+ }
+EOF
+ ${CC-cc} dummy.c -o dummy && ./dummy && rm dummy.c dummy && exit 0
+ rm -f dummy.c dummy
+ echo unknown-hitachi-hiuxwe2
+ exit 0 ;;
+ 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* )
+ echo hppa1.1-hp-bsd
+ exit 0 ;;
+ 9000/8??:4.3bsd:*:*)
+ echo hppa1.0-hp-bsd
+ exit 0 ;;
+ hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* )
+ echo hppa1.1-hp-osf
+ exit 0 ;;
+ hp8??:OSF1:*:*)
+ echo hppa1.0-hp-osf
+ exit 0 ;;
+ i?86:OSF1:*:*)
+ if [ -x /usr/sbin/sysversion ] ; then
+ echo ${UNAME_MACHINE}-unknown-osf1mk
+ else
+ echo ${UNAME_MACHINE}-unknown-osf1
+ fi
+ exit 0 ;;
+ parisc*:Lites*:*:*)
+ echo hppa1.1-hp-lites
+ exit 0 ;;
+ C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*)
+ echo c1-convex-bsd
+ exit 0 ;;
+ C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*)
+ if getsysinfo -f scalar_acc
+ then echo c32-convex-bsd
+ else echo c2-convex-bsd
+ fi
+ exit 0 ;;
+ C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*)
+ echo c34-convex-bsd
+ exit 0 ;;
+ C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*)
+ echo c38-convex-bsd
+ exit 0 ;;
+ C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*)
+ echo c4-convex-bsd
+ exit 0 ;;
+ CRAY*X-MP:*:*:*)
+ echo xmp-cray-unicos
+ exit 0 ;;
+ CRAY*Y-MP:*:*:*)
+ echo ymp-cray-unicos${UNAME_RELEASE}
+ exit 0 ;;
+ CRAY*[A-Z]90:*:*:*)
+ echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \
+ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \
+ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/
+ exit 0 ;;
+ CRAY*TS:*:*:*)
+ echo t90-cray-unicos${UNAME_RELEASE}
+ exit 0 ;;
+ CRAY-2:*:*:*)
+ echo cray2-cray-unicos
+ exit 0 ;;
+ F300:UNIX_System_V:*:*)
+ FUJITSU_SYS=`uname -p | tr [A-Z] [a-z] | sed -e 's/\///'`
+ FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'`
+ echo "f300-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}"
+ exit 0 ;;
+ F301:UNIX_System_V:*:*)
+ echo f301-fujitsu-uxpv`echo $UNAME_RELEASE | sed 's/ .*//'`
+ exit 0 ;;
+ hp3[0-9][05]:NetBSD:*:*)
+ echo m68k-hp-netbsd${UNAME_RELEASE}
+ exit 0 ;;
+ hp3[0-9][05]:OpenBSD:*:*)
+ echo m68k-hp-openbsd${UNAME_RELEASE}
+ exit 0 ;;
+ i?86:BSD/386:*:* | *:BSD/OS:*:*)
+ echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE}
+ exit 0 ;;
+ *:FreeBSD:*:*)
+ echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`
+ exit 0 ;;
+ *:NetBSD:*:*)
+ echo ${UNAME_MACHINE}-unknown-netbsd`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'`
+ exit 0 ;;
+ *:OpenBSD:*:*)
+ echo ${UNAME_MACHINE}-unknown-openbsd`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'`
+ exit 0 ;;
+ i*:CYGWIN*:*)
+ echo i386-pc-cygwin32
+ exit 0 ;;
+ p*:CYGWIN*:*)
+ echo powerpcle-unknown-cygwin32
+ exit 0 ;;
+ prep*:SunOS:5.*:*)
+ echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'`
+ exit 0 ;;
+ *:GNU:*:*)
+ echo `echo ${UNAME_MACHINE}|sed -e 's,/.*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'`
+ exit 0 ;;
+ *:Linux:*:*)
+ # The BFD linker knows what the default object file format is, so
+ # first see if it will tell us.
+ ld_help_string=`ld --help 2>&1`
+ if echo "$ld_help_string" | grep >/dev/null 2>&1 "supported emulations: elf_i.86"; then
+ echo "${UNAME_MACHINE}-pc-linux-gnu" ; exit 0
+ elif echo "$ld_help_string" | grep >/dev/null 2>&1 "supported emulations: i.86linux"; then
+ echo "${UNAME_MACHINE}-pc-linux-gnuaout" ; exit 0
+ elif echo "$ld_help_string" | grep >/dev/null 2>&1 "supported emulations: i.86coff"; then
+ echo "${UNAME_MACHINE}-pc-linux-gnucoff" ; exit 0
+ elif echo "$ld_help_string" | grep >/dev/null 2>&1 "supported emulations: m68kelf"; then
+ echo "${UNAME_MACHINE}-unknown-linux-gnu" ; exit 0
+ elif echo "$ld_help_string" | grep >/dev/null 2>&1 "supported emulations: m68klinux"; then
+ echo "${UNAME_MACHINE}-unknown-linux-gnuaout" ; exit 0
+ elif echo "$ld_help_string" | grep >/dev/null 2>&1 "supported emulations: elf32ppc"; then
+ echo "powerpc-unknown-linux-gnu" ; exit 0
+ elif test "${UNAME_MACHINE}" = "alpha" ; then
+ echo alpha-unknown-linux-gnu ; exit 0
+ elif test "${UNAME_MACHINE}" = "sparc" ; then
+ echo sparc-unknown-linux-gnu ; exit 0
+ else
+ # Either a pre-BFD a.out linker (linux-gnuoldld) or one that does not give us
+ # useful --help. Gcc wants to distinguish between linux-gnuoldld and linux-gnuaout.
+ test ! -d /usr/lib/ldscripts/. \
+ && echo "${UNAME_MACHINE}-pc-linux-gnuoldld" && exit 0
+ # Determine whether the default compiler is a.out or elf
+ cat >dummy.c <<EOF
+main(argc, argv)
+int argc;
+char *argv[];
+{
+#ifdef __ELF__
+ printf ("%s-pc-linux-gnu\n", argv[1]);
+#else
+ printf ("%s-pc-linux-gnuaout\n", argv[1]);
+#endif
+ return 0;
+}
+EOF
+ ${CC-cc} dummy.c -o dummy 2>/dev/null && ./dummy "${UNAME_MACHINE}" && rm dummy.c dummy && exit 0
+ rm -f dummy.c dummy
+ fi ;;
+# ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. earlier versions
+# are messed up and put the nodename in both sysname and nodename.
+ i?86:DYNIX/ptx:4*:*)
+ echo i386-sequent-sysv4
+ exit 0 ;;
+ i?86:*:4.*:* | i?86:SYSTEM_V:4.*:*)
+ if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then
+ echo ${UNAME_MACHINE}-univel-sysv${UNAME_RELEASE}
+ else
+ echo ${UNAME_MACHINE}-pc-sysv${UNAME_RELEASE}
+ fi
+ exit 0 ;;
+ i?86:*:3.2:*)
+ if test -f /usr/options/cb.name; then
+ UNAME_REL=`sed -n 's/.*Version //p' </usr/options/cb.name`
+ echo ${UNAME_MACHINE}-pc-isc$UNAME_REL
+ elif /bin/uname -X 2>/dev/null >/dev/null ; then
+ UNAME_REL=`(/bin/uname -X|egrep Release|sed -e 's/.*= //')`
+ (/bin/uname -X|egrep i80486 >/dev/null) && UNAME_MACHINE=i486
+ (/bin/uname -X|egrep '^Machine.*Pentium' >/dev/null) \
+ && UNAME_MACHINE=i586
+ echo ${UNAME_MACHINE}-pc-sco$UNAME_REL
+ else
+ echo ${UNAME_MACHINE}-pc-sysv32
+ fi
+ exit 0 ;;
+ Intel:Mach:3*:*)
+ echo i386-pc-mach3
+ exit 0 ;;
+ paragon:*:*:*)
+ echo i860-intel-osf1
+ exit 0 ;;
+ i860:*:4.*:*) # i860-SVR4
+ if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then
+ echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4
+ else # Add other i860-SVR4 vendors below as they are discovered.
+ echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4
+ fi
+ exit 0 ;;
+ mini*:CTIX:SYS*5:*)
+ # "miniframe"
+ echo m68010-convergent-sysv
+ exit 0 ;;
+ M68*:*:R3V[567]*:*)
+ test -r /sysV68 && echo 'm68k-motorola-sysv' && exit 0 ;;
+ 3[34]??:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 4850:*:4.0:3.0)
+ OS_REL=''
+ test -r /etc/.relid \
+ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid`
+ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+ && echo i486-ncr-sysv4.3${OS_REL} && exit 0
+ /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \
+ && echo i586-ncr-sysv4.3${OS_REL} && exit 0 ;;
+ 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*)
+ /bin/uname -p 2>/dev/null | grep 86 >/dev/null \
+ && echo i486-ncr-sysv4 && exit 0 ;;
+ m68*:LynxOS:2.*:*)
+ echo m68k-unknown-lynxos${UNAME_RELEASE}
+ exit 0 ;;
+ mc68030:UNIX_System_V:4.*:*)
+ echo m68k-atari-sysv4
+ exit 0 ;;
+ i?86:LynxOS:2.*:*)
+ echo i386-unknown-lynxos${UNAME_RELEASE}
+ exit 0 ;;
+ TSUNAMI:LynxOS:2.*:*)
+ echo sparc-unknown-lynxos${UNAME_RELEASE}
+ exit 0 ;;
+ rs6000:LynxOS:2.*:* | PowerPC:LynxOS:2.*:*)
+ echo rs6000-unknown-lynxos${UNAME_RELEASE}
+ exit 0 ;;
+ SM[BE]S:UNIX_SV:*:*)
+ echo mips-dde-sysv${UNAME_RELEASE}
+ exit 0 ;;
+ RM*:SINIX-*:*:*)
+ echo mips-sni-sysv4
+ exit 0 ;;
+ *:SINIX-*:*:*)
+ if uname -p 2>/dev/null >/dev/null ; then
+ UNAME_MACHINE=`(uname -p) 2>/dev/null`
+ echo ${UNAME_MACHINE}-sni-sysv4
+ else
+ echo ns32k-sni-sysv
+ fi
+ exit 0 ;;
+ *:UNIX_System_V:4*:FTX*)
+ # From Gerald Hewes <hewes@openmarket.com>.
+ # How about differentiating between stratus architectures? -djm
+ echo hppa1.1-stratus-sysv4
+ exit 0 ;;
+ *:*:*:FTX*)
+ # From seanf@swdc.stratus.com.
+ echo i860-stratus-sysv4
+ exit 0 ;;
+ mc68*:A/UX:*:*)
+ echo m68k-apple-aux${UNAME_RELEASE}
+ exit 0 ;;
+ R3000:*System_V*:*:* | R4000:UNIX_SYSV:*:*)
+ if [ -d /usr/nec ]; then
+ echo mips-nec-sysv${UNAME_RELEASE}
+ else
+ echo mips-unknown-sysv${UNAME_RELEASE}
+ fi
+ exit 0 ;;
+ PENTIUM:CPunix:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort
+ # says <Richard.M.Bartel@ccMail.Census.GOV>
+ echo i586-unisys-sysv4
+ exit 0 ;;
+esac
+
+#echo '(No uname command or uname output not recognized.)' 1>&2
+#echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2
+
+cat >dummy.c <<EOF
+#ifdef _SEQUENT_
+# include <sys/types.h>
+# include <sys/utsname.h>
+#endif
+main ()
+{
+#if defined (sony)
+#if defined (MIPSEB)
+ /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed,
+ I don't know.... */
+ printf ("mips-sony-bsd\n"); exit (0);
+#else
+#include <sys/param.h>
+ printf ("m68k-sony-newsos%s\n",
+#ifdef NEWSOS4
+ "4"
+#else
+ ""
+#endif
+ ); exit (0);
+#endif
+#endif
+
+#if defined (__arm) && defined (__acorn) && defined (__unix)
+ printf ("arm-acorn-riscix"); exit (0);
+#endif
+
+#if defined (hp300) && !defined (hpux)
+ printf ("m68k-hp-bsd\n"); exit (0);
+#endif
+
+#if defined (NeXT)
+#if !defined (__ARCHITECTURE__)
+#define __ARCHITECTURE__ "m68k"
+#endif
+ int version;
+ version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`;
+ printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version);
+ exit (0);
+#endif
+
+#if defined (MULTIMAX) || defined (n16)
+#if defined (UMAXV)
+ printf ("ns32k-encore-sysv\n"); exit (0);
+#else
+#if defined (CMU)
+ printf ("ns32k-encore-mach\n"); exit (0);
+#else
+ printf ("ns32k-encore-bsd\n"); exit (0);
+#endif
+#endif
+#endif
+
+#if defined (__386BSD__)
+ printf ("i386-pc-bsd\n"); exit (0);
+#endif
+
+#if defined (sequent)
+#if defined (i386)
+ printf ("i386-sequent-dynix\n"); exit (0);
+#endif
+#if defined (ns32000)
+ printf ("ns32k-sequent-dynix\n"); exit (0);
+#endif
+#endif
+
+#if defined (_SEQUENT_)
+ struct utsname un;
+
+ uname(&un);
+
+ if (strncmp(un.version, "V2", 2) == 0) {
+ printf ("i386-sequent-ptx2\n"); exit (0);
+ }
+ if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */
+ printf ("i386-sequent-ptx1\n"); exit (0);
+ }
+ printf ("i386-sequent-ptx\n"); exit (0);
+
+#endif
+
+#if defined (vax)
+#if !defined (ultrix)
+ printf ("vax-dec-bsd\n"); exit (0);
+#else
+ printf ("vax-dec-ultrix\n"); exit (0);
+#endif
+#endif
+
+#if defined (alliant) && defined (i860)
+ printf ("i860-alliant-bsd\n"); exit (0);
+#endif
+
+ exit (1);
+}
+EOF
+
+${CC-cc} dummy.c -o dummy 2>/dev/null && ./dummy && rm dummy.c dummy && exit 0
+rm -f dummy.c dummy
+
+# Apollos put the system type in the environment.
+
+test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit 0; }
+
+# Convex versions that predate uname can use getsysinfo(1)
+
+if [ -x /usr/convex/getsysinfo ]
+then
+ case `getsysinfo -f cpu_type` in
+ c1*)
+ echo c1-convex-bsd
+ exit 0 ;;
+ c2*)
+ if getsysinfo -f scalar_acc
+ then echo c32-convex-bsd
+ else echo c2-convex-bsd
+ fi
+ exit 0 ;;
+ c34*)
+ echo c34-convex-bsd
+ exit 0 ;;
+ c38*)
+ echo c38-convex-bsd
+ exit 0 ;;
+ c4*)
+ echo c4-convex-bsd
+ exit 0 ;;
+ esac
+fi
+
+#echo '(Unable to guess system type)' 1>&2
+
+exit 1
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/config.log b/package/etrax-tools/src/e100boot/libpcap-0.4/config.log
new file mode 100644
index 000000000..2fa5cab03
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/config.log
@@ -0,0 +1,61 @@
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+
+configure:578: checking host system type
+configure:599: checking target system type
+configure:617: checking build system type
+configure:711: checking for gcc
+configure:788: checking whether the C compiler (gcc ) works
+configure:802: gcc -o conftest conftest.c 1>&5
+configure:822: checking whether the C compiler (gcc ) is a cross-compiler
+configure:827: checking whether we are using GNU C
+configure:836: gcc -E conftest.c
+configure:851: checking whether gcc accepts -g
+configure:884: checking gcc version
+configure:1028: checking how to run the C preprocessor
+configure:1049: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:1092: checking for malloc.h
+configure:1102: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:1092: checking for sys/ioccom.h
+configure:1102: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:1098:24: error: sys/ioccom.h: No such file or directory
+configure: failed program was:
+#line 1097 "configure"
+#include "confdefs.h"
+#include <sys/ioccom.h>
+configure:1092: checking for sys/sockio.h
+configure:1102: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:1098:24: error: sys/sockio.h: No such file or directory
+configure: failed program was:
+#line 1097 "configure"
+#include "confdefs.h"
+#include <sys/sockio.h>
+configure:1131: checking for ANSI ioctl definitions
+configure:1155: gcc -c -g -O2 conftest.c 1>&5
+configure:1178: checking for ether_hostton
+configure:1206: gcc -o conftest -g -O2 conftest.c 1>&5
+configure:1178: checking for strerror
+configure:1206: gcc -o conftest -g -O2 conftest.c 1>&5
+configure:1238: checking packet capture type
+configure:1341: checking for net/if_arp.h
+configure:1351: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:1378: checking Linux kernel version
+configure:1419: checking for flex
+configure:1452: checking for flex 2.4 or higher
+configure:1478: checking for bison
+configure:1602: checking for ranlib
+configure:1672: checking if sockaddr struct has sa_len member
+configure:1686: gcc -c -g -O2 conftest.c 1>&5
+configure: In function 'main':
+configure:1682: error: 'struct sockaddr' has no member named 'sa_len'
+configure: failed program was:
+#line 1677 "configure"
+#include "confdefs.h"
+
+# include <sys/types.h>
+# include <sys/socket.h>
+int main() {
+u_int i = sizeof(((struct sockaddr *)0)->sa_len)
+; return 0; }
+configure:1707: checking if unaligned accesses fail
+configure:1803: checking for a BSD compatible install
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/config.status b/package/etrax-tools/src/e100boot/libpcap-0.4/config.status
new file mode 100755
index 000000000..f4c395e71
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/config.status
@@ -0,0 +1,179 @@
+#! /bin/sh
+# Generated automatically by configure.
+# Run this file to recreate the current configuration.
+# This directory was configured as follows,
+# on host bertha:
+#
+# ./configure
+#
+# Compiler output produced by configure, useful for debugging
+# configure, is in ./config.log if it exists.
+
+ac_cs_usage="Usage: ./config.status [--recheck] [--version] [--help]"
+for ac_option
+do
+ case "$ac_option" in
+ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+ echo "running ${CONFIG_SHELL-/bin/sh} ./configure --no-create --no-recursion"
+ exec ${CONFIG_SHELL-/bin/sh} ./configure --no-create --no-recursion ;;
+ -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
+ echo "./config.status generated by autoconf version 2.12"
+ exit 0 ;;
+ -help | --help | --hel | --he | --h)
+ echo "$ac_cs_usage"; exit 0 ;;
+ *) echo "$ac_cs_usage"; exit 1 ;;
+ esac
+done
+
+ac_given_srcdir=.
+ac_given_INSTALL=" install_elinux -p"
+
+trap 'rm -fr Makefile conftest*; exit 1' 1 2 15
+
+# Protect against being on the right side of a sed subst in config.status.
+sed 's/%@/@@/; s/@%/@@/; s/%g$/@g/; /@g$/s/[\\&%]/\\&/g;
+ s/@@/%@/; s/@@/@%/; s/@g$/%g/' > conftest.subs <<\CEOF
+/^[ ]*VPATH[ ]*=[^:]*$/d
+
+s%@CFLAGS@%-g -O2%g
+s%@CPPFLAGS@%%g
+s%@CXXFLAGS@%%g
+s%@DEFS@% -DHAVE_MALLOC_H=1 -DHAVE_ETHER_HOSTTON=1 -DHAVE_STRERROR=1 -DHAVE_NET_IF_ARP_H=1 %g
+s%@LDFLAGS@%%g
+s%@LIBS@%%g
+s%@exec_prefix@%${prefix}%g
+s%@prefix@%/usr/local%g
+s%@program_transform_name@%s,x,x,%g
+s%@bindir@%${exec_prefix}/bin%g
+s%@sbindir@%${exec_prefix}/sbin%g
+s%@libexecdir@%${exec_prefix}/libexec%g
+s%@datadir@%${prefix}/share%g
+s%@sysconfdir@%${prefix}/etc%g
+s%@sharedstatedir@%${prefix}/com%g
+s%@localstatedir@%${prefix}/var%g
+s%@libdir@%${exec_prefix}/lib%g
+s%@includedir@%${prefix}/include%g
+s%@oldincludedir@%/usr/include%g
+s%@infodir@%${prefix}/info%g
+s%@mandir@%${prefix}/man%g
+s%@host@%i686-pc-linux-gnu%g
+s%@host_alias@%i686-pc-linux-gnu%g
+s%@host_cpu@%i686%g
+s%@host_vendor@%pc%g
+s%@host_os@%linux-gnu%g
+s%@target@%i686-pc-linux-gnu%g
+s%@target_alias@%i686-pc-linux-gnu%g
+s%@target_cpu@%i686%g
+s%@target_vendor@%pc%g
+s%@target_os@%linux-gnu%g
+s%@build@%i686-pc-linux-gnu%g
+s%@build_alias@%i686-pc-linux-gnu%g
+s%@build_cpu@%i686%g
+s%@build_vendor@%pc%g
+s%@build_os@%linux-gnu%g
+s%@SHLICC2@%%g
+s%@CC@%gcc%g
+s%@CPP@%gcc -E%g
+s%@V_LEX@%flex -Ppcap_%g
+s%@V_YACC@%bison -y -p pcap_%g
+s%@V_RANLIB@%ranlib%g
+s%@V_CCOPT@%-O2%g
+s%@V_INCLS@% -Ilinux-include%g
+s%@V_PCAP@%linux%g
+s%@INSTALL_PROGRAM@%${INSTALL}%g
+s%@INSTALL_DATA@%${INSTALL} -m 644%g
+
+CEOF
+
+# Split the substitutions into bite-sized pieces for seds with
+# small command number limits, like on Digital OSF/1 and HP-UX.
+ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
+ac_file=1 # Number of current file.
+ac_beg=1 # First line for current file.
+ac_end=$ac_max_sed_cmds # Line after last line for current file.
+ac_more_lines=:
+ac_sed_cmds=""
+while $ac_more_lines; do
+ if test $ac_beg -gt 1; then
+ sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
+ else
+ sed "${ac_end}q" conftest.subs > conftest.s$ac_file
+ fi
+ if test ! -s conftest.s$ac_file; then
+ ac_more_lines=false
+ rm -f conftest.s$ac_file
+ else
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds="sed -f conftest.s$ac_file"
+ else
+ ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
+ fi
+ ac_file=`expr $ac_file + 1`
+ ac_beg=$ac_end
+ ac_end=`expr $ac_end + $ac_max_sed_cmds`
+ fi
+done
+if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds=cat
+fi
+
+CONFIG_FILES=${CONFIG_FILES-"Makefile"}
+for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case "$ac_file" in
+ *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+ ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+ *) ac_file_in="${ac_file}.in" ;;
+ esac
+
+ # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
+
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+ # The file is in a subdirectory.
+ test ! -d "$ac_dir" && mkdir "$ac_dir"
+ ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
+ else
+ ac_dir_suffix= ac_dots=
+ fi
+
+ case "$ac_given_srcdir" in
+ .) srcdir=.
+ if test -z "$ac_dots"; then top_srcdir=.
+ else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
+ /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
+ *) # Relative path.
+ srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
+ top_srcdir="$ac_dots$ac_given_srcdir" ;;
+ esac
+
+ case "$ac_given_INSTALL" in
+ [/$]*) INSTALL="$ac_given_INSTALL" ;;
+ *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
+ esac
+
+ echo creating "$ac_file"
+ rm -f "$ac_file"
+ configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
+ case "$ac_file" in
+ *Makefile*) ac_comsub="1i\\
+# $configure_input" ;;
+ *) ac_comsub= ;;
+ esac
+
+ ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+ sed -e "$ac_comsub
+s%@configure_input@%$configure_input%g
+s%@srcdir@%$srcdir%g
+s%@top_srcdir@%$top_srcdir%g
+s%@INSTALL@%$INSTALL%g
+" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
+fi; done
+rm -f conftest.s*
+
+
+
+exit 0
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/config.sub b/package/etrax-tools/src/e100boot/libpcap-0.4/config.sub
new file mode 100755
index 000000000..043252494
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/config.sub
@@ -0,0 +1,927 @@
+#! /bin/sh
+# Configuration validation subroutine script, version 1.1.
+# Copyright (C) 1991, 92, 93, 94, 95, 1996 Free Software Foundation, Inc.
+# This file is (in principle) common to ALL GNU software.
+# The presence of a machine in this file suggests that SOME GNU software
+# can handle that machine. It does not imply ALL GNU software can.
+#
+# This file is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place - Suite 330,
+# Boston, MA 02111-1307, USA.
+
+# As a special exception to the GNU General Public License, if you
+# distribute this file as part of a program that contains a
+# configuration script generated by Autoconf, you may include it under
+# the same distribution terms that you use for the rest of that program.
+
+# Configuration subroutine to validate and canonicalize a configuration type.
+# Supply the specified configuration type as an argument.
+# If it is invalid, we print an error message on stderr and exit with code 1.
+# Otherwise, we print the canonical config type on stdout and succeed.
+
+# This file is supposed to be the same for all GNU packages
+# and recognize all the CPU types, system types and aliases
+# that are meaningful with *any* GNU software.
+# Each package is responsible for reporting which valid configurations
+# it does not support. The user should be able to distinguish
+# a failure to support a valid configuration from a meaningless
+# configuration.
+
+# The goal of this file is to map all the various variations of a given
+# machine specification into a single specification in the form:
+# CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM
+# or in some cases, the newer four-part form:
+# CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM
+# It is wrong to echo any other type of specification.
+
+if [ x$1 = x ]
+then
+ echo Configuration name missing. 1>&2
+ echo "Usage: $0 CPU-MFR-OPSYS" 1>&2
+ echo "or $0 ALIAS" 1>&2
+ echo where ALIAS is a recognized configuration type. 1>&2
+ exit 1
+fi
+
+# First pass through any local machine types.
+case $1 in
+ *local*)
+ echo $1
+ exit 0
+ ;;
+ *)
+ ;;
+esac
+
+# Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any).
+# Here we must recognize all the valid KERNEL-OS combinations.
+maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'`
+case $maybe_os in
+ linux-gnu*)
+ os=-$maybe_os
+ basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'`
+ ;;
+ *)
+ basic_machine=`echo $1 | sed 's/-[^-]*$//'`
+ if [ $basic_machine != $1 ]
+ then os=`echo $1 | sed 's/.*-/-/'`
+ else os=; fi
+ ;;
+esac
+
+### Let's recognize common machines as not being operating systems so
+### that things like config.sub decstation-3100 work. We also
+### recognize some manufacturers as not being operating systems, so we
+### can provide default operating systems below.
+case $os in
+ -sun*os*)
+ # Prevent following clause from handling this invalid input.
+ ;;
+ -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \
+ -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \
+ -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \
+ -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\
+ -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \
+ -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \
+ -apple)
+ os=
+ basic_machine=$1
+ ;;
+ -hiux*)
+ os=-hiuxwe2
+ ;;
+ -sco5)
+ os=sco3.2v5
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
+ -sco4)
+ os=-sco3.2v4
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
+ -sco3.2.[4-9]*)
+ os=`echo $os | sed -e 's/sco3.2./sco3.2v/'`
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
+ -sco3.2v[4-9]*)
+ # Don't forget version if it is 3.2v4 or newer.
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
+ -sco*)
+ os=-sco3.2v2
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
+ -isc)
+ os=-isc2.2
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
+ -clix*)
+ basic_machine=clipper-intergraph
+ ;;
+ -isc*)
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'`
+ ;;
+ -lynx*)
+ os=-lynxos
+ ;;
+ -ptx*)
+ basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'`
+ ;;
+ -windowsnt*)
+ os=`echo $os | sed -e 's/windowsnt/winnt/'`
+ ;;
+ -psos*)
+ os=-psos
+ ;;
+esac
+
+# Decode aliases for certain CPU-COMPANY combinations.
+case $basic_machine in
+ # Recognize the basic CPU types without company name.
+ # Some are omitted here because they have special meanings below.
+ tahoe | i860 | m68k | m68000 | m88k | ns32k | arm \
+ | arme[lb] | pyramid \
+ | tron | a29k | 580 | i960 | h8300 | hppa | hppa1.0 | hppa1.1 \
+ | alpha | we32k | ns16k | clipper | i370 | sh \
+ | powerpc | powerpcle | 1750a | dsp16xx | mips64 | mipsel \
+ | pdp11 | mips64el | mips64orion | mips64orionel \
+ | sparc | sparclet | sparclite | sparc64)
+ basic_machine=$basic_machine-unknown
+ ;;
+ # We use `pc' rather than `unknown'
+ # because (1) that's what they normally are, and
+ # (2) the word "unknown" tends to confuse beginning users.
+ i[3456]86)
+ basic_machine=$basic_machine-pc
+ ;;
+ # Object if more than one company name word.
+ *-*-*)
+ echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2
+ exit 1
+ ;;
+ # Recognize the basic CPU types with company name.
+ vax-* | tahoe-* | i[3456]86-* | i860-* | m68k-* | m68000-* | m88k-* \
+ | sparc-* | ns32k-* | fx80-* | arm-* | c[123]* \
+ | mips-* | pyramid-* | tron-* | a29k-* | romp-* | rs6000-* | power-* \
+ | none-* | 580-* | cray2-* | h8300-* | i960-* | xmp-* | ymp-* \
+ | hppa-* | hppa1.0-* | hppa1.1-* | alpha-* | we32k-* | cydra-* | ns16k-* \
+ | pn-* | np1-* | xps100-* | clipper-* | orion-* | sparclite-* \
+ | pdp11-* | sh-* | powerpc-* | powerpcle-* | sparc64-* | mips64-* | mipsel-* \
+ | mips64el-* | mips64orion-* | mips64orionel-* | f301-*)
+ ;;
+ # Recognize the various machine names and aliases which stand
+ # for a CPU type and a company and sometimes even an OS.
+ 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc)
+ basic_machine=m68000-att
+ ;;
+ 3b*)
+ basic_machine=we32k-att
+ ;;
+ alliant | fx80)
+ basic_machine=fx80-alliant
+ ;;
+ altos | altos3068)
+ basic_machine=m68k-altos
+ ;;
+ am29k)
+ basic_machine=a29k-none
+ os=-bsd
+ ;;
+ amdahl)
+ basic_machine=580-amdahl
+ os=-sysv
+ ;;
+ amiga | amiga-*)
+ basic_machine=m68k-cbm
+ ;;
+ amigados)
+ basic_machine=m68k-cbm
+ os=-amigados
+ ;;
+ amigaunix | amix)
+ basic_machine=m68k-cbm
+ os=-sysv4
+ ;;
+ apollo68)
+ basic_machine=m68k-apollo
+ os=-sysv
+ ;;
+ aux)
+ basic_machine=m68k-apple
+ os=-aux
+ ;;
+ balance)
+ basic_machine=ns32k-sequent
+ os=-dynix
+ ;;
+ convex-c1)
+ basic_machine=c1-convex
+ os=-bsd
+ ;;
+ convex-c2)
+ basic_machine=c2-convex
+ os=-bsd
+ ;;
+ convex-c32)
+ basic_machine=c32-convex
+ os=-bsd
+ ;;
+ convex-c34)
+ basic_machine=c34-convex
+ os=-bsd
+ ;;
+ convex-c38)
+ basic_machine=c38-convex
+ os=-bsd
+ ;;
+ cray | ymp)
+ basic_machine=ymp-cray
+ os=-unicos
+ ;;
+ cray2)
+ basic_machine=cray2-cray
+ os=-unicos
+ ;;
+ [ctj]90-cray)
+ basic_machine=c90-cray
+ os=-unicos
+ ;;
+ crds | unos)
+ basic_machine=m68k-crds
+ ;;
+ da30 | da30-*)
+ basic_machine=m68k-da30
+ ;;
+ decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn)
+ basic_machine=mips-dec
+ ;;
+ delta | 3300 | motorola-3300 | motorola-delta \
+ | 3300-motorola | delta-motorola)
+ basic_machine=m68k-motorola
+ ;;
+ delta88)
+ basic_machine=m88k-motorola
+ os=-sysv3
+ ;;
+ dpx20 | dpx20-*)
+ basic_machine=rs6000-bull
+ os=-bosx
+ ;;
+ dpx2* | dpx2*-bull)
+ basic_machine=m68k-bull
+ os=-sysv3
+ ;;
+ ebmon29k)
+ basic_machine=a29k-amd
+ os=-ebmon
+ ;;
+ elxsi)
+ basic_machine=elxsi-elxsi
+ os=-bsd
+ ;;
+ encore | umax | mmax)
+ basic_machine=ns32k-encore
+ ;;
+ fx2800)
+ basic_machine=i860-alliant
+ ;;
+ genix)
+ basic_machine=ns32k-ns
+ ;;
+ gmicro)
+ basic_machine=tron-gmicro
+ os=-sysv
+ ;;
+ h3050r* | hiux*)
+ basic_machine=hppa1.1-hitachi
+ os=-hiuxwe2
+ ;;
+ h8300hms)
+ basic_machine=h8300-hitachi
+ os=-hms
+ ;;
+ harris)
+ basic_machine=m88k-harris
+ os=-sysv3
+ ;;
+ hp300-*)
+ basic_machine=m68k-hp
+ ;;
+ hp300bsd)
+ basic_machine=m68k-hp
+ os=-bsd
+ ;;
+ hp300hpux)
+ basic_machine=m68k-hp
+ os=-hpux
+ ;;
+ hp9k2[0-9][0-9] | hp9k31[0-9])
+ basic_machine=m68000-hp
+ ;;
+ hp9k3[2-9][0-9])
+ basic_machine=m68k-hp
+ ;;
+ hp9k7[0-9][0-9] | hp7[0-9][0-9] | hp9k8[0-9]7 | hp8[0-9]7)
+ basic_machine=hppa1.1-hp
+ ;;
+ hp9k8[0-9][0-9] | hp8[0-9][0-9])
+ basic_machine=hppa1.0-hp
+ ;;
+ hppa-next)
+ os=-nextstep3
+ ;;
+ i370-ibm* | ibm*)
+ basic_machine=i370-ibm
+ os=-mvs
+ ;;
+# I'm not sure what "Sysv32" means. Should this be sysv3.2?
+ i[3456]86v32)
+ basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
+ os=-sysv32
+ ;;
+ i[3456]86v4*)
+ basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
+ os=-sysv4
+ ;;
+ i[3456]86v)
+ basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
+ os=-sysv
+ ;;
+ i[3456]86sol2)
+ basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'`
+ os=-solaris2
+ ;;
+ iris | iris4d)
+ basic_machine=mips-sgi
+ case $os in
+ -irix*)
+ ;;
+ *)
+ os=-irix4
+ ;;
+ esac
+ ;;
+ isi68 | isi)
+ basic_machine=m68k-isi
+ os=-sysv
+ ;;
+ m88k-omron*)
+ basic_machine=m88k-omron
+ ;;
+ magnum | m3230)
+ basic_machine=mips-mips
+ os=-sysv
+ ;;
+ merlin)
+ basic_machine=ns32k-utek
+ os=-sysv
+ ;;
+ miniframe)
+ basic_machine=m68000-convergent
+ ;;
+ mips3*-*)
+ basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`
+ ;;
+ mips3*)
+ basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown
+ ;;
+ ncr3000)
+ basic_machine=i486-ncr
+ os=-sysv4
+ ;;
+ news | news700 | news800 | news900)
+ basic_machine=m68k-sony
+ os=-newsos
+ ;;
+ news1000)
+ basic_machine=m68030-sony
+ os=-newsos
+ ;;
+ news-3600 | risc-news)
+ basic_machine=mips-sony
+ os=-newsos
+ ;;
+ next | m*-next )
+ basic_machine=m68k-next
+ case $os in
+ -nextstep* )
+ ;;
+ -ns2*)
+ os=-nextstep2
+ ;;
+ *)
+ os=-nextstep3
+ ;;
+ esac
+ ;;
+ nh3000)
+ basic_machine=m68k-harris
+ os=-cxux
+ ;;
+ nh[45]000)
+ basic_machine=m88k-harris
+ os=-cxux
+ ;;
+ nindy960)
+ basic_machine=i960-intel
+ os=-nindy
+ ;;
+ np1)
+ basic_machine=np1-gould
+ ;;
+ pa-hitachi)
+ basic_machine=hppa1.1-hitachi
+ os=-hiuxwe2
+ ;;
+ paragon)
+ basic_machine=i860-intel
+ os=-osf
+ ;;
+ pbd)
+ basic_machine=sparc-tti
+ ;;
+ pbb)
+ basic_machine=m68k-tti
+ ;;
+ pc532 | pc532-*)
+ basic_machine=ns32k-pc532
+ ;;
+ pentium | p5)
+ basic_machine=i586-intel
+ ;;
+ pentiumpro | p6)
+ basic_machine=i686-intel
+ ;;
+ pentium-* | p5-*)
+ basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
+ pentiumpro-* | p6-*)
+ basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
+ k5)
+ # We don't have specific support for AMD's K5 yet, so just call it a Pentium
+ basic_machine=i586-amd
+ ;;
+ nexen)
+ # We don't have specific support for Nexgen yet, so just call it a Pentium
+ basic_machine=i586-nexgen
+ ;;
+ pn)
+ basic_machine=pn-gould
+ ;;
+ power) basic_machine=rs6000-ibm
+ ;;
+ ppc) basic_machine=powerpc-unknown
+ ;;
+ ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
+ ppcle | powerpclittle | ppc-le | powerpc-little)
+ basic_machine=powerpcle-unknown
+ ;;
+ ppcle-* | powerpclittle-*)
+ basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'`
+ ;;
+ ps2)
+ basic_machine=i386-ibm
+ ;;
+ rm[46]00)
+ basic_machine=mips-siemens
+ ;;
+ rtpc | rtpc-*)
+ basic_machine=romp-ibm
+ ;;
+ sequent)
+ basic_machine=i386-sequent
+ ;;
+ sh)
+ basic_machine=sh-hitachi
+ os=-hms
+ ;;
+ sps7)
+ basic_machine=m68k-bull
+ os=-sysv2
+ ;;
+ spur)
+ basic_machine=spur-unknown
+ ;;
+ sun2)
+ basic_machine=m68000-sun
+ ;;
+ sun2os3)
+ basic_machine=m68000-sun
+ os=-sunos3
+ ;;
+ sun2os4)
+ basic_machine=m68000-sun
+ os=-sunos4
+ ;;
+ sun3os3)
+ basic_machine=m68k-sun
+ os=-sunos3
+ ;;
+ sun3os4)
+ basic_machine=m68k-sun
+ os=-sunos4
+ ;;
+ sun4os3)
+ basic_machine=sparc-sun
+ os=-sunos3
+ ;;
+ sun4os4)
+ basic_machine=sparc-sun
+ os=-sunos4
+ ;;
+ sun4sol2)
+ basic_machine=sparc-sun
+ os=-solaris2
+ ;;
+ sun3 | sun3-*)
+ basic_machine=m68k-sun
+ ;;
+ sun4)
+ basic_machine=sparc-sun
+ ;;
+ sun386 | sun386i | roadrunner)
+ basic_machine=i386-sun
+ ;;
+ symmetry)
+ basic_machine=i386-sequent
+ os=-dynix
+ ;;
+ tower | tower-32)
+ basic_machine=m68k-ncr
+ ;;
+ udi29k)
+ basic_machine=a29k-amd
+ os=-udi
+ ;;
+ ultra3)
+ basic_machine=a29k-nyu
+ os=-sym1
+ ;;
+ vaxv)
+ basic_machine=vax-dec
+ os=-sysv
+ ;;
+ vms)
+ basic_machine=vax-dec
+ os=-vms
+ ;;
+ vpp*|vx|vx-*)
+ basic_machine=f301-fujitsu
+ ;;
+ vxworks960)
+ basic_machine=i960-wrs
+ os=-vxworks
+ ;;
+ vxworks68)
+ basic_machine=m68k-wrs
+ os=-vxworks
+ ;;
+ vxworks29k)
+ basic_machine=a29k-wrs
+ os=-vxworks
+ ;;
+ xmp)
+ basic_machine=xmp-cray
+ os=-unicos
+ ;;
+ xps | xps100)
+ basic_machine=xps100-honeywell
+ ;;
+ none)
+ basic_machine=none-none
+ os=-none
+ ;;
+
+# Here we handle the default manufacturer of certain CPU types. It is in
+# some cases the only manufacturer, in others, it is the most popular.
+ mips)
+ basic_machine=mips-mips
+ ;;
+ romp)
+ basic_machine=romp-ibm
+ ;;
+ rs6000)
+ basic_machine=rs6000-ibm
+ ;;
+ vax)
+ basic_machine=vax-dec
+ ;;
+ pdp11)
+ basic_machine=pdp11-dec
+ ;;
+ we32k)
+ basic_machine=we32k-att
+ ;;
+ sparc)
+ basic_machine=sparc-sun
+ ;;
+ cydra)
+ basic_machine=cydra-cydrome
+ ;;
+ orion)
+ basic_machine=orion-highlevel
+ ;;
+ orion105)
+ basic_machine=clipper-highlevel
+ ;;
+ *)
+ echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2
+ exit 1
+ ;;
+esac
+
+# Here we canonicalize certain aliases for manufacturers.
+case $basic_machine in
+ *-digital*)
+ basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'`
+ ;;
+ *-commodore*)
+ basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'`
+ ;;
+ *)
+ ;;
+esac
+
+# Decode manufacturer-specific aliases for certain operating systems.
+
+if [ x"$os" != x"" ]
+then
+case $os in
+ # First match some system type aliases
+ # that might get confused with valid system types.
+ # -solaris* is a basic system type, with this one exception.
+ -solaris1 | -solaris1.*)
+ os=`echo $os | sed -e 's|solaris1|sunos4|'`
+ ;;
+ -solaris)
+ os=-solaris2
+ ;;
+ -unixware* | svr4*)
+ os=-sysv4
+ ;;
+ -gnu/linux*)
+ os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'`
+ ;;
+ # First accept the basic system types.
+ # The portable systems comes first.
+ # Each alternative MUST END IN A *, to match a version number.
+ # -sysv* is not here because it comes later, after sysvr4.
+ -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \
+ | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\
+ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \
+ | -amigados* | -msdos* | -newsos* | -unicos* | -aof* | -aos* \
+ | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \
+ | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \
+ | -hiux* | -386bsd* | -netbsd* | -openbsd* | -freebsd* | -riscix* \
+ | -lynxos* | -bosx* | -nextstep* | -cxux* | -aout* | -elf* \
+ | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \
+ | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \
+ | -cygwin32* | -pe* | -psos* | -moss* | -proelf* | -rtems* \
+ | -linux-gnu* | -uxpv*)
+ # Remember, each alternative MUST END IN *, to match a version number.
+ ;;
+ -linux*)
+ os=`echo $os | sed -e 's|linux|linux-gnu|'`
+ ;;
+ -sunos5*)
+ os=`echo $os | sed -e 's|sunos5|solaris2|'`
+ ;;
+ -sunos6*)
+ os=`echo $os | sed -e 's|sunos6|solaris3|'`
+ ;;
+ -osfrose*)
+ os=-osfrose
+ ;;
+ -osf*)
+ os=-osf
+ ;;
+ -utek*)
+ os=-bsd
+ ;;
+ -dynix*)
+ os=-bsd
+ ;;
+ -acis*)
+ os=-aos
+ ;;
+ -ctix* | -uts*)
+ os=-sysv
+ ;;
+ -ns2 )
+ os=-nextstep2
+ ;;
+ # Preserve the version number of sinix5.
+ -sinix5.*)
+ os=`echo $os | sed -e 's|sinix|sysv|'`
+ ;;
+ -sinix*)
+ os=-sysv4
+ ;;
+ -triton*)
+ os=-sysv3
+ ;;
+ -oss*)
+ os=-sysv3
+ ;;
+ -svr4)
+ os=-sysv4
+ ;;
+ -svr3)
+ os=-sysv3
+ ;;
+ -sysvr4)
+ os=-sysv4
+ ;;
+ # This must come after -sysvr4.
+ -sysv*)
+ ;;
+ -xenix)
+ os=-xenix
+ ;;
+ -none)
+ ;;
+ *)
+ # Get rid of the `-' at the beginning of $os.
+ os=`echo $os | sed 's/[^-]*-//'`
+ echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2
+ exit 1
+ ;;
+esac
+else
+
+# Here we handle the default operating systems that come with various machines.
+# The value should be what the vendor currently ships out the door with their
+# machine or put another way, the most popular os provided with the machine.
+
+# Note that if you're going to try to match "-MANUFACTURER" here (say,
+# "-sun"), then you have to tell the case statement up towards the top
+# that MANUFACTURER isn't an operating system. Otherwise, code above
+# will signal an error saying that MANUFACTURER isn't an operating
+# system, and we'll never get to this point.
+
+case $basic_machine in
+ *-acorn)
+ os=-riscix1.2
+ ;;
+ arm*-semi)
+ os=-aout
+ ;;
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+ *-cbm)
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+ *-dg)
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+ *-dolphin)
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+ ;;
+ m68k-ccur)
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+ *-sequent)
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+ *-crds)
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+ *-ns)
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+ ;;
+ i370-*)
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+ *-next)
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+ *-gould)
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+ ;;
+ *-highlevel)
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+ *-encore)
+ os=-bsd
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+ *-sgi)
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+ *-siemens)
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+ *-masscomp)
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+ f301-fujitsu)
+ os=-uxpv
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+ *)
+ os=-none
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+
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diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/configure b/package/etrax-tools/src/e100boot/libpcap-0.4/configure
new file mode 100755
index 000000000..6bd9d5f16
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/configure
@@ -0,0 +1,2137 @@
+#! /bin/sh
+
+# Guess values for system-dependent variables and create Makefiles.
+# Generated automatically using autoconf version 2.12
+# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+
+# Defaults:
+ac_help=
+ac_default_prefix=/usr/local
+# Any additions from configure.in:
+ac_help="$ac_help
+ --without-gcc don't use gcc"
+ac_help="$ac_help
+ --with-pcap=TYPE use packet capture TYPE"
+ac_help="$ac_help
+ --without-flex don't use flex"
+ac_help="$ac_help
+ --without-bison don't use bison"
+
+# Initialize some variables set by options.
+# The variables have the same names as the options, with
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+build=NONE
+cache_file=./config.cache
+exec_prefix=NONE
+host=NONE
+no_create=
+nonopt=NONE
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+target=NONE
+verbose=
+x_includes=NONE
+x_libraries=NONE
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datadir='${prefix}/share'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+libdir='${exec_prefix}/lib'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+infodir='${prefix}/info'
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+
+# Initialize some other variables.
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+ --libexecdir=DIR program executables in DIR [EPREFIX/libexec]
+ --datadir=DIR read-only architecture-independent data in DIR
+ [PREFIX/share]
+ --sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc]
+ --sharedstatedir=DIR modifiable architecture-independent data in DIR
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+
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+ # Try the directory containing this script, then its parent.
+ ac_prog=$0
+ ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`
+ test "x$ac_confdir" = "x$ac_prog" && ac_confdir=.
+ srcdir=$ac_confdir
+ if test ! -r $srcdir/$ac_unique_file; then
+ srcdir=..
+ fi
+else
+ ac_srcdir_defaulted=no
+fi
+if test ! -r $srcdir/$ac_unique_file; then
+ if test "$ac_srcdir_defaulted" = yes; then
+ { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; }
+ else
+ { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; }
+ fi
+fi
+srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
+
+# Prefer explicitly selected file to automatically selected ones.
+if test -z "$CONFIG_SITE"; then
+ if test "x$prefix" != xNONE; then
+ CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+ else
+ CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+ fi
+fi
+for ac_site_file in $CONFIG_SITE; do
+ if test -r "$ac_site_file"; then
+ echo "loading site script $ac_site_file"
+ . "$ac_site_file"
+ fi
+done
+
+if test -r "$cache_file"; then
+ echo "loading cache $cache_file"
+ . $cache_file
+else
+ echo "creating cache $cache_file"
+ > $cache_file
+fi
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then
+ # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.
+ if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then
+ ac_n= ac_c='
+' ac_t=' '
+ else
+ ac_n=-n ac_c= ac_t=
+ fi
+else
+ ac_n= ac_c='\c' ac_t=
+fi
+
+
+
+ac_aux_dir=
+for ac_dir in $srcdir $srcdir/.. $srcdir/../..; do
+ if test -f $ac_dir/install-sh; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/install-sh -c"
+ break
+ elif test -f $ac_dir/install.sh; then
+ ac_aux_dir=$ac_dir
+ ac_install_sh="$ac_aux_dir/install.sh -c"
+ break
+ fi
+done
+if test -z "$ac_aux_dir"; then
+ { echo "configure: error: can not find install-sh or install.sh in $srcdir $srcdir/.. $srcdir/../.." 1>&2; exit 1; }
+fi
+ac_config_guess=$ac_aux_dir/config.guess
+ac_config_sub=$ac_aux_dir/config.sub
+ac_configure=$ac_aux_dir/configure # This should be Cygnus configure.
+
+
+# Do some error checking and defaulting for the host and target type.
+# The inputs are:
+# configure --host=HOST --target=TARGET --build=BUILD NONOPT
+#
+# The rules are:
+# 1. You are not allowed to specify --host, --target, and nonopt at the
+# same time.
+# 2. Host defaults to nonopt.
+# 3. If nonopt is not specified, then host defaults to the current host,
+# as determined by config.guess.
+# 4. Target and build default to nonopt.
+# 5. If nonopt is not specified, then target and build default to host.
+
+# The aliases save the names the user supplied, while $host etc.
+# will get canonicalized.
+case $host---$target---$nonopt in
+NONE---*---* | *---NONE---* | *---*---NONE) ;;
+*) { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; } ;;
+esac
+
+
+# Make sure we can run config.sub.
+if $ac_config_sub sun4 >/dev/null 2>&1; then :
+else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking host system type""... $ac_c" 1>&6
+echo "configure:578: checking host system type" >&5
+
+host_alias=$host
+case "$host_alias" in
+NONE)
+ case $nonopt in
+ NONE)
+ if host_alias=`$ac_config_guess`; then :
+ else { echo "configure: error: can not guess host type; you must specify one" 1>&2; exit 1; }
+ fi ;;
+ *) host_alias=$nonopt ;;
+ esac ;;
+esac
+
+host=`$ac_config_sub $host_alias`
+host_cpu=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+host_vendor=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$host" 1>&6
+
+echo $ac_n "checking target system type""... $ac_c" 1>&6
+echo "configure:599: checking target system type" >&5
+
+target_alias=$target
+case "$target_alias" in
+NONE)
+ case $nonopt in
+ NONE) target_alias=$host_alias ;;
+ *) target_alias=$nonopt ;;
+ esac ;;
+esac
+
+target=`$ac_config_sub $target_alias`
+target_cpu=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+target_vendor=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$target" 1>&6
+
+echo $ac_n "checking build system type""... $ac_c" 1>&6
+echo "configure:617: checking build system type" >&5
+
+build_alias=$build
+case "$build_alias" in
+NONE)
+ case $nonopt in
+ NONE) build_alias=$host_alias ;;
+ *) build_alias=$nonopt ;;
+ esac ;;
+esac
+
+build=`$ac_config_sub $build_alias`
+build_cpu=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\1/'`
+build_vendor=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\2/'`
+build_os=`echo $build | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'`
+echo "$ac_t""$build" 1>&6
+
+test "$host_alias" != "$target_alias" &&
+ test "$program_prefix$program_suffix$program_transform_name" = \
+ NONENONEs,x,x, &&
+ program_prefix=${target_alias}-
+
+
+umask 002
+
+if test -z "$PWD" ; then
+ PWD=`pwd`
+fi
+
+
+
+
+
+ # Check whether --with-gcc or --without-gcc was given.
+if test "${with_gcc+set}" = set; then
+ withval="$with_gcc"
+ :
+fi
+
+ V_CCOPT="-O"
+ V_INCLS=""
+ if test "${srcdir}" != "." ; then
+ V_INCLS="-I\$\(srcdir\)"
+ fi
+ if test "${CFLAGS+set}" = set; then
+ LBL_CFLAGS="$CFLAGS"
+ fi
+ if test -z "$CC" ; then
+ case "$target_os" in
+
+ bsdi*)
+ # Extract the first word of "shlicc2", so it can be a program name with args.
+set dummy shlicc2; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:671: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_SHLICC2'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$SHLICC2"; then
+ ac_cv_prog_SHLICC2="$SHLICC2" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_SHLICC2="yes"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+ test -z "$ac_cv_prog_SHLICC2" && ac_cv_prog_SHLICC2="no"
+fi
+fi
+SHLICC2="$ac_cv_prog_SHLICC2"
+if test -n "$SHLICC2"; then
+ echo "$ac_t""$SHLICC2" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ if test $SHLICC2 = yes ; then
+ CC=shlicc2
+ export CC
+ fi
+ ;;
+ esac
+ fi
+ if test -z "$CC" -a "$with_gcc" = no ; then
+ CC=cc
+ export CC
+ fi
+ # Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:711: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_CC="gcc"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+ echo "$ac_t""$CC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+if test -z "$CC"; then
+ # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:740: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ ac_prog_rejected=no
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
+ ac_prog_rejected=yes
+ continue
+ fi
+ ac_cv_prog_CC="cc"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+if test $ac_prog_rejected = yes; then
+ # We found a bogon in the path, so make sure we never use it.
+ set dummy $ac_cv_prog_CC
+ shift
+ if test $# -gt 0; then
+ # We chose a different compiler from the bogus one.
+ # However, it has the same basename, so the bogon will be chosen
+ # first if we set CC to just the basename; use the full file name.
+ shift
+ set dummy "$ac_dir/$ac_word" "$@"
+ shift
+ ac_cv_prog_CC="$@"
+ fi
+fi
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+ echo "$ac_t""$CC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
+echo "configure:788: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+cat > conftest.$ac_ext <<EOF
+#line 798 "configure"
+#include "confdefs.h"
+main(){return(0);}
+EOF
+if { (eval echo configure:802: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
+ ac_cv_prog_cc_works=yes
+ # If we can't run a trivial program, we are probably using a cross compiler.
+ if (./conftest; exit) 2>/dev/null; then
+ ac_cv_prog_cc_cross=no
+ else
+ ac_cv_prog_cc_cross=yes
+ fi
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ ac_cv_prog_cc_works=no
+fi
+rm -fr conftest*
+
+echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
+if test $ac_cv_prog_cc_works = no; then
+ { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
+fi
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
+echo "configure:822: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
+echo "configure:827: checking whether we are using GNU C" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.c <<EOF
+#ifdef __GNUC__
+ yes;
+#endif
+EOF
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:836: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+ ac_cv_prog_gcc=yes
+else
+ ac_cv_prog_gcc=no
+fi
+fi
+
+echo "$ac_t""$ac_cv_prog_gcc" 1>&6
+
+if test $ac_cv_prog_gcc = yes; then
+ GCC=yes
+ ac_test_CFLAGS="${CFLAGS+set}"
+ ac_save_CFLAGS="$CFLAGS"
+ CFLAGS=
+ echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
+echo "configure:851: checking whether ${CC-cc} accepts -g" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ echo 'void f(){}' > conftest.c
+if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
+ ac_cv_prog_cc_g=yes
+else
+ ac_cv_prog_cc_g=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
+ if test "$ac_test_CFLAGS" = set; then
+ CFLAGS="$ac_save_CFLAGS"
+ elif test $ac_cv_prog_cc_g = yes; then
+ CFLAGS="-g -O2"
+ else
+ CFLAGS="-O2"
+ fi
+else
+ GCC=
+ test "${CFLAGS+set}" = set || CFLAGS="-g"
+fi
+
+ if test "$GCC" = yes ; then
+ if test "$SHLICC2" = yes ; then
+ ac_cv_lbl_gcc_vers=2
+ V_CCOPT="-O2"
+ else
+ echo $ac_n "checking gcc version""... $ac_c" 1>&6
+echo "configure:884: checking gcc version" >&5
+ if eval "test \"`echo '$''{'ac_cv_lbl_gcc_vers'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ ac_cv_lbl_gcc_vers=`$CC -v 2>&1 | \
+ sed -e '/^gcc version /!d' \
+ -e 's/^gcc version //' \
+ -e 's/ .*//' -e 's/^[^0-9]*//' \
+ -e 's/\..*//'`
+fi
+
+ echo "$ac_t""$ac_cv_lbl_gcc_vers" 1>&6
+ if test $ac_cv_lbl_gcc_vers -gt 1 ; then
+ V_CCOPT="-O2"
+ fi
+ fi
+ else
+ echo $ac_n "checking that $CC handles ansi prototypes""... $ac_c" 1>&6
+echo "configure:902: checking that $CC handles ansi prototypes" >&5
+ if eval "test \"`echo '$''{'ac_cv_lbl_cc_ansi_prototypes'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 907 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+int main() {
+int frob(int, char *)
+; return 0; }
+EOF
+if { (eval echo configure:914: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_lbl_cc_ansi_prototypes=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_lbl_cc_ansi_prototypes=no
+fi
+rm -f conftest*
+fi
+
+ echo "$ac_t""$ac_cv_lbl_cc_ansi_prototypes" 1>&6
+ if test $ac_cv_lbl_cc_ansi_prototypes = no ; then
+ case "$target_os" in
+
+ hpux*)
+ echo $ac_n "checking for HP-UX ansi compiler ($CC -Aa -D_HPUX_SOURCE)""... $ac_c" 1>&6
+echo "configure:932: checking for HP-UX ansi compiler ($CC -Aa -D_HPUX_SOURCE)" >&5
+ savedcflags="$CFLAGS"
+ CFLAGS="-Aa -D_HPUX_SOURCE $CFLAGS"
+ if eval "test \"`echo '$''{'ac_cv_lbl_cc_hpux_cc_aa'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 939 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+int main() {
+int frob(int, char *)
+; return 0; }
+EOF
+if { (eval echo configure:946: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_lbl_cc_hpux_cc_aa=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_lbl_cc_hpux_cc_aa=no
+fi
+rm -f conftest*
+fi
+
+ echo "$ac_t""$ac_cv_lbl_cc_hpux_cc_aa" 1>&6
+ if test $ac_cv_lbl_cc_hpux_cc_aa = no ; then
+ { echo "configure: error: see the INSTALL doc for more info" 1>&2; exit 1; }
+ fi
+ CFLAGS="$savedcflags"
+ V_CCOPT="-Aa $V_CCOPT"
+ cat >> confdefs.h <<\EOF
+#define _HPUX_SOURCE 1
+EOF
+
+ ;;
+
+ *)
+ { echo "configure: error: see the INSTALL doc for more info" 1>&2; exit 1; }
+ ;;
+ esac
+ fi
+ V_INCLS="$V_INCLS -I/usr/local/include"
+ LDFLAGS="$LDFLAGS -L/usr/local/lib"
+
+ case "$target_os" in
+
+ irix*)
+ V_CCOPT="$V_CCOPT -xansi -signed -g3"
+ ;;
+
+ osf*)
+ V_CCOPT="$V_CCOPT -std1 -g3"
+ ;;
+
+ ultrix*)
+ echo $ac_n "checking that Ultrix $CC hacks const in prototypes""... $ac_c" 1>&6
+echo "configure:990: checking that Ultrix $CC hacks const in prototypes" >&5
+ if eval "test \"`echo '$''{'ac_cv_lbl_cc_const_proto'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 995 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+int main() {
+struct a { int b; };
+ void c(const struct a *)
+; return 0; }
+EOF
+if { (eval echo configure:1003: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_lbl_cc_const_proto=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_lbl_cc_const_proto=no
+fi
+rm -f conftest*
+fi
+
+ echo "$ac_t""$ac_cv_lbl_cc_const_proto" 1>&6
+ if test $ac_cv_lbl_cc_const_proto = no ; then
+ cat >> confdefs.h <<\EOF
+#define const
+EOF
+
+ fi
+ ;;
+ esac
+ fi
+
+
+echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
+echo "configure:1028: checking how to run the C preprocessor" >&5
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+ CPP=
+fi
+if test -z "$CPP"; then
+if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ # This must be in double quotes, not single quotes, because CPP may get
+ # substituted into the Makefile and "${CC-cc}" will confuse make.
+ CPP="${CC-cc} -E"
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp.
+ cat > conftest.$ac_ext <<EOF
+#line 1043 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1049: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out`
+if test -z "$ac_err"; then
+ :
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CPP="${CC-cc} -E -traditional-cpp"
+ cat > conftest.$ac_ext <<EOF
+#line 1060 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1066: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out`
+if test -z "$ac_err"; then
+ :
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CPP=/lib/cpp
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+ ac_cv_prog_CPP="$CPP"
+fi
+ CPP="$ac_cv_prog_CPP"
+else
+ ac_cv_prog_CPP="$CPP"
+fi
+echo "$ac_t""$CPP" 1>&6
+
+for ac_hdr in malloc.h sys/ioccom.h sys/sockio.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:1092: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1097 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1102: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+
+if test "$GCC" = yes ; then
+ echo $ac_n "checking for ANSI ioctl definitions""... $ac_c" 1>&6
+echo "configure:1131: checking for ANSI ioctl definitions" >&5
+ if eval "test \"`echo '$''{'ac_cv_lbl_gcc_fixincludes'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1136 "configure"
+#include "confdefs.h"
+/*
+ * This generates a "duplicate case value" when fixincludes
+ * has not be run.
+ */
+# include <sys/types.h>
+# include <sys/time.h>
+# include <sys/ioctl.h>
+# ifdef HAVE_SYS_IOCCOM_H
+# include <sys/ioccom.h>
+# endif
+int main() {
+switch (0) {
+ case _IO('A', 1):;
+ case _IO('B', 1):;
+ }
+; return 0; }
+EOF
+if { (eval echo configure:1155: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_lbl_gcc_fixincludes=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_lbl_gcc_fixincludes=no
+fi
+rm -f conftest*
+fi
+
+ echo "$ac_t""$ac_cv_lbl_gcc_fixincludes" 1>&6
+ if test $ac_cv_lbl_gcc_fixincludes = no ; then
+ # Don't cache failure
+ unset ac_cv_lbl_gcc_fixincludes
+ { echo "configure: error: see the INSTALL for more info" 1>&2; exit 1; }
+ fi
+ fi
+
+for ac_func in ether_hostton strerror
+do
+echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
+echo "configure:1178: checking for $ac_func" >&5
+if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1183 "configure"
+#include "confdefs.h"
+/* System header to define __stub macros and hopefully few prototypes,
+ which can conflict with char $ac_func(); below. */
+#include <assert.h>
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char $ac_func();
+
+int main() {
+
+/* The GNU C library defines this for functions which it implements
+ to always fail with ENOSYS. Some functions are actually named
+ something starting with __ and the normal name is an alias. */
+#if defined (__stub_$ac_func) || defined (__stub___$ac_func)
+choke me
+#else
+$ac_func();
+#endif
+
+; return 0; }
+EOF
+if { (eval echo configure:1206: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest; then
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_func_$ac_func=no"
+fi
+rm -f conftest*
+fi
+
+if eval "test \"`echo '$ac_cv_func_'$ac_func`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_func=HAVE_`echo $ac_func | tr 'abcdefghijklmnopqrstuvwxyz' 'ABCDEFGHIJKLMNOPQRSTUVWXYZ'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_func 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+
+# Check whether --with-pcap or --without-pcap was given.
+if test "${with_pcap+set}" = set; then
+ withval="$with_pcap"
+ :
+fi
+
+echo $ac_n "checking packet capture type""... $ac_c" 1>&6
+echo "configure:1238: checking packet capture type" >&5
+if test ! -z "$with_pcap" ; then
+ V_PCAP="$withval"
+elif test -r /dev/bpf0 ; then
+ V_PCAP=bpf
+elif test -r /usr/include/net/pfilt.h ; then
+ V_PCAP=pf
+elif test -r /dev/enet ; then
+ V_PCAP=enet
+elif test -r /dev/nit ; then
+ V_PCAP=snit
+elif test -r /usr/include/sys/net/nit.h ; then
+ V_PCAP=nit
+elif test -r /usr/include/net/raw.h ; then
+ V_PCAP=snoop
+elif test -r /usr/include/sys/dlpi.h ; then
+ V_PCAP=dlpi
+elif test -r /usr/include/linux/socket.h ; then
+ V_PCAP=linux
+elif test -c /dev/bpf0 ; then # check again in case not readable
+ V_PCAP=bpf
+elif test -c /dev/enet ; then # check again in case not readable
+ V_PCAP=enet
+elif test -c /dev/nit ; then # check again in case not readable
+ V_PCAP=snit
+else
+ V_PCAP=null
+fi
+echo "$ac_t""$V_PCAP" 1>&6
+
+case "$V_PCAP" in
+
+dlpi)
+ for ac_hdr in sys/bufmod.h sys/dlpi_ext.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:1275: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1280 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1285: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+ echo $ac_n "checking for /dev/dlpi device""... $ac_c" 1>&6
+echo "configure:1312: checking for /dev/dlpi device" >&5
+ if test -c /dev/dlpi ; then
+ echo "$ac_t""yes" 1>&6
+ cat >> confdefs.h <<\EOF
+#define HAVE_DEV_DLPI 1
+EOF
+
+ else
+ echo "$ac_t""no" 1>&6
+ dir="/dev/dlpi"
+ echo $ac_n "checking for $dir directory""... $ac_c" 1>&6
+echo "configure:1323: checking for $dir directory" >&5
+ if test -d $dir ; then
+ echo "$ac_t""yes" 1>&6
+ cat >> confdefs.h <<EOF
+#define PCAP_DEV_PREFIX "$dir"
+EOF
+
+ else
+ echo "$ac_t""no" 1>&6
+ fi
+ fi
+ ;;
+
+linux)
+ for ac_hdr in net/if_arp.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:1341: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1346 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:1351: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+ echo $ac_n "checking Linux kernel version""... $ac_c" 1>&6
+echo "configure:1378: checking Linux kernel version" >&5
+ if eval "test \"`echo '$''{'ac_cv_linux_vers'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ ac_cv_linux_vers=`uname -r 2>&1 | \
+ sed -n -e '$s/.* //' -e '$s/\..*//p'`
+fi
+
+ echo "$ac_t""$ac_cv_linux_vers" 1>&6
+ if test $ac_cv_linux_vers -lt 2 ; then
+ { echo "configure: error: version 2 or higher required; see the INSTALL doc for more info" 1>&2; exit 1; }
+ fi
+ ;;
+
+null)
+ echo "configure: warning: cannot determine packet capture interface" 1>&2
+ echo "configure: warning: (see the INSTALL doc for more info)" 1>&2
+ ;;
+
+esac
+
+# Check whether --with-flex or --without-flex was given.
+if test "${with_flex+set}" = set; then
+ withval="$with_flex"
+ :
+fi
+
+ # Check whether --with-bison or --without-bison was given.
+if test "${with_bison+set}" = set; then
+ withval="$with_bison"
+ :
+fi
+
+ if test "$with_flex" = no ; then
+ V_LEX=lex
+ else
+ for ac_prog in flex
+do
+# Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1419: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_V_LEX'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$V_LEX"; then
+ ac_cv_prog_V_LEX="$V_LEX" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_V_LEX="$ac_prog"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+fi
+fi
+V_LEX="$ac_cv_prog_V_LEX"
+if test -n "$V_LEX"; then
+ echo "$ac_t""$V_LEX" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+test -n "$V_LEX" && break
+done
+test -n "$V_LEX" || V_LEX="lex"
+
+ fi
+ if test "$V_LEX" = flex ; then
+ # The -V flag was added in 2.4
+ echo $ac_n "checking for flex 2.4 or higher""... $ac_c" 1>&6
+echo "configure:1452: checking for flex 2.4 or higher" >&5
+ if eval "test \"`echo '$''{'ac_cv_lbl_flex_v24'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if flex -V >/dev/null 2>&1; then
+ ac_cv_lbl_flex_v24=yes
+ else
+ ac_cv_lbl_flex_v24=no
+ fi
+fi
+
+ echo "$ac_t""$ac_cv_lbl_flex_v24" 1>&6
+ if test $ac_cv_lbl_flex_v24 = no ; then
+ s="2.4 or higher required"
+ echo "configure: warning: ignoring obsolete flex executable ($s)" 1>&2
+ V_LEX=lex
+ fi
+ fi
+ if test "$with_bison" = no ; then
+ V_YACC=yacc
+ else
+ for ac_prog in bison
+do
+# Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1478: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_V_YACC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$V_YACC"; then
+ ac_cv_prog_V_YACC="$V_YACC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_V_YACC="$ac_prog"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+fi
+fi
+V_YACC="$ac_cv_prog_V_YACC"
+if test -n "$V_YACC"; then
+ echo "$ac_t""$V_YACC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+test -n "$V_YACC" && break
+done
+test -n "$V_YACC" || V_YACC="yacc"
+
+ fi
+ if test "$V_YACC" = bison ; then
+ V_YACC="$V_YACC -y"
+ fi
+ if test "$V_LEX" != lex -a "$V_YACC" = yacc -o "$V_LEX" = lex -a "$V_YACC" != yacc ; then
+ echo "configure: warning: don't have both flex and bison; reverting to lex/yacc" 1>&2
+ V_LEX=lex
+ V_YACC=yacc
+ fi
+ if test "$V_LEX" = flex -a -n "pcap_" ; then
+ V_LEX="$V_LEX -Ppcap_"
+ V_YACC="$V_YACC -p pcap_"
+ fi
+
+case "$target_os" in
+
+aix*)
+ cat >> confdefs.h <<\EOF
+#define _SUN 1
+EOF
+
+ ;;
+
+hpux9*)
+ cat >> confdefs.h <<\EOF
+#define HAVE_HPUX9 1
+EOF
+
+ ;;
+
+hpux10.0*)
+ ;;
+
+hpux10.1*)
+ ;;
+
+hpux*)
+ cat >> confdefs.h <<\EOF
+#define HAVE_HPUX10_20 1
+EOF
+
+ ;;
+
+sinix*)
+ echo $ac_n "checking if SINIX compiler defines sinix""... $ac_c" 1>&6
+echo "configure:1552: checking if SINIX compiler defines sinix" >&5
+ if eval "test \"`echo '$''{'ac_cv_cc_sinix_defined'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1557 "configure"
+#include "confdefs.h"
+
+int main() {
+int i = sinix;
+; return 0; }
+EOF
+if { (eval echo configure:1564: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_cc_sinix_defined=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_cc_sinix_defined=no
+fi
+rm -f conftest*
+fi
+
+ echo "$ac_t""$ac_cv_cc_sinix_defined" 1>&6
+ if test $ac_cv_cc_sinix_defined = no ; then
+ cat >> confdefs.h <<\EOF
+#define sinix 1
+EOF
+
+ fi
+ ;;
+
+solaris*)
+ cat >> confdefs.h <<\EOF
+#define HAVE_SOLARIS 1
+EOF
+
+ ;;
+
+linux*)
+ V_INCLS="$V_INCLS -Ilinux-include"
+ ;;
+esac
+
+for ac_prog in ranlib
+do
+# Extract the first word of "$ac_prog", so it can be a program name with args.
+set dummy $ac_prog; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:1602: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_V_RANLIB'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$V_RANLIB"; then
+ ac_cv_prog_V_RANLIB="$V_RANLIB" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_V_RANLIB="$ac_prog"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+fi
+fi
+V_RANLIB="$ac_cv_prog_V_RANLIB"
+if test -n "$V_RANLIB"; then
+ echo "$ac_t""$V_RANLIB" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+test -n "$V_RANLIB" && break
+done
+test -n "$V_RANLIB" || V_RANLIB="@true"
+
+
+rm -f os-proto.h
+ if test "${LBL_CFLAGS+set}" = set; then
+ V_CCOPT="$V_CCOPT ${LBL_CFLAGS}"
+ fi
+ if test -f .devel ; then
+ if test "$GCC" = yes ; then
+ if test "${LBL_CFLAGS+set}" != set; then
+ if test "$ac_cv_prog_cc_g" = yes ; then
+ V_CCOPT="-g $V_CCOPT"
+ fi
+ V_CCOPT="$V_CCOPT -Wall"
+ if test $ac_cv_lbl_gcc_vers -gt 1 ; then
+ V_CCOPT="$V_CCOPT -Wmissing-prototypes -Wstrict-prototypes"
+ fi
+ fi
+ else
+ case "$target_os" in
+
+ irix6*)
+ V_CCOPT="$V_CCOPT -n32"
+ ;;
+
+ *)
+ ;;
+ esac
+ fi
+ os=`echo $target_os | sed -e 's/\([0-9][0-9]*\)[^0-9].*$/\1/'`
+ name="lbl/os-$os.h"
+ if test -f $name ; then
+ ln -s $name os-proto.h
+ cat >> confdefs.h <<\EOF
+#define HAVE_OS_PROTO_H 1
+EOF
+
+ else
+ echo "configure: warning: can't find $name" 1>&2
+ fi
+ fi
+
+echo $ac_n "checking if sockaddr struct has sa_len member""... $ac_c" 1>&6
+echo "configure:1672: checking if sockaddr struct has sa_len member" >&5
+ if eval "test \"`echo '$''{'ac_cv_lbl_sockaddr_has_sa_len'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1677 "configure"
+#include "confdefs.h"
+
+# include <sys/types.h>
+# include <sys/socket.h>
+int main() {
+u_int i = sizeof(((struct sockaddr *)0)->sa_len)
+; return 0; }
+EOF
+if { (eval echo configure:1686: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_lbl_sockaddr_has_sa_len=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_lbl_sockaddr_has_sa_len=no
+fi
+rm -f conftest*
+fi
+
+ echo "$ac_t""$ac_cv_lbl_sockaddr_has_sa_len" 1>&6
+ if test $ac_cv_lbl_sockaddr_has_sa_len = yes ; then
+ cat >> confdefs.h <<\EOF
+#define HAVE_SOCKADDR_SA_LEN 1
+EOF
+
+ fi
+
+echo $ac_n "checking if unaligned accesses fail""... $ac_c" 1>&6
+echo "configure:1707: checking if unaligned accesses fail" >&5
+ if eval "test \"`echo '$''{'ac_cv_lbl_unaligned_fail'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ case "$target_cpu" in
+
+ alpha|hp*|mips|sparc)
+ ac_cv_lbl_unaligned_fail=yes
+ ;;
+
+ *)
+ cat >conftest.c <<EOF
+# include <sys/types.h>
+# include <sys/wait.h>
+# include <stdio.h>
+ unsigned char a[5] = { 1, 2, 3, 4, 5 };
+ main() {
+ unsigned int i;
+ pid_t pid;
+ int status;
+ /* avoid "core dumped" message */
+ pid = fork();
+ if (pid < 0)
+ exit(2);
+ if (pid > 0) {
+ /* parent */
+ pid = waitpid(pid, &status, 0);
+ if (pid < 0)
+ exit(3);
+ exit(!WIFEXITED(status));
+ }
+ /* child */
+ i = *(unsigned int *)&a[1];
+ printf("%d\n", i);
+ exit(0);
+ }
+EOF
+ ${CC-cc} -o conftest $CFLAGS $CPPFLAGS $LDFLAGS \
+ conftest.c $LIBS >/dev/null 2>&1
+ if test ! -x conftest ; then
+ ac_cv_lbl_unaligned_fail=yes
+ else
+ ./conftest >conftest.out
+ if test ! -s conftest.out ; then
+ ac_cv_lbl_unaligned_fail=yes
+ else
+ ac_cv_lbl_unaligned_fail=no
+ fi
+ fi
+ rm -f conftest* core core.conftest
+ ;;
+ esac
+fi
+
+ echo "$ac_t""$ac_cv_lbl_unaligned_fail" 1>&6
+ if test $ac_cv_lbl_unaligned_fail = yes ; then
+ cat >> confdefs.h <<\EOF
+#define LBL_ALIGN 1
+EOF
+
+ fi
+
+if test "${srcdir}" = "." ; then
+ srcdirprefix=""
+else
+ srcdirprefix="./"
+fi
+
+if test -r ${srcdirprefix}lbl/gnuc.h ; then
+ rm -f gnuc.h
+ ln -s ${srcdirprefix}lbl/gnuc.h gnuc.h
+fi
+
+rm -f bpf_filter.c
+ln -s ${srcdirprefix}bpf/net/bpf_filter.c bpf_filter.c
+rm -f net
+ln -s ${srcdirprefix}bpf/net net
+
+
+
+
+
+
+
+
+# Find a good install program. We prefer a C program (faster),
+# so one script is as good as another. But avoid the broken or
+# incompatible versions:
+# SysV /etc/install, /usr/sbin/install
+# SunOS /usr/etc/install
+# IRIX /sbin/install
+# AIX /bin/install
+# AFS /usr/afsws/bin/install, which mishandles nonexistent args
+# SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff"
+# ./install, which can be erroneously created by make from ./install.sh.
+echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6
+echo "configure:1803: checking for a BSD compatible install" >&5
+if test -z "$INSTALL"; then
+if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ IFS="${IFS= }"; ac_save_IFS="$IFS"; IFS="${IFS}:"
+ for ac_dir in $PATH; do
+ # Account for people who put trailing slashes in PATH elements.
+ case "$ac_dir/" in
+ /|./|.//|/etc/*|/usr/sbin/*|/usr/etc/*|/sbin/*|/usr/afsws/bin/*|/usr/ucb/*) ;;
+ *)
+ # OSF1 and SCO ODT 3.0 have their own names for install.
+ for ac_prog in ginstall installbsd scoinst install; do
+ if test -f $ac_dir/$ac_prog; then
+ if test $ac_prog = install &&
+ grep dspmsg $ac_dir/$ac_prog >/dev/null 2>&1; then
+ # AIX install. It has an incompatible calling convention.
+ # OSF/1 installbsd also uses dspmsg, but is usable.
+ :
+ else
+ ac_cv_path_install="$ac_dir/$ac_prog -c"
+ break 2
+ fi
+ fi
+ done
+ ;;
+ esac
+ done
+ IFS="$ac_save_IFS"
+
+fi
+ if test "${ac_cv_path_install+set}" = set; then
+ INSTALL="$ac_cv_path_install"
+ else
+ # As a last resort, use the slow shell script. We don't cache a
+ # path for INSTALL within a source directory, because that will
+ # break other packages using the cache if that directory is
+ # removed, or if the path is relative.
+ INSTALL="$ac_install_sh"
+ fi
+fi
+echo "$ac_t""$INSTALL" 1>&6
+
+# Use test -z because SunOS4 sh mishandles braces in ${var-val}.
+# It thinks the first close brace ends the variable substitution.
+test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}'
+
+test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644'
+
+
+trap '' 1 2 15
+cat > confcache <<\EOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs. It is not useful on other systems.
+# If it contains results you don't want to keep, you may remove or edit it.
+#
+# By default, configure uses ./config.cache as the cache file,
+# creating it if it does not exist already. You can give configure
+# the --cache-file=FILE option to use a different cache file; that is
+# what configure does when it calls configure scripts in
+# subdirectories, so they share the cache.
+# Giving --cache-file=/dev/null disables caching, for debugging configure.
+# config.status only pays attention to the cache file if you give it the
+# --recheck option to rerun configure.
+#
+EOF
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, don't put newlines in cache variables' values.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(set) 2>&1 |
+ case `(ac_space=' '; set) 2>&1` in
+ *ac_space=\ *)
+ # `set' does not quote correctly, so add quotes (double-quote substitution
+ # turns \\\\ into \\, and sed turns \\ into \).
+ sed -n \
+ -e "s/'/'\\\\''/g" \
+ -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
+ ;;
+ *)
+ # `set' quotes correctly as required by POSIX, so do not add quotes.
+ sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
+ ;;
+ esac >> confcache
+if cmp -s $cache_file confcache; then
+ :
+else
+ if test -w $cache_file; then
+ echo "updating cache $cache_file"
+ cat confcache > $cache_file
+ else
+ echo "not updating unwritable cache $cache_file"
+ fi
+fi
+rm -f confcache
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# Any assignment to VPATH causes Sun make to only execute
+# the first set of double-colon rules, so remove it if not needed.
+# If there is a colon in the path, we need to keep it.
+if test "x$srcdir" = x.; then
+ ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d'
+fi
+
+trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
+
+# Transform confdefs.h into DEFS.
+# Protect against shell expansion while executing Makefile rules.
+# Protect against Makefile macro expansion.
+cat > conftest.defs <<\EOF
+s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%-D\1=\2%g
+s%[ `~#$^&*(){}\\|;'"<>?]%\\&%g
+s%\[%\\&%g
+s%\]%\\&%g
+s%\$%$$%g
+EOF
+DEFS=`sed -f conftest.defs confdefs.h | tr '\012' ' '`
+rm -f conftest.defs
+
+
+# Without the "./", some shells look in PATH for config.status.
+: ${CONFIG_STATUS=./config.status}
+
+echo creating $CONFIG_STATUS
+rm -f $CONFIG_STATUS
+cat > $CONFIG_STATUS <<EOF
+#! /bin/sh
+# Generated automatically by configure.
+# Run this file to recreate the current configuration.
+# This directory was configured as follows,
+# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+#
+# $0 $ac_configure_args
+#
+# Compiler output produced by configure, useful for debugging
+# configure, is in ./config.log if it exists.
+
+ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
+for ac_option
+do
+ case "\$ac_option" in
+ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+ echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
+ exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
+ -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
+ echo "$CONFIG_STATUS generated by autoconf version 2.12"
+ exit 0 ;;
+ -help | --help | --hel | --he | --h)
+ echo "\$ac_cs_usage"; exit 0 ;;
+ *) echo "\$ac_cs_usage"; exit 1 ;;
+ esac
+done
+
+ac_given_srcdir=$srcdir
+ac_given_INSTALL="$INSTALL"
+
+trap 'rm -fr `echo "Makefile" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+# Protect against being on the right side of a sed subst in config.status.
+sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
+ s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
+$ac_vpsub
+$extrasub
+s%@CFLAGS@%$CFLAGS%g
+s%@CPPFLAGS@%$CPPFLAGS%g
+s%@CXXFLAGS@%$CXXFLAGS%g
+s%@DEFS@%$DEFS%g
+s%@LDFLAGS@%$LDFLAGS%g
+s%@LIBS@%$LIBS%g
+s%@exec_prefix@%$exec_prefix%g
+s%@prefix@%$prefix%g
+s%@program_transform_name@%$program_transform_name%g
+s%@bindir@%$bindir%g
+s%@sbindir@%$sbindir%g
+s%@libexecdir@%$libexecdir%g
+s%@datadir@%$datadir%g
+s%@sysconfdir@%$sysconfdir%g
+s%@sharedstatedir@%$sharedstatedir%g
+s%@localstatedir@%$localstatedir%g
+s%@libdir@%$libdir%g
+s%@includedir@%$includedir%g
+s%@oldincludedir@%$oldincludedir%g
+s%@infodir@%$infodir%g
+s%@mandir@%$mandir%g
+s%@host@%$host%g
+s%@host_alias@%$host_alias%g
+s%@host_cpu@%$host_cpu%g
+s%@host_vendor@%$host_vendor%g
+s%@host_os@%$host_os%g
+s%@target@%$target%g
+s%@target_alias@%$target_alias%g
+s%@target_cpu@%$target_cpu%g
+s%@target_vendor@%$target_vendor%g
+s%@target_os@%$target_os%g
+s%@build@%$build%g
+s%@build_alias@%$build_alias%g
+s%@build_cpu@%$build_cpu%g
+s%@build_vendor@%$build_vendor%g
+s%@build_os@%$build_os%g
+s%@SHLICC2@%$SHLICC2%g
+s%@CC@%$CC%g
+s%@CPP@%$CPP%g
+s%@V_LEX@%$V_LEX%g
+s%@V_YACC@%$V_YACC%g
+s%@V_RANLIB@%$V_RANLIB%g
+s%@V_CCOPT@%$V_CCOPT%g
+s%@V_INCLS@%$V_INCLS%g
+s%@V_PCAP@%$V_PCAP%g
+s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g
+s%@INSTALL_DATA@%$INSTALL_DATA%g
+
+CEOF
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+
+# Split the substitutions into bite-sized pieces for seds with
+# small command number limits, like on Digital OSF/1 and HP-UX.
+ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
+ac_file=1 # Number of current file.
+ac_beg=1 # First line for current file.
+ac_end=$ac_max_sed_cmds # Line after last line for current file.
+ac_more_lines=:
+ac_sed_cmds=""
+while $ac_more_lines; do
+ if test $ac_beg -gt 1; then
+ sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
+ else
+ sed "${ac_end}q" conftest.subs > conftest.s$ac_file
+ fi
+ if test ! -s conftest.s$ac_file; then
+ ac_more_lines=false
+ rm -f conftest.s$ac_file
+ else
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds="sed -f conftest.s$ac_file"
+ else
+ ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
+ fi
+ ac_file=`expr $ac_file + 1`
+ ac_beg=$ac_end
+ ac_end=`expr $ac_end + $ac_max_sed_cmds`
+ fi
+done
+if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds=cat
+fi
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+
+CONFIG_FILES=\${CONFIG_FILES-"Makefile"}
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case "$ac_file" in
+ *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+ ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+ *) ac_file_in="${ac_file}.in" ;;
+ esac
+
+ # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
+
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+ # The file is in a subdirectory.
+ test ! -d "$ac_dir" && mkdir "$ac_dir"
+ ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
+ else
+ ac_dir_suffix= ac_dots=
+ fi
+
+ case "$ac_given_srcdir" in
+ .) srcdir=.
+ if test -z "$ac_dots"; then top_srcdir=.
+ else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
+ /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
+ *) # Relative path.
+ srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
+ top_srcdir="$ac_dots$ac_given_srcdir" ;;
+ esac
+
+ case "$ac_given_INSTALL" in
+ [/$]*) INSTALL="$ac_given_INSTALL" ;;
+ *) INSTALL="$ac_dots$ac_given_INSTALL" ;;
+ esac
+
+ echo creating "$ac_file"
+ rm -f "$ac_file"
+ configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
+ case "$ac_file" in
+ *Makefile*) ac_comsub="1i\\
+# $configure_input" ;;
+ *) ac_comsub= ;;
+ esac
+
+ ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+ sed -e "$ac_comsub
+s%@configure_input@%$configure_input%g
+s%@srcdir@%$srcdir%g
+s%@top_srcdir@%$top_srcdir%g
+s%@INSTALL@%$INSTALL%g
+" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
+fi; done
+rm -f conftest.s*
+
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+
+exit 0
+EOF
+chmod +x $CONFIG_STATUS
+rm -fr confdefs* $ac_clean_files
+test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
+
+
+if test -f .devel ; then
+ make depend
+fi
+exit 0
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/configure.in b/package/etrax-tools/src/e100boot/libpcap-0.4/configure.in
new file mode 100755
index 000000000..c5f33884f
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/configure.in
@@ -0,0 +1,189 @@
+dnl @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/configure.in,v 1.1 1999/08/26 10:05:21 johana Exp $ (LBL)
+dnl
+dnl Copyright (c) 1994, 1995, 1996, 1997
+dnl The Regents of the University of California. All rights reserved.
+dnl
+dnl Process this file with autoconf to produce a configure script.
+dnl
+
+AC_INIT(pcap.c)
+
+AC_CANONICAL_SYSTEM
+
+umask 002
+
+if test -z "$PWD" ; then
+ PWD=`pwd`
+fi
+
+AC_LBL_C_INIT(V_CCOPT, V_INCLS)
+
+AC_CHECK_HEADERS(malloc.h sys/ioccom.h sys/sockio.h)
+
+AC_LBL_FIXINCLUDES
+
+AC_CHECK_FUNCS(ether_hostton strerror)
+
+dnl
+dnl Not all versions of test support -c (character special) but it's a
+dnl better way of testing since the device might be protected. So we
+dnl check in our normal order using -r and then check the for the /dev
+dnl guys again using -c.
+dnl
+AC_ARG_WITH(pcap, [ --with-pcap=TYPE use packet capture TYPE])
+AC_MSG_CHECKING(packet capture type)
+if test ! -z "$with_pcap" ; then
+ V_PCAP="$withval"
+elif test -r /dev/bpf0 ; then
+ V_PCAP=bpf
+elif test -r /usr/include/net/pfilt.h ; then
+ V_PCAP=pf
+elif test -r /dev/enet ; then
+ V_PCAP=enet
+elif test -r /dev/nit ; then
+ V_PCAP=snit
+elif test -r /usr/include/sys/net/nit.h ; then
+ V_PCAP=nit
+elif test -r /usr/include/net/raw.h ; then
+ V_PCAP=snoop
+elif test -r /usr/include/sys/dlpi.h ; then
+ V_PCAP=dlpi
+elif test -r /usr/include/linux/socket.h ; then
+ V_PCAP=linux
+elif test -c /dev/bpf0 ; then # check again in case not readable
+ V_PCAP=bpf
+elif test -c /dev/enet ; then # check again in case not readable
+ V_PCAP=enet
+elif test -c /dev/nit ; then # check again in case not readable
+ V_PCAP=snit
+else
+ V_PCAP=null
+fi
+AC_MSG_RESULT($V_PCAP)
+
+case "$V_PCAP" in
+
+dlpi)
+ AC_CHECK_HEADERS(sys/bufmod.h sys/dlpi_ext.h)
+ AC_MSG_CHECKING(for /dev/dlpi device)
+ if test -c /dev/dlpi ; then
+ AC_MSG_RESULT(yes)
+ AC_DEFINE(HAVE_DEV_DLPI)
+ else
+ AC_MSG_RESULT(no)
+ dir="/dev/dlpi"
+ AC_MSG_CHECKING(for $dir directory)
+ if test -d $dir ; then
+ AC_MSG_RESULT(yes)
+ AC_DEFINE_UNQUOTED(PCAP_DEV_PREFIX, "$dir")
+ else
+ AC_MSG_RESULT(no)
+ fi
+ fi
+ ;;
+
+linux)
+ AC_CHECK_HEADERS(net/if_arp.h)
+ AC_MSG_CHECKING(Linux kernel version)
+ AC_CACHE_VAL(ac_cv_linux_vers,
+ ac_cv_linux_vers=`uname -r 2>&1 | \
+ sed -n -e '$s/.* //' -e '$s/\..*//p'`)
+ AC_MSG_RESULT($ac_cv_linux_vers)
+ if test $ac_cv_linux_vers -lt 2 ; then
+ AC_MSG_ERROR(version 2 or higher required; see the INSTALL doc for more info)
+ fi
+ ;;
+
+null)
+ AC_MSG_WARN(cannot determine packet capture interface)
+ AC_MSG_WARN((see the INSTALL doc for more info))
+ ;;
+
+esac
+
+AC_LBL_LEX_AND_YACC(V_LEX, V_YACC, pcap_)
+
+case "$target_os" in
+
+aix*)
+ dnl Workaround to enable certain features
+ AC_DEFINE(_SUN)
+ ;;
+
+hpux9*)
+ AC_DEFINE(HAVE_HPUX9)
+ ;;
+
+hpux10.0*)
+ ;;
+
+hpux10.1*)
+ ;;
+
+hpux*)
+ dnl HPUX 10.20 and above is similar to HPUX 9...
+ AC_DEFINE(HAVE_HPUX10_20)
+ ;;
+
+sinix*)
+ AC_MSG_CHECKING(if SINIX compiler defines sinix)
+ AC_CACHE_VAL(ac_cv_cc_sinix_defined,
+ AC_TRY_COMPILE(
+ [],
+ [int i = sinix;],
+ ac_cv_cc_sinix_defined=yes,
+ ac_cv_cc_sinix_defined=no))
+ AC_MSG_RESULT($ac_cv_cc_sinix_defined)
+ if test $ac_cv_cc_sinix_defined = no ; then
+ AC_DEFINE(sinix)
+ fi
+ ;;
+
+solaris*)
+ AC_DEFINE(HAVE_SOLARIS)
+ ;;
+
+linux*)
+ V_INCLS="$V_INCLS -Ilinux-include"
+ ;;
+esac
+
+AC_CHECK_PROGS(V_RANLIB, ranlib, @true)
+
+AC_LBL_DEVEL(V_CCOPT)
+
+AC_LBL_SOCKADDR_SA_LEN
+
+AC_LBL_UNALIGNED_ACCESS
+
+if test "${srcdir}" = "." ; then
+ srcdirprefix=""
+else
+ srcdirprefix="./"
+fi
+
+if test -r ${srcdirprefix}lbl/gnuc.h ; then
+ rm -f gnuc.h
+ ln -s ${srcdirprefix}lbl/gnuc.h gnuc.h
+fi
+
+rm -f bpf_filter.c
+ln -s ${srcdirprefix}bpf/net/bpf_filter.c bpf_filter.c
+rm -f net
+ln -s ${srcdirprefix}bpf/net net
+
+AC_SUBST(V_CCOPT)
+AC_SUBST(V_INCLS)
+AC_SUBST(V_LEX)
+AC_SUBST(V_PCAP)
+AC_SUBST(V_RANLIB)
+AC_SUBST(V_YACC)
+
+AC_PROG_INSTALL
+
+AC_OUTPUT(Makefile)
+
+if test -f .devel ; then
+ make depend
+fi
+exit 0
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/etherent.c b/package/etrax-tools/src/e100boot/libpcap-0.4/etherent.c
new file mode 100644
index 000000000..bd7ca24dd
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/etherent.c
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 1990, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/etherent.c,v 1.1 1999/08/26 10:05:21 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+
+#include <ctype.h>
+#include <memory.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "pcap-int.h"
+
+#include <pcap-namedb.h>
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+static inline int xdtoi(int);
+static inline int skip_space(FILE *);
+static inline int skip_line(FILE *);
+
+/* Hex digit to integer. */
+static inline int
+xdtoi(c)
+ register int c;
+{
+ if (isdigit(c))
+ return c - '0';
+ else if (islower(c))
+ return c - 'a' + 10;
+ else
+ return c - 'A' + 10;
+}
+
+static inline int
+skip_space(f)
+ FILE *f;
+{
+ int c;
+
+ do {
+ c = getc(f);
+ } while (isspace(c) && c != '\n');
+
+ return c;
+}
+
+static inline int
+skip_line(f)
+ FILE *f;
+{
+ int c;
+
+ do
+ c = getc(f);
+ while (c != '\n' && c != EOF);
+
+ return c;
+}
+
+struct pcap_etherent *
+pcap_next_etherent(FILE *fp)
+{
+ register int c, d, i;
+ char *bp;
+ static struct pcap_etherent e;
+
+ memset((char *)&e, 0, sizeof(e));
+ do {
+ /* Find addr */
+ c = skip_space(fp);
+ if (c == '\n')
+ continue;
+
+ /* If this is a comment, or first thing on line
+ cannot be etehrnet address, skip the line. */
+ if (!isxdigit(c)) {
+ c = skip_line(fp);
+ continue;
+ }
+
+ /* must be the start of an address */
+ for (i = 0; i < 6; i += 1) {
+ d = xdtoi(c);
+ c = getc(fp);
+ if (isxdigit(c)) {
+ d <<= 4;
+ d |= xdtoi(c);
+ c = getc(fp);
+ }
+ e.addr[i] = d;
+ if (c != ':')
+ break;
+ c = getc(fp);
+ }
+ if (c == EOF)
+ break;
+
+ /* Must be whitespace */
+ if (!isspace(c)) {
+ c = skip_line(fp);
+ continue;
+ }
+ c = skip_space(fp);
+
+ /* hit end of line... */
+ if (c == '\n')
+ continue;
+
+ if (c == '#') {
+ c = skip_line(fp);
+ continue;
+ }
+
+ /* pick up name */
+ bp = e.name;
+ /* Use 'd' to prevent buffer overflow. */
+ d = sizeof(e.name) - 1;
+ do {
+ *bp++ = c;
+ c = getc(fp);
+ } while (!isspace(c) && c != EOF && --d > 0);
+ *bp = '\0';
+
+ /* Eat trailing junk */
+ if (c != '\n')
+ (void)skip_line(fp);
+
+ return &e;
+
+ } while (c != EOF);
+
+ return (NULL);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/ethertype.h b/package/etrax-tools/src/e100boot/libpcap-0.4/ethertype.h
new file mode 100644
index 000000000..6849bcdf3
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/ethertype.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 1993, 1994, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/ethertype.h,v 1.1 1999/08/26 10:05:21 johana Exp $ (LBL)
+ */
+
+/* Types missing from some systems */
+
+#ifndef ETHERTYPE_NS
+#define ETHERTYPE_NS 0x0600
+#endif
+#ifndef ETHERTYPE_SPRITE
+#define ETHERTYPE_SPRITE 0x0500
+#endif
+#ifndef ETHERTYPE_TRAIL
+#define ETHERTYPE_TRAIL 0x1000
+#endif
+#ifndef ETHERTYPE_MOPDL
+#define ETHERTYPE_MOPDL 0x6001
+#endif
+#ifndef ETHERTYPE_MOPRC
+#define ETHERTYPE_MOPRC 0x6002
+#endif
+#ifndef ETHERTYPE_DN
+#define ETHERTYPE_DN 0x6003
+#endif
+#ifndef ETHERTYPE_LAT
+#define ETHERTYPE_LAT 0x6004
+#endif
+#ifndef ETHERTYPE_SCA
+#define ETHERTYPE_SCA 0x6007
+#endif
+#ifndef ETHERTYPE_REVARP
+#define ETHERTYPE_REVARP 0x8035
+#endif
+#ifndef ETHERTYPE_LANBRIDGE
+#define ETHERTYPE_LANBRIDGE 0x8038
+#endif
+#ifndef ETHERTYPE_DECDNS
+#define ETHERTYPE_DECDNS 0x803c
+#endif
+#ifndef ETHERTYPE_DECDTS
+#define ETHERTYPE_DECDTS 0x803e
+#endif
+#ifndef ETHERTYPE_VEXP
+#define ETHERTYPE_VEXP 0x805b
+#endif
+#ifndef ETHERTYPE_VPROD
+#define ETHERTYPE_VPROD 0x805c
+#endif
+#ifndef ETHERTYPE_ATALK
+#define ETHERTYPE_ATALK 0x809b
+#endif
+#ifndef ETHERTYPE_AARP
+#define ETHERTYPE_AARP 0x80f3
+#endif
+#ifndef ETHERTYPE_LOOPBACK
+#define ETHERTYPE_LOOPBACK 0x9000
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/gencode.c b/package/etrax-tools/src/e100boot/libpcap-0.4/gencode.c
new file mode 100644
index 000000000..f3fc5a60f
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/gencode.c
@@ -0,0 +1,1944 @@
+/*
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/gencode.c,v 1.1 1999/08/26 10:05:22 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <sys/time.h>
+
+#if __STDC__
+struct mbuf;
+struct rtentry;
+#endif
+
+#include <net/if.h>
+
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+
+#include <stdlib.h>
+#include <memory.h>
+#include <setjmp.h>
+#if __STDC__
+#include <stdarg.h>
+#else
+#include <varargs.h>
+#endif
+
+#include "pcap-int.h"
+
+#include "ethertype.h"
+#include "gencode.h"
+#include "ppp.h"
+#include <pcap-namedb.h>
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#define JMP(c) ((c)|BPF_JMP|BPF_K)
+
+/* Locals */
+static jmp_buf top_ctx;
+static pcap_t *bpf_pcap;
+
+/* XXX */
+#ifdef PCAP_FDDIPAD
+int pcap_fddipad = PCAP_FDDIPAD;
+#else
+int pcap_fddipad;
+#endif
+
+/* VARARGS */
+__dead void
+#if __STDC__
+bpf_error(const char *fmt, ...)
+#else
+bpf_error(fmt, va_alist)
+ const char *fmt;
+ va_dcl
+#endif
+{
+ va_list ap;
+
+#if __STDC__
+ va_start(ap, fmt);
+#else
+ va_start(ap);
+#endif
+ if (bpf_pcap != NULL)
+ (void)vsprintf(pcap_geterr(bpf_pcap), fmt, ap);
+ va_end(ap);
+ longjmp(top_ctx, 1);
+ /* NOTREACHED */
+}
+
+static void init_linktype(int);
+
+static int alloc_reg(void);
+static void free_reg(int);
+
+static struct block *root;
+
+/*
+ * We divy out chunks of memory rather than call malloc each time so
+ * we don't have to worry about leaking memory. It's probably
+ * not a big deal if all this memory was wasted but it this ever
+ * goes into a library that would probably not be a good idea.
+ */
+#define NCHUNKS 16
+#define CHUNK0SIZE 1024
+struct chunk {
+ u_int n_left;
+ void *m;
+};
+
+static struct chunk chunks[NCHUNKS];
+static int cur_chunk;
+
+static void *newchunk(u_int);
+static void freechunks(void);
+static inline struct block *new_block(int);
+static inline struct slist *new_stmt(int);
+static struct block *gen_retblk(int);
+static inline void syntax(void);
+
+static void backpatch(struct block *, struct block *);
+static void merge(struct block *, struct block *);
+static struct block *gen_cmp(u_int, u_int, bpf_int32);
+static struct block *gen_mcmp(u_int, u_int, bpf_int32, bpf_u_int32);
+static struct block *gen_bcmp(u_int, u_int, const u_char *);
+static struct block *gen_uncond(int);
+static inline struct block *gen_true(void);
+static inline struct block *gen_false(void);
+static struct block *gen_linktype(int);
+static struct block *gen_hostop(bpf_u_int32, bpf_u_int32, int, int, u_int, u_int);
+static struct block *gen_ehostop(const u_char *, int);
+static struct block *gen_fhostop(const u_char *, int);
+static struct block *gen_dnhostop(bpf_u_int32, int, u_int);
+static struct block *gen_host(bpf_u_int32, bpf_u_int32, int, int);
+static struct block *gen_gateway(const u_char *, bpf_u_int32 **, int, int);
+static struct block *gen_ipfrag(void);
+static struct block *gen_portatom(int, bpf_int32);
+struct block *gen_portop(int, int, int);
+static struct block *gen_port(int, int, int);
+static int lookup_proto(const char *, int);
+static struct block *gen_proto(int, int, int);
+static struct slist *xfer_to_x(struct arth *);
+static struct slist *xfer_to_a(struct arth *);
+static struct block *gen_len(int, int);
+
+static void *
+newchunk(n)
+ u_int n;
+{
+ struct chunk *cp;
+ int k, size;
+
+ /* XXX Round up to nearest long. */
+ n = (n + sizeof(long) - 1) & ~(sizeof(long) - 1);
+
+ cp = &chunks[cur_chunk];
+ if (n > cp->n_left) {
+ ++cp, k = ++cur_chunk;
+ if (k >= NCHUNKS)
+ bpf_error("out of memory");
+ size = CHUNK0SIZE << k;
+ cp->m = (void *)malloc(size);
+ memset((char *)cp->m, 0, size);
+ cp->n_left = size;
+ if (n > size)
+ bpf_error("out of memory");
+ }
+ cp->n_left -= n;
+ return (void *)((char *)cp->m + cp->n_left);
+}
+
+static void
+freechunks()
+{
+ int i;
+
+ cur_chunk = 0;
+ for (i = 0; i < NCHUNKS; ++i)
+ if (chunks[i].m != NULL) {
+ free(chunks[i].m);
+ chunks[i].m = NULL;
+ }
+}
+
+/*
+ * A strdup whose allocations are freed after code generation is over.
+ */
+char *
+sdup(s)
+ register const char *s;
+{
+ int n = strlen(s) + 1;
+ char *cp = newchunk(n);
+
+ strcpy(cp, s);
+ return (cp);
+}
+
+static inline struct block *
+new_block(code)
+ int code;
+{
+ struct block *p;
+
+ p = (struct block *)newchunk(sizeof(*p));
+ p->s.code = code;
+ p->head = p;
+
+ return p;
+}
+
+static inline struct slist *
+new_stmt(code)
+ int code;
+{
+ struct slist *p;
+
+ p = (struct slist *)newchunk(sizeof(*p));
+ p->s.code = code;
+
+ return p;
+}
+
+static struct block *
+gen_retblk(v)
+ int v;
+{
+ struct block *b = new_block(BPF_RET|BPF_K);
+
+ b->s.k = v;
+ return b;
+}
+
+static inline void
+syntax()
+{
+ bpf_error("syntax error in filter expression");
+}
+
+static bpf_u_int32 netmask;
+static int snaplen;
+
+int
+pcap_compile(pcap_t *p, struct bpf_program *program,
+ char *buf, int optimize, bpf_u_int32 mask)
+{
+ extern int n_errors;
+ int len;
+
+ n_errors = 0;
+ root = NULL;
+ bpf_pcap = p;
+ if (setjmp(top_ctx)) {
+ freechunks();
+ return (-1);
+ }
+
+ netmask = mask;
+ snaplen = pcap_snapshot(p);
+
+ lex_init(buf ? buf : "");
+ init_linktype(pcap_datalink(p));
+ (void)pcap_parse();
+
+ if (n_errors)
+ syntax();
+
+ if (root == NULL)
+ root = gen_retblk(snaplen);
+
+ if (optimize) {
+ bpf_optimize(&root);
+ if (root == NULL ||
+ (root->s.code == (BPF_RET|BPF_K) && root->s.k == 0))
+ bpf_error("expression rejects all packets");
+ }
+ program->bf_insns = icode_to_fcode(root, &len);
+ program->bf_len = len;
+
+ freechunks();
+ return (0);
+}
+
+/*
+ * Backpatch the blocks in 'list' to 'target'. The 'sense' field indicates
+ * which of the jt and jf fields has been resolved and which is a pointer
+ * back to another unresolved block (or nil). At least one of the fields
+ * in each block is already resolved.
+ */
+static void
+backpatch(list, target)
+ struct block *list, *target;
+{
+ struct block *next;
+
+ while (list) {
+ if (!list->sense) {
+ next = JT(list);
+ JT(list) = target;
+ } else {
+ next = JF(list);
+ JF(list) = target;
+ }
+ list = next;
+ }
+}
+
+/*
+ * Merge the lists in b0 and b1, using the 'sense' field to indicate
+ * which of jt and jf is the link.
+ */
+static void
+merge(b0, b1)
+ struct block *b0, *b1;
+{
+ register struct block **p = &b0;
+
+ /* Find end of list. */
+ while (*p)
+ p = !((*p)->sense) ? &JT(*p) : &JF(*p);
+
+ /* Concatenate the lists. */
+ *p = b1;
+}
+
+void
+finish_parse(p)
+ struct block *p;
+{
+ backpatch(p, gen_retblk(snaplen));
+ p->sense = !p->sense;
+ backpatch(p, gen_retblk(0));
+ root = p->head;
+}
+
+void
+gen_and(b0, b1)
+ struct block *b0, *b1;
+{
+ backpatch(b0, b1->head);
+ b0->sense = !b0->sense;
+ b1->sense = !b1->sense;
+ merge(b1, b0);
+ b1->sense = !b1->sense;
+ b1->head = b0->head;
+}
+
+void
+gen_or(b0, b1)
+ struct block *b0, *b1;
+{
+ b0->sense = !b0->sense;
+ backpatch(b0, b1->head);
+ b0->sense = !b0->sense;
+ merge(b1, b0);
+ b1->head = b0->head;
+}
+
+void
+gen_not(b)
+ struct block *b;
+{
+ b->sense = !b->sense;
+}
+
+static struct block *
+gen_cmp(offset, size, v)
+ u_int offset, size;
+ bpf_int32 v;
+{
+ struct slist *s;
+ struct block *b;
+
+ s = new_stmt(BPF_LD|BPF_ABS|size);
+ s->s.k = offset;
+
+ b = new_block(JMP(BPF_JEQ));
+ b->stmts = s;
+ b->s.k = v;
+
+ return b;
+}
+
+static struct block *
+gen_mcmp(offset, size, v, mask)
+ u_int offset, size;
+ bpf_int32 v;
+ bpf_u_int32 mask;
+{
+ struct block *b = gen_cmp(offset, size, v);
+ struct slist *s;
+
+ if (mask != 0xffffffff) {
+ s = new_stmt(BPF_ALU|BPF_AND|BPF_K);
+ s->s.k = mask;
+ b->stmts->next = s;
+ }
+ return b;
+}
+
+static struct block *
+gen_bcmp(offset, size, v)
+ register u_int offset, size;
+ register const u_char *v;
+{
+ register struct block *b, *tmp;
+
+ b = NULL;
+ while (size >= 4) {
+ register const u_char *p = &v[size - 4];
+ bpf_int32 w = ((bpf_int32)p[0] << 24) |
+ ((bpf_int32)p[1] << 16) | ((bpf_int32)p[2] << 8) | p[3];
+
+ tmp = gen_cmp(offset + size - 4, BPF_W, w);
+ if (b != NULL)
+ gen_and(b, tmp);
+ b = tmp;
+ size -= 4;
+ }
+ while (size >= 2) {
+ register const u_char *p = &v[size - 2];
+ bpf_int32 w = ((bpf_int32)p[0] << 8) | p[1];
+
+ tmp = gen_cmp(offset + size - 2, BPF_H, w);
+ if (b != NULL)
+ gen_and(b, tmp);
+ b = tmp;
+ size -= 2;
+ }
+ if (size > 0) {
+ tmp = gen_cmp(offset, BPF_B, (bpf_int32)v[0]);
+ if (b != NULL)
+ gen_and(b, tmp);
+ b = tmp;
+ }
+ return b;
+}
+
+/*
+ * Various code constructs need to know the layout of the data link
+ * layer. These variables give the necessary offsets. off_linktype
+ * is set to -1 for no encapsulation, in which case, IP is assumed.
+ */
+static u_int off_linktype;
+static u_int off_nl;
+static int linktype;
+
+static void
+init_linktype(type)
+ int type;
+{
+ linktype = type;
+
+ switch (type) {
+
+ case DLT_EN10MB:
+ off_linktype = 12;
+ off_nl = 14;
+ return;
+
+ case DLT_SLIP:
+ /*
+ * SLIP doesn't have a link level type. The 16 byte
+ * header is hacked into our SLIP driver.
+ */
+ off_linktype = -1;
+ off_nl = 16;
+ return;
+
+ case DLT_SLIP_BSDOS:
+ /* XXX this may be the same as the DLT_PPP_BSDOS case */
+ off_linktype = -1;
+ /* XXX end */
+ off_nl = 24;
+ return;
+
+ case DLT_NULL:
+ off_linktype = 0;
+ off_nl = 4;
+ return;
+
+ case DLT_PPP:
+ off_linktype = 2;
+ off_nl = 4;
+ return;
+
+ case DLT_PPP_BSDOS:
+ off_linktype = 5;
+ off_nl = 24;
+ return;
+
+ case DLT_FDDI:
+ /*
+ * FDDI doesn't really have a link-level type field.
+ * We assume that SSAP = SNAP is being used and pick
+ * out the encapsulated Ethernet type.
+ */
+ off_linktype = 19;
+#ifdef PCAP_FDDIPAD
+ off_linktype += pcap_fddipad;
+#endif
+ off_nl = 21;
+#ifdef PCAP_FDDIPAD
+ off_nl += pcap_fddipad;
+#endif
+ return;
+
+ case DLT_IEEE802:
+ off_linktype = 20;
+ off_nl = 22;
+ return;
+
+ case DLT_ATM_RFC1483:
+ /*
+ * assume routed, non-ISO PDUs
+ * (i.e., LLC = 0xAA-AA-03, OUT = 0x00-00-00)
+ */
+ off_linktype = 6;
+ off_nl = 8;
+ return;
+
+ case DLT_RAW:
+ off_linktype = -1;
+ off_nl = 0;
+ return;
+ }
+ bpf_error("unknown data link type 0x%x", linktype);
+ /* NOTREACHED */
+}
+
+static struct block *
+gen_uncond(rsense)
+ int rsense;
+{
+ struct block *b;
+ struct slist *s;
+
+ s = new_stmt(BPF_LD|BPF_IMM);
+ s->s.k = !rsense;
+ b = new_block(JMP(BPF_JEQ));
+ b->stmts = s;
+
+ return b;
+}
+
+static inline struct block *
+gen_true()
+{
+ return gen_uncond(1);
+}
+
+static inline struct block *
+gen_false()
+{
+ return gen_uncond(0);
+}
+
+static struct block *
+gen_linktype(proto)
+ register int proto;
+{
+ struct block *b0, *b1;
+
+ /* If we're not using encapsulation and checking for IP, we're done */
+ if (off_linktype == -1 && proto == ETHERTYPE_IP)
+ return gen_true();
+
+ switch (linktype) {
+
+ case DLT_SLIP:
+ return gen_false();
+
+ case DLT_PPP:
+ if (proto == ETHERTYPE_IP)
+ proto = PPP_IP; /* XXX was 0x21 */
+ break;
+
+ case DLT_PPP_BSDOS:
+ switch (proto) {
+
+ case ETHERTYPE_IP:
+ b0 = gen_cmp(off_linktype, BPF_H, PPP_IP);
+ b1 = gen_cmp(off_linktype, BPF_H, PPP_VJC);
+ gen_or(b0, b1);
+ b0 = gen_cmp(off_linktype, BPF_H, PPP_VJNC);
+ gen_or(b1, b0);
+ return b0;
+
+ case ETHERTYPE_DN:
+ proto = PPP_DECNET;
+ break;
+
+ case ETHERTYPE_ATALK:
+ proto = PPP_APPLE;
+ break;
+
+ case ETHERTYPE_NS:
+ proto = PPP_NS;
+ break;
+ }
+ break;
+
+ case DLT_NULL:
+ /* XXX */
+ if (proto == ETHERTYPE_IP)
+ return (gen_cmp(0, BPF_W, (bpf_int32)htonl(AF_INET)));
+ else
+ return gen_false();
+ }
+ return gen_cmp(off_linktype, BPF_H, (bpf_int32)proto);
+}
+
+static struct block *
+gen_hostop(addr, mask, dir, proto, src_off, dst_off)
+ bpf_u_int32 addr;
+ bpf_u_int32 mask;
+ int dir, proto;
+ u_int src_off, dst_off;
+{
+ struct block *b0, *b1;
+ u_int offset;
+
+ switch (dir) {
+
+ case Q_SRC:
+ offset = src_off;
+ break;
+
+ case Q_DST:
+ offset = dst_off;
+ break;
+
+ case Q_AND:
+ b0 = gen_hostop(addr, mask, Q_SRC, proto, src_off, dst_off);
+ b1 = gen_hostop(addr, mask, Q_DST, proto, src_off, dst_off);
+ gen_and(b0, b1);
+ return b1;
+
+ case Q_OR:
+ case Q_DEFAULT:
+ b0 = gen_hostop(addr, mask, Q_SRC, proto, src_off, dst_off);
+ b1 = gen_hostop(addr, mask, Q_DST, proto, src_off, dst_off);
+ gen_or(b0, b1);
+ return b1;
+
+ default:
+ abort();
+ }
+ b0 = gen_linktype(proto);
+ b1 = gen_mcmp(offset, BPF_W, (bpf_int32)addr, mask);
+ gen_and(b0, b1);
+ return b1;
+}
+
+static struct block *
+gen_ehostop(eaddr, dir)
+ register const u_char *eaddr;
+ register int dir;
+{
+ register struct block *b0, *b1;
+
+ switch (dir) {
+ case Q_SRC:
+ return gen_bcmp(6, 6, eaddr);
+
+ case Q_DST:
+ return gen_bcmp(0, 6, eaddr);
+
+ case Q_AND:
+ b0 = gen_ehostop(eaddr, Q_SRC);
+ b1 = gen_ehostop(eaddr, Q_DST);
+ gen_and(b0, b1);
+ return b1;
+
+ case Q_DEFAULT:
+ case Q_OR:
+ b0 = gen_ehostop(eaddr, Q_SRC);
+ b1 = gen_ehostop(eaddr, Q_DST);
+ gen_or(b0, b1);
+ return b1;
+ }
+ abort();
+ /* NOTREACHED */
+}
+
+/*
+ * Like gen_ehostop, but for DLT_FDDI
+ */
+static struct block *
+gen_fhostop(eaddr, dir)
+ register const u_char *eaddr;
+ register int dir;
+{
+ struct block *b0, *b1;
+
+ switch (dir) {
+ case Q_SRC:
+#ifdef PCAP_FDDIPAD
+ return gen_bcmp(6 + 1 + pcap_fddipad, 6, eaddr);
+#else
+ return gen_bcmp(6 + 1, 6, eaddr);
+#endif
+
+ case Q_DST:
+#ifdef PCAP_FDDIPAD
+ return gen_bcmp(0 + 1 + pcap_fddipad, 6, eaddr);
+#else
+ return gen_bcmp(0 + 1, 6, eaddr);
+#endif
+
+ case Q_AND:
+ b0 = gen_fhostop(eaddr, Q_SRC);
+ b1 = gen_fhostop(eaddr, Q_DST);
+ gen_and(b0, b1);
+ return b1;
+
+ case Q_DEFAULT:
+ case Q_OR:
+ b0 = gen_fhostop(eaddr, Q_SRC);
+ b1 = gen_fhostop(eaddr, Q_DST);
+ gen_or(b0, b1);
+ return b1;
+ }
+ abort();
+ /* NOTREACHED */
+}
+
+/*
+ * This is quite tricky because there may be pad bytes in front of the
+ * DECNET header, and then there are two possible data packet formats that
+ * carry both src and dst addresses, plus 5 packet types in a format that
+ * carries only the src node, plus 2 types that use a different format and
+ * also carry just the src node.
+ *
+ * Yuck.
+ *
+ * Instead of doing those all right, we just look for data packets with
+ * 0 or 1 bytes of padding. If you want to look at other packets, that
+ * will require a lot more hacking.
+ *
+ * To add support for filtering on DECNET "areas" (network numbers)
+ * one would want to add a "mask" argument to this routine. That would
+ * make the filter even more inefficient, although one could be clever
+ * and not generate masking instructions if the mask is 0xFFFF.
+ */
+static struct block *
+gen_dnhostop(addr, dir, base_off)
+ bpf_u_int32 addr;
+ int dir;
+ u_int base_off;
+{
+ struct block *b0, *b1, *b2, *tmp;
+ u_int offset_lh; /* offset if long header is received */
+ u_int offset_sh; /* offset if short header is received */
+
+ switch (dir) {
+
+ case Q_DST:
+ offset_sh = 1; /* follows flags */
+ offset_lh = 7; /* flgs,darea,dsubarea,HIORD */
+ break;
+
+ case Q_SRC:
+ offset_sh = 3; /* follows flags, dstnode */
+ offset_lh = 15; /* flgs,darea,dsubarea,did,sarea,ssub,HIORD */
+ break;
+
+ case Q_AND:
+ /* Inefficient because we do our Calvinball dance twice */
+ b0 = gen_dnhostop(addr, Q_SRC, base_off);
+ b1 = gen_dnhostop(addr, Q_DST, base_off);
+ gen_and(b0, b1);
+ return b1;
+
+ case Q_OR:
+ case Q_DEFAULT:
+ /* Inefficient because we do our Calvinball dance twice */
+ b0 = gen_dnhostop(addr, Q_SRC, base_off);
+ b1 = gen_dnhostop(addr, Q_DST, base_off);
+ gen_or(b0, b1);
+ return b1;
+
+ default:
+ abort();
+ }
+ b0 = gen_linktype(ETHERTYPE_DN);
+ /* Check for pad = 1, long header case */
+ tmp = gen_mcmp(base_off + 2, BPF_H,
+ (bpf_int32)ntohs(0x0681), (bpf_int32)ntohs(0x07FF));
+ b1 = gen_cmp(base_off + 2 + 1 + offset_lh,
+ BPF_H, (bpf_int32)ntohs(addr));
+ gen_and(tmp, b1);
+ /* Check for pad = 0, long header case */
+ tmp = gen_mcmp(base_off + 2, BPF_B, (bpf_int32)0x06, (bpf_int32)0x7);
+ b2 = gen_cmp(base_off + 2 + offset_lh, BPF_H, (bpf_int32)ntohs(addr));
+ gen_and(tmp, b2);
+ gen_or(b2, b1);
+ /* Check for pad = 1, short header case */
+ tmp = gen_mcmp(base_off + 2, BPF_H,
+ (bpf_int32)ntohs(0x0281), (bpf_int32)ntohs(0x07FF));
+ b2 = gen_cmp(base_off + 2 + 1 + offset_sh,
+ BPF_H, (bpf_int32)ntohs(addr));
+ gen_and(tmp, b2);
+ gen_or(b2, b1);
+ /* Check for pad = 0, short header case */
+ tmp = gen_mcmp(base_off + 2, BPF_B, (bpf_int32)0x02, (bpf_int32)0x7);
+ b2 = gen_cmp(base_off + 2 + offset_sh, BPF_H, (bpf_int32)ntohs(addr));
+ gen_and(tmp, b2);
+ gen_or(b2, b1);
+
+ /* Combine with test for linktype */
+ gen_and(b0, b1);
+ return b1;
+}
+
+static struct block *
+gen_host(addr, mask, proto, dir)
+ bpf_u_int32 addr;
+ bpf_u_int32 mask;
+ int proto;
+ int dir;
+{
+ struct block *b0, *b1;
+
+ switch (proto) {
+
+ case Q_DEFAULT:
+ b0 = gen_host(addr, mask, Q_IP, dir);
+ b1 = gen_host(addr, mask, Q_ARP, dir);
+ gen_or(b0, b1);
+ b0 = gen_host(addr, mask, Q_RARP, dir);
+ gen_or(b1, b0);
+ return b0;
+
+ case Q_IP:
+ return gen_hostop(addr, mask, dir, ETHERTYPE_IP,
+ off_nl + 12, off_nl + 16);
+
+ case Q_RARP:
+ return gen_hostop(addr, mask, dir, ETHERTYPE_REVARP,
+ off_nl + 14, off_nl + 24);
+
+ case Q_ARP:
+ return gen_hostop(addr, mask, dir, ETHERTYPE_ARP,
+ off_nl + 14, off_nl + 24);
+
+ case Q_TCP:
+ bpf_error("'tcp' modifier applied to host");
+
+ case Q_UDP:
+ bpf_error("'udp' modifier applied to host");
+
+ case Q_ICMP:
+ bpf_error("'icmp' modifier applied to host");
+
+ case Q_IGMP:
+ bpf_error("'igmp' modifier applied to host");
+
+ case Q_IGRP:
+ bpf_error("'igrp' modifier applied to host");
+
+ case Q_ATALK:
+ bpf_error("ATALK host filtering not implemented");
+
+ case Q_DECNET:
+ return gen_dnhostop(addr, dir, off_nl);
+
+ case Q_SCA:
+ bpf_error("SCA host filtering not implemented");
+
+ case Q_LAT:
+ bpf_error("LAT host filtering not implemented");
+
+ case Q_MOPDL:
+ bpf_error("MOPDL host filtering not implemented");
+
+ case Q_MOPRC:
+ bpf_error("MOPRC host filtering not implemented");
+
+ default:
+ abort();
+ }
+ /* NOTREACHED */
+}
+
+static struct block *
+gen_gateway(eaddr, alist, proto, dir)
+ const u_char *eaddr;
+ bpf_u_int32 **alist;
+ int proto;
+ int dir;
+{
+ struct block *b0, *b1, *tmp;
+
+ if (dir != 0)
+ bpf_error("direction applied to 'gateway'");
+
+ switch (proto) {
+ case Q_DEFAULT:
+ case Q_IP:
+ case Q_ARP:
+ case Q_RARP:
+ if (linktype == DLT_EN10MB)
+ b0 = gen_ehostop(eaddr, Q_OR);
+ else if (linktype == DLT_FDDI)
+ b0 = gen_fhostop(eaddr, Q_OR);
+ else
+ bpf_error(
+ "'gateway' supported only on ethernet or FDDI");
+
+ b1 = gen_host(**alist++, 0xffffffff, proto, Q_OR);
+ while (*alist) {
+ tmp = gen_host(**alist++, 0xffffffff, proto, Q_OR);
+ gen_or(b1, tmp);
+ b1 = tmp;
+ }
+ gen_not(b1);
+ gen_and(b0, b1);
+ return b1;
+ }
+ bpf_error("illegal modifier of 'gateway'");
+ /* NOTREACHED */
+}
+
+struct block *
+gen_proto_abbrev(proto)
+ int proto;
+{
+ struct block *b0, *b1;
+
+ switch (proto) {
+
+ case Q_TCP:
+ b0 = gen_linktype(ETHERTYPE_IP);
+ b1 = gen_cmp(off_nl + 9, BPF_B, (bpf_int32)IPPROTO_TCP);
+ gen_and(b0, b1);
+ break;
+
+ case Q_UDP:
+ b0 = gen_linktype(ETHERTYPE_IP);
+ b1 = gen_cmp(off_nl + 9, BPF_B, (bpf_int32)IPPROTO_UDP);
+ gen_and(b0, b1);
+ break;
+
+ case Q_ICMP:
+ b0 = gen_linktype(ETHERTYPE_IP);
+ b1 = gen_cmp(off_nl + 9, BPF_B, (bpf_int32)IPPROTO_ICMP);
+ gen_and(b0, b1);
+ break;
+
+ case Q_IGMP:
+ b0 = gen_linktype(ETHERTYPE_IP);
+ b1 = gen_cmp(off_nl + 9, BPF_B, (bpf_int32)2);
+ gen_and(b0, b1);
+ break;
+
+#ifndef IPPROTO_IGRP
+#define IPPROTO_IGRP 9
+#endif
+ case Q_IGRP:
+ b0 = gen_linktype(ETHERTYPE_IP);
+ b1 = gen_cmp(off_nl + 9, BPF_B, (long)IPPROTO_IGRP);
+ gen_and(b0, b1);
+ break;
+
+ case Q_IP:
+ b1 = gen_linktype(ETHERTYPE_IP);
+ break;
+
+ case Q_ARP:
+ b1 = gen_linktype(ETHERTYPE_ARP);
+ break;
+
+ case Q_RARP:
+ b1 = gen_linktype(ETHERTYPE_REVARP);
+ break;
+
+ case Q_LINK:
+ bpf_error("link layer applied in wrong context");
+
+ case Q_ATALK:
+ b1 = gen_linktype(ETHERTYPE_ATALK);
+ break;
+
+ case Q_DECNET:
+ b1 = gen_linktype(ETHERTYPE_DN);
+ break;
+
+ case Q_SCA:
+ b1 = gen_linktype(ETHERTYPE_SCA);
+ break;
+
+ case Q_LAT:
+ b1 = gen_linktype(ETHERTYPE_LAT);
+ break;
+
+ case Q_MOPDL:
+ b1 = gen_linktype(ETHERTYPE_MOPDL);
+ break;
+
+ case Q_MOPRC:
+ b1 = gen_linktype(ETHERTYPE_MOPRC);
+ break;
+
+ default:
+ abort();
+ }
+ return b1;
+}
+
+static struct block *
+gen_ipfrag()
+{
+ struct slist *s;
+ struct block *b;
+
+ /* not ip frag */
+ s = new_stmt(BPF_LD|BPF_H|BPF_ABS);
+ s->s.k = off_nl + 6;
+ b = new_block(JMP(BPF_JSET));
+ b->s.k = 0x1fff;
+ b->stmts = s;
+ gen_not(b);
+
+ return b;
+}
+
+static struct block *
+gen_portatom(off, v)
+ int off;
+ bpf_int32 v;
+{
+ struct slist *s;
+ struct block *b;
+
+ s = new_stmt(BPF_LDX|BPF_MSH|BPF_B);
+ s->s.k = off_nl;
+
+ s->next = new_stmt(BPF_LD|BPF_IND|BPF_H);
+ s->next->s.k = off_nl + off;
+
+ b = new_block(JMP(BPF_JEQ));
+ b->stmts = s;
+ b->s.k = v;
+
+ return b;
+}
+
+struct block *
+gen_portop(port, proto, dir)
+ int port, proto, dir;
+{
+ struct block *b0, *b1, *tmp;
+
+ /* ip proto 'proto' */
+ tmp = gen_cmp(off_nl + 9, BPF_B, (bpf_int32)proto);
+ b0 = gen_ipfrag();
+ gen_and(tmp, b0);
+
+ switch (dir) {
+ case Q_SRC:
+ b1 = gen_portatom(0, (bpf_int32)port);
+ break;
+
+ case Q_DST:
+ b1 = gen_portatom(2, (bpf_int32)port);
+ break;
+
+ case Q_OR:
+ case Q_DEFAULT:
+ tmp = gen_portatom(0, (bpf_int32)port);
+ b1 = gen_portatom(2, (bpf_int32)port);
+ gen_or(tmp, b1);
+ break;
+
+ case Q_AND:
+ tmp = gen_portatom(0, (bpf_int32)port);
+ b1 = gen_portatom(2, (bpf_int32)port);
+ gen_and(tmp, b1);
+ break;
+
+ default:
+ abort();
+ }
+ gen_and(b0, b1);
+
+ return b1;
+}
+
+static struct block *
+gen_port(port, ip_proto, dir)
+ int port;
+ int ip_proto;
+ int dir;
+{
+ struct block *b0, *b1, *tmp;
+
+ /* ether proto ip */
+ b0 = gen_linktype(ETHERTYPE_IP);
+
+ switch (ip_proto) {
+ case IPPROTO_UDP:
+ case IPPROTO_TCP:
+ b1 = gen_portop(port, ip_proto, dir);
+ break;
+
+ case PROTO_UNDEF:
+ tmp = gen_portop(port, IPPROTO_TCP, dir);
+ b1 = gen_portop(port, IPPROTO_UDP, dir);
+ gen_or(tmp, b1);
+ break;
+
+ default:
+ abort();
+ }
+ gen_and(b0, b1);
+ return b1;
+}
+
+static int
+lookup_proto(name, proto)
+ register const char *name;
+ register int proto;
+{
+ register int v;
+
+ switch (proto) {
+
+ case Q_DEFAULT:
+ case Q_IP:
+ v = pcap_nametoproto(name);
+ if (v == PROTO_UNDEF)
+ bpf_error("unknown ip proto '%s'", name);
+ break;
+
+ case Q_LINK:
+ /* XXX should look up h/w protocol type based on linktype */
+ v = pcap_nametoeproto(name);
+ if (v == PROTO_UNDEF)
+ bpf_error("unknown ether proto '%s'", name);
+ break;
+
+ default:
+ v = PROTO_UNDEF;
+ break;
+ }
+ return v;
+}
+
+static struct block *
+gen_proto(v, proto, dir)
+ int v;
+ int proto;
+ int dir;
+{
+ struct block *b0, *b1;
+
+ if (dir != Q_DEFAULT)
+ bpf_error("direction applied to 'proto'");
+
+ switch (proto) {
+ case Q_DEFAULT:
+ case Q_IP:
+ b0 = gen_linktype(ETHERTYPE_IP);
+ b1 = gen_cmp(off_nl + 9, BPF_B, (bpf_int32)v);
+ gen_and(b0, b1);
+ return b1;
+
+ case Q_ARP:
+ bpf_error("arp does not encapsulate another protocol");
+ /* NOTREACHED */
+
+ case Q_RARP:
+ bpf_error("rarp does not encapsulate another protocol");
+ /* NOTREACHED */
+
+ case Q_ATALK:
+ bpf_error("atalk encapsulation is not specifiable");
+ /* NOTREACHED */
+
+ case Q_DECNET:
+ bpf_error("decnet encapsulation is not specifiable");
+ /* NOTREACHED */
+
+ case Q_SCA:
+ bpf_error("sca does not encapsulate another protocol");
+ /* NOTREACHED */
+
+ case Q_LAT:
+ bpf_error("lat does not encapsulate another protocol");
+ /* NOTREACHED */
+
+ case Q_MOPRC:
+ bpf_error("moprc does not encapsulate another protocol");
+ /* NOTREACHED */
+
+ case Q_MOPDL:
+ bpf_error("mopdl does not encapsulate another protocol");
+ /* NOTREACHED */
+
+ case Q_LINK:
+ return gen_linktype(v);
+
+ case Q_UDP:
+ bpf_error("'udp proto' is bogus");
+ /* NOTREACHED */
+
+ case Q_TCP:
+ bpf_error("'tcp proto' is bogus");
+ /* NOTREACHED */
+
+ case Q_ICMP:
+ bpf_error("'icmp proto' is bogus");
+ /* NOTREACHED */
+
+ case Q_IGMP:
+ bpf_error("'igmp proto' is bogus");
+ /* NOTREACHED */
+
+ case Q_IGRP:
+ bpf_error("'igrp proto' is bogus");
+ /* NOTREACHED */
+
+ default:
+ abort();
+ /* NOTREACHED */
+ }
+ /* NOTREACHED */
+}
+
+struct block *
+gen_scode(name, q)
+ register const char *name;
+ struct qual q;
+{
+ int proto = q.proto;
+ int dir = q.dir;
+ int tproto;
+ u_char *eaddr;
+ bpf_u_int32 mask, addr, **alist;
+ struct block *b, *tmp;
+ int port, real_proto;
+
+ switch (q.addr) {
+
+ case Q_NET:
+ addr = pcap_nametonetaddr(name);
+ if (addr == 0)
+ bpf_error("unknown network '%s'", name);
+ /* Left justify network addr and calculate its network mask */
+ mask = 0xffffffff;
+ while (addr && (addr & 0xff000000) == 0) {
+ addr <<= 8;
+ mask <<= 8;
+ }
+ return gen_host(addr, mask, proto, dir);
+
+ case Q_DEFAULT:
+ case Q_HOST:
+ if (proto == Q_LINK) {
+ switch (linktype) {
+
+ case DLT_EN10MB:
+ eaddr = pcap_ether_hostton(name);
+ if (eaddr == NULL)
+ bpf_error(
+ "unknown ether host '%s'", name);
+ return gen_ehostop(eaddr, dir);
+
+ case DLT_FDDI:
+ eaddr = pcap_ether_hostton(name);
+ if (eaddr == NULL)
+ bpf_error(
+ "unknown FDDI host '%s'", name);
+ return gen_fhostop(eaddr, dir);
+
+ default:
+ bpf_error(
+ "only ethernet/FDDI supports link-level host name");
+ break;
+ }
+ } else if (proto == Q_DECNET) {
+ unsigned short dn_addr = __pcap_nametodnaddr(name);
+ /*
+ * I don't think DECNET hosts can be multihomed, so
+ * there is no need to build up a list of addresses
+ */
+ return (gen_host(dn_addr, 0, proto, dir));
+ } else {
+ alist = pcap_nametoaddr(name);
+ if (alist == NULL || *alist == NULL)
+ bpf_error("unknown host '%s'", name);
+ tproto = proto;
+ if (off_linktype == -1 && tproto == Q_DEFAULT)
+ tproto = Q_IP;
+ b = gen_host(**alist++, 0xffffffff, tproto, dir);
+ while (*alist) {
+ tmp = gen_host(**alist++, 0xffffffff,
+ tproto, dir);
+ gen_or(b, tmp);
+ b = tmp;
+ }
+ return b;
+ }
+
+ case Q_PORT:
+ if (proto != Q_DEFAULT && proto != Q_UDP && proto != Q_TCP)
+ bpf_error("illegal qualifier of 'port'");
+ if (pcap_nametoport(name, &port, &real_proto) == 0)
+ bpf_error("unknown port '%s'", name);
+ if (proto == Q_UDP) {
+ if (real_proto == IPPROTO_TCP)
+ bpf_error("port '%s' is tcp", name);
+ else
+ /* override PROTO_UNDEF */
+ real_proto = IPPROTO_UDP;
+ }
+ if (proto == Q_TCP) {
+ if (real_proto == IPPROTO_UDP)
+ bpf_error("port '%s' is udp", name);
+ else
+ /* override PROTO_UNDEF */
+ real_proto = IPPROTO_TCP;
+ }
+ return gen_port(port, real_proto, dir);
+
+ case Q_GATEWAY:
+ eaddr = pcap_ether_hostton(name);
+ if (eaddr == NULL)
+ bpf_error("unknown ether host: %s", name);
+
+ alist = pcap_nametoaddr(name);
+ if (alist == NULL || *alist == NULL)
+ bpf_error("unknown host '%s'", name);
+ return gen_gateway(eaddr, alist, proto, dir);
+
+ case Q_PROTO:
+ real_proto = lookup_proto(name, proto);
+ if (real_proto >= 0)
+ return gen_proto(real_proto, proto, dir);
+ else
+ bpf_error("unknown protocol: %s", name);
+
+ case Q_UNDEF:
+ syntax();
+ /* NOTREACHED */
+ }
+ abort();
+ /* NOTREACHED */
+}
+
+struct block *
+gen_mcode(s1, s2, masklen, q)
+ register const char *s1, *s2;
+ register int masklen;
+ struct qual q;
+{
+ register int nlen, mlen;
+ bpf_u_int32 n, m;
+
+ nlen = __pcap_atoin(s1, &n);
+ /* Promote short ipaddr */
+ n <<= 32 - nlen;
+
+ if (s2 != NULL) {
+ mlen = __pcap_atoin(s2, &m);
+ /* Promote short ipaddr */
+ m <<= 32 - mlen;
+ if ((n & ~m) != 0)
+ bpf_error("non-network bits set in \"%s mask %s\"",
+ s1, s2);
+ } else {
+ /* Convert mask len to mask */
+ if (masklen > 32)
+ bpf_error("mask length must be <= 32");
+ m = 0xffffffff << (32 - masklen);
+ if ((n & ~m) != 0)
+ bpf_error("non-network bits set in \"%s/%d\"",
+ s1, masklen);
+ }
+
+ switch (q.addr) {
+
+ case Q_NET:
+ return gen_host(n, m, q.proto, q.dir);
+
+ default:
+ bpf_error("Mask syntax for networks only");
+ /* NOTREACHED */
+ }
+}
+
+struct block *
+gen_ncode(s, v, q)
+ register const char *s;
+ bpf_u_int32 v;
+ struct qual q;
+{
+ bpf_u_int32 mask;
+ int proto = q.proto;
+ int dir = q.dir;
+ register int vlen;
+
+ if (s == NULL)
+ vlen = 32;
+ else if (q.proto == Q_DECNET)
+ vlen = __pcap_atodn(s, &v);
+ else
+ vlen = __pcap_atoin(s, &v);
+
+ switch (q.addr) {
+
+ case Q_DEFAULT:
+ case Q_HOST:
+ case Q_NET:
+ if (proto == Q_DECNET)
+ return gen_host(v, 0, proto, dir);
+ else if (proto == Q_LINK) {
+ bpf_error("illegal link layer address");
+ } else {
+ mask = 0xffffffff;
+ if (s == NULL && q.addr == Q_NET) {
+ /* Promote short net number */
+ while (v && (v & 0xff000000) == 0) {
+ v <<= 8;
+ mask <<= 8;
+ }
+ } else {
+ /* Promote short ipaddr */
+ v <<= 32 - vlen;
+ mask <<= 32 - vlen;
+ }
+ return gen_host(v, mask, proto, dir);
+ }
+
+ case Q_PORT:
+ if (proto == Q_UDP)
+ proto = IPPROTO_UDP;
+ else if (proto == Q_TCP)
+ proto = IPPROTO_TCP;
+ else if (proto == Q_DEFAULT)
+ proto = PROTO_UNDEF;
+ else
+ bpf_error("illegal qualifier of 'port'");
+
+ return gen_port((int)v, proto, dir);
+
+ case Q_GATEWAY:
+ bpf_error("'gateway' requires a name");
+ /* NOTREACHED */
+
+ case Q_PROTO:
+ return gen_proto((int)v, proto, dir);
+
+ case Q_UNDEF:
+ syntax();
+ /* NOTREACHED */
+
+ default:
+ abort();
+ /* NOTREACHED */
+ }
+ /* NOTREACHED */
+}
+
+struct block *
+gen_ecode(eaddr, q)
+ register const u_char *eaddr;
+ struct qual q;
+{
+ if ((q.addr == Q_HOST || q.addr == Q_DEFAULT) && q.proto == Q_LINK) {
+ if (linktype == DLT_EN10MB)
+ return gen_ehostop(eaddr, (int)q.dir);
+ if (linktype == DLT_FDDI)
+ return gen_fhostop(eaddr, (int)q.dir);
+ }
+ bpf_error("ethernet address used in non-ether expression");
+ /* NOTREACHED */
+}
+
+void
+sappend(s0, s1)
+ struct slist *s0, *s1;
+{
+ /*
+ * This is definitely not the best way to do this, but the
+ * lists will rarely get long.
+ */
+ while (s0->next)
+ s0 = s0->next;
+ s0->next = s1;
+}
+
+static struct slist *
+xfer_to_x(a)
+ struct arth *a;
+{
+ struct slist *s;
+
+ s = new_stmt(BPF_LDX|BPF_MEM);
+ s->s.k = a->regno;
+ return s;
+}
+
+static struct slist *
+xfer_to_a(a)
+ struct arth *a;
+{
+ struct slist *s;
+
+ s = new_stmt(BPF_LD|BPF_MEM);
+ s->s.k = a->regno;
+ return s;
+}
+
+struct arth *
+gen_load(proto, index, size)
+ int proto;
+ struct arth *index;
+ int size;
+{
+ struct slist *s, *tmp;
+ struct block *b;
+ int regno = alloc_reg();
+
+ free_reg(index->regno);
+ switch (size) {
+
+ default:
+ bpf_error("data size must be 1, 2, or 4");
+
+ case 1:
+ size = BPF_B;
+ break;
+
+ case 2:
+ size = BPF_H;
+ break;
+
+ case 4:
+ size = BPF_W;
+ break;
+ }
+ switch (proto) {
+ default:
+ bpf_error("unsupported index operation");
+
+ case Q_LINK:
+ s = xfer_to_x(index);
+ tmp = new_stmt(BPF_LD|BPF_IND|size);
+ sappend(s, tmp);
+ sappend(index->s, s);
+ break;
+
+ case Q_IP:
+ case Q_ARP:
+ case Q_RARP:
+ case Q_ATALK:
+ case Q_DECNET:
+ case Q_SCA:
+ case Q_LAT:
+ case Q_MOPRC:
+ case Q_MOPDL:
+ /* XXX Note that we assume a fixed link link header here. */
+ s = xfer_to_x(index);
+ tmp = new_stmt(BPF_LD|BPF_IND|size);
+ tmp->s.k = off_nl;
+ sappend(s, tmp);
+ sappend(index->s, s);
+
+ b = gen_proto_abbrev(proto);
+ if (index->b)
+ gen_and(index->b, b);
+ index->b = b;
+ break;
+
+ case Q_TCP:
+ case Q_UDP:
+ case Q_ICMP:
+ case Q_IGMP:
+ case Q_IGRP:
+ s = new_stmt(BPF_LDX|BPF_MSH|BPF_B);
+ s->s.k = off_nl;
+ sappend(s, xfer_to_a(index));
+ sappend(s, new_stmt(BPF_ALU|BPF_ADD|BPF_X));
+ sappend(s, new_stmt(BPF_MISC|BPF_TAX));
+ sappend(s, tmp = new_stmt(BPF_LD|BPF_IND|size));
+ tmp->s.k = off_nl;
+ sappend(index->s, s);
+
+ gen_and(gen_proto_abbrev(proto), b = gen_ipfrag());
+ if (index->b)
+ gen_and(index->b, b);
+ index->b = b;
+ break;
+ }
+ index->regno = regno;
+ s = new_stmt(BPF_ST);
+ s->s.k = regno;
+ sappend(index->s, s);
+
+ return index;
+}
+
+struct block *
+gen_relation(code, a0, a1, reversed)
+ int code;
+ struct arth *a0, *a1;
+ int reversed;
+{
+ struct slist *s0, *s1, *s2;
+ struct block *b, *tmp;
+
+ s0 = xfer_to_x(a1);
+ s1 = xfer_to_a(a0);
+ s2 = new_stmt(BPF_ALU|BPF_SUB|BPF_X);
+ b = new_block(JMP(code));
+ if (code == BPF_JGT || code == BPF_JGE) {
+ reversed = !reversed;
+ b->s.k = 0x80000000;
+ }
+ if (reversed)
+ gen_not(b);
+
+ sappend(s1, s2);
+ sappend(s0, s1);
+ sappend(a1->s, s0);
+ sappend(a0->s, a1->s);
+
+ b->stmts = a0->s;
+
+ free_reg(a0->regno);
+ free_reg(a1->regno);
+
+ /* 'and' together protocol checks */
+ if (a0->b) {
+ if (a1->b) {
+ gen_and(a0->b, tmp = a1->b);
+ }
+ else
+ tmp = a0->b;
+ } else
+ tmp = a1->b;
+
+ if (tmp)
+ gen_and(tmp, b);
+
+ return b;
+}
+
+struct arth *
+gen_loadlen()
+{
+ int regno = alloc_reg();
+ struct arth *a = (struct arth *)newchunk(sizeof(*a));
+ struct slist *s;
+
+ s = new_stmt(BPF_LD|BPF_LEN);
+ s->next = new_stmt(BPF_ST);
+ s->next->s.k = regno;
+ a->s = s;
+ a->regno = regno;
+
+ return a;
+}
+
+struct arth *
+gen_loadi(val)
+ int val;
+{
+ struct arth *a;
+ struct slist *s;
+ int reg;
+
+ a = (struct arth *)newchunk(sizeof(*a));
+
+ reg = alloc_reg();
+
+ s = new_stmt(BPF_LD|BPF_IMM);
+ s->s.k = val;
+ s->next = new_stmt(BPF_ST);
+ s->next->s.k = reg;
+ a->s = s;
+ a->regno = reg;
+
+ return a;
+}
+
+struct arth *
+gen_neg(a)
+ struct arth *a;
+{
+ struct slist *s;
+
+ s = xfer_to_a(a);
+ sappend(a->s, s);
+ s = new_stmt(BPF_ALU|BPF_NEG);
+ s->s.k = 0;
+ sappend(a->s, s);
+ s = new_stmt(BPF_ST);
+ s->s.k = a->regno;
+ sappend(a->s, s);
+
+ return a;
+}
+
+struct arth *
+gen_arth(code, a0, a1)
+ int code;
+ struct arth *a0, *a1;
+{
+ struct slist *s0, *s1, *s2;
+
+ s0 = xfer_to_x(a1);
+ s1 = xfer_to_a(a0);
+ s2 = new_stmt(BPF_ALU|BPF_X|code);
+
+ sappend(s1, s2);
+ sappend(s0, s1);
+ sappend(a1->s, s0);
+ sappend(a0->s, a1->s);
+
+ free_reg(a1->regno);
+
+ s0 = new_stmt(BPF_ST);
+ a0->regno = s0->s.k = alloc_reg();
+ sappend(a0->s, s0);
+
+ return a0;
+}
+
+/*
+ * Here we handle simple allocation of the scratch registers.
+ * If too many registers are alloc'd, the allocator punts.
+ */
+static int regused[BPF_MEMWORDS];
+static int curreg;
+
+/*
+ * Return the next free register.
+ */
+static int
+alloc_reg()
+{
+ int n = BPF_MEMWORDS;
+
+ while (--n >= 0) {
+ if (regused[curreg])
+ curreg = (curreg + 1) % BPF_MEMWORDS;
+ else {
+ regused[curreg] = 1;
+ return curreg;
+ }
+ }
+ bpf_error("too many registers needed to evaluate expression");
+ /* NOTREACHED */
+}
+
+/*
+ * Return a register to the table so it can
+ * be used later.
+ */
+static void
+free_reg(n)
+ int n;
+{
+ regused[n] = 0;
+}
+
+static struct block *
+gen_len(jmp, n)
+ int jmp, n;
+{
+ struct slist *s;
+ struct block *b;
+
+ s = new_stmt(BPF_LD|BPF_LEN);
+ b = new_block(JMP(jmp));
+ b->stmts = s;
+ b->s.k = n;
+
+ return b;
+}
+
+struct block *
+gen_greater(n)
+ int n;
+{
+ return gen_len(BPF_JGE, n);
+}
+
+struct block *
+gen_less(n)
+ int n;
+{
+ struct block *b;
+
+ b = gen_len(BPF_JGT, n);
+ gen_not(b);
+
+ return b;
+}
+
+struct block *
+gen_byteop(op, idx, val)
+ int op, idx, val;
+{
+ struct block *b;
+ struct slist *s;
+
+ switch (op) {
+ default:
+ abort();
+
+ case '=':
+ return gen_cmp((u_int)idx, BPF_B, (bpf_int32)val);
+
+ case '<':
+ b = gen_cmp((u_int)idx, BPF_B, (bpf_int32)val);
+ b->s.code = JMP(BPF_JGE);
+ gen_not(b);
+ return b;
+
+ case '>':
+ b = gen_cmp((u_int)idx, BPF_B, (bpf_int32)val);
+ b->s.code = JMP(BPF_JGT);
+ return b;
+
+ case '|':
+ s = new_stmt(BPF_ALU|BPF_OR|BPF_K);
+ break;
+
+ case '&':
+ s = new_stmt(BPF_ALU|BPF_AND|BPF_K);
+ break;
+ }
+ s->s.k = val;
+ b = new_block(JMP(BPF_JEQ));
+ b->stmts = s;
+ gen_not(b);
+
+ return b;
+}
+
+struct block *
+gen_broadcast(proto)
+ int proto;
+{
+ bpf_u_int32 hostmask;
+ struct block *b0, *b1, *b2;
+ static u_char ebroadcast[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
+
+ switch (proto) {
+
+ case Q_DEFAULT:
+ case Q_LINK:
+ if (linktype == DLT_EN10MB)
+ return gen_ehostop(ebroadcast, Q_DST);
+ if (linktype == DLT_FDDI)
+ return gen_fhostop(ebroadcast, Q_DST);
+ bpf_error("not a broadcast link");
+ break;
+
+ case Q_IP:
+ b0 = gen_linktype(ETHERTYPE_IP);
+ hostmask = ~netmask;
+ b1 = gen_mcmp(off_nl + 16, BPF_W, (bpf_int32)0, hostmask);
+ b2 = gen_mcmp(off_nl + 16, BPF_W,
+ (bpf_int32)(~0 & hostmask), hostmask);
+ gen_or(b1, b2);
+ gen_and(b0, b2);
+ return b2;
+ }
+ bpf_error("only ether/ip broadcast filters supported");
+}
+
+struct block *
+gen_multicast(proto)
+ int proto;
+{
+ register struct block *b0, *b1;
+ register struct slist *s;
+
+ switch (proto) {
+
+ case Q_DEFAULT:
+ case Q_LINK:
+ if (linktype == DLT_EN10MB) {
+ /* ether[0] & 1 != 0 */
+ s = new_stmt(BPF_LD|BPF_B|BPF_ABS);
+ s->s.k = 0;
+ b0 = new_block(JMP(BPF_JSET));
+ b0->s.k = 1;
+ b0->stmts = s;
+ return b0;
+ }
+
+ if (linktype == DLT_FDDI) {
+ /* XXX TEST THIS: MIGHT NOT PORT PROPERLY XXX */
+ /* fddi[1] & 1 != 0 */
+ s = new_stmt(BPF_LD|BPF_B|BPF_ABS);
+ s->s.k = 1;
+ b0 = new_block(JMP(BPF_JSET));
+ b0->s.k = 1;
+ b0->stmts = s;
+ return b0;
+ }
+ /* Link not known to support multicasts */
+ break;
+
+ case Q_IP:
+ b0 = gen_linktype(ETHERTYPE_IP);
+ b1 = gen_cmp(off_nl + 16, BPF_B, (bpf_int32)224);
+ b1->s.code = JMP(BPF_JGE);
+ gen_and(b0, b1);
+ return b1;
+ }
+ bpf_error("only IP multicast filters supported on ethernet/FDDI");
+}
+
+/*
+ * generate command for inbound/outbound. It's here so we can
+ * make it link-type specific. 'dir' = 0 implies "inbound",
+ * = 1 implies "outbound".
+ */
+struct block *
+gen_inbound(dir)
+ int dir;
+{
+ register struct block *b0;
+
+ b0 = gen_relation(BPF_JEQ,
+ gen_load(Q_LINK, gen_loadi(0), 1),
+ gen_loadi(0),
+ dir);
+ return (b0);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/gencode.h b/package/etrax-tools/src/e100boot/libpcap-0.4/gencode.h
new file mode 100644
index 000000000..44dd20fee
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/gencode.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/gencode.h,v 1.1 1999/08/26 10:05:22 johana Exp $ (LBL)
+ */
+
+/*XXX*/
+#include "gnuc.h"
+
+/* Address qualifiers. */
+
+#define Q_HOST 1
+#define Q_NET 2
+#define Q_PORT 3
+#define Q_GATEWAY 4
+#define Q_PROTO 5
+
+/* Protocol qualifiers. */
+
+#define Q_LINK 1
+#define Q_IP 2
+#define Q_ARP 3
+#define Q_RARP 4
+#define Q_TCP 5
+#define Q_UDP 6
+#define Q_ICMP 7
+#define Q_IGMP 8
+#define Q_IGRP 9
+
+
+#define Q_ATALK 10
+#define Q_DECNET 11
+#define Q_LAT 12
+#define Q_SCA 13
+#define Q_MOPRC 14
+#define Q_MOPDL 15
+
+/* Directional qualifiers. */
+
+#define Q_SRC 1
+#define Q_DST 2
+#define Q_OR 3
+#define Q_AND 4
+
+#define Q_DEFAULT 0
+#define Q_UNDEF 255
+
+struct stmt {
+ int code;
+ bpf_int32 k;
+};
+
+struct slist {
+ struct stmt s;
+ struct slist *next;
+};
+
+/*
+ * A bit vector to represent definition sets. We assume TOT_REGISTERS
+ * is smaller than 8*sizeof(atomset).
+ */
+typedef bpf_u_int32 atomset;
+#define ATOMMASK(n) (1 << (n))
+#define ATOMELEM(d, n) (d & ATOMMASK(n))
+
+/*
+ * An unbounded set.
+ */
+typedef bpf_u_int32 *uset;
+
+/*
+ * Total number of atomic entities, including accumulator (A) and index (X).
+ * We treat all these guys similarly during flow analysis.
+ */
+#define N_ATOMS (BPF_MEMWORDS+2)
+
+struct edge {
+ int id;
+ int code;
+ uset edom;
+ struct block *succ;
+ struct block *pred;
+ struct edge *next; /* link list of incoming edges for a node */
+};
+
+struct block {
+ int id;
+ struct slist *stmts; /* side effect stmts */
+ struct stmt s; /* branch stmt */
+ int mark;
+ int longjt; /* jt branch requires long jump */
+ int longjf; /* jf branch requires long jump */
+ int level;
+ int offset;
+ int sense;
+ struct edge et;
+ struct edge ef;
+ struct block *head;
+ struct block *link; /* link field used by optimizer */
+ uset dom;
+ uset closure;
+ struct edge *in_edges;
+ atomset def, kill;
+ atomset in_use;
+ atomset out_use;
+ int oval;
+ int val[N_ATOMS];
+};
+
+struct arth {
+ struct block *b; /* protocol checks */
+ struct slist *s; /* stmt list */
+ int regno; /* virtual register number of result */
+};
+
+struct qual {
+ unsigned char addr;
+ unsigned char proto;
+ unsigned char dir;
+ unsigned char pad;
+};
+
+struct arth *gen_loadi(int);
+struct arth *gen_load(int, struct arth *, int);
+struct arth *gen_loadlen(void);
+struct arth *gen_neg(struct arth *);
+struct arth *gen_arth(int, struct arth *, struct arth *);
+
+void gen_and(struct block *, struct block *);
+void gen_or(struct block *, struct block *);
+void gen_not(struct block *);
+
+struct block *gen_scode(const char *, struct qual);
+struct block *gen_ecode(const u_char *, struct qual);
+struct block *gen_mcode(const char *, const char *, int, struct qual);
+struct block *gen_ncode(const char *, bpf_u_int32, struct qual);
+struct block *gen_proto_abbrev(int);
+struct block *gen_relation(int, struct arth *, struct arth *, int);
+struct block *gen_less(int);
+struct block *gen_greater(int);
+struct block *gen_byteop(int, int, int);
+struct block *gen_broadcast(int);
+struct block *gen_multicast(int);
+struct block *gen_inbound(int);
+
+void bpf_optimize(struct block **);
+#if __STDC__
+__dead void bpf_error(const char *, ...)
+ __attribute__((volatile, format (printf, 1, 2)));
+#endif
+
+void finish_parse(struct block *);
+char *sdup(const char *);
+
+struct bpf_insn *icode_to_fcode(struct block *, int *);
+int pcap_parse(void);
+void lex_init(char *);
+void sappend(struct slist *, struct slist *);
+
+/* XXX */
+#define JT(b) ((b)->et.succ)
+#define JF(b) ((b)->ef.succ)
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/gnuc.h b/package/etrax-tools/src/e100boot/libpcap-0.4/gnuc.h
new file mode 120000
index 000000000..4cdb41afc
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/gnuc.h
@@ -0,0 +1 @@
+lbl/gnuc.h \ No newline at end of file
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/grammar.c b/package/etrax-tools/src/e100boot/libpcap-0.4/grammar.c
new file mode 100644
index 000000000..48b20bdb7
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/grammar.c
@@ -0,0 +1,2380 @@
+/* A Bison parser, made by GNU Bison 2.3. */
+
+/* Skeleton implementation for Bison's Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+/* C LALR(1) parser skeleton written by Richard Stallman, by
+ simplifying the original so-called "semantic" parser. */
+
+/* All symbols defined below should begin with yy or YY, to avoid
+ infringing on user name space. This should be done even for local
+ variables, as they might otherwise be expanded by user macros.
+ There are some unavoidable exceptions within include files to
+ define necessary library symbols; they are noted "INFRINGES ON
+ USER NAME SPACE" below. */
+
+/* Identify Bison output. */
+#define YYBISON 1
+
+/* Bison version. */
+#define YYBISON_VERSION "2.3"
+
+/* Skeleton name. */
+#define YYSKELETON_NAME "yacc.c"
+
+/* Pure parsers. */
+#define YYPURE 0
+
+/* Using locations. */
+#define YYLSP_NEEDED 0
+
+/* Substitute the variable and function names. */
+#define yyparse pcap_parse
+#define yylex pcap_lex
+#define yyerror pcap_error
+#define yylval pcap_lval
+#define yychar pcap_char
+#define yydebug pcap_debug
+#define yynerrs pcap_nerrs
+
+
+/* Tokens. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ /* Put the tokens into the symbol table, so that GDB and other debuggers
+ know about them. */
+ enum yytokentype {
+ DST = 258,
+ SRC = 259,
+ HOST = 260,
+ GATEWAY = 261,
+ NET = 262,
+ MASK = 263,
+ PORT = 264,
+ LESS = 265,
+ GREATER = 266,
+ PROTO = 267,
+ BYTE = 268,
+ ARP = 269,
+ RARP = 270,
+ IP = 271,
+ TCP = 272,
+ UDP = 273,
+ ICMP = 274,
+ IGMP = 275,
+ IGRP = 276,
+ ATALK = 277,
+ DECNET = 278,
+ LAT = 279,
+ SCA = 280,
+ MOPRC = 281,
+ MOPDL = 282,
+ TK_BROADCAST = 283,
+ TK_MULTICAST = 284,
+ NUM = 285,
+ INBOUND = 286,
+ OUTBOUND = 287,
+ LINK = 288,
+ GEQ = 289,
+ LEQ = 290,
+ NEQ = 291,
+ ID = 292,
+ EID = 293,
+ HID = 294,
+ LSH = 295,
+ RSH = 296,
+ LEN = 297,
+ AND = 298,
+ OR = 299,
+ UMINUS = 300
+ };
+#endif
+/* Tokens. */
+#define DST 258
+#define SRC 259
+#define HOST 260
+#define GATEWAY 261
+#define NET 262
+#define MASK 263
+#define PORT 264
+#define LESS 265
+#define GREATER 266
+#define PROTO 267
+#define BYTE 268
+#define ARP 269
+#define RARP 270
+#define IP 271
+#define TCP 272
+#define UDP 273
+#define ICMP 274
+#define IGMP 275
+#define IGRP 276
+#define ATALK 277
+#define DECNET 278
+#define LAT 279
+#define SCA 280
+#define MOPRC 281
+#define MOPDL 282
+#define TK_BROADCAST 283
+#define TK_MULTICAST 284
+#define NUM 285
+#define INBOUND 286
+#define OUTBOUND 287
+#define LINK 288
+#define GEQ 289
+#define LEQ 290
+#define NEQ 291
+#define ID 292
+#define EID 293
+#define HID 294
+#define LSH 295
+#define RSH 296
+#define LEN 297
+#define AND 298
+#define OR 299
+#define UMINUS 300
+
+
+
+
+/* Copy the first part of user declarations. */
+#line 1 "grammar.y"
+
+/*
+ * Copyright (c) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/grammar.y,v 1.1 1999/08/26 10:05:22 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/socket.h>
+
+#if __STDC__
+struct mbuf;
+struct rtentry;
+#endif
+
+#include <net/if.h>
+
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+
+#include <stdio.h>
+
+#include "pcap-int.h"
+
+#include "gencode.h"
+#include <pcap-namedb.h>
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#define QSET(q, p, d, a) (q).proto = (p),\
+ (q).dir = (d),\
+ (q).addr = (a)
+
+int n_errors = 0;
+
+static struct qual qerr = { Q_UNDEF, Q_UNDEF, Q_UNDEF, Q_UNDEF };
+
+static void
+yyerror(char *msg)
+{
+ ++n_errors;
+ bpf_error("%s", msg);
+ /* NOTREACHED */
+}
+
+#ifndef YYBISON
+int yyparse(void);
+
+int
+pcap_parse()
+{
+ return (yyparse());
+}
+#endif
+
+
+
+/* Enabling traces. */
+#ifndef YYDEBUG
+# define YYDEBUG 0
+#endif
+
+/* Enabling verbose error messages. */
+#ifdef YYERROR_VERBOSE
+# undef YYERROR_VERBOSE
+# define YYERROR_VERBOSE 1
+#else
+# define YYERROR_VERBOSE 0
+#endif
+
+/* Enabling the token table. */
+#ifndef YYTOKEN_TABLE
+# define YYTOKEN_TABLE 0
+#endif
+
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE
+#line 82 "grammar.y"
+{
+ int i;
+ bpf_u_int32 h;
+ u_char *e;
+ char *s;
+ struct stmt *stmt;
+ struct arth *a;
+ struct {
+ struct qual q;
+ struct block *b;
+ } blk;
+ struct block *rblk;
+}
+/* Line 187 of yacc.c. */
+#line 289 "y.tab.c"
+ YYSTYPE;
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+
+
+/* Copy the second part of user declarations. */
+
+
+/* Line 216 of yacc.c. */
+#line 302 "y.tab.c"
+
+#ifdef short
+# undef short
+#endif
+
+#ifdef YYTYPE_UINT8
+typedef YYTYPE_UINT8 yytype_uint8;
+#else
+typedef unsigned char yytype_uint8;
+#endif
+
+#ifdef YYTYPE_INT8
+typedef YYTYPE_INT8 yytype_int8;
+#elif (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+typedef signed char yytype_int8;
+#else
+typedef short int yytype_int8;
+#endif
+
+#ifdef YYTYPE_UINT16
+typedef YYTYPE_UINT16 yytype_uint16;
+#else
+typedef unsigned short int yytype_uint16;
+#endif
+
+#ifdef YYTYPE_INT16
+typedef YYTYPE_INT16 yytype_int16;
+#else
+typedef short int yytype_int16;
+#endif
+
+#ifndef YYSIZE_T
+# ifdef __SIZE_TYPE__
+# define YYSIZE_T __SIZE_TYPE__
+# elif defined size_t
+# define YYSIZE_T size_t
+# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+# include <stddef.h> /* INFRINGES ON USER NAME SPACE */
+# define YYSIZE_T size_t
+# else
+# define YYSIZE_T unsigned int
+# endif
+#endif
+
+#define YYSIZE_MAXIMUM ((YYSIZE_T) -1)
+
+#ifndef YY_
+# if YYENABLE_NLS
+# if ENABLE_NLS
+# include <libintl.h> /* INFRINGES ON USER NAME SPACE */
+# define YY_(msgid) dgettext ("bison-runtime", msgid)
+# endif
+# endif
+# ifndef YY_
+# define YY_(msgid) msgid
+# endif
+#endif
+
+/* Suppress unused-variable warnings by "using" E. */
+#if ! defined lint || defined __GNUC__
+# define YYUSE(e) ((void) (e))
+#else
+# define YYUSE(e) /* empty */
+#endif
+
+/* Identity function, used to suppress warnings about constant conditions. */
+#ifndef lint
+# define YYID(n) (n)
+#else
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+static int
+YYID (int i)
+#else
+static int
+YYID (i)
+ int i;
+#endif
+{
+ return i;
+}
+#endif
+
+#if ! defined yyoverflow || YYERROR_VERBOSE
+
+/* The parser invokes alloca or malloc; define the necessary symbols. */
+
+# ifdef YYSTACK_USE_ALLOCA
+# if YYSTACK_USE_ALLOCA
+# ifdef __GNUC__
+# define YYSTACK_ALLOC __builtin_alloca
+# elif defined __BUILTIN_VA_ARG_INCR
+# include <alloca.h> /* INFRINGES ON USER NAME SPACE */
+# elif defined _AIX
+# define YYSTACK_ALLOC __alloca
+# elif defined _MSC_VER
+# include <malloc.h> /* INFRINGES ON USER NAME SPACE */
+# define alloca _alloca
+# else
+# define YYSTACK_ALLOC alloca
+# if ! defined _ALLOCA_H && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+# ifndef _STDLIB_H
+# define _STDLIB_H 1
+# endif
+# endif
+# endif
+# endif
+# endif
+
+# ifdef YYSTACK_ALLOC
+ /* Pacify GCC's `empty if-body' warning. */
+# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0))
+# ifndef YYSTACK_ALLOC_MAXIMUM
+ /* The OS might guarantee only one guard page at the bottom of the stack,
+ and a page size can be as small as 4096 bytes. So we cannot safely
+ invoke alloca (N) if N exceeds 4096. Use a slightly smaller number
+ to allow for a few compiler-allocated temporary stack slots. */
+# define YYSTACK_ALLOC_MAXIMUM 4032 /* reasonable circa 2006 */
+# endif
+# else
+# define YYSTACK_ALLOC YYMALLOC
+# define YYSTACK_FREE YYFREE
+# ifndef YYSTACK_ALLOC_MAXIMUM
+# define YYSTACK_ALLOC_MAXIMUM YYSIZE_MAXIMUM
+# endif
+# if (defined __cplusplus && ! defined _STDLIB_H \
+ && ! ((defined YYMALLOC || defined malloc) \
+ && (defined YYFREE || defined free)))
+# include <stdlib.h> /* INFRINGES ON USER NAME SPACE */
+# ifndef _STDLIB_H
+# define _STDLIB_H 1
+# endif
+# endif
+# ifndef YYMALLOC
+# define YYMALLOC malloc
+# if ! defined malloc && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# ifndef YYFREE
+# define YYFREE free
+# if ! defined free && ! defined _STDLIB_H && (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+void free (void *); /* INFRINGES ON USER NAME SPACE */
+# endif
+# endif
+# endif
+#endif /* ! defined yyoverflow || YYERROR_VERBOSE */
+
+
+#if (! defined yyoverflow \
+ && (! defined __cplusplus \
+ || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL)))
+
+/* A type that is properly aligned for any stack member. */
+union yyalloc
+{
+ yytype_int16 yyss;
+ YYSTYPE yyvs;
+ };
+
+/* The size of the maximum gap between one aligned stack and the next. */
+# define YYSTACK_GAP_MAXIMUM (sizeof (union yyalloc) - 1)
+
+/* The size of an array large to enough to hold all stacks, each with
+ N elements. */
+# define YYSTACK_BYTES(N) \
+ ((N) * (sizeof (yytype_int16) + sizeof (YYSTYPE)) \
+ + YYSTACK_GAP_MAXIMUM)
+
+/* Copy COUNT objects from FROM to TO. The source and destination do
+ not overlap. */
+# ifndef YYCOPY
+# if defined __GNUC__ && 1 < __GNUC__
+# define YYCOPY(To, From, Count) \
+ __builtin_memcpy (To, From, (Count) * sizeof (*(From)))
+# else
+# define YYCOPY(To, From, Count) \
+ do \
+ { \
+ YYSIZE_T yyi; \
+ for (yyi = 0; yyi < (Count); yyi++) \
+ (To)[yyi] = (From)[yyi]; \
+ } \
+ while (YYID (0))
+# endif
+# endif
+
+/* Relocate STACK from its old location to the new one. The
+ local variables YYSIZE and YYSTACKSIZE give the old and new number of
+ elements in the stack, and YYPTR gives the new location of the
+ stack. Advance YYPTR to a properly aligned location for the next
+ stack. */
+# define YYSTACK_RELOCATE(Stack) \
+ do \
+ { \
+ YYSIZE_T yynewbytes; \
+ YYCOPY (&yyptr->Stack, Stack, yysize); \
+ Stack = &yyptr->Stack; \
+ yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \
+ yyptr += yynewbytes / sizeof (*yyptr); \
+ } \
+ while (YYID (0))
+
+#endif
+
+/* YYFINAL -- State number of the termination state. */
+#define YYFINAL 3
+/* YYLAST -- Last index in YYTABLE. */
+#define YYLAST 345
+
+/* YYNTOKENS -- Number of terminals. */
+#define YYNTOKENS 61
+/* YYNNTS -- Number of nonterminals. */
+#define YYNNTS 27
+/* YYNRULES -- Number of rules. */
+#define YYNRULES 102
+/* YYNRULES -- Number of states. */
+#define YYNSTATES 151
+
+/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */
+#define YYUNDEFTOK 2
+#define YYMAXUTOK 300
+
+#define YYTRANSLATE(YYX) \
+ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK)
+
+/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */
+static const yytype_uint8 yytranslate[] =
+{
+ 0, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 45, 2, 2, 2, 2, 47, 2,
+ 54, 53, 50, 48, 2, 49, 2, 51, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 60, 2,
+ 57, 56, 55, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 58, 2, 59, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 46, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, 2, 2, 2, 2, 2, 1, 2, 3, 4,
+ 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
+ 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
+ 25, 26, 27, 28, 29, 30, 31, 32, 33, 34,
+ 35, 36, 37, 38, 39, 40, 41, 42, 43, 44,
+ 52
+};
+
+#if YYDEBUG
+/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in
+ YYRHS. */
+static const yytype_uint16 yyprhs[] =
+{
+ 0, 0, 3, 6, 8, 9, 11, 15, 19, 23,
+ 27, 29, 31, 33, 35, 39, 41, 45, 49, 51,
+ 53, 56, 58, 60, 62, 66, 70, 72, 74, 76,
+ 79, 83, 86, 89, 92, 95, 98, 102, 104, 108,
+ 112, 114, 116, 117, 119, 121, 125, 129, 133, 137,
+ 139, 141, 143, 145, 147, 149, 151, 153, 155, 157,
+ 159, 161, 163, 165, 167, 169, 171, 173, 175, 178,
+ 181, 184, 187, 192, 194, 196, 198, 200, 202, 204,
+ 206, 208, 210, 212, 217, 224, 228, 232, 236, 240,
+ 244, 248, 252, 256, 259, 263, 265, 267, 269, 271,
+ 273, 275, 277
+};
+
+/* YYRHS -- A `-1'-separated list of the rules' RHS. */
+static const yytype_int8 yyrhs[] =
+{
+ 62, 0, -1, 63, 64, -1, 63, -1, -1, 73,
+ -1, 64, 65, 73, -1, 64, 65, 67, -1, 64,
+ 66, 73, -1, 64, 66, 67, -1, 43, -1, 44,
+ -1, 68, -1, 87, -1, 70, 71, 53, -1, 37,
+ -1, 39, 51, 30, -1, 39, 8, 39, -1, 39,
+ -1, 38, -1, 69, 67, -1, 45, -1, 54, -1,
+ 68, -1, 72, 65, 67, -1, 72, 66, 67, -1,
+ 87, -1, 71, -1, 75, -1, 69, 73, -1, 76,
+ 77, 78, -1, 76, 77, -1, 76, 78, -1, 76,
+ 12, -1, 76, 79, -1, 74, 67, -1, 70, 64,
+ 53, -1, 80, -1, 84, 82, 84, -1, 84, 83,
+ 84, -1, 81, -1, 80, -1, -1, 4, -1, 3,
+ -1, 4, 44, 3, -1, 3, 44, 4, -1, 4,
+ 43, 3, -1, 3, 43, 4, -1, 5, -1, 7,
+ -1, 9, -1, 6, -1, 33, -1, 16, -1, 14,
+ -1, 15, -1, 17, -1, 18, -1, 19, -1, 20,
+ -1, 21, -1, 22, -1, 23, -1, 24, -1, 25,
+ -1, 27, -1, 26, -1, 76, 28, -1, 76, 29,
+ -1, 10, 30, -1, 11, 30, -1, 13, 30, 86,
+ 30, -1, 31, -1, 32, -1, 55, -1, 34, -1,
+ 56, -1, 35, -1, 57, -1, 36, -1, 87, -1,
+ 85, -1, 80, 58, 84, 59, -1, 80, 58, 84,
+ 60, 30, 59, -1, 84, 48, 84, -1, 84, 49,
+ 84, -1, 84, 50, 84, -1, 84, 51, 84, -1,
+ 84, 47, 84, -1, 84, 46, 84, -1, 84, 40,
+ 84, -1, 84, 41, 84, -1, 49, 84, -1, 70,
+ 85, 53, -1, 42, -1, 47, -1, 46, -1, 57,
+ -1, 55, -1, 56, -1, 30, -1, 70, 87, 53,
+ -1
+};
+
+/* YYRLINE[YYN] -- source line where rule number YYN was defined. */
+static const yytype_uint16 yyrline[] =
+{
+ 0, 130, 130, 134, 136, 138, 139, 140, 141, 142,
+ 144, 146, 148, 149, 151, 153, 154, 156, 158, 170,
+ 171, 173, 175, 177, 178, 179, 181, 183, 185, 186,
+ 188, 189, 190, 191, 192, 194, 195, 196, 197, 199,
+ 201, 204, 205, 208, 209, 210, 211, 212, 213, 216,
+ 217, 218, 221, 223, 224, 225, 226, 227, 228, 229,
+ 230, 231, 232, 233, 234, 235, 236, 237, 239, 240,
+ 241, 242, 243, 244, 245, 247, 248, 249, 251, 252,
+ 253, 255, 256, 258, 259, 260, 261, 262, 263, 264,
+ 265, 266, 267, 268, 269, 270, 272, 273, 274, 275,
+ 276, 278, 279
+};
+#endif
+
+#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE
+/* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM.
+ First, the terminals, then, starting at YYNTOKENS, nonterminals. */
+static const char *const yytname[] =
+{
+ "$end", "error", "$undefined", "DST", "SRC", "HOST", "GATEWAY", "NET",
+ "MASK", "PORT", "LESS", "GREATER", "PROTO", "BYTE", "ARP", "RARP", "IP",
+ "TCP", "UDP", "ICMP", "IGMP", "IGRP", "ATALK", "DECNET", "LAT", "SCA",
+ "MOPRC", "MOPDL", "TK_BROADCAST", "TK_MULTICAST", "NUM", "INBOUND",
+ "OUTBOUND", "LINK", "GEQ", "LEQ", "NEQ", "ID", "EID", "HID", "LSH",
+ "RSH", "LEN", "AND", "OR", "'!'", "'|'", "'&'", "'+'", "'-'", "'*'",
+ "'/'", "UMINUS", "')'", "'('", "'>'", "'='", "'<'", "'['", "']'", "':'",
+ "$accept", "prog", "null", "expr", "and", "or", "id", "nid", "not",
+ "paren", "pid", "qid", "term", "head", "rterm", "pqual", "dqual",
+ "aqual", "ndaqual", "pname", "other", "relop", "irelop", "arth", "narth",
+ "byteop", "pnum", 0
+};
+#endif
+
+# ifdef YYPRINT
+/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to
+ token YYLEX-NUM. */
+static const yytype_uint16 yytoknum[] =
+{
+ 0, 256, 257, 258, 259, 260, 261, 262, 263, 264,
+ 265, 266, 267, 268, 269, 270, 271, 272, 273, 274,
+ 275, 276, 277, 278, 279, 280, 281, 282, 283, 284,
+ 285, 286, 287, 288, 289, 290, 291, 292, 293, 294,
+ 295, 296, 297, 298, 299, 33, 124, 38, 43, 45,
+ 42, 47, 300, 41, 40, 62, 61, 60, 91, 93,
+ 58
+};
+# endif
+
+/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */
+static const yytype_uint8 yyr1[] =
+{
+ 0, 61, 62, 62, 63, 64, 64, 64, 64, 64,
+ 65, 66, 67, 67, 67, 68, 68, 68, 68, 68,
+ 68, 69, 70, 71, 71, 71, 72, 72, 73, 73,
+ 74, 74, 74, 74, 74, 75, 75, 75, 75, 75,
+ 75, 76, 76, 77, 77, 77, 77, 77, 77, 78,
+ 78, 78, 79, 80, 80, 80, 80, 80, 80, 80,
+ 80, 80, 80, 80, 80, 80, 80, 80, 81, 81,
+ 81, 81, 81, 81, 81, 82, 82, 82, 83, 83,
+ 83, 84, 84, 85, 85, 85, 85, 85, 85, 85,
+ 85, 85, 85, 85, 85, 85, 86, 86, 86, 86,
+ 86, 87, 87
+};
+
+/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */
+static const yytype_uint8 yyr2[] =
+{
+ 0, 2, 2, 1, 0, 1, 3, 3, 3, 3,
+ 1, 1, 1, 1, 3, 1, 3, 3, 1, 1,
+ 2, 1, 1, 1, 3, 3, 1, 1, 1, 2,
+ 3, 2, 2, 2, 2, 2, 3, 1, 3, 3,
+ 1, 1, 0, 1, 1, 3, 3, 3, 3, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
+ 2, 2, 4, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 4, 6, 3, 3, 3, 3, 3,
+ 3, 3, 3, 2, 3, 1, 1, 1, 1, 1,
+ 1, 1, 3
+};
+
+/* YYDEFACT[STATE-NAME] -- Default rule to reduce with in state
+ STATE-NUM when YYTABLE doesn't specify something else to do. Zero
+ means the default is an error. */
+static const yytype_uint8 yydefact[] =
+{
+ 4, 0, 42, 1, 0, 0, 0, 55, 56, 54,
+ 57, 58, 59, 60, 61, 62, 63, 64, 65, 67,
+ 66, 101, 73, 74, 53, 95, 21, 0, 22, 2,
+ 42, 42, 5, 0, 28, 0, 41, 40, 0, 82,
+ 81, 70, 71, 0, 0, 0, 93, 10, 11, 42,
+ 42, 29, 0, 82, 81, 15, 19, 18, 35, 12,
+ 0, 0, 13, 44, 43, 49, 52, 50, 51, 33,
+ 68, 69, 31, 32, 34, 0, 76, 78, 80, 0,
+ 0, 0, 0, 0, 0, 0, 0, 75, 77, 79,
+ 0, 0, 97, 96, 99, 100, 98, 0, 0, 7,
+ 42, 42, 6, 81, 9, 8, 36, 94, 102, 0,
+ 0, 20, 23, 0, 27, 0, 26, 0, 0, 0,
+ 0, 30, 0, 91, 92, 90, 89, 85, 86, 87,
+ 88, 38, 39, 72, 81, 17, 16, 0, 14, 0,
+ 0, 48, 46, 47, 45, 83, 0, 24, 25, 0,
+ 84
+};
+
+/* YYDEFGOTO[NTERM-NUM]. */
+static const yytype_int8 yydefgoto[] =
+{
+ -1, 1, 2, 52, 49, 50, 111, 59, 60, 44,
+ 114, 115, 32, 33, 34, 35, 72, 73, 74, 45,
+ 37, 90, 91, 38, 39, 97, 40
+};
+
+/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing
+ STATE-NUM. */
+#define YYPACT_NINF -53
+static const yytype_int16 yypact[] =
+{
+ -53, 10, 129, -53, -25, -18, 0, -53, -53, -53,
+ -53, -53, -53, -53, -53, -53, -53, -53, -53, -53,
+ -53, -53, -53, -53, -53, -53, -53, 254, -53, -1,
+ 213, 213, -53, 50, -53, 285, 8, -53, 270, -53,
+ -53, -53, -53, 288, 254, -33, -53, -53, -53, 171,
+ 171, -53, -3, -26, -21, -53, -53, -5, -53, -53,
+ 50, 50, -53, 13, 53, -53, -53, -53, -53, -53,
+ -53, -53, 210, -53, -53, 254, -53, -53, -53, 254,
+ 254, 254, 254, 254, 254, 254, 254, -53, -53, -53,
+ 254, 254, -53, -53, -53, -53, -53, 9, 201, -53,
+ 171, 171, -53, 26, -53, -53, -53, -53, -53, 21,
+ 23, -53, -53, -17, -15, -1, -21, 58, 61, 64,
+ 69, -53, 117, 27, 27, 43, 282, -36, -36, -53,
+ -53, 201, 201, -53, 57, -53, -53, -21, -53, 50,
+ 50, -53, -53, -53, -53, -53, 52, -53, -53, 44,
+ -53
+};
+
+/* YYPGOTO[NTERM-NUM]. */
+static const yytype_int8 yypgoto[] =
+{
+ -53, -53, -53, 100, -8, 2, -31, -52, 5, -2,
+ -53, -53, -29, -53, -53, -53, -53, 46, -53, 14,
+ -53, -53, -53, 41, -20, -53, -27
+};
+
+/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If
+ positive, shift that token. If negative, reduce the rule which
+ number is the opposite. If zero, do what YYDEFACT says.
+ If YYTABLE_NINF, syntax error. */
+#define YYTABLE_NINF -38
+static const yytype_int16 yytable[] =
+{
+ 31, 51, 58, 109, 54, 41, 62, 30, -37, 112,
+ 3, 53, 42, 21, 85, 86, 36, 54, 99, 104,
+ 102, 105, 103, 103, 53, 75, -13, 107, 31, 31,
+ 43, 61, 108, 62, 116, 30, 30, 28, 138, 133,
+ 47, 48, 47, 48, 36, 36, 110, 101, 101, 112,
+ 106, -37, -37, 136, 100, 100, 117, 118, 61, 113,
+ 135, -37, 141, 36, 36, 142, 75, 143, 46, -13,
+ -13, 51, 144, 103, 134, 83, 84, 85, 86, -13,
+ 21, 53, 149, 79, 80, 98, 137, 55, 56, 57,
+ 82, 83, 84, 85, 86, 26, 119, 120, 101, 31,
+ -26, -26, 29, 150, 28, 100, 100, 139, 147, 148,
+ 108, 113, 62, 62, 36, 36, 122, 140, 121, 0,
+ 123, 124, 125, 126, 127, 128, 129, 130, 0, -3,
+ 0, 131, 132, 0, 0, 0, 0, 61, 61, 4,
+ 5, 0, 6, 7, 8, 9, 10, 11, 12, 13,
+ 14, 15, 16, 17, 18, 19, 20, 79, 80, 21,
+ 22, 23, 24, 81, 82, 83, 84, 85, 86, 0,
+ 0, 25, 0, 0, 26, 0, 145, 146, 27, 0,
+ 0, 4, 5, 28, 6, 7, 8, 9, 10, 11,
+ 12, 13, 14, 15, 16, 17, 18, 19, 20, 0,
+ 0, 21, 22, 23, 24, 0, 0, 0, 55, 56,
+ 57, 0, 0, 25, 0, 65, 26, 67, 0, 68,
+ 27, 0, 0, 4, 5, 28, 6, 7, 8, 9,
+ 10, 11, 12, 13, 14, 15, 16, 17, 18, 19,
+ 20, 79, 80, 21, 22, 23, 24, 81, 82, 83,
+ 84, 85, 86, 0, 0, 25, 0, 0, 26, 0,
+ 0, 0, 27, 0, 0, 0, 0, 28, 7, 8,
+ 9, 10, 11, 12, 13, 14, 15, 16, 17, 18,
+ 19, 20, 0, 0, 21, 0, 0, 24, 63, 64,
+ 65, 66, 67, 0, 68, 0, 25, 69, 0, 0,
+ 0, 0, 0, 27, 76, 77, 78, 0, 28, 0,
+ 79, 80, 0, 70, 71, 0, 81, 82, 83, 84,
+ 85, 86, 79, 80, 0, 87, 88, 89, 0, 0,
+ 83, 84, 85, 86, 92, 93, 0, 0, 0, 0,
+ 0, 0, 0, 94, 95, 96
+};
+
+static const yytype_int16 yycheck[] =
+{
+ 2, 30, 33, 8, 31, 30, 33, 2, 0, 61,
+ 0, 31, 30, 30, 50, 51, 2, 44, 49, 50,
+ 49, 50, 49, 50, 44, 58, 0, 53, 30, 31,
+ 30, 33, 53, 60, 61, 30, 31, 54, 53, 30,
+ 43, 44, 43, 44, 30, 31, 51, 49, 50, 101,
+ 53, 43, 44, 30, 49, 50, 43, 44, 60, 61,
+ 39, 53, 4, 49, 50, 4, 58, 3, 27, 43,
+ 44, 100, 3, 100, 101, 48, 49, 50, 51, 53,
+ 30, 101, 30, 40, 41, 44, 113, 37, 38, 39,
+ 47, 48, 49, 50, 51, 45, 43, 44, 100, 101,
+ 43, 44, 2, 59, 54, 100, 101, 115, 139, 140,
+ 53, 113, 139, 140, 100, 101, 75, 115, 72, -1,
+ 79, 80, 81, 82, 83, 84, 85, 86, -1, 0,
+ -1, 90, 91, -1, -1, -1, -1, 139, 140, 10,
+ 11, -1, 13, 14, 15, 16, 17, 18, 19, 20,
+ 21, 22, 23, 24, 25, 26, 27, 40, 41, 30,
+ 31, 32, 33, 46, 47, 48, 49, 50, 51, -1,
+ -1, 42, -1, -1, 45, -1, 59, 60, 49, -1,
+ -1, 10, 11, 54, 13, 14, 15, 16, 17, 18,
+ 19, 20, 21, 22, 23, 24, 25, 26, 27, -1,
+ -1, 30, 31, 32, 33, -1, -1, -1, 37, 38,
+ 39, -1, -1, 42, -1, 5, 45, 7, -1, 9,
+ 49, -1, -1, 10, 11, 54, 13, 14, 15, 16,
+ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
+ 27, 40, 41, 30, 31, 32, 33, 46, 47, 48,
+ 49, 50, 51, -1, -1, 42, -1, -1, 45, -1,
+ -1, -1, 49, -1, -1, -1, -1, 54, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+ 26, 27, -1, -1, 30, -1, -1, 33, 3, 4,
+ 5, 6, 7, -1, 9, -1, 42, 12, -1, -1,
+ -1, -1, -1, 49, 34, 35, 36, -1, 54, -1,
+ 40, 41, -1, 28, 29, -1, 46, 47, 48, 49,
+ 50, 51, 40, 41, -1, 55, 56, 57, -1, -1,
+ 48, 49, 50, 51, 46, 47, -1, -1, -1, -1,
+ -1, -1, -1, 55, 56, 57
+};
+
+/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing
+ symbol of state STATE-NUM. */
+static const yytype_uint8 yystos[] =
+{
+ 0, 62, 63, 0, 10, 11, 13, 14, 15, 16,
+ 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
+ 27, 30, 31, 32, 33, 42, 45, 49, 54, 64,
+ 69, 70, 73, 74, 75, 76, 80, 81, 84, 85,
+ 87, 30, 30, 30, 70, 80, 84, 43, 44, 65,
+ 66, 73, 64, 85, 87, 37, 38, 39, 67, 68,
+ 69, 70, 87, 3, 4, 5, 6, 7, 9, 12,
+ 28, 29, 77, 78, 79, 58, 34, 35, 36, 40,
+ 41, 46, 47, 48, 49, 50, 51, 55, 56, 57,
+ 82, 83, 46, 47, 55, 56, 57, 86, 84, 67,
+ 69, 70, 73, 87, 67, 73, 53, 53, 53, 8,
+ 51, 67, 68, 70, 71, 72, 87, 43, 44, 43,
+ 44, 78, 84, 84, 84, 84, 84, 84, 84, 84,
+ 84, 84, 84, 30, 87, 39, 30, 87, 53, 65,
+ 66, 4, 4, 3, 3, 59, 60, 67, 67, 30,
+ 59
+};
+
+#define yyerrok (yyerrstatus = 0)
+#define yyclearin (yychar = YYEMPTY)
+#define YYEMPTY (-2)
+#define YYEOF 0
+
+#define YYACCEPT goto yyacceptlab
+#define YYABORT goto yyabortlab
+#define YYERROR goto yyerrorlab
+
+
+/* Like YYERROR except do call yyerror. This remains here temporarily
+ to ease the transition to the new meaning of YYERROR, for GCC.
+ Once GCC version 2 has supplanted version 1, this can go. */
+
+#define YYFAIL goto yyerrlab
+
+#define YYRECOVERING() (!!yyerrstatus)
+
+#define YYBACKUP(Token, Value) \
+do \
+ if (yychar == YYEMPTY && yylen == 1) \
+ { \
+ yychar = (Token); \
+ yylval = (Value); \
+ yytoken = YYTRANSLATE (yychar); \
+ YYPOPSTACK (1); \
+ goto yybackup; \
+ } \
+ else \
+ { \
+ yyerror (YY_("syntax error: cannot back up")); \
+ YYERROR; \
+ } \
+while (YYID (0))
+
+
+#define YYTERROR 1
+#define YYERRCODE 256
+
+
+/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N].
+ If N is 0, then set CURRENT to the empty location which ends
+ the previous symbol: RHS[0] (always defined). */
+
+#define YYRHSLOC(Rhs, K) ((Rhs)[K])
+#ifndef YYLLOC_DEFAULT
+# define YYLLOC_DEFAULT(Current, Rhs, N) \
+ do \
+ if (YYID (N)) \
+ { \
+ (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \
+ (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \
+ (Current).last_line = YYRHSLOC (Rhs, N).last_line; \
+ (Current).last_column = YYRHSLOC (Rhs, N).last_column; \
+ } \
+ else \
+ { \
+ (Current).first_line = (Current).last_line = \
+ YYRHSLOC (Rhs, 0).last_line; \
+ (Current).first_column = (Current).last_column = \
+ YYRHSLOC (Rhs, 0).last_column; \
+ } \
+ while (YYID (0))
+#endif
+
+
+/* YY_LOCATION_PRINT -- Print the location on the stream.
+ This macro was not mandated originally: define only if we know
+ we won't break user code: when these are the locations we know. */
+
+#ifndef YY_LOCATION_PRINT
+# if YYLTYPE_IS_TRIVIAL
+# define YY_LOCATION_PRINT(File, Loc) \
+ fprintf (File, "%d.%d-%d.%d", \
+ (Loc).first_line, (Loc).first_column, \
+ (Loc).last_line, (Loc).last_column)
+# else
+# define YY_LOCATION_PRINT(File, Loc) ((void) 0)
+# endif
+#endif
+
+
+/* YYLEX -- calling `yylex' with the right arguments. */
+
+#ifdef YYLEX_PARAM
+# define YYLEX yylex (YYLEX_PARAM)
+#else
+# define YYLEX yylex ()
+#endif
+
+/* Enable debugging if requested. */
+#if YYDEBUG
+
+# ifndef YYFPRINTF
+# include <stdio.h> /* INFRINGES ON USER NAME SPACE */
+# define YYFPRINTF fprintf
+# endif
+
+# define YYDPRINTF(Args) \
+do { \
+ if (yydebug) \
+ YYFPRINTF Args; \
+} while (YYID (0))
+
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \
+do { \
+ if (yydebug) \
+ { \
+ YYFPRINTF (stderr, "%s ", Title); \
+ yy_symbol_print (stderr, \
+ Type, Value); \
+ YYFPRINTF (stderr, "\n"); \
+ } \
+} while (YYID (0))
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT. |
+`--------------------------------*/
+
+/*ARGSUSED*/
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+static void
+yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+#else
+static void
+yy_symbol_value_print (yyoutput, yytype, yyvaluep)
+ FILE *yyoutput;
+ int yytype;
+ YYSTYPE const * const yyvaluep;
+#endif
+{
+ if (!yyvaluep)
+ return;
+# ifdef YYPRINT
+ if (yytype < YYNTOKENS)
+ YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep);
+# else
+ YYUSE (yyoutput);
+# endif
+ switch (yytype)
+ {
+ default:
+ break;
+ }
+}
+
+
+/*--------------------------------.
+| Print this symbol on YYOUTPUT. |
+`--------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+static void
+yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep)
+#else
+static void
+yy_symbol_print (yyoutput, yytype, yyvaluep)
+ FILE *yyoutput;
+ int yytype;
+ YYSTYPE const * const yyvaluep;
+#endif
+{
+ if (yytype < YYNTOKENS)
+ YYFPRINTF (yyoutput, "token %s (", yytname[yytype]);
+ else
+ YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]);
+
+ yy_symbol_value_print (yyoutput, yytype, yyvaluep);
+ YYFPRINTF (yyoutput, ")");
+}
+
+/*------------------------------------------------------------------.
+| yy_stack_print -- Print the state stack from its BOTTOM up to its |
+| TOP (included). |
+`------------------------------------------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+static void
+yy_stack_print (yytype_int16 *bottom, yytype_int16 *top)
+#else
+static void
+yy_stack_print (bottom, top)
+ yytype_int16 *bottom;
+ yytype_int16 *top;
+#endif
+{
+ YYFPRINTF (stderr, "Stack now");
+ for (; bottom <= top; ++bottom)
+ YYFPRINTF (stderr, " %d", *bottom);
+ YYFPRINTF (stderr, "\n");
+}
+
+# define YY_STACK_PRINT(Bottom, Top) \
+do { \
+ if (yydebug) \
+ yy_stack_print ((Bottom), (Top)); \
+} while (YYID (0))
+
+
+/*------------------------------------------------.
+| Report that the YYRULE is going to be reduced. |
+`------------------------------------------------*/
+
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+static void
+yy_reduce_print (YYSTYPE *yyvsp, int yyrule)
+#else
+static void
+yy_reduce_print (yyvsp, yyrule)
+ YYSTYPE *yyvsp;
+ int yyrule;
+#endif
+{
+ int yynrhs = yyr2[yyrule];
+ int yyi;
+ unsigned long int yylno = yyrline[yyrule];
+ YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n",
+ yyrule - 1, yylno);
+ /* The symbols being reduced. */
+ for (yyi = 0; yyi < yynrhs; yyi++)
+ {
+ fprintf (stderr, " $%d = ", yyi + 1);
+ yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi],
+ &(yyvsp[(yyi + 1) - (yynrhs)])
+ );
+ fprintf (stderr, "\n");
+ }
+}
+
+# define YY_REDUCE_PRINT(Rule) \
+do { \
+ if (yydebug) \
+ yy_reduce_print (yyvsp, Rule); \
+} while (YYID (0))
+
+/* Nonzero means print parse trace. It is left uninitialized so that
+ multiple parsers can coexist. */
+int yydebug;
+#else /* !YYDEBUG */
+# define YYDPRINTF(Args)
+# define YY_SYMBOL_PRINT(Title, Type, Value, Location)
+# define YY_STACK_PRINT(Bottom, Top)
+# define YY_REDUCE_PRINT(Rule)
+#endif /* !YYDEBUG */
+
+
+/* YYINITDEPTH -- initial size of the parser's stacks. */
+#ifndef YYINITDEPTH
+# define YYINITDEPTH 200
+#endif
+
+/* YYMAXDEPTH -- maximum size the stacks can grow to (effective only
+ if the built-in stack extension method is used).
+
+ Do not make this value too large; the results are undefined if
+ YYSTACK_ALLOC_MAXIMUM < YYSTACK_BYTES (YYMAXDEPTH)
+ evaluated with infinite-precision integer arithmetic. */
+
+#ifndef YYMAXDEPTH
+# define YYMAXDEPTH 10000
+#endif
+
+
+
+#if YYERROR_VERBOSE
+
+# ifndef yystrlen
+# if defined __GLIBC__ && defined _STRING_H
+# define yystrlen strlen
+# else
+/* Return the length of YYSTR. */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+static YYSIZE_T
+yystrlen (const char *yystr)
+#else
+static YYSIZE_T
+yystrlen (yystr)
+ const char *yystr;
+#endif
+{
+ YYSIZE_T yylen;
+ for (yylen = 0; yystr[yylen]; yylen++)
+ continue;
+ return yylen;
+}
+# endif
+# endif
+
+# ifndef yystpcpy
+# if defined __GLIBC__ && defined _STRING_H && defined _GNU_SOURCE
+# define yystpcpy stpcpy
+# else
+/* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in
+ YYDEST. */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+static char *
+yystpcpy (char *yydest, const char *yysrc)
+#else
+static char *
+yystpcpy (yydest, yysrc)
+ char *yydest;
+ const char *yysrc;
+#endif
+{
+ char *yyd = yydest;
+ const char *yys = yysrc;
+
+ while ((*yyd++ = *yys++) != '\0')
+ continue;
+
+ return yyd - 1;
+}
+# endif
+# endif
+
+# ifndef yytnamerr
+/* Copy to YYRES the contents of YYSTR after stripping away unnecessary
+ quotes and backslashes, so that it's suitable for yyerror. The
+ heuristic is that double-quoting is unnecessary unless the string
+ contains an apostrophe, a comma, or backslash (other than
+ backslash-backslash). YYSTR is taken from yytname. If YYRES is
+ null, do not copy; instead, return the length of what the result
+ would have been. */
+static YYSIZE_T
+yytnamerr (char *yyres, const char *yystr)
+{
+ if (*yystr == '"')
+ {
+ YYSIZE_T yyn = 0;
+ char const *yyp = yystr;
+
+ for (;;)
+ switch (*++yyp)
+ {
+ case '\'':
+ case ',':
+ goto do_not_strip_quotes;
+
+ case '\\':
+ if (*++yyp != '\\')
+ goto do_not_strip_quotes;
+ /* Fall through. */
+ default:
+ if (yyres)
+ yyres[yyn] = *yyp;
+ yyn++;
+ break;
+
+ case '"':
+ if (yyres)
+ yyres[yyn] = '\0';
+ return yyn;
+ }
+ do_not_strip_quotes: ;
+ }
+
+ if (! yyres)
+ return yystrlen (yystr);
+
+ return yystpcpy (yyres, yystr) - yyres;
+}
+# endif
+
+/* Copy into YYRESULT an error message about the unexpected token
+ YYCHAR while in state YYSTATE. Return the number of bytes copied,
+ including the terminating null byte. If YYRESULT is null, do not
+ copy anything; just return the number of bytes that would be
+ copied. As a special case, return 0 if an ordinary "syntax error"
+ message will do. Return YYSIZE_MAXIMUM if overflow occurs during
+ size calculation. */
+static YYSIZE_T
+yysyntax_error (char *yyresult, int yystate, int yychar)
+{
+ int yyn = yypact[yystate];
+
+ if (! (YYPACT_NINF < yyn && yyn <= YYLAST))
+ return 0;
+ else
+ {
+ int yytype = YYTRANSLATE (yychar);
+ YYSIZE_T yysize0 = yytnamerr (0, yytname[yytype]);
+ YYSIZE_T yysize = yysize0;
+ YYSIZE_T yysize1;
+ int yysize_overflow = 0;
+ enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 };
+ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM];
+ int yyx;
+
+# if 0
+ /* This is so xgettext sees the translatable formats that are
+ constructed on the fly. */
+ YY_("syntax error, unexpected %s");
+ YY_("syntax error, unexpected %s, expecting %s");
+ YY_("syntax error, unexpected %s, expecting %s or %s");
+ YY_("syntax error, unexpected %s, expecting %s or %s or %s");
+ YY_("syntax error, unexpected %s, expecting %s or %s or %s or %s");
+# endif
+ char *yyfmt;
+ char const *yyf;
+ static char const yyunexpected[] = "syntax error, unexpected %s";
+ static char const yyexpecting[] = ", expecting %s";
+ static char const yyor[] = " or %s";
+ char yyformat[sizeof yyunexpected
+ + sizeof yyexpecting - 1
+ + ((YYERROR_VERBOSE_ARGS_MAXIMUM - 2)
+ * (sizeof yyor - 1))];
+ char const *yyprefix = yyexpecting;
+
+ /* Start YYX at -YYN if negative to avoid negative indexes in
+ YYCHECK. */
+ int yyxbegin = yyn < 0 ? -yyn : 0;
+
+ /* Stay within bounds of both yycheck and yytname. */
+ int yychecklim = YYLAST - yyn + 1;
+ int yyxend = yychecklim < YYNTOKENS ? yychecklim : YYNTOKENS;
+ int yycount = 1;
+
+ yyarg[0] = yytname[yytype];
+ yyfmt = yystpcpy (yyformat, yyunexpected);
+
+ for (yyx = yyxbegin; yyx < yyxend; ++yyx)
+ if (yycheck[yyx + yyn] == yyx && yyx != YYTERROR)
+ {
+ if (yycount == YYERROR_VERBOSE_ARGS_MAXIMUM)
+ {
+ yycount = 1;
+ yysize = yysize0;
+ yyformat[sizeof yyunexpected - 1] = '\0';
+ break;
+ }
+ yyarg[yycount++] = yytname[yyx];
+ yysize1 = yysize + yytnamerr (0, yytname[yyx]);
+ yysize_overflow |= (yysize1 < yysize);
+ yysize = yysize1;
+ yyfmt = yystpcpy (yyfmt, yyprefix);
+ yyprefix = yyor;
+ }
+
+ yyf = YY_(yyformat);
+ yysize1 = yysize + yystrlen (yyf);
+ yysize_overflow |= (yysize1 < yysize);
+ yysize = yysize1;
+
+ if (yysize_overflow)
+ return YYSIZE_MAXIMUM;
+
+ if (yyresult)
+ {
+ /* Avoid sprintf, as that infringes on the user's name space.
+ Don't have undefined behavior even if the translation
+ produced a string with the wrong number of "%s"s. */
+ char *yyp = yyresult;
+ int yyi = 0;
+ while ((*yyp = *yyf) != '\0')
+ {
+ if (*yyp == '%' && yyf[1] == 's' && yyi < yycount)
+ {
+ yyp += yytnamerr (yyp, yyarg[yyi++]);
+ yyf += 2;
+ }
+ else
+ {
+ yyp++;
+ yyf++;
+ }
+ }
+ }
+ return yysize;
+ }
+}
+#endif /* YYERROR_VERBOSE */
+
+
+/*-----------------------------------------------.
+| Release the memory associated to this symbol. |
+`-----------------------------------------------*/
+
+/*ARGSUSED*/
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+static void
+yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep)
+#else
+static void
+yydestruct (yymsg, yytype, yyvaluep)
+ const char *yymsg;
+ int yytype;
+ YYSTYPE *yyvaluep;
+#endif
+{
+ YYUSE (yyvaluep);
+
+ if (!yymsg)
+ yymsg = "Deleting";
+ YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp);
+
+ switch (yytype)
+ {
+
+ default:
+ break;
+ }
+}
+
+
+/* Prevent warnings from -Wmissing-prototypes. */
+
+#ifdef YYPARSE_PARAM
+#if defined __STDC__ || defined __cplusplus
+int yyparse (void *YYPARSE_PARAM);
+#else
+int yyparse ();
+#endif
+#else /* ! YYPARSE_PARAM */
+#if defined __STDC__ || defined __cplusplus
+int yyparse (void);
+#else
+int yyparse ();
+#endif
+#endif /* ! YYPARSE_PARAM */
+
+
+
+/* The look-ahead symbol. */
+int yychar;
+
+/* The semantic value of the look-ahead symbol. */
+YYSTYPE yylval;
+
+/* Number of syntax errors so far. */
+int yynerrs;
+
+
+
+/*----------.
+| yyparse. |
+`----------*/
+
+#ifdef YYPARSE_PARAM
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+int
+yyparse (void *YYPARSE_PARAM)
+#else
+int
+yyparse (YYPARSE_PARAM)
+ void *YYPARSE_PARAM;
+#endif
+#else /* ! YYPARSE_PARAM */
+#if (defined __STDC__ || defined __C99__FUNC__ \
+ || defined __cplusplus || defined _MSC_VER)
+int
+yyparse (void)
+#else
+int
+yyparse ()
+
+#endif
+#endif
+{
+
+ int yystate;
+ int yyn;
+ int yyresult;
+ /* Number of tokens to shift before error messages enabled. */
+ int yyerrstatus;
+ /* Look-ahead token as an internal (translated) token number. */
+ int yytoken = 0;
+#if YYERROR_VERBOSE
+ /* Buffer for error messages, and its allocated size. */
+ char yymsgbuf[128];
+ char *yymsg = yymsgbuf;
+ YYSIZE_T yymsg_alloc = sizeof yymsgbuf;
+#endif
+
+ /* Three stacks and their tools:
+ `yyss': related to states,
+ `yyvs': related to semantic values,
+ `yyls': related to locations.
+
+ Refer to the stacks thru separate pointers, to allow yyoverflow
+ to reallocate them elsewhere. */
+
+ /* The state stack. */
+ yytype_int16 yyssa[YYINITDEPTH];
+ yytype_int16 *yyss = yyssa;
+ yytype_int16 *yyssp;
+
+ /* The semantic value stack. */
+ YYSTYPE yyvsa[YYINITDEPTH];
+ YYSTYPE *yyvs = yyvsa;
+ YYSTYPE *yyvsp;
+
+
+
+#define YYPOPSTACK(N) (yyvsp -= (N), yyssp -= (N))
+
+ YYSIZE_T yystacksize = YYINITDEPTH;
+
+ /* The variables used to return semantic value and location from the
+ action routines. */
+ YYSTYPE yyval;
+
+
+ /* The number of symbols on the RHS of the reduced rule.
+ Keep to zero when no symbol should be popped. */
+ int yylen = 0;
+
+ YYDPRINTF ((stderr, "Starting parse\n"));
+
+ yystate = 0;
+ yyerrstatus = 0;
+ yynerrs = 0;
+ yychar = YYEMPTY; /* Cause a token to be read. */
+
+ /* Initialize stack pointers.
+ Waste one element of value and location stack
+ so that they stay on the same level as the state stack.
+ The wasted elements are never initialized. */
+
+ yyssp = yyss;
+ yyvsp = yyvs;
+
+ goto yysetstate;
+
+/*------------------------------------------------------------.
+| yynewstate -- Push a new state, which is found in yystate. |
+`------------------------------------------------------------*/
+ yynewstate:
+ /* In all cases, when you get here, the value and location stacks
+ have just been pushed. So pushing a state here evens the stacks. */
+ yyssp++;
+
+ yysetstate:
+ *yyssp = yystate;
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ {
+ /* Get the current used size of the three stacks, in elements. */
+ YYSIZE_T yysize = yyssp - yyss + 1;
+
+#ifdef yyoverflow
+ {
+ /* Give user a chance to reallocate the stack. Use copies of
+ these so that the &'s don't force the real ones into
+ memory. */
+ YYSTYPE *yyvs1 = yyvs;
+ yytype_int16 *yyss1 = yyss;
+
+
+ /* Each stack pointer address is followed by the size of the
+ data in use in that stack, in bytes. This used to be a
+ conditional around just the two extra args, but that might
+ be undefined if yyoverflow is a macro. */
+ yyoverflow (YY_("memory exhausted"),
+ &yyss1, yysize * sizeof (*yyssp),
+ &yyvs1, yysize * sizeof (*yyvsp),
+
+ &yystacksize);
+
+ yyss = yyss1;
+ yyvs = yyvs1;
+ }
+#else /* no yyoverflow */
+# ifndef YYSTACK_RELOCATE
+ goto yyexhaustedlab;
+# else
+ /* Extend the stack our own way. */
+ if (YYMAXDEPTH <= yystacksize)
+ goto yyexhaustedlab;
+ yystacksize *= 2;
+ if (YYMAXDEPTH < yystacksize)
+ yystacksize = YYMAXDEPTH;
+
+ {
+ yytype_int16 *yyss1 = yyss;
+ union yyalloc *yyptr =
+ (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize));
+ if (! yyptr)
+ goto yyexhaustedlab;
+ YYSTACK_RELOCATE (yyss);
+ YYSTACK_RELOCATE (yyvs);
+
+# undef YYSTACK_RELOCATE
+ if (yyss1 != yyssa)
+ YYSTACK_FREE (yyss1);
+ }
+# endif
+#endif /* no yyoverflow */
+
+ yyssp = yyss + yysize - 1;
+ yyvsp = yyvs + yysize - 1;
+
+
+ YYDPRINTF ((stderr, "Stack size increased to %lu\n",
+ (unsigned long int) yystacksize));
+
+ if (yyss + yystacksize - 1 <= yyssp)
+ YYABORT;
+ }
+
+ YYDPRINTF ((stderr, "Entering state %d\n", yystate));
+
+ goto yybackup;
+
+/*-----------.
+| yybackup. |
+`-----------*/
+yybackup:
+
+ /* Do appropriate processing given the current state. Read a
+ look-ahead token if we need one and don't already have one. */
+
+ /* First try to decide what to do without reference to look-ahead token. */
+ yyn = yypact[yystate];
+ if (yyn == YYPACT_NINF)
+ goto yydefault;
+
+ /* Not known => get a look-ahead token if don't already have one. */
+
+ /* YYCHAR is either YYEMPTY or YYEOF or a valid look-ahead symbol. */
+ if (yychar == YYEMPTY)
+ {
+ YYDPRINTF ((stderr, "Reading a token: "));
+ yychar = YYLEX;
+ }
+
+ if (yychar <= YYEOF)
+ {
+ yychar = yytoken = YYEOF;
+ YYDPRINTF ((stderr, "Now at end of input.\n"));
+ }
+ else
+ {
+ yytoken = YYTRANSLATE (yychar);
+ YY_SYMBOL_PRINT ("Next token is", yytoken, &yylval, &yylloc);
+ }
+
+ /* If the proper action on seeing token YYTOKEN is to reduce or to
+ detect an error, take that action. */
+ yyn += yytoken;
+ if (yyn < 0 || YYLAST < yyn || yycheck[yyn] != yytoken)
+ goto yydefault;
+ yyn = yytable[yyn];
+ if (yyn <= 0)
+ {
+ if (yyn == 0 || yyn == YYTABLE_NINF)
+ goto yyerrlab;
+ yyn = -yyn;
+ goto yyreduce;
+ }
+
+ if (yyn == YYFINAL)
+ YYACCEPT;
+
+ /* Count tokens shifted since error; after three, turn off error
+ status. */
+ if (yyerrstatus)
+ yyerrstatus--;
+
+ /* Shift the look-ahead token. */
+ YY_SYMBOL_PRINT ("Shifting", yytoken, &yylval, &yylloc);
+
+ /* Discard the shifted token unless it is eof. */
+ if (yychar != YYEOF)
+ yychar = YYEMPTY;
+
+ yystate = yyn;
+ *++yyvsp = yylval;
+
+ goto yynewstate;
+
+
+/*-----------------------------------------------------------.
+| yydefault -- do the default action for the current state. |
+`-----------------------------------------------------------*/
+yydefault:
+ yyn = yydefact[yystate];
+ if (yyn == 0)
+ goto yyerrlab;
+ goto yyreduce;
+
+
+/*-----------------------------.
+| yyreduce -- Do a reduction. |
+`-----------------------------*/
+yyreduce:
+ /* yyn is the number of a rule to reduce with. */
+ yylen = yyr2[yyn];
+
+ /* If YYLEN is nonzero, implement the default value of the action:
+ `$$ = $1'.
+
+ Otherwise, the following line sets YYVAL to garbage.
+ This behavior is undocumented and Bison
+ users should not rely upon it. Assigning to YYVAL
+ unconditionally makes the parser a bit smaller, and it avoids a
+ GCC warning that YYVAL may be used uninitialized. */
+ yyval = yyvsp[1-yylen];
+
+
+ YY_REDUCE_PRINT (yyn);
+ switch (yyn)
+ {
+ case 2:
+#line 131 "grammar.y"
+ {
+ finish_parse((yyvsp[(2) - (2)].blk).b);
+}
+ break;
+
+ case 4:
+#line 136 "grammar.y"
+ { (yyval.blk).q = qerr; }
+ break;
+
+ case 6:
+#line 139 "grammar.y"
+ { gen_and((yyvsp[(1) - (3)].blk).b, (yyvsp[(3) - (3)].blk).b); (yyval.blk) = (yyvsp[(3) - (3)].blk); }
+ break;
+
+ case 7:
+#line 140 "grammar.y"
+ { gen_and((yyvsp[(1) - (3)].blk).b, (yyvsp[(3) - (3)].blk).b); (yyval.blk) = (yyvsp[(3) - (3)].blk); }
+ break;
+
+ case 8:
+#line 141 "grammar.y"
+ { gen_or((yyvsp[(1) - (3)].blk).b, (yyvsp[(3) - (3)].blk).b); (yyval.blk) = (yyvsp[(3) - (3)].blk); }
+ break;
+
+ case 9:
+#line 142 "grammar.y"
+ { gen_or((yyvsp[(1) - (3)].blk).b, (yyvsp[(3) - (3)].blk).b); (yyval.blk) = (yyvsp[(3) - (3)].blk); }
+ break;
+
+ case 10:
+#line 144 "grammar.y"
+ { (yyval.blk) = (yyvsp[(0) - (1)].blk); }
+ break;
+
+ case 11:
+#line 146 "grammar.y"
+ { (yyval.blk) = (yyvsp[(0) - (1)].blk); }
+ break;
+
+ case 13:
+#line 149 "grammar.y"
+ { (yyval.blk).b = gen_ncode(NULL, (bpf_u_int32)(yyvsp[(1) - (1)].i),
+ (yyval.blk).q = (yyvsp[(0) - (1)].blk).q); }
+ break;
+
+ case 14:
+#line 151 "grammar.y"
+ { (yyval.blk) = (yyvsp[(2) - (3)].blk); }
+ break;
+
+ case 15:
+#line 153 "grammar.y"
+ { (yyval.blk).b = gen_scode((yyvsp[(1) - (1)].s), (yyval.blk).q = (yyvsp[(0) - (1)].blk).q); }
+ break;
+
+ case 16:
+#line 154 "grammar.y"
+ { (yyval.blk).b = gen_mcode((yyvsp[(1) - (3)].s), NULL, (yyvsp[(3) - (3)].i),
+ (yyval.blk).q = (yyvsp[(0) - (3)].blk).q); }
+ break;
+
+ case 17:
+#line 156 "grammar.y"
+ { (yyval.blk).b = gen_mcode((yyvsp[(1) - (3)].s), (yyvsp[(3) - (3)].s), 0,
+ (yyval.blk).q = (yyvsp[(0) - (3)].blk).q); }
+ break;
+
+ case 18:
+#line 158 "grammar.y"
+ {
+ /* Decide how to parse HID based on proto */
+ (yyval.blk).q = (yyvsp[(0) - (1)].blk).q;
+ switch ((yyval.blk).q.proto) {
+ case Q_DECNET:
+ (yyval.blk).b = gen_ncode((yyvsp[(1) - (1)].s), 0, (yyval.blk).q);
+ break;
+ default:
+ (yyval.blk).b = gen_ncode((yyvsp[(1) - (1)].s), 0, (yyval.blk).q);
+ break;
+ }
+ }
+ break;
+
+ case 19:
+#line 170 "grammar.y"
+ { (yyval.blk).b = gen_ecode((yyvsp[(1) - (1)].e), (yyval.blk).q = (yyvsp[(0) - (1)].blk).q); }
+ break;
+
+ case 20:
+#line 171 "grammar.y"
+ { gen_not((yyvsp[(2) - (2)].blk).b); (yyval.blk) = (yyvsp[(2) - (2)].blk); }
+ break;
+
+ case 21:
+#line 173 "grammar.y"
+ { (yyval.blk) = (yyvsp[(0) - (1)].blk); }
+ break;
+
+ case 22:
+#line 175 "grammar.y"
+ { (yyval.blk) = (yyvsp[(0) - (1)].blk); }
+ break;
+
+ case 24:
+#line 178 "grammar.y"
+ { gen_and((yyvsp[(1) - (3)].blk).b, (yyvsp[(3) - (3)].blk).b); (yyval.blk) = (yyvsp[(3) - (3)].blk); }
+ break;
+
+ case 25:
+#line 179 "grammar.y"
+ { gen_or((yyvsp[(1) - (3)].blk).b, (yyvsp[(3) - (3)].blk).b); (yyval.blk) = (yyvsp[(3) - (3)].blk); }
+ break;
+
+ case 26:
+#line 181 "grammar.y"
+ { (yyval.blk).b = gen_ncode(NULL, (bpf_u_int32)(yyvsp[(1) - (1)].i),
+ (yyval.blk).q = (yyvsp[(0) - (1)].blk).q); }
+ break;
+
+ case 29:
+#line 186 "grammar.y"
+ { gen_not((yyvsp[(2) - (2)].blk).b); (yyval.blk) = (yyvsp[(2) - (2)].blk); }
+ break;
+
+ case 30:
+#line 188 "grammar.y"
+ { QSET((yyval.blk).q, (yyvsp[(1) - (3)].i), (yyvsp[(2) - (3)].i), (yyvsp[(3) - (3)].i)); }
+ break;
+
+ case 31:
+#line 189 "grammar.y"
+ { QSET((yyval.blk).q, (yyvsp[(1) - (2)].i), (yyvsp[(2) - (2)].i), Q_DEFAULT); }
+ break;
+
+ case 32:
+#line 190 "grammar.y"
+ { QSET((yyval.blk).q, (yyvsp[(1) - (2)].i), Q_DEFAULT, (yyvsp[(2) - (2)].i)); }
+ break;
+
+ case 33:
+#line 191 "grammar.y"
+ { QSET((yyval.blk).q, (yyvsp[(1) - (2)].i), Q_DEFAULT, Q_PROTO); }
+ break;
+
+ case 34:
+#line 192 "grammar.y"
+ { QSET((yyval.blk).q, (yyvsp[(1) - (2)].i), Q_DEFAULT, (yyvsp[(2) - (2)].i)); }
+ break;
+
+ case 35:
+#line 194 "grammar.y"
+ { (yyval.blk) = (yyvsp[(2) - (2)].blk); }
+ break;
+
+ case 36:
+#line 195 "grammar.y"
+ { (yyval.blk).b = (yyvsp[(2) - (3)].blk).b; (yyval.blk).q = (yyvsp[(1) - (3)].blk).q; }
+ break;
+
+ case 37:
+#line 196 "grammar.y"
+ { (yyval.blk).b = gen_proto_abbrev((yyvsp[(1) - (1)].i)); (yyval.blk).q = qerr; }
+ break;
+
+ case 38:
+#line 197 "grammar.y"
+ { (yyval.blk).b = gen_relation((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a), 0);
+ (yyval.blk).q = qerr; }
+ break;
+
+ case 39:
+#line 199 "grammar.y"
+ { (yyval.blk).b = gen_relation((yyvsp[(2) - (3)].i), (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a), 1);
+ (yyval.blk).q = qerr; }
+ break;
+
+ case 40:
+#line 201 "grammar.y"
+ { (yyval.blk).b = (yyvsp[(1) - (1)].rblk); (yyval.blk).q = qerr; }
+ break;
+
+ case 42:
+#line 205 "grammar.y"
+ { (yyval.i) = Q_DEFAULT; }
+ break;
+
+ case 43:
+#line 208 "grammar.y"
+ { (yyval.i) = Q_SRC; }
+ break;
+
+ case 44:
+#line 209 "grammar.y"
+ { (yyval.i) = Q_DST; }
+ break;
+
+ case 45:
+#line 210 "grammar.y"
+ { (yyval.i) = Q_OR; }
+ break;
+
+ case 46:
+#line 211 "grammar.y"
+ { (yyval.i) = Q_OR; }
+ break;
+
+ case 47:
+#line 212 "grammar.y"
+ { (yyval.i) = Q_AND; }
+ break;
+
+ case 48:
+#line 213 "grammar.y"
+ { (yyval.i) = Q_AND; }
+ break;
+
+ case 49:
+#line 216 "grammar.y"
+ { (yyval.i) = Q_HOST; }
+ break;
+
+ case 50:
+#line 217 "grammar.y"
+ { (yyval.i) = Q_NET; }
+ break;
+
+ case 51:
+#line 218 "grammar.y"
+ { (yyval.i) = Q_PORT; }
+ break;
+
+ case 52:
+#line 221 "grammar.y"
+ { (yyval.i) = Q_GATEWAY; }
+ break;
+
+ case 53:
+#line 223 "grammar.y"
+ { (yyval.i) = Q_LINK; }
+ break;
+
+ case 54:
+#line 224 "grammar.y"
+ { (yyval.i) = Q_IP; }
+ break;
+
+ case 55:
+#line 225 "grammar.y"
+ { (yyval.i) = Q_ARP; }
+ break;
+
+ case 56:
+#line 226 "grammar.y"
+ { (yyval.i) = Q_RARP; }
+ break;
+
+ case 57:
+#line 227 "grammar.y"
+ { (yyval.i) = Q_TCP; }
+ break;
+
+ case 58:
+#line 228 "grammar.y"
+ { (yyval.i) = Q_UDP; }
+ break;
+
+ case 59:
+#line 229 "grammar.y"
+ { (yyval.i) = Q_ICMP; }
+ break;
+
+ case 60:
+#line 230 "grammar.y"
+ { (yyval.i) = Q_IGMP; }
+ break;
+
+ case 61:
+#line 231 "grammar.y"
+ { (yyval.i) = Q_IGRP; }
+ break;
+
+ case 62:
+#line 232 "grammar.y"
+ { (yyval.i) = Q_ATALK; }
+ break;
+
+ case 63:
+#line 233 "grammar.y"
+ { (yyval.i) = Q_DECNET; }
+ break;
+
+ case 64:
+#line 234 "grammar.y"
+ { (yyval.i) = Q_LAT; }
+ break;
+
+ case 65:
+#line 235 "grammar.y"
+ { (yyval.i) = Q_SCA; }
+ break;
+
+ case 66:
+#line 236 "grammar.y"
+ { (yyval.i) = Q_MOPDL; }
+ break;
+
+ case 67:
+#line 237 "grammar.y"
+ { (yyval.i) = Q_MOPRC; }
+ break;
+
+ case 68:
+#line 239 "grammar.y"
+ { (yyval.rblk) = gen_broadcast((yyvsp[(1) - (2)].i)); }
+ break;
+
+ case 69:
+#line 240 "grammar.y"
+ { (yyval.rblk) = gen_multicast((yyvsp[(1) - (2)].i)); }
+ break;
+
+ case 70:
+#line 241 "grammar.y"
+ { (yyval.rblk) = gen_less((yyvsp[(2) - (2)].i)); }
+ break;
+
+ case 71:
+#line 242 "grammar.y"
+ { (yyval.rblk) = gen_greater((yyvsp[(2) - (2)].i)); }
+ break;
+
+ case 72:
+#line 243 "grammar.y"
+ { (yyval.rblk) = gen_byteop((yyvsp[(3) - (4)].i), (yyvsp[(2) - (4)].i), (yyvsp[(4) - (4)].i)); }
+ break;
+
+ case 73:
+#line 244 "grammar.y"
+ { (yyval.rblk) = gen_inbound(0); }
+ break;
+
+ case 74:
+#line 245 "grammar.y"
+ { (yyval.rblk) = gen_inbound(1); }
+ break;
+
+ case 75:
+#line 247 "grammar.y"
+ { (yyval.i) = BPF_JGT; }
+ break;
+
+ case 76:
+#line 248 "grammar.y"
+ { (yyval.i) = BPF_JGE; }
+ break;
+
+ case 77:
+#line 249 "grammar.y"
+ { (yyval.i) = BPF_JEQ; }
+ break;
+
+ case 78:
+#line 251 "grammar.y"
+ { (yyval.i) = BPF_JGT; }
+ break;
+
+ case 79:
+#line 252 "grammar.y"
+ { (yyval.i) = BPF_JGE; }
+ break;
+
+ case 80:
+#line 253 "grammar.y"
+ { (yyval.i) = BPF_JEQ; }
+ break;
+
+ case 81:
+#line 255 "grammar.y"
+ { (yyval.a) = gen_loadi((yyvsp[(1) - (1)].i)); }
+ break;
+
+ case 83:
+#line 258 "grammar.y"
+ { (yyval.a) = gen_load((yyvsp[(1) - (4)].i), (yyvsp[(3) - (4)].a), 1); }
+ break;
+
+ case 84:
+#line 259 "grammar.y"
+ { (yyval.a) = gen_load((yyvsp[(1) - (6)].i), (yyvsp[(3) - (6)].a), (yyvsp[(5) - (6)].i)); }
+ break;
+
+ case 85:
+#line 260 "grammar.y"
+ { (yyval.a) = gen_arth(BPF_ADD, (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a)); }
+ break;
+
+ case 86:
+#line 261 "grammar.y"
+ { (yyval.a) = gen_arth(BPF_SUB, (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a)); }
+ break;
+
+ case 87:
+#line 262 "grammar.y"
+ { (yyval.a) = gen_arth(BPF_MUL, (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a)); }
+ break;
+
+ case 88:
+#line 263 "grammar.y"
+ { (yyval.a) = gen_arth(BPF_DIV, (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a)); }
+ break;
+
+ case 89:
+#line 264 "grammar.y"
+ { (yyval.a) = gen_arth(BPF_AND, (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a)); }
+ break;
+
+ case 90:
+#line 265 "grammar.y"
+ { (yyval.a) = gen_arth(BPF_OR, (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a)); }
+ break;
+
+ case 91:
+#line 266 "grammar.y"
+ { (yyval.a) = gen_arth(BPF_LSH, (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a)); }
+ break;
+
+ case 92:
+#line 267 "grammar.y"
+ { (yyval.a) = gen_arth(BPF_RSH, (yyvsp[(1) - (3)].a), (yyvsp[(3) - (3)].a)); }
+ break;
+
+ case 93:
+#line 268 "grammar.y"
+ { (yyval.a) = gen_neg((yyvsp[(2) - (2)].a)); }
+ break;
+
+ case 94:
+#line 269 "grammar.y"
+ { (yyval.a) = (yyvsp[(2) - (3)].a); }
+ break;
+
+ case 95:
+#line 270 "grammar.y"
+ { (yyval.a) = gen_loadlen(); }
+ break;
+
+ case 96:
+#line 272 "grammar.y"
+ { (yyval.i) = '&'; }
+ break;
+
+ case 97:
+#line 273 "grammar.y"
+ { (yyval.i) = '|'; }
+ break;
+
+ case 98:
+#line 274 "grammar.y"
+ { (yyval.i) = '<'; }
+ break;
+
+ case 99:
+#line 275 "grammar.y"
+ { (yyval.i) = '>'; }
+ break;
+
+ case 100:
+#line 276 "grammar.y"
+ { (yyval.i) = '='; }
+ break;
+
+ case 102:
+#line 279 "grammar.y"
+ { (yyval.i) = (yyvsp[(2) - (3)].i); }
+ break;
+
+
+/* Line 1267 of yacc.c. */
+#line 2165 "y.tab.c"
+ default: break;
+ }
+ YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc);
+
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+
+ *++yyvsp = yyval;
+
+
+ /* Now `shift' the result of the reduction. Determine what state
+ that goes to, based on the state we popped back to and the rule
+ number reduced by. */
+
+ yyn = yyr1[yyn];
+
+ yystate = yypgoto[yyn - YYNTOKENS] + *yyssp;
+ if (0 <= yystate && yystate <= YYLAST && yycheck[yystate] == *yyssp)
+ yystate = yytable[yystate];
+ else
+ yystate = yydefgoto[yyn - YYNTOKENS];
+
+ goto yynewstate;
+
+
+/*------------------------------------.
+| yyerrlab -- here on detecting error |
+`------------------------------------*/
+yyerrlab:
+ /* If not already recovering from an error, report this error. */
+ if (!yyerrstatus)
+ {
+ ++yynerrs;
+#if ! YYERROR_VERBOSE
+ yyerror (YY_("syntax error"));
+#else
+ {
+ YYSIZE_T yysize = yysyntax_error (0, yystate, yychar);
+ if (yymsg_alloc < yysize && yymsg_alloc < YYSTACK_ALLOC_MAXIMUM)
+ {
+ YYSIZE_T yyalloc = 2 * yysize;
+ if (! (yysize <= yyalloc && yyalloc <= YYSTACK_ALLOC_MAXIMUM))
+ yyalloc = YYSTACK_ALLOC_MAXIMUM;
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+ yymsg = (char *) YYSTACK_ALLOC (yyalloc);
+ if (yymsg)
+ yymsg_alloc = yyalloc;
+ else
+ {
+ yymsg = yymsgbuf;
+ yymsg_alloc = sizeof yymsgbuf;
+ }
+ }
+
+ if (0 < yysize && yysize <= yymsg_alloc)
+ {
+ (void) yysyntax_error (yymsg, yystate, yychar);
+ yyerror (yymsg);
+ }
+ else
+ {
+ yyerror (YY_("syntax error"));
+ if (yysize != 0)
+ goto yyexhaustedlab;
+ }
+ }
+#endif
+ }
+
+
+
+ if (yyerrstatus == 3)
+ {
+ /* If just tried and failed to reuse look-ahead token after an
+ error, discard it. */
+
+ if (yychar <= YYEOF)
+ {
+ /* Return failure if at end of input. */
+ if (yychar == YYEOF)
+ YYABORT;
+ }
+ else
+ {
+ yydestruct ("Error: discarding",
+ yytoken, &yylval);
+ yychar = YYEMPTY;
+ }
+ }
+
+ /* Else will try to reuse look-ahead token after shifting the error
+ token. */
+ goto yyerrlab1;
+
+
+/*---------------------------------------------------.
+| yyerrorlab -- error raised explicitly by YYERROR. |
+`---------------------------------------------------*/
+yyerrorlab:
+
+ /* Pacify compilers like GCC when the user code never invokes
+ YYERROR and the label yyerrorlab therefore never appears in user
+ code. */
+ if (/*CONSTCOND*/ 0)
+ goto yyerrorlab;
+
+ /* Do not reclaim the symbols of the rule which action triggered
+ this YYERROR. */
+ YYPOPSTACK (yylen);
+ yylen = 0;
+ YY_STACK_PRINT (yyss, yyssp);
+ yystate = *yyssp;
+ goto yyerrlab1;
+
+
+/*-------------------------------------------------------------.
+| yyerrlab1 -- common code for both syntax error and YYERROR. |
+`-------------------------------------------------------------*/
+yyerrlab1:
+ yyerrstatus = 3; /* Each real token shifted decrements this. */
+
+ for (;;)
+ {
+ yyn = yypact[yystate];
+ if (yyn != YYPACT_NINF)
+ {
+ yyn += YYTERROR;
+ if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR)
+ {
+ yyn = yytable[yyn];
+ if (0 < yyn)
+ break;
+ }
+ }
+
+ /* Pop the current state because it cannot handle the error token. */
+ if (yyssp == yyss)
+ YYABORT;
+
+
+ yydestruct ("Error: popping",
+ yystos[yystate], yyvsp);
+ YYPOPSTACK (1);
+ yystate = *yyssp;
+ YY_STACK_PRINT (yyss, yyssp);
+ }
+
+ if (yyn == YYFINAL)
+ YYACCEPT;
+
+ *++yyvsp = yylval;
+
+
+ /* Shift the error token. */
+ YY_SYMBOL_PRINT ("Shifting", yystos[yyn], yyvsp, yylsp);
+
+ yystate = yyn;
+ goto yynewstate;
+
+
+/*-------------------------------------.
+| yyacceptlab -- YYACCEPT comes here. |
+`-------------------------------------*/
+yyacceptlab:
+ yyresult = 0;
+ goto yyreturn;
+
+/*-----------------------------------.
+| yyabortlab -- YYABORT comes here. |
+`-----------------------------------*/
+yyabortlab:
+ yyresult = 1;
+ goto yyreturn;
+
+#ifndef yyoverflow
+/*-------------------------------------------------.
+| yyexhaustedlab -- memory exhaustion comes here. |
+`-------------------------------------------------*/
+yyexhaustedlab:
+ yyerror (YY_("memory exhausted"));
+ yyresult = 2;
+ /* Fall through. */
+#endif
+
+yyreturn:
+ if (yychar != YYEOF && yychar != YYEMPTY)
+ yydestruct ("Cleanup: discarding lookahead",
+ yytoken, &yylval);
+ /* Do not reclaim the symbols of the rule which action triggered
+ this YYABORT or YYACCEPT. */
+ YYPOPSTACK (yylen);
+ YY_STACK_PRINT (yyss, yyssp);
+ while (yyssp != yyss)
+ {
+ yydestruct ("Cleanup: popping",
+ yystos[*yyssp], yyvsp);
+ YYPOPSTACK (1);
+ }
+#ifndef yyoverflow
+ if (yyss != yyssa)
+ YYSTACK_FREE (yyss);
+#endif
+#if YYERROR_VERBOSE
+ if (yymsg != yymsgbuf)
+ YYSTACK_FREE (yymsg);
+#endif
+ /* Make sure YYID is used. */
+ return YYID (yyresult);
+}
+
+
+#line 281 "grammar.y"
+
+
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/grammar.y b/package/etrax-tools/src/e100boot/libpcap-0.4/grammar.y
new file mode 100644
index 000000000..fc3187949
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/grammar.y
@@ -0,0 +1,281 @@
+%{
+/*
+ * Copyright (c) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/grammar.y,v 1.1 1999/08/26 10:05:22 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/socket.h>
+
+#if __STDC__
+struct mbuf;
+struct rtentry;
+#endif
+
+#include <net/if.h>
+
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+
+#include <stdio.h>
+
+#include "pcap-int.h"
+
+#include "gencode.h"
+#include <pcap-namedb.h>
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#define QSET(q, p, d, a) (q).proto = (p),\
+ (q).dir = (d),\
+ (q).addr = (a)
+
+int n_errors = 0;
+
+static struct qual qerr = { Q_UNDEF, Q_UNDEF, Q_UNDEF, Q_UNDEF };
+
+static void
+yyerror(char *msg)
+{
+ ++n_errors;
+ bpf_error("%s", msg);
+ /* NOTREACHED */
+}
+
+#ifndef YYBISON
+int yyparse(void);
+
+int
+pcap_parse()
+{
+ return (yyparse());
+}
+#endif
+
+%}
+
+%union {
+ int i;
+ bpf_u_int32 h;
+ u_char *e;
+ char *s;
+ struct stmt *stmt;
+ struct arth *a;
+ struct {
+ struct qual q;
+ struct block *b;
+ } blk;
+ struct block *rblk;
+}
+
+%type <blk> expr id nid pid term rterm qid
+%type <blk> head
+%type <i> pqual dqual aqual ndaqual
+%type <a> arth narth
+%type <i> byteop pname pnum relop irelop
+%type <blk> and or paren not null prog
+%type <rblk> other
+
+%token DST SRC HOST GATEWAY
+%token NET MASK PORT LESS GREATER PROTO BYTE
+%token ARP RARP IP TCP UDP ICMP IGMP IGRP
+%token ATALK DECNET LAT SCA MOPRC MOPDL
+%token TK_BROADCAST TK_MULTICAST
+%token NUM INBOUND OUTBOUND
+%token LINK
+%token GEQ LEQ NEQ
+%token ID EID HID
+%token LSH RSH
+%token LEN
+
+%type <s> ID
+%type <e> EID
+%type <s> HID
+%type <i> NUM
+
+%left OR AND
+%nonassoc '!'
+%left '|'
+%left '&'
+%left LSH RSH
+%left '+' '-'
+%left '*' '/'
+%nonassoc UMINUS
+%%
+prog: null expr
+{
+ finish_parse($2.b);
+}
+ | null
+ ;
+null: /* null */ { $$.q = qerr; }
+ ;
+expr: term
+ | expr and term { gen_and($1.b, $3.b); $$ = $3; }
+ | expr and id { gen_and($1.b, $3.b); $$ = $3; }
+ | expr or term { gen_or($1.b, $3.b); $$ = $3; }
+ | expr or id { gen_or($1.b, $3.b); $$ = $3; }
+ ;
+and: AND { $$ = $<blk>0; }
+ ;
+or: OR { $$ = $<blk>0; }
+ ;
+id: nid
+ | pnum { $$.b = gen_ncode(NULL, (bpf_u_int32)$1,
+ $$.q = $<blk>0.q); }
+ | paren pid ')' { $$ = $2; }
+ ;
+nid: ID { $$.b = gen_scode($1, $$.q = $<blk>0.q); }
+ | HID '/' NUM { $$.b = gen_mcode($1, NULL, $3,
+ $$.q = $<blk>0.q); }
+ | HID MASK HID { $$.b = gen_mcode($1, $3, 0,
+ $$.q = $<blk>0.q); }
+ | HID {
+ /* Decide how to parse HID based on proto */
+ $$.q = $<blk>0.q;
+ switch ($$.q.proto) {
+ case Q_DECNET:
+ $$.b = gen_ncode($1, 0, $$.q);
+ break;
+ default:
+ $$.b = gen_ncode($1, 0, $$.q);
+ break;
+ }
+ }
+ | EID { $$.b = gen_ecode($1, $$.q = $<blk>0.q); }
+ | not id { gen_not($2.b); $$ = $2; }
+ ;
+not: '!' { $$ = $<blk>0; }
+ ;
+paren: '(' { $$ = $<blk>0; }
+ ;
+pid: nid
+ | qid and id { gen_and($1.b, $3.b); $$ = $3; }
+ | qid or id { gen_or($1.b, $3.b); $$ = $3; }
+ ;
+qid: pnum { $$.b = gen_ncode(NULL, (bpf_u_int32)$1,
+ $$.q = $<blk>0.q); }
+ | pid
+ ;
+term: rterm
+ | not term { gen_not($2.b); $$ = $2; }
+ ;
+head: pqual dqual aqual { QSET($$.q, $1, $2, $3); }
+ | pqual dqual { QSET($$.q, $1, $2, Q_DEFAULT); }
+ | pqual aqual { QSET($$.q, $1, Q_DEFAULT, $2); }
+ | pqual PROTO { QSET($$.q, $1, Q_DEFAULT, Q_PROTO); }
+ | pqual ndaqual { QSET($$.q, $1, Q_DEFAULT, $2); }
+ ;
+rterm: head id { $$ = $2; }
+ | paren expr ')' { $$.b = $2.b; $$.q = $1.q; }
+ | pname { $$.b = gen_proto_abbrev($1); $$.q = qerr; }
+ | arth relop arth { $$.b = gen_relation($2, $1, $3, 0);
+ $$.q = qerr; }
+ | arth irelop arth { $$.b = gen_relation($2, $1, $3, 1);
+ $$.q = qerr; }
+ | other { $$.b = $1; $$.q = qerr; }
+ ;
+/* protocol level qualifiers */
+pqual: pname
+ | { $$ = Q_DEFAULT; }
+ ;
+/* 'direction' qualifiers */
+dqual: SRC { $$ = Q_SRC; }
+ | DST { $$ = Q_DST; }
+ | SRC OR DST { $$ = Q_OR; }
+ | DST OR SRC { $$ = Q_OR; }
+ | SRC AND DST { $$ = Q_AND; }
+ | DST AND SRC { $$ = Q_AND; }
+ ;
+/* address type qualifiers */
+aqual: HOST { $$ = Q_HOST; }
+ | NET { $$ = Q_NET; }
+ | PORT { $$ = Q_PORT; }
+ ;
+/* non-directional address type qualifiers */
+ndaqual: GATEWAY { $$ = Q_GATEWAY; }
+ ;
+pname: LINK { $$ = Q_LINK; }
+ | IP { $$ = Q_IP; }
+ | ARP { $$ = Q_ARP; }
+ | RARP { $$ = Q_RARP; }
+ | TCP { $$ = Q_TCP; }
+ | UDP { $$ = Q_UDP; }
+ | ICMP { $$ = Q_ICMP; }
+ | IGMP { $$ = Q_IGMP; }
+ | IGRP { $$ = Q_IGRP; }
+ | ATALK { $$ = Q_ATALK; }
+ | DECNET { $$ = Q_DECNET; }
+ | LAT { $$ = Q_LAT; }
+ | SCA { $$ = Q_SCA; }
+ | MOPDL { $$ = Q_MOPDL; }
+ | MOPRC { $$ = Q_MOPRC; }
+ ;
+other: pqual TK_BROADCAST { $$ = gen_broadcast($1); }
+ | pqual TK_MULTICAST { $$ = gen_multicast($1); }
+ | LESS NUM { $$ = gen_less($2); }
+ | GREATER NUM { $$ = gen_greater($2); }
+ | BYTE NUM byteop NUM { $$ = gen_byteop($3, $2, $4); }
+ | INBOUND { $$ = gen_inbound(0); }
+ | OUTBOUND { $$ = gen_inbound(1); }
+ ;
+relop: '>' { $$ = BPF_JGT; }
+ | GEQ { $$ = BPF_JGE; }
+ | '=' { $$ = BPF_JEQ; }
+ ;
+irelop: LEQ { $$ = BPF_JGT; }
+ | '<' { $$ = BPF_JGE; }
+ | NEQ { $$ = BPF_JEQ; }
+ ;
+arth: pnum { $$ = gen_loadi($1); }
+ | narth
+ ;
+narth: pname '[' arth ']' { $$ = gen_load($1, $3, 1); }
+ | pname '[' arth ':' NUM ']' { $$ = gen_load($1, $3, $5); }
+ | arth '+' arth { $$ = gen_arth(BPF_ADD, $1, $3); }
+ | arth '-' arth { $$ = gen_arth(BPF_SUB, $1, $3); }
+ | arth '*' arth { $$ = gen_arth(BPF_MUL, $1, $3); }
+ | arth '/' arth { $$ = gen_arth(BPF_DIV, $1, $3); }
+ | arth '&' arth { $$ = gen_arth(BPF_AND, $1, $3); }
+ | arth '|' arth { $$ = gen_arth(BPF_OR, $1, $3); }
+ | arth LSH arth { $$ = gen_arth(BPF_LSH, $1, $3); }
+ | arth RSH arth { $$ = gen_arth(BPF_RSH, $1, $3); }
+ | '-' arth %prec UMINUS { $$ = gen_neg($2); }
+ | paren narth ')' { $$ = $2; }
+ | LEN { $$ = gen_loadlen(); }
+ ;
+byteop: '&' { $$ = '&'; }
+ | '|' { $$ = '|'; }
+ | '<' { $$ = '<'; }
+ | '>' { $$ = '>'; }
+ | '=' { $$ = '='; }
+ ;
+pnum: NUM
+ | paren pnum ')' { $$ = $2; }
+ ;
+%%
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/inet.c b/package/etrax-tools/src/e100boot/libpcap-0.4/inet.c
new file mode 100644
index 000000000..ddb3a15df
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/inet.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 1994, 1995, 1996, 1997, 1998
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the Computer Systems
+ * Engineering Group at Lawrence Berkeley Laboratory.
+ * 4. Neither the name of the University nor of the Laboratory may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/inet.c,v 1.1 1999/08/26 10:05:22 johana Exp $ (LBL)";
+#endif
+
+#include <sys/param.h>
+#include <sys/file.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+#ifdef HAVE_SYS_SOCKIO_H
+#include <sys/sockio.h>
+#endif
+#include <sys/time.h> /* concession to AIX */
+
+#if __STDC__
+struct mbuf;
+struct rtentry;
+#endif
+
+#include <net/if.h>
+#include <netinet/in.h>
+
+#include <ctype.h>
+#include <errno.h>
+#include <memory.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+/* Not all systems have IFF_LOOPBACK */
+#ifdef IFF_LOOPBACK
+#define ISLOOPBACK(p) ((p)->ifr_flags & IFF_LOOPBACK)
+#else
+#define ISLOOPBACK(p) ((p)->ifr_name[0] == 'l' && (p)->ifr_name[1] == 'o' && \
+ (isdigit((p)->ifr_name[2]) || (p)->ifr_name[2] == '\0'))
+#endif
+
+/*
+ * Return the name of a network interface attached to the system, or NULL
+ * if none can be found. The interface must be configured up; the
+ * lowest unit number is preferred; loopback is ignored.
+ */
+char *
+pcap_lookupdev(errbuf)
+ register char *errbuf;
+{
+ register int fd, minunit, n;
+ register char *cp;
+ register struct ifreq *ifrp, *ifend, *ifnext, *mp;
+ struct ifconf ifc;
+ struct ifreq ibuf[16], ifr;
+ static char device[sizeof(ifrp->ifr_name) + 1];
+
+ fd = socket(AF_INET, SOCK_DGRAM, 0);
+ if (fd < 0) {
+ (void)sprintf(errbuf, "socket: %s", pcap_strerror(errno));
+ return (NULL);
+ }
+ ifc.ifc_len = sizeof ibuf;
+ ifc.ifc_buf = (caddr_t)ibuf;
+
+ memset((char *)ibuf, 0, sizeof(ibuf));
+ if (ioctl(fd, SIOCGIFCONF, (char *)&ifc) < 0 ||
+ ifc.ifc_len < sizeof(struct ifreq)) {
+ (void)sprintf(errbuf, "SIOCGIFCONF: %s", pcap_strerror(errno));
+ (void)close(fd);
+ return (NULL);
+ }
+ ifrp = ibuf;
+ ifend = (struct ifreq *)((char *)ibuf + ifc.ifc_len);
+
+ mp = NULL;
+ minunit = 666;
+ for (; ifrp < ifend; ifrp = ifnext) {
+#ifdef HAVE_SOCKADDR_SA_LEN
+ n = ifrp->ifr_addr.sa_len + sizeof(ifrp->ifr_name);
+ if (n < sizeof(*ifrp))
+ ifnext = ifrp + 1;
+ else
+ ifnext = (struct ifreq *)((char *)ifrp + n);
+ if (ifrp->ifr_addr.sa_family != AF_INET)
+ continue;
+#else
+ ifnext = ifrp + 1;
+#endif
+ /*
+ * Need a template to preserve address info that is
+ * used below to locate the next entry. (Otherwise,
+ * SIOCGIFFLAGS stomps over it because the requests
+ * are returned in a union.)
+ */
+ strncpy(ifr.ifr_name, ifrp->ifr_name, sizeof(ifr.ifr_name));
+ if (ioctl(fd, SIOCGIFFLAGS, (char *)&ifr) < 0) {
+ if (errno == ENXIO)
+ continue;
+ (void)sprintf(errbuf, "SIOCGIFFLAGS: %.*s: %s",
+ (int)sizeof(ifr.ifr_name), ifr.ifr_name,
+ pcap_strerror(errno));
+ (void)close(fd);
+ return (NULL);
+ }
+
+ /* Must be up and not the loopback */
+ if ((ifr.ifr_flags & IFF_UP) == 0 || ISLOOPBACK(&ifr))
+ continue;
+
+ for (cp = ifrp->ifr_name; !isdigit(*cp); ++cp)
+ continue;
+ n = atoi(cp);
+ if (n < minunit) {
+ minunit = n;
+ mp = ifrp;
+ }
+ }
+ (void)close(fd);
+ if (mp == NULL) {
+ (void)strcpy(errbuf, "no suitable device found");
+ return (NULL);
+ }
+
+ (void)strncpy(device, mp->ifr_name, sizeof(device) - 1);
+ device[sizeof(device) - 1] = '\0';
+ return (device);
+}
+
+int
+pcap_lookupnet(device, netp, maskp, errbuf)
+ register char *device;
+ register bpf_u_int32 *netp, *maskp;
+ register char *errbuf;
+{
+ register int fd;
+ register struct sockaddr_in *sin;
+ struct ifreq ifr;
+
+ fd = socket(AF_INET, SOCK_DGRAM, 0);
+ if (fd < 0) {
+ (void)sprintf(errbuf, "socket: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ memset(&ifr, 0, sizeof(ifr));
+#ifdef linux
+ /* XXX Work around Linux kernel bug */
+ ifr.ifr_addr.sa_family = AF_INET;
+#endif
+ (void)strncpy(ifr.ifr_name, device, sizeof(ifr.ifr_name));
+ if (ioctl(fd, SIOCGIFADDR, (char *)&ifr) < 0) {
+ (void)sprintf(errbuf, "SIOCGIFADDR: %s: %s",
+ device, pcap_strerror(errno));
+ (void)close(fd);
+ return (-1);
+ }
+ sin = (struct sockaddr_in *)&ifr.ifr_addr;
+ *netp = sin->sin_addr.s_addr;
+ if (ioctl(fd, SIOCGIFNETMASK, (char *)&ifr) < 0) {
+ (void)sprintf(errbuf, "SIOCGIFNETMASK: %s: %s",
+ device, pcap_strerror(errno));
+ (void)close(fd);
+ return (-1);
+ }
+ (void)close(fd);
+ *maskp = sin->sin_addr.s_addr;
+ if (*maskp == 0) {
+ if (IN_CLASSA(*netp))
+ *maskp = IN_CLASSA_NET;
+ else if (IN_CLASSB(*netp))
+ *maskp = IN_CLASSB_NET;
+ else if (IN_CLASSC(*netp))
+ *maskp = IN_CLASSC_NET;
+ else {
+ (void)sprintf(errbuf, "inet class for 0x%x unknown",
+ *netp);
+ return (-1);
+ }
+ }
+ *netp &= *maskp;
+ return (0);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/install-sh b/package/etrax-tools/src/e100boot/libpcap-0.4/install-sh
new file mode 100755
index 000000000..ebc66913e
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/install-sh
@@ -0,0 +1,250 @@
+#! /bin/sh
+#
+# install - install a program, script, or datafile
+# This comes from X11R5 (mit/util/scripts/install.sh).
+#
+# Copyright 1991 by the Massachusetts Institute of Technology
+#
+# Permission to use, copy, modify, distribute, and sell this software and its
+# documentation for any purpose is hereby granted without fee, provided that
+# the above copyright notice appear in all copies and that both that
+# copyright notice and this permission notice appear in supporting
+# documentation, and that the name of M.I.T. not be used in advertising or
+# publicity pertaining to distribution of the software without specific,
+# written prior permission. M.I.T. makes no representations about the
+# suitability of this software for any purpose. It is provided "as is"
+# without express or implied warranty.
+#
+# Calling this script install-sh is preferred over install.sh, to prevent
+# `make' implicit rules from creating a file called install from it
+# when there is no Makefile.
+#
+# This script is compatible with the BSD install script, but was written
+# from scratch. It can only install one file at a time, a restriction
+# shared with many OS's install programs.
+
+
+# set DOITPROG to echo to test this script
+
+# Don't use :- since 4.3BSD and earlier shells don't like it.
+doit="${DOITPROG-}"
+
+
+# put in absolute paths if you don't have them in your path; or use env. vars.
+
+mvprog="${MVPROG-mv}"
+cpprog="${CPPROG-cp}"
+chmodprog="${CHMODPROG-chmod}"
+chownprog="${CHOWNPROG-chown}"
+chgrpprog="${CHGRPPROG-chgrp}"
+stripprog="${STRIPPROG-strip}"
+rmprog="${RMPROG-rm}"
+mkdirprog="${MKDIRPROG-mkdir}"
+
+transformbasename=""
+transform_arg=""
+instcmd="$mvprog"
+chmodcmd="$chmodprog 0755"
+chowncmd=""
+chgrpcmd=""
+stripcmd=""
+rmcmd="$rmprog -f"
+mvcmd="$mvprog"
+src=""
+dst=""
+dir_arg=""
+
+while [ x"$1" != x ]; do
+ case $1 in
+ -c) instcmd="$cpprog"
+ shift
+ continue;;
+
+ -d) dir_arg=true
+ shift
+ continue;;
+
+ -m) chmodcmd="$chmodprog $2"
+ shift
+ shift
+ continue;;
+
+ -o) chowncmd="$chownprog $2"
+ shift
+ shift
+ continue;;
+
+ -g) chgrpcmd="$chgrpprog $2"
+ shift
+ shift
+ continue;;
+
+ -s) stripcmd="$stripprog"
+ shift
+ continue;;
+
+ -t=*) transformarg=`echo $1 | sed 's/-t=//'`
+ shift
+ continue;;
+
+ -b=*) transformbasename=`echo $1 | sed 's/-b=//'`
+ shift
+ continue;;
+
+ *) if [ x"$src" = x ]
+ then
+ src=$1
+ else
+ # this colon is to work around a 386BSD /bin/sh bug
+ :
+ dst=$1
+ fi
+ shift
+ continue;;
+ esac
+done
+
+if [ x"$src" = x ]
+then
+ echo "install: no input file specified"
+ exit 1
+else
+ true
+fi
+
+if [ x"$dir_arg" != x ]; then
+ dst=$src
+ src=""
+
+ if [ -d $dst ]; then
+ instcmd=:
+ else
+ instcmd=mkdir
+ fi
+else
+
+# Waiting for this to be detected by the "$instcmd $src $dsttmp" command
+# might cause directories to be created, which would be especially bad
+# if $src (and thus $dsttmp) contains '*'.
+
+ if [ -f $src -o -d $src ]
+ then
+ true
+ else
+ echo "install: $src does not exist"
+ exit 1
+ fi
+
+ if [ x"$dst" = x ]
+ then
+ echo "install: no destination specified"
+ exit 1
+ else
+ true
+ fi
+
+# If destination is a directory, append the input filename; if your system
+# does not like double slashes in filenames, you may need to add some logic
+
+ if [ -d $dst ]
+ then
+ dst="$dst"/`basename $src`
+ else
+ true
+ fi
+fi
+
+## this sed command emulates the dirname command
+dstdir=`echo $dst | sed -e 's,[^/]*$,,;s,/$,,;s,^$,.,'`
+
+# Make sure that the destination directory exists.
+# this part is taken from Noah Friedman's mkinstalldirs script
+
+# Skip lots of stat calls in the usual case.
+if [ ! -d "$dstdir" ]; then
+defaultIFS='
+'
+IFS="${IFS-${defaultIFS}}"
+
+oIFS="${IFS}"
+# Some sh's can't handle IFS=/ for some reason.
+IFS='%'
+set - `echo ${dstdir} | sed -e 's@/@%@g' -e 's@^%@/@'`
+IFS="${oIFS}"
+
+pathcomp=''
+
+while [ $# -ne 0 ] ; do
+ pathcomp="${pathcomp}${1}"
+ shift
+
+ if [ ! -d "${pathcomp}" ] ;
+ then
+ $mkdirprog "${pathcomp}"
+ else
+ true
+ fi
+
+ pathcomp="${pathcomp}/"
+done
+fi
+
+if [ x"$dir_arg" != x ]
+then
+ $doit $instcmd $dst &&
+
+ if [ x"$chowncmd" != x ]; then $doit $chowncmd $dst; else true ; fi &&
+ if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dst; else true ; fi &&
+ if [ x"$stripcmd" != x ]; then $doit $stripcmd $dst; else true ; fi &&
+ if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dst; else true ; fi
+else
+
+# If we're going to rename the final executable, determine the name now.
+
+ if [ x"$transformarg" = x ]
+ then
+ dstfile=`basename $dst`
+ else
+ dstfile=`basename $dst $transformbasename |
+ sed $transformarg`$transformbasename
+ fi
+
+# don't allow the sed command to completely eliminate the filename
+
+ if [ x"$dstfile" = x ]
+ then
+ dstfile=`basename $dst`
+ else
+ true
+ fi
+
+# Make a temp file name in the proper directory.
+
+ dsttmp=$dstdir/#inst.$$#
+
+# Move or copy the file name to the temp name
+
+ $doit $instcmd $src $dsttmp &&
+
+ trap "rm -f ${dsttmp}" 0 &&
+
+# and set any options; do chmod last to preserve setuid bits
+
+# If any of these fail, we abort the whole thing. If we want to
+# ignore errors from any of these, just make sure not to ignore
+# errors from the above "$doit $instcmd $src $dsttmp" command.
+
+ if [ x"$chowncmd" != x ]; then $doit $chowncmd $dsttmp; else true;fi &&
+ if [ x"$chgrpcmd" != x ]; then $doit $chgrpcmd $dsttmp; else true;fi &&
+ if [ x"$stripcmd" != x ]; then $doit $stripcmd $dsttmp; else true;fi &&
+ if [ x"$chmodcmd" != x ]; then $doit $chmodcmd $dsttmp; else true;fi &&
+
+# Now rename the file to the real destination.
+
+ $doit $rmcmd -f $dstdir/$dstfile &&
+ $doit $mvcmd $dsttmp $dstdir/$dstfile
+
+fi &&
+
+
+exit 0
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/gnuc.h b/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/gnuc.h
new file mode 100644
index 000000000..96ee36876
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/gnuc.h
@@ -0,0 +1,43 @@
+/* @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/lbl/gnuc.h,v 1.1 1999/08/26 10:11:46 johana Exp $ (LBL) */
+
+/* Define __P() macro, if necessary */
+#ifndef __P
+#if __STDC__
+#define __P(protos) protos
+#else
+#define __P(protos) ()
+#endif
+#endif
+
+/* inline foo */
+#ifdef __GNUC__
+#define inline __inline
+#else
+#define inline
+#endif
+
+/*
+ * Handle new and old "dead" routine prototypes
+ *
+ * For example:
+ *
+ * __dead void foo(void) __attribute__((volatile));
+ *
+ */
+#ifdef __GNUC__
+#ifndef __dead
+#define __dead volatile
+#endif
+#if __GNUC__ < 2 || (__GNUC__ == 2 && __GNUC_MINOR__ < 5)
+#ifndef __attribute__
+#define __attribute__(args)
+#endif
+#endif
+#else
+#ifndef __dead
+#define __dead
+#endif
+#ifndef __attribute__
+#define __attribute__(args)
+#endif
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-solaris2.h b/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-solaris2.h
new file mode 100644
index 000000000..84a4f9931
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-solaris2.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/lbl/os-solaris2.h,v 1.1 1999/08/26 10:11:46 johana Exp $ (LBL)
+ */
+
+/* Prototypes missing in SunOS 5 */
+int daemon(int, int);
+int dn_expand(const u_char *, const u_char *, const u_char *, char *, int);
+int dn_skipname(const u_char *, const u_char *);
+int flock(int, int);
+int getdtablesize(void);
+int gethostname(char *, int);
+int getpagesize(void);
+char *getusershell(void);
+char *getwd(char *);
+int iruserok(u_int, int, char *, char *);
+#ifdef __STDC__
+struct utmp;
+void login(struct utmp *);
+#endif
+int logout(const char *);
+int res_query(const char *, int, int, u_char *, int);
+int setenv(const char *, const char *, int);
+#if defined(_STDIO_H) && defined(HAVE_SETLINEBUF)
+int setlinebuf(FILE *);
+#endif
+int sigblock(int);
+int sigsetmask(int);
+char *strerror(int);
+int snprintf(char *, size_t, const char *, ...);
+int strcasecmp(const char *, const char *);
+void unsetenv(const char *);
+#ifdef __STDC__
+struct timeval;
+#endif
+int utimes(const char *, struct timeval *);
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-sunos4.h b/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-sunos4.h
new file mode 100644
index 000000000..418988d65
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-sunos4.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 1989, 1990, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/lbl/os-sunos4.h,v 1.1 1999/08/26 10:11:46 johana Exp $ (LBL)
+ */
+
+/* Prototypes missing in SunOS 4 */
+#ifdef FILE
+int _filbuf(FILE *);
+int _flsbuf(u_char, FILE *);
+int fclose(FILE *);
+int fflush(FILE *);
+int fgetc(FILE *);
+int fprintf(FILE *, const char *, ...);
+int fputc(int, FILE *);
+int fputs(const char *, FILE *);
+u_int fread(void *, u_int, u_int, FILE *);
+int fseek(FILE *, long, int);
+u_int fwrite(const void *, u_int, u_int, FILE *);
+int pclose(FILE *);
+void rewind(FILE *);
+void setbuf(FILE *, char *);
+int setlinebuf(FILE *);
+int ungetc(int, FILE *);
+int vfprintf(FILE *, const char *, ...);
+int vprintf(const char *, ...);
+#endif
+
+#if __GNUC__ <= 1
+int read(int, char *, u_int);
+int write(int, char *, u_int);
+#endif
+
+long a64l(const char *);
+#ifdef __STDC__
+struct sockaddr;
+#endif
+int accept(int, struct sockaddr *, int *);
+int bind(int, struct sockaddr *, int);
+int bcmp(const void *, const void *, u_int);
+void bcopy(const void *, void *, u_int);
+void bzero(void *, int);
+int chroot(const char *);
+int close(int);
+void closelog(void);
+int connect(int, struct sockaddr *, int);
+char *crypt(const char *, const char *);
+int daemon(int, int);
+int fchmod(int, int);
+int fchown(int, int, int);
+void endgrent(void);
+void endpwent(void);
+void endservent(void);
+#ifdef __STDC__
+struct ether_addr;
+#endif
+struct ether_addr *ether_aton(const char *);
+int flock(int, int);
+#ifdef __STDC__
+struct stat;
+#endif
+int fstat(int, struct stat *);
+#ifdef __STDC__
+struct statfs;
+#endif
+int fstatfs(int, struct statfs *);
+int fsync(int);
+#ifdef __STDC__
+struct timeb;
+#endif
+int ftime(struct timeb *);
+int ftruncate(int, off_t);
+int getdtablesize(void);
+long gethostid(void);
+int gethostname(char *, int);
+int getopt(int, char * const *, const char *);
+int getpagesize(void);
+char *getpass(char *);
+int getpeername(int, struct sockaddr *, int *);
+int getpriority(int, int);
+#ifdef __STDC__
+struct rlimit;
+#endif
+int getrlimit(int, struct rlimit *);
+int getsockname(int, struct sockaddr *, int *);
+int getsockopt(int, int, int, char *, int *);
+#ifdef __STDC__
+struct timeval;
+struct timezone;
+#endif
+int gettimeofday(struct timeval *, struct timezone *);
+char *getusershell(void);
+char *getwd(char *);
+int initgroups(const char *, int);
+int ioctl(int, int, caddr_t);
+int iruserok(u_long, int, char *, char *);
+int isatty(int);
+int killpg(int, int);
+int listen(int, int);
+#ifdef __STDC__
+struct utmp;
+#endif
+void login(struct utmp *);
+int logout(const char *);
+off_t lseek(int, off_t, int);
+int lstat(const char *, struct stat *);
+int mkstemp(char *);
+char *mktemp(char *);
+int munmap(caddr_t, int);
+void openlog(const char *, int, int);
+void perror(const char *);
+int printf(const char *, ...);
+int puts(const char *);
+long random(void);
+int readlink(const char *, char *, int);
+#ifdef __STDC__
+struct iovec;
+#endif
+int readv(int, struct iovec *, int);
+int recv(int, char *, u_int, int);
+int recvfrom(int, char *, u_int, int, struct sockaddr *, int *);
+int rename(const char *, const char *);
+int rcmd(char **, u_short, char *, char *, char *, int *);
+int rresvport(int *);
+int send(int, char *, u_int, int);
+int sendto(int, char *, u_int, int, struct sockaddr *, int);
+int setenv(const char *, const char *, int);
+int seteuid(int);
+int setpriority(int, int, int);
+int select(int, fd_set *, fd_set *, fd_set *, struct timeval *);
+int setpgrp(int, int);
+void setpwent(void);
+int setrlimit(int, struct rlimit *);
+void setservent(int);
+int setsockopt(int, int, int, char *, int);
+int shutdown(int, int);
+int sigblock(int);
+void (*signal (int, void (*) (int))) (int);
+int sigpause(int);
+int sigsetmask(int);
+#ifdef __STDC__
+struct sigvec;
+#endif
+int sigvec(int, struct sigvec *, struct sigvec*);
+int snprintf(char *, size_t, const char *, ...);
+int socket(int, int, int);
+int socketpair(int, int, int, int *);
+int symlink(const char *, const char *);
+void srandom(int);
+int sscanf(char *, const char *, ...);
+int stat(const char *, struct stat *);
+int statfs(char *, struct statfs *);
+char *strerror(int);
+int strcasecmp(const char *, const char *);
+#ifdef __STDC__
+struct tm;
+#endif
+int strftime(char *, int, char *, struct tm *);
+int strncasecmp(const char *, const char *, int);
+long strtol(const char *, char **, int);
+void sync(void);
+void syslog(int, const char *, ...);
+int system(const char *);
+long tell(int);
+time_t time(time_t *);
+char *timezone(int, int);
+int tolower(int);
+int toupper(int);
+int truncate(char *, off_t);
+void unsetenv(const char *);
+int vfork(void);
+int vsprintf(char *, const char *, ...);
+int writev(int, struct iovec *, int);
+#ifdef __STDC__
+struct rusage;
+#endif
+int utimes(const char *, struct timeval *);
+#if __GNUC__ <= 1
+int wait(int *);
+pid_t wait3(int *, int, struct rusage *);
+#endif
+
+/* Ugly signal hacking */
+#ifdef SIG_ERR
+#undef SIG_ERR
+#define SIG_ERR (void (*)(int))-1
+#undef SIG_DFL
+#define SIG_DFL (void (*)(int))0
+#undef SIG_IGN
+#define SIG_IGN (void (*)(int))1
+
+#ifdef KERNEL
+#undef SIG_CATCH
+#define SIG_CATCH (void (*)(int))2
+#endif
+#undef SIG_HOLD
+#define SIG_HOLD (void (*)(int))3
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-ultrix4.h b/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-ultrix4.h
new file mode 100644
index 000000000..80047c7c0
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/lbl/os-ultrix4.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 1990, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/lbl/os-ultrix4.h,v 1.1 1999/08/26 10:11:46 johana Exp $ (LBL)
+ */
+
+/* Prototypes missing in Ultrix 4 */
+int bcmp(const char *, const char *, u_int);
+void bcopy(const void *, void *, u_int);
+void bzero(void *, u_int);
+void endservent(void);
+int getopt(int, char * const *, const char *);
+#ifdef __STDC__
+struct timeval;
+struct timezone;
+#endif
+int gettimeofday(struct timeval *, struct timezone *);
+int ioctl(int, int, caddr_t);
+int pfopen(char *, int);
+int setlinebuf(FILE *);
+int socket(int, int, int);
+int strcasecmp(const char *, const char *);
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/linux-include/netinet/if_ether.h b/package/etrax-tools/src/e100boot/libpcap-0.4/linux-include/netinet/if_ether.h
new file mode 100644
index 000000000..4148ab83e
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/linux-include/netinet/if_ether.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 1982, 1986, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)if_ether.h 8.3 (Berkeley) 5/2/95
+ */
+
+#include <net/if_arp.h>
+
+/*
+ * Ethernet address - 6 octets
+ */
+struct ether_addr {
+ u_char ether_addr_octet[6];
+};
+
+/*
+ * Structure of a 10Mb/s Ethernet header.
+ */
+struct ether_header {
+ u_char ether_dhost[6];
+ u_char ether_shost[6];
+ u_short ether_type;
+};
+
+#define ETHERTYPE_PUP 0x0200 /* PUP protocol */
+#define ETHERTYPE_IP 0x0800 /* IP protocol */
+#define ETHERTYPE_ARP 0x0806 /* Addr. resolution protocol */
+#define ETHERTYPE_REVARP 0x8035 /* reverse Addr. resolution protocol */
+
+/*
+ * The ETHERTYPE_NTRAILER packet types starting at ETHERTYPE_TRAIL have
+ * (type-ETHERTYPE_TRAIL)*512 bytes of data followed
+ * by an ETHER type (as given above) and then the (variable-length) header.
+ */
+#define ETHERTYPE_TRAIL 0x1000 /* Trailer packet */
+#define ETHERTYPE_NTRAILER 16
+
+#define ETHERMTU 1500
+#define ETHERMIN (60-14)
+
+/*
+ * Ethernet Address Resolution Protocol.
+ *
+ * See RFC 826 for protocol description. Structure below is adapted
+ * to resolving internet addresses. Field names used correspond to
+ * RFC 826.
+ */
+struct ether_arp {
+ struct arphdr ea_hdr; /* fixed-size header */
+ u_char arp_sha[6]; /* sender hardware address */
+ u_char arp_spa[4]; /* sender protocol address */
+ u_char arp_tha[6]; /* target hardware address */
+ u_char arp_tpa[4]; /* target protocol address */
+};
+#define arp_hrd ea_hdr.ar_hrd
+#define arp_pro ea_hdr.ar_pro
+#define arp_hln ea_hdr.ar_hln
+#define arp_pln ea_hdr.ar_pln
+#define arp_op ea_hdr.ar_op
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/linux-include/netinet/ip_var.h b/package/etrax-tools/src/e100boot/libpcap-0.4/linux-include/netinet/ip_var.h
new file mode 100644
index 000000000..c528b62fa
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/linux-include/netinet/ip_var.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 1982, 1986, 1993
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the University of
+ * California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#)ip_var.h 8.2 (Berkeley) 1/9/95
+ */
+
+#include <endian.h>
+
+/*
+ * Overlay for ip header used by other protocols (tcp, udp).
+ */
+struct ipovly {
+ caddr_t ih_next, ih_prev; /* for protocol sequence q's */
+ u_char ih_x1; /* (unused) */
+ u_char ih_pr; /* protocol */
+ short ih_len; /* protocol length */
+ struct in_addr ih_src; /* source internet address */
+ struct in_addr ih_dst; /* destination internet address */
+};
+
+/*
+ * Ip reassembly queue structure. Each fragment
+ * being reassembled is attached to one of these structures.
+ * They are timed out after ipq_ttl drops to 0, and may also
+ * be reclaimed if memory becomes tight.
+ */
+struct ipq {
+ struct ipq *next,*prev; /* to other reass headers */
+ u_char ipq_ttl; /* time for reass q to live */
+ u_char ipq_p; /* protocol of this fragment */
+ u_short ipq_id; /* sequence id for reassembly */
+ struct ipasfrag *ipq_next,*ipq_prev;
+ /* to ip headers of fragments */
+ struct in_addr ipq_src,ipq_dst;
+};
+
+/*
+ * Ip header, when holding a fragment.
+ *
+ * Note: ipf_next must be at same offset as ipq_next above
+ */
+struct ipasfrag {
+#if BYTE_ORDER == LITTLE_ENDIAN
+ u_char ip_hl:4,
+ ip_v:4;
+#endif
+#if BYTE_ORDER == BIG_ENDIAN
+ u_char ip_v:4,
+ ip_hl:4;
+#endif
+ u_char ipf_mff; /* XXX overlays ip_tos: use low bit
+ * to avoid destroying tos;
+ * copied from (ip_off&IP_MF) */
+ short ip_len;
+ u_short ip_id;
+ short ip_off;
+ u_char ip_ttl;
+ u_char ip_p;
+ u_short ip_sum;
+ struct ipasfrag *ipf_next; /* next fragment */
+ struct ipasfrag *ipf_prev; /* previous fragment */
+};
+
+/*
+ * Structure stored in mbuf in inpcb.ip_options
+ * and passed to ip_output when ip options are in use.
+ * The actual length of the options (including ipopt_dst)
+ * is in m_len.
+ */
+#define MAX_IPOPTLEN 40
+
+struct ipoption {
+ struct in_addr ipopt_dst; /* first-hop dst if source routed */
+ char ipopt_list[MAX_IPOPTLEN]; /* options proper */
+};
+
+struct ipstat {
+ n_long ips_total; /* total packets received */
+ n_long ips_badsum; /* checksum bad */
+ n_long ips_tooshort; /* packet too short */
+ n_long ips_toosmall; /* not enough data */
+ n_long ips_badhlen; /* ip header length < data size */
+ n_long ips_badlen; /* ip length < ip header length */
+ n_long ips_fragments; /* fragments received */
+ n_long ips_fragdropped; /* frags dropped (dups, out of space) */
+ n_long ips_fragtimeout; /* fragments timed out */
+ n_long ips_forward; /* packets forwarded */
+ n_long ips_cantforward; /* packets rcvd for unreachable dest */
+ n_long ips_redirectsent; /* packets forwarded on same net */
+ n_long ips_noproto; /* unknown or unsupported protocol */
+ n_long ips_delivered; /* datagrams delivered to upper level*/
+ n_long ips_localout; /* total ip packets generated here */
+ n_long ips_odropped; /* lost packets due to nobufs, etc. */
+ n_long ips_reassembled; /* total packets reassembled ok */
+ n_long ips_fragmented; /* datagrams sucessfully fragmented */
+ n_long ips_ofragments; /* output fragments created */
+ n_long ips_cantfrag; /* don't fragment flag was set, etc. */
+ n_long ips_badoptions; /* error in option processing */
+ n_long ips_noroute; /* packets discarded due to no route */
+ n_long ips_badvers; /* ip version != 4 */
+ n_long ips_rawout; /* total raw ip packets generated */
+};
+
+#ifdef KERNEL
+/* flags passed to ip_output as last parameter */
+#define IP_FORWARDING 0x1 /* most of ip header exists */
+#define IP_RAWOUTPUT 0x2 /* raw ip header exists */
+#define IP_ROUTETOIF SO_DONTROUTE /* bypass routing tables */
+#define IP_ALLOWBROADCAST SO_BROADCAST /* can send broadcast packets */
+
+struct ipstat ipstat;
+struct ipq ipq; /* ip reass. queue */
+u_short ip_id; /* ip packet ctr, for ids */
+int ip_defttl; /* default IP ttl */
+
+int in_control __P((struct socket *, n_long, caddr_t, struct ifnet *));
+int ip_ctloutput __P((int, struct socket *, int, int, struct mbuf **));
+void ip_deq __P((struct ipasfrag *));
+int ip_dooptions __P((struct mbuf *));
+void ip_drain __P((void));
+void ip_enq __P((struct ipasfrag *, struct ipasfrag *));
+void ip_forward __P((struct mbuf *, int));
+void ip_freef __P((struct ipq *));
+void ip_freemoptions __P((struct ip_moptions *));
+int ip_getmoptions __P((int, struct ip_moptions *, struct mbuf **));
+void ip_init __P((void));
+int ip_mforward __P((struct mbuf *, struct ifnet *));
+int ip_optcopy __P((struct ip *, struct ip *));
+int ip_output __P((struct mbuf *,
+ struct mbuf *, struct route *, int, struct ip_moptions *));
+int ip_pcbopts __P((struct mbuf **, struct mbuf *));
+struct ip *
+ ip_reass __P((struct ipasfrag *, struct ipq *));
+struct in_ifaddr *
+ ip_rtaddr __P((struct in_addr));
+int ip_setmoptions __P((int, struct ip_moptions **, struct mbuf *));
+void ip_slowtimo __P((void));
+struct mbuf *
+ ip_srcroute __P((void));
+void ip_stripoptions __P((struct mbuf *, struct mbuf *));
+int ip_sysctl __P((int *, n_long, void *, size_t *, void *, size_t));
+void ipintr __P((void));
+int rip_ctloutput __P((int, struct socket *, int, int, struct mbuf **));
+void rip_init __P((void));
+void rip_input __P((struct mbuf *));
+int rip_output __P((struct mbuf *, struct socket *, n_long));
+int rip_usrreq __P((struct socket *,
+ int, struct mbuf *, struct mbuf *, struct mbuf *));
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/mkdep b/package/etrax-tools/src/e100boot/libpcap-0.4/mkdep
new file mode 100755
index 000000000..2a9c221b1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/mkdep
@@ -0,0 +1,109 @@
+#!/bin/sh -
+#
+# Copyright (c) 1994, 1996
+# The Regents of the University of California. All rights reserved.
+#
+# Redistribution and use in source and binary forms are permitted
+# provided that this notice is preserved and that due credit is given
+# to the University of California at Berkeley. The name of the University
+# may not be used to endorse or promote products derived from this
+# software without specific prior written permission. This software
+# is provided ``as is'' without express or implied warranty.
+#
+# @(#)mkdep.sh 5.11 (Berkeley) 5/5/88
+#
+
+PATH=/bin:/usr/bin:/usr/ucb:/usr/local:/usr/local/bin
+export PATH
+
+MAKE=Makefile # default makefile name is "Makefile"
+CC=cc # default C compiler is "cc"
+
+while :
+ do case "$1" in
+ # -c allows you to specify the C compiler
+ -c)
+ CC=$2
+ shift; shift ;;
+
+ # -f allows you to select a makefile name
+ -f)
+ MAKE=$2
+ shift; shift ;;
+
+ # the -p flag produces "program: program.c" style dependencies
+ # so .o's don't get produced
+ -p)
+ SED='s;\.o;;'
+ shift ;;
+ *)
+ break ;;
+ esac
+done
+
+if [ $# = 0 ] ; then
+ echo 'usage: mkdep [-p] [-c cc] [-f makefile] [flags] file ...'
+ exit 1
+fi
+
+if [ ! -w $MAKE ]; then
+ echo "mkdep: no writeable file \"$MAKE\""
+ exit 1
+fi
+
+TMP=/tmp/mkdep$$
+
+trap 'rm -f $TMP ; exit 1' 1 2 3 13 15
+
+cp $MAKE ${MAKE}.bak
+
+sed -e '/DO NOT DELETE THIS LINE/,$d' < $MAKE > $TMP
+
+cat << _EOF_ >> $TMP
+# DO NOT DELETE THIS LINE -- mkdep uses it.
+# DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY.
+
+_EOF_
+
+# If your compiler doesn't have -M, add it. If you can't, the next two
+# lines will try and replace the "cc -M". The real problem is that this
+# hack can't deal with anything that requires a search path, and doesn't
+# even try for anything using bracket (<>) syntax.
+#
+# egrep '^#include[ ]*".*"' /dev/null $* |
+# sed -e 's/:[^"]*"\([^"]*\)".*/: \1/' -e 's/\.c/.o/' |
+
+# XXX this doesn't work with things like "-DDECLWAITSTATUS=union\ wait"
+$CC -M $* |
+sed "
+ s; \./; ;g
+ $SED" |
+awk '{
+ if ($1 != prev) {
+ if (rec != "")
+ print rec;
+ rec = $0;
+ prev = $1;
+ }
+ else {
+ if (length(rec $2) > 78) {
+ print rec;
+ rec = $0;
+ }
+ else
+ rec = rec " " $2
+ }
+}
+END {
+ print rec
+}' >> $TMP
+
+cat << _EOF_ >> $TMP
+
+# IF YOU PUT ANYTHING HERE IT WILL GO AWAY
+_EOF_
+
+# copy to preserve permissions
+cp $TMP $MAKE
+rm -f ${MAKE}.bak $TMP
+exit 0
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/nametoaddr.c b/package/etrax-tools/src/e100boot/libpcap-0.4/nametoaddr.c
new file mode 100644
index 000000000..f57f34eb0
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/nametoaddr.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Name to id translation routines used by the scanner.
+ * These functions are not time critical.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/nametoaddr.c,v 1.1 1999/08/26 10:05:23 johana Exp $ (LBL)";
+#endif
+
+#include <sys/param.h>
+#include <sys/types.h> /* concession to AIX */
+#include <sys/socket.h>
+#include <sys/time.h>
+
+#if __STDC__
+struct mbuf;
+struct rtentry;
+#endif
+
+#include <net/if.h>
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+#include <arpa/inet.h>
+
+#include <ctype.h>
+#include <errno.h>
+#include <stdlib.h>
+#include <memory.h>
+#include <netdb.h>
+#include <stdio.h>
+
+#include "pcap-int.h"
+
+#include "gencode.h"
+#include <pcap-namedb.h>
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#ifndef NTOHL
+#define NTOHL(x) (x) = ntohl(x)
+#define NTOHS(x) (x) = ntohs(x)
+#endif
+
+static inline int xdtoi(int);
+
+/*
+ * Convert host name to internet address.
+ * Return 0 upon failure.
+ */
+bpf_u_int32 **
+pcap_nametoaddr(const char *name)
+{
+#ifndef h_addr
+ static bpf_u_int32 *hlist[2];
+#endif
+ bpf_u_int32 **p;
+ struct hostent *hp;
+
+ if ((hp = gethostbyname(name)) != NULL) {
+#ifndef h_addr
+ hlist[0] = (bpf_u_int32 *)hp->h_addr;
+ NTOHL(hp->h_addr);
+ return hlist;
+#else
+ for (p = (bpf_u_int32 **)hp->h_addr_list; *p; ++p)
+ NTOHL(**p);
+ return (bpf_u_int32 **)hp->h_addr_list;
+#endif
+ }
+ else
+ return 0;
+}
+
+/*
+ * Convert net name to internet address.
+ * Return 0 upon failure.
+ */
+bpf_u_int32
+pcap_nametonetaddr(const char *name)
+{
+ struct netent *np;
+
+ if ((np = getnetbyname(name)) != NULL)
+ return np->n_net;
+ else
+ return 0;
+}
+
+/*
+ * Convert a port name to its port and protocol numbers.
+ * We assume only TCP or UDP.
+ * Return 0 upon failure.
+ */
+int
+pcap_nametoport(const char *name, int *port, int *proto)
+{
+ struct servent *sp;
+ char *other;
+
+ sp = getservbyname(name, (char *)0);
+ if (sp != NULL) {
+ NTOHS(sp->s_port);
+ *port = sp->s_port;
+ *proto = pcap_nametoproto(sp->s_proto);
+ /*
+ * We need to check /etc/services for ambiguous entries.
+ * If we find the ambiguous entry, and it has the
+ * same port number, change the proto to PROTO_UNDEF
+ * so both TCP and UDP will be checked.
+ */
+ if (*proto == IPPROTO_TCP)
+ other = "udp";
+ else
+ other = "tcp";
+
+ sp = getservbyname(name, other);
+ if (sp != 0) {
+ NTOHS(sp->s_port);
+#ifdef notdef
+ if (*port != sp->s_port)
+ /* Can't handle ambiguous names that refer
+ to different port numbers. */
+ warning("ambiguous port %s in /etc/services",
+ name);
+#endif
+ *proto = PROTO_UNDEF;
+ }
+ return 1;
+ }
+#if defined(ultrix) || defined(__osf__)
+ /* Special hack in case NFS isn't in /etc/services */
+ if (strcmp(name, "nfs") == 0) {
+ *port = 2049;
+ *proto = PROTO_UNDEF;
+ return 1;
+ }
+#endif
+ return 0;
+}
+
+int
+pcap_nametoproto(const char *str)
+{
+ struct protoent *p;
+
+ p = getprotobyname(str);
+ if (p != 0)
+ return p->p_proto;
+ else
+ return PROTO_UNDEF;
+}
+
+#include "ethertype.h"
+
+struct eproto {
+ char *s;
+ u_short p;
+};
+
+/* Static data base of ether protocol types. */
+struct eproto eproto_db[] = {
+ { "pup", ETHERTYPE_PUP },
+ { "xns", ETHERTYPE_NS },
+ { "ip", ETHERTYPE_IP },
+ { "arp", ETHERTYPE_ARP },
+ { "rarp", ETHERTYPE_REVARP },
+ { "sprite", ETHERTYPE_SPRITE },
+ { "mopdl", ETHERTYPE_MOPDL },
+ { "moprc", ETHERTYPE_MOPRC },
+ { "decnet", ETHERTYPE_DN },
+ { "lat", ETHERTYPE_LAT },
+ { "sca", ETHERTYPE_SCA },
+ { "lanbridge", ETHERTYPE_LANBRIDGE },
+ { "vexp", ETHERTYPE_VEXP },
+ { "vprod", ETHERTYPE_VPROD },
+ { "atalk", ETHERTYPE_ATALK },
+ { "atalkarp", ETHERTYPE_AARP },
+ { "loopback", ETHERTYPE_LOOPBACK },
+ { "decdts", ETHERTYPE_DECDTS },
+ { "decdns", ETHERTYPE_DECDNS },
+ { (char *)0, 0 }
+};
+
+int
+pcap_nametoeproto(const char *s)
+{
+ struct eproto *p = eproto_db;
+
+ while (p->s != 0) {
+ if (strcmp(p->s, s) == 0)
+ return p->p;
+ p += 1;
+ }
+ return PROTO_UNDEF;
+}
+
+/* Hex digit to integer. */
+static inline int
+xdtoi(c)
+ register int c;
+{
+ if (isdigit(c))
+ return c - '0';
+ else if (islower(c))
+ return c - 'a' + 10;
+ else
+ return c - 'A' + 10;
+}
+
+int
+__pcap_atoin(const char *s, bpf_u_int32 *addr)
+{
+ u_int n;
+ int len;
+
+ *addr = 0;
+ len = 0;
+ while (1) {
+ n = 0;
+ while (*s && *s != '.')
+ n = n * 10 + *s++ - '0';
+ *addr <<= 8;
+ *addr |= n & 0xff;
+ len += 8;
+ if (*s == '\0')
+ return len;
+ ++s;
+ }
+ /* NOTREACHED */
+}
+
+int
+__pcap_atodn(const char *s, bpf_u_int32 *addr)
+{
+#define AREASHIFT 10
+#define AREAMASK 0176000
+#define NODEMASK 01777
+
+ u_int node, area;
+
+ if (sscanf((char *)s, "%d.%d", &area, &node) != 2)
+ bpf_error("malformed decnet address '%s'", s);
+
+ *addr = (area << AREASHIFT) & AREAMASK;
+ *addr |= (node & NODEMASK);
+
+ return(32);
+}
+
+/*
+ * Convert 's' which has the form "xx:xx:xx:xx:xx:xx" into a new
+ * ethernet address. Assumes 's' is well formed.
+ */
+u_char *
+pcap_ether_aton(const char *s)
+{
+ register u_char *ep, *e;
+ register u_int d;
+
+ e = ep = (u_char *)malloc(6);
+
+ while (*s) {
+ if (*s == ':')
+ s += 1;
+ d = xdtoi(*s++);
+ if (isxdigit(*s)) {
+ d <<= 4;
+ d |= xdtoi(*s++);
+ }
+ *ep++ = d;
+ }
+
+ return (e);
+}
+
+#ifndef HAVE_ETHER_HOSTTON
+/* Roll our own */
+u_char *
+pcap_ether_hostton(const char *name)
+{
+ register struct pcap_etherent *ep;
+ register u_char *ap;
+ static FILE *fp = NULL;
+ static init = 0;
+
+ if (!init) {
+ fp = fopen(PCAP_ETHERS_FILE, "r");
+ ++init;
+ if (fp == NULL)
+ return (NULL);
+ } else if (fp == NULL)
+ return (NULL);
+ else
+ rewind(fp);
+
+ while ((ep = pcap_next_etherent(fp)) != NULL) {
+ if (strcmp(ep->name, name) == 0) {
+ ap = (u_char *)malloc(6);
+ if (ap != NULL) {
+ memcpy(ap, ep->addr, 6);
+ return (ap);
+ }
+ break;
+ }
+ }
+ return (NULL);
+}
+#else
+
+#ifndef sgi
+extern int ether_hostton(char *, struct ether_addr *);
+#endif
+
+/* Use the os supplied routines */
+u_char *
+pcap_ether_hostton(const char *name)
+{
+ register u_char *ap;
+ u_char a[6];
+
+ ap = NULL;
+ if (ether_hostton((char *)name, (struct ether_addr *)a) == 0) {
+ ap = (u_char *)malloc(6);
+ if (ap != NULL)
+ memcpy((char *)ap, (char *)a, 6);
+ }
+ return (ap);
+}
+#endif
+
+u_short
+__pcap_nametodnaddr(const char *name)
+{
+#ifdef DECNETLIB
+ struct nodeent *getnodebyname();
+ struct nodeent *nep;
+ unsigned short res;
+
+ nep = getnodebyname(name);
+ if (nep == ((struct nodeent *)0))
+ bpf_error("unknown decnet host name '%s'\n", name);
+
+ memcpy((char *)&res, (char *)nep->n_addr, sizeof(unsigned short));
+ return(res);
+#else
+ bpf_error("decnet name support not included, '%s' cannot be translated\n",
+ name);
+#endif
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/net b/package/etrax-tools/src/e100boot/libpcap-0.4/net
new file mode 120000
index 000000000..0cc773fc4
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/net
@@ -0,0 +1 @@
+bpf/net \ No newline at end of file
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/optimize.c b/package/etrax-tools/src/e100boot/libpcap-0.4/optimize.c
new file mode 100644
index 000000000..43d07d9da
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/optimize.c
@@ -0,0 +1,2004 @@
+/*
+ * Copyright (c) 1988, 1989, 1990, 1991, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Optimization module for tcpdump intermediate representation.
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/optimize.c,v 1.1 1999/08/26 10:05:23 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <memory.h>
+
+#include "pcap-int.h"
+
+#include "gencode.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#ifdef BDEBUG
+extern int dflag;
+#endif
+
+#define A_ATOM BPF_MEMWORDS
+#define X_ATOM (BPF_MEMWORDS+1)
+
+#define NOP -1
+
+/*
+ * This define is used to represent *both* the accumulator and
+ * x register in use-def computations.
+ * Currently, the use-def code assumes only one definition per instruction.
+ */
+#define AX_ATOM N_ATOMS
+
+/*
+ * A flag to indicate that further optimization is needed.
+ * Iterative passes are continued until a given pass yields no
+ * branch movement.
+ */
+static int done;
+
+/*
+ * A block is marked if only if its mark equals the current mark.
+ * Rather than traverse the code array, marking each item, 'cur_mark' is
+ * incremented. This automatically makes each element unmarked.
+ */
+static int cur_mark;
+#define isMarked(p) ((p)->mark == cur_mark)
+#define unMarkAll() cur_mark += 1
+#define Mark(p) ((p)->mark = cur_mark)
+
+static void opt_init(struct block *);
+static void opt_cleanup(void);
+
+static void make_marks(struct block *);
+static void mark_code(struct block *);
+
+static void intern_blocks(struct block *);
+
+static int eq_slist(struct slist *, struct slist *);
+
+static void find_levels_r(struct block *);
+
+static void find_levels(struct block *);
+static void find_dom(struct block *);
+static void propedom(struct edge *);
+static void find_edom(struct block *);
+static void find_closure(struct block *);
+static int atomuse(struct stmt *);
+static int atomdef(struct stmt *);
+static void compute_local_ud(struct block *);
+static void find_ud(struct block *);
+static void init_val(void);
+static int F(int, int, int);
+static inline void vstore(struct stmt *, int *, int, int);
+static void opt_blk(struct block *, int);
+static int use_conflict(struct block *, struct block *);
+static void opt_j(struct edge *);
+static void or_pullup(struct block *);
+static void and_pullup(struct block *);
+static void opt_blks(struct block *, int);
+static inline void link_inedge(struct edge *, struct block *);
+static void find_inedges(struct block *);
+static void opt_root(struct block **);
+static void opt_loop(struct block *, int);
+static void fold_op(struct stmt *, int, int);
+static inline struct slist *this_op(struct slist *);
+static void opt_not(struct block *);
+static void opt_peep(struct block *);
+static void opt_stmt(struct stmt *, int[], int);
+static void deadstmt(struct stmt *, struct stmt *[]);
+static void opt_deadstores(struct block *);
+static void opt_blk(struct block *, int);
+static int use_conflict(struct block *, struct block *);
+static void opt_j(struct edge *);
+static struct block *fold_edge(struct block *, struct edge *);
+static inline int eq_blk(struct block *, struct block *);
+static int slength(struct slist *);
+static int count_blocks(struct block *);
+static void number_blks_r(struct block *);
+static int count_stmts(struct block *);
+static int convert_code_r(struct block *);
+#ifdef BDEBUG
+static void opt_dump(struct block *);
+#endif
+
+static int n_blocks;
+struct block **blocks;
+static int n_edges;
+struct edge **edges;
+
+/*
+ * A bit vector set representation of the dominators.
+ * We round up the set size to the next power of two.
+ */
+static int nodewords;
+static int edgewords;
+struct block **levels;
+bpf_u_int32 *space;
+#define BITS_PER_WORD (8*sizeof(bpf_u_int32))
+/*
+ * True if a is in uset {p}
+ */
+#define SET_MEMBER(p, a) \
+((p)[(unsigned)(a) / BITS_PER_WORD] & (1 << ((unsigned)(a) % BITS_PER_WORD)))
+
+/*
+ * Add 'a' to uset p.
+ */
+#define SET_INSERT(p, a) \
+(p)[(unsigned)(a) / BITS_PER_WORD] |= (1 << ((unsigned)(a) % BITS_PER_WORD))
+
+/*
+ * Delete 'a' from uset p.
+ */
+#define SET_DELETE(p, a) \
+(p)[(unsigned)(a) / BITS_PER_WORD] &= ~(1 << ((unsigned)(a) % BITS_PER_WORD))
+
+/*
+ * a := a intersect b
+ */
+#define SET_INTERSECT(a, b, n)\
+{\
+ register bpf_u_int32 *_x = a, *_y = b;\
+ register int _n = n;\
+ while (--_n >= 0) *_x++ &= *_y++;\
+}
+
+/*
+ * a := a - b
+ */
+#define SET_SUBTRACT(a, b, n)\
+{\
+ register bpf_u_int32 *_x = a, *_y = b;\
+ register int _n = n;\
+ while (--_n >= 0) *_x++ &=~ *_y++;\
+}
+
+/*
+ * a := a union b
+ */
+#define SET_UNION(a, b, n)\
+{\
+ register bpf_u_int32 *_x = a, *_y = b;\
+ register int _n = n;\
+ while (--_n >= 0) *_x++ |= *_y++;\
+}
+
+static uset all_dom_sets;
+static uset all_closure_sets;
+static uset all_edge_sets;
+
+#ifndef MAX
+#define MAX(a,b) ((a)>(b)?(a):(b))
+#endif
+
+static void
+find_levels_r(b)
+ struct block *b;
+{
+ int level;
+
+ if (isMarked(b))
+ return;
+
+ Mark(b);
+ b->link = 0;
+
+ if (JT(b)) {
+ find_levels_r(JT(b));
+ find_levels_r(JF(b));
+ level = MAX(JT(b)->level, JF(b)->level) + 1;
+ } else
+ level = 0;
+ b->level = level;
+ b->link = levels[level];
+ levels[level] = b;
+}
+
+/*
+ * Level graph. The levels go from 0 at the leaves to
+ * N_LEVELS at the root. The levels[] array points to the
+ * first node of the level list, whose elements are linked
+ * with the 'link' field of the struct block.
+ */
+static void
+find_levels(root)
+ struct block *root;
+{
+ memset((char *)levels, 0, n_blocks * sizeof(*levels));
+ unMarkAll();
+ find_levels_r(root);
+}
+
+/*
+ * Find dominator relationships.
+ * Assumes graph has been leveled.
+ */
+static void
+find_dom(root)
+ struct block *root;
+{
+ int i;
+ struct block *b;
+ bpf_u_int32 *x;
+
+ /*
+ * Initialize sets to contain all nodes.
+ */
+ x = all_dom_sets;
+ i = n_blocks * nodewords;
+ while (--i >= 0)
+ *x++ = ~0;
+ /* Root starts off empty. */
+ for (i = nodewords; --i >= 0;)
+ root->dom[i] = 0;
+
+ /* root->level is the highest level no found. */
+ for (i = root->level; i >= 0; --i) {
+ for (b = levels[i]; b; b = b->link) {
+ SET_INSERT(b->dom, b->id);
+ if (JT(b) == 0)
+ continue;
+ SET_INTERSECT(JT(b)->dom, b->dom, nodewords);
+ SET_INTERSECT(JF(b)->dom, b->dom, nodewords);
+ }
+ }
+}
+
+static void
+propedom(ep)
+ struct edge *ep;
+{
+ SET_INSERT(ep->edom, ep->id);
+ if (ep->succ) {
+ SET_INTERSECT(ep->succ->et.edom, ep->edom, edgewords);
+ SET_INTERSECT(ep->succ->ef.edom, ep->edom, edgewords);
+ }
+}
+
+/*
+ * Compute edge dominators.
+ * Assumes graph has been leveled and predecessors established.
+ */
+static void
+find_edom(root)
+ struct block *root;
+{
+ int i;
+ uset x;
+ struct block *b;
+
+ x = all_edge_sets;
+ for (i = n_edges * edgewords; --i >= 0; )
+ x[i] = ~0;
+
+ /* root->level is the highest level no found. */
+ memset(root->et.edom, 0, edgewords * sizeof(*(uset)0));
+ memset(root->ef.edom, 0, edgewords * sizeof(*(uset)0));
+ for (i = root->level; i >= 0; --i) {
+ for (b = levels[i]; b != 0; b = b->link) {
+ propedom(&b->et);
+ propedom(&b->ef);
+ }
+ }
+}
+
+/*
+ * Find the backwards transitive closure of the flow graph. These sets
+ * are backwards in the sense that we find the set of nodes that reach
+ * a given node, not the set of nodes that can be reached by a node.
+ *
+ * Assumes graph has been leveled.
+ */
+static void
+find_closure(root)
+ struct block *root;
+{
+ int i;
+ struct block *b;
+
+ /*
+ * Initialize sets to contain no nodes.
+ */
+ memset((char *)all_closure_sets, 0,
+ n_blocks * nodewords * sizeof(*all_closure_sets));
+
+ /* root->level is the highest level no found. */
+ for (i = root->level; i >= 0; --i) {
+ for (b = levels[i]; b; b = b->link) {
+ SET_INSERT(b->closure, b->id);
+ if (JT(b) == 0)
+ continue;
+ SET_UNION(JT(b)->closure, b->closure, nodewords);
+ SET_UNION(JF(b)->closure, b->closure, nodewords);
+ }
+ }
+}
+
+/*
+ * Return the register number that is used by s. If A and X are both
+ * used, return AX_ATOM. If no register is used, return -1.
+ *
+ * The implementation should probably change to an array access.
+ */
+static int
+atomuse(s)
+ struct stmt *s;
+{
+ register int c = s->code;
+
+ if (c == NOP)
+ return -1;
+
+ switch (BPF_CLASS(c)) {
+
+ case BPF_RET:
+ return (BPF_RVAL(c) == BPF_A) ? A_ATOM :
+ (BPF_RVAL(c) == BPF_X) ? X_ATOM : -1;
+
+ case BPF_LD:
+ case BPF_LDX:
+ return (BPF_MODE(c) == BPF_IND) ? X_ATOM :
+ (BPF_MODE(c) == BPF_MEM) ? s->k : -1;
+
+ case BPF_ST:
+ return A_ATOM;
+
+ case BPF_STX:
+ return X_ATOM;
+
+ case BPF_JMP:
+ case BPF_ALU:
+ if (BPF_SRC(c) == BPF_X)
+ return AX_ATOM;
+ return A_ATOM;
+
+ case BPF_MISC:
+ return BPF_MISCOP(c) == BPF_TXA ? X_ATOM : A_ATOM;
+ }
+ abort();
+ /* NOTREACHED */
+}
+
+/*
+ * Return the register number that is defined by 's'. We assume that
+ * a single stmt cannot define more than one register. If no register
+ * is defined, return -1.
+ *
+ * The implementation should probably change to an array access.
+ */
+static int
+atomdef(s)
+ struct stmt *s;
+{
+ if (s->code == NOP)
+ return -1;
+
+ switch (BPF_CLASS(s->code)) {
+
+ case BPF_LD:
+ case BPF_ALU:
+ return A_ATOM;
+
+ case BPF_LDX:
+ return X_ATOM;
+
+ case BPF_ST:
+ case BPF_STX:
+ return s->k;
+
+ case BPF_MISC:
+ return BPF_MISCOP(s->code) == BPF_TAX ? X_ATOM : A_ATOM;
+ }
+ return -1;
+}
+
+static void
+compute_local_ud(b)
+ struct block *b;
+{
+ struct slist *s;
+ atomset def = 0, use = 0, kill = 0;
+ int atom;
+
+ for (s = b->stmts; s; s = s->next) {
+ if (s->s.code == NOP)
+ continue;
+ atom = atomuse(&s->s);
+ if (atom >= 0) {
+ if (atom == AX_ATOM) {
+ if (!ATOMELEM(def, X_ATOM))
+ use |= ATOMMASK(X_ATOM);
+ if (!ATOMELEM(def, A_ATOM))
+ use |= ATOMMASK(A_ATOM);
+ }
+ else if (atom < N_ATOMS) {
+ if (!ATOMELEM(def, atom))
+ use |= ATOMMASK(atom);
+ }
+ else
+ abort();
+ }
+ atom = atomdef(&s->s);
+ if (atom >= 0) {
+ if (!ATOMELEM(use, atom))
+ kill |= ATOMMASK(atom);
+ def |= ATOMMASK(atom);
+ }
+ }
+ if (!ATOMELEM(def, A_ATOM) && BPF_CLASS(b->s.code) == BPF_JMP)
+ use |= ATOMMASK(A_ATOM);
+
+ b->def = def;
+ b->kill = kill;
+ b->in_use = use;
+}
+
+/*
+ * Assume graph is already leveled.
+ */
+static void
+find_ud(root)
+ struct block *root;
+{
+ int i, maxlevel;
+ struct block *p;
+
+ /*
+ * root->level is the highest level no found;
+ * count down from there.
+ */
+ maxlevel = root->level;
+ for (i = maxlevel; i >= 0; --i)
+ for (p = levels[i]; p; p = p->link) {
+ compute_local_ud(p);
+ p->out_use = 0;
+ }
+
+ for (i = 1; i <= maxlevel; ++i) {
+ for (p = levels[i]; p; p = p->link) {
+ p->out_use |= JT(p)->in_use | JF(p)->in_use;
+ p->in_use |= p->out_use &~ p->kill;
+ }
+ }
+}
+
+/*
+ * These data structures are used in a Cocke and Shwarz style
+ * value numbering scheme. Since the flowgraph is acyclic,
+ * exit values can be propagated from a node's predecessors
+ * provided it is uniquely defined.
+ */
+struct valnode {
+ int code;
+ int v0, v1;
+ int val;
+ struct valnode *next;
+};
+
+#define MODULUS 213
+static struct valnode *hashtbl[MODULUS];
+static int curval;
+static int maxval;
+
+/* Integer constants mapped with the load immediate opcode. */
+#define K(i) F(BPF_LD|BPF_IMM|BPF_W, i, 0L)
+
+struct vmapinfo {
+ int is_const;
+ bpf_int32 const_val;
+};
+
+struct vmapinfo *vmap;
+struct valnode *vnode_base;
+struct valnode *next_vnode;
+
+static void
+init_val()
+{
+ curval = 0;
+ next_vnode = vnode_base;
+ memset((char *)vmap, 0, maxval * sizeof(*vmap));
+ memset((char *)hashtbl, 0, sizeof hashtbl);
+}
+
+/* Because we really don't have an IR, this stuff is a little messy. */
+static int
+F(code, v0, v1)
+ int code;
+ int v0, v1;
+{
+ u_int hash;
+ int val;
+ struct valnode *p;
+
+ hash = (u_int)code ^ (v0 << 4) ^ (v1 << 8);
+ hash %= MODULUS;
+
+ for (p = hashtbl[hash]; p; p = p->next)
+ if (p->code == code && p->v0 == v0 && p->v1 == v1)
+ return p->val;
+
+ val = ++curval;
+ if (BPF_MODE(code) == BPF_IMM &&
+ (BPF_CLASS(code) == BPF_LD || BPF_CLASS(code) == BPF_LDX)) {
+ vmap[val].const_val = v0;
+ vmap[val].is_const = 1;
+ }
+ p = next_vnode++;
+ p->val = val;
+ p->code = code;
+ p->v0 = v0;
+ p->v1 = v1;
+ p->next = hashtbl[hash];
+ hashtbl[hash] = p;
+
+ return val;
+}
+
+static inline void
+vstore(s, valp, newval, alter)
+ struct stmt *s;
+ int *valp;
+ int newval;
+ int alter;
+{
+ if (alter && *valp == newval)
+ s->code = NOP;
+ else
+ *valp = newval;
+}
+
+static void
+fold_op(s, v0, v1)
+ struct stmt *s;
+ int v0, v1;
+{
+ bpf_int32 a, b;
+
+ a = vmap[v0].const_val;
+ b = vmap[v1].const_val;
+
+ switch (BPF_OP(s->code)) {
+ case BPF_ADD:
+ a += b;
+ break;
+
+ case BPF_SUB:
+ a -= b;
+ break;
+
+ case BPF_MUL:
+ a *= b;
+ break;
+
+ case BPF_DIV:
+ if (b == 0)
+ bpf_error("division by zero");
+ a /= b;
+ break;
+
+ case BPF_AND:
+ a &= b;
+ break;
+
+ case BPF_OR:
+ a |= b;
+ break;
+
+ case BPF_LSH:
+ a <<= b;
+ break;
+
+ case BPF_RSH:
+ a >>= b;
+ break;
+
+ case BPF_NEG:
+ a = -a;
+ break;
+
+ default:
+ abort();
+ }
+ s->k = a;
+ s->code = BPF_LD|BPF_IMM;
+ done = 0;
+}
+
+static inline struct slist *
+this_op(s)
+ struct slist *s;
+{
+ while (s != 0 && s->s.code == NOP)
+ s = s->next;
+ return s;
+}
+
+static void
+opt_not(b)
+ struct block *b;
+{
+ struct block *tmp = JT(b);
+
+ JT(b) = JF(b);
+ JF(b) = tmp;
+}
+
+static void
+opt_peep(b)
+ struct block *b;
+{
+ struct slist *s;
+ struct slist *next, *last;
+ int val;
+
+ s = b->stmts;
+ if (s == 0)
+ return;
+
+ last = s;
+ while (1) {
+ s = this_op(s);
+ if (s == 0)
+ break;
+ next = this_op(s->next);
+ if (next == 0)
+ break;
+ last = next;
+
+ /*
+ * st M[k] --> st M[k]
+ * ldx M[k] tax
+ */
+ if (s->s.code == BPF_ST &&
+ next->s.code == (BPF_LDX|BPF_MEM) &&
+ s->s.k == next->s.k) {
+ done = 0;
+ next->s.code = BPF_MISC|BPF_TAX;
+ }
+ /*
+ * ld #k --> ldx #k
+ * tax txa
+ */
+ if (s->s.code == (BPF_LD|BPF_IMM) &&
+ next->s.code == (BPF_MISC|BPF_TAX)) {
+ s->s.code = BPF_LDX|BPF_IMM;
+ next->s.code = BPF_MISC|BPF_TXA;
+ done = 0;
+ }
+ /*
+ * This is an ugly special case, but it happens
+ * when you say tcp[k] or udp[k] where k is a constant.
+ */
+ if (s->s.code == (BPF_LD|BPF_IMM)) {
+ struct slist *add, *tax, *ild;
+
+ /*
+ * Check that X isn't used on exit from this
+ * block (which the optimizer might cause).
+ * We know the code generator won't generate
+ * any local dependencies.
+ */
+ if (ATOMELEM(b->out_use, X_ATOM))
+ break;
+
+ if (next->s.code != (BPF_LDX|BPF_MSH|BPF_B))
+ add = next;
+ else
+ add = this_op(next->next);
+ if (add == 0 || add->s.code != (BPF_ALU|BPF_ADD|BPF_X))
+ break;
+
+ tax = this_op(add->next);
+ if (tax == 0 || tax->s.code != (BPF_MISC|BPF_TAX))
+ break;
+
+ ild = this_op(tax->next);
+ if (ild == 0 || BPF_CLASS(ild->s.code) != BPF_LD ||
+ BPF_MODE(ild->s.code) != BPF_IND)
+ break;
+ /*
+ * XXX We need to check that X is not
+ * subsequently used. We know we can eliminate the
+ * accumulator modifications since it is defined
+ * by the last stmt of this sequence.
+ *
+ * We want to turn this sequence:
+ *
+ * (004) ldi #0x2 {s}
+ * (005) ldxms [14] {next} -- optional
+ * (006) addx {add}
+ * (007) tax {tax}
+ * (008) ild [x+0] {ild}
+ *
+ * into this sequence:
+ *
+ * (004) nop
+ * (005) ldxms [14]
+ * (006) nop
+ * (007) nop
+ * (008) ild [x+2]
+ *
+ */
+ ild->s.k += s->s.k;
+ s->s.code = NOP;
+ add->s.code = NOP;
+ tax->s.code = NOP;
+ done = 0;
+ }
+ s = next;
+ }
+ /*
+ * If we have a subtract to do a comparison, and the X register
+ * is a known constant, we can merge this value into the
+ * comparison.
+ */
+ if (last->s.code == (BPF_ALU|BPF_SUB|BPF_X) &&
+ !ATOMELEM(b->out_use, A_ATOM)) {
+ val = b->val[X_ATOM];
+ if (vmap[val].is_const) {
+ int op;
+
+ b->s.k += vmap[val].const_val;
+ op = BPF_OP(b->s.code);
+ if (op == BPF_JGT || op == BPF_JGE) {
+ struct block *t = JT(b);
+ JT(b) = JF(b);
+ JF(b) = t;
+ b->s.k += 0x80000000;
+ }
+ last->s.code = NOP;
+ done = 0;
+ } else if (b->s.k == 0) {
+ /*
+ * sub x -> nop
+ * j #0 j x
+ */
+ last->s.code = NOP;
+ b->s.code = BPF_CLASS(b->s.code) | BPF_OP(b->s.code) |
+ BPF_X;
+ done = 0;
+ }
+ }
+ /*
+ * Likewise, a constant subtract can be simplified.
+ */
+ else if (last->s.code == (BPF_ALU|BPF_SUB|BPF_K) &&
+ !ATOMELEM(b->out_use, A_ATOM)) {
+ int op;
+
+ b->s.k += last->s.k;
+ last->s.code = NOP;
+ op = BPF_OP(b->s.code);
+ if (op == BPF_JGT || op == BPF_JGE) {
+ struct block *t = JT(b);
+ JT(b) = JF(b);
+ JF(b) = t;
+ b->s.k += 0x80000000;
+ }
+ done = 0;
+ }
+ /*
+ * and #k nop
+ * jeq #0 -> jset #k
+ */
+ if (last->s.code == (BPF_ALU|BPF_AND|BPF_K) &&
+ !ATOMELEM(b->out_use, A_ATOM) && b->s.k == 0) {
+ b->s.k = last->s.k;
+ b->s.code = BPF_JMP|BPF_K|BPF_JSET;
+ last->s.code = NOP;
+ done = 0;
+ opt_not(b);
+ }
+ /*
+ * If the accumulator is a known constant, we can compute the
+ * comparison result.
+ */
+ val = b->val[A_ATOM];
+ if (vmap[val].is_const && BPF_SRC(b->s.code) == BPF_K) {
+ bpf_int32 v = vmap[val].const_val;
+ switch (BPF_OP(b->s.code)) {
+
+ case BPF_JEQ:
+ v = v == b->s.k;
+ break;
+
+ case BPF_JGT:
+ v = (unsigned)v > b->s.k;
+ break;
+
+ case BPF_JGE:
+ v = (unsigned)v >= b->s.k;
+ break;
+
+ case BPF_JSET:
+ v &= b->s.k;
+ break;
+
+ default:
+ abort();
+ }
+ if (JF(b) != JT(b))
+ done = 0;
+ if (v)
+ JF(b) = JT(b);
+ else
+ JT(b) = JF(b);
+ }
+}
+
+/*
+ * Compute the symbolic value of expression of 's', and update
+ * anything it defines in the value table 'val'. If 'alter' is true,
+ * do various optimizations. This code would be cleaner if symbolic
+ * evaluation and code transformations weren't folded together.
+ */
+static void
+opt_stmt(s, val, alter)
+ struct stmt *s;
+ int val[];
+ int alter;
+{
+ int op;
+ int v;
+
+ switch (s->code) {
+
+ case BPF_LD|BPF_ABS|BPF_W:
+ case BPF_LD|BPF_ABS|BPF_H:
+ case BPF_LD|BPF_ABS|BPF_B:
+ v = F(s->code, s->k, 0L);
+ vstore(s, &val[A_ATOM], v, alter);
+ break;
+
+ case BPF_LD|BPF_IND|BPF_W:
+ case BPF_LD|BPF_IND|BPF_H:
+ case BPF_LD|BPF_IND|BPF_B:
+ v = val[X_ATOM];
+ if (alter && vmap[v].is_const) {
+ s->code = BPF_LD|BPF_ABS|BPF_SIZE(s->code);
+ s->k += vmap[v].const_val;
+ v = F(s->code, s->k, 0L);
+ done = 0;
+ }
+ else
+ v = F(s->code, s->k, v);
+ vstore(s, &val[A_ATOM], v, alter);
+ break;
+
+ case BPF_LD|BPF_LEN:
+ v = F(s->code, 0L, 0L);
+ vstore(s, &val[A_ATOM], v, alter);
+ break;
+
+ case BPF_LD|BPF_IMM:
+ v = K(s->k);
+ vstore(s, &val[A_ATOM], v, alter);
+ break;
+
+ case BPF_LDX|BPF_IMM:
+ v = K(s->k);
+ vstore(s, &val[X_ATOM], v, alter);
+ break;
+
+ case BPF_LDX|BPF_MSH|BPF_B:
+ v = F(s->code, s->k, 0L);
+ vstore(s, &val[X_ATOM], v, alter);
+ break;
+
+ case BPF_ALU|BPF_NEG:
+ if (alter && vmap[val[A_ATOM]].is_const) {
+ s->code = BPF_LD|BPF_IMM;
+ s->k = -vmap[val[A_ATOM]].const_val;
+ val[A_ATOM] = K(s->k);
+ }
+ else
+ val[A_ATOM] = F(s->code, val[A_ATOM], 0L);
+ break;
+
+ case BPF_ALU|BPF_ADD|BPF_K:
+ case BPF_ALU|BPF_SUB|BPF_K:
+ case BPF_ALU|BPF_MUL|BPF_K:
+ case BPF_ALU|BPF_DIV|BPF_K:
+ case BPF_ALU|BPF_AND|BPF_K:
+ case BPF_ALU|BPF_OR|BPF_K:
+ case BPF_ALU|BPF_LSH|BPF_K:
+ case BPF_ALU|BPF_RSH|BPF_K:
+ op = BPF_OP(s->code);
+ if (alter) {
+ if (s->k == 0) {
+ if (op == BPF_ADD || op == BPF_SUB ||
+ op == BPF_LSH || op == BPF_RSH ||
+ op == BPF_OR) {
+ s->code = NOP;
+ break;
+ }
+ if (op == BPF_MUL || op == BPF_AND) {
+ s->code = BPF_LD|BPF_IMM;
+ val[A_ATOM] = K(s->k);
+ break;
+ }
+ }
+ if (vmap[val[A_ATOM]].is_const) {
+ fold_op(s, val[A_ATOM], K(s->k));
+ val[A_ATOM] = K(s->k);
+ break;
+ }
+ }
+ val[A_ATOM] = F(s->code, val[A_ATOM], K(s->k));
+ break;
+
+ case BPF_ALU|BPF_ADD|BPF_X:
+ case BPF_ALU|BPF_SUB|BPF_X:
+ case BPF_ALU|BPF_MUL|BPF_X:
+ case BPF_ALU|BPF_DIV|BPF_X:
+ case BPF_ALU|BPF_AND|BPF_X:
+ case BPF_ALU|BPF_OR|BPF_X:
+ case BPF_ALU|BPF_LSH|BPF_X:
+ case BPF_ALU|BPF_RSH|BPF_X:
+ op = BPF_OP(s->code);
+ if (alter && vmap[val[X_ATOM]].is_const) {
+ if (vmap[val[A_ATOM]].is_const) {
+ fold_op(s, val[A_ATOM], val[X_ATOM]);
+ val[A_ATOM] = K(s->k);
+ }
+ else {
+ s->code = BPF_ALU|BPF_K|op;
+ s->k = vmap[val[X_ATOM]].const_val;
+ done = 0;
+ val[A_ATOM] =
+ F(s->code, val[A_ATOM], K(s->k));
+ }
+ break;
+ }
+ /*
+ * Check if we're doing something to an accumulator
+ * that is 0, and simplify. This may not seem like
+ * much of a simplification but it could open up further
+ * optimizations.
+ * XXX We could also check for mul by 1, and -1, etc.
+ */
+ if (alter && vmap[val[A_ATOM]].is_const
+ && vmap[val[A_ATOM]].const_val == 0) {
+ if (op == BPF_ADD || op == BPF_OR ||
+ op == BPF_LSH || op == BPF_RSH || op == BPF_SUB) {
+ s->code = BPF_MISC|BPF_TXA;
+ vstore(s, &val[A_ATOM], val[X_ATOM], alter);
+ break;
+ }
+ else if (op == BPF_MUL || op == BPF_DIV ||
+ op == BPF_AND) {
+ s->code = BPF_LD|BPF_IMM;
+ s->k = 0;
+ vstore(s, &val[A_ATOM], K(s->k), alter);
+ break;
+ }
+ else if (op == BPF_NEG) {
+ s->code = NOP;
+ break;
+ }
+ }
+ val[A_ATOM] = F(s->code, val[A_ATOM], val[X_ATOM]);
+ break;
+
+ case BPF_MISC|BPF_TXA:
+ vstore(s, &val[A_ATOM], val[X_ATOM], alter);
+ break;
+
+ case BPF_LD|BPF_MEM:
+ v = val[s->k];
+ if (alter && vmap[v].is_const) {
+ s->code = BPF_LD|BPF_IMM;
+ s->k = vmap[v].const_val;
+ done = 0;
+ }
+ vstore(s, &val[A_ATOM], v, alter);
+ break;
+
+ case BPF_MISC|BPF_TAX:
+ vstore(s, &val[X_ATOM], val[A_ATOM], alter);
+ break;
+
+ case BPF_LDX|BPF_MEM:
+ v = val[s->k];
+ if (alter && vmap[v].is_const) {
+ s->code = BPF_LDX|BPF_IMM;
+ s->k = vmap[v].const_val;
+ done = 0;
+ }
+ vstore(s, &val[X_ATOM], v, alter);
+ break;
+
+ case BPF_ST:
+ vstore(s, &val[s->k], val[A_ATOM], alter);
+ break;
+
+ case BPF_STX:
+ vstore(s, &val[s->k], val[X_ATOM], alter);
+ break;
+ }
+}
+
+static void
+deadstmt(s, last)
+ register struct stmt *s;
+ register struct stmt *last[];
+{
+ register int atom;
+
+ atom = atomuse(s);
+ if (atom >= 0) {
+ if (atom == AX_ATOM) {
+ last[X_ATOM] = 0;
+ last[A_ATOM] = 0;
+ }
+ else
+ last[atom] = 0;
+ }
+ atom = atomdef(s);
+ if (atom >= 0) {
+ if (last[atom]) {
+ done = 0;
+ last[atom]->code = NOP;
+ }
+ last[atom] = s;
+ }
+}
+
+static void
+opt_deadstores(b)
+ register struct block *b;
+{
+ register struct slist *s;
+ register int atom;
+ struct stmt *last[N_ATOMS];
+
+ memset((char *)last, 0, sizeof last);
+
+ for (s = b->stmts; s != 0; s = s->next)
+ deadstmt(&s->s, last);
+ deadstmt(&b->s, last);
+
+ for (atom = 0; atom < N_ATOMS; ++atom)
+ if (last[atom] && !ATOMELEM(b->out_use, atom)) {
+ last[atom]->code = NOP;
+ done = 0;
+ }
+}
+
+static void
+opt_blk(b, do_stmts)
+ struct block *b;
+ int do_stmts;
+{
+ struct slist *s;
+ struct edge *p;
+ int i;
+ bpf_int32 aval;
+
+ /*
+ * Initialize the atom values.
+ * If we have no predecessors, everything is undefined.
+ * Otherwise, we inherent our values from our predecessors.
+ * If any register has an ambiguous value (i.e. control paths are
+ * merging) give it the undefined value of 0.
+ */
+ p = b->in_edges;
+ if (p == 0)
+ memset((char *)b->val, 0, sizeof(b->val));
+ else {
+ memcpy((char *)b->val, (char *)p->pred->val, sizeof(b->val));
+ while ((p = p->next) != NULL) {
+ for (i = 0; i < N_ATOMS; ++i)
+ if (b->val[i] != p->pred->val[i])
+ b->val[i] = 0;
+ }
+ }
+ aval = b->val[A_ATOM];
+ for (s = b->stmts; s; s = s->next)
+ opt_stmt(&s->s, b->val, do_stmts);
+
+ /*
+ * This is a special case: if we don't use anything from this
+ * block, and we load the accumulator with value that is
+ * already there, or if this block is a return,
+ * eliminate all the statements.
+ */
+ if (do_stmts &&
+ ((b->out_use == 0 && aval != 0 &&b->val[A_ATOM] == aval) ||
+ BPF_CLASS(b->s.code) == BPF_RET)) {
+ if (b->stmts != 0) {
+ b->stmts = 0;
+ done = 0;
+ }
+ } else {
+ opt_peep(b);
+ opt_deadstores(b);
+ }
+ /*
+ * Set up values for branch optimizer.
+ */
+ if (BPF_SRC(b->s.code) == BPF_K)
+ b->oval = K(b->s.k);
+ else
+ b->oval = b->val[X_ATOM];
+ b->et.code = b->s.code;
+ b->ef.code = -b->s.code;
+}
+
+/*
+ * Return true if any register that is used on exit from 'succ', has
+ * an exit value that is different from the corresponding exit value
+ * from 'b'.
+ */
+static int
+use_conflict(b, succ)
+ struct block *b, *succ;
+{
+ int atom;
+ atomset use = succ->out_use;
+
+ if (use == 0)
+ return 0;
+
+ for (atom = 0; atom < N_ATOMS; ++atom)
+ if (ATOMELEM(use, atom))
+ if (b->val[atom] != succ->val[atom])
+ return 1;
+ return 0;
+}
+
+static struct block *
+fold_edge(child, ep)
+ struct block *child;
+ struct edge *ep;
+{
+ int sense;
+ int aval0, aval1, oval0, oval1;
+ int code = ep->code;
+
+ if (code < 0) {
+ code = -code;
+ sense = 0;
+ } else
+ sense = 1;
+
+ if (child->s.code != code)
+ return 0;
+
+ aval0 = child->val[A_ATOM];
+ oval0 = child->oval;
+ aval1 = ep->pred->val[A_ATOM];
+ oval1 = ep->pred->oval;
+
+ if (aval0 != aval1)
+ return 0;
+
+ if (oval0 == oval1)
+ /*
+ * The operands are identical, so the
+ * result is true if a true branch was
+ * taken to get here, otherwise false.
+ */
+ return sense ? JT(child) : JF(child);
+
+ if (sense && code == (BPF_JMP|BPF_JEQ|BPF_K))
+ /*
+ * At this point, we only know the comparison if we
+ * came down the true branch, and it was an equality
+ * comparison with a constant. We rely on the fact that
+ * distinct constants have distinct value numbers.
+ */
+ return JF(child);
+
+ return 0;
+}
+
+static void
+opt_j(ep)
+ struct edge *ep;
+{
+ register int i, k;
+ register struct block *target;
+
+ if (JT(ep->succ) == 0)
+ return;
+
+ if (JT(ep->succ) == JF(ep->succ)) {
+ /*
+ * Common branch targets can be eliminated, provided
+ * there is no data dependency.
+ */
+ if (!use_conflict(ep->pred, ep->succ->et.succ)) {
+ done = 0;
+ ep->succ = JT(ep->succ);
+ }
+ }
+ /*
+ * For each edge dominator that matches the successor of this
+ * edge, promote the edge successor to the its grandchild.
+ *
+ * XXX We violate the set abstraction here in favor a reasonably
+ * efficient loop.
+ */
+ top:
+ for (i = 0; i < edgewords; ++i) {
+ register bpf_u_int32 x = ep->edom[i];
+
+ while (x != 0) {
+ k = ffs(x) - 1;
+ x &=~ (1 << k);
+ k += i * BITS_PER_WORD;
+
+ target = fold_edge(ep->succ, edges[k]);
+ /*
+ * Check that there is no data dependency between
+ * nodes that will be violated if we move the edge.
+ */
+ if (target != 0 && !use_conflict(ep->pred, target)) {
+ done = 0;
+ ep->succ = target;
+ if (JT(target) != 0)
+ /*
+ * Start over unless we hit a leaf.
+ */
+ goto top;
+ return;
+ }
+ }
+ }
+}
+
+
+static void
+or_pullup(b)
+ struct block *b;
+{
+ int val, at_top;
+ struct block *pull;
+ struct block **diffp, **samep;
+ struct edge *ep;
+
+ ep = b->in_edges;
+ if (ep == 0)
+ return;
+
+ /*
+ * Make sure each predecessor loads the same value.
+ * XXX why?
+ */
+ val = ep->pred->val[A_ATOM];
+ for (ep = ep->next; ep != 0; ep = ep->next)
+ if (val != ep->pred->val[A_ATOM])
+ return;
+
+ if (JT(b->in_edges->pred) == b)
+ diffp = &JT(b->in_edges->pred);
+ else
+ diffp = &JF(b->in_edges->pred);
+
+ at_top = 1;
+ while (1) {
+ if (*diffp == 0)
+ return;
+
+ if (JT(*diffp) != JT(b))
+ return;
+
+ if (!SET_MEMBER((*diffp)->dom, b->id))
+ return;
+
+ if ((*diffp)->val[A_ATOM] != val)
+ break;
+
+ diffp = &JF(*diffp);
+ at_top = 0;
+ }
+ samep = &JF(*diffp);
+ while (1) {
+ if (*samep == 0)
+ return;
+
+ if (JT(*samep) != JT(b))
+ return;
+
+ if (!SET_MEMBER((*samep)->dom, b->id))
+ return;
+
+ if ((*samep)->val[A_ATOM] == val)
+ break;
+
+ /* XXX Need to check that there are no data dependencies
+ between dp0 and dp1. Currently, the code generator
+ will not produce such dependencies. */
+ samep = &JF(*samep);
+ }
+#ifdef notdef
+ /* XXX This doesn't cover everything. */
+ for (i = 0; i < N_ATOMS; ++i)
+ if ((*samep)->val[i] != pred->val[i])
+ return;
+#endif
+ /* Pull up the node. */
+ pull = *samep;
+ *samep = JF(pull);
+ JF(pull) = *diffp;
+
+ /*
+ * At the top of the chain, each predecessor needs to point at the
+ * pulled up node. Inside the chain, there is only one predecessor
+ * to worry about.
+ */
+ if (at_top) {
+ for (ep = b->in_edges; ep != 0; ep = ep->next) {
+ if (JT(ep->pred) == b)
+ JT(ep->pred) = pull;
+ else
+ JF(ep->pred) = pull;
+ }
+ }
+ else
+ *diffp = pull;
+
+ done = 0;
+}
+
+static void
+and_pullup(b)
+ struct block *b;
+{
+ int val, at_top;
+ struct block *pull;
+ struct block **diffp, **samep;
+ struct edge *ep;
+
+ ep = b->in_edges;
+ if (ep == 0)
+ return;
+
+ /*
+ * Make sure each predecessor loads the same value.
+ */
+ val = ep->pred->val[A_ATOM];
+ for (ep = ep->next; ep != 0; ep = ep->next)
+ if (val != ep->pred->val[A_ATOM])
+ return;
+
+ if (JT(b->in_edges->pred) == b)
+ diffp = &JT(b->in_edges->pred);
+ else
+ diffp = &JF(b->in_edges->pred);
+
+ at_top = 1;
+ while (1) {
+ if (*diffp == 0)
+ return;
+
+ if (JF(*diffp) != JF(b))
+ return;
+
+ if (!SET_MEMBER((*diffp)->dom, b->id))
+ return;
+
+ if ((*diffp)->val[A_ATOM] != val)
+ break;
+
+ diffp = &JT(*diffp);
+ at_top = 0;
+ }
+ samep = &JT(*diffp);
+ while (1) {
+ if (*samep == 0)
+ return;
+
+ if (JF(*samep) != JF(b))
+ return;
+
+ if (!SET_MEMBER((*samep)->dom, b->id))
+ return;
+
+ if ((*samep)->val[A_ATOM] == val)
+ break;
+
+ /* XXX Need to check that there are no data dependencies
+ between diffp and samep. Currently, the code generator
+ will not produce such dependencies. */
+ samep = &JT(*samep);
+ }
+#ifdef notdef
+ /* XXX This doesn't cover everything. */
+ for (i = 0; i < N_ATOMS; ++i)
+ if ((*samep)->val[i] != pred->val[i])
+ return;
+#endif
+ /* Pull up the node. */
+ pull = *samep;
+ *samep = JT(pull);
+ JT(pull) = *diffp;
+
+ /*
+ * At the top of the chain, each predecessor needs to point at the
+ * pulled up node. Inside the chain, there is only one predecessor
+ * to worry about.
+ */
+ if (at_top) {
+ for (ep = b->in_edges; ep != 0; ep = ep->next) {
+ if (JT(ep->pred) == b)
+ JT(ep->pred) = pull;
+ else
+ JF(ep->pred) = pull;
+ }
+ }
+ else
+ *diffp = pull;
+
+ done = 0;
+}
+
+static void
+opt_blks(root, do_stmts)
+ struct block *root;
+ int do_stmts;
+{
+ int i, maxlevel;
+ struct block *p;
+
+ init_val();
+ maxlevel = root->level;
+ for (i = maxlevel; i >= 0; --i)
+ for (p = levels[i]; p; p = p->link)
+ opt_blk(p, do_stmts);
+
+ if (do_stmts)
+ /*
+ * No point trying to move branches; it can't possibly
+ * make a difference at this point.
+ */
+ return;
+
+ for (i = 1; i <= maxlevel; ++i) {
+ for (p = levels[i]; p; p = p->link) {
+ opt_j(&p->et);
+ opt_j(&p->ef);
+ }
+ }
+ for (i = 1; i <= maxlevel; ++i) {
+ for (p = levels[i]; p; p = p->link) {
+ or_pullup(p);
+ and_pullup(p);
+ }
+ }
+}
+
+static inline void
+link_inedge(parent, child)
+ struct edge *parent;
+ struct block *child;
+{
+ parent->next = child->in_edges;
+ child->in_edges = parent;
+}
+
+static void
+find_inedges(root)
+ struct block *root;
+{
+ int i;
+ struct block *b;
+
+ for (i = 0; i < n_blocks; ++i)
+ blocks[i]->in_edges = 0;
+
+ /*
+ * Traverse the graph, adding each edge to the predecessor
+ * list of its successors. Skip the leaves (i.e. level 0).
+ */
+ for (i = root->level; i > 0; --i) {
+ for (b = levels[i]; b != 0; b = b->link) {
+ link_inedge(&b->et, JT(b));
+ link_inedge(&b->ef, JF(b));
+ }
+ }
+}
+
+static void
+opt_root(b)
+ struct block **b;
+{
+ struct slist *tmp, *s;
+
+ s = (*b)->stmts;
+ (*b)->stmts = 0;
+ while (BPF_CLASS((*b)->s.code) == BPF_JMP && JT(*b) == JF(*b))
+ *b = JT(*b);
+
+ tmp = (*b)->stmts;
+ if (tmp != 0)
+ sappend(s, tmp);
+ (*b)->stmts = s;
+
+ /*
+ * If the root node is a return, then there is no
+ * point executing any statements (since the bpf machine
+ * has no side effects).
+ */
+ if (BPF_CLASS((*b)->s.code) == BPF_RET)
+ (*b)->stmts = 0;
+}
+
+static void
+opt_loop(root, do_stmts)
+ struct block *root;
+ int do_stmts;
+{
+
+#ifdef BDEBUG
+ if (dflag > 1)
+ opt_dump(root);
+#endif
+ do {
+ done = 1;
+ find_levels(root);
+ find_dom(root);
+ find_closure(root);
+ find_inedges(root);
+ find_ud(root);
+ find_edom(root);
+ opt_blks(root, do_stmts);
+#ifdef BDEBUG
+ if (dflag > 1)
+ opt_dump(root);
+#endif
+ } while (!done);
+}
+
+/*
+ * Optimize the filter code in its dag representation.
+ */
+void
+bpf_optimize(rootp)
+ struct block **rootp;
+{
+ struct block *root;
+
+ root = *rootp;
+
+ opt_init(root);
+ opt_loop(root, 0);
+ opt_loop(root, 1);
+ intern_blocks(root);
+ opt_root(rootp);
+ opt_cleanup();
+}
+
+static void
+make_marks(p)
+ struct block *p;
+{
+ if (!isMarked(p)) {
+ Mark(p);
+ if (BPF_CLASS(p->s.code) != BPF_RET) {
+ make_marks(JT(p));
+ make_marks(JF(p));
+ }
+ }
+}
+
+/*
+ * Mark code array such that isMarked(i) is true
+ * only for nodes that are alive.
+ */
+static void
+mark_code(p)
+ struct block *p;
+{
+ cur_mark += 1;
+ make_marks(p);
+}
+
+/*
+ * True iff the two stmt lists load the same value from the packet into
+ * the accumulator.
+ */
+static int
+eq_slist(x, y)
+ struct slist *x, *y;
+{
+ while (1) {
+ while (x && x->s.code == NOP)
+ x = x->next;
+ while (y && y->s.code == NOP)
+ y = y->next;
+ if (x == 0)
+ return y == 0;
+ if (y == 0)
+ return x == 0;
+ if (x->s.code != y->s.code || x->s.k != y->s.k)
+ return 0;
+ x = x->next;
+ y = y->next;
+ }
+}
+
+static inline int
+eq_blk(b0, b1)
+ struct block *b0, *b1;
+{
+ if (b0->s.code == b1->s.code &&
+ b0->s.k == b1->s.k &&
+ b0->et.succ == b1->et.succ &&
+ b0->ef.succ == b1->ef.succ)
+ return eq_slist(b0->stmts, b1->stmts);
+ return 0;
+}
+
+static void
+intern_blocks(root)
+ struct block *root;
+{
+ struct block *p;
+ int i, j;
+ int done;
+ top:
+ done = 1;
+ for (i = 0; i < n_blocks; ++i)
+ blocks[i]->link = 0;
+
+ mark_code(root);
+
+ for (i = n_blocks - 1; --i >= 0; ) {
+ if (!isMarked(blocks[i]))
+ continue;
+ for (j = i + 1; j < n_blocks; ++j) {
+ if (!isMarked(blocks[j]))
+ continue;
+ if (eq_blk(blocks[i], blocks[j])) {
+ blocks[i]->link = blocks[j]->link ?
+ blocks[j]->link : blocks[j];
+ break;
+ }
+ }
+ }
+ for (i = 0; i < n_blocks; ++i) {
+ p = blocks[i];
+ if (JT(p) == 0)
+ continue;
+ if (JT(p)->link) {
+ done = 0;
+ JT(p) = JT(p)->link;
+ }
+ if (JF(p)->link) {
+ done = 0;
+ JF(p) = JF(p)->link;
+ }
+ }
+ if (!done)
+ goto top;
+}
+
+static void
+opt_cleanup()
+{
+ free((void *)vnode_base);
+ free((void *)vmap);
+ free((void *)edges);
+ free((void *)space);
+ free((void *)levels);
+ free((void *)blocks);
+}
+
+/*
+ * Return the number of stmts in 's'.
+ */
+static int
+slength(s)
+ struct slist *s;
+{
+ int n = 0;
+
+ for (; s; s = s->next)
+ if (s->s.code != NOP)
+ ++n;
+ return n;
+}
+
+/*
+ * Return the number of nodes reachable by 'p'.
+ * All nodes should be initially unmarked.
+ */
+static int
+count_blocks(p)
+ struct block *p;
+{
+ if (p == 0 || isMarked(p))
+ return 0;
+ Mark(p);
+ return count_blocks(JT(p)) + count_blocks(JF(p)) + 1;
+}
+
+/*
+ * Do a depth first search on the flow graph, numbering the
+ * the basic blocks, and entering them into the 'blocks' array.`
+ */
+static void
+number_blks_r(p)
+ struct block *p;
+{
+ int n;
+
+ if (p == 0 || isMarked(p))
+ return;
+
+ Mark(p);
+ n = n_blocks++;
+ p->id = n;
+ blocks[n] = p;
+
+ number_blks_r(JT(p));
+ number_blks_r(JF(p));
+}
+
+/*
+ * Return the number of stmts in the flowgraph reachable by 'p'.
+ * The nodes should be unmarked before calling.
+ */
+static int
+count_stmts(p)
+ struct block *p;
+{
+ int n;
+
+ if (p == 0 || isMarked(p))
+ return 0;
+ Mark(p);
+ n = count_stmts(JT(p)) + count_stmts(JF(p));
+ return slength(p->stmts) + n + 1;
+}
+
+/*
+ * Allocate memory. All allocation is done before optimization
+ * is begun. A linear bound on the size of all data structures is computed
+ * from the total number of blocks and/or statements.
+ */
+static void
+opt_init(root)
+ struct block *root;
+{
+ bpf_u_int32 *p;
+ int i, n, max_stmts;
+
+ /*
+ * First, count the blocks, so we can malloc an array to map
+ * block number to block. Then, put the blocks into the array.
+ */
+ unMarkAll();
+ n = count_blocks(root);
+ blocks = (struct block **)malloc(n * sizeof(*blocks));
+ unMarkAll();
+ n_blocks = 0;
+ number_blks_r(root);
+
+ n_edges = 2 * n_blocks;
+ edges = (struct edge **)malloc(n_edges * sizeof(*edges));
+
+ /*
+ * The number of levels is bounded by the number of nodes.
+ */
+ levels = (struct block **)malloc(n_blocks * sizeof(*levels));
+
+ edgewords = n_edges / (8 * sizeof(bpf_u_int32)) + 1;
+ nodewords = n_blocks / (8 * sizeof(bpf_u_int32)) + 1;
+
+ /* XXX */
+ space = (bpf_u_int32 *)malloc(2 * n_blocks * nodewords * sizeof(*space)
+ + n_edges * edgewords * sizeof(*space));
+ p = space;
+ all_dom_sets = p;
+ for (i = 0; i < n; ++i) {
+ blocks[i]->dom = p;
+ p += nodewords;
+ }
+ all_closure_sets = p;
+ for (i = 0; i < n; ++i) {
+ blocks[i]->closure = p;
+ p += nodewords;
+ }
+ all_edge_sets = p;
+ for (i = 0; i < n; ++i) {
+ register struct block *b = blocks[i];
+
+ b->et.edom = p;
+ p += edgewords;
+ b->ef.edom = p;
+ p += edgewords;
+ b->et.id = i;
+ edges[i] = &b->et;
+ b->ef.id = n_blocks + i;
+ edges[n_blocks + i] = &b->ef;
+ b->et.pred = b;
+ b->ef.pred = b;
+ }
+ max_stmts = 0;
+ for (i = 0; i < n; ++i)
+ max_stmts += slength(blocks[i]->stmts) + 1;
+ /*
+ * We allocate at most 3 value numbers per statement,
+ * so this is an upper bound on the number of valnodes
+ * we'll need.
+ */
+ maxval = 3 * max_stmts;
+ vmap = (struct vmapinfo *)malloc(maxval * sizeof(*vmap));
+ vnode_base = (struct valnode *)malloc(maxval * sizeof(*vmap));
+}
+
+/*
+ * Some pointers used to convert the basic block form of the code,
+ * into the array form that BPF requires. 'fstart' will point to
+ * the malloc'd array while 'ftail' is used during the recursive traversal.
+ */
+static struct bpf_insn *fstart;
+static struct bpf_insn *ftail;
+
+#ifdef BDEBUG
+int bids[1000];
+#endif
+
+/*
+ * Returns true if successful. Returns false if a branch has
+ * an offset that is too large. If so, we have marked that
+ * branch so that on a subsequent iteration, it will be treated
+ * properly.
+ */
+static int
+convert_code_r(p)
+ struct block *p;
+{
+ struct bpf_insn *dst;
+ struct slist *src;
+ int slen;
+ u_int off;
+ int extrajmps; /* number of extra jumps inserted */
+
+ if (p == 0 || isMarked(p))
+ return (1);
+ Mark(p);
+
+ if (convert_code_r(JF(p)) == 0)
+ return (0);
+ if (convert_code_r(JT(p)) == 0)
+ return (0);
+
+ slen = slength(p->stmts);
+ dst = ftail -= (slen + 1 + p->longjt + p->longjf);
+ /* inflate length by any extra jumps */
+
+ p->offset = dst - fstart;
+
+ for (src = p->stmts; src; src = src->next) {
+ if (src->s.code == NOP)
+ continue;
+ dst->code = (u_short)src->s.code;
+ dst->k = src->s.k;
+ ++dst;
+ }
+#ifdef BDEBUG
+ bids[dst - fstart] = p->id + 1;
+#endif
+ dst->code = (u_short)p->s.code;
+ dst->k = p->s.k;
+ if (JT(p)) {
+ extrajmps = 0;
+ off = JT(p)->offset - (p->offset + slen) - 1;
+ if (off >= 256) {
+ /* offset too large for branch, must add a jump */
+ if (p->longjt == 0) {
+ /* mark this instruction and retry */
+ p->longjt++;
+ return(0);
+ }
+ /* branch if T to following jump */
+ dst->jt = extrajmps;
+ extrajmps++;
+ dst[extrajmps].code = BPF_JMP|BPF_JA;
+ dst[extrajmps].k = off - extrajmps;
+ }
+ else
+ dst->jt = off;
+ off = JF(p)->offset - (p->offset + slen) - 1;
+ if (off >= 256) {
+ /* offset too large for branch, must add a jump */
+ if (p->longjf == 0) {
+ /* mark this instruction and retry */
+ p->longjf++;
+ return(0);
+ }
+ /* branch if F to following jump */
+ /* if two jumps are inserted, F goes to second one */
+ dst->jf = extrajmps;
+ extrajmps++;
+ dst[extrajmps].code = BPF_JMP|BPF_JA;
+ dst[extrajmps].k = off - extrajmps;
+ }
+ else
+ dst->jf = off;
+ }
+ return (1);
+}
+
+
+/*
+ * Convert flowgraph intermediate representation to the
+ * BPF array representation. Set *lenp to the number of instructions.
+ */
+struct bpf_insn *
+icode_to_fcode(root, lenp)
+ struct block *root;
+ int *lenp;
+{
+ int n;
+ struct bpf_insn *fp;
+
+ /*
+ * Loop doing convert_codr_r() until no branches remain
+ * with too-large offsets.
+ */
+ while (1) {
+ unMarkAll();
+ n = *lenp = count_stmts(root);
+
+ fp = (struct bpf_insn *)malloc(sizeof(*fp) * n);
+ memset((char *)fp, 0, sizeof(*fp) * n);
+ fstart = fp;
+ ftail = fp + n;
+
+ unMarkAll();
+ if (convert_code_r(root))
+ break;
+ free(fp);
+ }
+
+ return fp;
+}
+
+#ifdef BDEBUG
+static void
+opt_dump(root)
+ struct block *root;
+{
+ struct bpf_program f;
+
+ memset(bids, 0, sizeof bids);
+ f.bf_insns = icode_to_fcode(root, &f.bf_len);
+ bpf_dump(&f, 1);
+ putchar('\n');
+ free((char *)f.bf_insns);
+}
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-bpf.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-bpf.c
new file mode 100644
index 000000000..d8006c39b
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-bpf.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 1993, 1994, 1995, 1996, 1998
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-bpf.c,v 1.1 1999/08/26 10:05:23 johana Exp $ (LBL)";
+#endif
+
+#include <sys/param.h> /* optionally get BSD define */
+#include <sys/time.h>
+#include <sys/timeb.h>
+#include <sys/socket.h>
+#include <sys/file.h>
+#include <sys/ioctl.h>
+
+#include <net/if.h>
+
+#include <ctype.h>
+#include <errno.h>
+#include <netdb.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+int
+pcap_stats(pcap_t *p, struct pcap_stat *ps)
+{
+ struct bpf_stat s;
+
+ if (ioctl(p->fd, BIOCGSTATS, (caddr_t)&s) < 0) {
+ sprintf(p->errbuf, "BIOCGSTATS: %s", pcap_strerror(errno));
+ return (-1);
+ }
+
+ ps->ps_recv = s.bs_recv;
+ ps->ps_drop = s.bs_drop;
+ return (0);
+}
+
+int
+pcap_read(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+ int cc;
+ int n = 0;
+ register u_char *bp, *ep;
+
+ again:
+ cc = p->cc;
+ if (p->cc == 0) {
+ cc = read(p->fd, (char *)p->buffer, p->bufsize);
+ if (cc < 0) {
+ /* Don't choke when we get ptraced */
+ switch (errno) {
+
+ case EINTR:
+ goto again;
+
+ case EWOULDBLOCK:
+ return (0);
+#if defined(sun) && !defined(BSD)
+ /*
+ * Due to a SunOS bug, after 2^31 bytes, the kernel
+ * file offset overflows and read fails with EINVAL.
+ * The lseek() to 0 will fix things.
+ */
+ case EINVAL:
+ if (lseek(p->fd, 0L, SEEK_CUR) +
+ p->bufsize < 0) {
+ (void)lseek(p->fd, 0L, SEEK_SET);
+ goto again;
+ }
+ /* fall through */
+#endif
+ }
+ sprintf(p->errbuf, "read: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ bp = p->buffer;
+ } else
+ bp = p->bp;
+
+ /*
+ * Loop through each packet.
+ */
+#define bhp ((struct bpf_hdr *)bp)
+ ep = bp + cc;
+ while (bp < ep) {
+ register int caplen, hdrlen;
+ caplen = bhp->bh_caplen;
+ hdrlen = bhp->bh_hdrlen;
+ /*
+ * XXX A bpf_hdr matches a pcap_pkthdr.
+ */
+ (*callback)(user, (struct pcap_pkthdr*)bp, bp + hdrlen);
+ bp += BPF_WORDALIGN(caplen + hdrlen);
+ if (++n >= cnt && cnt > 0) {
+ p->bp = bp;
+ p->cc = ep - bp;
+ return (n);
+ }
+ }
+#undef bhp
+ p->cc = 0;
+ return (n);
+}
+
+static inline int
+bpf_open(pcap_t *p, char *errbuf)
+{
+ int fd;
+ int n = 0;
+ char device[sizeof "/dev/bpf000"];
+
+ /*
+ * Go through all the minors and find one that isn't in use.
+ */
+ do {
+ (void)sprintf(device, "/dev/bpf%d", n++);
+ fd = open(device, O_RDONLY);
+ } while (fd < 0 && errno == EBUSY);
+
+ /*
+ * XXX better message for all minors used
+ */
+ if (fd < 0)
+ sprintf(errbuf, "%s: %s", device, pcap_strerror(errno));
+
+ return (fd);
+}
+
+pcap_t *
+pcap_open_live(char *device, int snaplen, int promisc, int to_ms, char *ebuf)
+{
+ int fd;
+ struct ifreq ifr;
+ struct bpf_version bv;
+ u_int v;
+ pcap_t *p;
+
+ p = (pcap_t *)malloc(sizeof(*p));
+ if (p == NULL) {
+ sprintf(ebuf, "malloc: %s", pcap_strerror(errno));
+ return (NULL);
+ }
+ bzero(p, sizeof(*p));
+ fd = bpf_open(p, ebuf);
+ if (fd < 0)
+ goto bad;
+
+ p->fd = fd;
+ p->snapshot = snaplen;
+
+ if (ioctl(fd, BIOCVERSION, (caddr_t)&bv) < 0) {
+ sprintf(ebuf, "BIOCVERSION: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ if (bv.bv_major != BPF_MAJOR_VERSION ||
+ bv.bv_minor < BPF_MINOR_VERSION) {
+ sprintf(ebuf, "kernel bpf filter out of date");
+ goto bad;
+ }
+ v = 32768; /* XXX this should be a user-accessible hook */
+ /* Ignore the return value - this is because the call fails on
+ * BPF systems that don't have kernel malloc. And if the call
+ * fails, it's no big deal, we just continue to use the standard
+ * buffer size.
+ */
+ (void) ioctl(fd, BIOCSBLEN, (caddr_t)&v);
+
+ (void)strncpy(ifr.ifr_name, device, sizeof(ifr.ifr_name));
+ if (ioctl(fd, BIOCSETIF, (caddr_t)&ifr) < 0) {
+ sprintf(ebuf, "%s: %s", device, pcap_strerror(errno));
+ goto bad;
+ }
+ /* Get the data link layer type. */
+ if (ioctl(fd, BIOCGDLT, (caddr_t)&v) < 0) {
+ sprintf(ebuf, "BIOCGDLT: %s", pcap_strerror(errno));
+ goto bad;
+ }
+#if _BSDI_VERSION - 0 >= 199510
+ /* The SLIP and PPP link layer header changed in BSD/OS 2.1 */
+ switch (v) {
+
+ case DLT_SLIP:
+ v = DLT_SLIP_BSDOS;
+ break;
+
+ case DLT_PPP:
+ v = DLT_PPP_BSDOS;
+ break;
+ }
+#endif
+ p->linktype = v;
+
+ /* set timeout */
+ if (to_ms != 0) {
+ struct timeval to;
+ to.tv_sec = to_ms / 1000;
+ to.tv_usec = (to_ms * 1000) % 1000000;
+ if (ioctl(p->fd, BIOCSRTIMEOUT, (caddr_t)&to) < 0) {
+ sprintf(ebuf, "BIOCSRTIMEOUT: %s",
+ pcap_strerror(errno));
+ goto bad;
+ }
+ }
+ if (promisc)
+ /* set promiscuous mode, okay if it fails */
+ (void)ioctl(p->fd, BIOCPROMISC, NULL);
+
+ if (ioctl(fd, BIOCGBLEN, (caddr_t)&v) < 0) {
+ sprintf(ebuf, "BIOCGBLEN: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ p->bufsize = v;
+ p->buffer = (u_char *)malloc(p->bufsize);
+ if (p->buffer == NULL) {
+ sprintf(ebuf, "malloc: %s", pcap_strerror(errno));
+ goto bad;
+ }
+
+ return (p);
+ bad:
+ (void)close(fd);
+ free(p);
+ return (NULL);
+}
+
+int
+pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+{
+ if (p->sf.rfile != NULL)
+ p->fcode = *fp;
+ else if (ioctl(p->fd, BIOCSETF, (caddr_t)fp) < 0) {
+ sprintf(p->errbuf, "BIOCSETF: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ return (0);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-dlpi.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-dlpi.c
new file mode 100644
index 000000000..11d19d866
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-dlpi.c
@@ -0,0 +1,848 @@
+/*
+ * Copyright (c) 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * This code contributed by Atanu Ghosh (atanu@cs.ucl.ac.uk),
+ * University College London.
+ */
+
+/*
+ * Packet capture routine for dlpi under SunOS 5
+ *
+ * Notes:
+ *
+ * - Apparently the DLIOCRAW ioctl() is specific to SunOS.
+ *
+ * - There is a bug in bufmod(7) such that setting the snapshot
+ * length results in data being left of the front of the packet.
+ *
+ * - It might be desirable to use pfmod(7) to filter packets in the
+ * kernel.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-dlpi.c,v 1.1 1999/08/26 10:05:23 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+#ifdef HAVE_SYS_BUFMOD_H
+#include <sys/bufmod.h>
+#endif
+#include <sys/dlpi.h>
+#ifdef HAVE_SYS_DLPI_EXT_H
+#include <sys/dlpi_ext.h>
+#endif
+#ifdef HAVE_HPUX9
+#include <sys/socket.h>
+#endif
+#ifdef DL_HP_PPA_ACK_OBS
+#include <sys/stat.h>
+#endif
+#include <sys/stream.h>
+#if defined(HAVE_SOLARIS) && defined(HAVE_SYS_BUFMOD_H)
+#include <sys/systeminfo.h>
+#endif
+
+#ifdef HAVE_HPUX9
+#include <net/if.h>
+#endif
+
+#include <ctype.h>
+#ifdef HAVE_HPUX9
+#include <nlist.h>
+#endif
+#include <errno.h>
+#include <fcntl.h>
+#include <memory.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stropts.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#ifndef PCAP_DEV_PREFIX
+#define PCAP_DEV_PREFIX "/dev"
+#endif
+
+#define MAXDLBUF 8192
+
+/* Forwards */
+static int dlattachreq(int, bpf_u_int32, char *);
+static int dlbindack(int, char *, char *);
+static int dlbindreq(int, bpf_u_int32, char *);
+static int dlinfoack(int, char *, char *);
+static int dlinforeq(int, char *);
+static int dlokack(int, const char *, char *, char *);
+static int recv_ack(int, int, const char *, char *, char *);
+static int dlpromisconreq(int, bpf_u_int32, char *);
+#if defined(HAVE_SOLARIS) && defined(HAVE_SYS_BUFMOD_H)
+static char *get_release(bpf_u_int32 *, bpf_u_int32 *, bpf_u_int32 *);
+#endif
+static int send_request(int, char *, int, char *, char *);
+#ifdef HAVE_SYS_BUFMOD_H
+static int strioctl(int, int, int, char *);
+#endif
+#ifdef HAVE_HPUX9
+static int dlpi_kread(int, off_t, void *, u_int, char *);
+#endif
+#ifdef HAVE_DEV_DLPI
+static int get_dlpi_ppa(int, const char *, int, char *);
+#endif
+
+int
+pcap_stats(pcap_t *p, struct pcap_stat *ps)
+{
+
+ *ps = p->md.stat;
+ return (0);
+}
+
+/* XXX Needed by HP-UX (at least) */
+static bpf_u_int32 ctlbuf[MAXDLBUF];
+static struct strbuf ctl = {
+ MAXDLBUF,
+ 0,
+ (char *)ctlbuf
+};
+
+int
+pcap_read(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+ register int cc, n, caplen, origlen;
+ register u_char *bp, *ep, *pk;
+ register struct bpf_insn *fcode;
+#ifdef HAVE_SYS_BUFMOD_H
+ register struct sb_hdr *sbp;
+#ifdef LBL_ALIGN
+ struct sb_hdr sbhdr;
+#endif
+#endif
+ int flags;
+ struct strbuf data;
+ struct pcap_pkthdr pkthdr;
+
+ flags = 0;
+ cc = p->cc;
+ if (cc == 0) {
+ data.buf = (char *)p->buffer + p->offset;
+ data.maxlen = MAXDLBUF;
+ data.len = 0;
+ do {
+ if (getmsg(p->fd, &ctl, &data, &flags) < 0) {
+ /* Don't choke when we get ptraced */
+ if (errno == EINTR) {
+ cc = 0;
+ continue;
+ }
+ strcpy(p->errbuf, pcap_strerror(errno));
+ return (-1);
+ }
+ cc = data.len;
+ } while (cc == 0);
+ bp = p->buffer + p->offset;
+ } else
+ bp = p->bp;
+
+ /* Loop through packets */
+ fcode = p->fcode.bf_insns;
+ ep = bp + cc;
+ n = 0;
+#ifdef HAVE_SYS_BUFMOD_H
+ while (bp < ep) {
+#ifdef LBL_ALIGN
+ if ((long)bp & 3) {
+ sbp = &sbhdr;
+ memcpy(sbp, bp, sizeof(*sbp));
+ } else
+#endif
+ sbp = (struct sb_hdr *)bp;
+ p->md.stat.ps_drop += sbp->sbh_drops;
+ pk = bp + sizeof(*sbp);
+ bp += sbp->sbh_totlen;
+ origlen = sbp->sbh_origlen;
+ caplen = sbp->sbh_msglen;
+#else
+ origlen = cc;
+ caplen = min(p->snapshot, cc);
+ pk = bp;
+ bp += caplen;
+#endif
+ ++p->md.stat.ps_recv;
+ if (bpf_filter(fcode, pk, origlen, caplen)) {
+#ifdef HAVE_SYS_BUFMOD_H
+ pkthdr.ts = sbp->sbh_timestamp;
+#else
+ (void)gettimeofday(&pkthdr.ts, NULL);
+#endif
+ pkthdr.len = origlen;
+ pkthdr.caplen = caplen;
+ /* Insure caplen does not exceed snapshot */
+ if (pkthdr.caplen > p->snapshot)
+ pkthdr.caplen = p->snapshot;
+ (*callback)(user, &pkthdr, pk);
+ if (++n >= cnt && cnt >= 0) {
+ p->cc = ep - bp;
+ p->bp = bp;
+ return (n);
+ }
+ }
+#ifdef HAVE_SYS_BUFMOD_H
+ }
+#endif
+ p->cc = 0;
+ return (n);
+}
+
+pcap_t *
+pcap_open_live(char *device, int snaplen, int promisc, int to_ms, char *ebuf)
+{
+ register char *cp;
+ char *eos;
+ register pcap_t *p;
+ register int ppa;
+ register dl_info_ack_t *infop;
+#ifdef HAVE_SYS_BUFMOD_H
+ bpf_u_int32 ss, flag;
+#ifdef HAVE_SOLARIS
+ register char *release;
+ bpf_u_int32 osmajor, osminor, osmicro;
+#endif
+#endif
+ bpf_u_int32 buf[MAXDLBUF];
+ char dname[100];
+#ifndef HAVE_DEV_DLPI
+ char dname2[100];
+#endif
+
+ p = (pcap_t *)malloc(sizeof(*p));
+ if (p == NULL) {
+ strcpy(ebuf, pcap_strerror(errno));
+ return (NULL);
+ }
+ memset(p, 0, sizeof(*p));
+
+ /*
+ ** Determine device and ppa
+ */
+ cp = strpbrk(device, "0123456789");
+ if (cp == NULL) {
+ sprintf(ebuf, "%s missing unit number", device);
+ goto bad;
+ }
+ ppa = strtol(cp, &eos, 10);
+ if (*eos != '\0') {
+ sprintf(ebuf, "%s bad unit number", device);
+ goto bad;
+ }
+
+ if (*device == '/')
+ strcpy(dname, device);
+ else
+ sprintf(dname, "%s/%s", PCAP_DEV_PREFIX, device);
+#ifdef HAVE_DEV_DLPI
+ /* Map network device to /dev/dlpi unit */
+ cp = "/dev/dlpi";
+ if ((p->fd = open(cp, O_RDWR)) < 0) {
+ sprintf(ebuf, "%s: %s", cp, pcap_strerror(errno));
+ goto bad;
+ }
+ /* Map network interface to /dev/dlpi unit */
+ ppa = get_dlpi_ppa(p->fd, dname, ppa, ebuf);
+ if (ppa < 0)
+ goto bad;
+#else
+ /* Try device without unit number */
+ strcpy(dname2, dname);
+ cp = strchr(dname, *cp);
+ *cp = '\0';
+ if ((p->fd = open(dname, O_RDWR)) < 0) {
+ if (errno != ENOENT) {
+ sprintf(ebuf, "%s: %s", dname, pcap_strerror(errno));
+ goto bad;
+ }
+
+ /* Try again with unit number */
+ if ((p->fd = open(dname2, O_RDWR)) < 0) {
+ sprintf(ebuf, "%s: %s", dname2, pcap_strerror(errno));
+ goto bad;
+ }
+ /* XXX Assume unit zero */
+ ppa = 0;
+ }
+#endif
+
+ p->snapshot = snaplen;
+
+ /*
+ ** Attach if "style 2" provider
+ */
+ if (dlinforeq(p->fd, ebuf) < 0 ||
+ dlinfoack(p->fd, (char *)buf, ebuf) < 0)
+ goto bad;
+ infop = &((union DL_primitives *)buf)->info_ack;
+ if (infop->dl_provider_style == DL_STYLE2 &&
+ (dlattachreq(p->fd, ppa, ebuf) < 0 ||
+ dlokack(p->fd, "attach", (char *)buf, ebuf) < 0))
+ goto bad;
+ /*
+ ** Bind (defer if using HP-UX 9 or HP-UX 10.20, totally skip if
+ ** using SINIX)
+ */
+#if !defined(HAVE_HPUX9) && !defined(HAVE_HPUX10_20) && !defined(sinix)
+ if (dlbindreq(p->fd, 0, ebuf) < 0 ||
+ dlbindack(p->fd, (char *)buf, ebuf) < 0)
+ goto bad;
+#endif
+
+ if (promisc) {
+ /*
+ ** Enable promiscuous
+ */
+ if (dlpromisconreq(p->fd, DL_PROMISC_PHYS, ebuf) < 0 ||
+ dlokack(p->fd, "promisc_phys", (char *)buf, ebuf) < 0)
+ goto bad;
+
+ /*
+ ** Try to enable multicast (you would have thought
+ ** promiscuous would be sufficient). (Skip if using
+ ** HP-UX or SINIX)
+ */
+#if !defined(__hpux) && !defined(sinix)
+ if (dlpromisconreq(p->fd, DL_PROMISC_MULTI, ebuf) < 0 ||
+ dlokack(p->fd, "promisc_multi", (char *)buf, ebuf) < 0)
+ fprintf(stderr,
+ "WARNING: DL_PROMISC_MULTI failed (%s)\n", ebuf);
+#endif
+ }
+ /*
+ ** Try to enable sap (when not in promiscuous mode when using
+ ** using HP-UX and never under SINIX)
+ */
+#ifndef sinix
+ if (
+#ifdef __hpux
+ !promisc &&
+#endif
+ (dlpromisconreq(p->fd, DL_PROMISC_SAP, ebuf) < 0 ||
+ dlokack(p->fd, "promisc_sap", (char *)buf, ebuf) < 0)) {
+ /* Not fatal if promisc since the DL_PROMISC_PHYS worked */
+ if (promisc)
+ fprintf(stderr,
+ "WARNING: DL_PROMISC_SAP failed (%s)\n", ebuf);
+ else
+ goto bad;
+ }
+#endif
+
+ /*
+ ** HP-UX 9 and HP-UX 10.20 must bind after setting promiscuous
+ ** options)
+ */
+#if defined(HAVE_HPUX9) || defined(HAVE_HPUX10_20)
+ if (dlbindreq(p->fd, 0, ebuf) < 0 ||
+ dlbindack(p->fd, (char *)buf, ebuf) < 0)
+ goto bad;
+#endif
+
+ /*
+ ** Determine link type
+ */
+ if (dlinforeq(p->fd, ebuf) < 0 ||
+ dlinfoack(p->fd, (char *)buf, ebuf) < 0)
+ goto bad;
+
+ infop = &((union DL_primitives *)buf)->info_ack;
+ switch (infop->dl_mac_type) {
+
+ case DL_CSMACD:
+ case DL_ETHER:
+ p->linktype = DLT_EN10MB;
+ p->offset = 2;
+ break;
+
+ case DL_FDDI:
+ p->linktype = DLT_FDDI;
+ p->offset = 3;
+ break;
+
+ default:
+ sprintf(ebuf, "unknown mac type 0x%lu", infop->dl_mac_type);
+ goto bad;
+ }
+
+#ifdef DLIOCRAW
+ /*
+ ** This is a non standard SunOS hack to get the ethernet header.
+ */
+ if (strioctl(p->fd, DLIOCRAW, 0, NULL) < 0) {
+ sprintf(ebuf, "DLIOCRAW: %s", pcap_strerror(errno));
+ goto bad;
+ }
+#endif
+
+#ifdef HAVE_SYS_BUFMOD_H
+ /*
+ ** Another non standard call to get the data nicely buffered
+ */
+ if (ioctl(p->fd, I_PUSH, "bufmod") != 0) {
+ sprintf(ebuf, "I_PUSH bufmod: %s", pcap_strerror(errno));
+ goto bad;
+ }
+
+ /*
+ ** Now that the bufmod is pushed lets configure it.
+ **
+ ** There is a bug in bufmod(7). When dealing with messages of
+ ** less than snaplen size it strips data from the beginning not
+ ** the end.
+ **
+ ** This bug is supposed to be fixed in 5.3.2. Also, there is a
+ ** patch available. Ask for bugid 1149065.
+ */
+ ss = snaplen;
+#ifdef HAVE_SOLARIS
+ release = get_release(&osmajor, &osminor, &osmicro);
+ if (osmajor == 5 && (osminor <= 2 || (osminor == 3 && osmicro < 2)) &&
+ getenv("BUFMOD_FIXED") == NULL) {
+ fprintf(stderr,
+ "WARNING: bufmod is broken in SunOS %s; ignoring snaplen.\n",
+ release);
+ ss = 0;
+ }
+#endif
+ if (ss > 0 &&
+ strioctl(p->fd, SBIOCSSNAP, sizeof(ss), (char *)&ss) != 0) {
+ sprintf(ebuf, "SBIOCSSNAP: %s", pcap_strerror(errno));
+ goto bad;
+ }
+
+ /*
+ ** Set up the bufmod flags
+ */
+ if (strioctl(p->fd, SBIOCGFLAGS, sizeof(flag), (char *)&flag) < 0) {
+ sprintf(ebuf, "SBIOCGFLAGS: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ flag |= SB_NO_DROPS;
+ if (strioctl(p->fd, SBIOCSFLAGS, sizeof(flag), (char *)&flag) != 0) {
+ sprintf(ebuf, "SBIOCSFLAGS: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ /*
+ ** Set up the bufmod timeout
+ */
+ if (to_ms != 0) {
+ struct timeval to;
+
+ to.tv_sec = to_ms / 1000;
+ to.tv_usec = (to_ms * 1000) % 1000000;
+ if (strioctl(p->fd, SBIOCSTIME, sizeof(to), (char *)&to) != 0) {
+ sprintf(ebuf, "SBIOCSTIME: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ }
+#endif
+
+ /*
+ ** As the last operation flush the read side.
+ */
+ if (ioctl(p->fd, I_FLUSH, FLUSHR) != 0) {
+ sprintf(ebuf, "FLUSHR: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ /* Allocate data buffer */
+ p->bufsize = MAXDLBUF * sizeof(bpf_u_int32);
+ p->buffer = (u_char *)malloc(p->bufsize + p->offset);
+
+ return (p);
+bad:
+ free(p);
+ return (NULL);
+}
+
+int
+pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+{
+
+ p->fcode = *fp;
+ return (0);
+}
+
+static int
+send_request(int fd, char *ptr, int len, char *what, char *ebuf)
+{
+ struct strbuf ctl;
+ int flags;
+
+ ctl.maxlen = 0;
+ ctl.len = len;
+ ctl.buf = ptr;
+
+ flags = 0;
+ if (putmsg(fd, &ctl, (struct strbuf *) NULL, flags) < 0) {
+ sprintf(ebuf, "send_request: putmsg \"%s\": %s",
+ what, pcap_strerror(errno));
+ return (-1);
+ }
+ return (0);
+}
+
+static int
+recv_ack(int fd, int size, const char *what, char *bufp, char *ebuf)
+{
+ union DL_primitives *dlp;
+ struct strbuf ctl;
+ int flags;
+
+ ctl.maxlen = MAXDLBUF;
+ ctl.len = 0;
+ ctl.buf = bufp;
+
+ flags = 0;
+ if (getmsg(fd, &ctl, (struct strbuf*)NULL, &flags) < 0) {
+ sprintf(ebuf, "recv_ack: %s getmsg: %s",
+ what, pcap_strerror(errno));
+ return (-1);
+ }
+
+ dlp = (union DL_primitives *) ctl.buf;
+ switch (dlp->dl_primitive) {
+
+ case DL_INFO_ACK:
+ case DL_BIND_ACK:
+ case DL_OK_ACK:
+#ifdef DL_HP_PPA_ACK
+ case DL_HP_PPA_ACK:
+#endif
+
+ /* These are OK */
+ break;
+
+ case DL_ERROR_ACK:
+ switch (dlp->error_ack.dl_errno) {
+
+ case DL_BADPPA:
+ sprintf(ebuf, "recv_ack: %s bad ppa (device unit)",
+ what);
+ break;
+
+
+ case DL_SYSERR:
+ sprintf(ebuf, "recv_ack: %s: %s",
+ what, pcap_strerror(dlp->error_ack.dl_unix_errno));
+ break;
+
+ case DL_UNSUPPORTED:
+ sprintf(ebuf,
+ "recv_ack: %s: Service not supplied by provider",
+ what);
+ break;
+
+ default:
+ sprintf(ebuf, "recv_ack: %s error 0x%x",
+ what, (bpf_u_int32)dlp->error_ack.dl_errno);
+ break;
+ }
+ return (-1);
+
+ default:
+ sprintf(ebuf, "recv_ack: %s unexpected primitive ack 0x%x ",
+ what, (bpf_u_int32)dlp->dl_primitive);
+ return (-1);
+ }
+
+ if (ctl.len < size) {
+ sprintf(ebuf, "recv_ack: %s ack too small (%d < %d)",
+ what, ctl.len, size);
+ return (-1);
+ }
+ return (ctl.len);
+}
+
+static int
+dlattachreq(int fd, bpf_u_int32 ppa, char *ebuf)
+{
+ dl_attach_req_t req;
+
+ req.dl_primitive = DL_ATTACH_REQ;
+ req.dl_ppa = ppa;
+
+ return (send_request(fd, (char *)&req, sizeof(req), "attach", ebuf));
+}
+
+static int
+dlbindreq(int fd, bpf_u_int32 sap, char *ebuf)
+{
+
+ dl_bind_req_t req;
+
+ memset((char *)&req, 0, sizeof(req));
+ req.dl_primitive = DL_BIND_REQ;
+#ifdef DL_HP_RAWDLS
+ req.dl_max_conind = 1; /* XXX magic number */
+ /* 22 is INSAP as per the HP-UX DLPI Programmer's Guide */
+ req.dl_sap = 22;
+ req.dl_service_mode = DL_HP_RAWDLS;
+#else
+ req.dl_sap = sap;
+#ifdef DL_CLDLS
+ req.dl_service_mode = DL_CLDLS;
+#endif
+#endif
+
+ return (send_request(fd, (char *)&req, sizeof(req), "bind", ebuf));
+}
+
+static int
+dlbindack(int fd, char *bufp, char *ebuf)
+{
+
+ return (recv_ack(fd, DL_BIND_ACK_SIZE, "bind", bufp, ebuf));
+}
+
+static int
+dlpromisconreq(int fd, bpf_u_int32 level, char *ebuf)
+{
+ dl_promiscon_req_t req;
+
+ req.dl_primitive = DL_PROMISCON_REQ;
+ req.dl_level = level;
+
+ return (send_request(fd, (char *)&req, sizeof(req), "promiscon", ebuf));
+}
+
+static int
+dlokack(int fd, const char *what, char *bufp, char *ebuf)
+{
+
+ return (recv_ack(fd, DL_OK_ACK_SIZE, what, bufp, ebuf));
+}
+
+
+static int
+dlinforeq(int fd, char *ebuf)
+{
+ dl_info_req_t req;
+
+ req.dl_primitive = DL_INFO_REQ;
+
+ return (send_request(fd, (char *)&req, sizeof(req), "info", ebuf));
+}
+
+static int
+dlinfoack(int fd, char *bufp, char *ebuf)
+{
+
+ return (recv_ack(fd, DL_INFO_ACK_SIZE, "info", bufp, ebuf));
+}
+
+#ifdef HAVE_SYS_BUFMOD_H
+static int
+strioctl(int fd, int cmd, int len, char *dp)
+{
+ struct strioctl str;
+ int rc;
+
+ str.ic_cmd = cmd;
+ str.ic_timout = -1;
+ str.ic_len = len;
+ str.ic_dp = dp;
+ rc = ioctl(fd, I_STR, &str);
+
+ if (rc < 0)
+ return (rc);
+ else
+ return (str.ic_len);
+}
+#endif
+
+#if defined(HAVE_SOLARIS) && defined(HAVE_SYS_BUFMOD_H)
+static char *
+get_release(bpf_u_int32 *majorp, bpf_u_int32 *minorp, bpf_u_int32 *microp)
+{
+ char *cp;
+ static char buf[32];
+
+ *majorp = 0;
+ *minorp = 0;
+ *microp = 0;
+ if (sysinfo(SI_RELEASE, buf, sizeof(buf)) < 0)
+ return ("?");
+ cp = buf;
+ if (!isdigit(*cp))
+ return (buf);
+ *majorp = strtol(cp, &cp, 10);
+ if (*cp++ != '.')
+ return (buf);
+ *minorp = strtol(cp, &cp, 10);
+ if (*cp++ != '.')
+ return (buf);
+ *microp = strtol(cp, &cp, 10);
+ return (buf);
+}
+#endif
+
+#ifdef DL_HP_PPA_ACK_OBS
+/*
+ * Under HP-UX 10, we can ask for the ppa
+ */
+
+
+/* Determine ppa number that specifies ifname */
+static int
+get_dlpi_ppa(register int fd, register const char *device, register int unit,
+ register char *ebuf)
+{
+ register dl_hp_ppa_ack_t *ap;
+ register dl_hp_ppa_info_t *ip;
+ register int i;
+ register u_long majdev;
+ dl_hp_ppa_req_t req;
+ struct stat statbuf;
+ bpf_u_int32 buf[MAXDLBUF];
+
+ if (stat(device, &statbuf) < 0) {
+ sprintf(ebuf, "stat: %s: %s", device, pcap_strerror(errno));
+ return (-1);
+ }
+ majdev = major(statbuf.st_rdev);
+
+ memset((char *)&req, 0, sizeof(req));
+ req.dl_primitive = DL_HP_PPA_REQ;
+
+ memset((char *)buf, 0, sizeof(buf));
+ if (send_request(fd, (char *)&req, sizeof(req), "hpppa", ebuf) < 0 ||
+ recv_ack(fd, DL_HP_PPA_ACK_SIZE, "hpppa", (char *)buf, ebuf) < 0)
+ return (-1);
+
+ ap = (dl_hp_ppa_ack_t *)buf;
+ ip = (dl_hp_ppa_info_t *)((u_char *)ap + ap->dl_offset);
+
+ for(i = 0; i < ap->dl_count; i++) {
+ if (ip->dl_mjr_num == majdev && ip->dl_instance_num == unit)
+ break;
+
+ ip = (dl_hp_ppa_info_t *)((u_char *)ip + ip->dl_next_offset);
+ }
+ if (i == ap->dl_count) {
+ sprintf(ebuf, "can't find PPA for %s", device);
+ return (-1);
+ }
+ if (ip->dl_hdw_state == HDW_DEAD) {
+ sprintf(ebuf, "%s: hardware state: DOWN\n", device);
+ return (-1);
+ }
+ return ((int)ip->dl_ppa);
+}
+#endif
+
+#ifdef HAVE_HPUX9
+/*
+ * Under HP-UX 9, there is no good way to determine the ppa.
+ * So punt and read it from /dev/kmem.
+ */
+static struct nlist nl[] = {
+#define NL_IFNET 0
+ { "ifnet" },
+ { "" }
+};
+
+static char path_vmunix[] = "/hp-ux";
+
+/* Determine ppa number that specifies ifname */
+static int
+get_dlpi_ppa(register int fd, register const char *ifname, register int unit,
+ register char *ebuf)
+{
+ register const char *cp;
+ register int kd;
+ void *addr;
+ struct ifnet ifnet;
+ char if_name[sizeof(ifnet.if_name)], tifname[32];
+
+ cp = strrchr(ifname, '/');
+ if (cp != NULL)
+ ifname = cp + 1;
+ if (nlist(path_vmunix, &nl) < 0) {
+ sprintf(ebuf, "nlist %s failed", path_vmunix);
+ return (-1);
+ }
+ if (nl[NL_IFNET].n_value == 0) {
+ sprintf(ebuf, "could't find %s kernel symbol",
+ nl[NL_IFNET].n_name);
+ return (-1);
+ }
+ kd = open("/dev/kmem", O_RDONLY);
+ if (kd < 0) {
+ sprintf(ebuf, "kmem open: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ if (dlpi_kread(kd, nl[NL_IFNET].n_value,
+ &addr, sizeof(addr), ebuf) < 0) {
+ close(kd);
+ return (-1);
+ }
+ for (; addr != NULL; addr = ifnet.if_next) {
+ if (dlpi_kread(kd, (off_t)addr,
+ &ifnet, sizeof(ifnet), ebuf) < 0 ||
+ dlpi_kread(kd, (off_t)ifnet.if_name,
+ if_name, sizeof(if_name), ebuf) < 0) {
+ (void)close(kd);
+ return (-1);
+ }
+ sprintf(tifname, "%.*s%d",
+ (int)sizeof(if_name), if_name, ifnet.if_unit);
+ if (strcmp(tifname, ifname) == 0)
+ return (ifnet.if_index);
+ }
+
+ sprintf(ebuf, "Can't find %s", ifname);
+ return (-1);
+}
+
+static int
+dlpi_kread(register int fd, register off_t addr,
+ register void *buf, register u_int len, register char *ebuf)
+{
+ register int cc;
+
+ if (lseek(fd, addr, SEEK_SET) < 0) {
+ sprintf(ebuf, "lseek: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ cc = read(fd, buf, len);
+ if (cc < 0) {
+ sprintf(ebuf, "read: %s", pcap_strerror(errno));
+ return (-1);
+ } else if (cc != len) {
+ sprintf(ebuf, "short read (%d != %d)", cc, len);
+ return (-1);
+ }
+ return (cc);
+}
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-enet.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-enet.c
new file mode 100644
index 000000000..3f4189b49
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-enet.c
@@ -0,0 +1,227 @@
+/*
+ * Stanford Enetfilter subroutines for tcpdump
+ *
+ * Based on the MERIT NNstat etherifrt.c and the Ultrix pcap-pf.c
+ * subroutines.
+ *
+ * Rayan Zachariassen, CA*Net
+ */
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/file.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/bpf.h>
+#include <net/enet.h>
+
+#include <netinet/in.h>
+#include <netinet/if_ether.h>
+
+#include <stdio.h>
+#include <errno.h>
+
+#include "interface.h"
+
+struct packet_header {
+#ifdef IBMRTPC
+ struct LengthWords length;
+ struct tap_header tap;
+#endif /* IBMRTPC */
+ u_char packet[8]
+};
+
+extern int errno;
+
+#define BUFSPACE (4*1024)
+
+/* Forwards */
+static void efReadError(int, char *);
+
+void
+readloop(int cnt, int if_fd, struct bpf_program *fp, printfunc printit)
+{
+#ifdef IBMRTPC
+ register struct packet_header *ph;
+ register u_char *bp;
+ register int inc;
+#else /* !IBMRTPC */
+ static struct timeval tv = { 0 };
+#endif /* IBMRTPC */
+ register int cc, caplen;
+ register struct bpf_insn *fcode = fp->bf_insns;
+ union {
+ struct packet_header hdr;
+ u_char p[BUFSPACE];
+ u_short s;
+ } buf;
+
+ while (1) {
+ if ((cc = read(if_fd, (char *)buf.p, sizeof(buf))) < 0)
+ efReadError(if_fd, "reader");
+
+#ifdef IBMRTPC
+ /*
+ * Loop through each packet.
+ */
+ bp = buf.p;
+ while (cc > 0) {
+ ph = (struct packet_header *)bp;
+ caplen = ph->tap.th_wirelen > snaplen ? snaplen : ph->tap
+.th_wirelen ;
+ if (bpf_filter(fcode, (char *)ph->packet,
+ ph->tap.th_wirelen, caplen)) {
+ if (cnt >= 0 && --cnt < 0)
+ goto out;
+ (*printit)((char *)ph->packet,
+ (struct timeval *)ph->tap.th_timestamp,
+ ph->tap.th_wirelen, caplen);
+ }
+ inc = ph->length.PacketOffset;
+ cc -= inc;
+ bp += inc;
+ }
+#else /* !IBMRTPC */
+ caplen = cc > snaplen ? snaplen : cc ;
+ if (bpf_filter(fcode, buf.hdr.packet, cc, caplen)) {
+ if (cnt >= 0 && --cnt < 0)
+ goto out;
+ (*printit)(buf.hdr.packet, &tv, cc, caplen);
+ }
+#endif /* IBMRTPC */
+ }
+ out:
+ wrapup(if_fd);
+}
+
+/* Call ONLY if read() has returned an error on packet filter */
+static void
+efReadError(int fid, char *msg)
+{
+ if (errno == EINVAL) { /* read MAXINT bytes already! */
+ if (lseek(fid, 0, 0) < 0) {
+ perror("tcpdump: efReadError/lseek");
+ exit(-1);
+ }
+ else
+ return;
+ }
+ else {
+ (void) fprintf(stderr, "tcpdump: ");
+ perror(msg);
+ exit(-1);
+ }
+}
+
+void
+wrapup(int fd)
+{
+#ifdef IBMRTPC
+ struct enstats es;
+
+ if (ioctl(fd, EIOSTATS, &es) == -1) {
+ perror("tcpdump: enet ioctl EIOSTATS error");
+ exit(-1);
+ }
+
+ fprintf(stderr, "%d packets queued", es.enStat_Rcnt);
+ if (es.enStat_Rdrops > 0)
+ fprintf(stderr, ", %d dropped", es.enStat_Rdrops);
+ if (es.enStat_Reads > 0)
+ fprintf(stderr, ", %d tcpdump %s", es.enStat_Reads,
+ es.enStat_Reads > 1 ? "reads" : "read");
+ if (es.enStat_MaxRead > 1)
+ fprintf(stderr, ", %d packets in largest read",
+ es.enStat_MaxRead);
+ putc('\n', stderr);
+#endif /* IBMRTPC */
+ close(fd);
+}
+
+int
+initdevice(char *device, int pflag, int *linktype)
+{
+ struct eniocb ctl;
+ struct enfilter filter;
+ u_int maxwaiting;
+ int if_fd;
+
+#ifdef IBMRTPC
+ GETENETDEVICE(0, O_RDONLY, &if_fd);
+#else /* !IBMRTPC */
+ if_fd = open("/dev/enet", O_RDONLY, 0);
+#endif /* IBMRTPC */
+
+ if (if_fd == -1) {
+ perror("tcpdump: enet open error");
+ error(
+"your system may not be properly configured; see \"man enet(4)\"");
+ exit(-1);
+ }
+
+ /* Get operating parameters. */
+
+ if (ioctl(if_fd, EIOCGETP, (char *)&ctl) == -1) {
+ perror("tcpdump: enet ioctl EIOCGETP error");
+ exit(-1);
+ }
+
+ /* Set operating parameters. */
+
+#ifdef IBMRTPC
+ ctl.en_rtout = 1 * ctl.en_hz;
+ ctl.en_tr_etherhead = 1;
+ ctl.en_tap_network = 1;
+ ctl.en_multi_packet = 1;
+ ctl.en_maxlen = BUFSPACE;
+#else /* !IBMRTPC */
+ ctl.en_rtout = 64; /* randomly picked value for HZ */
+#endif /* IBMRTPC */
+ if (ioctl(if_fd, EIOCSETP, &ctl) == -1) {
+ perror("tcpdump: enet ioctl EIOCSETP error");
+ exit(-1);
+ }
+
+ /* Flush the receive queue, since we've changed
+ the operating parameters and we otherwise might
+ receive data without headers. */
+
+ if (ioctl(if_fd, EIOCFLUSH) == -1) {
+ perror("tcpdump: enet ioctl EIOCFLUSH error");
+ exit(-1);
+ }
+
+ /* Set the receive queue depth to its maximum. */
+
+ maxwaiting = ctl.en_maxwaiting;
+ if (ioctl(if_fd, EIOCSETW, &maxwaiting) == -1) {
+ perror("tcpdump: enet ioctl EIOCSETW error");
+ exit(-1);
+ }
+
+#ifdef IBMRTPC
+ /* Clear statistics. */
+
+ if (ioctl(if_fd, EIOCLRSTAT, 0) == -1) {
+ perror("tcpdump: enet ioctl EIOCLRSTAT error");
+ exit(-1);
+ }
+#endif /* IBMRTPC */
+
+ /* Set the filter (accept all packets). */
+
+ filter.enf_Priority = 3;
+ filter.enf_FilterLen = 0;
+ if (ioctl(if_fd, EIOCSETF, &filter) == -1) {
+ perror("tcpdump: enet ioctl EIOCSETF error");
+ exit(-1);
+ }
+ /*
+ * "enetfilter" supports only ethernets.
+ */
+ *linktype = DLT_EN10MB;
+
+ return(if_fd);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-int.h b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-int.h
new file mode 100644
index 000000000..fa6417112
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-int.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the Computer Systems
+ * Engineering Group at Lawrence Berkeley Laboratory.
+ * 4. Neither the name of the University nor of the Laboratory may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-int.h,v 1.1 1999/08/26 10:05:24 johana Exp $ (LBL)
+ */
+
+#ifndef pcap_int_h
+#define pcap_int_h
+
+#include <pcap.h>
+
+/*
+ * Savefile
+ */
+struct pcap_sf {
+ FILE *rfile;
+ int swapped;
+ int version_major;
+ int version_minor;
+ u_char *base;
+};
+
+struct pcap_md {
+ struct pcap_stat stat;
+ /*XXX*/
+ int use_bpf;
+ u_long TotPkts; /* can't oflow for 79 hrs on ether */
+ u_long TotAccepted; /* count accepted by filter */
+ u_long TotDrops; /* count of dropped packets */
+ long TotMissed; /* missed by i/f during this run */
+ long OrigMissed; /* missed by i/f before this run */
+#ifdef linux
+ int pad;
+ int skip;
+ char *device;
+#endif
+};
+
+struct pcap {
+ int fd;
+ int snapshot;
+ int linktype;
+ int tzoff; /* timezone offset */
+ int offset; /* offset for proper alignment */
+
+ struct pcap_sf sf;
+ struct pcap_md md;
+
+ /*
+ * Read buffer.
+ */
+ int bufsize;
+ u_char *buffer;
+ u_char *bp;
+ int cc;
+
+ /*
+ * Place holder for pcap_next().
+ */
+ u_char *pkt;
+
+
+ /*
+ * Placeholder for filter code if bpf not in kernel.
+ */
+ struct bpf_program fcode;
+
+ char errbuf[PCAP_ERRBUF_SIZE];
+};
+
+int yylex(void);
+
+#ifndef min
+#define min(a, b) ((a) > (b) ? (b) : (a))
+#endif
+
+/* XXX should these be in pcap.h? */
+int pcap_offline_read(pcap_t *, int, pcap_handler, u_char *);
+int pcap_read(pcap_t *, int cnt, pcap_handler, u_char *);
+
+/* Ultrix pads to make everything line up on a nice boundary */
+#if defined(ultrix) || defined(__alpha)
+#define PCAP_FDDIPAD 3
+#endif
+
+/* XXX */
+extern int pcap_fddipad;
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-linux.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-linux.c
new file mode 100644
index 000000000..089ea0ab8
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-linux.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-linux.c,v 1.1 1999/08/26 10:05:24 johana Exp $ (LBL)";
+#endif
+
+#include <sys/param.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+#include <sys/time.h>
+
+#include <net/if.h>
+#ifdef HAVE_NET_IF_ARP_H
+#include <net/if_arp.h>
+#else
+#include <linux/if_arp.h>
+#endif
+#include <linux/if_ether.h>
+
+#include <netinet/in.h>
+
+#include <errno.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+static struct ifreq saved_ifr;
+static int read_timout_ms = 0;
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+void linux_restore_ifr(void);
+
+int
+pcap_stats(pcap_t *p, struct pcap_stat *ps)
+{
+
+ *ps = p->md.stat;
+ return (0);
+}
+
+int
+pcap_read(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+ register int cc;
+ register int bufsize;
+ register int caplen;
+ register u_char *bp;
+ struct sockaddr from;
+ int fromlen;
+
+ fd_set mask;
+ struct timeval tv;
+
+ if (read_timout_ms == 0) {
+ tv.tv_sec = 0;
+ tv.tv_usec = 0;
+ }
+ else {
+ tv.tv_sec = read_timout_ms/1000;
+ tv.tv_usec = read_timout_ms%1000;
+ }
+ FD_ZERO(&mask);
+ FD_SET(p->fd, &mask);
+
+ bp = p->buffer + p->offset;
+ bufsize = p->bufsize;
+ if (p->md.pad > 0) {
+ memset(bp, 0, p->md.pad);
+ bp += p->md.pad;
+ bufsize -= p->md.pad;
+ }
+
+again:
+ do {
+ fromlen = sizeof(from);
+ select(FD_SETSIZE, &mask, NULL, NULL, &tv);
+ if (FD_ISSET(p->fd, &mask) == 0) {
+ return (0);
+ }
+
+ cc = recvfrom(p->fd, bp, bufsize, 0, &from, &fromlen);
+ if (cc < 0) {
+ /* Don't choke when we get ptraced */
+ switch (errno) {
+
+ case EINTR:
+ goto again;
+
+ case EWOULDBLOCK:
+ return (0); /* XXX */
+ }
+ sprintf(p->errbuf, "read: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ } while (strcmp(p->md.device, from.sa_data));
+
+ /* If we need have leading zero bytes, adjust count */
+ cc += p->md.pad;
+ bp = p->buffer + p->offset;
+
+ /* If we need to step over leading junk, adjust count and pointer */
+ cc -= p->md.skip;
+ bp += p->md.skip;
+
+ /* Captured length can't exceed our read buffer size */
+ caplen = cc;
+ if (caplen > bufsize)
+ caplen = bufsize;
+
+ /* Captured length can't exceed the snapshot length */
+ if (caplen > p->snapshot)
+ caplen = p->snapshot;
+
+ if (p->fcode.bf_insns == NULL ||
+ bpf_filter(p->fcode.bf_insns, bp, cc, caplen)) {
+ struct pcap_pkthdr h;
+
+ ++p->md.stat.ps_recv;
+ /* Get timestamp */
+ if (ioctl(p->fd, SIOCGSTAMP, &h.ts) < 0) {
+ sprintf(p->errbuf, "SIOCGSTAMP: %s",
+ pcap_strerror(errno));
+ return (-1);
+ }
+ h.len = cc;
+ h.caplen = caplen;
+ (*callback)(user, &h, bp);
+ return (1);
+ }
+ return (0);
+}
+
+pcap_t *
+pcap_open_live(char *device, int snaplen, int promisc, int to_ms, char *ebuf)
+{
+ register int fd, broadcast;
+ register pcap_t *p;
+ struct ifreq ifr;
+ struct sockaddr sa;
+
+ read_timout_ms = to_ms;
+ p = (pcap_t *)malloc(sizeof(*p));
+ if (p == NULL) {
+ sprintf(ebuf, "malloc: %s", pcap_strerror(errno));
+ return (NULL);
+ }
+ memset(p, 0, sizeof(*p));
+ fd = -1;
+
+ fd = socket(PF_INET, SOCK_PACKET, htons(ETH_P_ALL));
+ if (fd < 0) {
+ sprintf(ebuf, "socket: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ p->fd = fd;
+
+ /* Bind to the interface name */
+ memset(&sa, 0, sizeof(sa));
+ sa.sa_family = AF_INET;
+ (void)strncpy(sa.sa_data, device, sizeof(sa.sa_data));
+ if (bind(p->fd, &sa, sizeof(sa))) {
+ sprintf(ebuf, "bind: %s: %s", device, pcap_strerror(errno));
+ goto bad;
+ }
+
+ memset(&ifr, 0, sizeof(ifr));
+ strncpy(ifr.ifr_name, device, sizeof(ifr.ifr_name));
+ if (ioctl(p->fd, SIOCGIFHWADDR, &ifr) < 0 ) {
+ sprintf(ebuf, "SIOCGIFHWADDR: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ broadcast = 0;
+ switch (ifr.ifr_hwaddr.sa_family) {
+
+ case ARPHRD_ETHER:
+ case ARPHRD_METRICOM:
+ p->linktype = DLT_EN10MB;
+ p->offset = 2;
+ ++broadcast;
+ break;
+
+ case ARPHRD_EETHER:
+ p->linktype = DLT_EN3MB;
+ ++broadcast;
+ break;
+
+ case ARPHRD_AX25:
+ p->linktype = DLT_AX25;
+ ++broadcast;
+ break;
+
+ case ARPHRD_PRONET:
+ p->linktype = DLT_PRONET;
+ break;
+
+ case ARPHRD_CHAOS:
+ p->linktype = DLT_CHAOS;
+ break;
+
+ case ARPHRD_IEEE802:
+ p->linktype = DLT_IEEE802;
+ ++broadcast;
+ break;
+
+ case ARPHRD_ARCNET:
+ p->linktype = DLT_ARCNET;
+ ++broadcast;
+ break;
+
+ case ARPHRD_SLIP:
+ case ARPHRD_CSLIP:
+ case ARPHRD_SLIP6:
+ case ARPHRD_CSLIP6:
+ case ARPHRD_PPP:
+ p->linktype = DLT_RAW;
+ break;
+
+ case ARPHRD_LOOPBACK:
+ p->linktype = DLT_NULL;
+ p->md.pad = 2;
+ p->md.skip = 12;
+ break;
+
+#ifdef ARPHRD_FDDI
+ /* Not all versions of the kernel has this define */
+ case ARPHRD_FDDI:
+ p->linktype = DLT_FDDI;
+ ++broadcast;
+ break;
+#endif
+
+#ifdef notdef
+ case ARPHRD_LOCALTLK:
+ case ARPHRD_NETROM:
+ case ARPHRD_APPLETLK:
+ case ARPHRD_DLCI:
+ case ARPHRD_RSRVD:
+ case ARPHRD_ADAPT:
+ case ARPHRD_TUNNEL:
+ case ARPHRD_TUNNEL6:
+ case ARPHRD_FRAD:
+ case ARPHRD_SKIP:
+ /* XXX currently do not know what to do with these... */
+ abort();
+#endif
+
+ default:
+ sprintf(ebuf, "unknown physical layer type 0x%x",
+ ifr.ifr_hwaddr.sa_family);
+ goto bad;
+ }
+
+ /* Base the buffer size on the interface MTU */
+ memset(&ifr, 0, sizeof(ifr));
+ strncpy(ifr.ifr_name, device, sizeof(ifr.ifr_name));
+ if (ioctl(p->fd, SIOCGIFMTU, &ifr) < 0 ) {
+ sprintf(ebuf, "SIOCGIFMTU: %s", pcap_strerror(errno));
+ goto bad;
+ }
+
+ /* Leave room for link header (which is never large under linux...) */
+ p->bufsize = ifr.ifr_mtu + 64;
+
+ p->buffer = (u_char *)malloc(p->bufsize + p->offset);
+ if (p->buffer == NULL) {
+ sprintf(ebuf, "malloc: %s", pcap_strerror(errno));
+ goto bad;
+ }
+
+ /* XXX */
+ if (promisc && broadcast) {
+ memset(&ifr, 0, sizeof(ifr));
+ strcpy(ifr.ifr_name, device);
+ if (ioctl(p->fd, SIOCGIFFLAGS, &ifr) < 0 ) {
+ sprintf(ebuf, "SIOCGIFFLAGS: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ saved_ifr = ifr;
+ ifr.ifr_flags |= IFF_PROMISC;
+ if (ioctl(p->fd, SIOCSIFFLAGS, &ifr) < 0 ) {
+ sprintf(ebuf, "SIOCSIFFLAGS: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ ifr.ifr_flags &= ~IFF_PROMISC;
+ atexit(linux_restore_ifr);
+ }
+
+ p->md.device = strdup(device);
+ if (p->md.device == NULL) {
+ sprintf(ebuf, "malloc: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ p->snapshot = snaplen;
+
+ return (p);
+bad:
+ if (fd >= 0)
+ (void)close(fd);
+ if (p->buffer != NULL)
+ free(p->buffer);
+ if (p->md.device != NULL)
+ free(p->md.device);
+ free(p);
+ return (NULL);
+}
+
+int
+pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+{
+
+ p->fcode = *fp;
+ return (0);
+}
+
+void
+linux_restore_ifr(void)
+{
+ register int fd;
+
+ fd = socket(PF_INET, SOCK_PACKET, htons(0x0003));
+ if (fd < 0)
+ fprintf(stderr, "linux socket: %s", pcap_strerror(errno));
+ else if (ioctl(fd, SIOCSIFFLAGS, &saved_ifr) < 0)
+ fprintf(stderr, "linux SIOCSIFFLAGS: %s", pcap_strerror(errno));
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-namedb.h b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-namedb.h
new file mode 100644
index 000000000..67b4bd26c
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-namedb.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 1994, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the Computer Systems
+ * Engineering Group at Lawrence Berkeley Laboratory.
+ * 4. Neither the name of the University nor of the Laboratory may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-namedb.h,v 1.1 1999/08/26 10:05:24 johana Exp $ (LBL)
+ */
+
+#ifndef lib_pcap_ethers_h
+#define lib_pcap_ethers_h
+
+/*
+ * As returned by the pcap_next_etherent()
+ * XXX this stuff doesn't belong in this interface, but this
+ * library already must do name to address translation, so
+ * on systems that don't have support for /etc/ethers, we
+ * export these hooks since they'll
+ */
+struct pcap_etherent {
+ u_char addr[6];
+ char name[122];
+};
+#ifndef PCAP_ETHERS_FILE
+#define PCAP_ETHERS_FILE "/etc/ethers"
+#endif
+struct pcap_etherent *pcap_next_etherent(FILE *);
+u_char *pcap_ether_hostton(const char*);
+u_char *pcap_ether_aton(const char *);
+
+bpf_u_int32 **pcap_nametoaddr(const char *);
+bpf_u_int32 pcap_nametonetaddr(const char *);
+
+int pcap_nametoport(const char *, int *, int *);
+int pcap_nametoproto(const char *);
+int pcap_nametoeproto(const char *);
+/*
+ * If a protocol is unknown, PROTO_UNDEF is returned.
+ * Also, pcap_nametoport() returns the protocol along with the port number.
+ * If there are ambiguous entried in /etc/services (i.e. domain
+ * can be either tcp or udp) PROTO_UNDEF is returned.
+ */
+#define PROTO_UNDEF -1
+
+/* XXX move these to pcap-int.h? */
+int __pcap_atodn(const char *, bpf_u_int32 *);
+int __pcap_atoin(const char *, bpf_u_int32 *);
+u_short __pcap_nametodnaddr(const char *);
+
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-nit.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-nit.c
new file mode 100644
index 000000000..f3c79b272
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-nit.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-nit.c,v 1.1 1999/08/26 10:05:24 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/timeb.h>
+#include <sys/file.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+
+#include <net/if.h>
+#include <net/nit.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#include <netinet/ip_var.h>
+#include <netinet/udp.h>
+#include <netinet/udp_var.h>
+#include <netinet/tcp.h>
+#include <netinet/tcpip.h>
+
+#include <ctype.h>
+#include <errno.h>
+#include <stdio.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+/*
+ * The chunk size for NIT. This is the amount of buffering
+ * done for read calls.
+ */
+#define CHUNKSIZE (2*1024)
+
+/*
+ * The total buffer space used by NIT.
+ */
+#define BUFSPACE (4*CHUNKSIZE)
+
+/* Forwards */
+static int nit_setflags(int, int, int, char *);
+
+int
+pcap_stats(pcap_t *p, struct pcap_stat *ps)
+{
+
+ *ps = p->md.stat;
+ return (0);
+}
+
+int
+pcap_read(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+ register int cc, n;
+ register struct bpf_insn *fcode = p->fcode.bf_insns;
+ register u_char *bp, *cp, *ep;
+ register struct nit_hdr *nh;
+ register int caplen;
+
+ cc = p->cc;
+ if (cc == 0) {
+ cc = read(p->fd, (char *)p->buffer, p->bufsize);
+ if (cc < 0) {
+ if (errno == EWOULDBLOCK)
+ return (0);
+ sprintf(p->errbuf, "pcap_read: %s",
+ pcap_strerror(errno));
+ return (-1);
+ }
+ bp = p->buffer;
+ } else
+ bp = p->bp;
+
+ /*
+ * Loop through each packet. The increment expression
+ * rounds up to the next int boundary past the end of
+ * the previous packet.
+ */
+ n = 0;
+ ep = bp + cc;
+ while (bp < ep) {
+ nh = (struct nit_hdr *)bp;
+ cp = bp + sizeof(*nh);
+
+ switch (nh->nh_state) {
+
+ case NIT_CATCH:
+ break;
+
+ case NIT_NOMBUF:
+ case NIT_NOCLUSTER:
+ case NIT_NOSPACE:
+ p->md.stat.ps_drop = nh->nh_dropped;
+ continue;
+
+ case NIT_SEQNO:
+ continue;
+
+ default:
+ sprintf(p->errbuf, "bad nit state %d", nh->nh_state);
+ return (-1);
+ }
+ ++p->md.stat.ps_recv;
+ bp += ((sizeof(struct nit_hdr) + nh->nh_datalen +
+ sizeof(int) - 1) & ~(sizeof(int) - 1));
+
+ caplen = nh->nh_wirelen;
+ if (caplen > p->snapshot)
+ caplen = p->snapshot;
+ if (bpf_filter(fcode, cp, nh->nh_wirelen, caplen)) {
+ struct pcap_pkthdr h;
+ h.ts = nh->nh_timestamp;
+ h.len = nh->nh_wirelen;
+ h.caplen = caplen;
+ (*callback)(user, &h, cp);
+ if (++n >= cnt && cnt >= 0) {
+ p->cc = ep - bp;
+ p->bp = bp;
+ return (n);
+ }
+ }
+ }
+ p->cc = 0;
+ return (n);
+}
+
+static int
+nit_setflags(int fd, int promisc, int to_ms, char *ebuf)
+{
+ struct nit_ioc nioc;
+
+ bzero((char *)&nioc, sizeof(nioc));
+ nioc.nioc_bufspace = BUFSPACE;
+ nioc.nioc_chunksize = CHUNKSIZE;
+ nioc.nioc_typetomatch = NT_ALLTYPES;
+ nioc.nioc_snaplen = p->snapshot;
+ nioc.nioc_bufalign = sizeof(int);
+ nioc.nioc_bufoffset = 0;
+
+ if (to_ms != 0) {
+ nioc.nioc_flags |= NF_TIMEOUT;
+ nioc.nioc_timeout.tv_sec = to_ms / 1000;
+ nioc.nioc_timeout.tv_usec = (to_ms * 1000) % 1000000;
+ }
+ if (promisc)
+ nioc.nioc_flags |= NF_PROMISC;
+
+ if (ioctl(fd, SIOCSNIT, &nioc) < 0) {
+ sprintf(ebuf, "SIOCSNIT: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ return (0);
+}
+
+pcap_t *
+pcap_open_live(char *device, int snaplen, int promisc, int to_ms, char *ebuf)
+{
+ int fd;
+ struct sockaddr_nit snit;
+ register pcap_t *p;
+
+ p = (pcap_t *)malloc(sizeof(*p));
+ if (p == NULL) {
+ strcpy(ebuf, pcap_strerror(errno));
+ return (NULL);
+ }
+
+ if (snaplen < 96)
+ /*
+ * NIT requires a snapshot length of at least 96.
+ */
+ snaplen = 96;
+
+ bzero(p, sizeof(*p));
+ p->fd = fd = socket(AF_NIT, SOCK_RAW, NITPROTO_RAW);
+ if (fd < 0) {
+ sprintf(ebuf, "socket: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ snit.snit_family = AF_NIT;
+ (void)strncpy(snit.snit_ifname, device, NITIFSIZ);
+
+ if (bind(fd, (struct sockaddr *)&snit, sizeof(snit))) {
+ sprintf(ebuf, "bind: %s: %s", snit.snit_ifname,
+ pcap_strerror(errno));
+ goto bad;
+ }
+ p->snapshot = snaplen;
+ nit_setflags(p->fd, promisc, to_ms, ebuf);
+
+ /*
+ * NIT supports only ethernets.
+ */
+ p->linktype = DLT_EN10MB;
+
+ p->bufsize = BUFSPACE;
+ p->buffer = (u_char *)malloc(p->bufsize);
+ if (p->buffer == NULL) {
+ strcpy(ebuf, pcap_strerror(errno));
+ goto bad;
+ }
+ return (p);
+ bad:
+ if (fd >= 0)
+ close(fd);
+ free(p);
+ return (NULL);
+}
+
+int
+pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+{
+
+ p->fcode = *fp;
+ return (0);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-nit.h b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-nit.h
new file mode 100644
index 000000000..f317fcad8
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-nit.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 1990, 1994
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Lawrence Berkeley Laboratory,
+ * Berkeley, CA. The name of the University may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-nit.h,v 1.1 1999/08/26 10:05:25 johana Exp $ (LBL)
+ */
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-null.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-null.c
new file mode 100644
index 000000000..e32753846
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-null.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-null.c,v 1.1 1999/08/26 10:05:25 johana Exp $ (LBL)";
+#endif
+
+#include <sys/param.h> /* optionally get BSD define */
+
+#include <string.h>
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#include "pcap-int.h"
+
+static char nosup[] = "live packet capture not supported on this system";
+
+int
+pcap_stats(pcap_t *p, struct pcap_stat *ps)
+{
+
+ (void)sprintf(p->errbuf, "pcap_stats: %s", nosup);
+ return (-1);
+}
+
+int
+pcap_read(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+
+ (void)sprintf(p->errbuf, "pcap_read: %s", nosup);
+ return (-1);
+}
+
+pcap_t *
+pcap_open_live(char *device, int snaplen, int promisc, int to_ms, char *ebuf)
+{
+
+ (void)strcpy(ebuf, nosup);
+ return (NULL);
+}
+
+int
+pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+{
+
+ if (p->sf.rfile == NULL) {
+ (void)sprintf(p->errbuf, "pcap_setfilter: %s", nosup);
+ return (-1);
+ }
+ p->fcode = *fp;
+ return (0);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-pf.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-pf.c
new file mode 100644
index 000000000..9d5c94bba
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-pf.c
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * packet filter subroutines for tcpdump
+ * Extraction/creation by Jeffrey Mogul, DECWRL
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-pf.c,v 1.1 1999/08/26 10:05:25 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/timeb.h>
+#include <sys/socket.h>
+#include <sys/file.h>
+#include <sys/ioctl.h>
+#include <net/pfilt.h>
+
+#if __STDC__
+struct mbuf;
+struct rtentry;
+#endif
+
+#include <net/if.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#include <netinet/ip_var.h>
+#include <netinet/udp.h>
+#include <netinet/udp_var.h>
+#include <netinet/tcp.h>
+#include <netinet/tcpip.h>
+
+#include <ctype.h>
+#include <errno.h>
+#include <netdb.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+/*
+ * BUFSPACE is the size in bytes of the packet read buffer. Most tcpdump
+ * applications aren't going to need more than 200 bytes of packet header
+ * and the read shouldn't return more packets than packetfilter's internal
+ * queue limit (bounded at 256).
+ */
+#define BUFSPACE (200 * 256)
+
+int
+pcap_read(pcap_t *pc, int cnt, pcap_handler callback, u_char *user)
+{
+ register u_char *p, *bp;
+ struct bpf_insn *fcode;
+ register int cc, n, buflen, inc;
+ register struct enstamp *sp;
+#ifdef LBL_ALIGN
+ struct enstamp stamp;
+#endif
+#ifdef PCAP_FDDIPAD
+ register int pad;
+#endif
+
+ fcode = pc->md.use_bpf ? NULL : pc->fcode.bf_insns;
+ again:
+ cc = pc->cc;
+ if (cc == 0) {
+ cc = read(pc->fd, (char *)pc->buffer + pc->offset, pc->bufsize);
+ if (cc < 0) {
+ if (errno == EWOULDBLOCK)
+ return (0);
+ if (errno == EINVAL &&
+ lseek(pc->fd, 0L, SEEK_CUR) + pc->bufsize < 0) {
+ /*
+ * Due to a kernel bug, after 2^31 bytes,
+ * the kernel file offset overflows and
+ * read fails with EINVAL. The lseek()
+ * to 0 will fix things.
+ */
+ (void)lseek(pc->fd, 0L, SEEK_SET);
+ goto again;
+ }
+ sprintf(pc->errbuf, "pf read: %s",
+ pcap_strerror(errno));
+ return (-1);
+ }
+ bp = pc->buffer + pc->offset;
+ } else
+ bp = pc->bp;
+ /*
+ * Loop through each packet.
+ */
+ n = 0;
+#ifdef PCAP_FDDIPAD
+ if (pc->linktype == DLT_FDDI)
+ pad = pcap_fddipad;
+ else
+ pad = 0;
+#endif
+ while (cc > 0) {
+ if (cc < sizeof(*sp)) {
+ sprintf(pc->errbuf, "pf short read (%d)", cc);
+ return (-1);
+ }
+#ifdef LBL_ALIGN
+ if ((long)bp & 3) {
+ sp = &stamp;
+ memcpy((char *)sp, (char *)bp, sizeof(*sp));
+ } else
+#endif
+ sp = (struct enstamp *)bp;
+ if (sp->ens_stamplen != sizeof(*sp)) {
+ sprintf(pc->errbuf, "pf short stamplen (%d)",
+ sp->ens_stamplen);
+ return (-1);
+ }
+
+ p = bp + sp->ens_stamplen;
+ buflen = sp->ens_count;
+ if (buflen > pc->snapshot)
+ buflen = pc->snapshot;
+
+ /* Calculate inc before possible pad update */
+ inc = ENALIGN(buflen + sp->ens_stamplen);
+ cc -= inc;
+ bp += inc;
+#ifdef PCAP_FDDIPAD
+ p += pad;
+ buflen -= pad;
+#endif
+ pc->md.TotPkts++;
+ pc->md.TotDrops += sp->ens_dropped;
+ pc->md.TotMissed = sp->ens_ifoverflows;
+ if (pc->md.OrigMissed < 0)
+ pc->md.OrigMissed = pc->md.TotMissed;
+
+ /*
+ * Short-circuit evaluation: if using BPF filter
+ * in kernel, no need to do it now.
+ */
+ if (fcode == NULL ||
+ bpf_filter(fcode, p, sp->ens_count, buflen)) {
+ struct pcap_pkthdr h;
+ pc->md.TotAccepted++;
+ h.ts = sp->ens_tstamp;
+#ifdef PCAP_FDDIPAD
+ h.len = sp->ens_count - pad;
+#else
+ h.len = sp->ens_count;
+#endif
+ h.caplen = buflen;
+ (*callback)(user, &h, p);
+ if (++n >= cnt && cnt > 0) {
+ pc->cc = cc;
+ pc->bp = bp;
+ return (n);
+ }
+ }
+ }
+ pc->cc = 0;
+ return (n);
+}
+
+int
+pcap_stats(pcap_t *p, struct pcap_stat *ps)
+{
+
+ ps->ps_recv = p->md.TotAccepted;
+ ps->ps_drop = p->md.TotDrops;
+ ps->ps_ifdrop = p->md.TotMissed - p->md.OrigMissed;
+ return (0);
+}
+
+pcap_t *
+pcap_open_live(char *device, int snaplen, int promisc, int to_ms, char *ebuf)
+{
+ pcap_t *p;
+ short enmode;
+ int backlog = -1; /* request the most */
+ struct enfilter Filter;
+ struct endevp devparams;
+
+ p = (pcap_t *)malloc(sizeof(*p));
+ if (p == NULL) {
+ sprintf(ebuf, "pcap_open_live: %s", pcap_strerror(errno));
+ return (0);
+ }
+ bzero((char *)p, sizeof(*p));
+ p->fd = pfopen(device, O_RDONLY);
+ if (p->fd < 0) {
+ sprintf(ebuf, "pf open: %s: %s\n\
+your system may not be properly configured; see \"man packetfilter(4)\"\n",
+ device, pcap_strerror(errno));
+ goto bad;
+ }
+ p->md.OrigMissed = -1;
+ enmode = ENTSTAMP|ENBATCH|ENNONEXCL;
+ if (promisc)
+ enmode |= ENPROMISC;
+ if (ioctl(p->fd, EIOCMBIS, (caddr_t)&enmode) < 0) {
+ sprintf(ebuf, "EIOCMBIS: %s", pcap_strerror(errno));
+ goto bad;
+ }
+#ifdef ENCOPYALL
+ /* Try to set COPYALL mode so that we see packets to ourself */
+ enmode = ENCOPYALL;
+ (void)ioctl(p->fd, EIOCMBIS, (caddr_t)&enmode);/* OK if this fails */
+#endif
+ /* set the backlog */
+ if (ioctl(p->fd, EIOCSETW, (caddr_t)&backlog) < 0) {
+ sprintf(ebuf, "EIOCSETW: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ /* discover interface type */
+ if (ioctl(p->fd, EIOCDEVP, (caddr_t)&devparams) < 0) {
+ sprintf(ebuf, "EIOCDEVP: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ /* HACK: to compile prior to Ultrix 4.2 */
+#ifndef ENDT_FDDI
+#define ENDT_FDDI 4
+#endif
+ switch (devparams.end_dev_type) {
+
+ case ENDT_10MB:
+ p->linktype = DLT_EN10MB;
+ p->offset = 2;
+ break;
+
+ case ENDT_FDDI:
+ p->linktype = DLT_FDDI;
+ break;
+
+ default:
+ /*
+ * XXX
+ * Currently, the Ultrix packet filter supports only
+ * Ethernet and FDDI. Eventually, support for SLIP and PPP
+ * (and possibly others: T1?) should be added.
+ */
+#ifdef notdef
+ warning(
+ "Packet filter data-link type %d unknown, assuming Ethernet",
+ devparams.end_dev_type);
+#endif
+ p->linktype = DLT_EN10MB;
+ p->offset = 2;
+ break;
+ }
+ /* set truncation */
+#ifdef PCAP_FDDIPAD
+ if (p->linktype == DLT_FDDI)
+ /* packetfilter includes the padding in the snapshot */
+ snaplen += pcap_fddipad;
+#endif
+ if (ioctl(p->fd, EIOCTRUNCATE, (caddr_t)&snaplen) < 0) {
+ sprintf(ebuf, "EIOCTRUNCATE: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ p->snapshot = snaplen;
+ /* accept all packets */
+ bzero((char *)&Filter, sizeof(Filter));
+ Filter.enf_Priority = 37; /* anything > 2 */
+ Filter.enf_FilterLen = 0; /* means "always true" */
+ if (ioctl(p->fd, EIOCSETF, (caddr_t)&Filter) < 0) {
+ sprintf(ebuf, "EIOCSETF: %s", pcap_strerror(errno));
+ goto bad;
+ }
+
+ if (to_ms != 0) {
+ struct timeval timeout;
+ timeout.tv_sec = to_ms / 1000;
+ timeout.tv_usec = (to_ms * 1000) % 1000000;
+ if (ioctl(p->fd, EIOCSRTIMEOUT, (caddr_t)&timeout) < 0) {
+ sprintf(ebuf, "EIOCSRTIMEOUT: %s",
+ pcap_strerror(errno));
+ goto bad;
+ }
+ }
+ p->bufsize = BUFSPACE;
+ p->buffer = (u_char*)malloc(p->bufsize + p->offset);
+
+ return (p);
+ bad:
+ free(p);
+ return (NULL);
+}
+
+int
+pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+{
+ /*
+ * See if BIOCSETF works. If it does, the kernel supports
+ * BPF-style filters, and we do not need to do post-filtering.
+ */
+ p->md.use_bpf = (ioctl(p->fd, BIOCSETF, (caddr_t)fp) >= 0);
+ if (p->md.use_bpf) {
+ struct bpf_version bv;
+
+ if (ioctl(p->fd, BIOCVERSION, (caddr_t)&bv) < 0) {
+ sprintf(p->errbuf, "BIOCVERSION: %s",
+ pcap_strerror(errno));
+ return (-1);
+ }
+ else if (bv.bv_major != BPF_MAJOR_VERSION ||
+ bv.bv_minor < BPF_MINOR_VERSION) {
+ fprintf(stderr,
+ "requires bpf language %d.%d or higher; kernel is %d.%d",
+ BPF_MAJOR_VERSION, BPF_MINOR_VERSION,
+ bv.bv_major, bv.bv_minor);
+ /* don't give up, just be inefficient */
+ p->md.use_bpf = 0;
+ }
+ } else
+ p->fcode = *fp;
+
+ /*XXX this goes in tcpdump*/
+ if (p->md.use_bpf)
+ fprintf(stderr, "tcpdump: Using kernel BPF filter\n");
+ else
+ fprintf(stderr, "tcpdump: Filtering in user process\n");
+ return (0);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-pf.h b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-pf.h
new file mode 100644
index 000000000..d0953d76a
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-pf.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 1990, 1994
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the above copyright notice and this paragraph are
+ * duplicated in all such forms and that any documentation,
+ * advertising materials, and other materials related to such
+ * distribution and use acknowledge that the software was developed
+ * by the University of California, Lawrence Berkeley Laboratory,
+ * Berkeley, CA. The name of the University may not be used to
+ * endorse or promote products derived from this software without
+ * specific prior written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
+ * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-pf.h,v 1.1 1999/08/26 10:05:25 johana Exp $ (LBL)
+ */
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-snit.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-snit.c
new file mode 100644
index 000000000..56f75fa62
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-snit.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 1990, 1991, 1992, 1993, 1994, 1995, 1996
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * Modifications made to accommodate the new SunOS4.0 NIT facility by
+ * Micky Liu, micky@cunixc.cc.columbia.edu, Columbia University in May, 1989.
+ * This module now handles the STREAMS based NIT.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-snit.c,v 1.1 1999/08/26 10:05:25 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+#include <sys/timeb.h>
+#include <sys/dir.h>
+#include <sys/fcntlcom.h>
+#include <sys/file.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+#include <sys/stropts.h>
+
+#include <net/if.h>
+#include <net/nit.h>
+#include <net/nit_if.h>
+#include <net/nit_pf.h>
+#include <net/nit_buf.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#include <netinet/ip_var.h>
+#include <netinet/udp.h>
+#include <netinet/udp_var.h>
+#include <netinet/tcp.h>
+#include <netinet/tcpip.h>
+
+#include <ctype.h>
+#include <errno.h>
+#ifdef HAVE_MALLOC_H
+#include <malloc.h>
+#endif
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+/*
+ * The chunk size for NIT. This is the amount of buffering
+ * done for read calls.
+ */
+#define CHUNKSIZE (2*1024)
+
+/*
+ * The total buffer space used by NIT.
+ */
+#define BUFSPACE (4*CHUNKSIZE)
+
+/* Forwards */
+static int nit_setflags(int, int, int, char *);
+
+int
+pcap_stats(pcap_t *p, struct pcap_stat *ps)
+{
+
+ *ps = p->md.stat;
+ return (0);
+}
+
+int
+pcap_read(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+ register int cc, n;
+ register struct bpf_insn *fcode = p->fcode.bf_insns;
+ register u_char *bp, *cp, *ep;
+ register struct nit_bufhdr *hdrp;
+ register struct nit_iftime *ntp;
+ register struct nit_iflen *nlp;
+ register struct nit_ifdrops *ndp;
+ register int caplen;
+
+ cc = p->cc;
+ if (cc == 0) {
+ cc = read(p->fd, (char *)p->buffer, p->bufsize);
+ if (cc < 0) {
+ if (errno == EWOULDBLOCK)
+ return (0);
+ sprintf(p->errbuf, "pcap_read: %s",
+ pcap_strerror(errno));
+ return (-1);
+ }
+ bp = p->buffer;
+ } else
+ bp = p->bp;
+
+ /*
+ * loop through each snapshot in the chunk
+ */
+ n = 0;
+ ep = bp + cc;
+ while (bp < ep) {
+ ++p->md.stat.ps_recv;
+ cp = bp;
+
+ /* get past NIT buffer */
+ hdrp = (struct nit_bufhdr *)cp;
+ cp += sizeof(*hdrp);
+
+ /* get past NIT timer */
+ ntp = (struct nit_iftime *)cp;
+ cp += sizeof(*ntp);
+
+ ndp = (struct nit_ifdrops *)cp;
+ p->md.stat.ps_drop = ndp->nh_drops;
+ cp += sizeof *ndp;
+
+ /* get past packet len */
+ nlp = (struct nit_iflen *)cp;
+ cp += sizeof(*nlp);
+
+ /* next snapshot */
+ bp += hdrp->nhb_totlen;
+
+ caplen = nlp->nh_pktlen;
+ if (caplen > p->snapshot)
+ caplen = p->snapshot;
+
+ if (bpf_filter(fcode, cp, nlp->nh_pktlen, caplen)) {
+ struct pcap_pkthdr h;
+ h.ts = ntp->nh_timestamp;
+ h.len = nlp->nh_pktlen;
+ h.caplen = caplen;
+ (*callback)(user, &h, cp);
+ if (++n >= cnt && cnt >= 0) {
+ p->cc = ep - bp;
+ p->bp = bp;
+ return (n);
+ }
+ }
+ }
+ p->cc = 0;
+ return (n);
+}
+
+static int
+nit_setflags(int fd, int promisc, int to_ms, char *ebuf)
+{
+ bpf_u_int32 flags;
+ struct strioctl si;
+ struct timeval timeout;
+
+ si.ic_timout = INFTIM;
+ if (to_ms != 0) {
+ timeout.tv_sec = to_ms / 1000;
+ timeout.tv_usec = (to_ms * 1000) % 1000000;
+ si.ic_cmd = NIOCSTIME;
+ si.ic_len = sizeof(timeout);
+ si.ic_dp = (char *)&timeout;
+ if (ioctl(fd, I_STR, (char *)&si) < 0) {
+ sprintf(ebuf, "NIOCSTIME: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ }
+ flags = NI_TIMESTAMP | NI_LEN | NI_DROPS;
+ if (promisc)
+ flags |= NI_PROMISC;
+ si.ic_cmd = NIOCSFLAGS;
+ si.ic_len = sizeof(flags);
+ si.ic_dp = (char *)&flags;
+ if (ioctl(fd, I_STR, (char *)&si) < 0) {
+ sprintf(ebuf, "NIOCSFLAGS: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ return (0);
+}
+
+pcap_t *
+pcap_open_live(char *device, int snaplen, int promisc, int to_ms, char *ebuf)
+{
+ struct strioctl si; /* struct for ioctl() */
+ struct ifreq ifr; /* interface request struct */
+ int chunksize = CHUNKSIZE;
+ int fd;
+ static char dev[] = "/dev/nit";
+ register pcap_t *p;
+
+ p = (pcap_t *)malloc(sizeof(*p));
+ if (p == NULL) {
+ strcpy(ebuf, pcap_strerror(errno));
+ return (NULL);
+ }
+
+ if (snaplen < 96)
+ /*
+ * NIT requires a snapshot length of at least 96.
+ */
+ snaplen = 96;
+
+ bzero(p, sizeof(*p));
+ p->fd = fd = open(dev, O_RDONLY);
+ if (fd < 0) {
+ sprintf(ebuf, "%s: %s", dev, pcap_strerror(errno));
+ goto bad;
+ }
+
+ /* arrange to get discrete messages from the STREAM and use NIT_BUF */
+ if (ioctl(fd, I_SRDOPT, (char *)RMSGD) < 0) {
+ sprintf(ebuf, "I_SRDOPT: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ if (ioctl(fd, I_PUSH, "nbuf") < 0) {
+ sprintf(ebuf, "push nbuf: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ /* set the chunksize */
+ si.ic_cmd = NIOCSCHUNK;
+ si.ic_timout = INFTIM;
+ si.ic_len = sizeof(chunksize);
+ si.ic_dp = (char *)&chunksize;
+ if (ioctl(fd, I_STR, (char *)&si) < 0) {
+ sprintf(ebuf, "NIOCSCHUNK: %s", pcap_strerror(errno));
+ goto bad;
+ }
+
+ /* request the interface */
+ strncpy(ifr.ifr_name, device, sizeof(ifr.ifr_name));
+ ifr.ifr_name[sizeof(ifr.ifr_name) - 1] = ' ';
+ si.ic_cmd = NIOCBIND;
+ si.ic_len = sizeof(ifr);
+ si.ic_dp = (char *)&ifr;
+ if (ioctl(fd, I_STR, (char *)&si) < 0) {
+ sprintf(ebuf, "NIOCBIND: %s: %s",
+ ifr.ifr_name, pcap_strerror(errno));
+ goto bad;
+ }
+
+ /* set the snapshot length */
+ si.ic_cmd = NIOCSSNAP;
+ si.ic_len = sizeof(snaplen);
+ si.ic_dp = (char *)&snaplen;
+ if (ioctl(fd, I_STR, (char *)&si) < 0) {
+ sprintf(ebuf, "NIOCSSNAP: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ p->snapshot = snaplen;
+ if (nit_setflags(p->fd, promisc, to_ms, ebuf) < 0)
+ goto bad;
+
+ (void)ioctl(fd, I_FLUSH, (char *)FLUSHR);
+ /*
+ * NIT supports only ethernets.
+ */
+ p->linktype = DLT_EN10MB;
+
+ p->bufsize = BUFSPACE;
+ p->buffer = (u_char *)malloc(p->bufsize);
+ if (p->buffer == NULL) {
+ strcpy(ebuf, pcap_strerror(errno));
+ goto bad;
+ }
+ return (p);
+ bad:
+ if (fd >= 0)
+ close(fd);
+ free(p);
+ return (NULL);
+}
+
+int
+pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+{
+
+ p->fcode = *fp;
+ return (0);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-snoop.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-snoop.c
new file mode 100644
index 000000000..075d9fa4b
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap-snoop.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap-snoop.c,v 1.1 1999/08/26 10:05:26 johana Exp $ (LBL)";
+#endif
+
+#include <sys/param.h>
+#include <sys/file.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+#include <sys/time.h>
+
+#include <net/raw.h>
+#include <net/if.h>
+
+#include <netinet/in.h>
+#include <netinet/in_systm.h>
+#include <netinet/ip.h>
+#include <netinet/if_ether.h>
+#include <netinet/ip_var.h>
+#include <netinet/udp.h>
+#include <netinet/udp_var.h>
+#include <netinet/tcp.h>
+#include <netinet/tcpip.h>
+
+#include <errno.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+int
+pcap_read(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+ int cc;
+ register struct snoopheader *sh;
+ register int datalen;
+ register int caplen;
+ register u_char *cp;
+
+again:
+ cc = read(p->fd, (char *)p->buffer, p->bufsize);
+ if (cc < 0) {
+ /* Don't choke when we get ptraced */
+ switch (errno) {
+
+ case EINTR:
+ goto again;
+
+ case EWOULDBLOCK:
+ return (0); /* XXX */
+ }
+ sprintf(p->errbuf, "read: %s", pcap_strerror(errno));
+ return (-1);
+ }
+ sh = (struct snoopheader *)p->buffer;
+ datalen = sh->snoop_packetlen;
+ caplen = (datalen < p->snapshot) ? datalen : p->snapshot;
+ cp = (u_char *)(sh + 1) + p->offset; /* XXX */
+
+ if (p->fcode.bf_insns == NULL ||
+ bpf_filter(p->fcode.bf_insns, cp, datalen, caplen)) {
+ struct pcap_pkthdr h;
+ ++p->md.stat.ps_recv;
+ h.ts = sh->snoop_timestamp;
+ h.len = datalen;
+ h.caplen = caplen;
+ (*callback)(user, &h, cp);
+ return (1);
+ }
+ return (0);
+}
+
+int
+pcap_stats(pcap_t *p, struct pcap_stat *ps)
+{
+ register struct rawstats *rs;
+ struct rawstats rawstats;
+
+ rs = &rawstats;
+ bzero((char *)rs, sizeof(*rs));
+ if (ioctl(p->fd, SIOCRAWSTATS, (char *)rs) < 0) {
+ sprintf(p->errbuf, "SIOCRAWSTATS: %s", pcap_strerror(errno));
+ return (-1);
+ }
+
+ p->md.stat.ps_drop =
+ rs->rs_snoop.ss_ifdrops + rs->rs_snoop.ss_sbdrops +
+ rs->rs_drain.ds_ifdrops + rs->rs_drain.ds_sbdrops;
+
+ *ps = p->md.stat;
+ return (0);
+}
+
+/* XXX can't disable promiscuous */
+pcap_t *
+pcap_open_live(char *device, int snaplen, int promisc, int to_ms, char *ebuf)
+{
+ int fd;
+ struct sockaddr_raw sr;
+ struct snoopfilter sf;
+ u_int v;
+ pcap_t *p;
+
+ p = (pcap_t *)malloc(sizeof(*p));
+ if (p == NULL) {
+ sprintf(ebuf, "malloc: %s", pcap_strerror(errno));
+ return (NULL);
+ }
+ bzero((char *)p, sizeof(*p));
+ fd = socket(PF_RAW, SOCK_RAW, RAWPROTO_SNOOP);
+ if (fd < 0) {
+ sprintf(ebuf, "snoop socket: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ p->fd = fd;
+ bzero((char *)&sr, sizeof(sr));
+ sr.sr_family = AF_RAW;
+ (void)strncpy(sr.sr_ifname, device, sizeof(sr.sr_ifname));
+ if (bind(fd, (struct sockaddr *)&sr, sizeof(sr))) {
+ sprintf(ebuf, "snoop bind: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ bzero((char *)&sf, sizeof(sf));
+ if (ioctl(fd, SIOCADDSNOOP, &sf) < 0) {
+ sprintf(ebuf, "SIOCADDSNOOP: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ v = 64 * 1024;
+ (void)setsockopt(fd, SOL_SOCKET, SO_RCVBUF, (char *)&v, sizeof(v));
+ if (ioctl(fd, SIOCSNOOPLEN, &snaplen) < 0) {
+ sprintf(ebuf, "SIOCSNOOPLEN: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ p->snapshot = snaplen;
+ v = 1;
+ if (ioctl(fd, SIOCSNOOPING, &v) < 0) {
+ sprintf(ebuf, "SIOCSNOOPING: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ /*
+ * XXX hack - map device name to link layer type
+ */
+ if (strncmp("et", device, 2) == 0 || /* Challenge 10 Mbit */
+ strncmp("ec", device, 2) == 0 || /* Indigo/Indy 10 Mbit,
+ O2 10/100 */
+ strncmp("ef", device, 2) == 0 || /* O200/2000 10/100 Mbit */
+ strncmp("gfe", device, 3) == 0 || /* GIO 100 Mbit */
+ strncmp("fxp", device, 3) == 0 || /* Challenge VME Enet */
+ strncmp("ep", device, 2) == 0 || /* Challenge 8x10 Mbit EPLEX */
+ strncmp("vfe", device, 3) == 0 || /* Challenge VME 100Mbit */
+ strncmp("fa", device, 2) == 0 ||
+ strncmp("qaa", device, 3) == 0) {
+ p->linktype = DLT_EN10MB;
+ p->offset = RAW_HDRPAD(sizeof(struct ether_header));
+ } else if (strncmp("ipg", device, 3) == 0 ||
+ strncmp("rns", device, 3) == 0 || /* O2/200/2000 FDDI */
+ strncmp("xpi", device, 3) == 0) {
+ p->linktype = DLT_FDDI;
+ p->offset = 3; /* XXX yeah? */
+ } else if (strncmp("ppp", device, 3) == 0) {
+ p->linktype = DLT_RAW;
+ } else if (strncmp("lo", device, 2) == 0) {
+ p->linktype = DLT_NULL;
+ } else {
+ sprintf(ebuf, "snoop: unknown physical layer type");
+ goto bad;
+ }
+
+ p->bufsize = 4096; /* XXX */
+ p->buffer = (u_char *)malloc(p->bufsize);
+ if (p->buffer == NULL) {
+ sprintf(ebuf, "malloc: %s", pcap_strerror(errno));
+ goto bad;
+ }
+
+ return (p);
+ bad:
+ (void)close(fd);
+ free(p);
+ return (NULL);
+}
+
+int
+pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+{
+
+ p->fcode = *fp;
+ return (0);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.3 b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.3
new file mode 100644
index 000000000..23e5b52b3
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.3
@@ -0,0 +1,340 @@
+.\" Copyright (c) 1994, 1996, 1997
+.\" The Regents of the University of California. All rights reserved.
+.\"
+.\" Redistribution and use in source and binary forms, with or without
+.\" modification, are permitted provided that: (1) source code distributions
+.\" retain the above copyright notice and this paragraph in its entirety, (2)
+.\" distributions including binary code include the above copyright notice and
+.\" this paragraph in its entirety in the documentation or other materials
+.\" provided with the distribution, and (3) all advertising materials mentioning
+.\" features or use of this software display the following acknowledgement:
+.\" ``This product includes software developed by the University of California,
+.\" Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+.\" the University nor the names of its contributors may be used to endorse
+.\" or promote products derived from this software without specific prior
+.\" written permission.
+.\" THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+.\" WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+.\" MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+.\"
+.TH PCAP 3 "24 June 1998"
+.SH NAME
+pcap \- Packet Capture library
+.SH SYNOPSIS
+.nf
+.ft B
+#include <pcap.h>
+.ft
+.LP
+.ft B
+pcap_t *pcap_open_live(char *device, int snaplen,
+.ti +8
+int promisc, int to_ms, char *ebuf)
+pcap_t *pcap_open_offline(char *fname, char *ebuf)
+pcap_dumper_t *pcap_dump_open(pcap_t *p, char *fname)
+.ft
+.LP
+.ft B
+char errbuf[PCAP_ERRBUF_SIZE];
+char *pcap_lookupdev(char *errbuf)
+int pcap_lookupnet(char *device, bpf_u_int32 *netp,
+.ti +8
+bpf_u_int32 *maskp, char *errbuf)
+.ft
+.LP
+.ft B
+int pcap_dispatch(pcap_t *p, int cnt,
+.ti +8
+pcap_handler callback, u_char *user)
+int pcap_loop(pcap_t *p, int cnt,
+.ti +8
+pcap_handler callback, u_char *user)
+void pcap_dump(u_char *user, struct pcap_pkthdr *h,
+.ti +8
+u_char *sp)
+.ft
+.LP
+.ft B
+int pcap_compile(pcap_t *p, struct bpf_program *fp,
+.ti +8
+char *str, int optimize, bpf_u_int32 netmask)
+int pcap_setfilter(pcap_t *p, struct bpf_program *fp)
+.ft
+.LP
+.ft B
+u_char *pcap_next(pcap_t *p, struct pcap_pkthdr *h)
+.ft
+.LP
+.ft B
+int pcap_datalink(pcap_t *p)
+int pcap_snapshot(pcap_t *p)
+int pcap_is_swapped(pcap_t *p)
+int pcap_major_version(pcap_t *p)
+int pcap_minor_version(pcap_t *p)
+int pcap_stats(pcap_t *p, struct pcap_stat *ps)
+FILE *pcap_file(pcap_t *p)
+int pcap_fileno(pcap_t *p)
+void pcap_perror(pcap_t *p, char *prefix)
+char *pcap_geterr(pcap_t *p)
+char *pcap_strerror(int error)
+.ft
+.LP
+.ft B
+void pcap_close(pcap_t *p)
+void pcap_dump_close(pcap_dumper_t *p)
+.ft
+.fi
+.SH DESCRIPTION
+The Packet Capture library
+provides a high level interface to packet capture systems. All packets
+on the network, even those destined for other hosts, are accessible
+through this mechanism.
+.PP
+.SH ROUTINES
+.B pcap_open_live()
+is used to obtain a packet capture descriptor to look
+at packets on the network.
+.I device
+is a string that specifies the network device to open.
+.I snaplen
+specifies the maximum number of bytes to capture.
+.I promisc
+specifies if the interface is to be put into promiscuous mode.
+(Note that even if this parameter is false, the interface
+could well be in promiscuous mode for some other reason.)
+.I to_ms
+specifies the read timeout in milliseconds.
+.I ebuf
+is used to return error text and is only set when
+.B pcap_open_live()
+fails and returns
+.BR NULL .
+.PP
+.B pcap_open_offline()
+is called to open a ``savefile'' for reading.
+.I fname
+specifies the name of the file to open. The file has
+the same format as those used by
+.B tcpdump(1)
+and
+.BR tcpslice(1) .
+The name "-" in a synonym for
+.BR stdin .
+.I ebuf
+is used to return error text and is only set when
+.B pcap_open_offline()
+fails and returns
+.BR NULL .
+.PP
+.B pcap_dump_open()
+is called to open a ``savefile'' for writing. The name "-" in a synonym
+for
+.BR stdout .
+.B NULL
+is returned on failure.
+.I p
+is a
+.I pcap
+struct as returned by
+.B pcap_open_offline()
+or
+.BR pcap_open_live() .
+.I fname
+specifies the name of the file to open.
+If
+.B NULL
+is returned,
+.B pcap_geterr()
+can be used to get the error text.
+.PP
+.B pcap_lookupdev()
+returns a pointer to a network device suitable for use with
+.B pcap_open_live()
+and
+.BR pcap_lookupnet() .
+If there is an error,
+.B NULL
+is returned and
+.I errbuf
+is filled in with with an appropriate error message.
+.PP
+.B pcap_lookupnet()
+is used to determine the network number and mask
+associated with the network device
+.BR device .
+Both
+.I netp
+and
+.I maskp
+are
+.I bpf_u_int32
+pointers.
+A return of -1 indicates an error in which case
+.I errbuf
+is filled in with with an appropriate error message.
+.PP
+.B pcap_dispatch()
+is used to collect and process packets.
+.I cnt
+specifies the maximum number of packets to process before returning. A
+.I cnt
+of -1 processes all the packets received in one buffer. A
+.I cnt
+of 0 processes all packets until an error occurs,
+.B EOF
+is reached, or the read times out (when doing live reads and a non-zero
+read timeout is specified).
+.I callback
+specifies a routine to be called with three arguments:
+a
+.I u_char
+pointer which is passed in from
+.BR pcap_dispatch() ,
+a pointer to the
+.I pcap_pkthdr
+struct (which precede the actual network headers and data),
+and a
+.I u_char
+pointer to the packet data. The number of packets read is returned.
+Zero is returned when
+.B EOF
+is reached in a ``savefile.'' A return of -1 indicates
+an error in which case
+.B pcap_perror()
+or
+.BR pcap_geterr()
+may be used to display the error text.
+.PP
+.B pcap_dump()
+outputs a packet to the ``savefile'' opened with
+.BR pcap_dump_open() .
+Note that its calling arguments are suitable for use with
+.BR pcap_dispatch() .
+.PP
+.B pcap_compile()
+is used to compile the string
+.I str
+into a filter program.
+.I program
+is a pointer to a
+.I bpf_program
+struct and is filled in by
+.BR pcap_compile() .
+.I optimize
+controls whether optimization on the resulting code is performed.
+.I netmask
+specifies the netmask of the local net.
+.PP
+.B pcap_setfilter()
+is used to specify a filter program.
+.I fp
+is a pointer to an array of
+.I bpf_program
+struct, usually the result of a call to
+.BR pcap_compile() .
+.B \-1
+is returned on failure;
+.B 0
+is returned on success.
+.PP
+.B pcap_loop()
+is similar to
+.B pcap_dispatch()
+except it keeps reading packets until
+.I cnt
+packets are processed or an error occurs.
+It does
+.B not
+return when live read timeouts occur.
+Rather, specifying a non-zero read timeout to
+.B pcap_open_live()
+and then calling
+.B pcap_dispatch()
+allows the reception and processing of any packets that arrive when the
+timeout occurs.
+A negative
+.I cnt
+causes
+.B pcap_loop()
+to loop forever (or at least until an error occurs).
+.PP
+.B pcap_next()
+returns a
+.I u_char
+pointer to the next packet.
+.PP
+.B pcap_datalink()
+returns the link layer type, e.g.
+.BR DLT_EN10MB .
+.PP
+.B pcap_snapshot()
+returns the snapshot length specified when
+.B pcap_open_live
+was called.
+.PP
+.B pcap_is_swapped()
+returns true if the current ``savefile'' uses a different byte order
+than the current system.
+.PP
+.B pcap_major_version()
+returns the major number of the version of the pcap used to write the
+savefile.
+.PP
+.B pcap_minor_version()
+returns the minor number of the version of the pcap used to write the
+savefile.
+.PP
+.B pcap_file()
+returns the name of the ``savefile.''
+.PP
+.B int pcap_stats()
+returns 0 and fills in a
+.B pcap_stat
+struct. The values represent packet statistics from the start of the
+run to the time of the call. If there is an error or the under lying
+packet capture doesn't support packet statistics, -1 is returned and
+the error text can be obtained with
+.B pcap_perror()
+or
+.BR pcap_geterr() .
+.PP
+.B pcap_fileno()
+returns the file descriptor number of the ``savefile.''
+.PP
+.B pcap_perror()
+prints the text of the last pcap library error on
+.BR stderr ,
+prefixed by
+.IR prefix .
+.PP
+.B pcap_geterr()
+returns the error text pertaining to the last pcap library error.
+.PP
+.B pcap_strerror()
+is provided in case
+.BR strerror (1)
+isn't available.
+.PP
+.B pcap_close()
+closes the files associated with
+.I p
+and deallocates resources.
+.PP
+.B pcap_dump_close()
+closes the ``savefile.''
+.PP
+.SH SEE ALSO
+tcpdump(1), tcpslice(1)
+.SH AUTHORS
+Van Jacobson,
+Craig Leres and
+Steven McCanne, all of the
+Lawrence Berkeley National Laboratory, University of California, Berkeley, CA.
+.LP
+The current version is available via anonymous ftp:
+.LP
+.RS
+.I ftp://ftp.ee.lbl.gov/libpcap.tar.Z
+.RE
+.SH BUGS
+Please send bug reports to libpcap@ee.lbl.gov.
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.c b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.c
new file mode 100644
index 000000000..31560b760
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 1993, 1994, 1995, 1996, 1997, 1998
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the Computer Systems
+ * Engineering Group at Lawrence Berkeley Laboratory.
+ * 4. Neither the name of the University nor of the Laboratory may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap.c,v 1.1 1999/08/26 10:05:26 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#include "pcap-int.h"
+
+int
+pcap_dispatch(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+
+ if (p->sf.rfile != NULL)
+ return (pcap_offline_read(p, cnt, callback, user));
+ return (pcap_read(p, cnt, callback, user));
+}
+
+int
+pcap_loop(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+ register int n;
+
+ for (;;) {
+ if (p->sf.rfile != NULL)
+ n = pcap_offline_read(p, cnt, callback, user);
+ else {
+ /*
+ * XXX keep reading until we get something
+ * (or an error occurs)
+ */
+ do {
+ n = pcap_read(p, cnt, callback, user);
+ } while (n == 0);
+ }
+ if (n <= 0)
+ return (n);
+ if (cnt > 0) {
+ cnt -= n;
+ if (cnt <= 0)
+ return (0);
+ }
+ }
+}
+
+struct singleton {
+ struct pcap_pkthdr *hdr;
+ const u_char *pkt;
+};
+
+
+static void
+pcap_oneshot(u_char *userData, const struct pcap_pkthdr *h, const u_char *pkt)
+{
+ struct singleton *sp = (struct singleton *)userData;
+ *sp->hdr = *h;
+ sp->pkt = pkt;
+}
+
+const u_char *
+pcap_next(pcap_t *p, struct pcap_pkthdr *h)
+{
+ struct singleton s;
+
+ s.hdr = h;
+ if (pcap_dispatch(p, 1, pcap_oneshot, (u_char*)&s) <= 0)
+ return (0);
+ return (s.pkt);
+}
+
+int
+pcap_datalink(pcap_t *p)
+{
+ return (p->linktype);
+}
+
+int
+pcap_snapshot(pcap_t *p)
+{
+ return (p->snapshot);
+}
+
+int
+pcap_is_swapped(pcap_t *p)
+{
+ return (p->sf.swapped);
+}
+
+int
+pcap_major_version(pcap_t *p)
+{
+ return (p->sf.version_major);
+}
+
+int
+pcap_minor_version(pcap_t *p)
+{
+ return (p->sf.version_minor);
+}
+
+FILE *
+pcap_file(pcap_t *p)
+{
+ return (p->sf.rfile);
+}
+
+int
+pcap_fileno(pcap_t *p)
+{
+ return (p->fd);
+}
+
+void
+pcap_perror(pcap_t *p, char *prefix)
+{
+ fprintf(stderr, "%s: %s\n", prefix, p->errbuf);
+}
+
+char *
+pcap_geterr(pcap_t *p)
+{
+ return (p->errbuf);
+}
+
+/*
+ * Not all systems have strerror().
+ */
+char *
+pcap_strerror(int errnum)
+{
+#ifdef HAVE_STRERROR
+ return (strerror(errnum));
+#else
+ extern int sys_nerr;
+ extern const char *const sys_errlist[];
+ static char ebuf[20];
+
+ if ((unsigned int)errnum < sys_nerr)
+ return ((char *)sys_errlist[errnum]);
+ (void)sprintf(ebuf, "Unknown error: %d", errnum);
+ return(ebuf);
+#endif
+}
+
+void
+pcap_close(pcap_t *p)
+{
+ /*XXX*/
+ if (p->fd >= 0)
+ close(p->fd);
+ if (p->sf.rfile != NULL) {
+ (void)fclose(p->sf.rfile);
+ if (p->sf.base != NULL)
+ free(p->sf.base);
+ } else if (p->buffer != NULL)
+ free(p->buffer);
+#ifdef linux
+ if (p->md.device != NULL)
+ free(p->md.device);
+#endif
+
+ free(p);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.h b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.h
new file mode 100644
index 000000000..dea401cde
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/pcap.h
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ * must display the following acknowledgement:
+ * This product includes software developed by the Computer Systems
+ * Engineering Group at Lawrence Berkeley Laboratory.
+ * 4. Neither the name of the University nor of the Laboratory may be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/pcap.h,v 1.1 1999/08/26 10:05:26 johana Exp $ (LBL)
+ */
+
+#ifndef lib_pcap_h
+#define lib_pcap_h
+
+#include <sys/types.h>
+#include <sys/time.h>
+
+#include <net/bpf.h>
+
+#include <stdio.h>
+
+#define PCAP_VERSION_MAJOR 2
+#define PCAP_VERSION_MINOR 4
+
+#define PCAP_ERRBUF_SIZE 256
+
+/*
+ * Compatibility for systems that have a bpf.h that
+ * predates the bpf typedefs for 64-bit support.
+ */
+#if BPF_RELEASE - 0 < 199406
+typedef int bpf_int32;
+typedef u_int bpf_u_int32;
+#endif
+
+typedef struct pcap pcap_t;
+typedef struct pcap_dumper pcap_dumper_t;
+
+/*
+ * The first record in the file contains saved values for some
+ * of the flags used in the printout phases of tcpdump.
+ * Many fields here are 32 bit ints so compilers won't insert unwanted
+ * padding; these files need to be interchangeable across architectures.
+ */
+struct pcap_file_header {
+ bpf_u_int32 magic;
+ u_short version_major;
+ u_short version_minor;
+ bpf_int32 thiszone; /* gmt to local correction */
+ bpf_u_int32 sigfigs; /* accuracy of timestamps */
+ bpf_u_int32 snaplen; /* max length saved portion of each pkt */
+ bpf_u_int32 linktype; /* data link type (DLT_*) */
+};
+
+/*
+ * Each packet in the dump file is prepended with this generic header.
+ * This gets around the problem of different headers for different
+ * packet interfaces.
+ */
+struct pcap_pkthdr {
+ struct timeval ts; /* time stamp */
+ bpf_u_int32 caplen; /* length of portion present */
+ bpf_u_int32 len; /* length this packet (off wire) */
+};
+
+/*
+ * As returned by the pcap_stats()
+ */
+struct pcap_stat {
+ u_int ps_recv; /* number of packets received */
+ u_int ps_drop; /* number of packets dropped */
+ u_int ps_ifdrop; /* drops by interface XXX not yet supported */
+};
+
+typedef void (*pcap_handler)(u_char *, const struct pcap_pkthdr *,
+ const u_char *);
+
+char *pcap_lookupdev(char *);
+int pcap_lookupnet(char *, bpf_u_int32 *, bpf_u_int32 *, char *);
+pcap_t *pcap_open_live(char *, int, int, int, char *);
+pcap_t *pcap_open_offline(const char *, char *);
+void pcap_close(pcap_t *);
+int pcap_loop(pcap_t *, int, pcap_handler, u_char *);
+int pcap_dispatch(pcap_t *, int, pcap_handler, u_char *);
+const u_char*
+ pcap_next(pcap_t *, struct pcap_pkthdr *);
+int pcap_stats(pcap_t *, struct pcap_stat *);
+int pcap_setfilter(pcap_t *, struct bpf_program *);
+void pcap_perror(pcap_t *, char *);
+char *pcap_strerror(int);
+char *pcap_geterr(pcap_t *);
+int pcap_compile(pcap_t *, struct bpf_program *, char *, int,
+ bpf_u_int32);
+/* XXX */
+int pcap_freecode(pcap_t *, struct bpf_program *);
+int pcap_datalink(pcap_t *);
+int pcap_snapshot(pcap_t *);
+int pcap_is_swapped(pcap_t *);
+int pcap_major_version(pcap_t *);
+int pcap_minor_version(pcap_t *);
+
+/* XXX */
+FILE *pcap_file(pcap_t *);
+int pcap_fileno(pcap_t *);
+
+pcap_dumper_t *pcap_dump_open(pcap_t *, const char *);
+void pcap_dump_close(pcap_dumper_t *);
+void pcap_dump(u_char *, const struct pcap_pkthdr *, const u_char *);
+
+/* XXX this guy lives in the bpf tree */
+u_int bpf_filter(struct bpf_insn *, u_char *, u_int, u_int);
+char *bpf_image(struct bpf_insn *, int);
+#endif
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/ppp.h b/package/etrax-tools/src/e100boot/libpcap-0.4/ppp.h
new file mode 100644
index 000000000..f8e982bd1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/ppp.h
@@ -0,0 +1,50 @@
+/* @(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/ppp.h,v 1.1 1999/08/26 10:05:26 johana Exp $ (LBL) */
+/*
+ * Point to Point Protocol (PPP) RFC1331
+ *
+ * Copyright 1989 by Carnegie Mellon.
+ *
+ * Permission to use, copy, modify, and distribute this program for any
+ * purpose and without fee is hereby granted, provided that this copyright
+ * and permission notice appear on all copies and supporting documentation,
+ * the name of Carnegie Mellon not be used in advertising or publicity
+ * pertaining to distribution of the program without specific prior
+ * permission, and notice be given in supporting documentation that copying
+ * and distribution is by permission of Carnegie Mellon and Stanford
+ * University. Carnegie Mellon makes no representations about the
+ * suitability of this software for any purpose. It is provided "as is"
+ * without express or implied warranty.
+ */
+#define PPP_ADDRESS 0xff /* The address byte value */
+#define PPP_CONTROL 0x03 /* The control byte value */
+
+/* Protocol numbers */
+#define PPP_IP 0x0021 /* Raw IP */
+#define PPP_OSI 0x0023 /* OSI Network Layer */
+#define PPP_NS 0x0025 /* Xerox NS IDP */
+#define PPP_DECNET 0x0027 /* DECnet Phase IV */
+#define PPP_APPLE 0x0029 /* Appletalk */
+#define PPP_IPX 0x002b /* Novell IPX */
+#define PPP_VJC 0x002d /* Van Jacobson Compressed TCP/IP */
+#define PPP_VJNC 0x002f /* Van Jacobson Uncompressed TCP/IP */
+#define PPP_BRPDU 0x0031 /* Bridging PDU */
+#define PPP_STII 0x0033 /* Stream Protocol (ST-II) */
+#define PPP_VINES 0x0035 /* Banyan Vines */
+
+#define PPP_HELLO 0x0201 /* 802.1d Hello Packets */
+#define PPP_LUXCOM 0x0231 /* Luxcom */
+#define PPP_SNS 0x0233 /* Sigma Network Systems */
+
+#define PPP_IPCP 0x8021 /* IP Control Protocol */
+#define PPP_OSICP 0x8023 /* OSI Network Layer Control Protocol */
+#define PPP_NSCP 0x8025 /* Xerox NS IDP Control Protocol */
+#define PPP_DECNETCP 0x8027 /* DECnet Control Protocol */
+#define PPP_APPLECP 0x8029 /* Appletalk Control Protocol */
+#define PPP_IPXCP 0x802b /* Novell IPX Control Protocol */
+#define PPP_STIICP 0x8033 /* Strean Protocol Control Protocol */
+#define PPP_VINESCP 0x8035 /* Banyan Vines Control Protocol */
+
+#define PPP_LCP 0xc021 /* Link Control Protocol */
+#define PPP_PAP 0xc023 /* Password Authentication Protocol */
+#define PPP_LQM 0xc025 /* Link Quality Monitoring */
+#define PPP_CHAP 0xc223 /* Challenge Handshake Authentication Protocol */
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/rmlinks b/package/etrax-tools/src/e100boot/libpcap-0.4/rmlinks
new file mode 100644
index 000000000..9ed425902
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/rmlinks
@@ -0,0 +1,3 @@
+rm bpf_filter.c
+rm gnuc.h
+rm net
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/savefile.c b/package/etrax-tools/src/e100boot/libpcap-0.4/savefile.c
new file mode 100644
index 000000000..c936fc438
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/savefile.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ * savefile.c - supports offline use of tcpdump
+ * Extraction/creation by Jeffrey Mogul, DECWRL
+ * Modified by Steve McCanne, LBL.
+ *
+ * Used to save the received packet headers, after filtering, to
+ * a file, and then read them later.
+ * The first record in the file contains saved values for the machine
+ * dependent values so we can print the dump file on any architecture.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/savefile.c,v 1.1 1999/08/26 10:05:27 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+
+#include <errno.h>
+#include <memory.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+#define TCPDUMP_MAGIC 0xa1b2c3d4
+
+/*
+ * We use the "receiver-makes-right" approach to byte order,
+ * because time is at a premium when we are writing the file.
+ * In other words, the pcap_file_header and pcap_pkthdr,
+ * records are written in host byte order.
+ * Note that the packets are always written in network byte order.
+ *
+ * ntoh[ls] aren't sufficient because we might need to swap on a big-endian
+ * machine (if the file was written in little-end order).
+ */
+#define SWAPLONG(y) \
+((((y)&0xff)<<24) | (((y)&0xff00)<<8) | (((y)&0xff0000)>>8) | (((y)>>24)&0xff))
+#define SWAPSHORT(y) \
+ ( (((y)&0xff)<<8) | ((u_short)((y)&0xff00)>>8) )
+
+#define SFERR_TRUNC 1
+#define SFERR_BADVERSION 2
+#define SFERR_BADF 3
+#define SFERR_EOF 4 /* not really an error, just a status */
+
+static int
+sf_write_header(FILE *fp, int linktype, int thiszone, int snaplen)
+{
+ struct pcap_file_header hdr;
+
+ hdr.magic = TCPDUMP_MAGIC;
+ hdr.version_major = PCAP_VERSION_MAJOR;
+ hdr.version_minor = PCAP_VERSION_MINOR;
+
+ hdr.thiszone = thiszone;
+ hdr.snaplen = snaplen;
+ hdr.sigfigs = 0;
+ hdr.linktype = linktype;
+
+ if (fwrite((char *)&hdr, sizeof(hdr), 1, fp) != 1)
+ return (-1);
+
+ return (0);
+}
+
+static void
+swap_hdr(struct pcap_file_header *hp)
+{
+ hp->version_major = SWAPSHORT(hp->version_major);
+ hp->version_minor = SWAPSHORT(hp->version_minor);
+ hp->thiszone = SWAPLONG(hp->thiszone);
+ hp->sigfigs = SWAPLONG(hp->sigfigs);
+ hp->snaplen = SWAPLONG(hp->snaplen);
+ hp->linktype = SWAPLONG(hp->linktype);
+}
+
+pcap_t *
+pcap_open_offline(const char *fname, char *errbuf)
+{
+ register pcap_t *p;
+ register FILE *fp;
+ struct pcap_file_header hdr;
+ int linklen;
+
+ p = (pcap_t *)malloc(sizeof(*p));
+ if (p == NULL) {
+ strcpy(errbuf, "out of swap");
+ return (NULL);
+ }
+
+ memset((char *)p, 0, sizeof(*p));
+ /*
+ * Set this field so we don't close stdin in pcap_close!
+ */
+ p->fd = -1;
+
+ if (fname[0] == '-' && fname[1] == '\0')
+ fp = stdin;
+ else {
+ fp = fopen(fname, "r");
+ if (fp == NULL) {
+ sprintf(errbuf, "%s: %s", fname, pcap_strerror(errno));
+ goto bad;
+ }
+ }
+ if (fread((char *)&hdr, sizeof(hdr), 1, fp) != 1) {
+ sprintf(errbuf, "fread: %s", pcap_strerror(errno));
+ goto bad;
+ }
+ if (hdr.magic != TCPDUMP_MAGIC) {
+ if (SWAPLONG(hdr.magic) != TCPDUMP_MAGIC) {
+ sprintf(errbuf, "bad dump file format");
+ goto bad;
+ }
+ p->sf.swapped = 1;
+ swap_hdr(&hdr);
+ }
+ if (hdr.version_major < PCAP_VERSION_MAJOR) {
+ sprintf(errbuf, "archaic file format");
+ goto bad;
+ }
+ p->tzoff = hdr.thiszone;
+ p->snapshot = hdr.snaplen;
+ p->linktype = hdr.linktype;
+ p->sf.rfile = fp;
+ p->bufsize = hdr.snaplen;
+
+ /* Align link header as required for proper data alignment */
+ /* XXX should handle all types */
+ switch (p->linktype) {
+
+ case DLT_EN10MB:
+ linklen = 14;
+ break;
+
+ case DLT_FDDI:
+ linklen = 13 + 8; /* fddi_header + llc */
+ break;
+
+ case DLT_NULL:
+ default:
+ linklen = 0;
+ break;
+ }
+
+ p->sf.base = (u_char *)malloc(p->bufsize + BPF_ALIGNMENT);
+ p->buffer = p->sf.base + BPF_ALIGNMENT - (linklen % BPF_ALIGNMENT);
+ p->sf.version_major = hdr.version_major;
+ p->sf.version_minor = hdr.version_minor;
+#ifdef PCAP_FDDIPAD
+ /* XXX padding only needed for kernel fcode */
+ pcap_fddipad = 0;
+#endif
+
+ return (p);
+ bad:
+ free(p);
+ return (NULL);
+}
+
+/*
+ * Read sf_readfile and return the next packet. Return the header in hdr
+ * and the contents in buf. Return 0 on success, SFERR_EOF if there were
+ * no more packets, and SFERR_TRUNC if a partial packet was encountered.
+ */
+static int
+sf_next_packet(pcap_t *p, struct pcap_pkthdr *hdr, u_char *buf, int buflen)
+{
+ FILE *fp = p->sf.rfile;
+
+ /* read the stamp */
+ if (fread((char *)hdr, sizeof(struct pcap_pkthdr), 1, fp) != 1) {
+ /* probably an EOF, though could be a truncated packet */
+ return (1);
+ }
+
+ if (p->sf.swapped) {
+ /* these were written in opposite byte order */
+ hdr->caplen = SWAPLONG(hdr->caplen);
+ hdr->len = SWAPLONG(hdr->len);
+ hdr->ts.tv_sec = SWAPLONG(hdr->ts.tv_sec);
+ hdr->ts.tv_usec = SWAPLONG(hdr->ts.tv_usec);
+ }
+ /*
+ * We interchanged the caplen and len fields at version 2.3,
+ * in order to match the bpf header layout. But unfortunately
+ * some files were written with version 2.3 in their headers
+ * but without the interchanged fields.
+ */
+ if (p->sf.version_minor < 3 ||
+ (p->sf.version_minor == 3 && hdr->caplen > hdr->len)) {
+ int t = hdr->caplen;
+ hdr->caplen = hdr->len;
+ hdr->len = t;
+ }
+
+ if (hdr->caplen > buflen) {
+ /*
+ * This can happen due to Solaris 2.3 systems tripping
+ * over the BUFMOD problem and not setting the snapshot
+ * correctly in the savefile header. If the caplen isn't
+ * grossly wrong, try to salvage.
+ */
+ static u_char *tp = NULL;
+ static int tsize = 0;
+
+ if (hdr->caplen > 65535) {
+ sprintf(p->errbuf, "bogus savefile header");
+ return (-1);
+ }
+ if (tsize < hdr->caplen) {
+ tsize = ((hdr->caplen + 1023) / 1024) * 1024;
+ if (tp != NULL)
+ free((u_char *)tp);
+ tp = (u_char *)malloc(tsize);
+ if (tp == NULL) {
+ tsize = 0;
+ sprintf(p->errbuf, "BUFMOD hack malloc");
+ return (-1);
+ }
+ }
+ if (fread((char *)tp, hdr->caplen, 1, fp) != 1) {
+ sprintf(p->errbuf, "truncated dump file");
+ return (-1);
+ }
+ /*
+ * We can only keep up to buflen bytes. Since caplen > buflen
+ * is exactly how we got here, we know we can only keep the
+ * first buflen bytes and must drop the remainder. Adjust
+ * caplen accordingly, so we don't get confused later as
+ * to how many bytes we have to play with.
+ */
+ hdr->caplen = buflen;
+ memcpy((char *)buf, (char *)tp, buflen);
+
+ } else {
+ /* read the packet itself */
+
+ if (fread((char *)buf, hdr->caplen, 1, fp) != 1) {
+ sprintf(p->errbuf, "truncated dump file");
+ return (-1);
+ }
+ }
+ return (0);
+}
+
+/*
+ * Print out packets stored in the file initialized by sf_read_init().
+ * If cnt > 0, return after 'cnt' packets, otherwise continue until eof.
+ */
+int
+pcap_offline_read(pcap_t *p, int cnt, pcap_handler callback, u_char *user)
+{
+ struct bpf_insn *fcode = p->fcode.bf_insns;
+ int status = 0;
+ int n = 0;
+
+ while (status == 0) {
+ struct pcap_pkthdr h;
+
+ status = sf_next_packet(p, &h, p->buffer, p->bufsize);
+ if (status) {
+ if (status == 1)
+ return (0);
+ return (status);
+ }
+
+ if (fcode == NULL ||
+ bpf_filter(fcode, p->buffer, h.len, h.caplen)) {
+ (*callback)(user, &h, p->buffer);
+ if (++n >= cnt && cnt > 0)
+ break;
+ }
+ }
+ /*XXX this breaks semantics tcpslice expects */
+ return (n);
+}
+
+/*
+ * Output a packet to the initialized dump file.
+ */
+void
+pcap_dump(u_char *user, const struct pcap_pkthdr *h, const u_char *sp)
+{
+ register FILE *f;
+
+ f = (FILE *)user;
+ /* XXX we should check the return status */
+ (void)fwrite((char *)h, sizeof(*h), 1, f);
+ (void)fwrite((char *)sp, h->caplen, 1, f);
+}
+
+/*
+ * Initialize so that sf_write() will output to the file named 'fname'.
+ */
+pcap_dumper_t *
+pcap_dump_open(pcap_t *p, const char *fname)
+{
+ FILE *f;
+ if (fname[0] == '-' && fname[1] == '\0')
+ f = stdout;
+ else {
+ f = fopen(fname, "w");
+ if (f == NULL) {
+ sprintf(p->errbuf, "%s: %s",
+ fname, pcap_strerror(errno));
+ return (NULL);
+ }
+ }
+ (void)sf_write_header(f, p->linktype, p->tzoff, p->snapshot);
+ return ((pcap_dumper_t *)f);
+}
+
+void
+pcap_dump_close(pcap_dumper_t *p)
+{
+
+#ifdef notyet
+ if (ferror((FILE *)p))
+ return-an-error;
+ /* XXX should check return from fclose() too */
+#endif
+ (void)fclose((FILE *)p);
+}
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/scanner.c b/package/etrax-tools/src/e100boot/libpcap-0.4/scanner.c
new file mode 100644
index 000000000..61e74bad5
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/scanner.c
@@ -0,0 +1,2242 @@
+
+#line 3 "<stdout>"
+
+#define YY_INT_ALIGNED short int
+
+/* A lexical scanner generated by flex */
+
+#define FLEX_SCANNER
+#define YY_FLEX_MAJOR_VERSION 2
+#define YY_FLEX_MINOR_VERSION 5
+#define YY_FLEX_SUBMINOR_VERSION 33
+#if YY_FLEX_SUBMINOR_VERSION > 0
+#define FLEX_BETA
+#endif
+
+/* First, we deal with platform-specific or compiler-specific issues. */
+
+/* begin standard C headers. */
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+
+/* end standard C headers. */
+
+/* flex integer type definitions */
+
+#ifndef FLEXINT_H
+#define FLEXINT_H
+
+/* C99 systems have <inttypes.h>. Non-C99 systems may or may not. */
+
+#if __STDC_VERSION__ >= 199901L
+
+/* C99 says to define __STDC_LIMIT_MACROS before including stdint.h,
+ * if you want the limit (max/min) macros for int types.
+ */
+#ifndef __STDC_LIMIT_MACROS
+#define __STDC_LIMIT_MACROS 1
+#endif
+
+#include <inttypes.h>
+typedef int8_t flex_int8_t;
+typedef uint8_t flex_uint8_t;
+typedef int16_t flex_int16_t;
+typedef uint16_t flex_uint16_t;
+typedef int32_t flex_int32_t;
+typedef uint32_t flex_uint32_t;
+#else
+typedef signed char flex_int8_t;
+typedef short int flex_int16_t;
+typedef int flex_int32_t;
+typedef unsigned char flex_uint8_t;
+typedef unsigned short int flex_uint16_t;
+typedef unsigned int flex_uint32_t;
+#endif /* ! C99 */
+
+/* Limits of integral types. */
+#ifndef INT8_MIN
+#define INT8_MIN (-128)
+#endif
+#ifndef INT16_MIN
+#define INT16_MIN (-32767-1)
+#endif
+#ifndef INT32_MIN
+#define INT32_MIN (-2147483647-1)
+#endif
+#ifndef INT8_MAX
+#define INT8_MAX (127)
+#endif
+#ifndef INT16_MAX
+#define INT16_MAX (32767)
+#endif
+#ifndef INT32_MAX
+#define INT32_MAX (2147483647)
+#endif
+#ifndef UINT8_MAX
+#define UINT8_MAX (255U)
+#endif
+#ifndef UINT16_MAX
+#define UINT16_MAX (65535U)
+#endif
+#ifndef UINT32_MAX
+#define UINT32_MAX (4294967295U)
+#endif
+
+#endif /* ! FLEXINT_H */
+
+#ifdef __cplusplus
+
+/* The "const" storage-class-modifier is valid. */
+#define YY_USE_CONST
+
+#else /* ! __cplusplus */
+
+#if __STDC__
+
+#define YY_USE_CONST
+
+#endif /* __STDC__ */
+#endif /* ! __cplusplus */
+
+#ifdef YY_USE_CONST
+#define yyconst const
+#else
+#define yyconst
+#endif
+
+/* Returned upon end-of-file. */
+#define YY_NULL 0
+
+/* Promotes a possibly negative, possibly signed char to an unsigned
+ * integer for use as an array index. If the signed char is negative,
+ * we want to instead treat it as an 8-bit unsigned char, hence the
+ * double cast.
+ */
+#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c)
+
+/* Enter a start condition. This macro really ought to take a parameter,
+ * but we do it the disgusting crufty way forced on us by the ()-less
+ * definition of BEGIN.
+ */
+#define BEGIN (yy_start) = 1 + 2 *
+
+/* Translate the current start state into a value that can be later handed
+ * to BEGIN to return to the state. The YYSTATE alias is for lex
+ * compatibility.
+ */
+#define YY_START (((yy_start) - 1) / 2)
+#define YYSTATE YY_START
+
+/* Action number for EOF rule of a given start state. */
+#define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1)
+
+/* Special action meaning "start processing a new file". */
+#define YY_NEW_FILE pcap_restart(pcap_in )
+
+#define YY_END_OF_BUFFER_CHAR 0
+
+/* Size of default input buffer. */
+#ifndef YY_BUF_SIZE
+#define YY_BUF_SIZE 16384
+#endif
+
+/* The state buf must be large enough to hold one state per character in the main buffer.
+ */
+#define YY_STATE_BUF_SIZE ((YY_BUF_SIZE + 2) * sizeof(yy_state_type))
+
+#ifndef YY_TYPEDEF_YY_BUFFER_STATE
+#define YY_TYPEDEF_YY_BUFFER_STATE
+typedef struct yy_buffer_state *YY_BUFFER_STATE;
+#endif
+
+extern int pcap_leng;
+
+extern FILE *pcap_in, *pcap_out;
+
+#define EOB_ACT_CONTINUE_SCAN 0
+#define EOB_ACT_END_OF_FILE 1
+#define EOB_ACT_LAST_MATCH 2
+
+ #define YY_LESS_LINENO(n)
+
+/* Return all but the first "n" matched characters back to the input stream. */
+#define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up pcap_text. */ \
+ int yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ *yy_cp = (yy_hold_char); \
+ YY_RESTORE_YY_MORE_OFFSET \
+ (yy_c_buf_p) = yy_cp = yy_bp + yyless_macro_arg - YY_MORE_ADJ; \
+ YY_DO_BEFORE_ACTION; /* set up pcap_text again */ \
+ } \
+ while ( 0 )
+
+#define unput(c) yyunput( c, (yytext_ptr) )
+
+/* The following is because we cannot portably get our hands on size_t
+ * (without autoconf's help, which isn't available because we want
+ * flex-generated scanners to compile on their own).
+ */
+
+#ifndef YY_TYPEDEF_YY_SIZE_T
+#define YY_TYPEDEF_YY_SIZE_T
+typedef unsigned int yy_size_t;
+#endif
+
+#ifndef YY_STRUCT_YY_BUFFER_STATE
+#define YY_STRUCT_YY_BUFFER_STATE
+struct yy_buffer_state
+ {
+ FILE *yy_input_file;
+
+ char *yy_ch_buf; /* input buffer */
+ char *yy_buf_pos; /* current position in input buffer */
+
+ /* Size of input buffer in bytes, not including room for EOB
+ * characters.
+ */
+ yy_size_t yy_buf_size;
+
+ /* Number of characters read into yy_ch_buf, not including EOB
+ * characters.
+ */
+ int yy_n_chars;
+
+ /* Whether we "own" the buffer - i.e., we know we created it,
+ * and can realloc() it to grow it, and should free() it to
+ * delete it.
+ */
+ int yy_is_our_buffer;
+
+ /* Whether this is an "interactive" input source; if so, and
+ * if we're using stdio for input, then we want to use getc()
+ * instead of fread(), to make sure we stop fetching input after
+ * each newline.
+ */
+ int yy_is_interactive;
+
+ /* Whether we're considered to be at the beginning of a line.
+ * If so, '^' rules will be active on the next match, otherwise
+ * not.
+ */
+ int yy_at_bol;
+
+ int yy_bs_lineno; /**< The line count. */
+ int yy_bs_column; /**< The column count. */
+
+ /* Whether to try to fill the input buffer when we reach the
+ * end of it.
+ */
+ int yy_fill_buffer;
+
+ int yy_buffer_status;
+
+#define YY_BUFFER_NEW 0
+#define YY_BUFFER_NORMAL 1
+ /* When an EOF's been seen but there's still some text to process
+ * then we mark the buffer as YY_EOF_PENDING, to indicate that we
+ * shouldn't try reading from the input source any more. We might
+ * still have a bunch of tokens to match, though, because of
+ * possible backing-up.
+ *
+ * When we actually see the EOF, we change the status to "new"
+ * (via pcap_restart()), so that the user can continue scanning by
+ * just pointing pcap_in at a new input file.
+ */
+#define YY_BUFFER_EOF_PENDING 2
+
+ };
+#endif /* !YY_STRUCT_YY_BUFFER_STATE */
+
+/* Stack of input buffers. */
+static size_t yy_buffer_stack_top = 0; /**< index of top of stack. */
+static size_t yy_buffer_stack_max = 0; /**< capacity of stack. */
+static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */
+
+/* We provide macros for accessing buffer states in case in the
+ * future we want to put the buffer states in a more general
+ * "scanner state".
+ *
+ * Returns the top of the stack, or NULL.
+ */
+#define YY_CURRENT_BUFFER ( (yy_buffer_stack) \
+ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \
+ : NULL)
+
+/* Same as previous macro, but useful when we know that the buffer stack is not
+ * NULL or when we need an lvalue. For internal use only.
+ */
+#define YY_CURRENT_BUFFER_LVALUE (yy_buffer_stack)[(yy_buffer_stack_top)]
+
+/* yy_hold_char holds the character lost when pcap_text is formed. */
+static char yy_hold_char;
+static int yy_n_chars; /* number of characters read into yy_ch_buf */
+int pcap_leng;
+
+/* Points to current character in buffer. */
+static char *yy_c_buf_p = (char *) 0;
+static int yy_init = 0; /* whether we need to initialize */
+static int yy_start = 0; /* start state number */
+
+/* Flag which is used to allow pcap_wrap()'s to do buffer switches
+ * instead of setting up a fresh pcap_in. A bit of a hack ...
+ */
+static int yy_did_buffer_switch_on_eof;
+
+void pcap_restart (FILE *input_file );
+void pcap__switch_to_buffer (YY_BUFFER_STATE new_buffer );
+YY_BUFFER_STATE pcap__create_buffer (FILE *file,int size );
+void pcap__delete_buffer (YY_BUFFER_STATE b );
+void pcap__flush_buffer (YY_BUFFER_STATE b );
+void pcap_push_buffer_state (YY_BUFFER_STATE new_buffer );
+void pcap_pop_buffer_state (void );
+
+static void pcap_ensure_buffer_stack (void );
+static void pcap__load_buffer_state (void );
+static void pcap__init_buffer (YY_BUFFER_STATE b,FILE *file );
+
+#define YY_FLUSH_BUFFER pcap__flush_buffer(YY_CURRENT_BUFFER )
+
+YY_BUFFER_STATE pcap__scan_buffer (char *base,yy_size_t size );
+YY_BUFFER_STATE pcap__scan_string (yyconst char *yy_str );
+YY_BUFFER_STATE pcap__scan_bytes (yyconst char *bytes,int len );
+
+void *pcap_alloc (yy_size_t );
+void *pcap_realloc (void *,yy_size_t );
+void pcap_free (void * );
+
+#define yy_new_buffer pcap__create_buffer
+
+#define yy_set_interactive(is_interactive) \
+ { \
+ if ( ! YY_CURRENT_BUFFER ){ \
+ pcap_ensure_buffer_stack (); \
+ YY_CURRENT_BUFFER_LVALUE = \
+ pcap__create_buffer(pcap_in,YY_BUF_SIZE ); \
+ } \
+ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \
+ }
+
+#define yy_set_bol(at_bol) \
+ { \
+ if ( ! YY_CURRENT_BUFFER ){\
+ pcap_ensure_buffer_stack (); \
+ YY_CURRENT_BUFFER_LVALUE = \
+ pcap__create_buffer(pcap_in,YY_BUF_SIZE ); \
+ } \
+ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \
+ }
+
+#define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol)
+
+/* Begin user sect3 */
+
+typedef unsigned char YY_CHAR;
+
+FILE *pcap_in = (FILE *) 0, *pcap_out = (FILE *) 0;
+
+typedef int yy_state_type;
+
+extern int pcap_lineno;
+
+int pcap_lineno = 1;
+
+extern char *pcap_text;
+#define yytext_ptr pcap_text
+
+static yy_state_type yy_get_previous_state (void );
+static yy_state_type yy_try_NUL_trans (yy_state_type current_state );
+static int yy_get_next_buffer (void );
+static void yy_fatal_error (yyconst char msg[] );
+
+/* Done after the current pattern has been matched and before the
+ * corresponding action - sets up pcap_text.
+ */
+#define YY_DO_BEFORE_ACTION \
+ (yytext_ptr) = yy_bp; \
+ pcap_leng = (size_t) (yy_cp - yy_bp); \
+ (yy_hold_char) = *yy_cp; \
+ *yy_cp = '\0'; \
+ (yy_c_buf_p) = yy_cp;
+
+#define YY_NUM_RULES 52
+#define YY_END_OF_BUFFER 53
+/* This struct is not used in this scanner,
+ but its presence is necessary. */
+struct yy_trans_info
+ {
+ flex_int32_t yy_verify;
+ flex_int32_t yy_nxt;
+ };
+static yyconst flex_int16_t yy_accept[217] =
+ { 0,
+ 0, 0, 53, 51, 36, 36, 37, 37, 37, 37,
+ 51, 44, 44, 37, 37, 37, 51, 51, 51, 51,
+ 51, 51, 51, 51, 51, 51, 51, 51, 51, 51,
+ 51, 51, 51, 51, 51, 51, 37, 0, 50, 40,
+ 30, 0, 48, 44, 0, 48, 48, 48, 42, 39,
+ 41, 38, 43, 49, 49, 49, 48, 48, 48, 48,
+ 48, 48, 48, 48, 48, 48, 48, 48, 48, 48,
+ 48, 7, 48, 48, 48, 48, 48, 48, 48, 48,
+ 31, 48, 48, 48, 48, 48, 48, 48, 48, 48,
+ 48, 31, 45, 45, 44, 0, 0, 44, 30, 5,
+
+ 48, 48, 48, 48, 1, 48, 48, 48, 48, 48,
+ 48, 48, 48, 48, 15, 33, 48, 48, 48, 48,
+ 48, 20, 32, 48, 48, 3, 48, 48, 16, 48,
+ 2, 8, 9, 48, 48, 0, 47, 0, 48, 48,
+ 27, 48, 48, 4, 48, 48, 19, 10, 11, 12,
+ 48, 48, 25, 21, 48, 48, 48, 48, 22, 48,
+ 6, 45, 45, 45, 0, 47, 0, 13, 48, 48,
+ 48, 48, 48, 48, 18, 17, 48, 48, 23, 48,
+ 48, 0, 47, 48, 14, 48, 48, 48, 33, 48,
+ 48, 45, 45, 45, 0, 48, 24, 26, 34, 48,
+
+ 48, 48, 0, 47, 48, 48, 35, 45, 0, 28,
+ 29, 0, 47, 46, 46, 0
+ } ;
+
+static yyconst flex_int32_t yy_ec[256] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 2, 3,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 2, 4, 1, 1, 1, 1, 5, 1, 6,
+ 6, 7, 7, 1, 8, 9, 7, 10, 11, 11,
+ 11, 11, 11, 11, 11, 11, 11, 12, 1, 13,
+ 14, 15, 1, 1, 16, 16, 16, 16, 16, 16,
+ 17, 17, 17, 17, 17, 17, 17, 17, 17, 17,
+ 17, 17, 17, 17, 17, 17, 17, 18, 17, 17,
+ 19, 20, 19, 1, 21, 1, 22, 23, 24, 25,
+
+ 26, 27, 28, 29, 30, 17, 31, 32, 33, 34,
+ 35, 36, 17, 37, 38, 39, 40, 17, 41, 42,
+ 43, 17, 1, 44, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1
+ } ;
+
+static yyconst flex_int32_t yy_meta[45] =
+ { 0,
+ 1, 2, 2, 2, 1, 2, 1, 1, 1, 3,
+ 3, 3, 1, 1, 1, 3, 1, 1, 1, 1,
+ 1, 3, 3, 3, 3, 3, 3, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1
+ } ;
+
+static yyconst flex_int16_t yy_base[230] =
+ { 0,
+ 0, 0, 381, 44, 382, 382, 366, 374, 382, 45,
+ 382, 68, 29, 35, 364, 39, 103, 137, 121, 171,
+ 24, 92, 86, 131, 33, 342, 108, 113, 47, 24,
+ 79, 136, 354, 36, 351, 349, 329, 176, 382, 382,
+ 382, 0, 127, 175, 360, 359, 0, 204, 382, 382,
+ 382, 382, 382, 191, 0, 0, 345, 333, 346, 332,
+ 327, 103, 326, 335, 142, 324, 336, 323, 327, 29,
+ 336, 0, 319, 140, 323, 318, 319, 322, 314, 313,
+ 0, 312, 313, 313, 313, 310, 324, 315, 320, 307,
+ 306, 382, 191, 184, 207, 329, 328, 330, 0, 0,
+
+ 306, 315, 310, 301, 0, 308, 303, 306, 309, 291,
+ 293, 292, 291, 291, 0, 297, 286, 292, 291, 115,
+ 282, 0, 0, 297, 280, 0, 279, 281, 0, 280,
+ 0, 0, 0, 147, 224, 303, 302, 301, 281, 286,
+ 0, 284, 272, 0, 267, 268, 0, 0, 0, 0,
+ 266, 266, 0, 0, 272, 279, 272, 266, 0, 265,
+ 0, 214, 227, 290, 286, 284, 276, 0, 263, 247,
+ 263, 258, 248, 252, 0, 0, 256, 239, 0, 165,
+ 247, 263, 256, 245, 0, 223, 228, 239, 0, 240,
+ 227, 234, 180, 251, 247, 217, 0, 0, 0, 216,
+
+ 228, 267, 231, 230, 202, 200, 0, 0, 210, 0,
+ 0, 207, 200, 195, 192, 382, 294, 196, 194, 166,
+ 163, 147, 131, 121, 114, 85, 80, 78, 69
+ } ;
+
+static yyconst flex_int16_t yy_def[230] =
+ { 0,
+ 216, 1, 216, 216, 216, 216, 216, 216, 216, 216,
+ 216, 216, 12, 216, 216, 216, 12, 12, 217, 12,
+ 20, 20, 20, 20, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 18, 18, 18, 216, 216, 216, 216,
+ 216, 18, 18, 18, 218, 18, 18, 18, 216, 216,
+ 216, 216, 216, 217, 217, 217, 18, 18, 18, 18,
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 216, 18, 18, 18, 219, 220, 48, 18, 18,
+
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 18, 18, 216, 221, 222, 18, 18,
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 135, 223, 220, 216, 18, 18, 18,
+ 18, 18, 18, 18, 18, 18, 18, 18, 18, 18,
+ 18, 216, 224, 18, 18, 18, 18, 18, 18, 18,
+ 18, 18, 18, 181, 225, 18, 18, 18, 18, 18,
+
+ 18, 18, 216, 226, 18, 18, 18, 202, 227, 18,
+ 18, 216, 228, 229, 216, 0, 216, 216, 216, 216,
+ 216, 216, 216, 216, 216, 216, 216, 216, 216
+ } ;
+
+static yyconst flex_int16_t yy_nxt[427] =
+ { 0,
+ 4, 5, 6, 7, 8, 9, 10, 9, 11, 12,
+ 13, 10, 14, 15, 16, 17, 18, 18, 9, 19,
+ 11, 20, 21, 17, 22, 23, 24, 25, 26, 27,
+ 18, 28, 29, 30, 31, 32, 33, 34, 35, 36,
+ 18, 18, 18, 37, 38, 38, 47, 49, 50, 79,
+ 38, 38, 52, 53, 66, 38, 38, 47, 80, 87,
+ 60, 112, 47, 38, 38, 113, 61, 88, 76, 67,
+ 47, 215, 89, 39, 39, 42, 43, 44, 44, 45,
+ 214, 77, 212, 46, 47, 48, 78, 209, 42, 46,
+ 46, 46, 46, 46, 46, 47, 47, 47, 47, 47,
+
+ 47, 47, 47, 47, 47, 47, 47, 47, 47, 48,
+ 47, 47, 46, 46, 45, 81, 203, 62, 82, 47,
+ 47, 54, 47, 195, 64, 47, 104, 54, 47, 63,
+ 47, 69, 54, 182, 73, 70, 93, 94, 74, 155,
+ 54, 71, 75, 72, 47, 47, 47, 47, 216, 167,
+ 56, 156, 47, 45, 47, 65, 162, 163, 47, 47,
+ 47, 47, 47, 47, 47, 165, 107, 47, 138, 47,
+ 83, 84, 85, 116, 192, 193, 38, 117, 47, 47,
+ 46, 46, 38, 43, 95, 95, 45, 38, 47, 193,
+ 193, 54, 134, 94, 94, 38, 136, 54, 96, 134,
+
+ 94, 94, 54, 166, 57, 39, 166, 58, 135, 59,
+ 54, 166, 47, 98, 98, 43, 95, 95, 213, 98,
+ 56, 213, 180, 163, 163, 98, 98, 98, 98, 98,
+ 98, 181, 135, 164, 164, 180, 163, 163, 211, 164,
+ 210, 166, 204, 193, 193, 164, 164, 164, 164, 164,
+ 164, 202, 207, 206, 205, 181, 194, 194, 204, 180,
+ 201, 200, 194, 199, 198, 197, 196, 166, 194, 194,
+ 194, 194, 194, 194, 183, 202, 208, 208, 191, 190,
+ 189, 188, 208, 187, 186, 185, 184, 166, 208, 208,
+ 208, 208, 208, 208, 55, 166, 55, 183, 134, 179,
+
+ 178, 177, 176, 175, 174, 173, 172, 171, 126, 170,
+ 169, 168, 166, 166, 137, 126, 161, 160, 159, 158,
+ 157, 154, 126, 153, 152, 151, 150, 149, 148, 147,
+ 146, 145, 144, 143, 142, 141, 140, 139, 43, 97,
+ 137, 133, 132, 131, 130, 129, 128, 127, 126, 125,
+ 124, 123, 122, 121, 120, 119, 118, 115, 114, 111,
+ 110, 109, 108, 106, 105, 103, 102, 101, 100, 99,
+ 45, 97, 92, 91, 90, 86, 68, 51, 41, 40,
+ 216, 3, 216, 216, 216, 216, 216, 216, 216, 216,
+ 216, 216, 216, 216, 216, 216, 216, 216, 216, 216,
+
+ 216, 216, 216, 216, 216, 216, 216, 216, 216, 216,
+ 216, 216, 216, 216, 216, 216, 216, 216, 216, 216,
+ 216, 216, 216, 216, 216, 216
+ } ;
+
+static yyconst flex_int16_t yy_chk[427] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 4, 10, 13, 14, 14, 30,
+ 4, 10, 16, 16, 25, 4, 10, 21, 30, 34,
+ 21, 70, 21, 4, 10, 70, 21, 34, 29, 25,
+ 13, 229, 34, 4, 10, 12, 12, 12, 12, 12,
+ 228, 29, 227, 12, 12, 12, 29, 226, 12, 12,
+ 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,
+
+ 12, 12, 12, 12, 12, 12, 12, 12, 12, 12,
+ 12, 17, 17, 17, 62, 31, 225, 22, 31, 23,
+ 17, 19, 23, 224, 23, 22, 62, 19, 22, 22,
+ 22, 27, 19, 223, 28, 27, 43, 43, 28, 120,
+ 19, 27, 28, 27, 17, 18, 18, 18, 18, 222,
+ 19, 120, 18, 65, 18, 24, 134, 134, 18, 18,
+ 18, 18, 18, 18, 24, 221, 65, 24, 220, 24,
+ 32, 32, 32, 74, 180, 180, 38, 74, 18, 20,
+ 20, 20, 38, 44, 44, 44, 44, 38, 20, 193,
+ 193, 54, 94, 94, 94, 38, 219, 54, 218, 93,
+
+ 93, 93, 54, 215, 20, 38, 214, 20, 93, 20,
+ 54, 213, 20, 48, 48, 95, 95, 95, 212, 48,
+ 54, 209, 162, 162, 162, 48, 48, 48, 48, 48,
+ 48, 162, 93, 135, 135, 163, 163, 163, 206, 135,
+ 205, 204, 203, 192, 192, 135, 135, 135, 135, 135,
+ 135, 192, 201, 200, 196, 162, 181, 181, 195, 194,
+ 191, 190, 181, 188, 187, 186, 184, 183, 181, 181,
+ 181, 181, 181, 181, 182, 192, 202, 202, 178, 177,
+ 174, 173, 202, 172, 171, 170, 169, 167, 202, 202,
+ 202, 202, 202, 202, 217, 166, 217, 165, 164, 160,
+
+ 158, 157, 156, 155, 152, 151, 146, 145, 143, 142,
+ 140, 139, 138, 137, 136, 130, 128, 127, 125, 124,
+ 121, 119, 118, 117, 116, 114, 113, 112, 111, 110,
+ 109, 108, 107, 106, 104, 103, 102, 101, 98, 97,
+ 96, 91, 90, 89, 88, 87, 86, 85, 84, 83,
+ 82, 80, 79, 78, 77, 76, 75, 73, 71, 69,
+ 68, 67, 66, 64, 63, 61, 60, 59, 58, 57,
+ 46, 45, 37, 36, 35, 33, 26, 15, 8, 7,
+ 3, 216, 216, 216, 216, 216, 216, 216, 216, 216,
+ 216, 216, 216, 216, 216, 216, 216, 216, 216, 216,
+
+ 216, 216, 216, 216, 216, 216, 216, 216, 216, 216,
+ 216, 216, 216, 216, 216, 216, 216, 216, 216, 216,
+ 216, 216, 216, 216, 216, 216
+ } ;
+
+static yy_state_type yy_last_accepting_state;
+static char *yy_last_accepting_cpos;
+
+extern int pcap__flex_debug;
+int pcap__flex_debug = 0;
+
+/* The intent behind this definition is that it'll catch
+ * any uses of REJECT which flex missed.
+ */
+#define REJECT reject_used_but_not_detected
+#define yymore() yymore_used_but_not_detected
+#define YY_MORE_ADJ 0
+#define YY_RESTORE_YY_MORE_OFFSET
+char *pcap_text;
+#line 1 "scanner.l"
+#line 2 "scanner.l"
+/*
+ * Copyright (c) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/scanner.l,v 1.1 1999/08/26 10:05:27 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+
+#include <ctype.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gencode.h"
+#include <pcap-namedb.h>
+#include "tokdefs.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+static int stoi(char *);
+static inline int xdtoi(int);
+
+#ifdef FLEX_SCANNER
+#define YY_NO_UNPUT
+#undef YY_INPUT
+#define YY_INPUT(buf, result, max)\
+ {\
+ char *src = in_buffer;\
+ int i;\
+\
+ if (*src == 0)\
+ result = YY_NULL;\
+ else {\
+ for (i = 0; *src && i < max; ++i)\
+ buf[i] = *src++;\
+ in_buffer += i;\
+ result = i;\
+ }\
+ }
+#else
+#undef getc
+#define getc(fp) (*in_buffer == 0 ? EOF : *in_buffer++)
+#endif
+
+#define yylval pcap_lval
+extern YYSTYPE yylval;
+
+static char *in_buffer;
+
+#line 694 "<stdout>"
+
+#define INITIAL 0
+
+#ifndef YY_NO_UNISTD_H
+/* Special case for "unistd.h", since it is non-ANSI. We include it way
+ * down here because we want the user's section 1 to have been scanned first.
+ * The user has a chance to override it with an option.
+ */
+#include <unistd.h>
+#endif
+
+#ifndef YY_EXTRA_TYPE
+#define YY_EXTRA_TYPE void *
+#endif
+
+static int yy_init_globals (void );
+
+/* Macros after this point can all be overridden by user definitions in
+ * section 1.
+ */
+
+#ifndef YY_SKIP_YYWRAP
+#ifdef __cplusplus
+extern "C" int pcap_wrap (void );
+#else
+extern int pcap_wrap (void );
+#endif
+#endif
+
+ static void yyunput (int c,char *buf_ptr );
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char *,yyconst char *,int );
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * );
+#endif
+
+#ifndef YY_NO_INPUT
+
+#ifdef __cplusplus
+static int yyinput (void );
+#else
+static int input (void );
+#endif
+
+#endif
+
+/* Amount of stuff to slurp up with each read. */
+#ifndef YY_READ_BUF_SIZE
+#define YY_READ_BUF_SIZE 8192
+#endif
+
+/* Copy whatever the last rule matched to the standard output. */
+#ifndef ECHO
+/* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+#define ECHO (void) fwrite( pcap_text, pcap_leng, 1, pcap_out )
+#endif
+
+/* Gets input and stuffs it into "buf". number of characters read, or YY_NULL,
+ * is returned in "result".
+ */
+#ifndef YY_INPUT
+#define YY_INPUT(buf,result,max_size) \
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
+ { \
+ int c = '*'; \
+ size_t n; \
+ for ( n = 0; n < max_size && \
+ (c = getc( pcap_in )) != EOF && c != '\n'; ++n ) \
+ buf[n] = (char) c; \
+ if ( c == '\n' ) \
+ buf[n++] = (char) c; \
+ if ( c == EOF && ferror( pcap_in ) ) \
+ YY_FATAL_ERROR( "input in flex scanner failed" ); \
+ result = n; \
+ } \
+ else \
+ { \
+ errno=0; \
+ while ( (result = fread(buf, 1, max_size, pcap_in))==0 && ferror(pcap_in)) \
+ { \
+ if( errno != EINTR) \
+ { \
+ YY_FATAL_ERROR( "input in flex scanner failed" ); \
+ break; \
+ } \
+ errno=0; \
+ clearerr(pcap_in); \
+ } \
+ }\
+\
+
+#endif
+
+/* No semi-colon after return; correct usage is to write "yyterminate();" -
+ * we don't want an extra ';' after the "return" because that will cause
+ * some compilers to complain about unreachable statements.
+ */
+#ifndef yyterminate
+#define yyterminate() return YY_NULL
+#endif
+
+/* Number of entries by which start-condition stack grows. */
+#ifndef YY_START_STACK_INCR
+#define YY_START_STACK_INCR 25
+#endif
+
+/* Report a fatal error. */
+#ifndef YY_FATAL_ERROR
+#define YY_FATAL_ERROR(msg) yy_fatal_error( msg )
+#endif
+
+/* end tables serialization structures and prototypes */
+
+/* Default declaration of generated scanner - a define so the user can
+ * easily add parameters.
+ */
+#ifndef YY_DECL
+#define YY_DECL_IS_OURS 1
+
+extern int pcap_lex (void);
+
+#define YY_DECL int pcap_lex (void)
+#endif /* !YY_DECL */
+
+/* Code executed at the beginning of each rule, after pcap_text and pcap_leng
+ * have been set up.
+ */
+#ifndef YY_USER_ACTION
+#define YY_USER_ACTION
+#endif
+
+/* Code executed at the end of each rule. */
+#ifndef YY_BREAK
+#define YY_BREAK break;
+#endif
+
+#define YY_RULE_SETUP \
+ YY_USER_ACTION
+
+/** The main scanner function which does all the work.
+ */
+YY_DECL
+{
+ register yy_state_type yy_current_state;
+ register char *yy_cp, *yy_bp;
+ register int yy_act;
+
+#line 82 "scanner.l"
+
+#line 849 "<stdout>"
+
+ if ( !(yy_init) )
+ {
+ (yy_init) = 1;
+
+#ifdef YY_USER_INIT
+ YY_USER_INIT;
+#endif
+
+ if ( ! (yy_start) )
+ (yy_start) = 1; /* first start state */
+
+ if ( ! pcap_in )
+ pcap_in = stdin;
+
+ if ( ! pcap_out )
+ pcap_out = stdout;
+
+ if ( ! YY_CURRENT_BUFFER ) {
+ pcap_ensure_buffer_stack ();
+ YY_CURRENT_BUFFER_LVALUE =
+ pcap__create_buffer(pcap_in,YY_BUF_SIZE );
+ }
+
+ pcap__load_buffer_state( );
+ }
+
+ while ( 1 ) /* loops until end-of-file is reached */
+ {
+ yy_cp = (yy_c_buf_p);
+
+ /* Support of pcap_text. */
+ *yy_cp = (yy_hold_char);
+
+ /* yy_bp points to the position in yy_ch_buf of the start of
+ * the current run.
+ */
+ yy_bp = yy_cp;
+
+ yy_current_state = (yy_start);
+yy_match:
+ do
+ {
+ register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 217 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ ++yy_cp;
+ }
+ while ( yy_base[yy_current_state] != 382 );
+
+yy_find_action:
+ yy_act = yy_accept[yy_current_state];
+ if ( yy_act == 0 )
+ { /* have to back up */
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+ yy_act = yy_accept[yy_current_state];
+ }
+
+ YY_DO_BEFORE_ACTION;
+
+do_action: /* This label is used only to access EOF actions. */
+
+ switch ( yy_act )
+ { /* beginning of action switch */
+ case 0: /* must back up */
+ /* undo the effects of YY_DO_BEFORE_ACTION */
+ *yy_cp = (yy_hold_char);
+ yy_cp = (yy_last_accepting_cpos);
+ yy_current_state = (yy_last_accepting_state);
+ goto yy_find_action;
+
+case 1:
+YY_RULE_SETUP
+#line 83 "scanner.l"
+return DST;
+ YY_BREAK
+case 2:
+YY_RULE_SETUP
+#line 84 "scanner.l"
+return SRC;
+ YY_BREAK
+case 3:
+YY_RULE_SETUP
+#line 86 "scanner.l"
+return LINK;
+ YY_BREAK
+case 4:
+YY_RULE_SETUP
+#line 87 "scanner.l"
+return LINK;
+ YY_BREAK
+case 5:
+YY_RULE_SETUP
+#line 88 "scanner.l"
+return ARP;
+ YY_BREAK
+case 6:
+YY_RULE_SETUP
+#line 89 "scanner.l"
+return RARP;
+ YY_BREAK
+case 7:
+YY_RULE_SETUP
+#line 90 "scanner.l"
+return IP;
+ YY_BREAK
+case 8:
+YY_RULE_SETUP
+#line 91 "scanner.l"
+return TCP;
+ YY_BREAK
+case 9:
+YY_RULE_SETUP
+#line 92 "scanner.l"
+return UDP;
+ YY_BREAK
+case 10:
+YY_RULE_SETUP
+#line 93 "scanner.l"
+return ICMP;
+ YY_BREAK
+case 11:
+YY_RULE_SETUP
+#line 94 "scanner.l"
+return IGMP;
+ YY_BREAK
+case 12:
+YY_RULE_SETUP
+#line 95 "scanner.l"
+return IGRP;
+ YY_BREAK
+case 13:
+YY_RULE_SETUP
+#line 97 "scanner.l"
+return ATALK;
+ YY_BREAK
+case 14:
+YY_RULE_SETUP
+#line 98 "scanner.l"
+return DECNET;
+ YY_BREAK
+case 15:
+YY_RULE_SETUP
+#line 99 "scanner.l"
+return LAT;
+ YY_BREAK
+case 16:
+YY_RULE_SETUP
+#line 100 "scanner.l"
+return SCA;
+ YY_BREAK
+case 17:
+YY_RULE_SETUP
+#line 101 "scanner.l"
+return MOPRC;
+ YY_BREAK
+case 18:
+YY_RULE_SETUP
+#line 102 "scanner.l"
+return MOPDL;
+ YY_BREAK
+case 19:
+YY_RULE_SETUP
+#line 104 "scanner.l"
+return HOST;
+ YY_BREAK
+case 20:
+YY_RULE_SETUP
+#line 105 "scanner.l"
+return NET;
+ YY_BREAK
+case 21:
+YY_RULE_SETUP
+#line 106 "scanner.l"
+return MASK;
+ YY_BREAK
+case 22:
+YY_RULE_SETUP
+#line 107 "scanner.l"
+return PORT;
+ YY_BREAK
+case 23:
+YY_RULE_SETUP
+#line 108 "scanner.l"
+return PROTO;
+ YY_BREAK
+case 24:
+YY_RULE_SETUP
+#line 110 "scanner.l"
+return GATEWAY;
+ YY_BREAK
+case 25:
+YY_RULE_SETUP
+#line 112 "scanner.l"
+return LESS;
+ YY_BREAK
+case 26:
+YY_RULE_SETUP
+#line 113 "scanner.l"
+return GREATER;
+ YY_BREAK
+case 27:
+YY_RULE_SETUP
+#line 114 "scanner.l"
+return BYTE;
+ YY_BREAK
+case 28:
+YY_RULE_SETUP
+#line 115 "scanner.l"
+return TK_BROADCAST;
+ YY_BREAK
+case 29:
+YY_RULE_SETUP
+#line 116 "scanner.l"
+return TK_MULTICAST;
+ YY_BREAK
+case 30:
+YY_RULE_SETUP
+#line 118 "scanner.l"
+return AND;
+ YY_BREAK
+case 31:
+YY_RULE_SETUP
+#line 119 "scanner.l"
+return OR;
+ YY_BREAK
+case 32:
+YY_RULE_SETUP
+#line 120 "scanner.l"
+return '!';
+ YY_BREAK
+case 33:
+YY_RULE_SETUP
+#line 122 "scanner.l"
+return LEN;
+ YY_BREAK
+case 34:
+YY_RULE_SETUP
+#line 123 "scanner.l"
+return INBOUND;
+ YY_BREAK
+case 35:
+YY_RULE_SETUP
+#line 124 "scanner.l"
+return OUTBOUND;
+ YY_BREAK
+case 36:
+/* rule 36 can match eol */
+YY_RULE_SETUP
+#line 126 "scanner.l"
+;
+ YY_BREAK
+case 37:
+YY_RULE_SETUP
+#line 127 "scanner.l"
+return pcap_text[0];
+ YY_BREAK
+case 38:
+YY_RULE_SETUP
+#line 128 "scanner.l"
+return GEQ;
+ YY_BREAK
+case 39:
+YY_RULE_SETUP
+#line 129 "scanner.l"
+return LEQ;
+ YY_BREAK
+case 40:
+YY_RULE_SETUP
+#line 130 "scanner.l"
+return NEQ;
+ YY_BREAK
+case 41:
+YY_RULE_SETUP
+#line 131 "scanner.l"
+return '=';
+ YY_BREAK
+case 42:
+YY_RULE_SETUP
+#line 132 "scanner.l"
+return LSH;
+ YY_BREAK
+case 43:
+YY_RULE_SETUP
+#line 133 "scanner.l"
+return RSH;
+ YY_BREAK
+case 44:
+YY_RULE_SETUP
+#line 134 "scanner.l"
+{ yylval.i = stoi((char *)pcap_text); return NUM; }
+ YY_BREAK
+case 45:
+YY_RULE_SETUP
+#line 135 "scanner.l"
+{
+ yylval.s = sdup((char *)pcap_text); return HID; }
+ YY_BREAK
+case 46:
+YY_RULE_SETUP
+#line 137 "scanner.l"
+{ yylval.e = pcap_ether_aton((char *)pcap_text);
+ return EID; }
+ YY_BREAK
+case 47:
+YY_RULE_SETUP
+#line 139 "scanner.l"
+{ bpf_error("bogus ethernet address %s", pcap_text); }
+ YY_BREAK
+case 48:
+YY_RULE_SETUP
+#line 140 "scanner.l"
+{
+ yylval.s = sdup((char *)pcap_text); return ID; }
+ YY_BREAK
+case 49:
+YY_RULE_SETUP
+#line 142 "scanner.l"
+{ yylval.s = sdup((char *)pcap_text + 1); return ID; }
+ YY_BREAK
+case 50:
+YY_RULE_SETUP
+#line 143 "scanner.l"
+{
+ bpf_error("illegal token: %s\n", pcap_text); }
+ YY_BREAK
+case 51:
+YY_RULE_SETUP
+#line 145 "scanner.l"
+{ bpf_error("illegal char '%c'", *pcap_text); }
+ YY_BREAK
+case 52:
+YY_RULE_SETUP
+#line 146 "scanner.l"
+ECHO;
+ YY_BREAK
+#line 1197 "<stdout>"
+case YY_STATE_EOF(INITIAL):
+ yyterminate();
+
+ case YY_END_OF_BUFFER:
+ {
+ /* Amount of text matched not including the EOB char. */
+ int yy_amount_of_matched_text = (int) (yy_cp - (yytext_ptr)) - 1;
+
+ /* Undo the effects of YY_DO_BEFORE_ACTION. */
+ *yy_cp = (yy_hold_char);
+ YY_RESTORE_YY_MORE_OFFSET
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_NEW )
+ {
+ /* We're scanning a new file or input source. It's
+ * possible that this happened because the user
+ * just pointed pcap_in at a new source and called
+ * pcap_lex(). If so, then we have to assure
+ * consistency between YY_CURRENT_BUFFER and our
+ * globals. Here is the right place to do so, because
+ * this is the first action (other than possibly a
+ * back-up) that will match for the new input source.
+ */
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+ YY_CURRENT_BUFFER_LVALUE->yy_input_file = pcap_in;
+ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status = YY_BUFFER_NORMAL;
+ }
+
+ /* Note that here we test for yy_c_buf_p "<=" to the position
+ * of the first EOB in the buffer, since yy_c_buf_p will
+ * already have been incremented past the NUL character
+ * (since all states make transitions on EOB to the
+ * end-of-buffer state). Contrast this with the test
+ * in input().
+ */
+ if ( (yy_c_buf_p) <= &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+ { /* This was really a NUL. */
+ yy_state_type yy_next_state;
+
+ (yy_c_buf_p) = (yytext_ptr) + yy_amount_of_matched_text;
+
+ yy_current_state = yy_get_previous_state( );
+
+ /* Okay, we're now positioned to make the NUL
+ * transition. We couldn't have
+ * yy_get_previous_state() go ahead and do it
+ * for us because it doesn't know how to deal
+ * with the possibility of jamming (and we don't
+ * want to build jamming into it because then it
+ * will run more slowly).
+ */
+
+ yy_next_state = yy_try_NUL_trans( yy_current_state );
+
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+
+ if ( yy_next_state )
+ {
+ /* Consume the NUL. */
+ yy_cp = ++(yy_c_buf_p);
+ yy_current_state = yy_next_state;
+ goto yy_match;
+ }
+
+ else
+ {
+ yy_cp = (yy_c_buf_p);
+ goto yy_find_action;
+ }
+ }
+
+ else switch ( yy_get_next_buffer( ) )
+ {
+ case EOB_ACT_END_OF_FILE:
+ {
+ (yy_did_buffer_switch_on_eof) = 0;
+
+ if ( pcap_wrap( ) )
+ {
+ /* Note: because we've taken care in
+ * yy_get_next_buffer() to have set up
+ * pcap_text, we can now set up
+ * yy_c_buf_p so that if some total
+ * hoser (like flex itself) wants to
+ * call the scanner after we return the
+ * YY_NULL, it'll still work - another
+ * YY_NULL will get returned.
+ */
+ (yy_c_buf_p) = (yytext_ptr) + YY_MORE_ADJ;
+
+ yy_act = YY_STATE_EOF(YY_START);
+ goto do_action;
+ }
+
+ else
+ {
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+ }
+ break;
+ }
+
+ case EOB_ACT_CONTINUE_SCAN:
+ (yy_c_buf_p) =
+ (yytext_ptr) + yy_amount_of_matched_text;
+
+ yy_current_state = yy_get_previous_state( );
+
+ yy_cp = (yy_c_buf_p);
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+ goto yy_match;
+
+ case EOB_ACT_LAST_MATCH:
+ (yy_c_buf_p) =
+ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)];
+
+ yy_current_state = yy_get_previous_state( );
+
+ yy_cp = (yy_c_buf_p);
+ yy_bp = (yytext_ptr) + YY_MORE_ADJ;
+ goto yy_find_action;
+ }
+ break;
+ }
+
+ default:
+ YY_FATAL_ERROR(
+ "fatal flex scanner internal error--no action found" );
+ } /* end of action switch */
+ } /* end of scanning one token */
+} /* end of pcap_lex */
+
+/* yy_get_next_buffer - try to read in a new buffer
+ *
+ * Returns a code representing an action:
+ * EOB_ACT_LAST_MATCH -
+ * EOB_ACT_CONTINUE_SCAN - continue scanning from current position
+ * EOB_ACT_END_OF_FILE - end of file
+ */
+static int yy_get_next_buffer (void)
+{
+ register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+ register char *source = (yytext_ptr);
+ register int number_to_move, i;
+ int ret_val;
+
+ if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+ YY_FATAL_ERROR(
+ "fatal flex scanner internal error--end of buffer missed" );
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_fill_buffer == 0 )
+ { /* Don't try to fill the buffer, so this is an EOF. */
+ if ( (yy_c_buf_p) - (yytext_ptr) - YY_MORE_ADJ == 1 )
+ {
+ /* We matched a single character, the EOB, so
+ * treat this as a final EOF.
+ */
+ return EOB_ACT_END_OF_FILE;
+ }
+
+ else
+ {
+ /* We matched some text prior to the EOB, first
+ * process it.
+ */
+ return EOB_ACT_LAST_MATCH;
+ }
+ }
+
+ /* Try to read more data. */
+
+ /* First move last chars to start of buffer. */
+ number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+ for ( i = 0; i < number_to_move; ++i )
+ *(dest++) = *(source++);
+
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_buffer_status == YY_BUFFER_EOF_PENDING )
+ /* don't do the read, it's not guaranteed to return an EOF,
+ * just force an EOF
+ */
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars) = 0;
+
+ else
+ {
+ int num_to_read =
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+ while ( num_to_read <= 0 )
+ { /* Not enough room in the buffer - grow it. */
+
+ /* just a shorter name for the current buffer */
+ YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
+
+ int yy_c_buf_p_offset =
+ (int) ((yy_c_buf_p) - b->yy_ch_buf);
+
+ if ( b->yy_is_our_buffer )
+ {
+ int new_size = b->yy_buf_size * 2;
+
+ if ( new_size <= 0 )
+ b->yy_buf_size += b->yy_buf_size / 8;
+ else
+ b->yy_buf_size *= 2;
+
+ b->yy_ch_buf = (char *)
+ /* Include room in for 2 EOB chars. */
+ pcap_realloc((void *) b->yy_ch_buf,b->yy_buf_size + 2 );
+ }
+ else
+ /* Can't grow it, we don't own it. */
+ b->yy_ch_buf = 0;
+
+ if ( ! b->yy_ch_buf )
+ YY_FATAL_ERROR(
+ "fatal error - scanner input buffer overflow" );
+
+ (yy_c_buf_p) = &b->yy_ch_buf[yy_c_buf_p_offset];
+
+ num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size -
+ number_to_move - 1;
+
+ }
+
+ if ( num_to_read > YY_READ_BUF_SIZE )
+ num_to_read = YY_READ_BUF_SIZE;
+
+ /* Read in more data. */
+ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]),
+ (yy_n_chars), (size_t) num_to_read );
+
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ if ( (yy_n_chars) == 0 )
+ {
+ if ( number_to_move == YY_MORE_ADJ )
+ {
+ ret_val = EOB_ACT_END_OF_FILE;
+ pcap_restart(pcap_in );
+ }
+
+ else
+ {
+ ret_val = EOB_ACT_LAST_MATCH;
+ YY_CURRENT_BUFFER_LVALUE->yy_buffer_status =
+ YY_BUFFER_EOF_PENDING;
+ }
+ }
+
+ else
+ ret_val = EOB_ACT_CONTINUE_SCAN;
+
+ (yy_n_chars) += number_to_move;
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] = YY_END_OF_BUFFER_CHAR;
+ YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] = YY_END_OF_BUFFER_CHAR;
+
+ (yytext_ptr) = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[0];
+
+ return ret_val;
+}
+
+/* yy_get_previous_state - get the state just before the EOB char was reached */
+
+ static yy_state_type yy_get_previous_state (void)
+{
+ register yy_state_type yy_current_state;
+ register char *yy_cp;
+
+ yy_current_state = (yy_start);
+
+ for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+ {
+ register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 217 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ }
+
+ return yy_current_state;
+}
+
+/* yy_try_NUL_trans - try to make a transition on the NUL character
+ *
+ * synopsis
+ * next_state = yy_try_NUL_trans( current_state );
+ */
+ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state )
+{
+ register int yy_is_jam;
+ register char *yy_cp = (yy_c_buf_p);
+
+ register YY_CHAR yy_c = 1;
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+ (yy_last_accepting_cpos) = yy_cp;
+ }
+ while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state )
+ {
+ yy_current_state = (int) yy_def[yy_current_state];
+ if ( yy_current_state >= 217 )
+ yy_c = yy_meta[(unsigned int) yy_c];
+ }
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ yy_is_jam = (yy_current_state == 216);
+
+ return yy_is_jam ? 0 : yy_current_state;
+}
+
+ static void yyunput (int c, register char * yy_bp )
+{
+ register char *yy_cp;
+
+ yy_cp = (yy_c_buf_p);
+
+ /* undo effects of setting up pcap_text */
+ *yy_cp = (yy_hold_char);
+
+ if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+ { /* need to shift things up to make room */
+ /* +2 for EOB chars. */
+ register int number_to_move = (yy_n_chars) + 2;
+ register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2];
+ register char *source =
+ &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move];
+
+ while ( source > YY_CURRENT_BUFFER_LVALUE->yy_ch_buf )
+ *--dest = *--source;
+
+ yy_cp += (int) (dest - source);
+ yy_bp += (int) (dest - source);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars =
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_buf_size;
+
+ if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 )
+ YY_FATAL_ERROR( "flex scanner push-back overflow" );
+ }
+
+ *--yy_cp = (char) c;
+
+ (yytext_ptr) = yy_bp;
+ (yy_hold_char) = *yy_cp;
+ (yy_c_buf_p) = yy_cp;
+}
+
+#ifndef YY_NO_INPUT
+#ifdef __cplusplus
+ static int yyinput (void)
+#else
+ static int input (void)
+#endif
+
+{
+ int c;
+
+ *(yy_c_buf_p) = (yy_hold_char);
+
+ if ( *(yy_c_buf_p) == YY_END_OF_BUFFER_CHAR )
+ {
+ /* yy_c_buf_p now points to the character we want to return.
+ * If this occurs *before* the EOB characters, then it's a
+ * valid NUL; if not, then we've hit the end of the buffer.
+ */
+ if ( (yy_c_buf_p) < &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars)] )
+ /* This was really a NUL. */
+ *(yy_c_buf_p) = '\0';
+
+ else
+ { /* need more input */
+ int offset = (yy_c_buf_p) - (yytext_ptr);
+ ++(yy_c_buf_p);
+
+ switch ( yy_get_next_buffer( ) )
+ {
+ case EOB_ACT_LAST_MATCH:
+ /* This happens because yy_g_n_b()
+ * sees that we've accumulated a
+ * token and flags that we need to
+ * try matching the token before
+ * proceeding. But for input(),
+ * there's no matching to consider.
+ * So convert the EOB_ACT_LAST_MATCH
+ * to EOB_ACT_END_OF_FILE.
+ */
+
+ /* Reset buffer status. */
+ pcap_restart(pcap_in );
+
+ /*FALLTHROUGH*/
+
+ case EOB_ACT_END_OF_FILE:
+ {
+ if ( pcap_wrap( ) )
+ return EOF;
+
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+#ifdef __cplusplus
+ return yyinput();
+#else
+ return input();
+#endif
+ }
+
+ case EOB_ACT_CONTINUE_SCAN:
+ (yy_c_buf_p) = (yytext_ptr) + offset;
+ break;
+ }
+ }
+ }
+
+ c = *(unsigned char *) (yy_c_buf_p); /* cast for 8-bit char's */
+ *(yy_c_buf_p) = '\0'; /* preserve pcap_text */
+ (yy_hold_char) = *++(yy_c_buf_p);
+
+ return c;
+}
+#endif /* ifndef YY_NO_INPUT */
+
+/** Immediately switch to a different input stream.
+ * @param input_file A readable stream.
+ *
+ * @note This function does not reset the start condition to @c INITIAL .
+ */
+ void pcap_restart (FILE * input_file )
+{
+
+ if ( ! YY_CURRENT_BUFFER ){
+ pcap_ensure_buffer_stack ();
+ YY_CURRENT_BUFFER_LVALUE =
+ pcap__create_buffer(pcap_in,YY_BUF_SIZE );
+ }
+
+ pcap__init_buffer(YY_CURRENT_BUFFER,input_file );
+ pcap__load_buffer_state( );
+}
+
+/** Switch to a different input buffer.
+ * @param new_buffer The new input buffer.
+ *
+ */
+ void pcap__switch_to_buffer (YY_BUFFER_STATE new_buffer )
+{
+
+ /* TODO. We should be able to replace this entire function body
+ * with
+ * pcap_pop_buffer_state();
+ * pcap_push_buffer_state(new_buffer);
+ */
+ pcap_ensure_buffer_stack ();
+ if ( YY_CURRENT_BUFFER == new_buffer )
+ return;
+
+ if ( YY_CURRENT_BUFFER )
+ {
+ /* Flush out information for old buffer. */
+ *(yy_c_buf_p) = (yy_hold_char);
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ YY_CURRENT_BUFFER_LVALUE = new_buffer;
+ pcap__load_buffer_state( );
+
+ /* We don't actually know whether we did this switch during
+ * EOF (pcap_wrap()) processing, but the only time this flag
+ * is looked at is after pcap_wrap() is called, so it's safe
+ * to go ahead and always set it.
+ */
+ (yy_did_buffer_switch_on_eof) = 1;
+}
+
+static void pcap__load_buffer_state (void)
+{
+ (yy_n_chars) = YY_CURRENT_BUFFER_LVALUE->yy_n_chars;
+ (yytext_ptr) = (yy_c_buf_p) = YY_CURRENT_BUFFER_LVALUE->yy_buf_pos;
+ pcap_in = YY_CURRENT_BUFFER_LVALUE->yy_input_file;
+ (yy_hold_char) = *(yy_c_buf_p);
+}
+
+/** Allocate and initialize an input buffer state.
+ * @param file A readable stream.
+ * @param size The character buffer size in bytes. When in doubt, use @c YY_BUF_SIZE.
+ *
+ * @return the allocated buffer state.
+ */
+ YY_BUFFER_STATE pcap__create_buffer (FILE * file, int size )
+{
+ YY_BUFFER_STATE b;
+
+ b = (YY_BUFFER_STATE) pcap_alloc(sizeof( struct yy_buffer_state ) );
+ if ( ! b )
+ YY_FATAL_ERROR( "out of dynamic memory in pcap__create_buffer()" );
+
+ b->yy_buf_size = size;
+
+ /* yy_ch_buf has to be 2 characters longer than the size given because
+ * we need to put in 2 end-of-buffer characters.
+ */
+ b->yy_ch_buf = (char *) pcap_alloc(b->yy_buf_size + 2 );
+ if ( ! b->yy_ch_buf )
+ YY_FATAL_ERROR( "out of dynamic memory in pcap__create_buffer()" );
+
+ b->yy_is_our_buffer = 1;
+
+ pcap__init_buffer(b,file );
+
+ return b;
+}
+
+/** Destroy the buffer.
+ * @param b a buffer created with pcap__create_buffer()
+ *
+ */
+ void pcap__delete_buffer (YY_BUFFER_STATE b )
+{
+
+ if ( ! b )
+ return;
+
+ if ( b == YY_CURRENT_BUFFER ) /* Not sure if we should pop here. */
+ YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0;
+
+ if ( b->yy_is_our_buffer )
+ pcap_free((void *) b->yy_ch_buf );
+
+ pcap_free((void *) b );
+}
+
+#ifndef __cplusplus
+extern int isatty (int );
+#endif /* __cplusplus */
+
+/* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a pcap_restart() or at EOF.
+ */
+ static void pcap__init_buffer (YY_BUFFER_STATE b, FILE * file )
+
+{
+ int oerrno = errno;
+
+ pcap__flush_buffer(b );
+
+ b->yy_input_file = file;
+ b->yy_fill_buffer = 1;
+
+ /* If b is the current buffer, then pcap__init_buffer was _probably_
+ * called from pcap_restart() or through yy_get_next_buffer.
+ * In that case, we don't want to reset the lineno or column.
+ */
+ if (b != YY_CURRENT_BUFFER){
+ b->yy_bs_lineno = 1;
+ b->yy_bs_column = 0;
+ }
+
+ b->yy_is_interactive = file ? (isatty( fileno(file) ) > 0) : 0;
+
+ errno = oerrno;
+}
+
+/** Discard all buffered characters. On the next scan, YY_INPUT will be called.
+ * @param b the buffer state to be flushed, usually @c YY_CURRENT_BUFFER.
+ *
+ */
+ void pcap__flush_buffer (YY_BUFFER_STATE b )
+{
+ if ( ! b )
+ return;
+
+ b->yy_n_chars = 0;
+
+ /* We always need two end-of-buffer characters. The first causes
+ * a transition to the end-of-buffer state. The second causes
+ * a jam in that state.
+ */
+ b->yy_ch_buf[0] = YY_END_OF_BUFFER_CHAR;
+ b->yy_ch_buf[1] = YY_END_OF_BUFFER_CHAR;
+
+ b->yy_buf_pos = &b->yy_ch_buf[0];
+
+ b->yy_at_bol = 1;
+ b->yy_buffer_status = YY_BUFFER_NEW;
+
+ if ( b == YY_CURRENT_BUFFER )
+ pcap__load_buffer_state( );
+}
+
+/** Pushes the new state onto the stack. The new state becomes
+ * the current state. This function will allocate the stack
+ * if necessary.
+ * @param new_buffer The new state.
+ *
+ */
+void pcap_push_buffer_state (YY_BUFFER_STATE new_buffer )
+{
+ if (new_buffer == NULL)
+ return;
+
+ pcap_ensure_buffer_stack();
+
+ /* This block is copied from pcap__switch_to_buffer. */
+ if ( YY_CURRENT_BUFFER )
+ {
+ /* Flush out information for old buffer. */
+ *(yy_c_buf_p) = (yy_hold_char);
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_pos = (yy_c_buf_p);
+ YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars);
+ }
+
+ /* Only push if top exists. Otherwise, replace top. */
+ if (YY_CURRENT_BUFFER)
+ (yy_buffer_stack_top)++;
+ YY_CURRENT_BUFFER_LVALUE = new_buffer;
+
+ /* copied from pcap__switch_to_buffer. */
+ pcap__load_buffer_state( );
+ (yy_did_buffer_switch_on_eof) = 1;
+}
+
+/** Removes and deletes the top of the stack, if present.
+ * The next element becomes the new top.
+ *
+ */
+void pcap_pop_buffer_state (void)
+{
+ if (!YY_CURRENT_BUFFER)
+ return;
+
+ pcap__delete_buffer(YY_CURRENT_BUFFER );
+ YY_CURRENT_BUFFER_LVALUE = NULL;
+ if ((yy_buffer_stack_top) > 0)
+ --(yy_buffer_stack_top);
+
+ if (YY_CURRENT_BUFFER) {
+ pcap__load_buffer_state( );
+ (yy_did_buffer_switch_on_eof) = 1;
+ }
+}
+
+/* Allocates the stack if it does not exist.
+ * Guarantees space for at least one push.
+ */
+static void pcap_ensure_buffer_stack (void)
+{
+ int num_to_alloc;
+
+ if (!(yy_buffer_stack)) {
+
+ /* First allocation is just for 2 elements, since we don't know if this
+ * scanner will even need a stack. We use 2 instead of 1 to avoid an
+ * immediate realloc on the next call.
+ */
+ num_to_alloc = 1;
+ (yy_buffer_stack) = (struct yy_buffer_state**)pcap_alloc
+ (num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+
+ memset((yy_buffer_stack), 0, num_to_alloc * sizeof(struct yy_buffer_state*));
+
+ (yy_buffer_stack_max) = num_to_alloc;
+ (yy_buffer_stack_top) = 0;
+ return;
+ }
+
+ if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+ /* Increase the buffer to prepare for a possible push. */
+ int grow_size = 8 /* arbitrary grow size */;
+
+ num_to_alloc = (yy_buffer_stack_max) + grow_size;
+ (yy_buffer_stack) = (struct yy_buffer_state**)pcap_realloc
+ ((yy_buffer_stack),
+ num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+
+ /* zero only the new slots.*/
+ memset((yy_buffer_stack) + (yy_buffer_stack_max), 0, grow_size * sizeof(struct yy_buffer_state*));
+ (yy_buffer_stack_max) = num_to_alloc;
+ }
+}
+
+/** Setup the input buffer state to scan directly from a user-specified character buffer.
+ * @param base the character buffer
+ * @param size the size in bytes of the character buffer
+ *
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE pcap__scan_buffer (char * base, yy_size_t size )
+{
+ YY_BUFFER_STATE b;
+
+ if ( size < 2 ||
+ base[size-2] != YY_END_OF_BUFFER_CHAR ||
+ base[size-1] != YY_END_OF_BUFFER_CHAR )
+ /* They forgot to leave room for the EOB's. */
+ return 0;
+
+ b = (YY_BUFFER_STATE) pcap_alloc(sizeof( struct yy_buffer_state ) );
+ if ( ! b )
+ YY_FATAL_ERROR( "out of dynamic memory in pcap__scan_buffer()" );
+
+ b->yy_buf_size = size - 2; /* "- 2" to take care of EOB's */
+ b->yy_buf_pos = b->yy_ch_buf = base;
+ b->yy_is_our_buffer = 0;
+ b->yy_input_file = 0;
+ b->yy_n_chars = b->yy_buf_size;
+ b->yy_is_interactive = 0;
+ b->yy_at_bol = 1;
+ b->yy_fill_buffer = 0;
+ b->yy_buffer_status = YY_BUFFER_NEW;
+
+ pcap__switch_to_buffer(b );
+
+ return b;
+}
+
+/** Setup the input buffer state to scan a string. The next call to pcap_lex() will
+ * scan from a @e copy of @a str.
+ * @param yystr a NUL-terminated string to scan
+ *
+ * @return the newly allocated buffer state object.
+ * @note If you want to scan bytes that may contain NUL values, then use
+ * pcap__scan_bytes() instead.
+ */
+YY_BUFFER_STATE pcap__scan_string (yyconst char * yystr )
+{
+
+ return pcap__scan_bytes(yystr,strlen(yystr) );
+}
+
+/** Setup the input buffer state to scan the given bytes. The next call to pcap_lex() will
+ * scan from a @e copy of @a bytes.
+ * @param bytes the byte buffer to scan
+ * @param len the number of bytes in the buffer pointed to by @a bytes.
+ *
+ * @return the newly allocated buffer state object.
+ */
+YY_BUFFER_STATE pcap__scan_bytes (yyconst char * yybytes, int _yybytes_len )
+{
+ YY_BUFFER_STATE b;
+ char *buf;
+ yy_size_t n;
+ int i;
+
+ /* Get memory for full buffer, including space for trailing EOB's. */
+ n = _yybytes_len + 2;
+ buf = (char *) pcap_alloc(n );
+ if ( ! buf )
+ YY_FATAL_ERROR( "out of dynamic memory in pcap__scan_bytes()" );
+
+ for ( i = 0; i < _yybytes_len; ++i )
+ buf[i] = yybytes[i];
+
+ buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR;
+
+ b = pcap__scan_buffer(buf,n );
+ if ( ! b )
+ YY_FATAL_ERROR( "bad buffer in pcap__scan_bytes()" );
+
+ /* It's okay to grow etc. this buffer, and we should throw it
+ * away when we're done.
+ */
+ b->yy_is_our_buffer = 1;
+
+ return b;
+}
+
+#ifndef YY_EXIT_FAILURE
+#define YY_EXIT_FAILURE 2
+#endif
+
+static void yy_fatal_error (yyconst char* msg )
+{
+ (void) fprintf( stderr, "%s\n", msg );
+ exit( YY_EXIT_FAILURE );
+}
+
+/* Redefine yyless() so it works in section 3 code. */
+
+#undef yyless
+#define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up pcap_text. */ \
+ int yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ pcap_text[pcap_leng] = (yy_hold_char); \
+ (yy_c_buf_p) = pcap_text + yyless_macro_arg; \
+ (yy_hold_char) = *(yy_c_buf_p); \
+ *(yy_c_buf_p) = '\0'; \
+ pcap_leng = yyless_macro_arg; \
+ } \
+ while ( 0 )
+
+/* Accessor methods (get/set functions) to struct members. */
+
+/** Get the current line number.
+ *
+ */
+int pcap_get_lineno (void)
+{
+
+ return pcap_lineno;
+}
+
+/** Get the input stream.
+ *
+ */
+FILE *pcap_get_in (void)
+{
+ return pcap_in;
+}
+
+/** Get the output stream.
+ *
+ */
+FILE *pcap_get_out (void)
+{
+ return pcap_out;
+}
+
+/** Get the length of the current token.
+ *
+ */
+int pcap_get_leng (void)
+{
+ return pcap_leng;
+}
+
+/** Get the current token.
+ *
+ */
+
+char *pcap_get_text (void)
+{
+ return pcap_text;
+}
+
+/** Set the current line number.
+ * @param line_number
+ *
+ */
+void pcap_set_lineno (int line_number )
+{
+
+ pcap_lineno = line_number;
+}
+
+/** Set the input stream. This does not discard the current
+ * input buffer.
+ * @param in_str A readable stream.
+ *
+ * @see pcap__switch_to_buffer
+ */
+void pcap_set_in (FILE * in_str )
+{
+ pcap_in = in_str ;
+}
+
+void pcap_set_out (FILE * out_str )
+{
+ pcap_out = out_str ;
+}
+
+int pcap_get_debug (void)
+{
+ return pcap__flex_debug;
+}
+
+void pcap_set_debug (int bdebug )
+{
+ pcap__flex_debug = bdebug ;
+}
+
+static int yy_init_globals (void)
+{
+ /* Initialization is the same as for the non-reentrant scanner.
+ * This function is called from pcap_lex_destroy(), so don't allocate here.
+ */
+
+ (yy_buffer_stack) = 0;
+ (yy_buffer_stack_top) = 0;
+ (yy_buffer_stack_max) = 0;
+ (yy_c_buf_p) = (char *) 0;
+ (yy_init) = 0;
+ (yy_start) = 0;
+
+/* Defined in main.c */
+#ifdef YY_STDINIT
+ pcap_in = stdin;
+ pcap_out = stdout;
+#else
+ pcap_in = (FILE *) 0;
+ pcap_out = (FILE *) 0;
+#endif
+
+ /* For future reference: Set errno on error, since we are called by
+ * pcap_lex_init()
+ */
+ return 0;
+}
+
+/* pcap_lex_destroy is for both reentrant and non-reentrant scanners. */
+int pcap_lex_destroy (void)
+{
+
+ /* Pop the buffer stack, destroying each element. */
+ while(YY_CURRENT_BUFFER){
+ pcap__delete_buffer(YY_CURRENT_BUFFER );
+ YY_CURRENT_BUFFER_LVALUE = NULL;
+ pcap_pop_buffer_state();
+ }
+
+ /* Destroy the stack itself. */
+ pcap_free((yy_buffer_stack) );
+ (yy_buffer_stack) = NULL;
+
+ /* Reset the globals. This is important in a non-reentrant scanner so the next time
+ * pcap_lex() is called, initialization will occur. */
+ yy_init_globals( );
+
+ return 0;
+}
+
+/*
+ * Internal utility routines.
+ */
+
+#ifndef yytext_ptr
+static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+{
+ register int i;
+ for ( i = 0; i < n; ++i )
+ s1[i] = s2[i];
+}
+#endif
+
+#ifdef YY_NEED_STRLEN
+static int yy_flex_strlen (yyconst char * s )
+{
+ register int n;
+ for ( n = 0; s[n]; ++n )
+ ;
+
+ return n;
+}
+#endif
+
+void *pcap_alloc (yy_size_t size )
+{
+ return (void *) malloc( size );
+}
+
+void *pcap_realloc (void * ptr, yy_size_t size )
+{
+ /* The cast to (char *) in the following accommodates both
+ * implementations that use char* generic pointers, and those
+ * that use void* generic pointers. It works with the latter
+ * because both ANSI C and C++ allow castless assignment from
+ * any pointer type to void*, and deal with argument conversions
+ * as though doing an assignment.
+ */
+ return (void *) realloc( (char *) ptr, size );
+}
+
+void pcap_free (void * ptr )
+{
+ free( (char *) ptr ); /* see pcap_realloc() for (char *) cast */
+}
+
+#define YYTABLES_NAME "yytables"
+
+#line 146 "scanner.l"
+
+
+void
+lex_init(buf)
+ char *buf;
+{
+ in_buffer = buf;
+}
+
+/*
+ * Also define a pcap_wrap. Note that if we're using flex, it will
+ * define a macro to map this identifier to pcap_wrap.
+ */
+int
+pcap_wrap()
+{
+ return 1;
+}
+
+/* Hex digit to integer. */
+static inline int
+xdtoi(c)
+ register int c;
+{
+ if (isdigit(c))
+ return c - '0';
+ else if (islower(c))
+ return c - 'a' + 10;
+ else
+ return c - 'A' + 10;
+}
+
+/*
+ * Convert string to integer. Just like atoi(), but checks for
+ * preceding 0x or 0 and uses hex or octal instead of decimal.
+ */
+static int
+stoi(s)
+ char *s;
+{
+ int base = 10;
+ int n = 0;
+
+ if (*s == '0') {
+ if (s[1] == 'x' || s[1] == 'X') {
+ s += 2;
+ base = 16;
+ }
+ else {
+ base = 8;
+ s += 1;
+ }
+ }
+ while (*s)
+ n = n * base + xdtoi(*s++);
+
+ return n;
+}
+
+
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/scanner.l b/package/etrax-tools/src/e100boot/libpcap-0.4/scanner.l
new file mode 100644
index 000000000..be435e8d3
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/scanner.l
@@ -0,0 +1,203 @@
+%{
+/*
+ * Copyright (c) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997
+ * The Regents of the University of California. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that: (1) source code distributions
+ * retain the above copyright notice and this paragraph in its entirety, (2)
+ * distributions including binary code include the above copyright notice and
+ * this paragraph in its entirety in the documentation or other materials
+ * provided with the distribution, and (3) all advertising materials mentioning
+ * features or use of this software display the following acknowledgement:
+ * ``This product includes software developed by the University of California,
+ * Lawrence Berkeley Laboratory and its contributors.'' Neither the name of
+ * the University nor the names of its contributors may be used to endorse
+ * or promote products derived from this software without specific prior
+ * written permission.
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+#ifndef lint
+static const char rcsid[] =
+ "@(#) $Header: /usr/local/cvs/linux/tools/build/e100boot/libpcap-0.4/scanner.l,v 1.1 1999/08/26 10:05:27 johana Exp $ (LBL)";
+#endif
+
+#include <sys/types.h>
+#include <sys/time.h>
+
+#include <ctype.h>
+#include <unistd.h>
+
+#include "pcap-int.h"
+
+#include "gencode.h"
+#include <pcap-namedb.h>
+#include "tokdefs.h"
+
+#include "gnuc.h"
+#ifdef HAVE_OS_PROTO_H
+#include "os-proto.h"
+#endif
+
+static int stoi(char *);
+static inline int xdtoi(int);
+
+#ifdef FLEX_SCANNER
+#define YY_NO_UNPUT
+#undef YY_INPUT
+#define YY_INPUT(buf, result, max)\
+ {\
+ char *src = in_buffer;\
+ int i;\
+\
+ if (*src == 0)\
+ result = YY_NULL;\
+ else {\
+ for (i = 0; *src && i < max; ++i)\
+ buf[i] = *src++;\
+ in_buffer += i;\
+ result = i;\
+ }\
+ }
+#else
+#undef getc
+#define getc(fp) (*in_buffer == 0 ? EOF : *in_buffer++)
+#endif
+
+#define yylval pcap_lval
+extern YYSTYPE yylval;
+
+static char *in_buffer;
+
+%}
+
+N ([0-9]+|(0X|0x)[0-9A-Fa-f]+)
+B ([0-9A-Fa-f][0-9A-Fa-f]?)
+
+%a 3000
+
+%%
+dst return DST;
+src return SRC;
+
+link|ether|ppp|slip return LINK;
+fddi return LINK;
+arp return ARP;
+rarp return RARP;
+ip return IP;
+tcp return TCP;
+udp return UDP;
+icmp return ICMP;
+igmp return IGMP;
+igrp return IGRP;
+
+atalk return ATALK;
+decnet return DECNET;
+lat return LAT;
+sca return SCA;
+moprc return MOPRC;
+mopdl return MOPDL;
+
+host return HOST;
+net return NET;
+mask return MASK;
+port return PORT;
+proto return PROTO;
+
+gateway return GATEWAY;
+
+less return LESS;
+greater return GREATER;
+byte return BYTE;
+broadcast return TK_BROADCAST;
+multicast return TK_MULTICAST;
+
+and|"&&" return AND;
+or|"||" return OR;
+not return '!';
+
+len|length return LEN;
+inbound return INBOUND;
+outbound return OUTBOUND;
+
+[ \n\t] ;
+[+\-*/:\[\]!<>()&|=] return yytext[0];
+">=" return GEQ;
+"<=" return LEQ;
+"!=" return NEQ;
+"==" return '=';
+"<<" return LSH;
+">>" return RSH;
+{N} { yylval.i = stoi((char *)yytext); return NUM; }
+({N}\.{N})|({N}\.{N}\.{N})|({N}\.{N}\.{N}\.{N}) {
+ yylval.s = sdup((char *)yytext); return HID; }
+{B}:{B}:{B}:{B}:{B}:{B} { yylval.e = pcap_ether_aton((char *)yytext);
+ return EID; }
+{B}:+({B}:+)+ { bpf_error("bogus ethernet address %s", yytext); }
+[A-Za-z0-9][-_.A-Za-z0-9]*[.A-Za-z0-9] {
+ yylval.s = sdup((char *)yytext); return ID; }
+"\\"[^ !()\n\t]+ { yylval.s = sdup((char *)yytext + 1); return ID; }
+[^ \[\]\t\n\-_.A-Za-z0-9!<>()&|=]+i {
+ bpf_error("illegal token: %s\n", yytext); }
+. { bpf_error("illegal char '%c'", *yytext); }
+%%
+void
+lex_init(buf)
+ char *buf;
+{
+ in_buffer = buf;
+}
+
+/*
+ * Also define a yywrap. Note that if we're using flex, it will
+ * define a macro to map this identifier to pcap_wrap.
+ */
+int
+yywrap()
+{
+ return 1;
+}
+
+/* Hex digit to integer. */
+static inline int
+xdtoi(c)
+ register int c;
+{
+ if (isdigit(c))
+ return c - '0';
+ else if (islower(c))
+ return c - 'a' + 10;
+ else
+ return c - 'A' + 10;
+}
+
+/*
+ * Convert string to integer. Just like atoi(), but checks for
+ * preceding 0x or 0 and uses hex or octal instead of decimal.
+ */
+static int
+stoi(s)
+ char *s;
+{
+ int base = 10;
+ int n = 0;
+
+ if (*s == '0') {
+ if (s[1] == 'x' || s[1] == 'X') {
+ s += 2;
+ base = 16;
+ }
+ else {
+ base = 8;
+ s += 1;
+ }
+ }
+ while (*s)
+ n = n * base + xdtoi(*s++);
+
+ return n;
+}
+
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/tokdefs.h b/package/etrax-tools/src/e100boot/libpcap-0.4/tokdefs.h
new file mode 100644
index 000000000..6b78a7d7d
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/tokdefs.h
@@ -0,0 +1,160 @@
+/* A Bison parser, made by GNU Bison 2.3. */
+
+/* Skeleton interface for Bison's Yacc-like parsers in C
+
+ Copyright (C) 1984, 1989, 1990, 2000, 2001, 2002, 2003, 2004, 2005, 2006
+ Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ Boston, MA 02110-1301, USA. */
+
+/* As a special exception, you may create a larger work that contains
+ part or all of the Bison parser skeleton and distribute that work
+ under terms of your choice, so long as that work isn't itself a
+ parser generator using the skeleton or a modified version thereof
+ as a parser skeleton. Alternatively, if you modify or redistribute
+ the parser skeleton itself, you may (at your option) remove this
+ special exception, which will cause the skeleton and the resulting
+ Bison output files to be licensed under the GNU General Public
+ License without this special exception.
+
+ This special exception was added by the Free Software Foundation in
+ version 2.2 of Bison. */
+
+/* Tokens. */
+#ifndef YYTOKENTYPE
+# define YYTOKENTYPE
+ /* Put the tokens into the symbol table, so that GDB and other debuggers
+ know about them. */
+ enum yytokentype {
+ DST = 258,
+ SRC = 259,
+ HOST = 260,
+ GATEWAY = 261,
+ NET = 262,
+ MASK = 263,
+ PORT = 264,
+ LESS = 265,
+ GREATER = 266,
+ PROTO = 267,
+ BYTE = 268,
+ ARP = 269,
+ RARP = 270,
+ IP = 271,
+ TCP = 272,
+ UDP = 273,
+ ICMP = 274,
+ IGMP = 275,
+ IGRP = 276,
+ ATALK = 277,
+ DECNET = 278,
+ LAT = 279,
+ SCA = 280,
+ MOPRC = 281,
+ MOPDL = 282,
+ TK_BROADCAST = 283,
+ TK_MULTICAST = 284,
+ NUM = 285,
+ INBOUND = 286,
+ OUTBOUND = 287,
+ LINK = 288,
+ GEQ = 289,
+ LEQ = 290,
+ NEQ = 291,
+ ID = 292,
+ EID = 293,
+ HID = 294,
+ LSH = 295,
+ RSH = 296,
+ LEN = 297,
+ AND = 298,
+ OR = 299,
+ UMINUS = 300
+ };
+#endif
+/* Tokens. */
+#define DST 258
+#define SRC 259
+#define HOST 260
+#define GATEWAY 261
+#define NET 262
+#define MASK 263
+#define PORT 264
+#define LESS 265
+#define GREATER 266
+#define PROTO 267
+#define BYTE 268
+#define ARP 269
+#define RARP 270
+#define IP 271
+#define TCP 272
+#define UDP 273
+#define ICMP 274
+#define IGMP 275
+#define IGRP 276
+#define ATALK 277
+#define DECNET 278
+#define LAT 279
+#define SCA 280
+#define MOPRC 281
+#define MOPDL 282
+#define TK_BROADCAST 283
+#define TK_MULTICAST 284
+#define NUM 285
+#define INBOUND 286
+#define OUTBOUND 287
+#define LINK 288
+#define GEQ 289
+#define LEQ 290
+#define NEQ 291
+#define ID 292
+#define EID 293
+#define HID 294
+#define LSH 295
+#define RSH 296
+#define LEN 297
+#define AND 298
+#define OR 299
+#define UMINUS 300
+
+
+
+
+#if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED
+typedef union YYSTYPE
+#line 82 "grammar.y"
+{
+ int i;
+ bpf_u_int32 h;
+ u_char *e;
+ char *s;
+ struct stmt *stmt;
+ struct arth *a;
+ struct {
+ struct qual q;
+ struct block *b;
+ } blk;
+ struct block *rblk;
+}
+/* Line 1489 of yacc.c. */
+#line 153 "y.tab.h"
+ YYSTYPE;
+# define yystype YYSTYPE /* obsolescent; will be withdrawn */
+# define YYSTYPE_IS_DECLARED 1
+# define YYSTYPE_IS_TRIVIAL 1
+#endif
+
+extern YYSTYPE pcap_lval;
+
diff --git a/package/etrax-tools/src/e100boot/libpcap-0.4/version.c b/package/etrax-tools/src/e100boot/libpcap-0.4/version.c
new file mode 100644
index 000000000..7fe9a8ef6
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/libpcap-0.4/version.c
@@ -0,0 +1 @@
+char pcap_version[] = "0.4";
diff --git a/package/etrax-tools/src/e100boot/sbl/Makefile b/package/etrax-tools/src/e100boot/sbl/Makefile
new file mode 100644
index 000000000..ffb6e9fb1
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/Makefile
@@ -0,0 +1,77 @@
+# Generated automatically from Makefile.in by configure.
+#
+# Makefile for e100boot, sbl side.
+#
+# $Id: Makefile.in,v 1.21 2003/11/21 11:38:30 pkj Exp $
+#
+
+VPATH := .:../cbl
+
+CC = gcc
+
+AXIS_USABLE_LIBS = UCLIBC GLIBC
+-include $(AXIS_TOP_DIR)/tools/build/Rules.axis
+
+CFLAGS += -I. -I../cbl/src -g -O2 -I../libpcap-0.4/ -I../libpcap-0.4/bpf/ -Wall -Wmissing-prototypes -Wno-unused
+LDFLAGS =
+LDLIBS = -L../libpcap-0.4/
+LDLIBS =
+LIBPCAP = ../libpcap-0.4/libpcap.a
+
+IMAGES := ../cbl/net/net.ima ../cbl/net_noleds/net_noleds.ima \
+ ../cbl/ser/ser.ima ../cbl/ser_noleds/ser_noleds.ima
+
+AUTOSRCS := $(addsuffix .c, $(subst .ima,_ima,$(notdir $(IMAGES))))
+
+OBJS := common.o network.o serial.o
+DEPS := $(addprefix deps/, $(subst .o,.d,$(OBJS)))
+
+STRIP ?= strip
+
+all: conf.h e100boot e100boot.stripped
+
+depend: $(DEPS)
+
+Makefile: Makefile.in
+ @echo -e "\n### New Makefile.in detected, regenerating Makefile..."
+ ./configure
+
+e100boot: common.o boot_images.o serial.o network.o $(LIBPCAP)
+ @echo -e '\n### Finally... Compiling e100boot.'
+ $(CC) $(LDFLAGS) $^ $(LDLIBS) -o $@
+
+e100boot.stripped: e100boot
+ cp $< $@
+ $(STRIP) --strip-unneeded $@
+
+boot_images.o: boot_images.c boot_images.h $(AUTOSRCS)
+ $(CC) -c $(CFLAGS) $< -o $@
+
+conf.h:
+ ./configure
+
+reconf:
+ ./configure --cache=/dev/null
+
+clean:
+ rm -rf e100boot Makefile conf.h config.log config.cache config.status deps *.ima *.o *_ima.c* *~
+
+$(IMAGES):
+ @echo -e '\n### Making cbl boot images (*.ima)...'
+ $(MAKE) -C ../cbl
+
+ifneq ($(MAKECMDGOALS),clean)
+-include $(DEPS)
+endif
+
+deps/%.d: %.c
+ @[ -d deps ] || mkdir deps
+ $(CC) -M $(CFLAGS) $< > $@
+
+deps/%.d: %.S
+ @[ -d deps ] || mkdir deps
+ $(CC) -M $(CFLAGS) $< > $@
+
+%_ima.c: %.ima
+ @echo -e "### Creating $@ from image $<"
+ @./cconv $*_ima < $< > $@
diff --git a/package/etrax-tools/src/e100boot/sbl/Makefile.in b/package/etrax-tools/src/e100boot/sbl/Makefile.in
new file mode 100644
index 000000000..bdefd7151
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/Makefile.in
@@ -0,0 +1,76 @@
+#
+# Makefile for e100boot, sbl side.
+#
+# $Id: Makefile.in,v 1.21 2003/11/21 11:38:30 pkj Exp $
+#
+
+VPATH := .:../cbl
+
+CC = @CC@
+
+AXIS_USABLE_LIBS = UCLIBC GLIBC
+-include $(AXIS_TOP_DIR)/tools/build/Rules.axis
+
+CFLAGS += -I. -I../cbl/src @CFLAGS@ -I../libpcap-0.4/ -I../libpcap-0.4/bpf/ -Wall -Wmissing-prototypes -Wno-unused
+LDFLAGS =
+LDLIBS = -L../libpcap-0.4/ @LIBS@
+LDLIBS =
+LIBPCAP = ../libpcap-0.4/libpcap.a
+
+IMAGES := ../cbl/net/net.ima ../cbl/net_noleds/net_noleds.ima \
+ ../cbl/ser/ser.ima ../cbl/ser_noleds/ser_noleds.ima
+
+AUTOSRCS := $(addsuffix .c, $(subst .ima,_ima,$(notdir $(IMAGES))))
+
+OBJS := common.o network.o serial.o
+DEPS := $(addprefix deps/, $(subst .o,.d,$(OBJS)))
+
+STRIP ?= strip
+
+all: conf.h e100boot e100boot.stripped
+
+depend: $(DEPS)
+
+Makefile: Makefile.in
+ @echo -e "\n### New Makefile.in detected, regenerating Makefile..."
+ ./configure
+
+e100boot: common.o boot_images.o serial.o network.o $(LIBPCAP)
+ @echo -e '\n### Finally... Compiling e100boot.'
+ $(CC) $(LDFLAGS) $^ $(LDLIBS) -o $@
+
+e100boot.stripped: e100boot
+ cp $< $@
+ $(STRIP) --strip-unneeded $@
+
+boot_images.o: boot_images.c boot_images.h $(AUTOSRCS)
+ $(CC) -c $(CFLAGS) $< -o $@
+
+conf.h:
+ ./configure
+
+reconf:
+ ./configure --cache=/dev/null
+
+clean:
+ rm -rf e100boot Makefile conf.h config.log config.cache config.status deps *.ima *.o *_ima.c* *~
+
+$(IMAGES):
+ @echo -e '\n### Making cbl boot images (*.ima)...'
+ $(MAKE) -C ../cbl
+
+ifneq ($(MAKECMDGOALS),clean)
+-include $(DEPS)
+endif
+
+deps/%.d: %.c
+ @[ -d deps ] || mkdir deps
+ $(CC) -M $(CFLAGS) $< > $@
+
+deps/%.d: %.S
+ @[ -d deps ] || mkdir deps
+ $(CC) -M $(CFLAGS) $< > $@
+
+%_ima.c: %.ima
+ @echo -e "### Creating $@ from image $<"
+ @./cconv $*_ima < $< > $@
diff --git a/package/etrax-tools/src/e100boot/sbl/boot_images.c b/package/etrax-tools/src/e100boot/sbl/boot_images.c
new file mode 100644
index 000000000..3aabdf06d
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/boot_images.c
@@ -0,0 +1,35 @@
+/* boot_images.c - Collection of the different boot images
+ * Johan Adolfsson Axis Communications AB
+ * $Id: boot_images.c,v 1.2 2002/07/01 14:37:51 pkj Exp $
+ */
+
+#include <stdio.h>
+#include "boot_images.h"
+
+/* We include the C files here to the size etc. easy */
+#include "net_ima.c"
+#include "ser_ima.c"
+#include "net_noleds_ima.c"
+#include "ser_noleds_ima.c"
+
+struct boot_image_info_type boot_image_info[] =
+{
+ { INTERNAL_NW, net_ima, sizeof net_ima, "Network boot (default)"},
+ { INTERNAL_SER, ser_ima, sizeof ser_ima, "Serial boot"},
+ { INTERNAL_SER_NOLEDS, ser_noleds_ima, sizeof ser_noleds_ima, "Serial boot, no leds"},
+ { INTERNAL_NW_NOLEDS, net_noleds_ima, sizeof net_noleds_ima, "Network boot, no leds"},
+
+ { "DBGNONE", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+ { "DBG0", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+ { "DBG1", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+ { "DBG2", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+ { "DBG3", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+
+ { "DBGNONE_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+ { "DBG0_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+ { "DBG1_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+ { "DBG2_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+ { "DBG3_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+
+ { NULL, NULL, 0, NULL } /* End of array */
+};
diff --git a/package/etrax-tools/src/e100boot/sbl/boot_images.h b/package/etrax-tools/src/e100boot/sbl/boot_images.h
new file mode 100644
index 000000000..cd7a1ae48
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/boot_images.h
@@ -0,0 +1,20 @@
+/* boot_images.h - Collection of the different boot images
+ * Johan Adolfsson Axis Communications AB
+ * $Id: boot_images.h,v 1.2 2002/07/01 14:37:51 pkj Exp $
+ */
+
+#define INTERNAL_SER "INTERNAL_SER"
+#define INTERNAL_NW "INTERNAL_NW"
+#define INTERNAL_NW_NOLEDS "INTERNAL_NW_NOLEDS"
+#define INTERNAL_SER_NOLEDS "INTERNAL_SER_NOLEDS"
+
+typedef struct boot_image_info_type
+{
+ const char *name;
+ const char *ptr;
+ unsigned long len;
+ const char *info;
+} boot_image_info_type;
+
+extern struct boot_image_info_type boot_image_info[];
+
diff --git a/package/etrax-tools/src/e100boot/sbl/cconv b/package/etrax-tools/src/e100boot/sbl/cconv
new file mode 100755
index 000000000..ce5ab3d70
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/cconv
@@ -0,0 +1,158 @@
+#!/usr/bin/perl
+#!
+#! FILE NAME : cconv
+#!
+#! PARAMETERS : Name of C program array variable.
+#!
+#! DESCRIPTION: Converts bytes of a binary file to C source code containing
+#! char array initialized with the binary file data.
+#!
+#! SUBROUTINES:
+#!
+#!---------------------------------------------------------------------------
+#! HISTORY
+#!
+#! DATE NAME CHANGES
+#! ---- ---- -------
+#! Dec 15 1997 Sven Ekstrom Initial version. Rewritten to Perl from C.
+#! Dec 16 1997 Sven Ekstrom Fixed bug that generated truncated result.
+#!
+#!---------------------------------------------------------------------------
+#!
+#! (C) Copyright 1997, Axis Communications AB, LUND, SWEDEN
+#!
+#!***************************************************************************
+# @(#) cconv 1.2 12/16/97
+
+#********************** CONSTANT SECTION ************************************
+
+$MyName = 'cconv';
+
+#
+# Number of bytes per line in the result.
+#
+$LineLength = 8;
+
+#********************** MAIN PROGRAM SECTION ********************************
+
+#
+# Make sure the command line contains the name of a C array.
+#
+if (scalar @ARGV != 1 || $ARGV[0] =~ /^-/)
+{
+ die "$MyName: Usage:\n",
+ "\n",
+ " Syntax\n",
+ " $MyName <name of C char array>\n",
+ "\n",
+ " <name of C char array> : This is the name of the char array where\n",
+ " the result is placed.\n",
+ "\n",
+ " Description\n",
+ "\n",
+ " Reads input from STDIN as binary data. Each byte of input data is\n",
+ " converted to C char data in hexadecimal form. The whole file read\n",
+ " from STDIN is converted and the result, C source code definition of\n",
+ " a char array, is printed on STDOUT.\n",
+ "\n";
+}
+
+#
+# Start with the name and version of this program and the name of the array.
+#
+print "\n",
+ "/* $MyName 1.2 12/16/97, Copyright (C) 1997, Axis Communications AB */\n",
+ "\n",
+ "const char $ARGV[0]\[\] =\n",
+ "{";
+
+#
+# Read all bytes from STDIN, convert them to char data and print them on
+# STDOUT.
+#
+$CurrentOffset = 0;
+while (!eof(STDIN))
+{
+ $Byte = ord(getc);
+
+ if ($CurrentOffset % $LineLength == 0)
+ {
+ #
+ # Start of a new line.
+ #
+ if ($CurrentOffset != 0)
+ {
+ #
+ # This is not the first byte.
+ #
+ print ",";
+ }
+ #
+ # The new line is indented by 2 spaces.
+ #
+ print "\n",
+ " ";
+ }
+ else
+ {
+ #
+ # Continuing an old line.
+ #
+ print ", ";
+ }
+
+ #
+ # Print the value of the byte as hex char data.
+ #
+ printf("'\\x%02x'", $Byte);
+
+ $CurrentOffset++;
+}
+
+if ($CurrentOffset == 0)
+{
+ #
+ # Initialize the array with a single byte of zero.
+ #
+ print "\n '\\x00'";
+}
+
+#
+# End with the closing bracket and semicolon.
+#
+print "\n",
+ "};\n";
+
+exit 0;
+
+
+#********************** SUBROUTINE DEFINITION SECTION ***********************
+
+#****************************************************************************
+#*
+#* SUBROUTINE :
+#*
+#* PARAMETERS :
+#*
+#* RETURNS :
+#*
+#* SIDE EFFECTS:
+#*
+#* DESCRIPTION :
+#*
+#*---------------------------------------------------------------------------
+#* HISTORY
+#*
+#* DATE NAME CHANGES
+#* ---- ---- -------
+#* May 05, 1995 Sven Ekstrom Initial version
+#*
+#****************************************************************************
+
+#sub NN
+#{
+# local() = @_;
+#
+#}
+
+#************************ END OF FILE cconv *********************************
diff --git a/package/etrax-tools/src/e100boot/sbl/common.c b/package/etrax-tools/src/e100boot/sbl/common.c
new file mode 100644
index 000000000..e0fe6ce29
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/common.c
@@ -0,0 +1,1677 @@
+/*!***************************************************************************
+*!
+*! FILE NAME : common.c
+*!
+*! DESCRIPTION: Common functions for e100boot.
+*!
+*! ---------------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! ??? ? ???? Ronny Ranerup Initial version
+*! ---------------------------------------------------------------------------
+*! (C) Copyright 1999-2006 Axis Communications AB, LUND, SWEDEN
+*!***************************************************************************/
+/* $Id: common.c,v 1.13 2006/02/08 14:00:25 pkj Exp $ */
+
+/************************** Version **************************************/
+
+char version[] = "Time-stamp: $Id: common.c,v 1.13 2006/02/08 14:00:25 pkj Exp $";
+
+/************************** Include files ********************************/
+
+#include <byteswap.h>
+
+#include <conf.h>
+#include <e100boot.h>
+#include <pcap.h>
+#include "boot_images.h"
+#include <reg_des.h>
+#include <sv_addr_ag.h>
+#include <common.h>
+
+#include <serial.h>
+#include <network.h>
+
+/************************** Constants and macros *************************/
+
+#define BOOT_CMDS_FILE "BOOT_CMDS"
+
+/************************** Type definitions *****************************/
+
+struct label_t {
+ struct label_t *prev;
+ udword addr;
+ char *name;
+};
+
+/************************** Global variables *****************************/
+
+char needle[MAX_STRING_LEN] = "END"; /* search needle for --find */
+int needle_len = 3;
+
+int exitonfind = FALSE;
+
+int doing_flash = FALSE; /* Just a flag to see if we should
+ warn that it might take some
+ time. */
+
+int toFiles = FALSE; /* Dump all packets to files. */
+int cmdsOnly = FALSE; /* Just dump boot cmds to file. */
+int netBoot = TRUE; /* Do network boot? */
+int serBoot = FALSE; /* Do serial boot? */
+
+struct label_t *loop_label = NULL;
+struct label_t *label = NULL;
+
+struct packet_buf *first_packet = NULL;
+struct packet_buf *last_packet = NULL;
+
+struct packet_buf *boot_cmds_packet;
+
+int create_boot_loader = TRUE;
+
+/* We use the INTERNAL boot image as default */
+char boot_loader_file[MAX_STRING_LEN] = INTERNAL_NW;
+
+int noleds = FALSE; /* Use boot images that doesn't toggle leds? */
+
+struct boot_files_T *first_boot_file = NULL;
+struct boot_files_T *last_boot_file = NULL;
+
+unsigned int boot_cmds[SIZE_OF_BOOT_CMDS / sizeof(unsigned int)];
+int boot_cmds_cnt = 0;
+
+int svboot = FALSE;
+
+int quiet = 0;
+
+struct packet_header_T send_packet;
+struct packet_header_T *receive_packet;
+
+int seq_nr = 0;
+
+/* debug flags */
+int db1 = FALSE;
+int db2 = FALSE;
+int db3 = FALSE;
+int db4 = FALSE;
+
+char device[MAX_STRING_LEN] = "eth0";
+
+/************************** Function prototypes **************************/
+
+FILE *Fopen (const char *name, const char *mode);
+int main (int argc, const char *argv[]);
+int GetNumberOption (int *argNr, int argCount, const char *argVect[], unsigned int *ret, const char *option, int base);
+int GetStringOption (int *argNr, int argCount, const char *argVect[], char *ret, const char *option);
+int GetRegisterOption (int *argNr, int argCount, const char *argVect[], unsigned int *ret, const char *option, int base);
+struct boot_files_T* allocate_boot_file (struct boot_files_T *bf);
+struct packet_buf* CreateNewBootPacket (void);
+struct packet_buf* allocate_packet (struct packet_buf *p);
+void SigHandler (int sig);
+void CreateBootLoader (void);
+void FinishBootCmds (void);
+void ParseArgs (int argc, const char *argv[]);
+void PrintHelp (void);
+void CreateBootCmds (void);
+void handle_labels (void);
+void new_label (struct label_t **label, udword addr, const char *name);
+unsigned int swap_endian (unsigned int);
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: main
+*#
+*# PARAMETERS: Command line arguments.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+main(int argc, const char *argv[])
+{
+ ParseArgs(argc, argv);
+
+ if (cmdsOnly) {
+ /* We make this a special case to avoid messing up other code. */
+ CreateBootCmds();
+ FinishBootCmds();
+ SendToDevice(&boot_cmds_packet->data[SIZE_OF_HEADER],SIZE_OF_BOOT_CMDS);
+ exit(EXIT_SUCCESS);
+ }
+
+ if (netBoot && !toFiles) {
+ /* Do not bother with this if we just want to write the packets to
+ files. Means you do not have to be root to run --tofiles. */
+ net_init();
+ }
+ else if (serBoot) {
+ if (!SetupSerial()) {
+ exit(0);
+ }
+ }
+
+ CreateBootLoader();
+ CreateBootCmds();
+ FinishBootCmds();
+
+ printf("Starting boot...\n");
+ if (doing_flash) {
+ printf("We're doing a flash write, this may take up to a few minutes...\n");
+ }
+
+ if (toFiles) {
+ udword seq = 0;
+ struct packet_buf *p;
+
+ while((p = create_packet(seq++))) {
+ SendToDevice(p->data, p->size);
+ }
+
+ exit(EXIT_SUCCESS);
+ }
+
+ if (netBoot) {
+ NetBoot();
+ }
+ else if (serBoot) {
+ SerBoot();
+ }
+
+ printf("Done.\n");
+ return EXIT_SUCCESS;
+} /* main */
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: free_packet
+*#
+*# PARAMETERS: struct to free
+*#
+*# DESCRIPTION: Frees struct and data in struct.
+*#
+*# RETURNS: Pointer to next struct.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000 02 07 ronny Initial version
+*#
+*#***************************************************************************/
+
+struct packet_buf*
+free_packet(struct packet_buf *p)
+{
+ struct packet_buf *next_p;
+
+ next_p = p->next;
+ free(p->data);
+ free(p);
+ return(next_p);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: create_packet
+*#
+*# PARAMETERS: Sequence number of desired packet.
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000 06 28 ronny Initial version
+*#
+*#***************************************************************************/
+
+struct packet_buf*
+create_packet(udword seq)
+{
+ struct packet_buf *p = first_packet;
+ /* Should check last first? */
+
+ if (db4) printf("> create_packet seq %d\n", seq);
+
+ while (p) {
+ if (p->seq == seq) {
+ return(p);
+ }
+ p = p->next;
+ }
+
+ return(CreateNewBootPacket());
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: find_string
+*#
+*# PARAMETERS: New string to search.
+*#
+*# DESCRIPTION: Searches a number of strings for needle[], including strings
+*# overlapping between different calls.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 020502 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+find_string(char *str)
+{
+ static int matched = 0;
+ int hs[MAX_STRING_LEN];
+ static int cur_hs = 0;
+ static int hs_len = 0;
+ static int last_hs = 0;
+
+ static int cur_needle = 0;
+
+ if (!needle[0]) {
+ return;
+ }
+ // printf("# adding >%s<\n", str);
+
+ {
+ int c = 0;
+ int s = 0;
+
+ while((c = str[s])) {
+ // printf("\n# cur_hs %d, hs_len %d\n", cur_hs, hs_len);
+ {
+ int i;
+
+ for(i = 0; i != hs_len; i++) {
+ // printf("hs[%d] = %d(%c)\n", i, (int)hs[i], hs[i] < 32 ? 'X' : hs[i]);
+ }
+ }
+
+ if (cur_hs == hs_len) {
+ // printf("adding char %d(%c) at hs[%d]\n", (int)c, c < 32 ? 'X' : c, hs_len);
+ hs[hs_len] = c;
+ hs_len++;
+ s++;
+ }
+
+ // printf("testing %d at cur_hs %d against %d at cur_needle %d\n",
+ // (int)hs[cur_hs], cur_hs, (int)needle[cur_needle], cur_needle);
+
+ if (hs[cur_hs] == needle[cur_needle]) {
+ if (cur_needle+1 == needle_len) {
+ int exitcode = EXIT_SUCCESS;
+
+ // printf("\nFound needle from --find option.\n");
+ if (exitonfind) {
+ int ret;
+ // printf("scanf (s=%d)'%s'\n", s, &str[s+1]);
+ ret = sscanf(&str[s+1], "%i", &exitcode);
+ // printf("ret %d, '%s'\n", ret, &str[s+1]);
+ }
+ printf("Exiting with code %d\n", exitcode);
+ exit(exitcode);
+ }
+ cur_needle++;
+ cur_hs++;
+ }
+ else {
+ // printf("no match, shifting hs.\n");
+ {
+ int i;
+ for(i=0; i!= hs_len-1; i++) {
+ hs[i] = hs[i+1];
+ }
+ }
+ hs_len--;
+ cur_needle = 0;
+ cur_hs = 0;
+ }
+ }
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: Fopen
+*#
+*# PARAMETERS: Name and mode, both strings.
+*#
+*# DESCRIPTION: Opens a file and returns its fd, or NULL.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+FILE *
+Fopen(const char *name, const char *mode)
+{
+ FILE *fd;
+
+ if (db2) printf(">>> Fopen '%s', mode '%s'\n", name, mode);
+
+#if defined(_WIN32)
+ fd = _fsopen(name, mode, _SH_DENYNO);
+#else
+ fd = fopen(name, mode);
+#endif
+
+ if (fd == NULL) {
+ printf("<<< Fopen failed on '%s', mode '%s'\n", name, mode);
+ return ((FILE*) NULL);
+ }
+
+ if (strncmp(mode, "a", 1) == 0) {
+ if (db3) printf("* Append mode, seeking to end.\n");
+ fseek(fd, 0L, SEEK_SET);
+ }
+
+ if (db2) printf("<<< Fopen: '%s'\n", name);
+
+ return(fd);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: ParseArgs
+*#
+*# PARAMETERS: Standard command line args.
+*#
+*# DESCRIPTION: Parses command line arguments.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+void
+ParseArgs (int argc, const char *argv[])
+{
+ int argi;
+ int i;
+ int printHelp = FALSE;
+ int exitCode = EXIT_SUCCESS;
+ char dbStr[MAX_STRING_LEN]; /* Debug option string. */
+ int number;
+ int argCount;
+ const char **argVect;
+ struct stat st;
+
+ if (db4) printf(">>> ParseArgs\n");
+ argCount = argc;
+ argVect = argv;
+
+ for (argi = 1; argi < argCount; argi++) {
+ if (db4) printf("argv[%d] = '%s'\n", argi, argVect[argi]);
+ if (strncmp(argVect[argi], "--from", 6) == 0) {
+ if (GetStringOption(&argi, argCount, argVect, host1, "--from") == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ else {
+ printf("Host: %s %s\n", host1, host2);
+ if (sscanf(host1, "%x-%x-%x-%x-%x-%x", &i, &i, &i, &i, &i, &i) == 6) {
+ printf("Ethernet address\n");
+ }
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--device", 8) == 0) {
+ if (GetStringOption(&argi, argCount, argVect, device, "--device") == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--network", 9) == 0) {
+ netBoot = TRUE;
+ serBoot = FALSE;
+ strcpy(device, "eth0");
+ strcpy(boot_loader_file, INTERNAL_NW);
+ }
+
+ else if (strncmp(argVect[argi], "--serial", 8) == 0) {
+ serBoot = TRUE;
+ netBoot = FALSE;
+ strcpy(device, "/dev/ttyS0");
+ strcpy(boot_loader_file, INTERNAL_SER);
+ }
+
+ else if (strncmp(argVect[argi], "--noleds", 8) == 0) {
+ noleds = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--images", 8) == 0) {
+ int i = 0;
+
+ printf("Internal images:\n");
+
+ while(boot_image_info[i].name) {
+ printf("'%s', %s, size %lu bytes.\n",
+ boot_image_info[i].name,
+ boot_image_info[i].info,
+ boot_image_info[i].len
+ );
+ i++;
+ }
+ exit(EXIT_SUCCESS);
+ }
+
+ else if (strncmp(argv[argi], "--baudrate", 10) == 0) {
+ if (GetNumberOption (&argi, argCount, argVect, &set_baudrate, "--baudrate", 10) == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--tofiles", 9) == 0) {
+ toFiles = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--cmdsonly", 10) == 0) {
+ cmdsOnly = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--to", 4) == 0) {
+ if ((GetStringOption(&argi, argCount, argVect, host2, "--to") == 0)) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ else {
+ printf("Host: %s %s\n", host1, host2);
+ both_addresses = TRUE;
+ if (sscanf(host2, "%x-%x-%x-%x-%x-%x", &i, &i, &i, &i, &i, &i) == 6) {
+ printf("Ethernet address\n");
+ }
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--printp", 8) == 0) {
+ pPacket = 1;
+ }
+
+ else if (strncmp(argVect[argi], "--printascii", 11) == 0) {
+ pPacket = 1;
+ printPacketType = ASCII;
+ }
+
+ else if (strncmp(argVect[argi], "--printudec", 11) == 0) {
+ pPacket = 1;
+ printPacketType = UDEC;
+ }
+
+ else if (strncmp(argVect[argi], "--printhex", 10) == 0) {
+ pPacket = 1;
+ printPacketType = HEX;
+ }
+
+ else if (strncmp(argVect[argi], "--bpl", 5) == 0) {
+ if (GetNumberOption(&argi, argCount, argVect, &p_packet_bpl, "--bpl", 10) == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--promisc", 11) == 0) {
+ promisc = 1;
+ }
+
+ else if (strncmp(argVect[argi], "--5400", 6) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb0000000;
+ boot_cmds[boot_cmds_cnt++] = 0x000095b6;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb0000008;
+ boot_cmds[boot_cmds_cnt++] = 0x0000e751;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb000000c;
+ boot_cmds[boot_cmds_cnt++] = 0x12604040;
+ }
+
+ else if (strncmp(argVect[argi], "--5600", 6) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb0000000;
+ boot_cmds[boot_cmds_cnt++] = 0x000095b6;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb0000008;
+ boot_cmds[boot_cmds_cnt++] = 0x00006751;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb000000c;
+ boot_cmds[boot_cmds_cnt++] = 0x12204040;
+ }
+
+ else if (strncmp(argVect[argi], "--testcardlx", 12) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x12604040;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_TIMING;
+ boot_cmds[boot_cmds_cnt++] = 0x0000e751;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_WAITSTATES;
+ boot_cmds[boot_cmds_cnt++] = 0x00b395b5;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_BUS_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x00000207;
+ }
+
+ else if (strncmp(argVect[argi], "--testcard", 10) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_WAITSTATES;
+ boot_cmds[boot_cmds_cnt++] = 0x000010b3;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_TIMING;
+ boot_cmds[boot_cmds_cnt++] = 0x00006543;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x12966060;
+ }
+
+ else if (strncmp(argVect[argi], "--devboard", 10) == 0) {
+ /* Printing on serial port will not work until PORT_PB is set... */
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_PORT_PB_SET;
+ boot_cmds[boot_cmds_cnt++] = 0x01001ef3;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_PORT_PA_SET;
+ boot_cmds[boot_cmds_cnt++] = 0x00001df0;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_WAITSTATES;
+ boot_cmds[boot_cmds_cnt++] = 0x000095a6;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x1a200040;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_TIMING;
+ boot_cmds[boot_cmds_cnt++] = 0x00005611;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_BUS_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x00000104;
+ }
+
+ else if (strncmp(argVect[argi], "--verify", 8) == 0) {
+ boot_cmds[boot_cmds_cnt++] = MEM_VERIFY;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--verify", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--verify", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--setreg", 8) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ if ((argVect[argi+1][0] >= 'A') && (argVect[argi+1][0] <= 'Z')) {
+ GetRegisterOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--setreg", 16);
+ }
+ else {
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--setreg", 16);
+ }
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--setreg", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--getreg", 8) == 0) {
+ boot_cmds[boot_cmds_cnt++] = GET_REGISTER;
+ if ((argVect[argi+1][0] >= 'A') && (argVect[argi+1][0] <= 'Z')) {
+ GetRegisterOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--getreg", 16);
+ }
+ else {
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--getreg", 16);
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--pause", 7) == 0) {
+ boot_cmds[boot_cmds_cnt++] = PAUSE_LOOP;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--pause", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--memtest", 9) == 0) {
+ boot_cmds[boot_cmds_cnt++] = MEM_TEST;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memtest", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memtest", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--loop", 6) == 0) {
+ char str[MAX_STRING_LEN];
+ boot_cmds[boot_cmds_cnt++] = LOOP;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--loop", 16);
+ GetStringOption(&argi, argCount, argVect, str, argVect[argi]);
+ new_label(&loop_label, boot_cmds_cnt+1, str);
+ boot_cmds_cnt++;
+ }
+
+ else if (strncmp(argVect[argi], "--label", 7) == 0) {
+ char str[MAX_STRING_LEN];
+ GetStringOption(&argi, argCount, argVect, str, "--label");
+ new_label(&label, boot_cmds_cnt, str);
+ }
+
+ else if (strncmp(argVect[argi], "--memdump", 9) == 0) {
+ boot_cmds[boot_cmds_cnt++] = MEM_DUMP;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memdump", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memdump", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--memclear", 10) == 0) {
+ boot_cmds[boot_cmds_cnt++] = MEM_CLEAR;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memclear", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memclear", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--flash", 7) == 0) {
+ boot_cmds[boot_cmds_cnt++] = FLASH;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--flash", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--flash", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--flash", 16);
+ doing_flash = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--jump", 6) == 0) {
+ boot_cmds[boot_cmds_cnt++] = JUMP;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--jump", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--file", 6) == 0) {
+ char str[MAX_STRING_LEN];
+ boot_cmds[boot_cmds_cnt++] = PACKET_INFO;
+ GetStringOption(&argi, argCount, argVect,
+ str, "--file"); /* file name */
+ GetNumberOption(&argi, argCount, argVect,
+ &boot_cmds[boot_cmds_cnt++], str, 16); /* address */
+ last_boot_file = allocate_boot_file(last_boot_file);
+ first_boot_file = first_boot_file ? first_boot_file : last_boot_file;
+ last_boot_file->fileName = malloc(strlen(str) + 1);
+ strcpy(last_boot_file->fileName, str);
+ last_boot_file->size_p = &boot_cmds[boot_cmds_cnt];
+ last_boot_file->size_sent = 0;
+ if (strncmp(str, "-", 1) != 0) {
+ if (stat(last_boot_file->fileName, &st) == -1) {
+ printf("Cannot get size of file '%s'. %s.\n",
+ last_boot_file->fileName, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ if (db2) printf("* size is %d 0x%8.8x\n",
+ (int)st.st_size, (unsigned int)st.st_size);
+ last_boot_file->size = st.st_size;
+ boot_cmds[boot_cmds_cnt++] = st.st_size;
+ }
+ else {
+ GetNumberOption(&argi, argCount, argVect,
+ &last_boot_file->size , str, 16); /* size */
+
+ boot_cmds[boot_cmds_cnt++] = last_boot_file->size;
+ printf("* size is %d 0x%8.8x\n", last_boot_file->size,
+ last_boot_file->size);
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--bootfile", 10) == 0) {
+ GetStringOption(&argi, argCount, argVect,
+ boot_loader_file, "--bootfile");
+ }
+
+ else if (strncmp(argVect[argi], "-d", 2) == 0) {
+ if (GetNumberOption (&argi, argCount, argVect, &number, "-d", 10) == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ else {
+ sprintf(dbStr, "%d", number);
+ for (i = 0; i != (int) strlen(dbStr); i++) {
+ switch (dbStr[i] - '0') {
+ case 1:
+ db1 = TRUE;
+ break;
+ case 2:
+ db2 = TRUE;
+ break;
+ case 3:
+ db3 = TRUE;
+ break;
+ case 4:
+ db4 = TRUE;
+ break;
+ default:
+ printf("ERROR! Debug level %d is not defined.\n", dbStr[i] - '0');
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ break;
+ }
+ }
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--find", 6) == 0) {
+ GetStringOption(&argi, argCount, argVect, needle, "--find");
+ /* convert control characters like /n to the real ascii valure */
+ {
+ int i;
+ int j = 0;
+ char c;
+ int esc = 0;
+
+ for (i = 0; (c = needle[i]); i++,j++) {
+// printf("c = %d, i %d, j %d\n", (int)c, i, j);
+ if (c == '\\') {
+// printf("esc\n");
+ esc = 1;
+ continue;
+ }
+ else if (esc) {
+ esc = 0;
+ switch(c) {
+ case 'r':
+ c = '\r';
+ break;
+
+ case 'n':
+ c = '\n';
+ break;
+
+ case '\\':
+ c = '\\';
+ break;
+
+ default:
+ printf("Uknown escape sequence '\\%c'\n", c);
+ exit(EXIT_FAILURE);
+ }
+ j--;
+ }
+ // printf("setting j %d to %d\n", j, (int)c);
+ needle[j] = c;
+ }
+ needle_len = j;
+ }
+
+ for (i = 0; needle[i]; i++) {
+ //printf("i = %d, c %d\n", i,(int)needle[i]);
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--exitonfind", 12) == 0) {
+ exitonfind = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--help", 6) == 0) {
+ printHelp = TRUE;
+ }
+
+ else {
+ printf("ERROR! Don't understand option '%s'\n", argVect[argi]);
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ }
+
+ if (printHelp == TRUE) {
+ PrintHelp();
+ exit(exitCode);
+ }
+
+ if (noleds) {
+ strcpy(&boot_loader_file[strlen(boot_loader_file)], "_NOLEDS");
+ }
+
+ handle_labels();
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: handle_labels
+*#
+*# PARAMETERS: global loop_label, label
+*#
+*# DESCRIPTION: Checks and matches labels from --loop and --label commands
+*# and inserts the resolved addresses into boot commands.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 20020204 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+handle_labels(void)
+{
+ struct label_t *ll = loop_label;
+ struct label_t *l = label;
+ struct label_t *last_l = l;
+
+ while(ll) {
+ int match = 0;
+
+ l = last_l;
+ while(l) {
+ match = 0;
+
+ if (l->name && ll->name && (strcmp(l->name, ll->name) == 0)) {
+ match = 1;
+ boot_cmds[ll->addr] = IO_BUF_START+(l->addr*4);
+ break;
+ }
+ l = l->prev;
+ }
+ if (!match) {
+ printf("Error. No label '%s' defined as needed by --loop command.\n", ll->name);
+ exit(EXIT_FAILURE);
+ }
+ ll = ll->prev;
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: new_label
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 20020201 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+new_label(struct label_t **label, udword addr, const char *name)
+{
+ struct label_t *new_p;
+
+ new_p = malloc(sizeof(struct label_t));
+
+ if (*label == NULL) { /* first one? */
+ *label = new_p;
+ new_p->prev = NULL;
+ }
+ else {
+ new_p->prev = *label;
+ }
+ *label = new_p;
+ new_p->addr = boot_cmds_cnt;
+ new_p->name = malloc(strlen(name));
+ strcpy(new_p->name, name);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetStringOption
+*#
+*# PARAMETERS: int *argNr : Returns next argc here.
+*# int argCount : Index of last argument.
+*# char *argVect[] : argv.
+*# char *ret : Copy string here.
+*# char *option : Name of the option.
+*#
+*# DESCRIPTION: Extracts a string option from argv, and updates argnr.
+*# Returns TRUE/FALSE and string in *ret.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*# 961203 ronny Handles filenames with spaces within 'file name'.
+*#
+*#***************************************************************************/
+
+int
+GetStringOption(int *argNr, int argCount, const char *argVect[], char *ret,
+ const char *option)
+{
+ int startChar = strlen(option);
+
+ *ret = '\0';
+
+ /* Are there any more chars after option? If not skip to next argv. */
+ if (strlen(argVect[*argNr]) <= (unsigned int)startChar) {
+ (*argNr)++;
+ startChar = 0;
+ }
+
+ /* Any args left? */
+ if (*argNr >= argCount) {
+ printf("ERROR! The option '%s' needs a string argument.\n", option);
+ PrintHelp();
+ exit(EXIT_FAILURE);
+ }
+
+ /* avoid stack overflow hacks */
+ if (strlen(&argVect[*argNr][startChar]) > MAX_STRING_LEN) {
+ printf("Argument '%s' longer than maximum allowable %d characters.\n",
+ &argVect[*argNr][startChar], MAX_STRING_LEN);
+ exit(EXIT_FAILURE);
+ }
+
+ strcpy(ret, &argVect[*argNr][startChar]);
+ if (db4) printf("<<< GetStringOption '%s'\n", ret);
+
+ return TRUE;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetNumberOption
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+GetNumberOption(int *argNr, int argCount, const char *argVect[],
+ unsigned int *ret, const char *option, int base)
+{
+ int startChar = 0;
+ int add_io_base = 0;
+
+ (*argNr)++;
+
+ if (*argNr >= argCount) {
+ printf("ERROR! The option '%s' needs a number argument.\n", option);
+ PrintHelp();
+ exit(EXIT_FAILURE);
+ }
+
+ if (argVect[*argNr][startChar] == '+') {
+ add_io_base = 1;
+ startChar++;
+ }
+
+ *ret = strtoul(&argVect[*argNr][startChar], NULL, base);
+
+ if (add_io_base) {
+ *ret += IO_BUF_START;
+ if (*ret < IO_BUF_START || *ret >= IO_BUF_END) {
+ printf("ERROR! '%s' is outside the IO buffer (option '%s').\n",
+ argVect[*argNr], option);
+ exit(EXIT_FAILURE);
+ }
+ }
+
+ if (db4) printf("<<< GetNumberOption %08x\r\n", *ret);
+
+ return TRUE;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetRegisterOption
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+GetRegisterOption(int *argNr, int argCount, const char *argVect[],
+ unsigned int *ret, const char *option, int base)
+{
+ int startChar = 0;
+
+ (*argNr)++;
+
+ if (*argNr >= argCount) {
+ printf("Error! The option '%s' needs a register name.\n", option);
+ PrintHelp();
+ exit(EXIT_FAILURE);
+ }
+
+ {
+ int r = 0;
+
+ while (reg_des[r].name) {
+ if (strcmp(reg_des[r].name, argVect[*argNr]) == 0) {
+ *ret = reg_des[r].addr;
+ return TRUE;
+ break;
+ }
+ r++;
+ }
+ }
+
+ printf("Error! Didn't find a register name matching '%s'.\n",
+ argVect[*argNr]);
+
+ exit(EXIT_FAILURE);
+
+ return FALSE;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: PrintHelp
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Prints help info.
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+PrintHelp(void)
+{
+ printf("e100boot version %s.\n", version);
+
+ printf("\ne100boot [--device devicename] [--file filename|- addr [size]]\n"
+ " [--flash ram-source flash-offset size]\n"
+ " [--pause iter]\n"
+ " [--memtest addr addr]\n"
+ " [--memclear addr addr] [--memdump addr addr]\n"
+ " [--setreg addr|regname val] [--getreg addr|regname]\n"
+ " [--verify addr val] [--label label] [--loop addr label]\n"
+ " [--5400] [--5600] [--testcard] [--devboard]\n"
+ " [--testcardlx] [--network] [--serial]\n"
+ " [--baudrate baudrate] [--bootfile file] [--jump addr]\n"
+ " [--tofiles] [--cmdsonly] [--images] [--noleds]\n"
+ " [--help]\n\n");
+
+ printf(" The commands sent to the cbl, and which are parsed by the cbl,\n"
+ " are stored at 0x%8.8x-0x%8.8x.\n\n", IO_BUF_START, IO_BUF_END);
+
+ printf(" See the man page for more details about e100boot.\n\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: CreateBootLoader
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Creates boot packets from boot file or internal loader.
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+void
+CreateBootLoader(void)
+{
+ struct stat st;
+ char *buf = NULL;
+ // int size_pos = 0x18;
+ // int addr_pos = 0x28;
+ struct packet_header_T *ph;
+ int packet_size;
+ int header_size;
+ int buf_cnt = 0;
+ int i;
+ udword sum = 0;
+
+ if (create_boot_loader) {
+ int image_nbr = 0;
+ int found = 0;
+ const struct boot_image_info_type *info;
+
+ if (db4) printf("> CreateBootLoader\n");
+
+ info = &boot_image_info[image_nbr];
+
+ /* Use internal boot loader? */
+ while (!found && info->name != NULL) {
+ if (strcmp(boot_loader_file, info->name) == 0) {
+ st.st_size = info->len;
+ buf = (char*) malloc(st.st_size);
+ memcpy(buf, info->ptr, st.st_size); /* unnecessary? */
+ found = TRUE;
+ printf("Using internal boot loader: %s - %s.\n",
+ info->name, info->info);
+ }
+ else {
+ image_nbr++;
+ info = &boot_image_info[image_nbr];
+ }
+ }
+
+ /* No internal? Load it from file instead. */
+ if (!found) {
+ FILE *fd;
+
+ /* We didn't find an internal match, load the boot file from disk. */
+ if ((fd = Fopen(boot_loader_file, "r")) == NULL) {
+ printf("Cannot open bootloader '%s'. %s.\n",
+ boot_loader_file, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ if (fstat(fileno(fd), &st) == -1) {
+ printf("Cannot get filestatus of bootloader '%s'. %s.\n",
+ boot_loader_file, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ buf = (char*) malloc(st.st_size);
+ // printf("CreateBootLoader: buf = (char*) malloc(st.st_size); 2\n");
+ if (read(fileno(fd), buf, st.st_size) != st.st_size) {
+ printf("Read fewer bytes than there should be in %s.\n",
+ boot_loader_file);
+ exit(EXIT_FAILURE);
+ }
+
+ fclose(fd);
+ }
+
+ /* Alright, got loader in buf[] and size in st. */
+ if (netBoot) {
+ /* The etrax code for all boot methods are linked to adress
+ 380000f0 but since network boot starts execution at 380000f4
+ we have two nops in the beginning of the code which we do not
+ transmit to etrax in the network case. The link adress
+ doesn't change though. */
+ buf += 4;
+ st.st_size -= 4;
+ packet_size = DATA_SIZE;
+ }
+ else {
+ packet_size = st.st_size;
+ }
+
+ /* Hack binary, insert size and address. */
+
+ /* Giovanni Varasano (24/06/2005) : bug
+ * It is not a good habit to make code endian dependent on the host
+ * processor where cross compilation happens. Intel is little endian and
+ * PowerPC is big endian, but the target (ETRAX) is always little endian.
+ * The use of swap_endian() solves the problem.
+ */
+
+#define SIZE_PATTERN 0x12345678
+#define ADDR_PATTERN 0x87654321
+#define SIZE_POS (netBoot ? 0x0c : 0x10)
+#define ADDR_POS (netBoot ? 0x10 : 0x14)
+
+ if (swap_endian(*(udword*)&buf[SIZE_POS]) != SIZE_PATTERN) {
+ printf("Bootloader corrupt. Should contain ret/nop (0x%8.8x) at 0x%x, but contains %x\n",
+ SIZE_PATTERN, SIZE_POS, *(udword*)&buf[SIZE_POS]);
+ exit(EXIT_FAILURE);
+ }
+
+ /* How much data to load except data in first packet. */
+
+ if (netBoot) {
+ *(udword*)(&buf[SIZE_POS]) = swap_endian(st.st_size - DATA_SIZE);
+ }
+ else {
+ *(udword*)(&buf[SIZE_POS]) = swap_endian(st.st_size - 784);
+ }
+
+ if (db3) printf("Inserting boot size 0x%x at 0x%x.\n",
+ (unsigned int) *(udword*)(&buf[SIZE_POS]),
+ (unsigned int)&buf[SIZE_POS]);
+
+ if (swap_endian(*(udword*)&buf[ADDR_POS]) != ADDR_PATTERN) {
+ printf("Bootloader corrupt. Should contain ret/nop (0x%8.8x) at 0x%x, but contains %x\n",
+ ADDR_PATTERN, ADDR_POS, *(udword*)&buf[ADDR_POS]);
+ exit(EXIT_FAILURE);
+ }
+
+ if (netBoot) {
+ *(udword*)(&buf[ADDR_POS]) = swap_endian(BOOT_ADDRESS + DATA_SIZE);
+ }
+ else {
+ *(udword*)(&buf[ADDR_POS]) = swap_endian(BOOT_ADDRESS-4 + 784);
+ }
+
+ if (db3) printf("Inserting boot address 0x%x at 0x%x.\n",
+ (unsigned int)*(udword*)(&buf[ADDR_POS]),
+ (unsigned int)&buf[ADDR_POS]);
+
+
+ for (i = 0; i != st.st_size; i++) {
+ sum += ((byte*)buf)[i];
+ }
+ if (db1) printf("Checksum 0x%x, bytes %d\n", sum, i);
+
+ if (db4) {
+ int i;
+
+ for(i=0; i<st.st_size; i+=8) {
+ int j;
+
+ printf("0x%8.8x[%4.4x]: ", BOOT_ADDRESS+i, i);
+ for(j=0; i+j<st.st_size && j<8; j++) {
+ printf("%2.2x ", (unsigned char) buf[i+j]);
+ }
+ printf("\n");
+ }
+ }
+ /* Now create list of packets. */
+ while (buf_cnt <= st.st_size) {
+
+ header_size = seq_nr == 0 ?
+ SIZE_OF_FIRST_HEADER : sizeof(struct packet_header_T);
+
+ if (netBoot) {
+ packet_size = ((st.st_size - buf_cnt) < DATA_SIZE ?
+ st.st_size - buf_cnt : DATA_SIZE) + header_size;
+ }
+ else {
+ packet_size = st.st_size;
+ header_size = 0;
+ }
+
+ if (db4) printf("seq_nr %d, header_size %d, packet_size %d\n",
+ seq_nr, header_size, packet_size);
+
+ last_packet = allocate_packet(last_packet);
+
+ first_packet = first_packet ? first_packet : last_packet;
+
+ last_packet->size = packet_size;
+ last_packet->data = (char*)malloc(packet_size);
+ last_packet->seq = seq_nr;
+ last_packet->baud_rate = 9600;
+
+ last_packet->boot_file = allocate_boot_file(NULL);
+ last_packet->boot_file->fileName = boot_loader_file;
+
+ // printf("last_packet->size %8.8x\n", last_packet->size);
+ // printf("last_packet->data %8.8x\n",last_packet->data);
+
+ if (netBoot) {
+ ph = (struct packet_header_T*) last_packet->data;
+ memcpy(ph->dest, dst_addr_of_device, 6);
+ memcpy(ph->src, eth_addr_local, 6);
+ ph->length = htons(packet_size);
+ ph->snap1 = htonl(SNAP1);
+ ph->snap2 = htonl(SNAP2);
+ ph->tag = htonl(SERVER_TAG);
+ ph->seq = htonl(seq_nr);
+ if (seq_nr != 0) {
+ ph->type = htonl(BOOT_PACKET);
+ ph->id = htonl(0);
+ }
+ }
+
+ memcpy(&last_packet->data[header_size], &buf[buf_cnt],
+ packet_size - header_size);
+ if (db3) DecodeSvintoBoot(last_packet->data);
+
+ if (netBoot) {
+ buf_cnt += DATA_SIZE;
+ }
+ else {
+ buf_cnt += packet_size +1;
+ }
+
+ seq_nr++;
+ }
+ }
+
+ if (db4) printf("< CreateBootLoader\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: allocate_packet
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+struct packet_buf*
+allocate_packet(struct packet_buf *p)
+{
+ if (db4) printf("> allocate_packet\n");
+
+ if (p) {
+ p->next = (struct packet_buf*) malloc(sizeof(struct packet_buf));
+ p = p->next;
+ }
+ else {
+ p = (struct packet_buf*) malloc(sizeof(struct packet_buf));
+ }
+ p->next = NULL;
+
+ return(p);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: allocate_boot_file
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+struct boot_files_T*
+allocate_boot_file(struct boot_files_T *bf)
+{
+ if (bf) {
+ bf->next = (struct boot_files_T*) malloc(sizeof(struct boot_files_T));
+ bf = bf->next;
+ }
+ else {
+ bf = (struct boot_files_T*) malloc(sizeof(struct boot_files_T));
+ }
+ bf->next = NULL;
+
+ return(bf);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: CreateBootCmds
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Creates a boot packet from the boot commands. The data is
+*# filled in later by FinishBootCmds().
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980818 ronny Initial version
+*#***************************************************************************/
+
+void
+CreateBootCmds(void)
+{
+ struct packet_header_T *ph;
+
+ if (db4) printf("***> CreateBootCmds\n");
+
+ last_packet = allocate_packet(last_packet);
+
+ boot_cmds_packet = last_packet;
+
+ last_packet->boot_file = allocate_boot_file(NULL);
+ last_packet->boot_file->fileName = BOOT_CMDS_FILE;
+ last_packet->baud_rate = 9600;
+
+ last_packet->size = netBoot ? SIZE_OF_BOOT_CMDS + sizeof(struct packet_header_T)
+ : SIZE_OF_BOOT_CMDS;
+
+ last_packet->data = (char *) malloc(last_packet->size);
+ last_packet->seq = seq_nr;
+
+ if (netBoot) {
+ /* Create packet header. */
+ ph = (struct packet_header_T *) last_packet->data;
+ memcpy(ph->dest, dst_addr_of_device, 6);
+ memcpy(ph->src, eth_addr_local, 6);
+ ph->length = htons(last_packet->size);
+ ph->snap1 = htonl(SNAP1);
+ ph->snap2 = htonl(SNAP2);
+ ph->tag = htonl(SERVER_TAG);
+ ph->seq = htonl(seq_nr);
+ seq_nr++;
+ ph->type = htonl(BOOT_CMDS);
+ ph->id = htonl(0);
+ }
+
+ if (db3) DecodeSvintoBoot(last_packet->data);
+ if (db4) printf("<*** CreateBootCmds\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: FinishBootCmds
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Copies the boot commands into the correct packet and changes
+*# the dwords to network order.
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+void
+FinishBootCmds(void)
+{
+ int i;
+ unsigned int offset = 0;
+
+ for (i = 0; i != boot_cmds_cnt; i++) {
+ boot_cmds[i] = htonl(boot_cmds[i]);
+ if (db3) printf("%8.8x\n", boot_cmds[i]);
+ }
+
+ /* Copy boot commands into packet. */
+ if (netBoot) {
+ offset = sizeof(struct packet_header_T);
+ }
+
+ memcpy(&boot_cmds_packet->data[offset], boot_cmds,
+ boot_cmds_cnt * sizeof(udword));
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: CreateNewBootPacket
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Creates next packet for the files specified by '--file'.
+*#
+*# RETURNS: Next packet, or NULL.
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+struct packet_buf*
+CreateNewBootPacket(void)
+{
+ static char buf[DATA_SIZE];
+ struct packet_header_T *ph;
+ int packet_size;
+ int header_size;
+ int i;
+ udword sum;
+ int size = 0;
+ int padding = 0;
+
+ static struct boot_files_T *bf = NULL;
+
+ if (db3) printf("> CreateNewBootPacket\n");
+
+ bf = bf ? bf : first_boot_file;
+
+ while (bf) {
+ if (!bf->fd) {
+ if (strcmp(bf->fileName, "-") == 0) {
+ bf->fd = stdin;
+ }
+ else {
+ bf->fd = fopen(bf->fileName, "r");
+ }
+
+ if (bf->fd == NULL) {
+ printf("Cannot open boot file %s. Exiting\n", bf->fileName);
+ exit(EXIT_FAILURE);
+ }
+ if (db3) printf("Opening boot file %s\n", bf->fileName);
+ }
+
+ if (!padding) {
+ size = fread(buf, 1, DATA_SIZE, bf->fd);
+ if (size == 0) {
+ if (db3) printf("Nothing more to read. Read: %d/%d\n",
+ bf->size_sent, bf->size);
+ padding = 1;
+ }
+ }
+
+ if (padding) {
+ if (bf->size_sent < bf->size) {
+ if (db3) printf("padding...\n");
+ size = (bf->size - bf->size_sent > DATA_SIZE) ?
+ DATA_SIZE : bf->size - bf->size_sent;
+ memset(buf, 0, size);
+ }
+ else {
+ if (db3) printf("All written\n");
+ padding = 0;
+ size = 0;
+ }
+ }
+
+ if (size != 0) {
+ if (db3) printf("size: %d %d/%d\n", size, bf->size_sent, bf->size);
+ bf->size_sent += size;
+ last_packet = allocate_packet(last_packet);
+
+ /* Calculate checksum. */
+ sum = 0;
+ for (i = 0; i != size; i++) {
+ sum += ((byte*)buf)[i];
+ }
+ if (db2) printf("Checksum 0x%x, bytes %d\n", sum, i);
+
+ /* Figure out size of packet. */
+ if (netBoot) {
+ header_size = seq_nr == 0 ?
+ SIZE_OF_FIRST_HEADER : sizeof(struct packet_header_T);
+
+ packet_size = ((size) < DATA_SIZE ? size : DATA_SIZE) + header_size;
+ }
+ else {
+ header_size = 0;
+ packet_size = size;
+ }
+
+ if (packet_size < 60) { /* CRC adds 4 bytes to 64 */
+ printf(
+ "Last packet from file '%s', is smaller than 64 bytes. \n"
+ "This is not allowed in the Ethernet standard. Will pad with %d "
+ "bytes.\n", bf->fileName, 60-packet_size);
+
+ *(bf->size_p) += 60-packet_size;
+ packet_size = 60;
+ }
+
+ last_packet->size = packet_size;
+ last_packet->data = (char*)malloc(packet_size);
+ last_packet->boot_file = bf;
+ last_packet->baud_rate = set_baudrate;
+
+ /* printf("size %8.8x\n", last_packet->size);*/
+ /* printf("data %8.8x\n",last_packet->data);*/
+
+ if (netBoot) {
+ /* Initialize ethernet header. */
+ ph = (struct packet_header_T*) last_packet->data;
+ memcpy(ph->dest, dst_addr_of_device, 6);
+ memcpy(ph->src, eth_addr_local, 6);
+ /* printf("packet_size %d\n", packet_size);*/
+ ph->length = htons(packet_size);
+ ph->snap1 = htonl(SNAP1);
+ ph->snap2 = htonl(SNAP2);
+ ph->tag = htonl(SERVER_TAG);
+ ph->seq = htonl(seq_nr);
+ last_packet->seq = seq_nr;
+ if (seq_nr != 0) {
+ ph->type = htonl(BOOT_PACKET);
+ ph->id = htonl(0); /* id doesn't matter, we send to a unicast address */
+ }
+ }
+
+ /* Copy data in place. */
+ memcpy(&last_packet->data[header_size], buf, packet_size - header_size);
+ if (db2) DecodeSvintoBoot(last_packet->data);
+ /* PrintPacket(last_packet->data, last_packet->size, HEX);*/
+ seq_nr++;
+
+ if (db3) printf("< CreateNewBootPacket\n");
+ return(last_packet);
+ }
+ else { /* Nothing read from fd. */
+ fclose(bf->fd);
+ bf = bf->next;
+ }
+ }
+
+ if (db3) printf("< CreateNewBootPacket\n");
+ return(NULL);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: swap_endian
+*#
+*# PARAMETERS: u - An unsigned value.
+*#
+*# DESCRIPTION: Convert the unsigned value from host order to little endian.
+*#
+*# RETURNS: The unsigned value as little endian.
+*#
+*#***************************************************************************/
+
+unsigned int
+swap_endian(unsigned int u)
+{
+ /* If the host order is the same as the network order (which is big endian),
+ * we need to swap the bytes in the supplied value.
+ */
+ return ntohl(0x12345678) == 0x12345678 ? bswap_32(u) : u;
+}
+
+/****************** END OF FILE common.c ************************************/
diff --git a/package/etrax-tools/src/e100boot/sbl/common.h b/package/etrax-tools/src/e100boot/sbl/common.h
new file mode 100644
index 000000000..8f854e447
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/common.h
@@ -0,0 +1,57 @@
+/*!***************************************************************************
+*!
+*! FILE NAME : common.h
+*!
+*! DESCRIPTION: Common stuff for e100boot.
+*!
+*! ---------------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! 2002 05 02 Ronny Ranerup Initial version
+*! ---------------------------------------------------------------------------
+*! (C) Copyright 1999, 2000, 2001, 2002 Axis Communications AB, LUND, SWEDEN
+*!***************************************************************************/
+/************************** Include files ********************************/
+/************************** Constants and macros *************************/
+/* max length of argument strings */
+#define MAX_STRING_LEN 256
+/************************** Type definitions *****************************/
+struct packet_buf {
+ unsigned int size;
+ struct packet_buf *next;
+ unsigned int seq;
+ char *data;
+ struct boot_files_T *boot_file;
+ unsigned int baud_rate;
+};
+
+struct boot_files_T {
+ char *fileName;
+ unsigned int *size_p; /* Pointer to size in boot_cmds. */
+ unsigned int size; /* Size of file. */
+ unsigned int size_sent; /* Number of bytes sent so far. */
+ struct boot_files_T *next;
+ FILE *fd;
+};
+
+/************************** Global variables *****************************/
+extern int db1;
+extern int db2;
+extern int db3;
+extern int db4;
+
+extern char device[MAX_STRING_LEN];
+extern struct packet_buf *first_packet;
+extern int cmdsOnly; /* Just dump boot cmds to file. */
+extern int toFiles; /* Dump all packets to files. */
+
+/************************** Function prototypes **************************/
+
+struct packet_buf* create_packet (unsigned int seq);
+struct packet_buf* free_packet (struct packet_buf *p);
+void find_string (char *str);
+
+
+
diff --git a/package/etrax-tools/src/e100boot/sbl/conf.h b/package/etrax-tools/src/e100boot/sbl/conf.h
new file mode 100644
index 000000000..4105bbffb
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/conf.h
@@ -0,0 +1,139 @@
+/* conf.h. Generated automatically by configure. */
+#define HAVE_NET_IF_H 1
+#define HAVE_NETINET_IN_H 1 /* Socket data structure */
+#define HAVE_NETINET_IN_SYSTM_H 1
+#define HAVE_NETINET_IP_H 1
+#define HAVE_NETINET_UDP_H 1
+#define HAVE_NETINET_TCP_H 1
+#define HAVE_NETDB_H 1
+#define HAVE_ARPA_INET_H 1
+#define HAVE_SYS_SOCKET_H 1
+#define HAVE_FCNTL_H 1 /* O_RDONLY */
+#define HAVE_LINUX_IF_ETHER_H 1
+#define HAVE_SIGNAL_H 1
+#define HAVE_STRING_H 1
+#define HAVE_STDLIB_H 1
+#define HAVE_STDIO_H 1
+#define HAVE_SYS_TIME_H 1
+#define HAVE_UNISTD_H 1
+#define HAVE_SYS_STAT_H 1
+#define HAVE_SYS_TYPES_H 1
+#define HAVE_ERRNO_H 1
+#define HAVE_LINUX_SOCKIOS_H 1 /* SIOCGIFHWADDR */
+#define HAVE_CTYPE_H 1
+#define HAVE_PCAP_H 0
+#define TIME_WITH_SYS_TIME 1
+#define HAVE_SYS_SOCKET_H 1
+#define HAVE_SYS_IOCTL_H 1
+#define HAVE_TERMIOS_H 1
+
+#if HAVE_TERMIOS_H
+#include <termios.h>
+#endif
+
+#if HAVE_SYS_IOCTL_H
+#include <sys/ioctl.h>
+#endif
+
+#if HAVE_SYS_TYPES_H
+#include <sys/types.h>
+#endif
+
+#if HAVE_CTYPE_H
+#include <ctype.h>
+#endif
+
+#if HAVE_SYS_SOCKET_H
+#include <sys/socket.h>
+#endif
+
+#if HAVE_NETINET_IN_H
+#include <netinet/in.h>
+#endif
+
+#if HAVE_NET_IF_H
+#include <net/if.h>
+#endif
+
+#if HAVE_NETINET_IN_SYSTM_H
+#include <netinet/in_systm.h>
+#endif
+
+#if HAVE_NETINET_IP_H
+#include <netinet/ip.h>
+#endif
+
+#if HAVE_NETINET_UDP_H
+#include <netinet/udp.h>
+#endif
+
+#if HAVE_NETINET_TCP_H
+#include <netinet/tcp.h>
+#endif
+
+#if HAVE_NETDB_H
+#include <netdb.h>
+#endif
+
+#if HAVE_ARPA_INET_H
+#include <arpa/inet.h>
+#endif
+
+#if HAVE_SYS_SOCKET_H
+#include <sys/socket.h>
+#endif
+
+#if HAVE_FCNTL_H
+#include <fcntl.h>
+#endif
+
+#if HAVE_LINUX_IF_ETHER_H
+#include <linux/if_ether.h>
+#endif
+
+#if HAVE_SIGNAL_H
+#include <signal.h>
+#endif
+
+#if HAVE_STRING_H
+#include <string.h>
+#endif
+
+#if HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+
+#if HAVE_STDIO_H
+#include <stdio.h>
+#endif
+
+#if HAVE_UNISTD_H
+#include <unistd.h>
+#endif
+
+#if HAVE_SYS_STAT_H
+#include <sys/stat.h>
+#endif
+
+#if HAVE_ERRNO_H
+#include <errno.h>
+#endif
+
+#if HAVE_LINUX_SOCKIOS_H
+#include <linux/sockios.h>
+#endif
+
+#if HAVE_PCAP_H
+#include <pcap.h>
+#endif
+
+#if TIME_WITH_SYS_TIME
+#include <sys/time.h>
+#include <time.h>
+#else
+#if HAVE_SYS_TIME_H
+#include <sys/time.h>
+#else
+#include <time.h>
+#endif
+#endif
diff --git a/package/etrax-tools/src/e100boot/sbl/conf.h.in b/package/etrax-tools/src/e100boot/sbl/conf.h.in
new file mode 100644
index 000000000..779c47314
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/conf.h.in
@@ -0,0 +1,138 @@
+#define HAVE_NET_IF_H 0
+#define HAVE_NETINET_IN_H 0 /* Socket data structure */
+#define HAVE_NETINET_IN_SYSTM_H 0
+#define HAVE_NETINET_IP_H 0
+#define HAVE_NETINET_UDP_H 0
+#define HAVE_NETINET_TCP_H 0
+#define HAVE_NETDB_H 0
+#define HAVE_ARPA_INET_H 0
+#define HAVE_SYS_SOCKET_H 0
+#define HAVE_FCNTL_H 0 /* O_RDONLY */
+#define HAVE_LINUX_IF_ETHER_H 0
+#define HAVE_SIGNAL_H 0
+#define HAVE_STRING_H 0
+#define HAVE_STDLIB_H 0
+#define HAVE_STDIO_H 0
+#define HAVE_SYS_TIME_H 0
+#define HAVE_UNISTD_H 0
+#define HAVE_SYS_STAT_H 0
+#define HAVE_SYS_TYPES_H 0
+#define HAVE_ERRNO_H 0
+#define HAVE_LINUX_SOCKIOS_H 0 /* SIOCGIFHWADDR */
+#define HAVE_CTYPE_H 0
+#define HAVE_PCAP_H 0
+#define TIME_WITH_SYS_TIME 0
+#define HAVE_SYS_SOCKET_H 0
+#define HAVE_SYS_IOCTL_H 0
+#define HAVE_TERMIOS_H 0
+
+#if HAVE_TERMIOS_H
+#include <termios.h>
+#endif
+
+#if HAVE_SYS_IOCTL_H
+#include <sys/ioctl.h>
+#endif
+
+#if HAVE_SYS_TYPES_H
+#include <sys/types.h>
+#endif
+
+#if HAVE_CTYPE_H
+#include <ctype.h>
+#endif
+
+#if HAVE_SYS_SOCKET_H
+#include <sys/socket.h>
+#endif
+
+#if HAVE_NETINET_IN_H
+#include <netinet/in.h>
+#endif
+
+#if HAVE_NET_IF_H
+#include <net/if.h>
+#endif
+
+#if HAVE_NETINET_IN_SYSTM_H
+#include <netinet/in_systm.h>
+#endif
+
+#if HAVE_NETINET_IP_H
+#include <netinet/ip.h>
+#endif
+
+#if HAVE_NETINET_UDP_H
+#include <netinet/udp.h>
+#endif
+
+#if HAVE_NETINET_TCP_H
+#include <netinet/tcp.h>
+#endif
+
+#if HAVE_NETDB_H
+#include <netdb.h>
+#endif
+
+#if HAVE_ARPA_INET_H
+#include <arpa/inet.h>
+#endif
+
+#if HAVE_SYS_SOCKET_H
+#include <sys/socket.h>
+#endif
+
+#if HAVE_FCNTL_H
+#include <fcntl.h>
+#endif
+
+#if HAVE_LINUX_IF_ETHER_H
+#include <linux/if_ether.h>
+#endif
+
+#if HAVE_SIGNAL_H
+#include <signal.h>
+#endif
+
+#if HAVE_STRING_H
+#include <string.h>
+#endif
+
+#if HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+
+#if HAVE_STDIO_H
+#include <stdio.h>
+#endif
+
+#if HAVE_UNISTD_H
+#include <unistd.h>
+#endif
+
+#if HAVE_SYS_STAT_H
+#include <sys/stat.h>
+#endif
+
+#if HAVE_ERRNO_H
+#include <errno.h>
+#endif
+
+#if HAVE_LINUX_SOCKIOS_H
+#include <linux/sockios.h>
+#endif
+
+#if HAVE_PCAP_H
+#include <pcap.h>
+#endif
+
+#if TIME_WITH_SYS_TIME
+#include <sys/time.h>
+#include <time.h>
+#else
+#if HAVE_SYS_TIME_H
+#include <sys/time.h>
+#else
+#include <time.h>
+#endif
+#endif
diff --git a/package/etrax-tools/src/e100boot/sbl/config.cache b/package/etrax-tools/src/e100boot/sbl/config.cache
new file mode 100644
index 000000000..a5c0e9cf7
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/config.cache
@@ -0,0 +1,48 @@
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs. It is not useful on other systems.
+# If it contains results you don't want to keep, you may remove or edit it.
+#
+# By default, configure uses ./config.cache as the cache file,
+# creating it if it does not exist already. You can give configure
+# the --cache-file=FILE option to use a different cache file; that is
+# what configure does when it calls configure scripts in
+# subdirectories, so they share the cache.
+# Giving --cache-file=/dev/null disables caching, for debugging configure.
+# config.status only pays attention to the cache file if you give it the
+# --recheck option to rerun configure.
+#
+ac_cv_header_arpa_inet_h=${ac_cv_header_arpa_inet_h=yes}
+ac_cv_header_ctype_h=${ac_cv_header_ctype_h=yes}
+ac_cv_header_errno_h=${ac_cv_header_errno_h=yes}
+ac_cv_header_fcntl_h=${ac_cv_header_fcntl_h=yes}
+ac_cv_header_linux_if_ether_h=${ac_cv_header_linux_if_ether_h=yes}
+ac_cv_header_linux_sockios_h=${ac_cv_header_linux_sockios_h=yes}
+ac_cv_header_net_if_h=${ac_cv_header_net_if_h=yes}
+ac_cv_header_netdb_h=${ac_cv_header_netdb_h=yes}
+ac_cv_header_netinet_in_h=${ac_cv_header_netinet_in_h=yes}
+ac_cv_header_netinet_in_systm_h=${ac_cv_header_netinet_in_systm_h=yes}
+ac_cv_header_netinet_ip_h=${ac_cv_header_netinet_ip_h=yes}
+ac_cv_header_netinet_tcp_h=${ac_cv_header_netinet_tcp_h=yes}
+ac_cv_header_netinet_udp_h=${ac_cv_header_netinet_udp_h=yes}
+ac_cv_header_pcap_pcap_h=${ac_cv_header_pcap_pcap_h=no}
+ac_cv_header_signal_h=${ac_cv_header_signal_h=yes}
+ac_cv_header_stdc=${ac_cv_header_stdc=yes}
+ac_cv_header_stdio_h=${ac_cv_header_stdio_h=yes}
+ac_cv_header_stdlib_h=${ac_cv_header_stdlib_h=yes}
+ac_cv_header_string_h=${ac_cv_header_string_h=yes}
+ac_cv_header_sys_ioctl_h=${ac_cv_header_sys_ioctl_h=yes}
+ac_cv_header_sys_socket_h=${ac_cv_header_sys_socket_h=yes}
+ac_cv_header_sys_stat_h=${ac_cv_header_sys_stat_h=yes}
+ac_cv_header_sys_time_h=${ac_cv_header_sys_time_h=yes}
+ac_cv_header_sys_types_h=${ac_cv_header_sys_types_h=yes}
+ac_cv_header_termios_h=${ac_cv_header_termios_h=yes}
+ac_cv_header_time=${ac_cv_header_time=yes}
+ac_cv_header_unistd_h=${ac_cv_header_unistd_h=yes}
+ac_cv_lib_pcap_pcap_open_live=${ac_cv_lib_pcap_pcap_open_live=no}
+ac_cv_prog_CC=${ac_cv_prog_CC=gcc}
+ac_cv_prog_CPP=${ac_cv_prog_CPP='gcc -E'}
+ac_cv_prog_cc_cross=${ac_cv_prog_cc_cross=no}
+ac_cv_prog_cc_g=${ac_cv_prog_cc_g=yes}
+ac_cv_prog_cc_works=${ac_cv_prog_cc_works=yes}
+ac_cv_prog_gcc=${ac_cv_prog_gcc=yes}
diff --git a/package/etrax-tools/src/e100boot/sbl/config.log b/package/etrax-tools/src/e100boot/sbl/config.log
new file mode 100644
index 000000000..43de9c5da
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/config.log
@@ -0,0 +1,90 @@
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+
+configure:530: checking for gcc
+configure:643: checking whether the C compiler (gcc ) works
+configure:659: gcc -o conftest conftest.c 1>&5
+configure:685: checking whether the C compiler (gcc ) is a cross-compiler
+configure:690: checking whether we are using GNU C
+configure:699: gcc -E conftest.c
+configure:718: checking whether gcc accepts -g
+configure:751: checking for pcap_open_live in -lpcap
+configure:770: gcc -o conftest -g -O2 conftest.c -lpcap 1>&5
+/usr/bin/ld: cannot find -lpcap
+collect2: ld returned 1 exit status
+configure: failed program was:
+#line 759 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char pcap_open_live();
+
+int main() {
+pcap_open_live()
+; return 0; }
+configure:799: checking how to run the C preprocessor
+configure:820: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:879: checking for ANSI C header files
+configure:892: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:959: gcc -o conftest -g -O2 conftest.c 1>&5
+configure: In function 'main':
+configure:954: warning: incompatible implicit declaration of built-in function 'exit'
+configure:986: checking for termios.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for sys/ioctl.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for net/if.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for netinet/in.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for netinet/in_systm.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for netinet/ip.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for netinet/udp.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for netinet/tcp.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for netdb.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for arpa/inet.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for sys/socket.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for fcntl.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for linux/if_ether.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for signal.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for string.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for stdlib.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for stdio.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for sys/time.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for unistd.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for sys/stat.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for sys/types.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for errno.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for linux/sockios.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for ctype.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:986: checking for sys/socket.h
+configure:986: checking for pcap/pcap.h
+configure:996: gcc -E conftest.c >/dev/null 2>conftest.out
+configure:992:23: error: pcap/pcap.h: No such file or directory
+configure: failed program was:
+#line 991 "configure"
+#include "confdefs.h"
+#include <pcap/pcap.h>
+configure:1024: checking whether time.h and sys/time.h may both be included
+configure:1038: gcc -c -g -O2 conftest.c 1>&5
diff --git a/package/etrax-tools/src/e100boot/sbl/config.status b/package/etrax-tools/src/e100boot/sbl/config.status
new file mode 100755
index 000000000..3580ac717
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/config.status
@@ -0,0 +1,330 @@
+#! /bin/sh
+# Generated automatically by configure.
+# Run this file to recreate the current configuration.
+# This directory was configured as follows,
+# on host bertha:
+#
+# ./configure
+#
+# Compiler output produced by configure, useful for debugging
+# configure, is in ./config.log if it exists.
+
+ac_cs_usage="Usage: ./config.status [--recheck] [--version] [--help]"
+for ac_option
+do
+ case "$ac_option" in
+ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+ echo "running ${CONFIG_SHELL-/bin/sh} ./configure --no-create --no-recursion"
+ exec ${CONFIG_SHELL-/bin/sh} ./configure --no-create --no-recursion ;;
+ -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
+ echo "./config.status generated by autoconf version 2.13"
+ exit 0 ;;
+ -help | --help | --hel | --he | --h)
+ echo "$ac_cs_usage"; exit 0 ;;
+ *) echo "$ac_cs_usage"; exit 1 ;;
+ esac
+done
+
+ac_given_srcdir=.
+
+trap 'rm -fr Makefile conf.h conftest*; exit 1' 1 2 15
+
+# Protect against being on the right side of a sed subst in config.status.
+sed 's/%@/@@/; s/@%/@@/; s/%g$/@g/; /@g$/s/[\\&%]/\\&/g;
+ s/@@/%@/; s/@@/@%/; s/@g$/%g/' > conftest.subs <<\CEOF
+/^[ ]*VPATH[ ]*=[^:]*$/d
+
+s%@SHELL@%/bin/sh%g
+s%@CFLAGS@%-g -O2%g
+s%@CPPFLAGS@%%g
+s%@CXXFLAGS@%%g
+s%@FFLAGS@%%g
+s%@DEFS@%-DHAVE_CONFIG_H%g
+s%@LDFLAGS@%%g
+s%@LIBS@%%g
+s%@exec_prefix@%${prefix}%g
+s%@prefix@%/usr/local%g
+s%@program_transform_name@%s,x,x,%g
+s%@bindir@%${exec_prefix}/bin%g
+s%@sbindir@%${exec_prefix}/sbin%g
+s%@libexecdir@%${exec_prefix}/libexec%g
+s%@datadir@%${prefix}/share%g
+s%@sysconfdir@%${prefix}/etc%g
+s%@sharedstatedir@%${prefix}/com%g
+s%@localstatedir@%${prefix}/var%g
+s%@libdir@%${exec_prefix}/lib%g
+s%@includedir@%${prefix}/include%g
+s%@oldincludedir@%/usr/include%g
+s%@infodir@%${prefix}/info%g
+s%@mandir@%${prefix}/man%g
+s%@CC@%gcc%g
+s%@CPP@%gcc -E%g
+
+CEOF
+
+# Split the substitutions into bite-sized pieces for seds with
+# small command number limits, like on Digital OSF/1 and HP-UX.
+ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
+ac_file=1 # Number of current file.
+ac_beg=1 # First line for current file.
+ac_end=$ac_max_sed_cmds # Line after last line for current file.
+ac_more_lines=:
+ac_sed_cmds=""
+while $ac_more_lines; do
+ if test $ac_beg -gt 1; then
+ sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
+ else
+ sed "${ac_end}q" conftest.subs > conftest.s$ac_file
+ fi
+ if test ! -s conftest.s$ac_file; then
+ ac_more_lines=false
+ rm -f conftest.s$ac_file
+ else
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds="sed -f conftest.s$ac_file"
+ else
+ ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
+ fi
+ ac_file=`expr $ac_file + 1`
+ ac_beg=$ac_end
+ ac_end=`expr $ac_end + $ac_max_sed_cmds`
+ fi
+done
+if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds=cat
+fi
+
+CONFIG_FILES=${CONFIG_FILES-"Makefile"}
+for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case "$ac_file" in
+ *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+ ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+ *) ac_file_in="${ac_file}.in" ;;
+ esac
+
+ # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
+
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+ # The file is in a subdirectory.
+ test ! -d "$ac_dir" && mkdir "$ac_dir"
+ ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
+ else
+ ac_dir_suffix= ac_dots=
+ fi
+
+ case "$ac_given_srcdir" in
+ .) srcdir=.
+ if test -z "$ac_dots"; then top_srcdir=.
+ else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
+ /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
+ *) # Relative path.
+ srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
+ top_srcdir="$ac_dots$ac_given_srcdir" ;;
+ esac
+
+
+ echo creating "$ac_file"
+ rm -f "$ac_file"
+ configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
+ case "$ac_file" in
+ *Makefile*) ac_comsub="1i\\
+# $configure_input" ;;
+ *) ac_comsub= ;;
+ esac
+
+ ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+ sed -e "$ac_comsub
+s%@configure_input@%$configure_input%g
+s%@srcdir@%$srcdir%g
+s%@top_srcdir@%$top_srcdir%g
+" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
+fi; done
+rm -f conftest.s*
+
+# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
+# NAME is the cpp macro being defined and VALUE is the value it is being given.
+#
+# ac_d sets the value in "#define NAME VALUE" lines.
+ac_dA='s%^\([ ]*\)#\([ ]*define[ ][ ]*\)'
+ac_dB='\([ ][ ]*\)[^ ]*%\1#\2'
+ac_dC='\3'
+ac_dD='%g'
+# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE".
+ac_uA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)'
+ac_uB='\([ ]\)%\1#\2define\3'
+ac_uC=' '
+ac_uD='\4%g'
+# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
+ac_eA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)'
+ac_eB='$%\1#\2define\3'
+ac_eC=' '
+ac_eD='%g'
+
+if test "${CONFIG_HEADERS+set}" != set; then
+ CONFIG_HEADERS="conf.h"
+fi
+for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case "$ac_file" in
+ *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+ ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+ *) ac_file_in="${ac_file}.in" ;;
+ esac
+
+ echo creating $ac_file
+
+ rm -f conftest.frag conftest.in conftest.out
+ ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+ cat $ac_file_inputs > conftest.in
+
+ cat > conftest.frag <<CEOF
+${ac_dA}STDC_HEADERS${ac_dB}STDC_HEADERS${ac_dC}1${ac_dD}
+${ac_uA}STDC_HEADERS${ac_uB}STDC_HEADERS${ac_uC}1${ac_uD}
+${ac_eA}STDC_HEADERS${ac_eB}STDC_HEADERS${ac_eC}1${ac_eD}
+${ac_dA}HAVE_TERMIOS_H${ac_dB}HAVE_TERMIOS_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_TERMIOS_H${ac_uB}HAVE_TERMIOS_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_TERMIOS_H${ac_eB}HAVE_TERMIOS_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_SYS_IOCTL_H${ac_dB}HAVE_SYS_IOCTL_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_SYS_IOCTL_H${ac_uB}HAVE_SYS_IOCTL_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_SYS_IOCTL_H${ac_eB}HAVE_SYS_IOCTL_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_NET_IF_H${ac_dB}HAVE_NET_IF_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_NET_IF_H${ac_uB}HAVE_NET_IF_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_NET_IF_H${ac_eB}HAVE_NET_IF_H${ac_eC}1${ac_eD}
+CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+
+ cat > conftest.frag <<CEOF
+${ac_dA}HAVE_NETINET_IN_H${ac_dB}HAVE_NETINET_IN_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_NETINET_IN_H${ac_uB}HAVE_NETINET_IN_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_NETINET_IN_H${ac_eB}HAVE_NETINET_IN_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_NETINET_IN_SYSTM_H${ac_dB}HAVE_NETINET_IN_SYSTM_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_NETINET_IN_SYSTM_H${ac_uB}HAVE_NETINET_IN_SYSTM_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_NETINET_IN_SYSTM_H${ac_eB}HAVE_NETINET_IN_SYSTM_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_NETINET_IP_H${ac_dB}HAVE_NETINET_IP_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_NETINET_IP_H${ac_uB}HAVE_NETINET_IP_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_NETINET_IP_H${ac_eB}HAVE_NETINET_IP_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_NETINET_UDP_H${ac_dB}HAVE_NETINET_UDP_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_NETINET_UDP_H${ac_uB}HAVE_NETINET_UDP_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_NETINET_UDP_H${ac_eB}HAVE_NETINET_UDP_H${ac_eC}1${ac_eD}
+CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+
+ cat > conftest.frag <<CEOF
+${ac_dA}HAVE_NETINET_TCP_H${ac_dB}HAVE_NETINET_TCP_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_NETINET_TCP_H${ac_uB}HAVE_NETINET_TCP_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_NETINET_TCP_H${ac_eB}HAVE_NETINET_TCP_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_NETDB_H${ac_dB}HAVE_NETDB_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_NETDB_H${ac_uB}HAVE_NETDB_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_NETDB_H${ac_eB}HAVE_NETDB_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_ARPA_INET_H${ac_dB}HAVE_ARPA_INET_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_ARPA_INET_H${ac_uB}HAVE_ARPA_INET_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_ARPA_INET_H${ac_eB}HAVE_ARPA_INET_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_SYS_SOCKET_H${ac_dB}HAVE_SYS_SOCKET_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_SYS_SOCKET_H${ac_uB}HAVE_SYS_SOCKET_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_SYS_SOCKET_H${ac_eB}HAVE_SYS_SOCKET_H${ac_eC}1${ac_eD}
+CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+
+ cat > conftest.frag <<CEOF
+${ac_dA}HAVE_FCNTL_H${ac_dB}HAVE_FCNTL_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_FCNTL_H${ac_uB}HAVE_FCNTL_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_FCNTL_H${ac_eB}HAVE_FCNTL_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_LINUX_IF_ETHER_H${ac_dB}HAVE_LINUX_IF_ETHER_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_LINUX_IF_ETHER_H${ac_uB}HAVE_LINUX_IF_ETHER_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_LINUX_IF_ETHER_H${ac_eB}HAVE_LINUX_IF_ETHER_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_SIGNAL_H${ac_dB}HAVE_SIGNAL_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_SIGNAL_H${ac_uB}HAVE_SIGNAL_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_SIGNAL_H${ac_eB}HAVE_SIGNAL_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_STRING_H${ac_dB}HAVE_STRING_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_STRING_H${ac_uB}HAVE_STRING_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_STRING_H${ac_eB}HAVE_STRING_H${ac_eC}1${ac_eD}
+CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+
+ cat > conftest.frag <<CEOF
+${ac_dA}HAVE_STDLIB_H${ac_dB}HAVE_STDLIB_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_STDLIB_H${ac_uB}HAVE_STDLIB_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_STDLIB_H${ac_eB}HAVE_STDLIB_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_STDIO_H${ac_dB}HAVE_STDIO_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_STDIO_H${ac_uB}HAVE_STDIO_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_STDIO_H${ac_eB}HAVE_STDIO_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_SYS_TIME_H${ac_dB}HAVE_SYS_TIME_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_SYS_TIME_H${ac_uB}HAVE_SYS_TIME_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_SYS_TIME_H${ac_eB}HAVE_SYS_TIME_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_UNISTD_H${ac_dB}HAVE_UNISTD_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_UNISTD_H${ac_uB}HAVE_UNISTD_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_UNISTD_H${ac_eB}HAVE_UNISTD_H${ac_eC}1${ac_eD}
+CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+
+ cat > conftest.frag <<CEOF
+${ac_dA}HAVE_SYS_STAT_H${ac_dB}HAVE_SYS_STAT_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_SYS_STAT_H${ac_uB}HAVE_SYS_STAT_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_SYS_STAT_H${ac_eB}HAVE_SYS_STAT_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_SYS_TYPES_H${ac_dB}HAVE_SYS_TYPES_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_SYS_TYPES_H${ac_uB}HAVE_SYS_TYPES_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_SYS_TYPES_H${ac_eB}HAVE_SYS_TYPES_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_ERRNO_H${ac_dB}HAVE_ERRNO_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_ERRNO_H${ac_uB}HAVE_ERRNO_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_ERRNO_H${ac_eB}HAVE_ERRNO_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_LINUX_SOCKIOS_H${ac_dB}HAVE_LINUX_SOCKIOS_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_LINUX_SOCKIOS_H${ac_uB}HAVE_LINUX_SOCKIOS_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_LINUX_SOCKIOS_H${ac_eB}HAVE_LINUX_SOCKIOS_H${ac_eC}1${ac_eD}
+CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+
+ cat > conftest.frag <<CEOF
+${ac_dA}HAVE_CTYPE_H${ac_dB}HAVE_CTYPE_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_CTYPE_H${ac_uB}HAVE_CTYPE_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_CTYPE_H${ac_eB}HAVE_CTYPE_H${ac_eC}1${ac_eD}
+${ac_dA}HAVE_SYS_SOCKET_H${ac_dB}HAVE_SYS_SOCKET_H${ac_dC}1${ac_dD}
+${ac_uA}HAVE_SYS_SOCKET_H${ac_uB}HAVE_SYS_SOCKET_H${ac_uC}1${ac_uD}
+${ac_eA}HAVE_SYS_SOCKET_H${ac_eB}HAVE_SYS_SOCKET_H${ac_eC}1${ac_eD}
+${ac_dA}TIME_WITH_SYS_TIME${ac_dB}TIME_WITH_SYS_TIME${ac_dC}1${ac_dD}
+${ac_uA}TIME_WITH_SYS_TIME${ac_uB}TIME_WITH_SYS_TIME${ac_uC}1${ac_uD}
+${ac_eA}TIME_WITH_SYS_TIME${ac_eB}TIME_WITH_SYS_TIME${ac_eC}1${ac_eD}
+s%^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%
+CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+
+ rm -f conftest.frag conftest.h
+ echo "/* $ac_file. Generated automatically by configure. */" > conftest.h
+ cat conftest.in >> conftest.h
+ rm -f conftest.in
+ if cmp -s $ac_file conftest.h 2>/dev/null; then
+ echo "$ac_file is unchanged"
+ rm -f conftest.h
+ else
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+ # The file is in a subdirectory.
+ test ! -d "$ac_dir" && mkdir "$ac_dir"
+ fi
+ rm -f $ac_file
+ mv conftest.h $ac_file
+ fi
+fi; done
+
+
+
+exit 0
diff --git a/package/etrax-tools/src/e100boot/sbl/configure b/package/etrax-tools/src/e100boot/sbl/configure
new file mode 100755
index 000000000..16b8bf52f
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/configure
@@ -0,0 +1,1405 @@
+#! /bin/sh
+
+# Guess values for system-dependent variables and create Makefiles.
+# Generated automatically using autoconf version 2.13
+# Copyright (C) 1992, 93, 94, 95, 96 Free Software Foundation, Inc.
+#
+# This configure script is free software; the Free Software Foundation
+# gives unlimited permission to copy, distribute and modify it.
+
+# Defaults:
+ac_help=
+ac_default_prefix=/usr/local
+# Any additions from configure.in:
+
+# Initialize some variables set by options.
+# The variables have the same names as the options, with
+# dashes changed to underlines.
+build=NONE
+cache_file=./config.cache
+exec_prefix=NONE
+host=NONE
+no_create=
+nonopt=NONE
+no_recursion=
+prefix=NONE
+program_prefix=NONE
+program_suffix=NONE
+program_transform_name=s,x,x,
+silent=
+site=
+srcdir=
+target=NONE
+verbose=
+x_includes=NONE
+x_libraries=NONE
+bindir='${exec_prefix}/bin'
+sbindir='${exec_prefix}/sbin'
+libexecdir='${exec_prefix}/libexec'
+datadir='${prefix}/share'
+sysconfdir='${prefix}/etc'
+sharedstatedir='${prefix}/com'
+localstatedir='${prefix}/var'
+libdir='${exec_prefix}/lib'
+includedir='${prefix}/include'
+oldincludedir='/usr/include'
+infodir='${prefix}/info'
+mandir='${prefix}/man'
+
+# Initialize some other variables.
+subdirs=
+MFLAGS= MAKEFLAGS=
+SHELL=${CONFIG_SHELL-/bin/sh}
+# Maximum number of lines to put in a shell here document.
+ac_max_here_lines=12
+
+ac_prev=
+for ac_option
+do
+
+ # If the previous option needs an argument, assign it.
+ if test -n "$ac_prev"; then
+ eval "$ac_prev=\$ac_option"
+ ac_prev=
+ continue
+ fi
+
+ case "$ac_option" in
+ -*=*) ac_optarg=`echo "$ac_option" | sed 's/[-_a-zA-Z0-9]*=//'` ;;
+ *) ac_optarg= ;;
+ esac
+
+ # Accept the important Cygnus configure options, so we can diagnose typos.
+
+ case "$ac_option" in
+
+ -bindir | --bindir | --bindi | --bind | --bin | --bi)
+ ac_prev=bindir ;;
+ -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*)
+ bindir="$ac_optarg" ;;
+
+ -build | --build | --buil | --bui | --bu)
+ ac_prev=build ;;
+ -build=* | --build=* | --buil=* | --bui=* | --bu=*)
+ build="$ac_optarg" ;;
+
+ -cache-file | --cache-file | --cache-fil | --cache-fi \
+ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c)
+ ac_prev=cache_file ;;
+ -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \
+ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*)
+ cache_file="$ac_optarg" ;;
+
+ -datadir | --datadir | --datadi | --datad | --data | --dat | --da)
+ ac_prev=datadir ;;
+ -datadir=* | --datadir=* | --datadi=* | --datad=* | --data=* | --dat=* \
+ | --da=*)
+ datadir="$ac_optarg" ;;
+
+ -disable-* | --disable-*)
+ ac_feature=`echo $ac_option|sed -e 's/-*disable-//'`
+ # Reject names that are not valid shell variable names.
+ if test -n "`echo $ac_feature| sed 's/[-a-zA-Z0-9_]//g'`"; then
+ { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+ fi
+ ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+ eval "enable_${ac_feature}=no" ;;
+
+ -enable-* | --enable-*)
+ ac_feature=`echo $ac_option|sed -e 's/-*enable-//' -e 's/=.*//'`
+ # Reject names that are not valid shell variable names.
+ if test -n "`echo $ac_feature| sed 's/[-_a-zA-Z0-9]//g'`"; then
+ { echo "configure: error: $ac_feature: invalid feature name" 1>&2; exit 1; }
+ fi
+ ac_feature=`echo $ac_feature| sed 's/-/_/g'`
+ case "$ac_option" in
+ *=*) ;;
+ *) ac_optarg=yes ;;
+ esac
+ eval "enable_${ac_feature}='$ac_optarg'" ;;
+
+ -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \
+ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \
+ | --exec | --exe | --ex)
+ ac_prev=exec_prefix ;;
+ -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \
+ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \
+ | --exec=* | --exe=* | --ex=*)
+ exec_prefix="$ac_optarg" ;;
+
+ -gas | --gas | --ga | --g)
+ # Obsolete; use --with-gas.
+ with_gas=yes ;;
+
+ -help | --help | --hel | --he)
+ # Omit some internal or obsolete options to make the list less imposing.
+ # This message is too long to be a string in the A/UX 3.1 sh.
+ cat << EOF
+Usage: configure [options] [host]
+Options: [defaults in brackets after descriptions]
+Configuration:
+ --cache-file=FILE cache test results in FILE
+ --help print this message
+ --no-create do not create output files
+ --quiet, --silent do not print \`checking...' messages
+ --version print the version of autoconf that created configure
+Directory and file names:
+ --prefix=PREFIX install architecture-independent files in PREFIX
+ [$ac_default_prefix]
+ --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX
+ [same as prefix]
+ --bindir=DIR user executables in DIR [EPREFIX/bin]
+ --sbindir=DIR system admin executables in DIR [EPREFIX/sbin]
+ --libexecdir=DIR program executables in DIR [EPREFIX/libexec]
+ --datadir=DIR read-only architecture-independent data in DIR
+ [PREFIX/share]
+ --sysconfdir=DIR read-only single-machine data in DIR [PREFIX/etc]
+ --sharedstatedir=DIR modifiable architecture-independent data in DIR
+ [PREFIX/com]
+ --localstatedir=DIR modifiable single-machine data in DIR [PREFIX/var]
+ --libdir=DIR object code libraries in DIR [EPREFIX/lib]
+ --includedir=DIR C header files in DIR [PREFIX/include]
+ --oldincludedir=DIR C header files for non-gcc in DIR [/usr/include]
+ --infodir=DIR info documentation in DIR [PREFIX/info]
+ --mandir=DIR man documentation in DIR [PREFIX/man]
+ --srcdir=DIR find the sources in DIR [configure dir or ..]
+ --program-prefix=PREFIX prepend PREFIX to installed program names
+ --program-suffix=SUFFIX append SUFFIX to installed program names
+ --program-transform-name=PROGRAM
+ run sed PROGRAM on installed program names
+EOF
+ cat << EOF
+Host type:
+ --build=BUILD configure for building on BUILD [BUILD=HOST]
+ --host=HOST configure for HOST [guessed]
+ --target=TARGET configure for TARGET [TARGET=HOST]
+Features and packages:
+ --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no)
+ --enable-FEATURE[=ARG] include FEATURE [ARG=yes]
+ --with-PACKAGE[=ARG] use PACKAGE [ARG=yes]
+ --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no)
+ --x-includes=DIR X include files are in DIR
+ --x-libraries=DIR X library files are in DIR
+EOF
+ if test -n "$ac_help"; then
+ echo "--enable and --with options recognized:$ac_help"
+ fi
+ exit 0 ;;
+
+ -host | --host | --hos | --ho)
+ ac_prev=host ;;
+ -host=* | --host=* | --hos=* | --ho=*)
+ host="$ac_optarg" ;;
+
+ -includedir | --includedir | --includedi | --included | --include \
+ | --includ | --inclu | --incl | --inc)
+ ac_prev=includedir ;;
+ -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \
+ | --includ=* | --inclu=* | --incl=* | --inc=*)
+ includedir="$ac_optarg" ;;
+
+ -infodir | --infodir | --infodi | --infod | --info | --inf)
+ ac_prev=infodir ;;
+ -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*)
+ infodir="$ac_optarg" ;;
+
+ -libdir | --libdir | --libdi | --libd)
+ ac_prev=libdir ;;
+ -libdir=* | --libdir=* | --libdi=* | --libd=*)
+ libdir="$ac_optarg" ;;
+
+ -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \
+ | --libexe | --libex | --libe)
+ ac_prev=libexecdir ;;
+ -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \
+ | --libexe=* | --libex=* | --libe=*)
+ libexecdir="$ac_optarg" ;;
+
+ -localstatedir | --localstatedir | --localstatedi | --localstated \
+ | --localstate | --localstat | --localsta | --localst \
+ | --locals | --local | --loca | --loc | --lo)
+ ac_prev=localstatedir ;;
+ -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \
+ | --localstate=* | --localstat=* | --localsta=* | --localst=* \
+ | --locals=* | --local=* | --loca=* | --loc=* | --lo=*)
+ localstatedir="$ac_optarg" ;;
+
+ -mandir | --mandir | --mandi | --mand | --man | --ma | --m)
+ ac_prev=mandir ;;
+ -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*)
+ mandir="$ac_optarg" ;;
+
+ -nfp | --nfp | --nf)
+ # Obsolete; use --without-fp.
+ with_fp=no ;;
+
+ -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+ | --no-cr | --no-c)
+ no_create=yes ;;
+
+ -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r)
+ no_recursion=yes ;;
+
+ -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \
+ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \
+ | --oldin | --oldi | --old | --ol | --o)
+ ac_prev=oldincludedir ;;
+ -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \
+ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \
+ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*)
+ oldincludedir="$ac_optarg" ;;
+
+ -prefix | --prefix | --prefi | --pref | --pre | --pr | --p)
+ ac_prev=prefix ;;
+ -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
+ prefix="$ac_optarg" ;;
+
+ -program-prefix | --program-prefix | --program-prefi | --program-pref \
+ | --program-pre | --program-pr | --program-p)
+ ac_prev=program_prefix ;;
+ -program-prefix=* | --program-prefix=* | --program-prefi=* \
+ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
+ program_prefix="$ac_optarg" ;;
+
+ -program-suffix | --program-suffix | --program-suffi | --program-suff \
+ | --program-suf | --program-su | --program-s)
+ ac_prev=program_suffix ;;
+ -program-suffix=* | --program-suffix=* | --program-suffi=* \
+ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
+ program_suffix="$ac_optarg" ;;
+
+ -program-transform-name | --program-transform-name \
+ | --program-transform-nam | --program-transform-na \
+ | --program-transform-n | --program-transform- \
+ | --program-transform | --program-transfor \
+ | --program-transfo | --program-transf \
+ | --program-trans | --program-tran \
+ | --progr-tra | --program-tr | --program-t)
+ ac_prev=program_transform_name ;;
+ -program-transform-name=* | --program-transform-name=* \
+ | --program-transform-nam=* | --program-transform-na=* \
+ | --program-transform-n=* | --program-transform-=* \
+ | --program-transform=* | --program-transfor=* \
+ | --program-transfo=* | --program-transf=* \
+ | --program-trans=* | --program-tran=* \
+ | --progr-tra=* | --program-tr=* | --program-t=*)
+ program_transform_name="$ac_optarg" ;;
+
+ -q | -quiet | --quiet | --quie | --qui | --qu | --q \
+ | -silent | --silent | --silen | --sile | --sil)
+ silent=yes ;;
+
+ -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb)
+ ac_prev=sbindir ;;
+ -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \
+ | --sbi=* | --sb=*)
+ sbindir="$ac_optarg" ;;
+
+ -sharedstatedir | --sharedstatedir | --sharedstatedi \
+ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \
+ | --sharedst | --shareds | --shared | --share | --shar \
+ | --sha | --sh)
+ ac_prev=sharedstatedir ;;
+ -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \
+ | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \
+ | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \
+ | --sha=* | --sh=*)
+ sharedstatedir="$ac_optarg" ;;
+
+ -site | --site | --sit)
+ ac_prev=site ;;
+ -site=* | --site=* | --sit=*)
+ site="$ac_optarg" ;;
+
+ -srcdir | --srcdir | --srcdi | --srcd | --src | --sr)
+ ac_prev=srcdir ;;
+ -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*)
+ srcdir="$ac_optarg" ;;
+
+ -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \
+ | --syscon | --sysco | --sysc | --sys | --sy)
+ ac_prev=sysconfdir ;;
+ -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \
+ | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*)
+ sysconfdir="$ac_optarg" ;;
+
+ -target | --target | --targe | --targ | --tar | --ta | --t)
+ ac_prev=target ;;
+ -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*)
+ target="$ac_optarg" ;;
+
+ -v | -verbose | --verbose | --verbos | --verbo | --verb)
+ verbose=yes ;;
+
+ -version | --version | --versio | --versi | --vers)
+ echo "configure generated by autoconf version 2.13"
+ exit 0 ;;
+
+ -with-* | --with-*)
+ ac_package=`echo $ac_option|sed -e 's/-*with-//' -e 's/=.*//'`
+ # Reject names that are not valid shell variable names.
+ if test -n "`echo $ac_package| sed 's/[-_a-zA-Z0-9]//g'`"; then
+ { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+ fi
+ ac_package=`echo $ac_package| sed 's/-/_/g'`
+ case "$ac_option" in
+ *=*) ;;
+ *) ac_optarg=yes ;;
+ esac
+ eval "with_${ac_package}='$ac_optarg'" ;;
+
+ -without-* | --without-*)
+ ac_package=`echo $ac_option|sed -e 's/-*without-//'`
+ # Reject names that are not valid shell variable names.
+ if test -n "`echo $ac_package| sed 's/[-a-zA-Z0-9_]//g'`"; then
+ { echo "configure: error: $ac_package: invalid package name" 1>&2; exit 1; }
+ fi
+ ac_package=`echo $ac_package| sed 's/-/_/g'`
+ eval "with_${ac_package}=no" ;;
+
+ --x)
+ # Obsolete; use --with-x.
+ with_x=yes ;;
+
+ -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \
+ | --x-incl | --x-inc | --x-in | --x-i)
+ ac_prev=x_includes ;;
+ -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \
+ | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*)
+ x_includes="$ac_optarg" ;;
+
+ -x-libraries | --x-libraries | --x-librarie | --x-librari \
+ | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l)
+ ac_prev=x_libraries ;;
+ -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \
+ | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*)
+ x_libraries="$ac_optarg" ;;
+
+ -*) { echo "configure: error: $ac_option: invalid option; use --help to show usage" 1>&2; exit 1; }
+ ;;
+
+ *)
+ if test -n "`echo $ac_option| sed 's/[-a-z0-9.]//g'`"; then
+ echo "configure: warning: $ac_option: invalid host type" 1>&2
+ fi
+ if test "x$nonopt" != xNONE; then
+ { echo "configure: error: can only configure for one host and one target at a time" 1>&2; exit 1; }
+ fi
+ nonopt="$ac_option"
+ ;;
+
+ esac
+done
+
+if test -n "$ac_prev"; then
+ { echo "configure: error: missing argument to --`echo $ac_prev | sed 's/_/-/g'`" 1>&2; exit 1; }
+fi
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+# File descriptor usage:
+# 0 standard input
+# 1 file creation
+# 2 errors and warnings
+# 3 some systems may open it to /dev/tty
+# 4 used on the Kubota Titan
+# 6 checking for... messages and results
+# 5 compiler messages saved in config.log
+if test "$silent" = yes; then
+ exec 6>/dev/null
+else
+ exec 6>&1
+fi
+exec 5>./config.log
+
+echo "\
+This file contains any messages produced by compilers while
+running configure, to aid debugging if configure makes a mistake.
+" 1>&5
+
+# Strip out --no-create and --no-recursion so they do not pile up.
+# Also quote any args containing shell metacharacters.
+ac_configure_args=
+for ac_arg
+do
+ case "$ac_arg" in
+ -no-create | --no-create | --no-creat | --no-crea | --no-cre \
+ | --no-cr | --no-c) ;;
+ -no-recursion | --no-recursion | --no-recursio | --no-recursi \
+ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ;;
+ *" "*|*" "*|*[\[\]\~\#\$\^\&\*\(\)\{\}\\\|\;\<\>\?]*)
+ ac_configure_args="$ac_configure_args '$ac_arg'" ;;
+ *) ac_configure_args="$ac_configure_args $ac_arg" ;;
+ esac
+done
+
+# NLS nuisances.
+# Only set these to C if already set. These must not be set unconditionally
+# because not all systems understand e.g. LANG=C (notably SCO).
+# Fixing LC_MESSAGES prevents Solaris sh from translating var values in `set'!
+# Non-C LC_CTYPE values break the ctype check.
+if test "${LANG+set}" = set; then LANG=C; export LANG; fi
+if test "${LC_ALL+set}" = set; then LC_ALL=C; export LC_ALL; fi
+if test "${LC_MESSAGES+set}" = set; then LC_MESSAGES=C; export LC_MESSAGES; fi
+if test "${LC_CTYPE+set}" = set; then LC_CTYPE=C; export LC_CTYPE; fi
+
+# confdefs.h avoids OS command line length limits that DEFS can exceed.
+rm -rf conftest* confdefs.h
+# AIX cpp loses on an empty file, so make sure it contains at least a newline.
+echo > confdefs.h
+
+# A filename unique to this package, relative to the directory that
+# configure is in, which we can look for to find out if srcdir is correct.
+ac_unique_file=common.c
+
+# Find the source files, if location was not specified.
+if test -z "$srcdir"; then
+ ac_srcdir_defaulted=yes
+ # Try the directory containing this script, then its parent.
+ ac_prog=$0
+ ac_confdir=`echo $ac_prog|sed 's%/[^/][^/]*$%%'`
+ test "x$ac_confdir" = "x$ac_prog" && ac_confdir=.
+ srcdir=$ac_confdir
+ if test ! -r $srcdir/$ac_unique_file; then
+ srcdir=..
+ fi
+else
+ ac_srcdir_defaulted=no
+fi
+if test ! -r $srcdir/$ac_unique_file; then
+ if test "$ac_srcdir_defaulted" = yes; then
+ { echo "configure: error: can not find sources in $ac_confdir or .." 1>&2; exit 1; }
+ else
+ { echo "configure: error: can not find sources in $srcdir" 1>&2; exit 1; }
+ fi
+fi
+srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'`
+
+# Prefer explicitly selected file to automatically selected ones.
+if test -z "$CONFIG_SITE"; then
+ if test "x$prefix" != xNONE; then
+ CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site"
+ else
+ CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site"
+ fi
+fi
+for ac_site_file in $CONFIG_SITE; do
+ if test -r "$ac_site_file"; then
+ echo "loading site script $ac_site_file"
+ . "$ac_site_file"
+ fi
+done
+
+if test -r "$cache_file"; then
+ echo "loading cache $cache_file"
+ . $cache_file
+else
+ echo "creating cache $cache_file"
+ > $cache_file
+fi
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+ac_exeext=
+ac_objext=o
+if (echo "testing\c"; echo 1,2,3) | grep c >/dev/null; then
+ # Stardent Vistra SVR4 grep lacks -e, says ghazi@caip.rutgers.edu.
+ if (echo -n testing; echo 1,2,3) | sed s/-n/xn/ | grep xn >/dev/null; then
+ ac_n= ac_c='
+' ac_t=' '
+ else
+ ac_n=-n ac_c= ac_t=
+ fi
+else
+ ac_n= ac_c='\c' ac_t=
+fi
+
+
+
+
+# Extract the first word of "gcc", so it can be a program name with args.
+set dummy gcc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:530: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_CC="gcc"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+ echo "$ac_t""$CC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+if test -z "$CC"; then
+ # Extract the first word of "cc", so it can be a program name with args.
+set dummy cc; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:560: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_prog_rejected=no
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then
+ ac_prog_rejected=yes
+ continue
+ fi
+ ac_cv_prog_CC="cc"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+if test $ac_prog_rejected = yes; then
+ # We found a bogon in the path, so make sure we never use it.
+ set dummy $ac_cv_prog_CC
+ shift
+ if test $# -gt 0; then
+ # We chose a different compiler from the bogus one.
+ # However, it has the same basename, so the bogon will be chosen
+ # first if we set CC to just the basename; use the full file name.
+ shift
+ set dummy "$ac_dir/$ac_word" "$@"
+ shift
+ ac_cv_prog_CC="$@"
+ fi
+fi
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+ echo "$ac_t""$CC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+ if test -z "$CC"; then
+ case "`uname -s`" in
+ *win32* | *WIN32*)
+ # Extract the first word of "cl", so it can be a program name with args.
+set dummy cl; ac_word=$2
+echo $ac_n "checking for $ac_word""... $ac_c" 1>&6
+echo "configure:611: checking for $ac_word" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ if test -n "$CC"; then
+ ac_cv_prog_CC="$CC" # Let the user override the test.
+else
+ IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":"
+ ac_dummy="$PATH"
+ for ac_dir in $ac_dummy; do
+ test -z "$ac_dir" && ac_dir=.
+ if test -f $ac_dir/$ac_word; then
+ ac_cv_prog_CC="cl"
+ break
+ fi
+ done
+ IFS="$ac_save_ifs"
+fi
+fi
+CC="$ac_cv_prog_CC"
+if test -n "$CC"; then
+ echo "$ac_t""$CC" 1>&6
+else
+ echo "$ac_t""no" 1>&6
+fi
+ ;;
+ esac
+ fi
+ test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; }
+fi
+
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6
+echo "configure:643: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5
+
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+cat > conftest.$ac_ext << EOF
+
+#line 654 "configure"
+#include "confdefs.h"
+
+main(){return(0);}
+EOF
+if { (eval echo configure:659: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ ac_cv_prog_cc_works=yes
+ # If we can't run a trivial program, we are probably using a cross compiler.
+ if (./conftest; exit) 2>/dev/null; then
+ ac_cv_prog_cc_cross=no
+ else
+ ac_cv_prog_cc_cross=yes
+ fi
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ ac_cv_prog_cc_works=no
+fi
+rm -fr conftest*
+ac_ext=c
+# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options.
+ac_cpp='$CPP $CPPFLAGS'
+ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5'
+ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5'
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo "$ac_t""$ac_cv_prog_cc_works" 1>&6
+if test $ac_cv_prog_cc_works = no; then
+ { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; }
+fi
+echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6
+echo "configure:685: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5
+echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6
+cross_compiling=$ac_cv_prog_cc_cross
+
+echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6
+echo "configure:690: checking whether we are using GNU C" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.c <<EOF
+#ifdef __GNUC__
+ yes;
+#endif
+EOF
+if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:699: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then
+ ac_cv_prog_gcc=yes
+else
+ ac_cv_prog_gcc=no
+fi
+fi
+
+echo "$ac_t""$ac_cv_prog_gcc" 1>&6
+
+if test $ac_cv_prog_gcc = yes; then
+ GCC=yes
+else
+ GCC=
+fi
+
+ac_test_CFLAGS="${CFLAGS+set}"
+ac_save_CFLAGS="$CFLAGS"
+CFLAGS=
+echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6
+echo "configure:718: checking whether ${CC-cc} accepts -g" >&5
+if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ echo 'void f(){}' > conftest.c
+if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then
+ ac_cv_prog_cc_g=yes
+else
+ ac_cv_prog_cc_g=no
+fi
+rm -f conftest*
+
+fi
+
+echo "$ac_t""$ac_cv_prog_cc_g" 1>&6
+if test "$ac_test_CFLAGS" = set; then
+ CFLAGS="$ac_save_CFLAGS"
+elif test $ac_cv_prog_cc_g = yes; then
+ if test "$GCC" = yes; then
+ CFLAGS="-g -O2"
+ else
+ CFLAGS="-g"
+ fi
+else
+ if test "$GCC" = yes; then
+ CFLAGS="-O2"
+ else
+ CFLAGS=
+ fi
+fi
+
+
+echo $ac_n "checking for pcap_open_live in -lpcap""... $ac_c" 1>&6
+echo "configure:751: checking for pcap_open_live in -lpcap" >&5
+ac_lib_var=`echo pcap'_'pcap_open_live | sed 'y%./+-%__p_%'`
+if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ ac_save_LIBS="$LIBS"
+LIBS="-lpcap $LIBS"
+cat > conftest.$ac_ext <<EOF
+#line 759 "configure"
+#include "confdefs.h"
+/* Override any gcc2 internal prototype to avoid an error. */
+/* We use char because int might match the return type of a gcc2
+ builtin and then its argument prototype would still apply. */
+char pcap_open_live();
+
+int main() {
+pcap_open_live()
+; return 0; }
+EOF
+if { (eval echo configure:770: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
+ rm -rf conftest*
+ eval "ac_cv_lib_$ac_lib_var=yes"
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_lib_$ac_lib_var=no"
+fi
+rm -f conftest*
+LIBS="$ac_save_LIBS"
+
+fi
+if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_lib=HAVE_LIB`echo pcap | sed -e 's/[^a-zA-Z0-9_]/_/g' \
+ -e 'y/abcdefghijklmnopqrstuvwxyz/ABCDEFGHIJKLMNOPQRSTUVWXYZ/'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_lib 1
+EOF
+
+ LIBS="-lpcap $LIBS"
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+
+
+echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6
+echo "configure:799: checking how to run the C preprocessor" >&5
+# On Suns, sometimes $CPP names a directory.
+if test -n "$CPP" && test -d "$CPP"; then
+ CPP=
+fi
+if test -z "$CPP"; then
+if eval "test \"`echo '$''{'ac_cv_prog_CPP'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ # This must be in double quotes, not single quotes, because CPP may get
+ # substituted into the Makefile and "${CC-cc}" will confuse make.
+ CPP="${CC-cc} -E"
+ # On the NeXT, cc -E runs the code through the compiler's parser,
+ # not just through cpp.
+ cat > conftest.$ac_ext <<EOF
+#line 814 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:820: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ :
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CPP="${CC-cc} -E -traditional-cpp"
+ cat > conftest.$ac_ext <<EOF
+#line 831 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:837: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ :
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CPP="${CC-cc} -nologo -E"
+ cat > conftest.$ac_ext <<EOF
+#line 848 "configure"
+#include "confdefs.h"
+#include <assert.h>
+Syntax Error
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:854: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ :
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ CPP=/lib/cpp
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+fi
+rm -f conftest*
+ ac_cv_prog_CPP="$CPP"
+fi
+ CPP="$ac_cv_prog_CPP"
+else
+ ac_cv_prog_CPP="$CPP"
+fi
+echo "$ac_t""$CPP" 1>&6
+
+echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6
+echo "configure:879: checking for ANSI C header files" >&5
+if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 884 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+#include <stdarg.h>
+#include <string.h>
+#include <float.h>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:892: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ ac_cv_header_stdc=yes
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+if test $ac_cv_header_stdc = yes; then
+ # SunOS 4.x string.h does not declare mem*, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 909 "configure"
+#include "confdefs.h"
+#include <string.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ egrep "memchr" >/dev/null 2>&1; then
+ :
+else
+ rm -rf conftest*
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI.
+cat > conftest.$ac_ext <<EOF
+#line 927 "configure"
+#include "confdefs.h"
+#include <stdlib.h>
+EOF
+if (eval "$ac_cpp conftest.$ac_ext") 2>&5 |
+ egrep "free" >/dev/null 2>&1; then
+ :
+else
+ rm -rf conftest*
+ ac_cv_header_stdc=no
+fi
+rm -f conftest*
+
+fi
+
+if test $ac_cv_header_stdc = yes; then
+ # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi.
+if test "$cross_compiling" = yes; then
+ :
+else
+ cat > conftest.$ac_ext <<EOF
+#line 948 "configure"
+#include "confdefs.h"
+#include <ctype.h>
+#define ISLOWER(c) ('a' <= (c) && (c) <= 'z')
+#define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c))
+#define XOR(e, f) (((e) && !(f)) || (!(e) && (f)))
+int main () { int i; for (i = 0; i < 256; i++)
+if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2);
+exit (0); }
+
+EOF
+if { (eval echo configure:959: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null
+then
+ :
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -fr conftest*
+ ac_cv_header_stdc=no
+fi
+rm -fr conftest*
+fi
+
+fi
+fi
+
+echo "$ac_t""$ac_cv_header_stdc" 1>&6
+if test $ac_cv_header_stdc = yes; then
+ cat >> confdefs.h <<\EOF
+#define STDC_HEADERS 1
+EOF
+
+fi
+
+for ac_hdr in termios.h sys/ioctl.h net/if.h netinet/in.h netinet/in_systm.h netinet/ip.h netinet/udp.h netinet/tcp.h netdb.h arpa/inet.h sys/socket.h fcntl.h linux/if_ether.h signal.h string.h stdlib.h stdio.h sys/time.h unistd.h sys/stat.h sys/types.h errno.h linux/sockios.h ctype.h sys/socket.h pcap/pcap.h
+do
+ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
+echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
+echo "configure:986: checking for $ac_hdr" >&5
+if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 991 "configure"
+#include "confdefs.h"
+#include <$ac_hdr>
+EOF
+ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
+{ (eval echo configure:996: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
+ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
+if test -z "$ac_err"; then
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=yes"
+else
+ echo "$ac_err" >&5
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ eval "ac_cv_header_$ac_safe=no"
+fi
+rm -f conftest*
+fi
+if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then
+ echo "$ac_t""yes" 1>&6
+ ac_tr_hdr=HAVE_`echo $ac_hdr | sed 'y%abcdefghijklmnopqrstuvwxyz./-%ABCDEFGHIJKLMNOPQRSTUVWXYZ___%'`
+ cat >> confdefs.h <<EOF
+#define $ac_tr_hdr 1
+EOF
+
+else
+ echo "$ac_t""no" 1>&6
+fi
+done
+
+
+echo $ac_n "checking whether time.h and sys/time.h may both be included""... $ac_c" 1>&6
+echo "configure:1024: checking whether time.h and sys/time.h may both be included" >&5
+if eval "test \"`echo '$''{'ac_cv_header_time'+set}'`\" = set"; then
+ echo $ac_n "(cached) $ac_c" 1>&6
+else
+ cat > conftest.$ac_ext <<EOF
+#line 1029 "configure"
+#include "confdefs.h"
+#include <sys/types.h>
+#include <sys/time.h>
+#include <time.h>
+int main() {
+struct tm *tp;
+; return 0; }
+EOF
+if { (eval echo configure:1038: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then
+ rm -rf conftest*
+ ac_cv_header_time=yes
+else
+ echo "configure: failed program was:" >&5
+ cat conftest.$ac_ext >&5
+ rm -rf conftest*
+ ac_cv_header_time=no
+fi
+rm -f conftest*
+fi
+
+echo "$ac_t""$ac_cv_header_time" 1>&6
+if test $ac_cv_header_time = yes; then
+ cat >> confdefs.h <<\EOF
+#define TIME_WITH_SYS_TIME 1
+EOF
+
+fi
+
+
+trap '' 1 2 15
+cat > confcache <<\EOF
+# This file is a shell script that caches the results of configure
+# tests run on this system so they can be shared between configure
+# scripts and configure runs. It is not useful on other systems.
+# If it contains results you don't want to keep, you may remove or edit it.
+#
+# By default, configure uses ./config.cache as the cache file,
+# creating it if it does not exist already. You can give configure
+# the --cache-file=FILE option to use a different cache file; that is
+# what configure does when it calls configure scripts in
+# subdirectories, so they share the cache.
+# Giving --cache-file=/dev/null disables caching, for debugging configure.
+# config.status only pays attention to the cache file if you give it the
+# --recheck option to rerun configure.
+#
+EOF
+# The following way of writing the cache mishandles newlines in values,
+# but we know of no workaround that is simple, portable, and efficient.
+# So, don't put newlines in cache variables' values.
+# Ultrix sh set writes to stderr and can't be redirected directly,
+# and sets the high bit in the cache file unless we assign to the vars.
+(set) 2>&1 |
+ case `(ac_space=' '; set | grep ac_space) 2>&1` in
+ *ac_space=\ *)
+ # `set' does not quote correctly, so add quotes (double-quote substitution
+ # turns \\\\ into \\, and sed turns \\ into \).
+ sed -n \
+ -e "s/'/'\\\\''/g" \
+ -e "s/^\\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\\)=\\(.*\\)/\\1=\${\\1='\\2'}/p"
+ ;;
+ *)
+ # `set' quotes correctly as required by POSIX, so do not add quotes.
+ sed -n -e 's/^\([a-zA-Z0-9_]*_cv_[a-zA-Z0-9_]*\)=\(.*\)/\1=${\1=\2}/p'
+ ;;
+ esac >> confcache
+if cmp -s $cache_file confcache; then
+ :
+else
+ if test -w $cache_file; then
+ echo "updating cache $cache_file"
+ cat confcache > $cache_file
+ else
+ echo "not updating unwritable cache $cache_file"
+ fi
+fi
+rm -f confcache
+
+trap 'rm -fr conftest* confdefs* core core.* *.core $ac_clean_files; exit 1' 1 2 15
+
+test "x$prefix" = xNONE && prefix=$ac_default_prefix
+# Let make expand exec_prefix.
+test "x$exec_prefix" = xNONE && exec_prefix='${prefix}'
+
+# Any assignment to VPATH causes Sun make to only execute
+# the first set of double-colon rules, so remove it if not needed.
+# If there is a colon in the path, we need to keep it.
+if test "x$srcdir" = x.; then
+ ac_vpsub='/^[ ]*VPATH[ ]*=[^:]*$/d'
+fi
+
+trap 'rm -f $CONFIG_STATUS conftest*; exit 1' 1 2 15
+
+DEFS=-DHAVE_CONFIG_H
+
+# Without the "./", some shells look in PATH for config.status.
+: ${CONFIG_STATUS=./config.status}
+
+echo creating $CONFIG_STATUS
+rm -f $CONFIG_STATUS
+cat > $CONFIG_STATUS <<EOF
+#! /bin/sh
+# Generated automatically by configure.
+# Run this file to recreate the current configuration.
+# This directory was configured as follows,
+# on host `(hostname || uname -n) 2>/dev/null | sed 1q`:
+#
+# $0 $ac_configure_args
+#
+# Compiler output produced by configure, useful for debugging
+# configure, is in ./config.log if it exists.
+
+ac_cs_usage="Usage: $CONFIG_STATUS [--recheck] [--version] [--help]"
+for ac_option
+do
+ case "\$ac_option" in
+ -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r)
+ echo "running \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion"
+ exec \${CONFIG_SHELL-/bin/sh} $0 $ac_configure_args --no-create --no-recursion ;;
+ -version | --version | --versio | --versi | --vers | --ver | --ve | --v)
+ echo "$CONFIG_STATUS generated by autoconf version 2.13"
+ exit 0 ;;
+ -help | --help | --hel | --he | --h)
+ echo "\$ac_cs_usage"; exit 0 ;;
+ *) echo "\$ac_cs_usage"; exit 1 ;;
+ esac
+done
+
+ac_given_srcdir=$srcdir
+
+trap 'rm -fr `echo "Makefile conf.h" | sed "s/:[^ ]*//g"` conftest*; exit 1' 1 2 15
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+# Protect against being on the right side of a sed subst in config.status.
+sed 's/%@/@@/; s/@%/@@/; s/%g\$/@g/; /@g\$/s/[\\\\&%]/\\\\&/g;
+ s/@@/%@/; s/@@/@%/; s/@g\$/%g/' > conftest.subs <<\\CEOF
+$ac_vpsub
+$extrasub
+s%@SHELL@%$SHELL%g
+s%@CFLAGS@%$CFLAGS%g
+s%@CPPFLAGS@%$CPPFLAGS%g
+s%@CXXFLAGS@%$CXXFLAGS%g
+s%@FFLAGS@%$FFLAGS%g
+s%@DEFS@%$DEFS%g
+s%@LDFLAGS@%$LDFLAGS%g
+s%@LIBS@%$LIBS%g
+s%@exec_prefix@%$exec_prefix%g
+s%@prefix@%$prefix%g
+s%@program_transform_name@%$program_transform_name%g
+s%@bindir@%$bindir%g
+s%@sbindir@%$sbindir%g
+s%@libexecdir@%$libexecdir%g
+s%@datadir@%$datadir%g
+s%@sysconfdir@%$sysconfdir%g
+s%@sharedstatedir@%$sharedstatedir%g
+s%@localstatedir@%$localstatedir%g
+s%@libdir@%$libdir%g
+s%@includedir@%$includedir%g
+s%@oldincludedir@%$oldincludedir%g
+s%@infodir@%$infodir%g
+s%@mandir@%$mandir%g
+s%@CC@%$CC%g
+s%@CPP@%$CPP%g
+
+CEOF
+EOF
+
+cat >> $CONFIG_STATUS <<\EOF
+
+# Split the substitutions into bite-sized pieces for seds with
+# small command number limits, like on Digital OSF/1 and HP-UX.
+ac_max_sed_cmds=90 # Maximum number of lines to put in a sed script.
+ac_file=1 # Number of current file.
+ac_beg=1 # First line for current file.
+ac_end=$ac_max_sed_cmds # Line after last line for current file.
+ac_more_lines=:
+ac_sed_cmds=""
+while $ac_more_lines; do
+ if test $ac_beg -gt 1; then
+ sed "1,${ac_beg}d; ${ac_end}q" conftest.subs > conftest.s$ac_file
+ else
+ sed "${ac_end}q" conftest.subs > conftest.s$ac_file
+ fi
+ if test ! -s conftest.s$ac_file; then
+ ac_more_lines=false
+ rm -f conftest.s$ac_file
+ else
+ if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds="sed -f conftest.s$ac_file"
+ else
+ ac_sed_cmds="$ac_sed_cmds | sed -f conftest.s$ac_file"
+ fi
+ ac_file=`expr $ac_file + 1`
+ ac_beg=$ac_end
+ ac_end=`expr $ac_end + $ac_max_sed_cmds`
+ fi
+done
+if test -z "$ac_sed_cmds"; then
+ ac_sed_cmds=cat
+fi
+EOF
+
+cat >> $CONFIG_STATUS <<EOF
+
+CONFIG_FILES=\${CONFIG_FILES-"Makefile"}
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+for ac_file in .. $CONFIG_FILES; do if test "x$ac_file" != x..; then
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case "$ac_file" in
+ *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+ ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+ *) ac_file_in="${ac_file}.in" ;;
+ esac
+
+ # Adjust a relative srcdir, top_srcdir, and INSTALL for subdirectories.
+
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+ # The file is in a subdirectory.
+ test ! -d "$ac_dir" && mkdir "$ac_dir"
+ ac_dir_suffix="/`echo $ac_dir|sed 's%^\./%%'`"
+ # A "../" for each directory in $ac_dir_suffix.
+ ac_dots=`echo $ac_dir_suffix|sed 's%/[^/]*%../%g'`
+ else
+ ac_dir_suffix= ac_dots=
+ fi
+
+ case "$ac_given_srcdir" in
+ .) srcdir=.
+ if test -z "$ac_dots"; then top_srcdir=.
+ else top_srcdir=`echo $ac_dots|sed 's%/$%%'`; fi ;;
+ /*) srcdir="$ac_given_srcdir$ac_dir_suffix"; top_srcdir="$ac_given_srcdir" ;;
+ *) # Relative path.
+ srcdir="$ac_dots$ac_given_srcdir$ac_dir_suffix"
+ top_srcdir="$ac_dots$ac_given_srcdir" ;;
+ esac
+
+
+ echo creating "$ac_file"
+ rm -f "$ac_file"
+ configure_input="Generated automatically from `echo $ac_file_in|sed 's%.*/%%'` by configure."
+ case "$ac_file" in
+ *Makefile*) ac_comsub="1i\\
+# $configure_input" ;;
+ *) ac_comsub= ;;
+ esac
+
+ ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+ sed -e "$ac_comsub
+s%@configure_input@%$configure_input%g
+s%@srcdir@%$srcdir%g
+s%@top_srcdir@%$top_srcdir%g
+" $ac_file_inputs | (eval "$ac_sed_cmds") > $ac_file
+fi; done
+rm -f conftest.s*
+
+# These sed commands are passed to sed as "A NAME B NAME C VALUE D", where
+# NAME is the cpp macro being defined and VALUE is the value it is being given.
+#
+# ac_d sets the value in "#define NAME VALUE" lines.
+ac_dA='s%^\([ ]*\)#\([ ]*define[ ][ ]*\)'
+ac_dB='\([ ][ ]*\)[^ ]*%\1#\2'
+ac_dC='\3'
+ac_dD='%g'
+# ac_u turns "#undef NAME" with trailing blanks into "#define NAME VALUE".
+ac_uA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)'
+ac_uB='\([ ]\)%\1#\2define\3'
+ac_uC=' '
+ac_uD='\4%g'
+# ac_e turns "#undef NAME" without trailing blanks into "#define NAME VALUE".
+ac_eA='s%^\([ ]*\)#\([ ]*\)undef\([ ][ ]*\)'
+ac_eB='$%\1#\2define\3'
+ac_eC=' '
+ac_eD='%g'
+
+if test "${CONFIG_HEADERS+set}" != set; then
+EOF
+cat >> $CONFIG_STATUS <<EOF
+ CONFIG_HEADERS="conf.h"
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+fi
+for ac_file in .. $CONFIG_HEADERS; do if test "x$ac_file" != x..; then
+ # Support "outfile[:infile[:infile...]]", defaulting infile="outfile.in".
+ case "$ac_file" in
+ *:*) ac_file_in=`echo "$ac_file"|sed 's%[^:]*:%%'`
+ ac_file=`echo "$ac_file"|sed 's%:.*%%'` ;;
+ *) ac_file_in="${ac_file}.in" ;;
+ esac
+
+ echo creating $ac_file
+
+ rm -f conftest.frag conftest.in conftest.out
+ ac_file_inputs=`echo $ac_file_in|sed -e "s%^%$ac_given_srcdir/%" -e "s%:% $ac_given_srcdir/%g"`
+ cat $ac_file_inputs > conftest.in
+
+EOF
+
+# Transform confdefs.h into a sed script conftest.vals that substitutes
+# the proper values into config.h.in to produce config.h. And first:
+# Protect against being on the right side of a sed subst in config.status.
+# Protect against being in an unquoted here document in config.status.
+rm -f conftest.vals
+cat > conftest.hdr <<\EOF
+s/[\\&%]/\\&/g
+s%[\\$`]%\\&%g
+s%#define \([A-Za-z_][A-Za-z0-9_]*\) *\(.*\)%${ac_dA}\1${ac_dB}\1${ac_dC}\2${ac_dD}%gp
+s%ac_d%ac_u%gp
+s%ac_u%ac_e%gp
+EOF
+sed -n -f conftest.hdr confdefs.h > conftest.vals
+rm -f conftest.hdr
+
+# This sed command replaces #undef with comments. This is necessary, for
+# example, in the case of _POSIX_SOURCE, which is predefined and required
+# on some systems where configure will not decide to define it.
+cat >> conftest.vals <<\EOF
+s%^[ ]*#[ ]*undef[ ][ ]*[a-zA-Z_][a-zA-Z_0-9]*%/* & */%
+EOF
+
+# Break up conftest.vals because some shells have a limit on
+# the size of here documents, and old seds have small limits too.
+
+rm -f conftest.tail
+while :
+do
+ ac_lines=`grep -c . conftest.vals`
+ # grep -c gives empty output for an empty file on some AIX systems.
+ if test -z "$ac_lines" || test "$ac_lines" -eq 0; then break; fi
+ # Write a limited-size here document to conftest.frag.
+ echo ' cat > conftest.frag <<CEOF' >> $CONFIG_STATUS
+ sed ${ac_max_here_lines}q conftest.vals >> $CONFIG_STATUS
+ echo 'CEOF
+ sed -f conftest.frag conftest.in > conftest.out
+ rm -f conftest.in
+ mv conftest.out conftest.in
+' >> $CONFIG_STATUS
+ sed 1,${ac_max_here_lines}d conftest.vals > conftest.tail
+ rm -f conftest.vals
+ mv conftest.tail conftest.vals
+done
+rm -f conftest.vals
+
+cat >> $CONFIG_STATUS <<\EOF
+ rm -f conftest.frag conftest.h
+ echo "/* $ac_file. Generated automatically by configure. */" > conftest.h
+ cat conftest.in >> conftest.h
+ rm -f conftest.in
+ if cmp -s $ac_file conftest.h 2>/dev/null; then
+ echo "$ac_file is unchanged"
+ rm -f conftest.h
+ else
+ # Remove last slash and all that follows it. Not all systems have dirname.
+ ac_dir=`echo $ac_file|sed 's%/[^/][^/]*$%%'`
+ if test "$ac_dir" != "$ac_file" && test "$ac_dir" != .; then
+ # The file is in a subdirectory.
+ test ! -d "$ac_dir" && mkdir "$ac_dir"
+ fi
+ rm -f $ac_file
+ mv conftest.h $ac_file
+ fi
+fi; done
+
+EOF
+cat >> $CONFIG_STATUS <<EOF
+
+EOF
+cat >> $CONFIG_STATUS <<\EOF
+
+exit 0
+EOF
+chmod +x $CONFIG_STATUS
+rm -fr confdefs* $ac_clean_files
+test "$no_create" = yes || ${CONFIG_SHELL-/bin/sh} $CONFIG_STATUS || exit 1
+
diff --git a/package/etrax-tools/src/e100boot/sbl/configure.in b/package/etrax-tools/src/e100boot/sbl/configure.in
new file mode 100644
index 000000000..24e161c50
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/configure.in
@@ -0,0 +1,19 @@
+dnl Process this file with autoconf to produce a configure script.
+AC_INIT(common.c)
+AC_CONFIG_HEADER(conf.h)
+
+dnl Checks for programs.
+AC_PROG_CC
+
+dnl Checks for libraries.
+AC_CHECK_LIB(pcap, pcap_open_live)
+
+dnl Checks for header files.
+AC_HEADER_STDC
+AC_CHECK_HEADERS(termios.h sys/ioctl.h net/if.h netinet/in.h netinet/in_systm.h netinet/ip.h netinet/udp.h netinet/tcp.h netdb.h arpa/inet.h sys/socket.h fcntl.h linux/if_ether.h signal.h string.h stdlib.h stdio.h sys/time.h unistd.h sys/stat.h sys/types.h errno.h linux/sockios.h ctype.h sys/socket.h pcap/pcap.h)
+
+dnl Check for typedefs, structures, and compiler characteristics.
+AC_HEADER_TIME
+
+dnl Checks for library functions.
+AC_OUTPUT(Makefile)
diff --git a/package/etrax-tools/src/e100boot/sbl/create_regs.pl b/package/etrax-tools/src/e100boot/sbl/create_regs.pl
new file mode 100755
index 000000000..5127538b7
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/create_regs.pl
@@ -0,0 +1,14 @@
+#!/usr/bin/perl
+
+print "struct reg_des {
+ char *name;
+ unsigned int addr;
+} reg_des[] = {\n";
+while(<>) {
+ if (/define+ (\w+) .*IO_TYPECAST+.*DWORD.*\s+(\w+)/) {
+ print " \"$1\", $2,\n";
+ }
+}
+ print " NULL, 0
+};
+";
diff --git a/package/etrax-tools/src/e100boot/sbl/net_ima.c b/package/etrax-tools/src/e100boot/sbl/net_ima.c
new file mode 100644
index 000000000..749fe1ef8
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/net_ima.c
@@ -0,0 +1,891 @@
+
+/* cconv 1.2 12/16/97, Copyright (C) 1997, Axis Communications AB */
+
+const char net_ima[] =
+{
+ '\x0f', '\x05', '\x0f', '\x05', '\x6f', '\xee', '\x00', '\x1f',
+ '\x00', '\x38', '\x3f', '\x0d', '\x08', '\x01', '\x00', '\x38',
+ '\x78', '\x56', '\x34', '\x12', '\x21', '\x43', '\x65', '\x87',
+ '\x6f', '\xde', '\x20', '\x00', '\x00', '\xb0', '\x5f', '\x9c',
+ '\x65', '\x6f', '\xed', '\x9b', '\x5f', '\x9c', '\x25', '\x2f',
+ '\x7f', '\x0d', '\x80', '\x18', '\x00', '\x38', '\xe9', '\x9b',
+ '\xed', '\x9b', '\x3f', '\x0d', '\x28', '\x01', '\x00', '\x38',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x7e', '\x92', '\x7f', '\x0d',
+ '\x31', '\x00', '\x00', '\xb0', '\xc9', '\x9b', '\x7f', '\x0d',
+ '\x30', '\x00', '\x00', '\xb0', '\x70', '\x0a', '\x7f', '\x92',
+ '\x7f', '\x0d', '\x80', '\x18', '\x00', '\x38', '\xc9', '\x9b',
+ '\x7f', '\x0d', '\x39', '\x00', '\x00', '\xb0', '\xc9', '\x9b',
+ '\x7f', '\x0d', '\x38', '\x00', '\x00', '\xb0', '\xc9', '\x9b',
+ '\x7f', '\x0d', '\x22', '\x1d', '\x00', '\x38', '\x70', '\x8a',
+ '\x6f', '\x9e', '\x20', '\x00', '\x00', '\xb0', '\x69', '\x9a',
+ '\x79', '\x67', '\x7f', '\x0d', '\xd6', '\x1c', '\x00', '\x38',
+ '\xe9', '\x9b', '\x6f', '\x9e', '\x22', '\x00', '\x00', '\xb0',
+ '\x59', '\x9a', '\x59', '\x94', '\x7f', '\x0d', '\x3e', '\x1d',
+ '\x00', '\x38', '\xe9', '\x9b', '\x6f', '\x9e', '\x04', '\x00',
+ '\x00', '\xb0', '\x69', '\x9a', '\x06', '\x93', '\xe1', '\x93',
+ '\x81', '\x92', '\x7f', '\x0d', '\x26', '\x1d', '\x00', '\x38',
+ '\xc9', '\x9b', '\x7f', '\x0d', '\xe8', '\x1c', '\x00', '\x38',
+ '\x70', '\x4a', '\x3f', '\xbd', '\x68', '\x02', '\x00', '\x38',
+ '\x3f', '\xbd', '\x70', '\x04', '\x00', '\x38', '\x3f', '\xbd',
+ '\x0c', '\x02', '\x00', '\x38', '\x6a', '\xa6', '\xf7', '\x30',
+ '\x0f', '\x05', '\x6f', '\x9e', '\x00', '\x01', '\x00', '\x38',
+ '\x69', '\x9a', '\x7f', '\x0d', '\x22', '\x1d', '\x00', '\x38',
+ '\xe9', '\x9a', '\x24', '\x80', '\x0f', '\x05', '\x6f', '\x9e',
+ '\x26', '\x1d', '\x00', '\x38', '\x49', '\x9a', '\xcf', '\x9e',
+ '\x01', '\x00', '\xd3', '\x20', '\x0f', '\x05', '\x6f', '\xde',
+ '\xd4', '\x01', '\x00', '\xb0', '\x4d', '\x9a', '\x38', '\x93',
+ '\x41', '\x93', '\xcd', '\x9b', '\xc1', '\xe0', '\x0f', '\x05',
+ '\x4f', '\x9e', '\x55', '\x00', '\x7f', '\x0d', '\x80', '\x18',
+ '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\x0d', '\x30', '\x00',
+ '\x00', '\xb0', '\xc9', '\x9b', '\x3e', '\xbe', '\x3f', '\x0d',
+ '\xc0', '\x05', '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x3f', '\xbd', '\xa2', '\x03', '\x00', '\x38', '\x6a', '\xa6',
+ '\x16', '\x20', '\x41', '\x92', '\x3f', '\xbd', '\x34', '\x02',
+ '\x00', '\x38', '\x6a', '\xa6', '\x0a', '\x30', '\x79', '\x86',
+ '\x3f', '\xbd', '\x70', '\x04', '\x00', '\x38', '\x79', '\x86',
+ '\x69', '\xa6', '\x3e', '\x0d', '\x84', '\xe2', '\x6f', '\x9e',
+ '\x22', '\x00', '\x00', '\xb0', '\x59', '\x9a', '\x59', '\x94',
+ '\xee', '\x9b', '\x6f', '\xce', '\x3e', '\x1d', '\x00', '\x38',
+ '\x6c', '\x9a', '\x6e', '\xda', '\xad', '\x96', '\xb9', '\x96',
+ '\xdf', '\x9c', '\x80', '\x25', '\x0a', '\xd0', '\x0f', '\x05',
+ '\x6e', '\x9a', '\xec', '\x9b', '\x04', '\xe0', '\x41', '\xa2',
+ '\x7a', '\x86', '\x7f', '\xb6', '\x04', '\xe2', '\x00', '\x00',
+ '\x88', '\xe2', '\xfe', '\x1b', '\x6f', '\x9e', '\x8c', '\x00',
+ '\x00', '\xb0', '\x79', '\x8a', '\x69', '\x9a', '\x7f', '\x0d',
+ '\x90', '\x00', '\x00', '\xb0', '\xe9', '\x9b', '\x6f', '\x9e',
+ '\x01', '\x40', '\x8c', '\x00', '\x7f', '\x0d', '\x80', '\x00',
+ '\x00', '\xb0', '\xe9', '\x9b', '\x6f', '\xce', '\x01', '\x00',
+ '\x01', '\x40', '\x7f', '\x0d', '\x84', '\x00', '\x00', '\xb0',
+ '\xec', '\xcb', '\x6f', '\xde', '\x8c', '\x00', '\x01', '\x00',
+ '\x7f', '\x0d', '\x88', '\x00', '\x00', '\xb0', '\xed', '\xdb',
+ '\x41', '\x12', '\x7f', '\x0d', '\x94', '\x00', '\x00', '\xb0',
+ '\xe1', '\x1b', '\x7f', '\x0d', '\xa0', '\x00', '\x00', '\xb0',
+ '\x70', '\x8a', '\x5f', '\x9c', '\x02', '\x01', '\x7f', '\x0d',
+ '\x9c', '\x00', '\x00', '\xb0', '\xe9', '\x9b', '\x43', '\xc2',
+ '\x7f', '\x0d', '\x98', '\x00', '\x00', '\xb0', '\xec', '\xcb',
+ '\x44', '\xd2', '\x7f', '\x0d', '\xd0', '\x01', '\x00', '\xb0',
+ '\xcd', '\xdb', '\x6f', '\x0e', '\xd4', '\x01', '\x00', '\xb0',
+ '\xc0', '\xdb', '\x6f', '\xbe', '\xa4', '\x1c', '\x00', '\x38',
+ '\x6b', '\x96', '\x4f', '\xcc', '\x26', '\x00', '\xd9', '\xcf',
+ '\x79', '\x4a', '\x6f', '\xde', '\xda', '\x1c', '\x00', '\x38',
+ '\x04', '\xb1', '\xed', '\xdb', '\x6f', '\x9e', '\xfc', '\x1c',
+ '\x00', '\x38', '\x08', '\xb1', '\xe9', '\x9b', '\x6d', '\x96',
+ '\x5f', '\xce', '\xdc', '\x05', '\xd9', '\xcf', '\x47', '\xc2',
+ '\xd9', '\xcb', '\x6f', '\x9e', '\x04', '\x01', '\x00', '\x38',
+ '\x69', '\x9a', '\x08', '\xd1', '\xe9', '\x9b', '\x6f', '\xce',
+ '\xba', '\x1c', '\x00', '\x38', '\x6f', '\x9e', '\x00', '\x8c',
+ '\x40', '\x02', '\x79', '\x67', '\x6c', '\xd6', '\xed', '\x9f',
+ '\x5f', '\x9e', '\x00', '\x01', '\x79', '\x27', '\xdd', '\x9b',
+ '\x6c', '\xa6', '\x86', '\xa2', '\x4f', '\x9c', '\x40', '\x00',
+ '\x79', '\x27', '\x06', '\xc1', '\xd9', '\x9b', '\x6f', '\x9e',
+ '\x00', '\x03', '\xaa', '\xaa', '\x79', '\x67', '\x08', '\xc1',
+ '\xe9', '\x9b', '\x6f', '\x9e', '\x56', '\x88', '\x8c', '\x40',
+ '\x79', '\x67', '\x0c', '\xc1', '\xe9', '\x9b', '\x7e', '\x92',
+ '\x79', '\x67', '\x10', '\xc1', '\xe9', '\x9b', '\x14', '\xc1',
+ '\x70', '\x8a', '\x18', '\xc1', '\x70', '\x8a', '\x6f', '\xde',
+ '\x2e', '\x1d', '\x00', '\x38', '\x6d', '\x96', '\x4f', '\xcc',
+ '\x26', '\x00', '\xd9', '\xcf', '\x47', '\xc2', '\xd9', '\xcb',
+ '\x08', '\xd1', '\xea', '\xab', '\x7f', '\x0d', '\xea', '\x1c',
+ '\x00', '\x38', '\x70', '\x0a', '\x7f', '\x0d', '\x2a', '\x1d',
+ '\x00', '\x38', '\x70', '\x8a', '\x7f', '\x0d', '\xa4', '\x01',
+ '\x00', '\xb0', '\xeb', '\xbb', '\xc0', '\x1b', '\x7f', '\xb6',
+ '\xbe', '\x1f', '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2',
+ '\xfe', '\x0b', '\x6f', '\x0e', '\xda', '\x1c', '\x00', '\x38',
+ '\x0e', '\x01', '\x5d', '\x9e', '\x81', '\x93', '\xb4', '\xa0',
+ '\x7a', '\x86', '\x7d', '\x4a', '\x6f', '\x9e', '\xa4', '\x1c',
+ '\x00', '\x38', '\x7f', '\x0d', '\xa4', '\x01', '\x00', '\xb0',
+ '\xe9', '\x9b', '\x6f', '\xde', '\x16', '\x1d', '\x00', '\x38',
+ '\x6d', '\xda', '\x7d', '\x67', '\x6f', '\x9e', '\x2a', '\x1d',
+ '\x00', '\x38', '\x69', '\x9a', '\x01', '\x92', '\xe9', '\xd6',
+ '\x8a', '\x20', '\x41', '\xa2', '\x41', '\x92', '\x7f', '\x0d',
+ '\x26', '\x1d', '\x00', '\x38', '\xc9', '\x9b', '\x6f', '\x9e',
+ '\x20', '\x00', '\x00', '\xb0', '\x69', '\x9a', '\xf0', '\x93',
+ '\x7f', '\x0d', '\x3e', '\x1d', '\x00', '\x38', '\xe9', '\x9b',
+ '\x6f', '\xae', '\x22', '\x1d', '\x00', '\x38', '\x0c', '\x01',
+ '\x5b', '\xb8', '\x6a', '\xda', '\x2b', '\xd6', '\x84', '\xd2',
+ '\xea', '\xdb', '\x08', '\x01', '\x6c', '\x9e', '\x2b', '\x96',
+ '\x84', '\x92', '\xec', '\x9b', '\x60', '\xc6', '\x6f', '\xbe',
+ '\x00', '\x01', '\x00', '\x38', '\x6b', '\x9a', '\xad', '\x96',
+ '\x84', '\x92', '\xdf', '\x9c', '\xdb', '\x05', '\x0a', '\x90',
+ '\x0f', '\x05', '\x6b', '\x9a', '\x9a', '\x9a', '\x06', '\xe0',
+ '\x04', '\x92', '\x5f', '\x9e', '\xdc', '\x05', '\xdc', '\x9b',
+ '\x6f', '\xce', '\xda', '\x1c', '\x00', '\x38', '\x5c', '\xda',
+ '\x5d', '\x94', '\x26', '\x92', '\xcf', '\x9c', '\x3f', '\x00',
+ '\x04', '\x90', '\x0f', '\x05', '\x5a', '\xd2', '\xdc', '\xdb',
+ '\x6f', '\xde', '\x2a', '\x1d', '\x00', '\x38', '\x6d', '\x9a',
+ '\x01', '\x92', '\xed', '\x9b', '\x3f', '\xbd', '\x70', '\x04',
+ '\x00', '\x38', '\x41', '\xa2', '\xbe', '\x0f', '\x3e', '\x0d',
+ '\x6f', '\x9e', '\xea', '\x1c', '\x00', '\x38', '\x89', '\x0b',
+ '\x44', '\x20', '\x41', '\xc2', '\xc9', '\xcb', '\x6f', '\x9e',
+ '\x04', '\x00', '\x00', '\xb0', '\x69', '\x9a', '\x06', '\x93',
+ '\xc4', '\x92', '\x1e', '\x20', '\x0f', '\x05', '\x6f', '\x9e',
+ '\xb4', '\x1c', '\x00', '\x38', '\x6f', '\xde', '\xdc', '\x00',
+ '\x00', '\x38', '\x6d', '\xda', '\xe9', '\xdf', '\x6f', '\xce',
+ '\xe0', '\x00', '\x00', '\x38', '\x5c', '\xca', '\x16', '\xe0',
+ '\xd9', '\xcb', '\x6f', '\xde', '\xb4', '\x1c', '\x00', '\x38',
+ '\x6f', '\x9e', '\x02', '\x1d', '\x00', '\x38', '\x69', '\xce',
+ '\xed', '\xcf', '\x59', '\x9a', '\xdd', '\x9b', '\x6f', '\xde',
+ '\xb4', '\x1c', '\x00', '\x38', '\x6f', '\x9e', '\x2a', '\x1d',
+ '\x00', '\x38', '\x69', '\x9a', '\x79', '\x67', '\x1a', '\xd1',
+ '\xe9', '\x9b', '\x42', '\x92', '\x79', '\x67', '\x1e', '\xd1',
+ '\xe9', '\x9b', '\x6f', '\x9e', '\x2e', '\x1d', '\x00', '\x38',
+ '\x47', '\xd2', '\x02', '\x91', '\xdd', '\xdb', '\x4f', '\xcc',
+ '\x26', '\x00', '\xd9', '\xcb', '\x3f', '\x0d', '\xf2', '\x04',
+ '\x00', '\x38', '\x6f', '\x9e', '\x2e', '\x1d', '\x00', '\x38',
+ '\x7f', '\x0d', '\xa0', '\x01', '\x00', '\xb0', '\xe9', '\x9b',
+ '\x41', '\x92', '\x7f', '\x0d', '\xd0', '\x01', '\x00', '\xb0',
+ '\xc9', '\x9b', '\x6f', '\x9e', '\xa0', '\x01', '\x00', '\xb0',
+ '\x69', '\x9a', '\xf7', '\x20', '\x0f', '\x05', '\x7f', '\xb6',
+ '\x0f', '\x05', '\x6f', '\x9e', '\x2e', '\x1d', '\x00', '\x38',
+ '\x6f', '\xce', '\xec', '\x1c', '\x00', '\x38', '\x04', '\x91',
+ '\xec', '\xcb', '\x02', '\x91', '\x70', '\x4a', '\x8a', '\x0b',
+ '\x0c', '\x30', '\x7d', '\x86', '\x01', '\xd2', '\x4a', '\xd5',
+ '\x80', '\x0b', '\xf9', '\x20', '\x0f', '\x05', '\x7f', '\x0d',
+ '\xd2', '\x1c', '\x00', '\x38', '\x70', '\x8a', '\x6f', '\x9e',
+ '\xec', '\x1c', '\x00', '\x38', '\x47', '\xc2', '\x02', '\x91',
+ '\xdc', '\xcb', '\x08', '\x91', '\xea', '\xab', '\x01', '\xd2',
+ '\xd9', '\xdb', '\x3f', '\x0d', '\xf2', '\x04', '\x00', '\x38',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2', '\xee', '\xab',
+ '\x6f', '\x9e', '\x2e', '\x1d', '\x00', '\x38', '\x6f', '\xde',
+ '\xec', '\x1c', '\x00', '\x38', '\x04', '\x91', '\xed', '\xdb',
+ '\x02', '\x91', '\x70', '\x4a', '\x4b', '\xb6', '\x04', '\x20',
+ '\x46', '\x92', '\x45', '\x92', '\x79', '\x67', '\x7f', '\x0d',
+ '\xd2', '\x1c', '\x00', '\x38', '\xe9', '\x9b', '\x79', '\x86',
+ '\x01', '\x92', '\xdf', '\x9c', '\x00', '\x40', '\xf9', '\x20',
+ '\x0f', '\x05', '\x6e', '\x9a', '\x79', '\x67', '\xee', '\x9b',
+ '\x6f', '\x9e', '\xec', '\x1c', '\x00', '\x38', '\x47', '\xd2',
+ '\x02', '\x91', '\xdd', '\xdb', '\x08', '\x91', '\xee', '\xeb',
+ '\x44', '\xd2', '\xd9', '\xdb', '\x3f', '\xbd', '\xf2', '\x04',
+ '\x00', '\x38', '\x04', '\xe2', '\x3e', '\x0d', '\x00', '\x00',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2', '\xfe', '\x0b',
+ '\x4f', '\x9e', '\xaa', '\xff', '\x7f', '\x0d', '\x80', '\x18',
+ '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\x0d', '\x30', '\x00',
+ '\x00', '\xb0', '\xc9', '\x9b', '\x6f', '\x0e', '\x1a', '\x05',
+ '\x00', '\x38', '\x6f', '\xae', '\x84', '\x18', '\x00', '\x38',
+ '\xb0', '\xb9', '\x6f', '\xae', '\xd6', '\x1c', '\x00', '\x38',
+ '\x6a', '\xaa', '\x7a', '\x67', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x60', '\x05', '\x00', '\x38', '\x6f', '\xae', '\x50', '\x1c',
+ '\x00', '\x38', '\xb0', '\xb9', '\x6f', '\x9e', '\xf0', '\x00',
+ '\x00', '\x38', '\xef', '\x9e', '\x96', '\x1c', '\x00', '\x38',
+ '\x0e', '\x30', '\x70', '\x86', '\x09', '\x0c', '\xef', '\x9e',
+ '\x96', '\x1c', '\x00', '\x38', '\xf7', '\x20', '\x0f', '\x05',
+ '\x6f', '\xae', '\x96', '\x18', '\x00', '\x38', '\x3f', '\xbd',
+ '\x1a', '\x05', '\x00', '\x38', '\x60', '\xa6', '\x41', '\xb2',
+ '\x3f', '\xbd', '\x60', '\x05', '\x00', '\x38', '\x3f', '\xbd',
+ '\x88', '\x06', '\x00', '\x38', '\x3f', '\x0d', '\x28', '\x01',
+ '\x00', '\x38', '\xbe', '\x0f', '\x3e', '\x0d', '\x84', '\xe2',
+ '\x4f', '\x9e', '\x55', '\x00', '\x7f', '\x0d', '\x80', '\x18',
+ '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\x0d', '\x30', '\x00',
+ '\x00', '\xb0', '\xc9', '\x9b', '\x6f', '\x9e', '\x30', '\x00',
+ '\x00', '\xb0', '\x69', '\xda', '\x7d', '\x87', '\x7f', '\x0d',
+ '\x80', '\x18', '\x00', '\x38', '\xcd', '\xdb', '\xc9', '\xdb',
+ '\x7e', '\x8a', '\x6e', '\x9a', '\xef', '\x9e', '\x80', '\x84',
+ '\x1e', '\x00', '\xe1', '\x30', '\x0f', '\x05', '\x6e', '\x9a',
+ '\x01', '\x92', '\xee', '\x9b', '\xed', '\xe0', '\x0f', '\x05',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2', '\xfe', '\x0b',
+ '\x6f', '\x0e', '\x1a', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\xb2', '\x18', '\x00', '\x38', '\xb0', '\xb9', '\x3f', '\xbd',
+ '\x70', '\x04', '\x00', '\x38', '\x6f', '\xae', '\x00', '\x1f',
+ '\x00', '\x38', '\x5f', '\xbc', '\xec', '\x01', '\x3f', '\xbd',
+ '\x06', '\x0a', '\x00', '\x38', '\x6f', '\xae', '\xcc', '\x18',
+ '\x00', '\x38', '\xb0', '\xb9', '\x3f', '\xbd', '\xcc', '\x06',
+ '\x00', '\x38', '\xbe', '\x0f', '\x3e', '\xbe', '\x3f', '\x0d',
+ '\x46', '\x06', '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x98', '\xe2', '\xfe', '\x4b', '\x6f', '\xde', '\x00', '\x1f',
+ '\x00', '\x38', '\x6d', '\x9a', '\x79', '\x67', '\xed', '\x9f',
+ '\xef', '\xde', '\xec', '\x20', '\x00', '\x38', '\xf3', '\x20',
+ '\x0f', '\x05', '\x6f', '\x3e', '\x00', '\x1f', '\x00', '\x38',
+ '\xa3', '\x0b', '\xff', '\x3d', '\xfe', '\x02', '\x0f', '\x05',
+ '\x63', '\x9a', '\x81', '\x92', '\xcf', '\x9d', '\x0b', '\x00',
+ '\x5f', '\x95', '\x3f', '\xf8', '\x54', '\x02', '\x22', '\x01',
+ '\x18', '\x00', '\x62', '\x00', '\x90', '\x00', '\x96', '\x01',
+ '\xc8', '\x01', '\xe4', '\x00', '\x00', '\x02', '\xb8', '\x00',
+ '\x9a', '\x02', '\xce', '\x02', '\x6f', '\xae', '\xde', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\x6f', '\x0e', '\x60', '\x05', '\x00', '\x38', '\x04', '\x31',
+ '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31',
+ '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x6f', '\x0e',
+ '\x2a', '\x1d', '\x00', '\x38', '\x60', '\x9a', '\x81', '\x92',
+ '\xe0', '\x9b', '\x3f', '\xbd', '\x70', '\x04', '\x00', '\x38',
+ '\x60', '\x9a', '\x01', '\x92', '\xe0', '\x9b', '\x62', '\xaa',
+ '\x61', '\xba', '\x3f', '\xbd', '\x06', '\x0a', '\x00', '\x38',
+ '\xff', '\xed', '\x88', '\x02', '\x0c', '\x32', '\x6f', '\xae',
+ '\xec', '\x18', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\x6f', '\x0e', '\x60', '\x05', '\x00', '\x38',
+ '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x61', '\x1a', '\x72', '\x09', '\xe1', '\x1b', '\xff', '\xed',
+ '\x5a', '\x02', '\x0c', '\x32', '\x6f', '\xae', '\xfc', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\x6f', '\x1e', '\x60', '\x05', '\x00', '\x38', '\x04', '\x31',
+ '\x60', '\xae', '\x41', '\xb2', '\xb1', '\xb9', '\x60', '\xaa',
+ '\x6a', '\xaa', '\x41', '\xb2', '\xb1', '\xb9', '\xff', '\xed',
+ '\x32', '\x02', '\x08', '\x32', '\x6f', '\xae', '\x0c', '\x19',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\x04', '\x31', '\x60', '\xae', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x60', '\x05', '\x00', '\x38', '\x60', '\xaa', '\xff', '\x3d',
+ '\xc0', '\x01', '\x0f', '\x05', '\x81', '\xa2', '\xfd', '\x20',
+ '\x0f', '\x05', '\xff', '\xed', '\x06', '\x02', '\x08', '\x32',
+ '\x6f', '\x4e', '\x1a', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\x1a', '\x19', '\x00', '\x38', '\xb4', '\xb9', '\x6f', '\x0e',
+ '\x60', '\x05', '\x00', '\x38', '\x04', '\x31', '\x62', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x62', '\x2a', '\x62', '\x2a',
+ '\xe1', '\x2a', '\xff', '\x3d', '\xb8', '\x01', '\x0f', '\x05',
+ '\x6f', '\xae', '\x28', '\x19', '\x00', '\x38', '\xb4', '\xb9',
+ '\xff', '\xed', '\xd0', '\x01', '\x0f', '\x05', '\x6f', '\x4e',
+ '\x1a', '\x05', '\x00', '\x38', '\x6f', '\xae', '\x38', '\x19',
+ '\x00', '\x38', '\xb4', '\xb9', '\x6f', '\x2e', '\x60', '\x05',
+ '\x00', '\x38', '\x04', '\x31', '\x61', '\xae', '\x41', '\xb2',
+ '\xb2', '\xb9', '\x08', '\x31', '\x60', '\xae', '\x41', '\xb2',
+ '\xb2', '\xb9', '\x61', '\xaa', '\x60', '\xba', '\x6e', '\xc6',
+ '\x14', '\xc2', '\x3f', '\xbd', '\x04', '\x0b', '\x00', '\x38',
+ '\x6a', '\xa6', '\x30', '\x20', '\x0f', '\x05', '\x6f', '\xae',
+ '\x44', '\x19', '\x00', '\x38', '\xb4', '\xb9', '\x14', '\xe1',
+ '\x6a', '\xaa', '\x41', '\xb2', '\xb2', '\xb9', '\x14', '\xe1',
+ '\x6a', '\xaa', '\x6a', '\xb6', '\x0f', '\xbc', '\x40', '\x00',
+ '\x8f', '\xac', '\x40', '\x00', '\x3c', '\xa3', '\x3c', '\xb3',
+ '\x3f', '\xbd', '\xac', '\x0b', '\x00', '\x38', '\xff', '\xed',
+ '\x6a', '\x01', '\x0f', '\x05', '\x6f', '\xae', '\x60', '\x19',
+ '\x00', '\x38', '\xb4', '\xb9', '\xff', '\xed', '\x54', '\x01',
+ '\x0c', '\x32', '\x6f', '\xae', '\x76', '\x19', '\x00', '\x38',
+ '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38', '\x6f', '\x0e',
+ '\x60', '\x05', '\x00', '\x38', '\x04', '\x31', '\x62', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x62', '\xaa', '\x61', '\xba',
+ '\x3f', '\xbd', '\xac', '\x0b', '\x00', '\x38', '\xff', '\xed',
+ '\x22', '\x01', '\x0c', '\x32', '\x6f', '\xae', '\x82', '\x19',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\x6f', '\x0e', '\x60', '\x05', '\x00', '\x38', '\x04', '\x31',
+ '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31',
+ '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x62', '\xaa',
+ '\xe1', '\xaa', '\xda', '\x90', '\x0f', '\x05', '\x7a', '\x0e',
+ '\x08', '\x31', '\xea', '\xaa', '\xf9', '\x80', '\x0f', '\x05',
+ '\xea', '\xe0', '\x0c', '\x32', '\x6f', '\xae', '\x8e', '\x19',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\x6f', '\x0e', '\x60', '\x05', '\x00', '\x38', '\x04', '\x31',
+ '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31',
+ '\x64', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x0c', '\x31',
+ '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x6f', '\x0e',
+ '\x4a', '\x15', '\x00', '\x38', '\x61', '\xaa', '\x64', '\xba',
+ '\x62', '\xca', '\xb0', '\xb9', '\x6a', '\xa6', '\xac', '\x30',
+ '\x10', '\x32', '\xc3', '\xa2', '\xae', '\x20', '\x7a', '\x86',
+ '\x62', '\xca', '\xef', '\xcd', '\x00', '\x00', '\x01', '\x00',
+ '\x64', '\xba', '\xb0', '\xb9', '\x9e', '\xe0', '\x0f', '\x05',
+ '\x6f', '\xde', '\xb4', '\x1c', '\x00', '\x38', '\x6d', '\x9a',
+ '\x7f', '\x0d', '\xc0', '\x01', '\x00', '\xb0', '\xe9', '\x9b',
+ '\x04', '\xd1', '\x59', '\x98', '\x7f', '\x0d', '\xc4', '\x01',
+ '\x00', '\xb0', '\xe9', '\x9b', '\x6f', '\x1e', '\x1a', '\x05',
+ '\x00', '\x38', '\x6f', '\xae', '\x96', '\x19', '\x00', '\x38',
+ '\xb1', '\xb9', '\x04', '\x31', '\x60', '\xae', '\x41', '\xb2',
+ '\x3f', '\xbd', '\x60', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\x9e', '\x19', '\x00', '\x38', '\xb1', '\xb9', '\x60', '\x9a',
+ '\xb9', '\x09', '\x50', '\xe0', '\x08', '\x32', '\x6f', '\xae',
+ '\x12', '\x19', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\x6f', '\x0e', '\x60', '\x05', '\x00', '\x38',
+ '\x04', '\x31', '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x08', '\x31', '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x61', '\x1a', '\x61', '\x9a', '\x08', '\x30', '\x81', '\x92',
+ '\xe1', '\x9b', '\x20', '\xe0', '\x62', '\x3a', '\x1c', '\xe0',
+ '\x0c', '\x32', '\x6f', '\xae', '\xa4', '\x19', '\x00', '\x38',
+ '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38', '\x63', '\xaa',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x60', '\x05', '\x00', '\x38',
+ '\x0a', '\xe0', '\x0f', '\x05', '\xa3', '\x0b', '\xff', '\x2d',
+ '\x06', '\xfd', '\x0f', '\x05', '\x6f', '\xae', '\x9e', '\x19',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\xbe', '\x4f', '\x04', '\xe2', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x8c', '\xe2', '\xfe', '\x2b', '\x6a', '\x26',
+ '\x6b', '\x06', '\x7f', '\x0d', '\x22', '\x1d', '\x00', '\x38',
+ '\x70', '\x8a', '\x7f', '\x0d', '\x04', '\x01', '\x00', '\x38',
+ '\xea', '\xab', '\x6f', '\x9e', '\x26', '\x1d', '\x00', '\x38',
+ '\x49', '\x9a', '\xcf', '\x9e', '\x01', '\x00', '\x86', '\x20',
+ '\x0f', '\x05', '\x6f', '\xde', '\xda', '\x1c', '\x00', '\x38',
+ '\x08', '\xd1', '\xea', '\xab', '\x7f', '\x0d', '\x00', '\x01',
+ '\x00', '\x38', '\xeb', '\xbb', '\x6b', '\x96', '\x04', '\x92',
+ '\xdf', '\x9d', '\xdc', '\x05', '\xdd', '\x9b', '\x6f', '\x9e',
+ '\xa4', '\x01', '\x00', '\xb0', '\x69', '\xda', '\x6f', '\xde',
+ '\xa4', '\x1c', '\x00', '\x38', '\xe9', '\xdb', '\x6f', '\xde',
+ '\xd4', '\x01', '\x00', '\xb0', '\x4d', '\x9a', '\x38', '\x93',
+ '\x44', '\x93', '\xcd', '\x9b', '\x6f', '\xde', '\xd4', '\x01',
+ '\x00', '\xb0', '\x4d', '\x9a', '\x07', '\x93', '\xcf', '\x9e',
+ '\x04', '\x00', '\xf7', '\x30', '\x0f', '\x05', '\x4d', '\x9a',
+ '\x38', '\x93', '\x41', '\x93', '\xcd', '\x9b', '\x3f', '\xbd',
+ '\x0c', '\x02', '\x00', '\x38', '\x6a', '\xa6', '\xf7', '\x30',
+ '\x0f', '\x05', '\x6f', '\xce', '\x22', '\x1d', '\x00', '\x38',
+ '\xec', '\x0a', '\x10', '\x80', '\x0f', '\x05', '\x6f', '\xde',
+ '\xd4', '\x01', '\x00', '\xb0', '\x4d', '\x9a', '\x38', '\x93',
+ '\x41', '\x93', '\xcd', '\x9b', '\xec', '\x0a', '\xd7', '\x90',
+ '\x71', '\x86', '\x22', '\xe0', '\x62', '\x96', '\x7f', '\x0d',
+ '\x22', '\x1d', '\x00', '\x38', '\xeb', '\xba', '\x14', '\x80',
+ '\x71', '\x86', '\x3f', '\xbd', '\x0c', '\x02', '\x00', '\x38',
+ '\x7f', '\x0d', '\x22', '\x1d', '\x00', '\x38', '\xe0', '\x0a',
+ '\xf1', '\x90', '\x71', '\x86', '\x62', '\x96', '\x20', '\x96',
+ '\xe9', '\x26', '\x0e', '\x30', '\x62', '\xd6', '\x0d', '\x1c',
+ '\x62', '\x96', '\x20', '\x96', '\xe9', '\xd6', '\xf7', '\x20',
+ '\x0f', '\x05', '\x6f', '\xae', '\xb8', '\x19', '\x00', '\x38',
+ '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38', '\x61', '\xa6',
+ '\x41', '\xb2', '\xbe', '\x2f', '\x3e', '\xbe', '\x3f', '\x0d',
+ '\x60', '\x05', '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x8c', '\xe2', '\xfe', '\x2b', '\x6b', '\x06', '\x6c', '\x26',
+ '\xeb', '\xa6', '\x40', '\x00', '\x6a', '\xc6', '\xe0', '\xc6',
+ '\x32', '\x00', '\x71', '\x86', '\x6c', '\xb6', '\x6c', '\x96',
+ '\x79', '\x87', '\x61', '\xd6', '\xc3', '\xd3', '\xed', '\x97',
+ '\x49', '\xd6', '\xcb', '\x9b', '\x4b', '\x9a', '\xcd', '\x96',
+ '\x0c', '\x30', '\x7d', '\x87', '\x6f', '\xae', '\xce', '\x19',
+ '\x00', '\x38', '\x40', '\xe0', '\xe2', '\xbb', '\xcb', '\xdf',
+ '\x01', '\x12', '\xc4', '\x12', '\x06', '\x30', '\xe0', '\xb6',
+ '\xd7', '\x10', '\x6c', '\x96', '\x04', '\xc2', '\xe0', '\xc6',
+ '\xc5', '\x10', '\x0f', '\x05', '\xe0', '\xa6', '\x4e', '\x00',
+ '\x6a', '\xc6', '\xe0', '\xc6', '\x40', '\x00', '\x71', '\x86',
+ '\x6c', '\xa6', '\x61', '\x96', '\xc3', '\x93', '\x6c', '\xd6',
+ '\xe9', '\xd7', '\x4a', '\x9a', '\xcd', '\x96', '\x22', '\x30',
+ '\x01', '\x12', '\x81', '\x12', '\xe2', '\xab', '\x6f', '\xae',
+ '\xec', '\x19', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\x62', '\xaa', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x60', '\x05', '\x00', '\x38', '\x7a', '\x86', '\xbe', '\x2f',
+ '\x3e', '\x0d', '\xc4', '\x12', '\x08', '\x30', '\x01', '\xa2',
+ '\xe0', '\xa6', '\xc9', '\x10', '\x61', '\x96', '\x04', '\xc2',
+ '\xe0', '\xc6', '\xb7', '\x10', '\x0f', '\x05', '\x41', '\xa2',
+ '\xbe', '\x2f', '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x94', '\xe2', '\xfe', '\x4b', '\x6b', '\x26', '\xeb', '\xa6',
+ '\x5a', '\x90', '\x6a', '\x06', '\x60', '\xa6', '\x7b', '\x86',
+ '\x3f', '\xbd', '\x60', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\x0a', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\xe2', '\x06', '\x2a', '\x90', '\x74', '\x86',
+ '\x60', '\x16', '\x60', '\x36', '\x6f', '\xae', '\x60', '\x1a',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\x63', '\xae', '\x7b', '\x86', '\x3f', '\xbd', '\x60', '\x05',
+ '\x00', '\x38', '\x01', '\x42', '\xc4', '\x42', '\x08', '\x30',
+ '\x04', '\x12', '\xe2', '\x16', '\xdf', '\x80', '\x0f', '\x05',
+ '\x6f', '\xae', '\xc8', '\x18', '\x00', '\x38', '\x3f', '\xbd',
+ '\x1a', '\x05', '\x00', '\x38', '\x10', '\x02', '\xe2', '\x06',
+ '\xad', '\x80', '\x60', '\xa6', '\xbe', '\x4f', '\x3e', '\x0d',
+ '\x05', '\xa1', '\x49', '\x98', '\xc2', '\x92', '\x0a', '\x30',
+ '\xc4', '\x92', '\x0e', '\x30', '\x0f', '\x05', '\x7f', '\xb6',
+ '\x7a', '\x86', '\x6a', '\xb9', '\x5a', '\xa8', '\x7f', '\xb6',
+ '\x0f', '\x05', '\x6a', '\xb9', '\x6a', '\xaa', '\x7f', '\xb6',
+ '\x0f', '\x05', '\x6a', '\xd6', '\x05', '\xa1', '\x4a', '\xaa',
+ '\x4a', '\x94', '\xc2', '\x92', '\x0a', '\x30', '\xc4', '\x92',
+ '\x10', '\x30', '\x0f', '\x05', '\x7f', '\xb6', '\x7a', '\x86',
+ '\x5c', '\xca', '\x6d', '\xb9', '\xdc', '\xcb', '\x7f', '\xb6',
+ '\x4a', '\xa4', '\x6c', '\xca', '\x6d', '\xb9', '\xec', '\xcb',
+ '\x4a', '\xa4', '\x7f', '\xb6', '\x0f', '\x05', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x84', '\xe2', '\xee', '\xbb', '\x04', '\xa1',
+ '\x49', '\x9a', '\xcf', '\x9e', '\x01', '\x00', '\x06', '\x20',
+ '\x0f', '\x05', '\x24', '\xe0', '\xc1', '\xc3', '\xcf', '\x9e',
+ '\x02', '\x00', '\x0c', '\x20', '\x6b', '\x96', '\xd0', '\x93',
+ '\x69', '\xb7', '\xee', '\xbb', '\x12', '\xe0', '\xc2', '\xc3',
+ '\x6f', '\xae', '\x36', '\x1a', '\x00', '\x38', '\x3f', '\xbd',
+ '\x1a', '\x05', '\x00', '\x38', '\x0c', '\xe0', '\x0f', '\x05',
+ '\x6c', '\xb6', '\x6e', '\xc6', '\x3f', '\xbd', '\x3a', '\x0c',
+ '\x00', '\x38', '\x04', '\xe2', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x84', '\xe2', '\xfe', '\x0b', '\x6a', '\x06',
+ '\x4f', '\xbc', '\xaa', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\x66', '\x0c', '\x00', '\x38', '\x60', '\xa6',
+ '\x4f', '\xbc', '\x55', '\x00', '\x5f', '\xcc', '\xaa', '\x02',
+ '\xbe', '\x0f', '\x3e', '\xbe', '\x3f', '\x0d', '\x66', '\x0c',
+ '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe', '\x90', '\xe2',
+ '\xfe', '\x3b', '\x6a', '\x26', '\x04', '\xa1', '\x49', '\x9a',
+ '\xcf', '\x9e', '\x02', '\x00', '\x42', '\x20', '\x6b', '\x36',
+ '\x6f', '\x0e', '\x18', '\x0c', '\x00', '\x38', '\xb0', '\xb9',
+ '\x6a', '\x16', '\x62', '\xa6', '\x63', '\xb6', '\xb0', '\xb9',
+ '\x61', '\xd6', '\xf0', '\xd3', '\x1f', '\xdf', '\x40', '\x00',
+ '\x6a', '\x96', '\xf0', '\x93', '\x1f', '\x9f', '\x40', '\x00',
+ '\xe9', '\xd6', '\x14', '\x20', '\x7c', '\x86', '\x2f', '\x1f',
+ '\x40', '\x00', '\x00', '\x00', '\x2f', '\xaf', '\x40', '\x00',
+ '\x00', '\x00', '\xea', '\x16', '\x04', '\x30', '\x0f', '\x05',
+ '\x41', '\xc2', '\x6c', '\xa6', '\xbe', '\x3f', '\x3e', '\x0d',
+ '\x6f', '\x1e', '\x18', '\x0c', '\x00', '\x38', '\xb1', '\xb9',
+ '\x4a', '\x04', '\x0f', '\x0f', '\x40', '\x00', '\x62', '\xa6',
+ '\x63', '\xb6', '\xb1', '\xb9', '\x2f', '\xaf', '\x40', '\x00',
+ '\x00', '\x00', '\xea', '\x06', '\x3a', '\x25', '\xbe', '\x3f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\xa8', '\xe2',
+ '\xfe', '\x8b', '\x6a', '\x36', '\x04', '\xa1', '\x44', '\x9e',
+ '\xcf', '\x9e', '\x02', '\x00', '\x04', '\x20', '\x41', '\x72',
+ '\x42', '\x72', '\x6f', '\x2e', '\x66', '\x0c', '\x00', '\x38',
+ '\x4f', '\xbc', '\x98', '\x00', '\x4f', '\xcc', '\x55', '\x00',
+ '\xb2', '\xb9', '\x50', '\xb2', '\xe7', '\xb4', '\x6f', '\x1e',
+ '\x18', '\x0c', '\x00', '\x38', '\x63', '\xa6', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x51', '\x00', '\xff', '\x2d', '\x9c', '\x01',
+ '\x63', '\xa6', '\x51', '\xb2', '\xe7', '\xb4', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x52', '\x00', '\xff', '\x2d', '\x8c', '\x01',
+ '\x63', '\xa6', '\x52', '\xb2', '\xe7', '\xb4', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x59', '\x00', '\xff', '\x2d', '\x7c', '\x01',
+ '\x63', '\xa6', '\x24', '\xe1', '\x70', '\x8a', '\x6f', '\xae',
+ '\x50', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\x63', '\xaa', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x60', '\x05', '\x00', '\x38', '\x4f', '\xbc', '\x27', '\x00',
+ '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9', '\x41', '\x92',
+ '\xea', '\x94', '\x06', '\x32', '\xe3', '\x9b', '\x86', '\x32',
+ '\x4f', '\xbc', '\x2c', '\x00', '\xe7', '\xb4', '\x63', '\xa6',
+ '\xb1', '\xb9', '\x6a', '\x86', '\x55', '\xb2', '\xe7', '\xb4',
+ '\x63', '\xa6', '\xb1', '\xb9', '\x6a', '\x06', '\x6a', '\xb6',
+ '\x04', '\xb2', '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x30', '\x00', '\x3e', '\x20', '\x63', '\xa6',
+ '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\xb2', '\xb9', '\x63', '\xa6', '\x3f', '\xbd', '\xae', '\x0c',
+ '\x00', '\x38', '\x63', '\xa6', '\x4f', '\xbc', '\x90', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\xb2', '\xb9', '\x44', '\xb8',
+ '\x2b', '\xb6', '\x63', '\xa6', '\xb1', '\xb9', '\x4a', '\x54',
+ '\x0f', '\x5f', '\x80', '\xff', '\x63', '\xa6', '\x4f', '\xbc',
+ '\x98', '\x00', '\x4f', '\xcc', '\x55', '\x00', '\xb2', '\xb9',
+ '\x10', '\xe0', '\x0f', '\x05', '\x0f', '\x02', '\xe7', '\x04',
+ '\x60', '\xb6', '\xb1', '\xb9', '\xcf', '\xae', '\x03', '\x00',
+ '\x35', '\x35', '\x0a', '\x31', '\xd8', '\x8b', '\xc8', '\x82',
+ '\x12', '\xd0', '\x68', '\x46', '\x6f', '\xae', '\x62', '\x1a',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\xd2', '\xe0', '\x7a', '\x86', '\x65', '\x56', '\x94', '\x20',
+ '\x81', '\x42', '\x90', '\xe0', '\x74', '\x86', '\xc2', '\x03',
+ '\x60', '\xb6', '\x2f', '\xb2', '\xe7', '\xb4', '\x6f', '\x1e',
+ '\x18', '\x0c', '\x00', '\x38', '\x63', '\xa6', '\xb1', '\xb9',
+ '\x6a', '\x66', '\x60', '\xb6', '\x30', '\xb2', '\xe7', '\xb4',
+ '\x63', '\xa6', '\xb1', '\xb9', '\xc8', '\xa3', '\x6a', '\x67',
+ '\xc8', '\x63', '\x60', '\xb6', '\x2d', '\xb2', '\xe7', '\xb4',
+ '\x63', '\xa6', '\xb1', '\xb9', '\x6a', '\x26', '\x2e', '\x02',
+ '\xe7', '\x04', '\x63', '\xa6', '\x60', '\xb6', '\xb1', '\xb9',
+ '\xc8', '\xa3', '\x6a', '\x27', '\x65', '\x56', '\x0a', '\x30',
+ '\x01', '\x22', '\x68', '\x96', '\xa4', '\x96', '\x04', '\xe0',
+ '\x81', '\x92', '\x64', '\x96', '\x19', '\x95', '\x63', '\xd6',
+ '\x2d', '\x95', '\x6d', '\x96', '\x24', '\xe1', '\x6d', '\xda',
+ '\x0c', '\x91', '\xed', '\xdb', '\x10', '\x91', '\xe6', '\x6b',
+ '\x14', '\x91', '\xe2', '\x2b', '\x62', '\x26', '\x10', '\xd0',
+ '\x0f', '\x05', '\x24', '\xe1', '\x29', '\x6a', '\x24', '\xe1',
+ '\xe9', '\x9b', '\x81', '\x22', '\xf5', '\x20', '\x0f', '\x05',
+ '\x24', '\xe1', '\x6d', '\xda', '\x06', '\x31', '\xed', '\xda',
+ '\x1e', '\x30', '\x65', '\x56', '\x06', '\x30', '\x01', '\x42',
+ '\x81', '\x42', '\x81', '\x42', '\x65', '\x56', '\x0c', '\x30',
+ '\xe8', '\x46', '\x64', '\x46', '\x69', '\xa0', '\x64', '\x06',
+ '\x08', '\xe0', '\x63', '\xa6', '\x61', '\xb0', '\x64', '\x06',
+ '\x63', '\xa6', '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc',
+ '\x55', '\x05', '\x3f', '\xbd', '\x66', '\x0c', '\x00', '\x38',
+ '\x12', '\xe0', '\x41', '\xa2', '\x4f', '\xbc', '\xf0', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\x66', '\x0c',
+ '\x00', '\x38', '\x7a', '\x86', '\xbe', '\x8f', '\x04', '\xe2',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x90', '\xe2',
+ '\xfe', '\x3b', '\x06', '\xa1', '\xa0', '\x0b', '\xff', '\x2d',
+ '\x16', '\x04', '\x6a', '\x26', '\x3f', '\xbd', '\x52', '\x0d',
+ '\x00', '\x38', '\x6a', '\xa6', '\xff', '\x2d', '\x86', '\x03',
+ '\x41', '\xa2', '\x62', '\xa6', '\x3f', '\xbd', '\xae', '\x0c',
+ '\x00', '\x38', '\x62', '\xa6', '\x4f', '\xbc', '\x90', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\x66', '\x0c',
+ '\x00', '\x38', '\x6f', '\x1e', '\x18', '\x0c', '\x00', '\x38',
+ '\x62', '\xa6', '\x7b', '\x86', '\xb1', '\xb9', '\x6a', '\x36',
+ '\x04', '\x21', '\x40', '\xbe', '\x4b', '\xb4', '\x2b', '\xb6',
+ '\x62', '\xa6', '\xb1', '\xb9', '\x42', '\x92', '\xc0', '\x9a',
+ '\x1c', '\x20', '\x63', '\xc6', '\xf0', '\xc3', '\x53', '\x94',
+ '\xe9', '\xc6', '\x14', '\x20', '\x63', '\x06', '\x6a', '\xd6',
+ '\xf0', '\xd3', '\x5a', '\x94', '\xe9', '\xd6', '\x0a', '\x20',
+ '\xd0', '\x03', '\x6c', '\x36', '\x6d', '\xa6', '\x63', '\x06',
+ '\xd0', '\x03', '\x6a', '\x07', '\x62', '\xa6', '\x4f', '\xbc',
+ '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd',
+ '\x66', '\x0c', '\x00', '\x38', '\xef', '\x0e', '\xc0', '\x00',
+ '\x1f', '\x00', '\xff', '\x3d', '\x48', '\x02', '\x0f', '\x05',
+ '\x60', '\x90', '\x0f', '\x05', '\xef', '\x0e', '\xc4', '\x22',
+ '\x01', '\x00', '\xb0', '\x30', '\x0f', '\x05', '\x20', '\x90',
+ '\x0f', '\x05', '\xef', '\x0e', '\x58', '\x22', '\x01', '\x00',
+ '\xff', '\x3d', '\x5a', '\x01', '\x0f', '\x05', '\xef', '\x0e',
+ '\x5b', '\x22', '\x01', '\x00', '\xff', '\x3d', '\x4e', '\x01',
+ '\x0f', '\x05', '\xff', '\xed', '\xb6', '\x02', '\x0f', '\x05',
+ '\xef', '\x0e', '\xda', '\x22', '\x01', '\x00', '\xff', '\x3d',
+ '\x9c', '\x01', '\x0f', '\x05', '\x14', '\x90', '\x0f', '\x05',
+ '\xef', '\x0e', '\xd6', '\x22', '\x01', '\x00', '\xff', '\x3d',
+ '\x8c', '\x01', '\x0f', '\x05', '\xff', '\xed', '\x94', '\x02',
+ '\x0f', '\x05', '\xef', '\x0e', '\x49', '\x22', '\x04', '\x00',
+ '\xc4', '\x30', '\x0f', '\x05', '\xff', '\xed', '\x84', '\x02',
+ '\x0f', '\x05', '\xef', '\x0e', '\xd7', '\x00', '\x20', '\x00',
+ '\xff', '\x3d', '\x6a', '\x01', '\x0f', '\x05', '\x20', '\x90',
+ '\x0f', '\x05', '\xef', '\x0e', '\xc2', '\x00', '\x1f', '\x00',
+ '\xff', '\x3d', '\x00', '\x02', '\x0f', '\x05', '\xef', '\x0e',
+ '\xc9', '\x00', '\x1f', '\x00', '\xff', '\x3d', '\x18', '\x02',
+ '\x0f', '\x05', '\xff', '\xed', '\x56', '\x02', '\x0f', '\x05',
+ '\xef', '\x0e', '\x4f', '\x00', '\x98', '\x00', '\xff', '\x3d',
+ '\x3c', '\x01', '\x0f', '\x05', '\x12', '\x90', '\x0f', '\x05',
+ '\xef', '\x0e', '\x43', '\x00', '\x98', '\x00', '\x76', '\x30',
+ '\x0f', '\x05', '\xff', '\xed', '\x36', '\x02', '\x0f', '\x05',
+ '\xef', '\x0e', '\xc2', '\x00', '\x98', '\x00', '\xff', '\x2d',
+ '\x2a', '\x02', '\x0f', '\x05', '\x6f', '\x1e', '\x46', '\x1b',
+ '\x00', '\x38', '\x61', '\x1a', '\x6f', '\xde', '\x00', '\x00',
+ '\x20', '\x00', '\x06', '\x21', '\xed', '\xdb', '\x0c', '\x21',
+ '\x70', '\x8a', '\x6f', '\x9e', '\x00', '\x00', '\x01', '\x00',
+ '\x10', '\x21', '\xe9', '\x9b', '\x5f', '\xd2', '\x14', '\x21',
+ '\xed', '\xdb', '\x6f', '\x9e', '\x00', '\x00', '\x1f', '\x00',
+ '\x18', '\x21', '\xe9', '\x9b', '\x1f', '\xdc', '\xe1', '\x7f',
+ '\x1c', '\x21', '\xed', '\xdb', '\x41', '\x92', '\x20', '\x21',
+ '\xe9', '\x9b', '\x6f', '\xde', '\x00', '\x80', '\x1f', '\x00',
+ '\x24', '\x21', '\xed', '\xdb', '\x5f', '\xdc', '\x00', '\x20',
+ '\x28', '\x21', '\xed', '\xdb', '\x42', '\xd2', '\x2c', '\x21',
+ '\xed', '\xdb', '\x6f', '\xde', '\x00', '\xc0', '\x1f', '\x00',
+ '\xff', '\xed', '\x16', '\x01', '\x0f', '\x05', '\x6f', '\x1e',
+ '\x42', '\x1b', '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x20', '\x00', '\x06', '\x21', '\xe9', '\x9b',
+ '\x0c', '\x21', '\x70', '\x8a', '\x5f', '\x9c', '\x00', '\x40',
+ '\x10', '\x21', '\xe9', '\x9b', '\x41', '\xd2', '\x14', '\x21',
+ '\xed', '\xdb', '\x18', '\x21', '\xe9', '\x9b', '\x5f', '\x9c',
+ '\x00', '\x20', '\x1c', '\x21', '\xe9', '\x9b', '\x42', '\x92',
+ '\x20', '\x21', '\xe9', '\x9b', '\x1f', '\x9c', '\xfe', '\x7f',
+ '\x24', '\x21', '\xe9', '\x9b', '\x28', '\x21', '\xe9', '\x9b',
+ '\x2c', '\x21', '\xed', '\xdb', '\x6f', '\x9e', '\x00', '\x00',
+ '\x01', '\x00', '\x30', '\x21', '\xe9', '\x9b', '\x34', '\x21',
+ '\xe9', '\x9b', '\x58', '\xe0', '\x5f', '\xd2', '\x6f', '\x1e',
+ '\x3a', '\x1b', '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x10', '\x00', '\x06', '\x21', '\xe9', '\x9b',
+ '\x0c', '\x21', '\x70', '\x8a', '\x5f', '\x9c', '\x00', '\x40',
+ '\x10', '\x21', '\xe9', '\x9b', '\x41', '\xd2', '\x14', '\x21',
+ '\xed', '\xdb', '\x18', '\x21', '\xe9', '\x9b', '\x5f', '\x9c',
+ '\x00', '\x20', '\x1c', '\x21', '\xe9', '\x9b', '\x42', '\x92',
+ '\x20', '\x21', '\xe9', '\x9b', '\x1f', '\x9c', '\xfe', '\x7f',
+ '\x24', '\x21', '\xe9', '\x9b', '\x28', '\x21', '\xe9', '\x9b',
+ '\x2c', '\x21', '\xed', '\xdb', '\x6f', '\x9e', '\x00', '\x00',
+ '\x01', '\x00', '\x30', '\x21', '\xe9', '\x9b', '\x34', '\x21',
+ '\xe9', '\x9b', '\x4f', '\xd2', '\x38', '\x21', '\xed', '\xdb',
+ '\xff', '\xed', '\x3e', '\x01', '\x0f', '\x05', '\x6f', '\x1e',
+ '\x3e', '\x1b', '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x10', '\x00', '\x06', '\x21', '\xe9', '\x9b',
+ '\x0c', '\x21', '\x70', '\x8a', '\x6f', '\xde', '\x00', '\x00',
+ '\x01', '\x00', '\x10', '\x21', '\xed', '\xdb', '\x4f', '\x92',
+ '\x14', '\x21', '\xe9', '\x9b', '\x6f', '\xde', '\x00', '\x00',
+ '\x0f', '\x00', '\x18', '\x21', '\xed', '\xdb', '\x1f', '\x9c',
+ '\xf1', '\x7f', '\x1c', '\x21', '\xe9', '\x9b', '\x41', '\x92',
+ '\x20', '\x21', '\xe9', '\x9b', '\x6f', '\xde', '\x00', '\x80',
+ '\x0f', '\x00', '\x24', '\x21', '\xed', '\xdb', '\x5f', '\xdc',
+ '\x00', '\x20', '\x28', '\x21', '\xed', '\xdb', '\x42', '\xd2',
+ '\x2c', '\x21', '\xed', '\xdb', '\x6f', '\xde', '\x00', '\xc0',
+ '\x0f', '\x00', '\x30', '\x21', '\xed', '\xdb', '\x5f', '\xdc',
+ '\x00', '\x40', '\x34', '\x21', '\xed', '\xdb', '\x38', '\x21',
+ '\xe9', '\x9b', '\xce', '\xe0', '\x0f', '\x05', '\x6f', '\x1e',
+ '\x42', '\x1b', '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x20', '\x00', '\x06', '\x21', '\xe9', '\x9b',
+ '\x0c', '\x21', '\x70', '\x8a', '\x5f', '\xdc', '\x00', '\x20',
+ '\x10', '\x21', '\xed', '\xdb', '\x48', '\x92', '\x14', '\x21',
+ '\xe9', '\x9b', '\x6f', '\x9e', '\x00', '\x00', '\x01', '\x00',
+ '\x18', '\x21', '\xe9', '\x9b', '\x1c', '\x21', '\xe9', '\x9b',
+ '\x62', '\xe0', '\x5f', '\xd2', '\x6f', '\x1e', '\x46', '\x1b',
+ '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00',
+ '\x20', '\x00', '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21',
+ '\x70', '\x8a', '\x6f', '\xde', '\x00', '\x00', '\x01', '\x00',
+ '\x10', '\x21', '\xed', '\xdb', '\x26', '\xe0', '\x5f', '\x92',
+ '\x6f', '\x1e', '\x4a', '\x1b', '\x00', '\x38', '\x61', '\x1a',
+ '\x6f', '\x9e', '\x00', '\x00', '\x40', '\x00', '\x06', '\x21',
+ '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a', '\x6f', '\xde',
+ '\x00', '\x00', '\x01', '\x00', '\x10', '\x21', '\xed', '\xdb',
+ '\x4f', '\x9c', '\x3f', '\x00', '\x14', '\x21', '\xe9', '\x9b',
+ '\x6f', '\xde', '\x00', '\x00', '\x1f', '\x00', '\x18', '\x21',
+ '\xed', '\xdb', '\x5f', '\x9c', '\x00', '\x20', '\x1c', '\x21',
+ '\xe9', '\x9b', '\x48', '\xd2', '\x20', '\x21', '\xed', '\xdb',
+ '\x30', '\xe0', '\x0f', '\x05', '\x04', '\x21', '\x49', '\x9a',
+ '\x6f', '\xae', '\x7e', '\x1a', '\x00', '\x38', '\xcf', '\x9e',
+ '\x01', '\x00', '\x08', '\x30', '\x0f', '\x05', '\x6f', '\xae',
+ '\x90', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\x62', '\xaa', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x60', '\x05', '\x00', '\x38', '\x7a', '\x86', '\xbe', '\x3f',
+ '\x3e', '\x0d', '\x6f', '\x3e', '\x1a', '\x05', '\x00', '\x38',
+ '\x6f', '\xae', '\xa8', '\x1a', '\x00', '\x38', '\xb3', '\xb9',
+ '\x04', '\x21', '\x40', '\x9e', '\xcf', '\x9e', '\x01', '\x00',
+ '\x0c', '\x20', '\x42', '\xd2', '\x6f', '\xae', '\xb0', '\x1a',
+ '\x00', '\x38', '\xb3', '\xb9', '\x42', '\xd2', '\xc0', '\xda',
+ '\x32', '\x20', '\x47', '\xc2', '\x06', '\x21', '\x6d', '\x9e',
+ '\xc1', '\x93', '\xed', '\x9b', '\x62', '\xd6', '\x0c', '\xd1',
+ '\x69', '\x9a', '\xc1', '\x93', '\x0c', '\xd1', '\xe9', '\x9b',
+ '\x10', '\xd1', '\x69', '\x9a', '\xc1', '\x93', '\x10', '\xd1',
+ '\xe9', '\x9b', '\x81', '\xc2', '\xe9', '\x60', '\x0c', '\xd2',
+ '\x6f', '\xae', '\xb2', '\x1a', '\x00', '\x38', '\x3f', '\xbd',
+ '\x1a', '\x05', '\x00', '\x38', '\x6f', '\x0e', '\x1a', '\x05',
+ '\x00', '\x38', '\x6f', '\xae', '\xb4', '\x1a', '\x00', '\x38',
+ '\xb0', '\xb9', '\x61', '\xa6', '\xb0', '\xb9', '\x6f', '\xae',
+ '\xe6', '\x19', '\x00', '\x38', '\xb0', '\xb9', '\x62', '\xaa',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x60', '\x05', '\x00', '\x38',
+ '\x41', '\xa2', '\xbe', '\x3f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x8c', '\xe2', '\xfe', '\x2b', '\x6a', '\x16',
+ '\x6b', '\x26', '\x6f', '\x0e', '\xae', '\x0c', '\x00', '\x38',
+ '\xb0', '\xb9', '\x61', '\xa6', '\x4f', '\xbc', '\x80', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\x66', '\x0c',
+ '\x00', '\x38', '\x61', '\xa6', '\xb0', '\xb9', '\x04', '\x11',
+ '\x49', '\x9a', '\xcf', '\x9e', '\x02', '\x00', '\x10', '\x20',
+ '\x0f', '\x05', '\x6f', '\x9e', '\x30', '\x00', '\x30', '\x00',
+ '\x61', '\x29', '\xe9', '\x9b', '\xbe', '\x2f', '\x3e', '\x0d',
+ '\x4f', '\x9c', '\x30', '\x00', '\x61', '\x29', '\xd9', '\x9b',
+ '\xbe', '\x2f', '\x3e', '\x0d', '\x84', '\xe2', '\xfe', '\x0b',
+ '\x06', '\xa1', '\xeb', '\xba', '\x10', '\x10', '\x0f', '\x05',
+ '\x7a', '\x86', '\x7f', '\xb6', '\xbe', '\x0f', '\x10', '\xa1',
+ '\x6a', '\xaa', '\x7f', '\xb6', '\xbe', '\x0f', '\x70', '\x86',
+ '\x0c', '\xa1', '\xeb', '\xba', '\x22', '\x10', '\x7d', '\x86',
+ '\x14', '\xa1', '\xed', '\xda', '\x10', '\x00', '\x79', '\x86',
+ '\x10', '\xa1', '\x6c', '\xca', '\x01', '\x92', '\x14', '\xa1',
+ '\xe9', '\x9a', '\xf9', '\x10', '\x2c', '\xd6', '\x0c', '\xa1',
+ '\x29', '\xda', '\xe9', '\xb6', '\xd1', '\x10', '\x0f', '\x05',
+ '\x01', '\x02', '\xc7', '\x02', '\xd3', '\x80', '\x0c', '\xa2',
+ '\x7a', '\x86', '\x7f', '\xb6', '\xbe', '\x0f', '\x84', '\xe2',
+ '\xfe', '\x0b', '\x6a', '\x06', '\x6b', '\xa6', '\x6d', '\xb6',
+ '\x7d', '\x86', '\xeb', '\xd6', '\x48', '\xa0', '\x0f', '\x05',
+ '\x60', '\x9a', '\x2d', '\x96', '\x49', '\xa5', '\x59', '\x9a',
+ '\x4c', '\xd5', '\xd9', '\x9a', '\x32', '\x30', '\x02', '\xd2',
+ '\x82', '\xd2', '\x6b', '\x96', '\x2a', '\x96', '\xe9', '\xa6',
+ '\x20', '\x00', '\x6a', '\xc6', '\x60', '\xc9', '\x59', '\x9a',
+ '\xdf', '\x9e', '\xff', '\xff', '\x0a', '\x30', '\x02', '\xc2',
+ '\x82', '\xc2', '\x42', '\xa2', '\x7f', '\xb6', '\xbe', '\x0f',
+ '\x6b', '\x96', '\x2a', '\x96', '\xe9', '\xc6', '\xe5', '\x10',
+ '\x0f', '\x05', '\x41', '\xa2', '\x7f', '\xb6', '\xbe', '\x0f',
+ '\xeb', '\xd6', '\xbd', '\xb0', '\x0f', '\x05', '\x7a', '\x86',
+ '\x7f', '\xb6', '\xbe', '\x0f', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x90', '\xe2', '\xfe', '\x3b', '\x73', '\x86', '\x72', '\x86',
+ '\x6f', '\x0e', '\x4e', '\x1b', '\x00', '\x38', '\x41', '\x12',
+ '\x04', '\x01', '\xc1', '\x1b', '\xcf', '\x1e', '\x01', '\x00',
+ '\x04', '\x30', '\x42', '\x92', '\x44', '\x92', '\x05', '\x01',
+ '\xc9', '\x9b', '\x60', '\xa6', '\x3f', '\xbd', '\x42', '\x0f',
+ '\x00', '\x38', '\x6a', '\xa6', '\x0c', '\x20', '\x0f', '\x05',
+ '\xc1', '\x13', '\xcf', '\x1e', '\x03', '\x00', '\xd9', '\x80',
+ '\x0f', '\x05', '\x06', '\x01', '\x23', '\x3a', '\x0f', '\x0c',
+ '\x6c', '\x00', '\x01', '\x22', '\xc1', '\x22', '\xc7', '\x80',
+ '\x63', '\xa6', '\xbe', '\x3f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x98', '\xe2', '\xfe', '\x5b', '\x6a', '\x16',
+ '\x6b', '\x56', '\x6c', '\x36', '\x70', '\x86', '\xed', '\x06',
+ '\x74', '\xa0', '\x6d', '\x46', '\x05', '\x11', '\x49', '\x9a',
+ '\xcf', '\x9e', '\x02', '\x00', '\x12', '\x20', '\x0f', '\x05',
+ '\x43', '\x05', '\x59', '\x9a', '\xdf', '\x9e', '\xff', '\xff',
+ '\x54', '\x30', '\x42', '\x22', '\x05', '\x11', '\x49', '\x9a',
+ '\xcf', '\x9e', '\x04', '\x00', '\x0e', '\x20', '\x61', '\xa6',
+ '\x43', '\x05', '\x69', '\x9a', '\xff', '\x92', '\x3e', '\x30',
+ '\x44', '\x22', '\x61', '\xa6', '\x3f', '\xbd', '\xae', '\x0c',
+ '\x00', '\x38', '\x61', '\xa6', '\x4f', '\xbc', '\xa0', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\x66', '\x0c',
+ '\x00', '\x38', '\x65', '\xb6', '\x20', '\xb6', '\x63', '\xc6',
+ '\x20', '\xc6', '\x61', '\xa6', '\x3f', '\xbd', '\x3a', '\x0c',
+ '\x00', '\x38', '\x6a', '\x26', '\x61', '\xa6', '\x65', '\xb6',
+ '\x20', '\xb6', '\x3f', '\xbd', '\xda', '\x0c', '\x00', '\x38',
+ '\x6a', '\xa6', '\xf3', '\x20', '\x61', '\xa6', '\x22', '\x06',
+ '\xe4', '\x06', '\x91', '\xb0', '\x0f', '\x05', '\xbe', '\x5f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\xa4', '\xe2',
+ '\xfe', '\x8b', '\x6a', '\x16', '\x6b', '\x06', '\x6c', '\x86',
+ '\x3f', '\xbd', '\x6c', '\x14', '\x00', '\x38', '\x6a', '\x96',
+ '\x1a', '\x30', '\x41', '\xa2', '\x60', '\xd6', '\x28', '\xd6',
+ '\xe9', '\xd6', '\x14', '\x80', '\x0f', '\x05', '\x6f', '\xae',
+ '\xb8', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\x42', '\xa2', '\xbe', '\x8f', '\x3e', '\x0d',
+ '\x6f', '\xce', '\x54', '\x1b', '\x00', '\x38', '\x6c', '\xca',
+ '\xec', '\x06', '\x1e', '\x10', '\xec', '\xd6', '\x6f', '\x9e',
+ '\x26', '\x1c', '\x00', '\x38', '\x09', '\x91', '\x70', '\x8a',
+ '\x16', '\x91', '\xe1', '\x1b', '\xac', '\x06', '\x1a', '\x91',
+ '\xe0', '\x0b', '\x1e', '\x91', '\xe8', '\x8b', '\x74', '\xe0',
+ '\x0f', '\x05', '\x5a', '\x80', '\x6c', '\x96', '\x6f', '\xde',
+ '\x26', '\x1c', '\x00', '\x38', '\x01', '\xd1', '\xe1', '\x1b',
+ '\x05', '\xd1', '\xe0', '\x0b', '\xa0', '\x96', '\x09', '\xd1',
+ '\xe9', '\x9b', '\x29', '\x16', '\x16', '\xd1', '\xe1', '\x1b',
+ '\x1a', '\xd1', '\x70', '\x8a', '\x68', '\xc6', '\xa9', '\xc6',
+ '\x1e', '\xd1', '\xec', '\xcb', '\x46', '\xe0', '\x0f', '\x05',
+ '\x6f', '\xae', '\xd4', '\x1a', '\x00', '\x38', '\x3f', '\xbd',
+ '\x1a', '\x05', '\x00', '\x38', '\x44', '\xa2', '\xbe', '\x8f',
+ '\x3e', '\x0d', '\x6f', '\xae', '\xe8', '\x1a', '\x00', '\x38',
+ '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38', '\x60', '\xa6',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x60', '\x05', '\x00', '\x38',
+ '\x43', '\xa2', '\xbe', '\x8f', '\x3e', '\x0d', '\x6f', '\x9e',
+ '\x26', '\x1c', '\x00', '\x38', '\x01', '\x91', '\xe1', '\x1b',
+ '\x05', '\x91', '\xe0', '\x0b', '\x09', '\x91', '\xe8', '\x8b',
+ '\x1e', '\x91', '\x70', '\x8a', '\x6f', '\xce', '\x26', '\x1c',
+ '\x00', '\x38', '\x7c', '\x0a', '\x0d', '\xc1', '\x70', '\x8a',
+ '\x11', '\xc1', '\x70', '\x8a', '\x15', '\xc1', '\x79', '\x0e',
+ '\x7f', '\x0d', '\x48', '\x1c', '\x00', '\x38', '\x70', '\x8a',
+ '\x7f', '\x0d', '\x4c', '\x1c', '\x00', '\x38', '\x70', '\x8a',
+ '\x0d', '\x91', '\xe8', '\x8a', '\xff', '\x8d', '\xc0', '\x01',
+ '\x75', '\x86', '\x65', '\x56', '\x04', '\x20', '\x6c', '\xd6',
+ '\x15', '\xd2', '\x65', '\x96', '\x29', '\x55', '\x65', '\x36',
+ '\x23', '\x95', '\x09', '\xd1', '\x69', '\x9a', '\x24', '\x30',
+ '\x2c', '\x36', '\x0d', '\xd1', '\xe9', '\x9a', '\x1c', '\x80',
+ '\x0f', '\x05', '\x09', '\x31', '\x69', '\x9a', '\x10', '\x30',
+ '\x0f', '\x05', '\x83', '\x0b', '\x0a', '\x20', '\x0f', '\x05',
+ '\x0d', '\x31', '\xe9', '\x9a', '\x06', '\x20', '\x0f', '\x05',
+ '\x65', '\x56', '\x35', '\x35', '\x11', '\x31', '\x63', '\x3a',
+ '\xca', '\x32', '\x4d', '\x90', '\x65', '\x96', '\x29', '\x55',
+ '\x65', '\x36', '\x23', '\x95', '\x2f', '\x3e', '\x26', '\x1c',
+ '\x00', '\x38', '\x05', '\x31', '\x64', '\x4a', '\x0d', '\x31',
+ '\x69', '\x9a', '\x29', '\x46', '\x01', '\x31', '\x27', '\x9a',
+ '\x65', '\xa6', '\xc3', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\x2f', '\xae', '\x4e', '\x1b',
+ '\x00', '\x38', '\x64', '\xb6', '\x3f', '\xbd', '\xbc', '\x13',
+ '\x00', '\x38', '\x83', '\x0b', '\x24', '\x30', '\x6a', '\x66',
+ '\x65', '\xa6', '\xc3', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\x2f', '\xae', '\x4e', '\x1b',
+ '\x00', '\x38', '\x64', '\xb6', '\x3f', '\xbd', '\xda', '\x0c',
+ '\x00', '\x38', '\x6a', '\xa6', '\xe5', '\x20', '\x65', '\xa6',
+ '\x73', '\x0a', '\x65', '\x26', '\xc3', '\x23', '\xa5', '\x26',
+ '\xc2', '\x23', '\xa5', '\x26', '\xc2', '\x23', '\x2f', '\x2e',
+ '\x4e', '\x1b', '\x00', '\x38', '\x62', '\xa6', '\x4f', '\xbc',
+ '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd',
+ '\x66', '\x0c', '\x00', '\x38', '\x62', '\xa6', '\x64', '\xb6',
+ '\x67', '\xc6', '\x66', '\xd6', '\x3f', '\xbd', '\x0e', '\x14',
+ '\x00', '\x38', '\x4a', '\xa6', '\x28', '\x20', '\x7b', '\x86',
+ '\x0d', '\x31', '\x69', '\xde', '\x26', '\xd6', '\xe9', '\xdb',
+ '\x11', '\x31', '\x70', '\x8a', '\x62', '\xaa', '\x24', '\xa6',
+ '\x3f', '\xbd', '\x60', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\xf2', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\xaa', '\xe0', '\x0f', '\x05', '\xcf', '\xae',
+ '\x01', '\x00', '\x4c', '\x30', '\x0f', '\x05', '\xcf', '\xae',
+ '\x02', '\x00', '\x46', '\x20', '\x65', '\xa6', '\x62', '\xaa',
+ '\x24', '\xa6', '\x6f', '\x1e', '\x60', '\x05', '\x00', '\x38',
+ '\x7b', '\x86', '\xb1', '\xb9', '\x6f', '\x0e', '\x1a', '\x05',
+ '\x00', '\x38', '\x6f', '\xae', '\x06', '\x1b', '\x00', '\x38',
+ '\xb0', '\xb9', '\x66', '\xa6', '\x7b', '\x86', '\xb1', '\xb9',
+ '\x6f', '\xae', '\x12', '\x1b', '\x00', '\x38', '\xb0', '\xb9',
+ '\x62', '\xa6', '\x64', '\xb6', '\x3f', '\xbd', '\x6e', '\x13',
+ '\x00', '\x38', '\x41', '\x92', '\xc3', '\x9b', '\x11', '\x31',
+ '\x6d', '\x9e', '\x01', '\x92', '\x58', '\xe0', '\xed', '\x9b',
+ '\x65', '\xa6', '\xc3', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\x6f', '\xad', '\x4e', '\x1b',
+ '\x00', '\x38', '\x62', '\xae', '\x24', '\xa6', '\x6f', '\x1e',
+ '\x60', '\x05', '\x00', '\x38', '\x7b', '\x86', '\xb1', '\xb9',
+ '\x6f', '\x0e', '\x1a', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\x1a', '\x1b', '\x00', '\x38', '\xb0', '\xb9', '\x66', '\xa6',
+ '\x7b', '\x86', '\xb1', '\xb9', '\x6f', '\xae', '\x12', '\x1b',
+ '\x00', '\x38', '\xb0', '\xb9', '\x62', '\xa6', '\x64', '\xb6',
+ '\x67', '\xc6', '\x66', '\xd6', '\x3f', '\xbd', '\xbe', '\x14',
+ '\x00', '\x38', '\x0d', '\x31', '\x6d', '\x9e', '\x26', '\x96',
+ '\xed', '\x9b', '\x11', '\x31', '\x70', '\x8a', '\x6f', '\xce',
+ '\x26', '\x1c', '\x00', '\x38', '\x0d', '\xc1', '\x69', '\x9a',
+ '\x7f', '\x0d', '\x48', '\x1c', '\x00', '\x38', '\x29', '\x9a',
+ '\xe8', '\x96', '\xff', '\x1d', '\x44', '\xfe', '\x0f', '\x05',
+ '\x75', '\x86', '\x6f', '\x2e', '\x4e', '\x1b', '\x00', '\x38',
+ '\x6f', '\x1e', '\x26', '\x1c', '\x00', '\x38', '\x09', '\x11',
+ '\xa0', '\x0b', '\x4c', '\x30', '\x7b', '\x86', '\x62', '\xaa',
+ '\x3f', '\xbd', '\x60', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\x26', '\x1b', '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05',
+ '\x00', '\x38', '\x70', '\x86', '\x09', '\x11', '\xe0', '\x0a',
+ '\x22', '\x00', '\x0f', '\x05', '\x05', '\x11', '\x29', '\x0a',
+ '\x01', '\x11', '\x6d', '\xda', '\x62', '\x99', '\x59', '\x9a',
+ '\x4d', '\x05', '\xd9', '\x9a', '\xff', '\x2d', '\x9a', '\xfd',
+ '\x0f', '\x05', '\x02', '\x02', '\x09', '\x11', '\xe0', '\x0a',
+ '\xe3', '\x10', '\x0f', '\x05', '\x6f', '\xae', '\x36', '\x1b',
+ '\x00', '\x38', '\x3f', '\xbd', '\x1a', '\x05', '\x00', '\x38',
+ '\x0f', '\x2c', '\x6c', '\x00', '\x01', '\x52', '\xc1', '\x52',
+ '\xa5', '\x80', '\x15', '\x12', '\x7a', '\x86', '\xbe', '\x8f',
+ '\x3e', '\x0d', '\x00', '\x00', '\x7f', '\xb6', '\x0f', '\x05',
+ '\x00', '\x00', '\x00', '\x00', '\x0d', '\x0a', '\x0d', '\x0a',
+ '\x44', '\x65', '\x76', '\x69', '\x63', '\x65', '\x20', '\x49',
+ '\x44', '\x20', '\x3d', '\x20', '\x00', '\x00', '\x43', '\x68',
+ '\x65', '\x63', '\x6b', '\x73', '\x75', '\x6d', '\x20', '\x6f',
+ '\x66', '\x20', '\x62', '\x6f', '\x6f', '\x74', '\x6c', '\x6f',
+ '\x61', '\x64', '\x65', '\x72', '\x20', '\x69', '\x73', '\x20',
+ '\x00', '\x00', '\x57', '\x61', '\x69', '\x74', '\x69', '\x6e',
+ '\x67', '\x20', '\x66', '\x6f', '\x72', '\x20', '\x6c', '\x6f',
+ '\x61', '\x64', '\x20', '\x69', '\x6e', '\x66', '\x6f', '\x2e',
+ '\x0d', '\x0a', '\x00', '\x00', '\x47', '\x6f', '\x74', '\x20',
+ '\x6c', '\x6f', '\x61', '\x64', '\x20', '\x69', '\x6e', '\x66',
+ '\x6f', '\x2e', '\x0d', '\x0a', '\x00', '\x00', '\x50', '\x41',
+ '\x43', '\x4b', '\x45', '\x54', '\x5f', '\x49', '\x4e', '\x46',
+ '\x4f', '\x0d', '\x0a', '\x00', '\x53', '\x45', '\x54', '\x5f',
+ '\x52', '\x45', '\x47', '\x49', '\x53', '\x54', '\x45', '\x52',
+ '\x0d', '\x0a', '\x00', '\x00', '\x47', '\x45', '\x54', '\x5f',
+ '\x52', '\x45', '\x47', '\x49', '\x53', '\x54', '\x45', '\x52',
+ '\x0d', '\x0a', '\x00', '\x00', '\x50', '\x41', '\x55', '\x53',
+ '\x45', '\x5f', '\x4c', '\x4f', '\x4f', '\x50', '\x0d', '\x0a',
+ '\x00', '\x00', '\x4d', '\x45', '\x4d', '\x5f', '\x56', '\x45',
+ '\x52', '\x49', '\x46', '\x59', '\x0d', '\x0a', '\x00', '\x00',
+ '\x76', '\x65', '\x72', '\x69', '\x66', '\x79', '\x20', '\x66',
+ '\x61', '\x69', '\x6c', '\x65', '\x64', '\x0d', '\x0a', '\x00',
+ '\x4d', '\x45', '\x4d', '\x5f', '\x54', '\x45', '\x53', '\x54',
+ '\x0d', '\x0a', '\x00', '\x00', '\x23', '\x23', '\x23', '\x20',
+ '\x4d', '\x65', '\x6d', '\x6f', '\x72', '\x79', '\x20', '\x74',
+ '\x65', '\x73', '\x74', '\x20', '\x66', '\x61', '\x69', '\x6c',
+ '\x65', '\x64', '\x20', '\x61', '\x74', '\x20', '\x00', '\x00',
+ '\x50', '\x61', '\x73', '\x73', '\x65', '\x64', '\x20', '\x6d',
+ '\x65', '\x6d', '\x6f', '\x72', '\x79', '\x20', '\x74', '\x65',
+ '\x73', '\x74', '\x2e', '\x0d', '\x0a', '\x00', '\x4d', '\x45',
+ '\x4d', '\x5f', '\x44', '\x55', '\x4d', '\x50', '\x0d', '\x0a',
+ '\x00', '\x00', '\x4d', '\x45', '\x4d', '\x5f', '\x43', '\x4c',
+ '\x45', '\x41', '\x52', '\x0d', '\x0a', '\x00', '\x46', '\x4c',
+ '\x41', '\x53', '\x48', '\x0d', '\x0a', '\x00', '\x4a', '\x55',
+ '\x4d', '\x50', '\x0d', '\x0a', '\x00', '\x00', '\x45', '\x4e',
+ '\x44', '\x0d', '\x0a', '\x00', '\x23', '\x23', '\x23', '\x20',
+ '\x55', '\x6e', '\x6b', '\x6e', '\x6f', '\x77', '\x6e', '\x20',
+ '\x74', '\x79', '\x70', '\x65', '\x3a', '\x20', '\x00', '\x00',
+ '\x43', '\x68', '\x65', '\x63', '\x6b', '\x73', '\x75', '\x6d',
+ '\x20', '\x6f', '\x66', '\x20', '\x66', '\x69', '\x6c', '\x65',
+ '\x20', '\x69', '\x73', '\x20', '\x00', '\x00', '\x23', '\x23',
+ '\x23', '\x20', '\x4d', '\x65', '\x6d', '\x6f', '\x72', '\x79',
+ '\x20', '\x74', '\x65', '\x73', '\x74', '\x20', '\x31', '\x20',
+ '\x66', '\x61', '\x69', '\x6c', '\x65', '\x64', '\x20', '\x61',
+ '\x74', '\x20', '\x00', '\x00', '\x23', '\x23', '\x23', '\x20',
+ '\x4d', '\x65', '\x6d', '\x6f', '\x72', '\x79', '\x20', '\x74',
+ '\x65', '\x73', '\x74', '\x20', '\x32', '\x20', '\x66', '\x61',
+ '\x69', '\x6c', '\x65', '\x64', '\x20', '\x61', '\x74', '\x20',
+ '\x00', '\x00', '\x20', '\x3a', '\x00', '\x00', '\x38', '\x4d',
+ '\x62', '\x20', '\x42', '\x42', '\x00', '\x00', '\x38', '\x4d',
+ '\x62', '\x20', '\x54', '\x42', '\x00', '\x00', '\x31', '\x36',
+ '\x4d', '\x62', '\x20', '\x42', '\x42', '\x00', '\x31', '\x36',
+ '\x4d', '\x62', '\x20', '\x54', '\x42', '\x00', '\x33', '\x32',
+ '\x4d', '\x62', '\x20', '\x54', '\x42', '\x00', '\x55', '\x6e',
+ '\x73', '\x75', '\x70', '\x70', '\x6f', '\x72', '\x74', '\x65',
+ '\x64', '\x20', '\x69', '\x6e', '\x74', '\x65', '\x72', '\x6c',
+ '\x65', '\x61', '\x76', '\x65', '\x21', '\x0a', '\x00', '\x00',
+ '\x46', '\x6f', '\x75', '\x6e', '\x64', '\x20', '\x31', '\x20',
+ '\x78', '\x20', '\x43', '\x46', '\x49', '\x20', '\x61', '\x74',
+ '\x20', '\x00', '\x54', '\x6f', '\x6f', '\x20', '\x6d', '\x61',
+ '\x6e', '\x79', '\x20', '\x72', '\x65', '\x67', '\x69', '\x6f',
+ '\x6e', '\x73', '\x20', '\x6f', '\x6e', '\x20', '\x63', '\x68',
+ '\x69', '\x70', '\x21', '\x0a', '\x00', '\x00', '\x4e', '\x6f',
+ '\x20', '\x73', '\x69', '\x6e', '\x67', '\x6c', '\x65', '\x20',
+ '\x78', '\x31', '\x36', '\x20', '\x61', '\x74', '\x20', '\x00',
+ '\x4e', '\x6f', '\x20', '\x69', '\x6e', '\x74', '\x65', '\x72',
+ '\x6c', '\x65', '\x61', '\x76', '\x65', '\x64', '\x20', '\x78',
+ '\x31', '\x36', '\x20', '\x61', '\x74', '\x20', '\x00', '\x00',
+ '\x46', '\x6f', '\x75', '\x6e', '\x64', '\x20', '\x00', '\x00',
+ '\x31', '\x00', '\x32', '\x00', '\x20', '\x78', '\x20', '\x00',
+ '\x46', '\x61', '\x74', '\x61', '\x6c', '\x3a', '\x20', '\x66',
+ '\x6c', '\x61', '\x73', '\x68', '\x20', '\x69', '\x73', '\x20',
+ '\x74', '\x6f', '\x6f', '\x20', '\x73', '\x6d', '\x61', '\x6c',
+ '\x6c', '\x2e', '\x0a', '\x00', '\x53', '\x65', '\x63', '\x74',
+ '\x6f', '\x72', '\x20', '\x65', '\x72', '\x61', '\x73', '\x65',
+ '\x20', '\x65', '\x72', '\x72', '\x6f', '\x72', '\x0a', '\x00',
+ '\x45', '\x72', '\x72', '\x6f', '\x72', '\x20', '\x61', '\x74',
+ '\x20', '\x00', '\x3a', '\x20', '\x4e', '\x6f', '\x20', '\x6e',
+ '\x65', '\x65', '\x64', '\x20', '\x74', '\x6f', '\x20', '\x77',
+ '\x72', '\x69', '\x74', '\x65', '\x0a', '\x00', '\x3a', '\x20',
+ '\x45', '\x72', '\x61', '\x73', '\x69', '\x6e', '\x67', '\x20',
+ '\x00', '\x00', '\x20', '\x62', '\x79', '\x74', '\x65', '\x73',
+ '\x0a', '\x00', '\x3a', '\x20', '\x57', '\x72', '\x69', '\x74',
+ '\x69', '\x6e', '\x67', '\x20', '\x00', '\x00', '\x3a', '\x20',
+ '\x56', '\x65', '\x72', '\x69', '\x66', '\x79', '\x69', '\x6e',
+ '\x67', '\x2e', '\x2e', '\x2e', '\x00', '\x00', '\x4f', '\x4b',
+ '\x0a', '\x00', '\x0e', '\x1a', '\x00', '\x38', '\x16', '\x1a',
+ '\x00', '\x38', '\x1e', '\x1a', '\x00', '\x38', '\x26', '\x1a',
+ '\x00', '\x38', '\x2e', '\x1a', '\x00', '\x38', '\x00', '\x00',
+ '\x00', '\x80', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x84', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x54', '\x68', '\x69', '\x73', '\x20', '\x62', '\x6f', '\x6f',
+ '\x74', '\x6c', '\x6f', '\x61', '\x64', '\x65', '\x72', '\x20',
+ '\x77', '\x61', '\x73', '\x20', '\x62', '\x75', '\x69', '\x6c',
+ '\x74', '\x20', '\x62', '\x79', '\x20', '\x72', '\x6f', '\x6f',
+ '\x74', '\x20', '\x6f', '\x6e', '\x20', '\x57', '\x65', '\x64',
+ '\x20', '\x4d', '\x61', '\x79', '\x20', '\x31', '\x36', '\x20',
+ '\x32', '\x31', '\x3a', '\x33', '\x31', '\x3a', '\x34', '\x31',
+ '\x20', '\x43', '\x45', '\x53', '\x54', '\x20', '\x32', '\x30',
+ '\x30', '\x37', '\x2e', '\x0d', '\x0a', '\x00'
+};
diff --git a/package/etrax-tools/src/e100boot/sbl/net_noleds_ima.c b/package/etrax-tools/src/e100boot/sbl/net_noleds_ima.c
new file mode 100644
index 000000000..d5e03d1f2
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/net_noleds_ima.c
@@ -0,0 +1,873 @@
+
+/* cconv 1.2 12/16/97, Copyright (C) 1997, Axis Communications AB */
+
+const char net_noleds_ima[] =
+{
+ '\x0f', '\x05', '\x0f', '\x05', '\x6f', '\xee', '\x00', '\x1f',
+ '\x00', '\x38', '\x3f', '\x0d', '\x08', '\x01', '\x00', '\x38',
+ '\x78', '\x56', '\x34', '\x12', '\x21', '\x43', '\x65', '\x87',
+ '\x6f', '\xde', '\x20', '\x00', '\x00', '\xb0', '\x5f', '\x9c',
+ '\x65', '\x6f', '\xed', '\x9b', '\x5f', '\x9c', '\x25', '\x2f',
+ '\x7f', '\x0d', '\xf0', '\x17', '\x00', '\x38', '\xe9', '\x9b',
+ '\xed', '\x9b', '\x3f', '\x0d', '\x28', '\x01', '\x00', '\x38',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x7f', '\x0d', '\x92', '\x1c',
+ '\x00', '\x38', '\x70', '\x8a', '\x6f', '\x9e', '\x20', '\x00',
+ '\x00', '\xb0', '\x69', '\x9a', '\x79', '\x67', '\x7f', '\x0d',
+ '\x46', '\x1c', '\x00', '\x38', '\xe9', '\x9b', '\x6f', '\x9e',
+ '\x22', '\x00', '\x00', '\xb0', '\x59', '\x9a', '\x59', '\x94',
+ '\x7f', '\x0d', '\xae', '\x1c', '\x00', '\x38', '\xe9', '\x9b',
+ '\x6f', '\x9e', '\x04', '\x00', '\x00', '\xb0', '\x69', '\x9a',
+ '\x06', '\x93', '\xe1', '\x93', '\x81', '\x92', '\x7f', '\x0d',
+ '\x96', '\x1c', '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\x0d',
+ '\x58', '\x1c', '\x00', '\x38', '\x70', '\x4a', '\x3f', '\xbd',
+ '\x28', '\x02', '\x00', '\x38', '\x3f', '\xbd', '\x30', '\x04',
+ '\x00', '\x38', '\x3f', '\xbd', '\xcc', '\x01', '\x00', '\x38',
+ '\x6a', '\xa6', '\xf7', '\x30', '\x0f', '\x05', '\x6f', '\x9e',
+ '\x00', '\x01', '\x00', '\x38', '\x69', '\x9a', '\x7f', '\x0d',
+ '\x92', '\x1c', '\x00', '\x38', '\xe9', '\x9a', '\x24', '\x80',
+ '\x0f', '\x05', '\x6f', '\x9e', '\x96', '\x1c', '\x00', '\x38',
+ '\x49', '\x9a', '\xcf', '\x9e', '\x01', '\x00', '\xd3', '\x20',
+ '\x0f', '\x05', '\x6f', '\xde', '\xd4', '\x01', '\x00', '\xb0',
+ '\x4d', '\x9a', '\x38', '\x93', '\x41', '\x93', '\xcd', '\x9b',
+ '\xc1', '\xe0', '\x0f', '\x05', '\x3e', '\xbe', '\x3f', '\x0d',
+ '\x80', '\x05', '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x3f', '\xbd', '\x62', '\x03', '\x00', '\x38', '\x6a', '\xa6',
+ '\x16', '\x20', '\x41', '\x92', '\x3f', '\xbd', '\xf4', '\x01',
+ '\x00', '\x38', '\x6a', '\xa6', '\x0a', '\x30', '\x79', '\x86',
+ '\x3f', '\xbd', '\x30', '\x04', '\x00', '\x38', '\x79', '\x86',
+ '\x69', '\xa6', '\x3e', '\x0d', '\x84', '\xe2', '\x6f', '\x9e',
+ '\x22', '\x00', '\x00', '\xb0', '\x59', '\x9a', '\x59', '\x94',
+ '\xee', '\x9b', '\x6f', '\xce', '\xae', '\x1c', '\x00', '\x38',
+ '\x6c', '\x9a', '\x6e', '\xda', '\xad', '\x96', '\xb9', '\x96',
+ '\xdf', '\x9c', '\x80', '\x25', '\x0a', '\xd0', '\x0f', '\x05',
+ '\x6e', '\x9a', '\xec', '\x9b', '\x04', '\xe0', '\x41', '\xa2',
+ '\x7a', '\x86', '\x7f', '\xb6', '\x04', '\xe2', '\x00', '\x00',
+ '\x88', '\xe2', '\xfe', '\x1b', '\x6f', '\x9e', '\x8c', '\x00',
+ '\x00', '\xb0', '\x79', '\x8a', '\x69', '\x9a', '\x7f', '\x0d',
+ '\x90', '\x00', '\x00', '\xb0', '\xe9', '\x9b', '\x6f', '\x9e',
+ '\x01', '\x40', '\x8c', '\x00', '\x7f', '\x0d', '\x80', '\x00',
+ '\x00', '\xb0', '\xe9', '\x9b', '\x6f', '\xce', '\x01', '\x00',
+ '\x01', '\x40', '\x7f', '\x0d', '\x84', '\x00', '\x00', '\xb0',
+ '\xec', '\xcb', '\x6f', '\xde', '\x8c', '\x00', '\x01', '\x00',
+ '\x7f', '\x0d', '\x88', '\x00', '\x00', '\xb0', '\xed', '\xdb',
+ '\x41', '\x12', '\x7f', '\x0d', '\x94', '\x00', '\x00', '\xb0',
+ '\xe1', '\x1b', '\x7f', '\x0d', '\xa0', '\x00', '\x00', '\xb0',
+ '\x70', '\x8a', '\x5f', '\x9c', '\x02', '\x01', '\x7f', '\x0d',
+ '\x9c', '\x00', '\x00', '\xb0', '\xe9', '\x9b', '\x43', '\xc2',
+ '\x7f', '\x0d', '\x98', '\x00', '\x00', '\xb0', '\xec', '\xcb',
+ '\x44', '\xd2', '\x7f', '\x0d', '\xd0', '\x01', '\x00', '\xb0',
+ '\xcd', '\xdb', '\x6f', '\x0e', '\xd4', '\x01', '\x00', '\xb0',
+ '\xc0', '\xdb', '\x6f', '\xbe', '\x14', '\x1c', '\x00', '\x38',
+ '\x6b', '\x96', '\x4f', '\xcc', '\x26', '\x00', '\xd9', '\xcf',
+ '\x79', '\x4a', '\x6f', '\xde', '\x4a', '\x1c', '\x00', '\x38',
+ '\x04', '\xb1', '\xed', '\xdb', '\x6f', '\x9e', '\x6c', '\x1c',
+ '\x00', '\x38', '\x08', '\xb1', '\xe9', '\x9b', '\x6d', '\x96',
+ '\x5f', '\xce', '\xdc', '\x05', '\xd9', '\xcf', '\x47', '\xc2',
+ '\xd9', '\xcb', '\x6f', '\x9e', '\x04', '\x01', '\x00', '\x38',
+ '\x69', '\x9a', '\x08', '\xd1', '\xe9', '\x9b', '\x6f', '\xce',
+ '\x2a', '\x1c', '\x00', '\x38', '\x6f', '\x9e', '\x00', '\x8c',
+ '\x40', '\x02', '\x79', '\x67', '\x6c', '\xd6', '\xed', '\x9f',
+ '\x5f', '\x9e', '\x00', '\x01', '\x79', '\x27', '\xdd', '\x9b',
+ '\x6c', '\xa6', '\x86', '\xa2', '\x4f', '\x9c', '\x40', '\x00',
+ '\x79', '\x27', '\x06', '\xc1', '\xd9', '\x9b', '\x6f', '\x9e',
+ '\x00', '\x03', '\xaa', '\xaa', '\x79', '\x67', '\x08', '\xc1',
+ '\xe9', '\x9b', '\x6f', '\x9e', '\x56', '\x88', '\x8c', '\x40',
+ '\x79', '\x67', '\x0c', '\xc1', '\xe9', '\x9b', '\x7e', '\x92',
+ '\x79', '\x67', '\x10', '\xc1', '\xe9', '\x9b', '\x14', '\xc1',
+ '\x70', '\x8a', '\x18', '\xc1', '\x70', '\x8a', '\x6f', '\xde',
+ '\x9e', '\x1c', '\x00', '\x38', '\x6d', '\x96', '\x4f', '\xcc',
+ '\x26', '\x00', '\xd9', '\xcf', '\x47', '\xc2', '\xd9', '\xcb',
+ '\x08', '\xd1', '\xea', '\xab', '\x7f', '\x0d', '\x5a', '\x1c',
+ '\x00', '\x38', '\x70', '\x0a', '\x7f', '\x0d', '\x9a', '\x1c',
+ '\x00', '\x38', '\x70', '\x8a', '\x7f', '\x0d', '\xa4', '\x01',
+ '\x00', '\xb0', '\xeb', '\xbb', '\xc0', '\x1b', '\x7f', '\xb6',
+ '\xbe', '\x1f', '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2',
+ '\xfe', '\x0b', '\x6f', '\x0e', '\x4a', '\x1c', '\x00', '\x38',
+ '\x0e', '\x01', '\x5d', '\x9e', '\x81', '\x93', '\xb4', '\xa0',
+ '\x7a', '\x86', '\x7d', '\x4a', '\x6f', '\x9e', '\x14', '\x1c',
+ '\x00', '\x38', '\x7f', '\x0d', '\xa4', '\x01', '\x00', '\xb0',
+ '\xe9', '\x9b', '\x6f', '\xde', '\x86', '\x1c', '\x00', '\x38',
+ '\x6d', '\xda', '\x7d', '\x67', '\x6f', '\x9e', '\x9a', '\x1c',
+ '\x00', '\x38', '\x69', '\x9a', '\x01', '\x92', '\xe9', '\xd6',
+ '\x8a', '\x20', '\x41', '\xa2', '\x41', '\x92', '\x7f', '\x0d',
+ '\x96', '\x1c', '\x00', '\x38', '\xc9', '\x9b', '\x6f', '\x9e',
+ '\x20', '\x00', '\x00', '\xb0', '\x69', '\x9a', '\xf0', '\x93',
+ '\x7f', '\x0d', '\xae', '\x1c', '\x00', '\x38', '\xe9', '\x9b',
+ '\x6f', '\xae', '\x92', '\x1c', '\x00', '\x38', '\x0c', '\x01',
+ '\x5b', '\xb8', '\x6a', '\xda', '\x2b', '\xd6', '\x84', '\xd2',
+ '\xea', '\xdb', '\x08', '\x01', '\x6c', '\x9e', '\x2b', '\x96',
+ '\x84', '\x92', '\xec', '\x9b', '\x60', '\xc6', '\x6f', '\xbe',
+ '\x00', '\x01', '\x00', '\x38', '\x6b', '\x9a', '\xad', '\x96',
+ '\x84', '\x92', '\xdf', '\x9c', '\xdb', '\x05', '\x0a', '\x90',
+ '\x0f', '\x05', '\x6b', '\x9a', '\x9a', '\x9a', '\x06', '\xe0',
+ '\x04', '\x92', '\x5f', '\x9e', '\xdc', '\x05', '\xdc', '\x9b',
+ '\x6f', '\xce', '\x4a', '\x1c', '\x00', '\x38', '\x5c', '\xda',
+ '\x5d', '\x94', '\x26', '\x92', '\xcf', '\x9c', '\x3f', '\x00',
+ '\x04', '\x90', '\x0f', '\x05', '\x5a', '\xd2', '\xdc', '\xdb',
+ '\x6f', '\xde', '\x9a', '\x1c', '\x00', '\x38', '\x6d', '\x9a',
+ '\x01', '\x92', '\xed', '\x9b', '\x3f', '\xbd', '\x30', '\x04',
+ '\x00', '\x38', '\x41', '\xa2', '\xbe', '\x0f', '\x3e', '\x0d',
+ '\x6f', '\x9e', '\x5a', '\x1c', '\x00', '\x38', '\x89', '\x0b',
+ '\x44', '\x20', '\x41', '\xc2', '\xc9', '\xcb', '\x6f', '\x9e',
+ '\x04', '\x00', '\x00', '\xb0', '\x69', '\x9a', '\x06', '\x93',
+ '\xc4', '\x92', '\x1e', '\x20', '\x0f', '\x05', '\x6f', '\x9e',
+ '\x24', '\x1c', '\x00', '\x38', '\x6f', '\xde', '\xdc', '\x00',
+ '\x00', '\x38', '\x6d', '\xda', '\xe9', '\xdf', '\x6f', '\xce',
+ '\xe0', '\x00', '\x00', '\x38', '\x5c', '\xca', '\x16', '\xe0',
+ '\xd9', '\xcb', '\x6f', '\xde', '\x24', '\x1c', '\x00', '\x38',
+ '\x6f', '\x9e', '\x72', '\x1c', '\x00', '\x38', '\x69', '\xce',
+ '\xed', '\xcf', '\x59', '\x9a', '\xdd', '\x9b', '\x6f', '\xde',
+ '\x24', '\x1c', '\x00', '\x38', '\x6f', '\x9e', '\x9a', '\x1c',
+ '\x00', '\x38', '\x69', '\x9a', '\x79', '\x67', '\x1a', '\xd1',
+ '\xe9', '\x9b', '\x42', '\x92', '\x79', '\x67', '\x1e', '\xd1',
+ '\xe9', '\x9b', '\x6f', '\x9e', '\x9e', '\x1c', '\x00', '\x38',
+ '\x47', '\xd2', '\x02', '\x91', '\xdd', '\xdb', '\x4f', '\xcc',
+ '\x26', '\x00', '\xd9', '\xcb', '\x3f', '\x0d', '\xb2', '\x04',
+ '\x00', '\x38', '\x6f', '\x9e', '\x9e', '\x1c', '\x00', '\x38',
+ '\x7f', '\x0d', '\xa0', '\x01', '\x00', '\xb0', '\xe9', '\x9b',
+ '\x41', '\x92', '\x7f', '\x0d', '\xd0', '\x01', '\x00', '\xb0',
+ '\xc9', '\x9b', '\x6f', '\x9e', '\xa0', '\x01', '\x00', '\xb0',
+ '\x69', '\x9a', '\xf7', '\x20', '\x0f', '\x05', '\x7f', '\xb6',
+ '\x0f', '\x05', '\x6f', '\x9e', '\x9e', '\x1c', '\x00', '\x38',
+ '\x6f', '\xce', '\x5c', '\x1c', '\x00', '\x38', '\x04', '\x91',
+ '\xec', '\xcb', '\x02', '\x91', '\x70', '\x4a', '\x8a', '\x0b',
+ '\x0c', '\x30', '\x7d', '\x86', '\x01', '\xd2', '\x4a', '\xd5',
+ '\x80', '\x0b', '\xf9', '\x20', '\x0f', '\x05', '\x7f', '\x0d',
+ '\x42', '\x1c', '\x00', '\x38', '\x70', '\x8a', '\x6f', '\x9e',
+ '\x5c', '\x1c', '\x00', '\x38', '\x47', '\xc2', '\x02', '\x91',
+ '\xdc', '\xcb', '\x08', '\x91', '\xea', '\xab', '\x01', '\xd2',
+ '\xd9', '\xdb', '\x3f', '\x0d', '\xb2', '\x04', '\x00', '\x38',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2', '\xee', '\xab',
+ '\x6f', '\x9e', '\x9e', '\x1c', '\x00', '\x38', '\x6f', '\xde',
+ '\x5c', '\x1c', '\x00', '\x38', '\x04', '\x91', '\xed', '\xdb',
+ '\x02', '\x91', '\x70', '\x4a', '\x4b', '\xb6', '\x04', '\x20',
+ '\x46', '\x92', '\x45', '\x92', '\x79', '\x67', '\x7f', '\x0d',
+ '\x42', '\x1c', '\x00', '\x38', '\xe9', '\x9b', '\x79', '\x86',
+ '\x01', '\x92', '\xdf', '\x9c', '\x00', '\x40', '\xf9', '\x20',
+ '\x0f', '\x05', '\x6e', '\x9a', '\x79', '\x67', '\xee', '\x9b',
+ '\x6f', '\x9e', '\x5c', '\x1c', '\x00', '\x38', '\x47', '\xd2',
+ '\x02', '\x91', '\xdd', '\xdb', '\x08', '\x91', '\xee', '\xeb',
+ '\x44', '\xd2', '\xd9', '\xdb', '\x3f', '\xbd', '\xb2', '\x04',
+ '\x00', '\x38', '\x04', '\xe2', '\x3e', '\x0d', '\x00', '\x00',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2', '\xfe', '\x0b',
+ '\x6f', '\x0e', '\xda', '\x04', '\x00', '\x38', '\x6f', '\xae',
+ '\xf4', '\x17', '\x00', '\x38', '\xb0', '\xb9', '\x6f', '\xae',
+ '\x46', '\x1c', '\x00', '\x38', '\x6a', '\xaa', '\x7a', '\x67',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x20', '\x05', '\x00', '\x38',
+ '\x6f', '\xae', '\xc0', '\x1b', '\x00', '\x38', '\xb0', '\xb9',
+ '\x6f', '\x9e', '\xf0', '\x00', '\x00', '\x38', '\xef', '\x9e',
+ '\x06', '\x1c', '\x00', '\x38', '\x0e', '\x30', '\x70', '\x86',
+ '\x09', '\x0c', '\xef', '\x9e', '\x06', '\x1c', '\x00', '\x38',
+ '\xf7', '\x20', '\x0f', '\x05', '\x6f', '\xae', '\x06', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38',
+ '\x60', '\xa6', '\x41', '\xb2', '\x3f', '\xbd', '\x20', '\x05',
+ '\x00', '\x38', '\x3f', '\xbd', '\xf6', '\x05', '\x00', '\x38',
+ '\x3f', '\x0d', '\x28', '\x01', '\x00', '\x38', '\xbe', '\x0f',
+ '\x3e', '\x0d', '\xff', '\xe0', '\x0f', '\x05', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x84', '\xe2', '\xfe', '\x0b', '\x6f', '\x0e',
+ '\xda', '\x04', '\x00', '\x38', '\x6f', '\xae', '\x22', '\x18',
+ '\x00', '\x38', '\xb0', '\xb9', '\x3f', '\xbd', '\x30', '\x04',
+ '\x00', '\x38', '\x6f', '\xae', '\x00', '\x1f', '\x00', '\x38',
+ '\x5f', '\xbc', '\xec', '\x01', '\x3f', '\xbd', '\x74', '\x09',
+ '\x00', '\x38', '\x6f', '\xae', '\x3c', '\x18', '\x00', '\x38',
+ '\xb0', '\xb9', '\x3f', '\xbd', '\x3a', '\x06', '\x00', '\x38',
+ '\xbe', '\x0f', '\x3e', '\xbe', '\x3f', '\x0d', '\xf2', '\x05',
+ '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe', '\x98', '\xe2',
+ '\xfe', '\x4b', '\x6f', '\xde', '\x00', '\x1f', '\x00', '\x38',
+ '\x6d', '\x9a', '\x79', '\x67', '\xed', '\x9f', '\xef', '\xde',
+ '\xec', '\x20', '\x00', '\x38', '\xf3', '\x20', '\x0f', '\x05',
+ '\x6f', '\x3e', '\x00', '\x1f', '\x00', '\x38', '\xa3', '\x0b',
+ '\xff', '\x3d', '\xfe', '\x02', '\x0f', '\x05', '\x63', '\x9a',
+ '\x81', '\x92', '\xcf', '\x9d', '\x0b', '\x00', '\x5f', '\x95',
+ '\x3f', '\xf8', '\x54', '\x02', '\x22', '\x01', '\x18', '\x00',
+ '\x62', '\x00', '\x90', '\x00', '\x96', '\x01', '\xc8', '\x01',
+ '\xe4', '\x00', '\x00', '\x02', '\xb8', '\x00', '\x9a', '\x02',
+ '\xce', '\x02', '\x6f', '\xae', '\x4e', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38', '\x6f', '\x0e',
+ '\x20', '\x05', '\x00', '\x38', '\x04', '\x31', '\x62', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x6f', '\x0e', '\x9a', '\x1c',
+ '\x00', '\x38', '\x60', '\x9a', '\x81', '\x92', '\xe0', '\x9b',
+ '\x3f', '\xbd', '\x30', '\x04', '\x00', '\x38', '\x60', '\x9a',
+ '\x01', '\x92', '\xe0', '\x9b', '\x62', '\xaa', '\x61', '\xba',
+ '\x3f', '\xbd', '\x74', '\x09', '\x00', '\x38', '\xff', '\xed',
+ '\x88', '\x02', '\x0c', '\x32', '\x6f', '\xae', '\x5c', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38',
+ '\x6f', '\x0e', '\x20', '\x05', '\x00', '\x38', '\x04', '\x31',
+ '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31',
+ '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x61', '\x1a',
+ '\x72', '\x09', '\xe1', '\x1b', '\xff', '\xed', '\x5a', '\x02',
+ '\x0c', '\x32', '\x6f', '\xae', '\x6c', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38', '\x6f', '\x1e',
+ '\x20', '\x05', '\x00', '\x38', '\x04', '\x31', '\x60', '\xae',
+ '\x41', '\xb2', '\xb1', '\xb9', '\x60', '\xaa', '\x6a', '\xaa',
+ '\x41', '\xb2', '\xb1', '\xb9', '\xff', '\xed', '\x32', '\x02',
+ '\x08', '\x32', '\x6f', '\xae', '\x7c', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38', '\x04', '\x31',
+ '\x60', '\xae', '\x41', '\xb2', '\x3f', '\xbd', '\x20', '\x05',
+ '\x00', '\x38', '\x60', '\xaa', '\xff', '\x3d', '\xc0', '\x01',
+ '\x0f', '\x05', '\x81', '\xa2', '\xfd', '\x20', '\x0f', '\x05',
+ '\xff', '\xed', '\x06', '\x02', '\x08', '\x32', '\x6f', '\x4e',
+ '\xda', '\x04', '\x00', '\x38', '\x6f', '\xae', '\x8a', '\x18',
+ '\x00', '\x38', '\xb4', '\xb9', '\x6f', '\x0e', '\x20', '\x05',
+ '\x00', '\x38', '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x62', '\x2a', '\x62', '\x2a', '\xe1', '\x2a',
+ '\xff', '\x3d', '\xb8', '\x01', '\x0f', '\x05', '\x6f', '\xae',
+ '\x98', '\x18', '\x00', '\x38', '\xb4', '\xb9', '\xff', '\xed',
+ '\xd0', '\x01', '\x0f', '\x05', '\x6f', '\x4e', '\xda', '\x04',
+ '\x00', '\x38', '\x6f', '\xae', '\xa8', '\x18', '\x00', '\x38',
+ '\xb4', '\xb9', '\x6f', '\x2e', '\x20', '\x05', '\x00', '\x38',
+ '\x04', '\x31', '\x61', '\xae', '\x41', '\xb2', '\xb2', '\xb9',
+ '\x08', '\x31', '\x60', '\xae', '\x41', '\xb2', '\xb2', '\xb9',
+ '\x61', '\xaa', '\x60', '\xba', '\x6e', '\xc6', '\x14', '\xc2',
+ '\x3f', '\xbd', '\x72', '\x0a', '\x00', '\x38', '\x6a', '\xa6',
+ '\x30', '\x20', '\x0f', '\x05', '\x6f', '\xae', '\xb4', '\x18',
+ '\x00', '\x38', '\xb4', '\xb9', '\x14', '\xe1', '\x6a', '\xaa',
+ '\x41', '\xb2', '\xb2', '\xb9', '\x14', '\xe1', '\x6a', '\xaa',
+ '\x6a', '\xb6', '\x0f', '\xbc', '\x40', '\x00', '\x8f', '\xac',
+ '\x40', '\x00', '\x3c', '\xa3', '\x3c', '\xb3', '\x3f', '\xbd',
+ '\x1a', '\x0b', '\x00', '\x38', '\xff', '\xed', '\x6a', '\x01',
+ '\x0f', '\x05', '\x6f', '\xae', '\xd0', '\x18', '\x00', '\x38',
+ '\xb4', '\xb9', '\xff', '\xed', '\x54', '\x01', '\x0c', '\x32',
+ '\x6f', '\xae', '\xe6', '\x18', '\x00', '\x38', '\x3f', '\xbd',
+ '\xda', '\x04', '\x00', '\x38', '\x6f', '\x0e', '\x20', '\x05',
+ '\x00', '\x38', '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x62', '\xaa', '\x61', '\xba', '\x3f', '\xbd',
+ '\x1a', '\x0b', '\x00', '\x38', '\xff', '\xed', '\x22', '\x01',
+ '\x0c', '\x32', '\x6f', '\xae', '\xf2', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38', '\x6f', '\x0e',
+ '\x20', '\x05', '\x00', '\x38', '\x04', '\x31', '\x62', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x62', '\xaa', '\xe1', '\xaa',
+ '\xda', '\x90', '\x0f', '\x05', '\x7a', '\x0e', '\x08', '\x31',
+ '\xea', '\xaa', '\xf9', '\x80', '\x0f', '\x05', '\xea', '\xe0',
+ '\x0c', '\x32', '\x6f', '\xae', '\xfe', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38', '\x6f', '\x0e',
+ '\x20', '\x05', '\x00', '\x38', '\x04', '\x31', '\x61', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31', '\x64', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x0c', '\x31', '\x62', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x6f', '\x0e', '\xba', '\x14',
+ '\x00', '\x38', '\x61', '\xaa', '\x64', '\xba', '\x62', '\xca',
+ '\xb0', '\xb9', '\x6a', '\xa6', '\xac', '\x30', '\x10', '\x32',
+ '\xc3', '\xa2', '\xae', '\x20', '\x7a', '\x86', '\x62', '\xca',
+ '\xef', '\xcd', '\x00', '\x00', '\x01', '\x00', '\x64', '\xba',
+ '\xb0', '\xb9', '\x9e', '\xe0', '\x0f', '\x05', '\x6f', '\xde',
+ '\x24', '\x1c', '\x00', '\x38', '\x6d', '\x9a', '\x7f', '\x0d',
+ '\xc0', '\x01', '\x00', '\xb0', '\xe9', '\x9b', '\x04', '\xd1',
+ '\x59', '\x98', '\x7f', '\x0d', '\xc4', '\x01', '\x00', '\xb0',
+ '\xe9', '\x9b', '\x6f', '\x1e', '\xda', '\x04', '\x00', '\x38',
+ '\x6f', '\xae', '\x06', '\x19', '\x00', '\x38', '\xb1', '\xb9',
+ '\x04', '\x31', '\x60', '\xae', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x20', '\x05', '\x00', '\x38', '\x6f', '\xae', '\x0e', '\x19',
+ '\x00', '\x38', '\xb1', '\xb9', '\x60', '\x9a', '\xb9', '\x09',
+ '\x50', '\xe0', '\x08', '\x32', '\x6f', '\xae', '\x82', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38',
+ '\x6f', '\x0e', '\x20', '\x05', '\x00', '\x38', '\x04', '\x31',
+ '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31',
+ '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x61', '\x1a',
+ '\x61', '\x9a', '\x08', '\x30', '\x81', '\x92', '\xe1', '\x9b',
+ '\x20', '\xe0', '\x62', '\x3a', '\x1c', '\xe0', '\x0c', '\x32',
+ '\x6f', '\xae', '\x14', '\x19', '\x00', '\x38', '\x3f', '\xbd',
+ '\xda', '\x04', '\x00', '\x38', '\x63', '\xaa', '\x41', '\xb2',
+ '\x3f', '\xbd', '\x20', '\x05', '\x00', '\x38', '\x0a', '\xe0',
+ '\x0f', '\x05', '\xa3', '\x0b', '\xff', '\x2d', '\x06', '\xfd',
+ '\x0f', '\x05', '\x6f', '\xae', '\x0e', '\x19', '\x00', '\x38',
+ '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38', '\xbe', '\x4f',
+ '\x04', '\xe2', '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x8c', '\xe2', '\xfe', '\x2b', '\x6a', '\x26', '\x6b', '\x06',
+ '\x7f', '\x0d', '\x92', '\x1c', '\x00', '\x38', '\x70', '\x8a',
+ '\x7f', '\x0d', '\x04', '\x01', '\x00', '\x38', '\xea', '\xab',
+ '\x6f', '\x9e', '\x96', '\x1c', '\x00', '\x38', '\x49', '\x9a',
+ '\xcf', '\x9e', '\x01', '\x00', '\x86', '\x20', '\x0f', '\x05',
+ '\x6f', '\xde', '\x4a', '\x1c', '\x00', '\x38', '\x08', '\xd1',
+ '\xea', '\xab', '\x7f', '\x0d', '\x00', '\x01', '\x00', '\x38',
+ '\xeb', '\xbb', '\x6b', '\x96', '\x04', '\x92', '\xdf', '\x9d',
+ '\xdc', '\x05', '\xdd', '\x9b', '\x6f', '\x9e', '\xa4', '\x01',
+ '\x00', '\xb0', '\x69', '\xda', '\x6f', '\xde', '\x14', '\x1c',
+ '\x00', '\x38', '\xe9', '\xdb', '\x6f', '\xde', '\xd4', '\x01',
+ '\x00', '\xb0', '\x4d', '\x9a', '\x38', '\x93', '\x44', '\x93',
+ '\xcd', '\x9b', '\x6f', '\xde', '\xd4', '\x01', '\x00', '\xb0',
+ '\x4d', '\x9a', '\x07', '\x93', '\xcf', '\x9e', '\x04', '\x00',
+ '\xf7', '\x30', '\x0f', '\x05', '\x4d', '\x9a', '\x38', '\x93',
+ '\x41', '\x93', '\xcd', '\x9b', '\x3f', '\xbd', '\xcc', '\x01',
+ '\x00', '\x38', '\x6a', '\xa6', '\xf7', '\x30', '\x0f', '\x05',
+ '\x6f', '\xce', '\x92', '\x1c', '\x00', '\x38', '\xec', '\x0a',
+ '\x10', '\x80', '\x0f', '\x05', '\x6f', '\xde', '\xd4', '\x01',
+ '\x00', '\xb0', '\x4d', '\x9a', '\x38', '\x93', '\x41', '\x93',
+ '\xcd', '\x9b', '\xec', '\x0a', '\xd7', '\x90', '\x71', '\x86',
+ '\x22', '\xe0', '\x62', '\x96', '\x7f', '\x0d', '\x92', '\x1c',
+ '\x00', '\x38', '\xeb', '\xba', '\x14', '\x80', '\x71', '\x86',
+ '\x3f', '\xbd', '\xcc', '\x01', '\x00', '\x38', '\x7f', '\x0d',
+ '\x92', '\x1c', '\x00', '\x38', '\xe0', '\x0a', '\xf1', '\x90',
+ '\x71', '\x86', '\x62', '\x96', '\x20', '\x96', '\xe9', '\x26',
+ '\x0e', '\x30', '\x62', '\xd6', '\x0d', '\x1c', '\x62', '\x96',
+ '\x20', '\x96', '\xe9', '\xd6', '\xf7', '\x20', '\x0f', '\x05',
+ '\x6f', '\xae', '\x28', '\x19', '\x00', '\x38', '\x3f', '\xbd',
+ '\xda', '\x04', '\x00', '\x38', '\x61', '\xa6', '\x41', '\xb2',
+ '\xbe', '\x2f', '\x3e', '\xbe', '\x3f', '\x0d', '\x20', '\x05',
+ '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe', '\x8c', '\xe2',
+ '\xfe', '\x2b', '\x6b', '\x06', '\x6c', '\x26', '\xeb', '\xa6',
+ '\x40', '\x00', '\x6a', '\xc6', '\xe0', '\xc6', '\x32', '\x00',
+ '\x71', '\x86', '\x6c', '\xb6', '\x6c', '\x96', '\x79', '\x87',
+ '\x61', '\xd6', '\xc3', '\xd3', '\xed', '\x97', '\x49', '\xd6',
+ '\xcb', '\x9b', '\x4b', '\x9a', '\xcd', '\x96', '\x0c', '\x30',
+ '\x7d', '\x87', '\x6f', '\xae', '\x3e', '\x19', '\x00', '\x38',
+ '\x40', '\xe0', '\xe2', '\xbb', '\xcb', '\xdf', '\x01', '\x12',
+ '\xc4', '\x12', '\x06', '\x30', '\xe0', '\xb6', '\xd7', '\x10',
+ '\x6c', '\x96', '\x04', '\xc2', '\xe0', '\xc6', '\xc5', '\x10',
+ '\x0f', '\x05', '\xe0', '\xa6', '\x4e', '\x00', '\x6a', '\xc6',
+ '\xe0', '\xc6', '\x40', '\x00', '\x71', '\x86', '\x6c', '\xa6',
+ '\x61', '\x96', '\xc3', '\x93', '\x6c', '\xd6', '\xe9', '\xd7',
+ '\x4a', '\x9a', '\xcd', '\x96', '\x22', '\x30', '\x01', '\x12',
+ '\x81', '\x12', '\xe2', '\xab', '\x6f', '\xae', '\x5c', '\x19',
+ '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38',
+ '\x62', '\xaa', '\x41', '\xb2', '\x3f', '\xbd', '\x20', '\x05',
+ '\x00', '\x38', '\x7a', '\x86', '\xbe', '\x2f', '\x3e', '\x0d',
+ '\xc4', '\x12', '\x08', '\x30', '\x01', '\xa2', '\xe0', '\xa6',
+ '\xc9', '\x10', '\x61', '\x96', '\x04', '\xc2', '\xe0', '\xc6',
+ '\xb7', '\x10', '\x0f', '\x05', '\x41', '\xa2', '\xbe', '\x2f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x94', '\xe2',
+ '\xfe', '\x4b', '\x6b', '\x26', '\xeb', '\xa6', '\x5a', '\x90',
+ '\x6a', '\x06', '\x60', '\xa6', '\x7b', '\x86', '\x3f', '\xbd',
+ '\x20', '\x05', '\x00', '\x38', '\x6f', '\xae', '\x7a', '\x19',
+ '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38',
+ '\xe2', '\x06', '\x2a', '\x90', '\x74', '\x86', '\x60', '\x16',
+ '\x60', '\x36', '\x6f', '\xae', '\xd0', '\x19', '\x00', '\x38',
+ '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38', '\x63', '\xae',
+ '\x7b', '\x86', '\x3f', '\xbd', '\x20', '\x05', '\x00', '\x38',
+ '\x01', '\x42', '\xc4', '\x42', '\x08', '\x30', '\x04', '\x12',
+ '\xe2', '\x16', '\xdf', '\x80', '\x0f', '\x05', '\x6f', '\xae',
+ '\x38', '\x18', '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04',
+ '\x00', '\x38', '\x10', '\x02', '\xe2', '\x06', '\xad', '\x80',
+ '\x60', '\xa6', '\xbe', '\x4f', '\x3e', '\x0d', '\x00', '\x00',
+ '\x05', '\xa1', '\x49', '\x98', '\xc2', '\x92', '\x0a', '\x30',
+ '\xc4', '\x92', '\x0e', '\x30', '\x0f', '\x05', '\x7f', '\xb6',
+ '\x7a', '\x86', '\x6a', '\xb9', '\x5a', '\xa8', '\x7f', '\xb6',
+ '\x0f', '\x05', '\x6a', '\xb9', '\x6a', '\xaa', '\x7f', '\xb6',
+ '\x0f', '\x05', '\x6a', '\xd6', '\x05', '\xa1', '\x4a', '\xaa',
+ '\x4a', '\x94', '\xc2', '\x92', '\x0a', '\x30', '\xc4', '\x92',
+ '\x10', '\x30', '\x0f', '\x05', '\x7f', '\xb6', '\x7a', '\x86',
+ '\x5c', '\xca', '\x6d', '\xb9', '\xdc', '\xcb', '\x7f', '\xb6',
+ '\x4a', '\xa4', '\x6c', '\xca', '\x6d', '\xb9', '\xec', '\xcb',
+ '\x4a', '\xa4', '\x7f', '\xb6', '\x0f', '\x05', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x84', '\xe2', '\xee', '\xbb', '\x04', '\xa1',
+ '\x49', '\x9a', '\xcf', '\x9e', '\x01', '\x00', '\x06', '\x20',
+ '\x0f', '\x05', '\x24', '\xe0', '\xc1', '\xc3', '\xcf', '\x9e',
+ '\x02', '\x00', '\x0c', '\x20', '\x6b', '\x96', '\xd0', '\x93',
+ '\x69', '\xb7', '\xee', '\xbb', '\x12', '\xe0', '\xc2', '\xc3',
+ '\x6f', '\xae', '\xa6', '\x19', '\x00', '\x38', '\x3f', '\xbd',
+ '\xda', '\x04', '\x00', '\x38', '\x0c', '\xe0', '\x0f', '\x05',
+ '\x6c', '\xb6', '\x6e', '\xc6', '\x3f', '\xbd', '\xaa', '\x0b',
+ '\x00', '\x38', '\x04', '\xe2', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x84', '\xe2', '\xfe', '\x0b', '\x6a', '\x06',
+ '\x4f', '\xbc', '\xaa', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\xd6', '\x0b', '\x00', '\x38', '\x60', '\xa6',
+ '\x4f', '\xbc', '\x55', '\x00', '\x5f', '\xcc', '\xaa', '\x02',
+ '\xbe', '\x0f', '\x3e', '\xbe', '\x3f', '\x0d', '\xd6', '\x0b',
+ '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe', '\x90', '\xe2',
+ '\xfe', '\x3b', '\x6a', '\x26', '\x04', '\xa1', '\x49', '\x9a',
+ '\xcf', '\x9e', '\x02', '\x00', '\x42', '\x20', '\x6b', '\x36',
+ '\x6f', '\x0e', '\x88', '\x0b', '\x00', '\x38', '\xb0', '\xb9',
+ '\x6a', '\x16', '\x62', '\xa6', '\x63', '\xb6', '\xb0', '\xb9',
+ '\x61', '\xd6', '\xf0', '\xd3', '\x1f', '\xdf', '\x40', '\x00',
+ '\x6a', '\x96', '\xf0', '\x93', '\x1f', '\x9f', '\x40', '\x00',
+ '\xe9', '\xd6', '\x14', '\x20', '\x7c', '\x86', '\x2f', '\x1f',
+ '\x40', '\x00', '\x00', '\x00', '\x2f', '\xaf', '\x40', '\x00',
+ '\x00', '\x00', '\xea', '\x16', '\x04', '\x30', '\x0f', '\x05',
+ '\x41', '\xc2', '\x6c', '\xa6', '\xbe', '\x3f', '\x3e', '\x0d',
+ '\x6f', '\x1e', '\x88', '\x0b', '\x00', '\x38', '\xb1', '\xb9',
+ '\x4a', '\x04', '\x0f', '\x0f', '\x40', '\x00', '\x62', '\xa6',
+ '\x63', '\xb6', '\xb1', '\xb9', '\x2f', '\xaf', '\x40', '\x00',
+ '\x00', '\x00', '\xea', '\x06', '\x3a', '\x25', '\xbe', '\x3f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\xa8', '\xe2',
+ '\xfe', '\x8b', '\x6a', '\x36', '\x04', '\xa1', '\x44', '\x9e',
+ '\xcf', '\x9e', '\x02', '\x00', '\x04', '\x20', '\x41', '\x72',
+ '\x42', '\x72', '\x6f', '\x2e', '\xd6', '\x0b', '\x00', '\x38',
+ '\x4f', '\xbc', '\x98', '\x00', '\x4f', '\xcc', '\x55', '\x00',
+ '\xb2', '\xb9', '\x50', '\xb2', '\xe7', '\xb4', '\x6f', '\x1e',
+ '\x88', '\x0b', '\x00', '\x38', '\x63', '\xa6', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x51', '\x00', '\xff', '\x2d', '\x9c', '\x01',
+ '\x63', '\xa6', '\x51', '\xb2', '\xe7', '\xb4', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x52', '\x00', '\xff', '\x2d', '\x8c', '\x01',
+ '\x63', '\xa6', '\x52', '\xb2', '\xe7', '\xb4', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x59', '\x00', '\xff', '\x2d', '\x7c', '\x01',
+ '\x63', '\xa6', '\x24', '\xe1', '\x70', '\x8a', '\x6f', '\xae',
+ '\xc0', '\x19', '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04',
+ '\x00', '\x38', '\x63', '\xaa', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x20', '\x05', '\x00', '\x38', '\x4f', '\xbc', '\x27', '\x00',
+ '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9', '\x41', '\x92',
+ '\xea', '\x94', '\x06', '\x32', '\xe3', '\x9b', '\x86', '\x32',
+ '\x4f', '\xbc', '\x2c', '\x00', '\xe7', '\xb4', '\x63', '\xa6',
+ '\xb1', '\xb9', '\x6a', '\x86', '\x55', '\xb2', '\xe7', '\xb4',
+ '\x63', '\xa6', '\xb1', '\xb9', '\x6a', '\x06', '\x6a', '\xb6',
+ '\x04', '\xb2', '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x30', '\x00', '\x3e', '\x20', '\x63', '\xa6',
+ '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\xb2', '\xb9', '\x63', '\xa6', '\x3f', '\xbd', '\x1e', '\x0c',
+ '\x00', '\x38', '\x63', '\xa6', '\x4f', '\xbc', '\x90', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\xb2', '\xb9', '\x44', '\xb8',
+ '\x2b', '\xb6', '\x63', '\xa6', '\xb1', '\xb9', '\x4a', '\x54',
+ '\x0f', '\x5f', '\x80', '\xff', '\x63', '\xa6', '\x4f', '\xbc',
+ '\x98', '\x00', '\x4f', '\xcc', '\x55', '\x00', '\xb2', '\xb9',
+ '\x10', '\xe0', '\x0f', '\x05', '\x0f', '\x02', '\xe7', '\x04',
+ '\x60', '\xb6', '\xb1', '\xb9', '\xcf', '\xae', '\x03', '\x00',
+ '\x35', '\x35', '\x0a', '\x31', '\xd8', '\x8b', '\xc8', '\x82',
+ '\x12', '\xd0', '\x68', '\x46', '\x6f', '\xae', '\xd2', '\x19',
+ '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38',
+ '\xd2', '\xe0', '\x7a', '\x86', '\x65', '\x56', '\x94', '\x20',
+ '\x81', '\x42', '\x90', '\xe0', '\x74', '\x86', '\xc2', '\x03',
+ '\x60', '\xb6', '\x2f', '\xb2', '\xe7', '\xb4', '\x6f', '\x1e',
+ '\x88', '\x0b', '\x00', '\x38', '\x63', '\xa6', '\xb1', '\xb9',
+ '\x6a', '\x66', '\x60', '\xb6', '\x30', '\xb2', '\xe7', '\xb4',
+ '\x63', '\xa6', '\xb1', '\xb9', '\xc8', '\xa3', '\x6a', '\x67',
+ '\xc8', '\x63', '\x60', '\xb6', '\x2d', '\xb2', '\xe7', '\xb4',
+ '\x63', '\xa6', '\xb1', '\xb9', '\x6a', '\x26', '\x2e', '\x02',
+ '\xe7', '\x04', '\x63', '\xa6', '\x60', '\xb6', '\xb1', '\xb9',
+ '\xc8', '\xa3', '\x6a', '\x27', '\x65', '\x56', '\x0a', '\x30',
+ '\x01', '\x22', '\x68', '\x96', '\xa4', '\x96', '\x04', '\xe0',
+ '\x81', '\x92', '\x64', '\x96', '\x19', '\x95', '\x63', '\xd6',
+ '\x2d', '\x95', '\x6d', '\x96', '\x24', '\xe1', '\x6d', '\xda',
+ '\x0c', '\x91', '\xed', '\xdb', '\x10', '\x91', '\xe6', '\x6b',
+ '\x14', '\x91', '\xe2', '\x2b', '\x62', '\x26', '\x10', '\xd0',
+ '\x0f', '\x05', '\x24', '\xe1', '\x29', '\x6a', '\x24', '\xe1',
+ '\xe9', '\x9b', '\x81', '\x22', '\xf5', '\x20', '\x0f', '\x05',
+ '\x24', '\xe1', '\x6d', '\xda', '\x06', '\x31', '\xed', '\xda',
+ '\x1e', '\x30', '\x65', '\x56', '\x06', '\x30', '\x01', '\x42',
+ '\x81', '\x42', '\x81', '\x42', '\x65', '\x56', '\x0c', '\x30',
+ '\xe8', '\x46', '\x64', '\x46', '\x69', '\xa0', '\x64', '\x06',
+ '\x08', '\xe0', '\x63', '\xa6', '\x61', '\xb0', '\x64', '\x06',
+ '\x63', '\xa6', '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc',
+ '\x55', '\x05', '\x3f', '\xbd', '\xd6', '\x0b', '\x00', '\x38',
+ '\x12', '\xe0', '\x41', '\xa2', '\x4f', '\xbc', '\xf0', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\xd6', '\x0b',
+ '\x00', '\x38', '\x7a', '\x86', '\xbe', '\x8f', '\x04', '\xe2',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x90', '\xe2',
+ '\xfe', '\x3b', '\x06', '\xa1', '\xa0', '\x0b', '\xff', '\x2d',
+ '\x16', '\x04', '\x6a', '\x26', '\x3f', '\xbd', '\xc2', '\x0c',
+ '\x00', '\x38', '\x6a', '\xa6', '\xff', '\x2d', '\x86', '\x03',
+ '\x41', '\xa2', '\x62', '\xa6', '\x3f', '\xbd', '\x1e', '\x0c',
+ '\x00', '\x38', '\x62', '\xa6', '\x4f', '\xbc', '\x90', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\xd6', '\x0b',
+ '\x00', '\x38', '\x6f', '\x1e', '\x88', '\x0b', '\x00', '\x38',
+ '\x62', '\xa6', '\x7b', '\x86', '\xb1', '\xb9', '\x6a', '\x36',
+ '\x04', '\x21', '\x40', '\xbe', '\x4b', '\xb4', '\x2b', '\xb6',
+ '\x62', '\xa6', '\xb1', '\xb9', '\x42', '\x92', '\xc0', '\x9a',
+ '\x1c', '\x20', '\x63', '\xc6', '\xf0', '\xc3', '\x53', '\x94',
+ '\xe9', '\xc6', '\x14', '\x20', '\x63', '\x06', '\x6a', '\xd6',
+ '\xf0', '\xd3', '\x5a', '\x94', '\xe9', '\xd6', '\x0a', '\x20',
+ '\xd0', '\x03', '\x6c', '\x36', '\x6d', '\xa6', '\x63', '\x06',
+ '\xd0', '\x03', '\x6a', '\x07', '\x62', '\xa6', '\x4f', '\xbc',
+ '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd',
+ '\xd6', '\x0b', '\x00', '\x38', '\xef', '\x0e', '\xc0', '\x00',
+ '\x1f', '\x00', '\xff', '\x3d', '\x48', '\x02', '\x0f', '\x05',
+ '\x60', '\x90', '\x0f', '\x05', '\xef', '\x0e', '\xc4', '\x22',
+ '\x01', '\x00', '\xb0', '\x30', '\x0f', '\x05', '\x20', '\x90',
+ '\x0f', '\x05', '\xef', '\x0e', '\x58', '\x22', '\x01', '\x00',
+ '\xff', '\x3d', '\x5a', '\x01', '\x0f', '\x05', '\xef', '\x0e',
+ '\x5b', '\x22', '\x01', '\x00', '\xff', '\x3d', '\x4e', '\x01',
+ '\x0f', '\x05', '\xff', '\xed', '\xb6', '\x02', '\x0f', '\x05',
+ '\xef', '\x0e', '\xda', '\x22', '\x01', '\x00', '\xff', '\x3d',
+ '\x9c', '\x01', '\x0f', '\x05', '\x14', '\x90', '\x0f', '\x05',
+ '\xef', '\x0e', '\xd6', '\x22', '\x01', '\x00', '\xff', '\x3d',
+ '\x8c', '\x01', '\x0f', '\x05', '\xff', '\xed', '\x94', '\x02',
+ '\x0f', '\x05', '\xef', '\x0e', '\x49', '\x22', '\x04', '\x00',
+ '\xc4', '\x30', '\x0f', '\x05', '\xff', '\xed', '\x84', '\x02',
+ '\x0f', '\x05', '\xef', '\x0e', '\xd7', '\x00', '\x20', '\x00',
+ '\xff', '\x3d', '\x6a', '\x01', '\x0f', '\x05', '\x20', '\x90',
+ '\x0f', '\x05', '\xef', '\x0e', '\xc2', '\x00', '\x1f', '\x00',
+ '\xff', '\x3d', '\x00', '\x02', '\x0f', '\x05', '\xef', '\x0e',
+ '\xc9', '\x00', '\x1f', '\x00', '\xff', '\x3d', '\x18', '\x02',
+ '\x0f', '\x05', '\xff', '\xed', '\x56', '\x02', '\x0f', '\x05',
+ '\xef', '\x0e', '\x4f', '\x00', '\x98', '\x00', '\xff', '\x3d',
+ '\x3c', '\x01', '\x0f', '\x05', '\x12', '\x90', '\x0f', '\x05',
+ '\xef', '\x0e', '\x43', '\x00', '\x98', '\x00', '\x76', '\x30',
+ '\x0f', '\x05', '\xff', '\xed', '\x36', '\x02', '\x0f', '\x05',
+ '\xef', '\x0e', '\xc2', '\x00', '\x98', '\x00', '\xff', '\x2d',
+ '\x2a', '\x02', '\x0f', '\x05', '\x6f', '\x1e', '\xb6', '\x1a',
+ '\x00', '\x38', '\x61', '\x1a', '\x6f', '\xde', '\x00', '\x00',
+ '\x20', '\x00', '\x06', '\x21', '\xed', '\xdb', '\x0c', '\x21',
+ '\x70', '\x8a', '\x6f', '\x9e', '\x00', '\x00', '\x01', '\x00',
+ '\x10', '\x21', '\xe9', '\x9b', '\x5f', '\xd2', '\x14', '\x21',
+ '\xed', '\xdb', '\x6f', '\x9e', '\x00', '\x00', '\x1f', '\x00',
+ '\x18', '\x21', '\xe9', '\x9b', '\x1f', '\xdc', '\xe1', '\x7f',
+ '\x1c', '\x21', '\xed', '\xdb', '\x41', '\x92', '\x20', '\x21',
+ '\xe9', '\x9b', '\x6f', '\xde', '\x00', '\x80', '\x1f', '\x00',
+ '\x24', '\x21', '\xed', '\xdb', '\x5f', '\xdc', '\x00', '\x20',
+ '\x28', '\x21', '\xed', '\xdb', '\x42', '\xd2', '\x2c', '\x21',
+ '\xed', '\xdb', '\x6f', '\xde', '\x00', '\xc0', '\x1f', '\x00',
+ '\xff', '\xed', '\x16', '\x01', '\x0f', '\x05', '\x6f', '\x1e',
+ '\xb2', '\x1a', '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x20', '\x00', '\x06', '\x21', '\xe9', '\x9b',
+ '\x0c', '\x21', '\x70', '\x8a', '\x5f', '\x9c', '\x00', '\x40',
+ '\x10', '\x21', '\xe9', '\x9b', '\x41', '\xd2', '\x14', '\x21',
+ '\xed', '\xdb', '\x18', '\x21', '\xe9', '\x9b', '\x5f', '\x9c',
+ '\x00', '\x20', '\x1c', '\x21', '\xe9', '\x9b', '\x42', '\x92',
+ '\x20', '\x21', '\xe9', '\x9b', '\x1f', '\x9c', '\xfe', '\x7f',
+ '\x24', '\x21', '\xe9', '\x9b', '\x28', '\x21', '\xe9', '\x9b',
+ '\x2c', '\x21', '\xed', '\xdb', '\x6f', '\x9e', '\x00', '\x00',
+ '\x01', '\x00', '\x30', '\x21', '\xe9', '\x9b', '\x34', '\x21',
+ '\xe9', '\x9b', '\x58', '\xe0', '\x5f', '\xd2', '\x6f', '\x1e',
+ '\xaa', '\x1a', '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x10', '\x00', '\x06', '\x21', '\xe9', '\x9b',
+ '\x0c', '\x21', '\x70', '\x8a', '\x5f', '\x9c', '\x00', '\x40',
+ '\x10', '\x21', '\xe9', '\x9b', '\x41', '\xd2', '\x14', '\x21',
+ '\xed', '\xdb', '\x18', '\x21', '\xe9', '\x9b', '\x5f', '\x9c',
+ '\x00', '\x20', '\x1c', '\x21', '\xe9', '\x9b', '\x42', '\x92',
+ '\x20', '\x21', '\xe9', '\x9b', '\x1f', '\x9c', '\xfe', '\x7f',
+ '\x24', '\x21', '\xe9', '\x9b', '\x28', '\x21', '\xe9', '\x9b',
+ '\x2c', '\x21', '\xed', '\xdb', '\x6f', '\x9e', '\x00', '\x00',
+ '\x01', '\x00', '\x30', '\x21', '\xe9', '\x9b', '\x34', '\x21',
+ '\xe9', '\x9b', '\x4f', '\xd2', '\x38', '\x21', '\xed', '\xdb',
+ '\xff', '\xed', '\x3e', '\x01', '\x0f', '\x05', '\x6f', '\x1e',
+ '\xae', '\x1a', '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x10', '\x00', '\x06', '\x21', '\xe9', '\x9b',
+ '\x0c', '\x21', '\x70', '\x8a', '\x6f', '\xde', '\x00', '\x00',
+ '\x01', '\x00', '\x10', '\x21', '\xed', '\xdb', '\x4f', '\x92',
+ '\x14', '\x21', '\xe9', '\x9b', '\x6f', '\xde', '\x00', '\x00',
+ '\x0f', '\x00', '\x18', '\x21', '\xed', '\xdb', '\x1f', '\x9c',
+ '\xf1', '\x7f', '\x1c', '\x21', '\xe9', '\x9b', '\x41', '\x92',
+ '\x20', '\x21', '\xe9', '\x9b', '\x6f', '\xde', '\x00', '\x80',
+ '\x0f', '\x00', '\x24', '\x21', '\xed', '\xdb', '\x5f', '\xdc',
+ '\x00', '\x20', '\x28', '\x21', '\xed', '\xdb', '\x42', '\xd2',
+ '\x2c', '\x21', '\xed', '\xdb', '\x6f', '\xde', '\x00', '\xc0',
+ '\x0f', '\x00', '\x30', '\x21', '\xed', '\xdb', '\x5f', '\xdc',
+ '\x00', '\x40', '\x34', '\x21', '\xed', '\xdb', '\x38', '\x21',
+ '\xe9', '\x9b', '\xce', '\xe0', '\x0f', '\x05', '\x6f', '\x1e',
+ '\xb2', '\x1a', '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x20', '\x00', '\x06', '\x21', '\xe9', '\x9b',
+ '\x0c', '\x21', '\x70', '\x8a', '\x5f', '\xdc', '\x00', '\x20',
+ '\x10', '\x21', '\xed', '\xdb', '\x48', '\x92', '\x14', '\x21',
+ '\xe9', '\x9b', '\x6f', '\x9e', '\x00', '\x00', '\x01', '\x00',
+ '\x18', '\x21', '\xe9', '\x9b', '\x1c', '\x21', '\xe9', '\x9b',
+ '\x62', '\xe0', '\x5f', '\xd2', '\x6f', '\x1e', '\xb6', '\x1a',
+ '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00',
+ '\x20', '\x00', '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21',
+ '\x70', '\x8a', '\x6f', '\xde', '\x00', '\x00', '\x01', '\x00',
+ '\x10', '\x21', '\xed', '\xdb', '\x26', '\xe0', '\x5f', '\x92',
+ '\x6f', '\x1e', '\xba', '\x1a', '\x00', '\x38', '\x61', '\x1a',
+ '\x6f', '\x9e', '\x00', '\x00', '\x40', '\x00', '\x06', '\x21',
+ '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a', '\x6f', '\xde',
+ '\x00', '\x00', '\x01', '\x00', '\x10', '\x21', '\xed', '\xdb',
+ '\x4f', '\x9c', '\x3f', '\x00', '\x14', '\x21', '\xe9', '\x9b',
+ '\x6f', '\xde', '\x00', '\x00', '\x1f', '\x00', '\x18', '\x21',
+ '\xed', '\xdb', '\x5f', '\x9c', '\x00', '\x20', '\x1c', '\x21',
+ '\xe9', '\x9b', '\x48', '\xd2', '\x20', '\x21', '\xed', '\xdb',
+ '\x30', '\xe0', '\x0f', '\x05', '\x04', '\x21', '\x49', '\x9a',
+ '\x6f', '\xae', '\xee', '\x19', '\x00', '\x38', '\xcf', '\x9e',
+ '\x01', '\x00', '\x08', '\x30', '\x0f', '\x05', '\x6f', '\xae',
+ '\x00', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04',
+ '\x00', '\x38', '\x62', '\xaa', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x20', '\x05', '\x00', '\x38', '\x7a', '\x86', '\xbe', '\x3f',
+ '\x3e', '\x0d', '\x6f', '\x3e', '\xda', '\x04', '\x00', '\x38',
+ '\x6f', '\xae', '\x18', '\x1a', '\x00', '\x38', '\xb3', '\xb9',
+ '\x04', '\x21', '\x40', '\x9e', '\xcf', '\x9e', '\x01', '\x00',
+ '\x0c', '\x20', '\x42', '\xd2', '\x6f', '\xae', '\x20', '\x1a',
+ '\x00', '\x38', '\xb3', '\xb9', '\x42', '\xd2', '\xc0', '\xda',
+ '\x32', '\x20', '\x47', '\xc2', '\x06', '\x21', '\x6d', '\x9e',
+ '\xc1', '\x93', '\xed', '\x9b', '\x62', '\xd6', '\x0c', '\xd1',
+ '\x69', '\x9a', '\xc1', '\x93', '\x0c', '\xd1', '\xe9', '\x9b',
+ '\x10', '\xd1', '\x69', '\x9a', '\xc1', '\x93', '\x10', '\xd1',
+ '\xe9', '\x9b', '\x81', '\xc2', '\xe9', '\x60', '\x0c', '\xd2',
+ '\x6f', '\xae', '\x22', '\x1a', '\x00', '\x38', '\x3f', '\xbd',
+ '\xda', '\x04', '\x00', '\x38', '\x6f', '\x0e', '\xda', '\x04',
+ '\x00', '\x38', '\x6f', '\xae', '\x24', '\x1a', '\x00', '\x38',
+ '\xb0', '\xb9', '\x61', '\xa6', '\xb0', '\xb9', '\x6f', '\xae',
+ '\x56', '\x19', '\x00', '\x38', '\xb0', '\xb9', '\x62', '\xaa',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x20', '\x05', '\x00', '\x38',
+ '\x41', '\xa2', '\xbe', '\x3f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x8c', '\xe2', '\xfe', '\x2b', '\x6a', '\x16',
+ '\x6b', '\x26', '\x6f', '\x0e', '\x1e', '\x0c', '\x00', '\x38',
+ '\xb0', '\xb9', '\x61', '\xa6', '\x4f', '\xbc', '\x80', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\xd6', '\x0b',
+ '\x00', '\x38', '\x61', '\xa6', '\xb0', '\xb9', '\x04', '\x11',
+ '\x49', '\x9a', '\xcf', '\x9e', '\x02', '\x00', '\x10', '\x20',
+ '\x0f', '\x05', '\x6f', '\x9e', '\x30', '\x00', '\x30', '\x00',
+ '\x61', '\x29', '\xe9', '\x9b', '\xbe', '\x2f', '\x3e', '\x0d',
+ '\x4f', '\x9c', '\x30', '\x00', '\x61', '\x29', '\xd9', '\x9b',
+ '\xbe', '\x2f', '\x3e', '\x0d', '\x84', '\xe2', '\xfe', '\x0b',
+ '\x06', '\xa1', '\xeb', '\xba', '\x10', '\x10', '\x0f', '\x05',
+ '\x7a', '\x86', '\x7f', '\xb6', '\xbe', '\x0f', '\x10', '\xa1',
+ '\x6a', '\xaa', '\x7f', '\xb6', '\xbe', '\x0f', '\x70', '\x86',
+ '\x0c', '\xa1', '\xeb', '\xba', '\x22', '\x10', '\x7d', '\x86',
+ '\x14', '\xa1', '\xed', '\xda', '\x10', '\x00', '\x79', '\x86',
+ '\x10', '\xa1', '\x6c', '\xca', '\x01', '\x92', '\x14', '\xa1',
+ '\xe9', '\x9a', '\xf9', '\x10', '\x2c', '\xd6', '\x0c', '\xa1',
+ '\x29', '\xda', '\xe9', '\xb6', '\xd1', '\x10', '\x0f', '\x05',
+ '\x01', '\x02', '\xc7', '\x02', '\xd3', '\x80', '\x0c', '\xa2',
+ '\x7a', '\x86', '\x7f', '\xb6', '\xbe', '\x0f', '\x84', '\xe2',
+ '\xfe', '\x0b', '\x6a', '\x06', '\x6b', '\xa6', '\x6d', '\xb6',
+ '\x7d', '\x86', '\xeb', '\xd6', '\x48', '\xa0', '\x0f', '\x05',
+ '\x60', '\x9a', '\x2d', '\x96', '\x49', '\xa5', '\x59', '\x9a',
+ '\x4c', '\xd5', '\xd9', '\x9a', '\x32', '\x30', '\x02', '\xd2',
+ '\x82', '\xd2', '\x6b', '\x96', '\x2a', '\x96', '\xe9', '\xa6',
+ '\x20', '\x00', '\x6a', '\xc6', '\x60', '\xc9', '\x59', '\x9a',
+ '\xdf', '\x9e', '\xff', '\xff', '\x0a', '\x30', '\x02', '\xc2',
+ '\x82', '\xc2', '\x42', '\xa2', '\x7f', '\xb6', '\xbe', '\x0f',
+ '\x6b', '\x96', '\x2a', '\x96', '\xe9', '\xc6', '\xe5', '\x10',
+ '\x0f', '\x05', '\x41', '\xa2', '\x7f', '\xb6', '\xbe', '\x0f',
+ '\xeb', '\xd6', '\xbd', '\xb0', '\x0f', '\x05', '\x7a', '\x86',
+ '\x7f', '\xb6', '\xbe', '\x0f', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x90', '\xe2', '\xfe', '\x3b', '\x73', '\x86', '\x72', '\x86',
+ '\x6f', '\x0e', '\xbe', '\x1a', '\x00', '\x38', '\x41', '\x12',
+ '\x04', '\x01', '\xc1', '\x1b', '\xcf', '\x1e', '\x01', '\x00',
+ '\x04', '\x30', '\x42', '\x92', '\x44', '\x92', '\x05', '\x01',
+ '\xc9', '\x9b', '\x60', '\xa6', '\x3f', '\xbd', '\xb2', '\x0e',
+ '\x00', '\x38', '\x6a', '\xa6', '\x0c', '\x20', '\x0f', '\x05',
+ '\xc1', '\x13', '\xcf', '\x1e', '\x03', '\x00', '\xd9', '\x80',
+ '\x0f', '\x05', '\x06', '\x01', '\x23', '\x3a', '\x0f', '\x0c',
+ '\x6c', '\x00', '\x01', '\x22', '\xc1', '\x22', '\xc7', '\x80',
+ '\x63', '\xa6', '\xbe', '\x3f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x98', '\xe2', '\xfe', '\x5b', '\x6a', '\x16',
+ '\x6b', '\x56', '\x6c', '\x36', '\x70', '\x86', '\xed', '\x06',
+ '\x74', '\xa0', '\x6d', '\x46', '\x05', '\x11', '\x49', '\x9a',
+ '\xcf', '\x9e', '\x02', '\x00', '\x12', '\x20', '\x0f', '\x05',
+ '\x43', '\x05', '\x59', '\x9a', '\xdf', '\x9e', '\xff', '\xff',
+ '\x54', '\x30', '\x42', '\x22', '\x05', '\x11', '\x49', '\x9a',
+ '\xcf', '\x9e', '\x04', '\x00', '\x0e', '\x20', '\x61', '\xa6',
+ '\x43', '\x05', '\x69', '\x9a', '\xff', '\x92', '\x3e', '\x30',
+ '\x44', '\x22', '\x61', '\xa6', '\x3f', '\xbd', '\x1e', '\x0c',
+ '\x00', '\x38', '\x61', '\xa6', '\x4f', '\xbc', '\xa0', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\xd6', '\x0b',
+ '\x00', '\x38', '\x65', '\xb6', '\x20', '\xb6', '\x63', '\xc6',
+ '\x20', '\xc6', '\x61', '\xa6', '\x3f', '\xbd', '\xaa', '\x0b',
+ '\x00', '\x38', '\x6a', '\x26', '\x61', '\xa6', '\x65', '\xb6',
+ '\x20', '\xb6', '\x3f', '\xbd', '\x4a', '\x0c', '\x00', '\x38',
+ '\x6a', '\xa6', '\xf3', '\x20', '\x61', '\xa6', '\x22', '\x06',
+ '\xe4', '\x06', '\x91', '\xb0', '\x0f', '\x05', '\xbe', '\x5f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\xa4', '\xe2',
+ '\xfe', '\x8b', '\x6a', '\x16', '\x6b', '\x06', '\x6c', '\x86',
+ '\x3f', '\xbd', '\xdc', '\x13', '\x00', '\x38', '\x6a', '\x96',
+ '\x1a', '\x30', '\x41', '\xa2', '\x60', '\xd6', '\x28', '\xd6',
+ '\xe9', '\xd6', '\x14', '\x80', '\x0f', '\x05', '\x6f', '\xae',
+ '\x28', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04',
+ '\x00', '\x38', '\x42', '\xa2', '\xbe', '\x8f', '\x3e', '\x0d',
+ '\x6f', '\xce', '\xc4', '\x1a', '\x00', '\x38', '\x6c', '\xca',
+ '\xec', '\x06', '\x1e', '\x10', '\xec', '\xd6', '\x6f', '\x9e',
+ '\x96', '\x1b', '\x00', '\x38', '\x09', '\x91', '\x70', '\x8a',
+ '\x16', '\x91', '\xe1', '\x1b', '\xac', '\x06', '\x1a', '\x91',
+ '\xe0', '\x0b', '\x1e', '\x91', '\xe8', '\x8b', '\x74', '\xe0',
+ '\x0f', '\x05', '\x5a', '\x80', '\x6c', '\x96', '\x6f', '\xde',
+ '\x96', '\x1b', '\x00', '\x38', '\x01', '\xd1', '\xe1', '\x1b',
+ '\x05', '\xd1', '\xe0', '\x0b', '\xa0', '\x96', '\x09', '\xd1',
+ '\xe9', '\x9b', '\x29', '\x16', '\x16', '\xd1', '\xe1', '\x1b',
+ '\x1a', '\xd1', '\x70', '\x8a', '\x68', '\xc6', '\xa9', '\xc6',
+ '\x1e', '\xd1', '\xec', '\xcb', '\x46', '\xe0', '\x0f', '\x05',
+ '\x6f', '\xae', '\x44', '\x1a', '\x00', '\x38', '\x3f', '\xbd',
+ '\xda', '\x04', '\x00', '\x38', '\x44', '\xa2', '\xbe', '\x8f',
+ '\x3e', '\x0d', '\x6f', '\xae', '\x58', '\x1a', '\x00', '\x38',
+ '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38', '\x60', '\xa6',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x20', '\x05', '\x00', '\x38',
+ '\x43', '\xa2', '\xbe', '\x8f', '\x3e', '\x0d', '\x6f', '\x9e',
+ '\x96', '\x1b', '\x00', '\x38', '\x01', '\x91', '\xe1', '\x1b',
+ '\x05', '\x91', '\xe0', '\x0b', '\x09', '\x91', '\xe8', '\x8b',
+ '\x1e', '\x91', '\x70', '\x8a', '\x6f', '\xce', '\x96', '\x1b',
+ '\x00', '\x38', '\x7c', '\x0a', '\x0d', '\xc1', '\x70', '\x8a',
+ '\x11', '\xc1', '\x70', '\x8a', '\x15', '\xc1', '\x79', '\x0e',
+ '\x7f', '\x0d', '\xb8', '\x1b', '\x00', '\x38', '\x70', '\x8a',
+ '\x7f', '\x0d', '\xbc', '\x1b', '\x00', '\x38', '\x70', '\x8a',
+ '\x0d', '\x91', '\xe8', '\x8a', '\xff', '\x8d', '\xc0', '\x01',
+ '\x75', '\x86', '\x65', '\x56', '\x04', '\x20', '\x6c', '\xd6',
+ '\x15', '\xd2', '\x65', '\x96', '\x29', '\x55', '\x65', '\x36',
+ '\x23', '\x95', '\x09', '\xd1', '\x69', '\x9a', '\x24', '\x30',
+ '\x2c', '\x36', '\x0d', '\xd1', '\xe9', '\x9a', '\x1c', '\x80',
+ '\x0f', '\x05', '\x09', '\x31', '\x69', '\x9a', '\x10', '\x30',
+ '\x0f', '\x05', '\x83', '\x0b', '\x0a', '\x20', '\x0f', '\x05',
+ '\x0d', '\x31', '\xe9', '\x9a', '\x06', '\x20', '\x0f', '\x05',
+ '\x65', '\x56', '\x35', '\x35', '\x11', '\x31', '\x63', '\x3a',
+ '\xca', '\x32', '\x4d', '\x90', '\x65', '\x96', '\x29', '\x55',
+ '\x65', '\x36', '\x23', '\x95', '\x2f', '\x3e', '\x96', '\x1b',
+ '\x00', '\x38', '\x05', '\x31', '\x64', '\x4a', '\x0d', '\x31',
+ '\x69', '\x9a', '\x29', '\x46', '\x01', '\x31', '\x27', '\x9a',
+ '\x65', '\xa6', '\xc3', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\x2f', '\xae', '\xbe', '\x1a',
+ '\x00', '\x38', '\x64', '\xb6', '\x3f', '\xbd', '\x2c', '\x13',
+ '\x00', '\x38', '\x83', '\x0b', '\x24', '\x30', '\x6a', '\x66',
+ '\x65', '\xa6', '\xc3', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\x2f', '\xae', '\xbe', '\x1a',
+ '\x00', '\x38', '\x64', '\xb6', '\x3f', '\xbd', '\x4a', '\x0c',
+ '\x00', '\x38', '\x6a', '\xa6', '\xe5', '\x20', '\x65', '\xa6',
+ '\x73', '\x0a', '\x65', '\x26', '\xc3', '\x23', '\xa5', '\x26',
+ '\xc2', '\x23', '\xa5', '\x26', '\xc2', '\x23', '\x2f', '\x2e',
+ '\xbe', '\x1a', '\x00', '\x38', '\x62', '\xa6', '\x4f', '\xbc',
+ '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd',
+ '\xd6', '\x0b', '\x00', '\x38', '\x62', '\xa6', '\x64', '\xb6',
+ '\x67', '\xc6', '\x66', '\xd6', '\x3f', '\xbd', '\x7e', '\x13',
+ '\x00', '\x38', '\x4a', '\xa6', '\x28', '\x20', '\x7b', '\x86',
+ '\x0d', '\x31', '\x69', '\xde', '\x26', '\xd6', '\xe9', '\xdb',
+ '\x11', '\x31', '\x70', '\x8a', '\x62', '\xaa', '\x24', '\xa6',
+ '\x3f', '\xbd', '\x20', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\x62', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04',
+ '\x00', '\x38', '\xaa', '\xe0', '\x0f', '\x05', '\xcf', '\xae',
+ '\x01', '\x00', '\x4c', '\x30', '\x0f', '\x05', '\xcf', '\xae',
+ '\x02', '\x00', '\x46', '\x20', '\x65', '\xa6', '\x62', '\xaa',
+ '\x24', '\xa6', '\x6f', '\x1e', '\x20', '\x05', '\x00', '\x38',
+ '\x7b', '\x86', '\xb1', '\xb9', '\x6f', '\x0e', '\xda', '\x04',
+ '\x00', '\x38', '\x6f', '\xae', '\x76', '\x1a', '\x00', '\x38',
+ '\xb0', '\xb9', '\x66', '\xa6', '\x7b', '\x86', '\xb1', '\xb9',
+ '\x6f', '\xae', '\x82', '\x1a', '\x00', '\x38', '\xb0', '\xb9',
+ '\x62', '\xa6', '\x64', '\xb6', '\x3f', '\xbd', '\xde', '\x12',
+ '\x00', '\x38', '\x41', '\x92', '\xc3', '\x9b', '\x11', '\x31',
+ '\x6d', '\x9e', '\x01', '\x92', '\x58', '\xe0', '\xed', '\x9b',
+ '\x65', '\xa6', '\xc3', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\x6f', '\xad', '\xbe', '\x1a',
+ '\x00', '\x38', '\x62', '\xae', '\x24', '\xa6', '\x6f', '\x1e',
+ '\x20', '\x05', '\x00', '\x38', '\x7b', '\x86', '\xb1', '\xb9',
+ '\x6f', '\x0e', '\xda', '\x04', '\x00', '\x38', '\x6f', '\xae',
+ '\x8a', '\x1a', '\x00', '\x38', '\xb0', '\xb9', '\x66', '\xa6',
+ '\x7b', '\x86', '\xb1', '\xb9', '\x6f', '\xae', '\x82', '\x1a',
+ '\x00', '\x38', '\xb0', '\xb9', '\x62', '\xa6', '\x64', '\xb6',
+ '\x67', '\xc6', '\x66', '\xd6', '\x3f', '\xbd', '\x2e', '\x14',
+ '\x00', '\x38', '\x0d', '\x31', '\x6d', '\x9e', '\x26', '\x96',
+ '\xed', '\x9b', '\x11', '\x31', '\x70', '\x8a', '\x6f', '\xce',
+ '\x96', '\x1b', '\x00', '\x38', '\x0d', '\xc1', '\x69', '\x9a',
+ '\x7f', '\x0d', '\xb8', '\x1b', '\x00', '\x38', '\x29', '\x9a',
+ '\xe8', '\x96', '\xff', '\x1d', '\x44', '\xfe', '\x0f', '\x05',
+ '\x75', '\x86', '\x6f', '\x2e', '\xbe', '\x1a', '\x00', '\x38',
+ '\x6f', '\x1e', '\x96', '\x1b', '\x00', '\x38', '\x09', '\x11',
+ '\xa0', '\x0b', '\x4c', '\x30', '\x7b', '\x86', '\x62', '\xaa',
+ '\x3f', '\xbd', '\x20', '\x05', '\x00', '\x38', '\x6f', '\xae',
+ '\x96', '\x1a', '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04',
+ '\x00', '\x38', '\x70', '\x86', '\x09', '\x11', '\xe0', '\x0a',
+ '\x22', '\x00', '\x0f', '\x05', '\x05', '\x11', '\x29', '\x0a',
+ '\x01', '\x11', '\x6d', '\xda', '\x62', '\x99', '\x59', '\x9a',
+ '\x4d', '\x05', '\xd9', '\x9a', '\xff', '\x2d', '\x9a', '\xfd',
+ '\x0f', '\x05', '\x02', '\x02', '\x09', '\x11', '\xe0', '\x0a',
+ '\xe3', '\x10', '\x0f', '\x05', '\x6f', '\xae', '\xa6', '\x1a',
+ '\x00', '\x38', '\x3f', '\xbd', '\xda', '\x04', '\x00', '\x38',
+ '\x0f', '\x2c', '\x6c', '\x00', '\x01', '\x52', '\xc1', '\x52',
+ '\xa5', '\x80', '\x15', '\x12', '\x7a', '\x86', '\xbe', '\x8f',
+ '\x3e', '\x0d', '\x00', '\x00', '\x7f', '\xb6', '\x0f', '\x05',
+ '\x00', '\x00', '\x00', '\x00', '\x0d', '\x0a', '\x0d', '\x0a',
+ '\x44', '\x65', '\x76', '\x69', '\x63', '\x65', '\x20', '\x49',
+ '\x44', '\x20', '\x3d', '\x20', '\x00', '\x00', '\x43', '\x68',
+ '\x65', '\x63', '\x6b', '\x73', '\x75', '\x6d', '\x20', '\x6f',
+ '\x66', '\x20', '\x62', '\x6f', '\x6f', '\x74', '\x6c', '\x6f',
+ '\x61', '\x64', '\x65', '\x72', '\x20', '\x69', '\x73', '\x20',
+ '\x00', '\x00', '\x57', '\x61', '\x69', '\x74', '\x69', '\x6e',
+ '\x67', '\x20', '\x66', '\x6f', '\x72', '\x20', '\x6c', '\x6f',
+ '\x61', '\x64', '\x20', '\x69', '\x6e', '\x66', '\x6f', '\x2e',
+ '\x0d', '\x0a', '\x00', '\x00', '\x47', '\x6f', '\x74', '\x20',
+ '\x6c', '\x6f', '\x61', '\x64', '\x20', '\x69', '\x6e', '\x66',
+ '\x6f', '\x2e', '\x0d', '\x0a', '\x00', '\x00', '\x50', '\x41',
+ '\x43', '\x4b', '\x45', '\x54', '\x5f', '\x49', '\x4e', '\x46',
+ '\x4f', '\x0d', '\x0a', '\x00', '\x53', '\x45', '\x54', '\x5f',
+ '\x52', '\x45', '\x47', '\x49', '\x53', '\x54', '\x45', '\x52',
+ '\x0d', '\x0a', '\x00', '\x00', '\x47', '\x45', '\x54', '\x5f',
+ '\x52', '\x45', '\x47', '\x49', '\x53', '\x54', '\x45', '\x52',
+ '\x0d', '\x0a', '\x00', '\x00', '\x50', '\x41', '\x55', '\x53',
+ '\x45', '\x5f', '\x4c', '\x4f', '\x4f', '\x50', '\x0d', '\x0a',
+ '\x00', '\x00', '\x4d', '\x45', '\x4d', '\x5f', '\x56', '\x45',
+ '\x52', '\x49', '\x46', '\x59', '\x0d', '\x0a', '\x00', '\x00',
+ '\x76', '\x65', '\x72', '\x69', '\x66', '\x79', '\x20', '\x66',
+ '\x61', '\x69', '\x6c', '\x65', '\x64', '\x0d', '\x0a', '\x00',
+ '\x4d', '\x45', '\x4d', '\x5f', '\x54', '\x45', '\x53', '\x54',
+ '\x0d', '\x0a', '\x00', '\x00', '\x23', '\x23', '\x23', '\x20',
+ '\x4d', '\x65', '\x6d', '\x6f', '\x72', '\x79', '\x20', '\x74',
+ '\x65', '\x73', '\x74', '\x20', '\x66', '\x61', '\x69', '\x6c',
+ '\x65', '\x64', '\x20', '\x61', '\x74', '\x20', '\x00', '\x00',
+ '\x50', '\x61', '\x73', '\x73', '\x65', '\x64', '\x20', '\x6d',
+ '\x65', '\x6d', '\x6f', '\x72', '\x79', '\x20', '\x74', '\x65',
+ '\x73', '\x74', '\x2e', '\x0d', '\x0a', '\x00', '\x4d', '\x45',
+ '\x4d', '\x5f', '\x44', '\x55', '\x4d', '\x50', '\x0d', '\x0a',
+ '\x00', '\x00', '\x4d', '\x45', '\x4d', '\x5f', '\x43', '\x4c',
+ '\x45', '\x41', '\x52', '\x0d', '\x0a', '\x00', '\x46', '\x4c',
+ '\x41', '\x53', '\x48', '\x0d', '\x0a', '\x00', '\x4a', '\x55',
+ '\x4d', '\x50', '\x0d', '\x0a', '\x00', '\x00', '\x45', '\x4e',
+ '\x44', '\x0d', '\x0a', '\x00', '\x23', '\x23', '\x23', '\x20',
+ '\x55', '\x6e', '\x6b', '\x6e', '\x6f', '\x77', '\x6e', '\x20',
+ '\x74', '\x79', '\x70', '\x65', '\x3a', '\x20', '\x00', '\x00',
+ '\x43', '\x68', '\x65', '\x63', '\x6b', '\x73', '\x75', '\x6d',
+ '\x20', '\x6f', '\x66', '\x20', '\x66', '\x69', '\x6c', '\x65',
+ '\x20', '\x69', '\x73', '\x20', '\x00', '\x00', '\x23', '\x23',
+ '\x23', '\x20', '\x4d', '\x65', '\x6d', '\x6f', '\x72', '\x79',
+ '\x20', '\x74', '\x65', '\x73', '\x74', '\x20', '\x31', '\x20',
+ '\x66', '\x61', '\x69', '\x6c', '\x65', '\x64', '\x20', '\x61',
+ '\x74', '\x20', '\x00', '\x00', '\x23', '\x23', '\x23', '\x20',
+ '\x4d', '\x65', '\x6d', '\x6f', '\x72', '\x79', '\x20', '\x74',
+ '\x65', '\x73', '\x74', '\x20', '\x32', '\x20', '\x66', '\x61',
+ '\x69', '\x6c', '\x65', '\x64', '\x20', '\x61', '\x74', '\x20',
+ '\x00', '\x00', '\x20', '\x3a', '\x00', '\x00', '\x38', '\x4d',
+ '\x62', '\x20', '\x42', '\x42', '\x00', '\x00', '\x38', '\x4d',
+ '\x62', '\x20', '\x54', '\x42', '\x00', '\x00', '\x31', '\x36',
+ '\x4d', '\x62', '\x20', '\x42', '\x42', '\x00', '\x31', '\x36',
+ '\x4d', '\x62', '\x20', '\x54', '\x42', '\x00', '\x33', '\x32',
+ '\x4d', '\x62', '\x20', '\x54', '\x42', '\x00', '\x55', '\x6e',
+ '\x73', '\x75', '\x70', '\x70', '\x6f', '\x72', '\x74', '\x65',
+ '\x64', '\x20', '\x69', '\x6e', '\x74', '\x65', '\x72', '\x6c',
+ '\x65', '\x61', '\x76', '\x65', '\x21', '\x0a', '\x00', '\x00',
+ '\x46', '\x6f', '\x75', '\x6e', '\x64', '\x20', '\x31', '\x20',
+ '\x78', '\x20', '\x43', '\x46', '\x49', '\x20', '\x61', '\x74',
+ '\x20', '\x00', '\x54', '\x6f', '\x6f', '\x20', '\x6d', '\x61',
+ '\x6e', '\x79', '\x20', '\x72', '\x65', '\x67', '\x69', '\x6f',
+ '\x6e', '\x73', '\x20', '\x6f', '\x6e', '\x20', '\x63', '\x68',
+ '\x69', '\x70', '\x21', '\x0a', '\x00', '\x00', '\x4e', '\x6f',
+ '\x20', '\x73', '\x69', '\x6e', '\x67', '\x6c', '\x65', '\x20',
+ '\x78', '\x31', '\x36', '\x20', '\x61', '\x74', '\x20', '\x00',
+ '\x4e', '\x6f', '\x20', '\x69', '\x6e', '\x74', '\x65', '\x72',
+ '\x6c', '\x65', '\x61', '\x76', '\x65', '\x64', '\x20', '\x78',
+ '\x31', '\x36', '\x20', '\x61', '\x74', '\x20', '\x00', '\x00',
+ '\x46', '\x6f', '\x75', '\x6e', '\x64', '\x20', '\x00', '\x00',
+ '\x31', '\x00', '\x32', '\x00', '\x20', '\x78', '\x20', '\x00',
+ '\x46', '\x61', '\x74', '\x61', '\x6c', '\x3a', '\x20', '\x66',
+ '\x6c', '\x61', '\x73', '\x68', '\x20', '\x69', '\x73', '\x20',
+ '\x74', '\x6f', '\x6f', '\x20', '\x73', '\x6d', '\x61', '\x6c',
+ '\x6c', '\x2e', '\x0a', '\x00', '\x53', '\x65', '\x63', '\x74',
+ '\x6f', '\x72', '\x20', '\x65', '\x72', '\x61', '\x73', '\x65',
+ '\x20', '\x65', '\x72', '\x72', '\x6f', '\x72', '\x0a', '\x00',
+ '\x45', '\x72', '\x72', '\x6f', '\x72', '\x20', '\x61', '\x74',
+ '\x20', '\x00', '\x3a', '\x20', '\x4e', '\x6f', '\x20', '\x6e',
+ '\x65', '\x65', '\x64', '\x20', '\x74', '\x6f', '\x20', '\x77',
+ '\x72', '\x69', '\x74', '\x65', '\x0a', '\x00', '\x3a', '\x20',
+ '\x45', '\x72', '\x61', '\x73', '\x69', '\x6e', '\x67', '\x20',
+ '\x00', '\x00', '\x20', '\x62', '\x79', '\x74', '\x65', '\x73',
+ '\x0a', '\x00', '\x3a', '\x20', '\x57', '\x72', '\x69', '\x74',
+ '\x69', '\x6e', '\x67', '\x20', '\x00', '\x00', '\x3a', '\x20',
+ '\x56', '\x65', '\x72', '\x69', '\x66', '\x79', '\x69', '\x6e',
+ '\x67', '\x2e', '\x2e', '\x2e', '\x00', '\x00', '\x4f', '\x4b',
+ '\x0a', '\x00', '\x7e', '\x19', '\x00', '\x38', '\x86', '\x19',
+ '\x00', '\x38', '\x8e', '\x19', '\x00', '\x38', '\x96', '\x19',
+ '\x00', '\x38', '\x9e', '\x19', '\x00', '\x38', '\x00', '\x00',
+ '\x00', '\x80', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x84', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x54', '\x68', '\x69', '\x73', '\x20', '\x62', '\x6f', '\x6f',
+ '\x74', '\x6c', '\x6f', '\x61', '\x64', '\x65', '\x72', '\x20',
+ '\x77', '\x61', '\x73', '\x20', '\x62', '\x75', '\x69', '\x6c',
+ '\x74', '\x20', '\x62', '\x79', '\x20', '\x72', '\x6f', '\x6f',
+ '\x74', '\x20', '\x6f', '\x6e', '\x20', '\x57', '\x65', '\x64',
+ '\x20', '\x4d', '\x61', '\x79', '\x20', '\x31', '\x36', '\x20',
+ '\x32', '\x31', '\x3a', '\x33', '\x31', '\x3a', '\x34', '\x33',
+ '\x20', '\x43', '\x45', '\x53', '\x54', '\x20', '\x32', '\x30',
+ '\x30', '\x37', '\x2e', '\x0d', '\x0a', '\x00'
+};
diff --git a/package/etrax-tools/src/e100boot/sbl/network.c b/package/etrax-tools/src/e100boot/sbl/network.c
new file mode 100644
index 000000000..7c77d5e52
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/network.c
@@ -0,0 +1,706 @@
+/*!***************************************************************************
+*!
+*! FILE NAME : network.c
+*!
+*! DESCRIPTION: Network boot stuff for e100boot.
+*!
+*! ---------------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! 1996 Ronny Raneup Initial version
+*! 2002 05 02 Ronny Ranerup Moved it into this file
+*! ---------------------------------------------------------------------------
+*! (C) Copyright 1999, 2000, 2001, 2002 Axis Communications AB, LUND, SWEDEN
+*!***************************************************************************/
+
+/************************** Include files ********************************/
+
+#include <stdio.h>
+#include <pcap.h>
+#include <conf.h> /* from configure */
+
+#include <e100boot.h>
+#include <common.h>
+#include <network.h>
+
+/************************** Constants and macros *************************/
+
+#define CRC_LEN 4
+
+/************************** Type definitions *****************************/
+
+/************************** Global variables *****************************/
+
+udword highest_ack_received;
+udword last_ack_received = -1;
+int new_ack = FALSE;
+int got_new_packet = FALSE;
+
+unsigned char dst_addr_of_device[] = { 0x01, 0x40, 0x8c, 0x00, 0x01, 0x00 };
+unsigned char src_addr_of_device[] = { 0x02, 0x40, 0x8c, 0x00, 0x01, 0x00 };
+unsigned char eth_addr_local[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+struct sockaddr sock_addr;
+int sock_fd;
+int pPacket = 0;
+pcap_t *pd;
+
+pcap_handler handler;
+
+struct packet_buf first_rec_packet;
+struct packet_buf *last_rec_packet = &first_rec_packet;
+
+int promisc = 1; /* promiscuous mode */
+int all_ids = TRUE;
+
+int both_addresses = FALSE;
+int p_packet_bpl = 8;
+int printPacketType = CHAR;
+
+unsigned int id;
+int one_id_only = TRUE;
+
+unsigned char buf[10000]; /* pcap buffer */
+
+const struct pcap_pkthdr *hdrG;
+
+char host1[MAX_STRING_LEN]; /* name of ethernet host */
+char host2[MAX_STRING_LEN]; /* name of ethernet host */
+
+/************************** Function prototypes **************************/
+
+int timeout (struct timeval *tvThen, int ms);
+int InitSendSocket (char *device_name);
+int highest_seq_received (void);
+struct packet_buf* ack_on_seq (int seq);
+struct packet_buf* packet_with_seq (int seq);
+struct timeval timeval_subtract (struct timeval *x, struct timeval *y);
+void GetNextPacket (void);
+void PrintPacket (const unsigned char *p, int size, int type);
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: net_init
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2002 05 02 ronny Initial version
+*#
+*#***************************************************************************/
+void
+net_init(void)
+{
+ static char *dev;
+ static char errBuf[1000];
+
+ GetLocalEthAddr();
+ first_rec_packet.data = malloc(PACKET_SIZE);
+
+ if ((dev = pcap_lookupdev(errBuf)) == NULL) {
+ printf("Error %s\n", errBuf);
+ if (errno == EPERM)
+ {
+ printf("Make sure this program is executed with root privileges.\n");
+ }
+
+ exit(EXIT_FAILURE);
+ }
+
+ if ((pd = pcap_open_live(device, 200, promisc, 10, errBuf)) == NULL) {
+ printf("Error %s\n", errBuf);
+ if (errno == EPERM)
+ {
+ printf("Make sure this program is executed with root privileges.\n");
+ }
+
+ exit(EXIT_FAILURE);
+ }
+
+ handler = (pcap_handler) Handler;
+
+ InitSendSocket(device);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: NetBoot
+*#
+*# DESCRIPTION: The main network boot routine.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000 01 07 ronny Initial version
+*# 2002 05 02 ronny Fixed segv bug
+*#
+*#***************************************************************************/
+
+void
+NetBoot(void)
+{
+ struct packet_buf *p;
+ struct timeval tv;
+
+ gettimeofday(&tv, NULL);
+
+ p = create_packet(0);
+ SendToDevice(p->data, p->size);
+
+ while(1) {
+ static int all_trans = FALSE;
+
+ if (got_new_packet) {
+ got_new_packet = FALSE;
+
+ if (new_ack && first_packet) {
+ if (db4) {
+ printf("* got ACK %d.\n", last_ack_received);
+ printf("* ACK wanted %d.\n", first_packet->seq);
+ }
+ if (last_ack_received == first_packet->seq) {
+ if (!(p = create_packet(first_packet->seq+1))) {
+ //break;
+ }
+ first_packet = free_packet(first_packet);
+ }
+ }
+ }
+
+ if (new_ack || timeout(&tv, 500)) {
+ if (p) {
+ SendToDevice(p->data, p->size);
+ }
+ new_ack = FALSE;
+ gettimeofday(&tv, NULL);
+ }
+
+ GetNextPacket();
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetNextPacket
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+GetNextPacket(void)
+{
+ int ret;
+
+ if (db2) printf("> GetNextPacket\n");
+
+ /* got_new_packet = FALSE;*/
+ if ((ret = pcap_dispatch(pd, 1, handler, buf)) == -1) {
+ pcap_perror(pd, "Error in pcap_dispatch");
+ exit(EXIT_FAILURE);
+ }
+
+ if (db2) printf("< GetNextPacket\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: Handler
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+Handler(unsigned char *buf, const struct pcap_pkthdr *hdr,
+ const unsigned char *p)
+{
+ const unsigned char *src = &p[6];
+ const unsigned char *dst = &p[0];
+ struct packet_header_T *h = (struct packet_header_T*)p;
+
+ if (db2) printf("> Handler\n");
+ got_new_packet = TRUE;
+ if ((!memcmp(src, eth_addr_local, 6) && !memcmp(dst, dst_addr_of_device, 6))
+ || (!memcmp(src, src_addr_of_device, 6) && !memcmp(dst, eth_addr_local, 6))) {
+ if (db1) printf("#RX######################################################\n");
+ if (db1) printf("Length: %u(0x%x)\n", (udword)hdr->len, (udword)hdr->len);
+ if (pPacket) PrintPacket(p, hdr->caplen, printPacketType);
+ DecodeSvintoBoot(p);
+ /* should clean up this... */
+ if ((ntohl(h->type) == ACK)) {
+ if (all_ids || (ntohl(h->id) == id)) {
+ if (all_ids && one_id_only) {
+ if (ntohl(h->id) == 0) {
+ all_ids = FALSE;
+ id = ntohl(h->id);
+ printf("Booting device with random id %8.8x.\n", id);
+ }
+ }
+ }
+ else {
+ printf("Got ACK from a new id, %8.8lx. Ignoring.\n",
+ (unsigned long)ntohl(h->id));
+ return;
+ }
+ new_ack = TRUE;
+ last_ack_received = ntohl(h->seq);
+ if (last_ack_received > highest_ack_received) {
+ highest_ack_received = last_ack_received;
+ }
+ }
+
+ if (db1) printf("#########################################################\n");
+
+ }
+ if (db2) printf("< Handler\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: ack_on_seq
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980817 ronny Initial version
+*#
+*#***************************************************************************/
+
+struct packet_buf *
+packet_with_seq(int seq)
+{
+ static int last_seq = 0;
+ struct packet_buf *p = first_packet;
+ struct packet_header_T *h;
+
+ if (seq < last_seq) {
+ p = first_packet;
+ }
+
+ while(p) {
+ h = (struct packet_header_T*)p->data;
+ if (ntohl(h->seq) == seq) {
+ return(p);
+ }
+ p = p->next;
+ }
+ return(NULL);
+}
+
+struct packet_buf *
+ack_on_seq(int seq)
+{
+ struct packet_buf *p = &first_rec_packet;
+ struct packet_header_T *h;
+
+ if (db1) printf("***> ack_on_seq: %d.\n", seq);
+
+ while (p) {
+ /* printf("\nPacket at %x.\n", p);*/
+ /* DecodeSvintoBoot(p->data);*/
+ h = (struct packet_header_T*)p->data;
+ if ( (ntohl(h->type) == ACK) && (ntohl(h->seq) == seq) ) {
+ if (all_ids || ntohl(h->id) == id) {
+ printf("***< ack_on_seq %d, ok.\n", seq);
+ return(p);
+ }
+ }
+ p = p->next;
+ }
+ if (db1) printf("***< ack_on_seq, no.\n");
+ return(NULL);
+}
+
+int
+highest_seq_received(void)
+{
+ struct packet_buf *p = &first_rec_packet;
+ struct packet_header_T *h;
+ int highest_seq = -1;
+
+ if (db1) printf("***> highest_seq_received\n");
+
+ while (p) {
+ /* printf("\nPacket at %x.\n", p);*/
+ /* DecodeSvintoBoot(p->data);*/
+ h = (struct packet_header_T*)p->data;
+ if ((ntohl(h->type) == ACK) && (all_ids || (ntohl(h->id) == id))) {
+ if ((int)ntohl(h->seq) > highest_seq) {
+ highest_seq = ntohl(h->seq);
+ if (db4) printf("Highest seq: %d\n", highest_seq);
+ }
+ }
+ p = p->next;
+ }
+
+ if (db1) printf("***< highest_seq_received: %d\n", highest_seq);
+ return(highest_seq);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: PrintPacket
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+PrintPacket(const unsigned char *p, int size, int type)
+{
+ int i;
+
+ /* printf("size %d\n", size);*/
+ for (i = 0; i != size; i++) {
+ if (i % p_packet_bpl == 0)
+ printf("\n%-4.4d: ", i);
+ if (type == UDEC)
+ printf("%-3d ", p[i]);
+ else if (type == HEX)
+ printf("%-2.2x ", p[i]);
+ else if (type == CHAR) {
+ if (isprint(p[i]))
+ printf("%-3c ", p[i]);
+ else
+ printf("%-3d ", p[i]);
+ }
+ else if (type == ASCII) {
+ if (isprint(p[i]))
+ printf("%c", p[i]);
+ else
+ printf(".");
+ }
+ }
+ printf("\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: DecodeSvintoBoot
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION: Decodes packets that follow the e100boot protocol.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+DecodeSvintoBoot(const unsigned char *p)
+{
+ char *str;
+ volatile struct packet_header_T *ph = (struct packet_header_T*)p;
+
+ /* printf("size %d \n", sizeof(struct packet_header_T));*/
+
+ if (db4) printf("\n>DecodeSvintoBoot. Packet at 0x%x\n", (unsigned int)p);
+ if (db1) {
+ printf("%2.2x-%2.2x-%2.2x-%2.2x-%2.2x-%2.2x -> ", p[6],p[7],p[8],p[9],p[10], p[11]);
+ printf("%2.2x-%2.2x-%2.2x-%2.2x-%2.2x-%2.2x\n", p[0],p[1],p[2],p[3],p[4], p[5]);
+
+ printf("length : %4.4lx\n", (long)ntohs(ph->length));
+ printf("snap1 : %8.8lx\n", (long)ntohl(ph->snap1));
+ printf("snap2 : %8.8lx\n", (long)ntohl(ph->snap2));
+
+ switch (ntohl(ph->tag)) {
+ case 0xffffffff:
+ str = "(host > ETRAX)";
+ break;
+ case 0xfffffffe:
+ str = "(host < ETRAX)";
+ break;
+ default:
+ str = "(unknown)";
+ break;
+ }
+ printf("tag : %8.8lx %s\n", (unsigned long)ntohl(ph->tag), str);
+ printf("seq : %8.8lx\n", (unsigned long)ntohl(ph->seq));
+ }
+
+ switch (ntohl(ph->type)) {
+
+ case STRING:
+ str = "(STRING)";
+ fprintf(stderr, "%s", &p[sizeof(struct packet_header_T)]);
+ find_string((char*)&p[sizeof(struct packet_header_T)]);
+ break;
+
+ case NET_INT: {
+ char search_str[20];
+
+ str = "(NET_INT)";
+ sprintf(search_str, "0x%8.8x", ntohl(*(udword*)&p[sizeof(struct packet_header_T)]));
+ fprintf(stderr, search_str);
+ find_string(search_str);
+ break;
+ }
+
+ case NET_INT_NL: {
+ char search_str[20];
+
+ str = "(NET_INT_NL)";
+ sprintf(search_str, "0x%8.8x\n", ntohl(*(udword*)&p[sizeof(struct packet_header_T)]));
+ fprintf(stderr, search_str);
+ find_string(search_str);
+ break;
+ }
+
+ case ACK:
+ str = "(ACK)";
+ break;
+
+ case BOOT_PACKET:
+ str = "(bootpacket)";
+ break;
+
+ case BOOT_CMDS:
+ str = "(bootcmds)";
+ break;
+
+ default:
+ str = "(unknown)";
+ break;
+ }
+
+ if (db1) {
+ printf("(type : %8.8lx %s)\n", (unsigned long)ntohl(ph->type), str);
+ printf("(id : %8.8lx)\n", (unsigned long)ntohl(ph->id));
+ id = ntohl(ph->id);
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetLocalEthAddr
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980818 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+GetLocalEthAddr(void)
+{
+ int fd;
+ struct ifreq ifr;
+
+ if ((fd = socket(AF_INET, SOCK_DGRAM, 0)) == -1) {
+ perror("socket (GetLocalEthAddr)");
+ exit(EXIT_FAILURE);
+ }
+
+ strcpy(ifr.ifr_name, device);
+ if (ioctl(fd, SIOCGIFHWADDR, &ifr) < 0) {
+ perror("ioctl");
+ exit(EXIT_FAILURE);
+ }
+
+ memcpy(eth_addr_local, ifr.ifr_hwaddr.sa_data, 6);
+ if (db1) printf("Ethernet adress for device %s is %2.2x-%2.2x-%2.2x-%2.2x-%2.2x-%2.2x\n",
+ device,
+ eth_addr_local[0],
+ eth_addr_local[1],
+ eth_addr_local[2],
+ eth_addr_local[3],
+ eth_addr_local[4],
+ eth_addr_local[5]);
+ shutdown(fd, 2);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SendToDevice
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980818 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+SendToDevice(unsigned char *data, int data_len)
+{
+ char fName[MAX_STRING_LEN];
+ FILE *fd;
+ struct packet_header_T *h = (struct packet_header_T*) data;
+
+ if (db1) printf("***> SendToDevice\n");
+
+ if (db2) printf("Sending %d bytes at 0x%x to %s.\n", data_len, (unsigned int)data, device);
+ if (db1) printf("#TX######################################################\n");
+ if (db1) DecodeSvintoBoot(data);
+
+ if (db1) printf("#########################################################\n");
+ if (toFiles || cmdsOnly) {
+ if (cmdsOnly) { /* use a simpler name */
+ sprintf(fName, "e100boot.cmds");
+ }
+ else {
+ sprintf(fName, "e100boot.seq%lu", (unsigned long)ntohl(h->seq));
+ }
+ if (db2) printf("Writing packet to file '%s'.\n", fName);
+ if ((fd = fopen(fName, "w+")) == NULL) {
+ printf("Cannot open/create '%s'. %s.\n", fName, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ fwrite(data, data_len, 1, fd);
+ fclose(fd);
+ }
+ else if (sendto(sock_fd, data, data_len, 0, &sock_addr, sizeof(sock_addr)) < 0) {
+ perror("Sendto failed:");
+ exit(EXIT_FAILURE);
+ }
+
+ if (db1) printf("<*** SendToDevice\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: InitSendSocket
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980818 ronny Initial version
+*#***************************************************************************/
+
+int
+InitSendSocket(char *device_name)
+{
+ if ((sock_fd = socket(AF_INET, SOCK_PACKET, htons(ETH_P_ALL))) < 0) {
+ perror("Socket call failed:");
+ exit(EXIT_FAILURE);
+ }
+
+ fcntl(sock_fd, F_SETFL, O_NDELAY);
+
+ sock_addr.sa_family = AF_INET;
+ strcpy(sock_addr.sa_data, device_name);
+
+ return sock_fd;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: timeout
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980817 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+timeout(struct timeval *tvThen, int ms)
+{
+ struct timeval tvNow;
+ struct timeval tvDiff;
+
+ (void) gettimeofday(&tvNow, NULL);
+ tvDiff = timeval_subtract(&tvNow, tvThen);
+ if (db4) printf("sec %d.%d\n", (int)tvDiff.tv_sec, (int)tvDiff.tv_usec);
+ if (ms * 1000 < (tvDiff.tv_sec * 1000000 + tvDiff.tv_usec)) {
+ if (db4) printf("TIMEOUT\n");
+ return(TRUE);
+ }
+
+ return(FALSE);
+}
+
+/****************************************************************************
+ *#
+ *# FUNCTION NAME: timeval_subtract
+ *#
+ *# PARAMETERS:
+ *#
+ *# DESCRIPTION: Subtract x-y, and return result.
+ *#
+ *# DATE NAME CHANGES
+ *# ---- ---- -------
+ *# 970128 ronny Initial version
+ *#
+ *#***************************************************************************/
+
+struct timeval
+timeval_subtract(struct timeval *x, struct timeval *y)
+{
+ struct timeval diff;
+
+ diff.tv_sec = x->tv_sec - y->tv_sec;
+ diff.tv_usec = x->tv_usec - y->tv_usec;
+
+ if (diff.tv_usec < 0) {
+ diff.tv_sec--;
+ diff.tv_usec = 1000000 + diff.tv_usec;
+ }
+
+ return diff;
+}
diff --git a/package/etrax-tools/src/e100boot/sbl/network.h b/package/etrax-tools/src/e100boot/sbl/network.h
new file mode 100644
index 000000000..c01a9869b
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/network.h
@@ -0,0 +1,42 @@
+
+extern unsigned char dst_addr_of_device[];
+extern unsigned char src_addr_of_device[];
+extern unsigned char eth_addr_local[];
+
+extern int pPacket;
+
+extern int promisc;
+
+extern char host1[MAX_STRING_LEN];
+extern char host2[MAX_STRING_LEN];
+
+extern int both_addresses;
+extern int printPacketType;
+extern int p_packet_bpl;
+
+
+#define UDEC 0
+#define CHAR 1
+#define ASCII 2
+#define HEX 3
+
+#define SIZE_OF_HEADER (sizeof(struct packet_header_T))
+#define DATA_SIZE 1460
+#define SNAP1 0xaaaa0300
+#define SNAP2 0x408c8856
+#define SERVER_TAG 0xffffffff
+#define CLIENT_TAG 0xfffffffe
+
+#define SIZE_OF_FIRST_HEADER (SIZE_OF_HEADER-8)
+#define PACKET_SIZE (DATA_SIZE + SIZE_OF_HEADER)
+#define SIZE_OF_BOOT_CMDS ((IO_BUF_END-IO_BUF_START)-CRC_LEN)
+
+#define BOOT_ADDRESS 0x380000f4
+
+
+void NetBoot (void);
+void SendToDevice (unsigned char *data, int data_len);
+void Handler (unsigned char *buf, const struct pcap_pkthdr *hdr, const unsigned char *p);
+void GetLocalEthAddr (void);
+void net_init (void);
+void DecodeSvintoBoot (const unsigned char *p);
diff --git a/package/etrax-tools/src/e100boot/sbl/reg_des.h b/package/etrax-tools/src/e100boot/sbl/reg_des.h
new file mode 100644
index 000000000..dcc0133bc
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/reg_des.h
@@ -0,0 +1,141 @@
+struct reg_des {
+ char *name;
+ unsigned int addr;
+} reg_des[] = {
+ { "R_WAITSTATES", 0xb0000000 },
+ { "R_BUS_CONFIG", 0xb0000004 },
+ { "R_BUS_STATUS", 0xb0000004 },
+ { "R_DRAM_TIMING", 0xb0000008 },
+ { "R_SDRAM_TIMING", 0xb0000008 },
+ { "R_DRAM_CONFIG", 0xb000000c },
+ { "R_SDRAM_CONFIG", 0xb000000c },
+ { "R_EXT_DMA_0_CMD", 0xb0000010 },
+ { "R_EXT_DMA_0_STAT", 0xb0000010 },
+ { "R_EXT_DMA_0_ADDR", 0xb0000014 },
+ { "R_EXT_DMA_1_CMD", 0xb0000018 },
+ { "R_EXT_DMA_1_STAT", 0xb0000018 },
+ { "R_EXT_DMA_1_ADDR", 0xb000001c },
+ { "R_TIMER_CTRL", 0xb0000020 },
+ { "R_TIMER_DATA", 0xb0000020 },
+ { "R_WATCHDOG", 0xb0000024 },
+ { "R_SHARED_RAM_CONFIG", 0xb0000040 },
+ { "R_SHARED_RAM_ADDR", 0xb0000044 },
+ { "R_GEN_CONFIG", 0xb000002c },
+ { "R_PORT_G_DATA", 0xb0000028 },
+ { "R_PORT_PA_SET", 0xb0000030 },
+ { "R_PORT_PA_READ", 0xb0000030 },
+ { "R_PORT_PB_SET", 0xb0000038 },
+ { "R_PORT_PB_READ", 0xb0000038 },
+ { "R_SERIAL0_CTRL", 0xb0000060 },
+ { "R_SERIAL0_READ", 0xb0000060 },
+ { "R_SERIAL0_XOFF", 0xb0000064 },
+ { "R_SERIAL1_CTRL", 0xb0000068 },
+ { "R_SERIAL1_READ", 0xb0000068 },
+ { "R_SERIAL1_XOFF", 0xb000006c },
+ { "R_SERIAL2_CTRL", 0xb0000070 },
+ { "R_SERIAL2_READ", 0xb0000070 },
+ { "R_SERIAL2_XOFF", 0xb0000074 },
+ { "R_SERIAL3_CTRL", 0xb0000078 },
+ { "R_SERIAL3_READ", 0xb0000078 },
+ { "R_SERIAL3_XOFF", 0xb000007c },
+ { "R_NETWORK_SA_0", 0xb0000080 },
+ { "R_NETWORK_SA_1", 0xb0000084 },
+ { "R_NETWORK_SA_2", 0xb0000088 },
+ { "R_NETWORK_GA_0", 0xb000008c },
+ { "R_NETWORK_GA_1", 0xb0000090 },
+ { "R_NETWORK_REC_CONFIG", 0xb0000094 },
+ { "R_NETWORK_GEN_CONFIG", 0xb0000098 },
+ { "R_NETWORK_TR_CTRL", 0xb000009c },
+ { "R_NETWORK_MGM_CTRL", 0xb00000a0 },
+ { "R_NETWORK_STAT", 0xb00000a0 },
+ { "R_REC_COUNTERS", 0xb00000a4 },
+ { "R_TR_COUNTERS", 0xb00000a8 },
+ { "R_PHY_COUNTERS", 0xb00000ac },
+ { "R_PAR0_CTRL_DATA", 0xb0000040 },
+ { "R_PAR0_STATUS_DATA", 0xb0000040 },
+ { "R_PAR0_CONFIG", 0xb0000044 },
+ { "R_PAR0_DELAY", 0xb0000048 },
+ { "R_PAR1_CTRL_DATA", 0xb0000050 },
+ { "R_PAR1_STATUS_DATA", 0xb0000050 },
+ { "R_PAR1_CONFIG", 0xb0000054 },
+ { "R_PAR1_DELAY", 0xb0000058 },
+ { "R_ATA_CTRL_DATA", 0xb0000040 },
+ { "R_ATA_STATUS_DATA", 0xb0000040 },
+ { "R_ATA_CONFIG", 0xb0000044 },
+ { "R_ATA_TRANSFER_CNT", 0xb0000048 },
+ { "R_SCSI0_CTRL", 0xb0000044 },
+ { "R_SCSI0_CMD_DATA", 0xb0000040 },
+ { "R_SCSI0_STATUS", 0xb0000048 },
+ { "R_SCSI1_CTRL", 0xb0000054 },
+ { "R_SCSI1_CMD_DATA", 0xb0000050 },
+ { "R_SCSI1_STATUS", 0xb0000058 },
+ { "R_IRQ_MASK0_RD", 0xb00000c0 },
+ { "R_IRQ_MASK0_CLR", 0xb00000c0 },
+ { "R_IRQ_READ0", 0xb00000c4 },
+ { "R_IRQ_MASK0_SET", 0xb00000c4 },
+ { "R_IRQ_MASK1_RD", 0xb00000c8 },
+ { "R_IRQ_MASK1_CLR", 0xb00000c8 },
+ { "R_IRQ_READ1", 0xb00000cc },
+ { "R_IRQ_MASK1_SET", 0xb00000cc },
+ { "R_IRQ_MASK2_RD", 0xb00000d0 },
+ { "R_IRQ_MASK2_CLR", 0xb00000d0 },
+ { "R_IRQ_READ2", 0xb00000d4 },
+ { "R_IRQ_MASK2_SET", 0xb00000d4 },
+ { "R_VECT_MASK_RD", 0xb00000d8 },
+ { "R_VECT_MASK_CLR", 0xb00000d8 },
+ { "R_VECT_READ", 0xb00000dc },
+ { "R_VECT_MASK_SET", 0xb00000dc },
+ { "R_SET_EOP", 0xb000003c },
+ { "R_DMA_CH0_HWSW", 0xb0000100 },
+ { "R_DMA_CH0_DESCR", 0xb000010c },
+ { "R_DMA_CH0_NEXT", 0xb0000104 },
+ { "R_DMA_CH0_BUF", 0xb0000108 },
+ { "R_DMA_CH0_FIRST", 0xb00001a0 },
+ { "R_DMA_CH1_HWSW", 0xb0000110 },
+ { "R_DMA_CH1_DESCR", 0xb000011c },
+ { "R_DMA_CH1_NEXT", 0xb0000114 },
+ { "R_DMA_CH1_BUF", 0xb0000118 },
+ { "R_DMA_CH1_FIRST", 0xb00001a4 },
+ { "R_DMA_CH2_HWSW", 0xb0000120 },
+ { "R_DMA_CH2_DESCR", 0xb000012c },
+ { "R_DMA_CH2_NEXT", 0xb0000124 },
+ { "R_DMA_CH2_BUF", 0xb0000128 },
+ { "R_DMA_CH2_FIRST", 0xb00001a8 },
+ { "R_DMA_CH3_HWSW", 0xb0000130 },
+ { "R_DMA_CH3_DESCR", 0xb000013c },
+ { "R_DMA_CH3_NEXT", 0xb0000134 },
+ { "R_DMA_CH3_BUF", 0xb0000138 },
+ { "R_DMA_CH3_FIRST", 0xb00001ac },
+ { "R_DMA_CH4_HWSW", 0xb0000140 },
+ { "R_DMA_CH4_DESCR", 0xb000014c },
+ { "R_DMA_CH4_NEXT", 0xb0000144 },
+ { "R_DMA_CH4_BUF", 0xb0000148 },
+ { "R_DMA_CH4_FIRST", 0xb00001b0 },
+ { "R_DMA_CH5_HWSW", 0xb0000150 },
+ { "R_DMA_CH5_DESCR", 0xb000015c },
+ { "R_DMA_CH5_NEXT", 0xb0000154 },
+ { "R_DMA_CH5_BUF", 0xb0000158 },
+ { "R_DMA_CH5_FIRST", 0xb00001b4 },
+ { "R_DMA_CH6_HWSW", 0xb0000160 },
+ { "R_DMA_CH6_DESCR", 0xb000016c },
+ { "R_DMA_CH6_NEXT", 0xb0000164 },
+ { "R_DMA_CH6_BUF", 0xb0000168 },
+ { "R_DMA_CH6_FIRST", 0xb00001b8 },
+ { "R_DMA_CH7_HWSW", 0xb0000170 },
+ { "R_DMA_CH7_DESCR", 0xb000017c },
+ { "R_DMA_CH7_NEXT", 0xb0000174 },
+ { "R_DMA_CH7_BUF", 0xb0000178 },
+ { "R_DMA_CH7_FIRST", 0xb00001bc },
+ { "R_DMA_CH8_HWSW", 0xb0000180 },
+ { "R_DMA_CH8_DESCR", 0xb000018c },
+ { "R_DMA_CH8_NEXT", 0xb0000184 },
+ { "R_DMA_CH8_BUF", 0xb0000188 },
+ { "R_DMA_CH8_FIRST", 0xb00001c0 },
+ { "R_DMA_CH9_HWSW", 0xb0000190 },
+ { "R_DMA_CH9_DESCR", 0xb000019c },
+ { "R_DMA_CH9_NEXT", 0xb0000194 },
+ { "R_DMA_CH9_BUF", 0xb0000198 },
+ { "R_DMA_CH9_FIRST", 0xb00001c4 },
+ { "R_TEST_MODE", 0xb00000fc },
+ { NULL, 0 }
+};
diff --git a/package/etrax-tools/src/e100boot/sbl/ser_ima.c b/package/etrax-tools/src/e100boot/sbl/ser_ima.c
new file mode 100644
index 000000000..2aa50d242
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/ser_ima.c
@@ -0,0 +1,825 @@
+
+/* cconv 1.2 12/16/97, Copyright (C) 1997, Axis Communications AB */
+
+const char ser_ima[] =
+{
+ '\x0f', '\x05', '\x0f', '\x05', '\x6f', '\xee', '\x00', '\x1f',
+ '\x00', '\x38', '\x3f', '\x0d', '\x08', '\x01', '\x00', '\x38',
+ '\x78', '\x56', '\x34', '\x12', '\x21', '\x43', '\x65', '\x87',
+ '\x6f', '\xde', '\x20', '\x00', '\x00', '\xb0', '\x5f', '\x9c',
+ '\x65', '\x6f', '\xed', '\x9b', '\x5f', '\x9c', '\x25', '\x2f',
+ '\x7f', '\x0d', '\x6c', '\x16', '\x00', '\x38', '\xe9', '\x9b',
+ '\xed', '\x9b', '\x3f', '\x0d', '\x28', '\x01', '\x00', '\x38',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x7e', '\x92', '\x7f', '\x0d',
+ '\x31', '\x00', '\x00', '\xb0', '\xc9', '\x9b', '\x7f', '\x0d',
+ '\x30', '\x00', '\x00', '\xb0', '\x70', '\x0a', '\x7f', '\x92',
+ '\x7f', '\x0d', '\x6c', '\x16', '\x00', '\x38', '\xc9', '\x9b',
+ '\x7f', '\x0d', '\x39', '\x00', '\x00', '\xb0', '\xc9', '\x9b',
+ '\x7f', '\x0d', '\x38', '\x00', '\x00', '\xb0', '\xc9', '\x9b',
+ '\x7f', '\x0d', '\x0e', '\x1b', '\x00', '\x38', '\x70', '\x8a',
+ '\x6f', '\x9e', '\x20', '\x00', '\x00', '\xb0', '\x69', '\x9a',
+ '\x79', '\x67', '\x7f', '\x0d', '\xc2', '\x1a', '\x00', '\x38',
+ '\xe9', '\x9b', '\x6f', '\x9e', '\x22', '\x00', '\x00', '\xb0',
+ '\x59', '\x9a', '\x59', '\x94', '\x7f', '\x0d', '\x2a', '\x1b',
+ '\x00', '\x38', '\xe9', '\x9b', '\x6f', '\x9e', '\x04', '\x00',
+ '\x00', '\xb0', '\x69', '\x9a', '\x06', '\x93', '\xe1', '\x93',
+ '\x81', '\x92', '\x7f', '\x0d', '\x12', '\x1b', '\x00', '\x38',
+ '\xc9', '\x9b', '\x7f', '\x0d', '\xd4', '\x1a', '\x00', '\x38',
+ '\x70', '\x4a', '\x3f', '\xbd', '\x68', '\x02', '\x00', '\x38',
+ '\x3f', '\xbd', '\xec', '\x02', '\x00', '\x38', '\x3f', '\xbd',
+ '\x0c', '\x02', '\x00', '\x38', '\x6a', '\xa6', '\xf7', '\x30',
+ '\x0f', '\x05', '\x6f', '\x9e', '\x00', '\x01', '\x00', '\x38',
+ '\x69', '\x9a', '\x7f', '\x0d', '\x0e', '\x1b', '\x00', '\x38',
+ '\xe9', '\x9a', '\x24', '\x80', '\x0f', '\x05', '\x6f', '\x9e',
+ '\x12', '\x1b', '\x00', '\x38', '\x49', '\x9a', '\xcf', '\x9e',
+ '\x01', '\x00', '\xd3', '\x20', '\x0f', '\x05', '\x6f', '\xde',
+ '\xd4', '\x01', '\x00', '\xb0', '\x4d', '\x9a', '\x38', '\x93',
+ '\x41', '\x93', '\xcd', '\x9b', '\xc1', '\xe0', '\x0f', '\x05',
+ '\x4f', '\x9e', '\x55', '\x00', '\x7f', '\x0d', '\x6c', '\x16',
+ '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\x0d', '\x30', '\x00',
+ '\x00', '\xb0', '\xc9', '\x9b', '\x3e', '\xbe', '\x3f', '\x0d',
+ '\xac', '\x03', '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x3f', '\xbd', '\xa8', '\x02', '\x00', '\x38', '\x6a', '\xa6',
+ '\x16', '\x20', '\x41', '\x92', '\x3f', '\xbd', '\x34', '\x02',
+ '\x00', '\x38', '\x6a', '\xa6', '\x0a', '\x30', '\x79', '\x86',
+ '\x3f', '\xbd', '\xec', '\x02', '\x00', '\x38', '\x79', '\x86',
+ '\x69', '\xa6', '\x3e', '\x0d', '\x84', '\xe2', '\x6f', '\x9e',
+ '\x22', '\x00', '\x00', '\xb0', '\x59', '\x9a', '\x59', '\x94',
+ '\xee', '\x9b', '\x6f', '\xce', '\x2a', '\x1b', '\x00', '\x38',
+ '\x6c', '\x9a', '\x6e', '\xda', '\xad', '\x96', '\xb9', '\x96',
+ '\xdf', '\x9c', '\x80', '\x25', '\x0a', '\xd0', '\x0f', '\x05',
+ '\x6e', '\x9a', '\xec', '\x9b', '\x04', '\xe0', '\x41', '\xa2',
+ '\x7a', '\x86', '\x7f', '\xb6', '\x04', '\xe2', '\x00', '\x00',
+ '\x6f', '\x9e', '\x6c', '\x16', '\x00', '\x38', '\x79', '\x8a',
+ '\x7f', '\x0d', '\x64', '\x00', '\x00', '\xb0', '\x70', '\x8a',
+ '\x4f', '\xde', '\x55', '\x00', '\x7f', '\x0d', '\x63', '\x00',
+ '\x00', '\xb0', '\xcd', '\xdb', '\x0b', '\xd2', '\x7f', '\x0d',
+ '\x62', '\x00', '\x00', '\xb0', '\xcd', '\xdb', '\xa0', '\xd2',
+ '\xc9', '\xdb', '\x7f', '\x0d', '\x61', '\x00', '\x00', '\xb0',
+ '\xcd', '\xdb', '\x41', '\x92', '\x7f', '\x0d', '\x14', '\x1b',
+ '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\xb6', '\x0f', '\x05',
+ '\x6f', '\x9e', '\x60', '\x00', '\x00', '\xb0', '\x69', '\x9a',
+ '\x59', '\xb4', '\x1f', '\xbf', '\xff', '\x01', '\x88', '\x93',
+ '\x2e', '\xa0', '\x0f', '\x05', '\x6f', '\xce', '\x0e', '\x1b',
+ '\x00', '\x38', '\x6c', '\x9a', '\x6f', '\xde', '\x04', '\x01',
+ '\x00', '\x38', '\x6d', '\x99', '\xcb', '\xbb', '\x01', '\x92',
+ '\xec', '\x9b', '\x6f', '\x9e', '\x22', '\x00', '\x00', '\xb0',
+ '\x49', '\x9a', '\x49', '\x94', '\x7f', '\x0d', '\x2a', '\x1b',
+ '\x00', '\x38', '\xe9', '\x9b', '\x7f', '\xb6', '\x41', '\xa2',
+ '\x7f', '\xb6', '\x7a', '\x86', '\x6f', '\x9e', '\x61', '\x00',
+ '\x00', '\xb0', '\x49', '\x9a', '\x85', '\x93', '\xf5', '\xa0',
+ '\x0f', '\x05', '\x4f', '\x9e', '\x2b', '\x00', '\x7f', '\x0d',
+ '\x6c', '\x16', '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\x0d',
+ '\x60', '\x00', '\x00', '\xb0', '\xc9', '\x9b', '\x7f', '\xb6',
+ '\x0f', '\x05', '\x8a', '\x0b', '\x28', '\x30', '\x0f', '\x05',
+ '\x6f', '\x9e', '\x61', '\x00', '\x00', '\xb0', '\x49', '\x9a',
+ '\x85', '\x93', '\x14', '\xa0', '\x0f', '\x05', '\x6f', '\x9e',
+ '\x6c', '\x16', '\x00', '\x38', '\x4a', '\xde', '\xc9', '\xdb',
+ '\x7f', '\x0d', '\x60', '\x00', '\x00', '\xb0', '\xcd', '\xdb',
+ '\x8a', '\x0b', '\xdd', '\x20', '\x0f', '\x05', '\x7f', '\xb6',
+ '\x0f', '\x05', '\xfc', '\xe1', '\x7e', '\xbe', '\x8e', '\xe2',
+ '\x4f', '\x9e', '\x30', '\x00', '\x01', '\xe1', '\xc9', '\x9b',
+ '\x4f', '\xde', '\x78', '\x00', '\x02', '\xe1', '\xcd', '\xdb',
+ '\x4d', '\x92', '\x0b', '\xe1', '\xc9', '\x9b', '\x4a', '\xd2',
+ '\x0c', '\xe1', '\xcd', '\xdb', '\x0d', '\xe1', '\x70', '\x0a',
+ '\x4b', '\xb6', '\x06', '\x20', '\x7c', '\x86', '\x0b', '\xe1',
+ '\x70', '\x0a', '\x6c', '\x96', '\xc2', '\x93', '\x6a', '\xb6',
+ '\xe9', '\xb7', '\x4b', '\xd6', '\x0f', '\xd3', '\xcf', '\xde',
+ '\x09', '\x00', '\x04', '\x80', '\x49', '\x92', '\x07', '\xd2',
+ '\xac', '\x96', '\x4e', '\xb2', '\x2e', '\xb6', '\x2b', '\x96',
+ '\x30', '\xd2', '\xf3', '\x91', '\xcd', '\xdb', '\x01', '\xc2',
+ '\xc8', '\xc2', '\xd9', '\x20', '\x6c', '\x96', '\x6e', '\xa6',
+ '\x01', '\xa2', '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38',
+ '\x0e', '\xe2', '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x84', '\xe2', '\xfe', '\x0b', '\x4f', '\x9e', '\xaa', '\xff',
+ '\x7f', '\x0d', '\x6c', '\x16', '\x00', '\x38', '\xc9', '\x9b',
+ '\x7f', '\x0d', '\x30', '\x00', '\x00', '\xb0', '\xc9', '\x9b',
+ '\x6f', '\x0e', '\x12', '\x03', '\x00', '\x38', '\x6f', '\xae',
+ '\x70', '\x16', '\x00', '\x38', '\xb0', '\xb9', '\x6f', '\xae',
+ '\xc2', '\x1a', '\x00', '\x38', '\x6a', '\xaa', '\x7a', '\x67',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x42', '\x03', '\x00', '\x38',
+ '\x6f', '\xae', '\x3c', '\x1a', '\x00', '\x38', '\xb0', '\xb9',
+ '\x6f', '\x9e', '\xf0', '\x00', '\x00', '\x38', '\xef', '\x9e',
+ '\x82', '\x1a', '\x00', '\x38', '\x0e', '\x30', '\x70', '\x86',
+ '\x09', '\x0c', '\xef', '\x9e', '\x82', '\x1a', '\x00', '\x38',
+ '\xf7', '\x20', '\x0f', '\x05', '\x6f', '\xae', '\x82', '\x16',
+ '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38',
+ '\x60', '\xa6', '\x41', '\xb2', '\x3f', '\xbd', '\x42', '\x03',
+ '\x00', '\x38', '\x3f', '\xbd', '\x74', '\x04', '\x00', '\x38',
+ '\x3f', '\x0d', '\x28', '\x01', '\x00', '\x38', '\xbe', '\x0f',
+ '\x3e', '\x0d', '\x84', '\xe2', '\x4f', '\x9e', '\x55', '\x00',
+ '\x7f', '\x0d', '\x6c', '\x16', '\x00', '\x38', '\xc9', '\x9b',
+ '\x7f', '\x0d', '\x30', '\x00', '\x00', '\xb0', '\xc9', '\x9b',
+ '\x6f', '\x9e', '\x30', '\x00', '\x00', '\xb0', '\x69', '\xda',
+ '\x7d', '\x87', '\x7f', '\x0d', '\x6c', '\x16', '\x00', '\x38',
+ '\xcd', '\xdb', '\xc9', '\xdb', '\x7e', '\x8a', '\x6e', '\x9a',
+ '\xef', '\x9e', '\x80', '\x84', '\x1e', '\x00', '\xe1', '\x30',
+ '\x0f', '\x05', '\x6e', '\x9a', '\x01', '\x92', '\xee', '\x9b',
+ '\xed', '\xe0', '\x0f', '\x05', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x84', '\xe2', '\xfe', '\x0b', '\x6f', '\x0e', '\x12', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\x9e', '\x16', '\x00', '\x38',
+ '\xb0', '\xb9', '\x3f', '\xbd', '\xec', '\x02', '\x00', '\x38',
+ '\x6f', '\xae', '\x00', '\x1f', '\x00', '\x38', '\x5f', '\xbc',
+ '\xec', '\x01', '\x3f', '\xbd', '\xf2', '\x07', '\x00', '\x38',
+ '\x6f', '\xae', '\xb8', '\x16', '\x00', '\x38', '\xb0', '\xb9',
+ '\x3f', '\xbd', '\xb8', '\x04', '\x00', '\x38', '\xbe', '\x0f',
+ '\x3e', '\xbe', '\x3f', '\x0d', '\x32', '\x04', '\x00', '\x38',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x98', '\xe2', '\xfe', '\x4b',
+ '\x6f', '\xde', '\x00', '\x1f', '\x00', '\x38', '\x6d', '\x9a',
+ '\x79', '\x67', '\xed', '\x9f', '\xef', '\xde', '\xec', '\x20',
+ '\x00', '\x38', '\xf3', '\x20', '\x0f', '\x05', '\x6f', '\x3e',
+ '\x00', '\x1f', '\x00', '\x38', '\xa3', '\x0b', '\xff', '\x3d',
+ '\xfe', '\x02', '\x0f', '\x05', '\x63', '\x9a', '\x81', '\x92',
+ '\xcf', '\x9d', '\x0b', '\x00', '\x5f', '\x95', '\x3f', '\xf8',
+ '\x54', '\x02', '\x22', '\x01', '\x18', '\x00', '\x62', '\x00',
+ '\x90', '\x00', '\x96', '\x01', '\xc8', '\x01', '\xe4', '\x00',
+ '\x00', '\x02', '\xb8', '\x00', '\x9a', '\x02', '\xce', '\x02',
+ '\x6f', '\xae', '\xca', '\x16', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\x6f', '\x0e', '\x42', '\x03',
+ '\x00', '\x38', '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x6f', '\x0e', '\x16', '\x1b', '\x00', '\x38',
+ '\x60', '\x9a', '\x81', '\x92', '\xe0', '\x9b', '\x3f', '\xbd',
+ '\xec', '\x02', '\x00', '\x38', '\x60', '\x9a', '\x01', '\x92',
+ '\xe0', '\x9b', '\x62', '\xaa', '\x61', '\xba', '\x3f', '\xbd',
+ '\xf2', '\x07', '\x00', '\x38', '\xff', '\xed', '\x88', '\x02',
+ '\x0c', '\x32', '\x6f', '\xae', '\xd8', '\x16', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\x6f', '\x0e',
+ '\x42', '\x03', '\x00', '\x38', '\x04', '\x31', '\x62', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x61', '\x1a', '\x72', '\x09',
+ '\xe1', '\x1b', '\xff', '\xed', '\x5a', '\x02', '\x0c', '\x32',
+ '\x6f', '\xae', '\xe8', '\x16', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\x6f', '\x1e', '\x42', '\x03',
+ '\x00', '\x38', '\x04', '\x31', '\x60', '\xae', '\x41', '\xb2',
+ '\xb1', '\xb9', '\x60', '\xaa', '\x6a', '\xaa', '\x41', '\xb2',
+ '\xb1', '\xb9', '\xff', '\xed', '\x32', '\x02', '\x08', '\x32',
+ '\x6f', '\xae', '\xf8', '\x16', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\x04', '\x31', '\x60', '\xae',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x42', '\x03', '\x00', '\x38',
+ '\x60', '\xaa', '\xff', '\x3d', '\xc0', '\x01', '\x0f', '\x05',
+ '\x81', '\xa2', '\xfd', '\x20', '\x0f', '\x05', '\xff', '\xed',
+ '\x06', '\x02', '\x08', '\x32', '\x6f', '\x4e', '\x12', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\x06', '\x17', '\x00', '\x38',
+ '\xb4', '\xb9', '\x6f', '\x0e', '\x42', '\x03', '\x00', '\x38',
+ '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x62', '\x2a', '\x62', '\x2a', '\xe1', '\x2a', '\xff', '\x3d',
+ '\xb8', '\x01', '\x0f', '\x05', '\x6f', '\xae', '\x14', '\x17',
+ '\x00', '\x38', '\xb4', '\xb9', '\xff', '\xed', '\xd0', '\x01',
+ '\x0f', '\x05', '\x6f', '\x4e', '\x12', '\x03', '\x00', '\x38',
+ '\x6f', '\xae', '\x24', '\x17', '\x00', '\x38', '\xb4', '\xb9',
+ '\x6f', '\x2e', '\x42', '\x03', '\x00', '\x38', '\x04', '\x31',
+ '\x61', '\xae', '\x41', '\xb2', '\xb2', '\xb9', '\x08', '\x31',
+ '\x60', '\xae', '\x41', '\xb2', '\xb2', '\xb9', '\x61', '\xaa',
+ '\x60', '\xba', '\x6e', '\xc6', '\x14', '\xc2', '\x3f', '\xbd',
+ '\xf0', '\x08', '\x00', '\x38', '\x6a', '\xa6', '\x30', '\x20',
+ '\x0f', '\x05', '\x6f', '\xae', '\x30', '\x17', '\x00', '\x38',
+ '\xb4', '\xb9', '\x14', '\xe1', '\x6a', '\xaa', '\x41', '\xb2',
+ '\xb2', '\xb9', '\x14', '\xe1', '\x6a', '\xaa', '\x6a', '\xb6',
+ '\x0f', '\xbc', '\x40', '\x00', '\x8f', '\xac', '\x40', '\x00',
+ '\x3c', '\xa3', '\x3c', '\xb3', '\x3f', '\xbd', '\x98', '\x09',
+ '\x00', '\x38', '\xff', '\xed', '\x6a', '\x01', '\x0f', '\x05',
+ '\x6f', '\xae', '\x4c', '\x17', '\x00', '\x38', '\xb4', '\xb9',
+ '\xff', '\xed', '\x54', '\x01', '\x0c', '\x32', '\x6f', '\xae',
+ '\x62', '\x17', '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03',
+ '\x00', '\x38', '\x6f', '\x0e', '\x42', '\x03', '\x00', '\x38',
+ '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x62', '\xaa', '\x61', '\xba', '\x3f', '\xbd', '\x98', '\x09',
+ '\x00', '\x38', '\xff', '\xed', '\x22', '\x01', '\x0c', '\x32',
+ '\x6f', '\xae', '\x6e', '\x17', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\x6f', '\x0e', '\x42', '\x03',
+ '\x00', '\x38', '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x62', '\xaa', '\xe1', '\xaa', '\xda', '\x90',
+ '\x0f', '\x05', '\x7a', '\x0e', '\x08', '\x31', '\xea', '\xaa',
+ '\xf9', '\x80', '\x0f', '\x05', '\xea', '\xe0', '\x0c', '\x32',
+ '\x6f', '\xae', '\x7a', '\x17', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\x6f', '\x0e', '\x42', '\x03',
+ '\x00', '\x38', '\x04', '\x31', '\x61', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x08', '\x31', '\x64', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x0c', '\x31', '\x62', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x6f', '\x0e', '\x36', '\x13', '\x00', '\x38',
+ '\x61', '\xaa', '\x64', '\xba', '\x62', '\xca', '\xb0', '\xb9',
+ '\x6a', '\xa6', '\xac', '\x30', '\x10', '\x32', '\xc3', '\xa2',
+ '\xae', '\x20', '\x7a', '\x86', '\x62', '\xca', '\xef', '\xcd',
+ '\x00', '\x00', '\x01', '\x00', '\x64', '\xba', '\xb0', '\xb9',
+ '\x9e', '\xe0', '\x0f', '\x05', '\x6f', '\xde', '\xa0', '\x1a',
+ '\x00', '\x38', '\x6d', '\x9a', '\x7f', '\x0d', '\xc0', '\x01',
+ '\x00', '\xb0', '\xe9', '\x9b', '\x04', '\xd1', '\x59', '\x98',
+ '\x7f', '\x0d', '\xc4', '\x01', '\x00', '\xb0', '\xe9', '\x9b',
+ '\x6f', '\x1e', '\x12', '\x03', '\x00', '\x38', '\x6f', '\xae',
+ '\x82', '\x17', '\x00', '\x38', '\xb1', '\xb9', '\x04', '\x31',
+ '\x60', '\xae', '\x41', '\xb2', '\x3f', '\xbd', '\x42', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\x8a', '\x17', '\x00', '\x38',
+ '\xb1', '\xb9', '\x60', '\x9a', '\xb9', '\x09', '\x50', '\xe0',
+ '\x08', '\x32', '\x6f', '\xae', '\xfe', '\x16', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\x6f', '\x0e',
+ '\x42', '\x03', '\x00', '\x38', '\x04', '\x31', '\x61', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31', '\x62', '\xae',
+ '\x41', '\xb2', '\xb0', '\xb9', '\x61', '\x1a', '\x61', '\x9a',
+ '\x08', '\x30', '\x81', '\x92', '\xe1', '\x9b', '\x20', '\xe0',
+ '\x62', '\x3a', '\x1c', '\xe0', '\x0c', '\x32', '\x6f', '\xae',
+ '\x90', '\x17', '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03',
+ '\x00', '\x38', '\x63', '\xaa', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x42', '\x03', '\x00', '\x38', '\x0a', '\xe0', '\x0f', '\x05',
+ '\xa3', '\x0b', '\xff', '\x2d', '\x06', '\xfd', '\x0f', '\x05',
+ '\x6f', '\xae', '\x8a', '\x17', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\xbe', '\x4f', '\x04', '\xe2',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x8c', '\xe2',
+ '\xfe', '\x2b', '\x6a', '\x26', '\x6b', '\x06', '\x7f', '\x0d',
+ '\x0e', '\x1b', '\x00', '\x38', '\x70', '\x8a', '\x7f', '\x0d',
+ '\x04', '\x01', '\x00', '\x38', '\xea', '\xab', '\x6f', '\x9e',
+ '\x12', '\x1b', '\x00', '\x38', '\x49', '\x9a', '\xcf', '\x9e',
+ '\x01', '\x00', '\x86', '\x20', '\x0f', '\x05', '\x6f', '\xde',
+ '\xc6', '\x1a', '\x00', '\x38', '\x08', '\xd1', '\xea', '\xab',
+ '\x7f', '\x0d', '\x00', '\x01', '\x00', '\x38', '\xeb', '\xbb',
+ '\x6b', '\x96', '\x04', '\x92', '\xdf', '\x9d', '\xdc', '\x05',
+ '\xdd', '\x9b', '\x6f', '\x9e', '\xa4', '\x01', '\x00', '\xb0',
+ '\x69', '\xda', '\x6f', '\xde', '\x90', '\x1a', '\x00', '\x38',
+ '\xe9', '\xdb', '\x6f', '\xde', '\xd4', '\x01', '\x00', '\xb0',
+ '\x4d', '\x9a', '\x38', '\x93', '\x44', '\x93', '\xcd', '\x9b',
+ '\x6f', '\xde', '\xd4', '\x01', '\x00', '\xb0', '\x4d', '\x9a',
+ '\x07', '\x93', '\xcf', '\x9e', '\x04', '\x00', '\xf7', '\x30',
+ '\x0f', '\x05', '\x4d', '\x9a', '\x38', '\x93', '\x41', '\x93',
+ '\xcd', '\x9b', '\x3f', '\xbd', '\x0c', '\x02', '\x00', '\x38',
+ '\x6a', '\xa6', '\xf7', '\x30', '\x0f', '\x05', '\x6f', '\xce',
+ '\x0e', '\x1b', '\x00', '\x38', '\xec', '\x0a', '\x10', '\x80',
+ '\x0f', '\x05', '\x6f', '\xde', '\xd4', '\x01', '\x00', '\xb0',
+ '\x4d', '\x9a', '\x38', '\x93', '\x41', '\x93', '\xcd', '\x9b',
+ '\xec', '\x0a', '\xd7', '\x90', '\x71', '\x86', '\x22', '\xe0',
+ '\x62', '\x96', '\x7f', '\x0d', '\x0e', '\x1b', '\x00', '\x38',
+ '\xeb', '\xba', '\x14', '\x80', '\x71', '\x86', '\x3f', '\xbd',
+ '\x0c', '\x02', '\x00', '\x38', '\x7f', '\x0d', '\x0e', '\x1b',
+ '\x00', '\x38', '\xe0', '\x0a', '\xf1', '\x90', '\x71', '\x86',
+ '\x62', '\x96', '\x20', '\x96', '\xe9', '\x26', '\x0e', '\x30',
+ '\x62', '\xd6', '\x0d', '\x1c', '\x62', '\x96', '\x20', '\x96',
+ '\xe9', '\xd6', '\xf7', '\x20', '\x0f', '\x05', '\x6f', '\xae',
+ '\xa4', '\x17', '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03',
+ '\x00', '\x38', '\x61', '\xa6', '\x41', '\xb2', '\xbe', '\x2f',
+ '\x3e', '\xbe', '\x3f', '\x0d', '\x42', '\x03', '\x00', '\x38',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x8c', '\xe2', '\xfe', '\x2b',
+ '\x6b', '\x06', '\x6c', '\x26', '\xeb', '\xa6', '\x40', '\x00',
+ '\x6a', '\xc6', '\xe0', '\xc6', '\x32', '\x00', '\x71', '\x86',
+ '\x6c', '\xb6', '\x6c', '\x96', '\x79', '\x87', '\x61', '\xd6',
+ '\xc3', '\xd3', '\xed', '\x97', '\x49', '\xd6', '\xcb', '\x9b',
+ '\x4b', '\x9a', '\xcd', '\x96', '\x0c', '\x30', '\x7d', '\x87',
+ '\x6f', '\xae', '\xba', '\x17', '\x00', '\x38', '\x40', '\xe0',
+ '\xe2', '\xbb', '\xcb', '\xdf', '\x01', '\x12', '\xc4', '\x12',
+ '\x06', '\x30', '\xe0', '\xb6', '\xd7', '\x10', '\x6c', '\x96',
+ '\x04', '\xc2', '\xe0', '\xc6', '\xc5', '\x10', '\x0f', '\x05',
+ '\xe0', '\xa6', '\x4e', '\x00', '\x6a', '\xc6', '\xe0', '\xc6',
+ '\x40', '\x00', '\x71', '\x86', '\x6c', '\xa6', '\x61', '\x96',
+ '\xc3', '\x93', '\x6c', '\xd6', '\xe9', '\xd7', '\x4a', '\x9a',
+ '\xcd', '\x96', '\x22', '\x30', '\x01', '\x12', '\x81', '\x12',
+ '\xe2', '\xab', '\x6f', '\xae', '\xd8', '\x17', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\x62', '\xaa',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x42', '\x03', '\x00', '\x38',
+ '\x7a', '\x86', '\xbe', '\x2f', '\x3e', '\x0d', '\xc4', '\x12',
+ '\x08', '\x30', '\x01', '\xa2', '\xe0', '\xa6', '\xc9', '\x10',
+ '\x61', '\x96', '\x04', '\xc2', '\xe0', '\xc6', '\xb7', '\x10',
+ '\x0f', '\x05', '\x41', '\xa2', '\xbe', '\x2f', '\x3e', '\x0d',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x94', '\xe2', '\xfe', '\x4b',
+ '\x6b', '\x26', '\xeb', '\xa6', '\x5a', '\x90', '\x6a', '\x06',
+ '\x60', '\xa6', '\x7b', '\x86', '\x3f', '\xbd', '\x42', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\xf6', '\x17', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\xe2', '\x06',
+ '\x2a', '\x90', '\x74', '\x86', '\x60', '\x16', '\x60', '\x36',
+ '\x6f', '\xae', '\x4c', '\x18', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\x63', '\xae', '\x7b', '\x86',
+ '\x3f', '\xbd', '\x42', '\x03', '\x00', '\x38', '\x01', '\x42',
+ '\xc4', '\x42', '\x08', '\x30', '\x04', '\x12', '\xe2', '\x16',
+ '\xdf', '\x80', '\x0f', '\x05', '\x6f', '\xae', '\xb4', '\x16',
+ '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38',
+ '\x10', '\x02', '\xe2', '\x06', '\xad', '\x80', '\x60', '\xa6',
+ '\xbe', '\x4f', '\x3e', '\x0d', '\x05', '\xa1', '\x49', '\x98',
+ '\xc2', '\x92', '\x0a', '\x30', '\xc4', '\x92', '\x0e', '\x30',
+ '\x0f', '\x05', '\x7f', '\xb6', '\x7a', '\x86', '\x6a', '\xb9',
+ '\x5a', '\xa8', '\x7f', '\xb6', '\x0f', '\x05', '\x6a', '\xb9',
+ '\x6a', '\xaa', '\x7f', '\xb6', '\x0f', '\x05', '\x6a', '\xd6',
+ '\x05', '\xa1', '\x4a', '\xaa', '\x4a', '\x94', '\xc2', '\x92',
+ '\x0a', '\x30', '\xc4', '\x92', '\x10', '\x30', '\x0f', '\x05',
+ '\x7f', '\xb6', '\x7a', '\x86', '\x5c', '\xca', '\x6d', '\xb9',
+ '\xdc', '\xcb', '\x7f', '\xb6', '\x4a', '\xa4', '\x6c', '\xca',
+ '\x6d', '\xb9', '\xec', '\xcb', '\x4a', '\xa4', '\x7f', '\xb6',
+ '\x0f', '\x05', '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2',
+ '\xee', '\xbb', '\x04', '\xa1', '\x49', '\x9a', '\xcf', '\x9e',
+ '\x01', '\x00', '\x06', '\x20', '\x0f', '\x05', '\x24', '\xe0',
+ '\xc1', '\xc3', '\xcf', '\x9e', '\x02', '\x00', '\x0c', '\x20',
+ '\x6b', '\x96', '\xd0', '\x93', '\x69', '\xb7', '\xee', '\xbb',
+ '\x12', '\xe0', '\xc2', '\xc3', '\x6f', '\xae', '\x22', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38',
+ '\x0c', '\xe0', '\x0f', '\x05', '\x6c', '\xb6', '\x6e', '\xc6',
+ '\x3f', '\xbd', '\x26', '\x0a', '\x00', '\x38', '\x04', '\xe2',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2',
+ '\xfe', '\x0b', '\x6a', '\x06', '\x4f', '\xbc', '\xaa', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\x52', '\x0a',
+ '\x00', '\x38', '\x60', '\xa6', '\x4f', '\xbc', '\x55', '\x00',
+ '\x5f', '\xcc', '\xaa', '\x02', '\xbe', '\x0f', '\x3e', '\xbe',
+ '\x3f', '\x0d', '\x52', '\x0a', '\x00', '\x38', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x90', '\xe2', '\xfe', '\x3b', '\x6a', '\x26',
+ '\x04', '\xa1', '\x49', '\x9a', '\xcf', '\x9e', '\x02', '\x00',
+ '\x42', '\x20', '\x6b', '\x36', '\x6f', '\x0e', '\x04', '\x0a',
+ '\x00', '\x38', '\xb0', '\xb9', '\x6a', '\x16', '\x62', '\xa6',
+ '\x63', '\xb6', '\xb0', '\xb9', '\x61', '\xd6', '\xf0', '\xd3',
+ '\x1f', '\xdf', '\x40', '\x00', '\x6a', '\x96', '\xf0', '\x93',
+ '\x1f', '\x9f', '\x40', '\x00', '\xe9', '\xd6', '\x14', '\x20',
+ '\x7c', '\x86', '\x2f', '\x1f', '\x40', '\x00', '\x00', '\x00',
+ '\x2f', '\xaf', '\x40', '\x00', '\x00', '\x00', '\xea', '\x16',
+ '\x04', '\x30', '\x0f', '\x05', '\x41', '\xc2', '\x6c', '\xa6',
+ '\xbe', '\x3f', '\x3e', '\x0d', '\x6f', '\x1e', '\x04', '\x0a',
+ '\x00', '\x38', '\xb1', '\xb9', '\x4a', '\x04', '\x0f', '\x0f',
+ '\x40', '\x00', '\x62', '\xa6', '\x63', '\xb6', '\xb1', '\xb9',
+ '\x2f', '\xaf', '\x40', '\x00', '\x00', '\x00', '\xea', '\x06',
+ '\x3a', '\x25', '\xbe', '\x3f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\xa8', '\xe2', '\xfe', '\x8b', '\x6a', '\x36',
+ '\x04', '\xa1', '\x44', '\x9e', '\xcf', '\x9e', '\x02', '\x00',
+ '\x04', '\x20', '\x41', '\x72', '\x42', '\x72', '\x6f', '\x2e',
+ '\x52', '\x0a', '\x00', '\x38', '\x4f', '\xbc', '\x98', '\x00',
+ '\x4f', '\xcc', '\x55', '\x00', '\xb2', '\xb9', '\x50', '\xb2',
+ '\xe7', '\xb4', '\x6f', '\x1e', '\x04', '\x0a', '\x00', '\x38',
+ '\x63', '\xa6', '\xb1', '\xb9', '\xcf', '\xae', '\x51', '\x00',
+ '\xff', '\x2d', '\x9c', '\x01', '\x63', '\xa6', '\x51', '\xb2',
+ '\xe7', '\xb4', '\xb1', '\xb9', '\xcf', '\xae', '\x52', '\x00',
+ '\xff', '\x2d', '\x8c', '\x01', '\x63', '\xa6', '\x52', '\xb2',
+ '\xe7', '\xb4', '\xb1', '\xb9', '\xcf', '\xae', '\x59', '\x00',
+ '\xff', '\x2d', '\x7c', '\x01', '\x63', '\xa6', '\x24', '\xe1',
+ '\x70', '\x8a', '\x6f', '\xae', '\x3c', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\x63', '\xaa',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x42', '\x03', '\x00', '\x38',
+ '\x4f', '\xbc', '\x27', '\x00', '\xe7', '\xb4', '\x63', '\xa6',
+ '\xb1', '\xb9', '\x41', '\x92', '\xea', '\x94', '\x06', '\x32',
+ '\xe3', '\x9b', '\x86', '\x32', '\x4f', '\xbc', '\x2c', '\x00',
+ '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9', '\x6a', '\x86',
+ '\x55', '\xb2', '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9',
+ '\x6a', '\x06', '\x6a', '\xb6', '\x04', '\xb2', '\xe7', '\xb4',
+ '\x63', '\xa6', '\xb1', '\xb9', '\xcf', '\xae', '\x30', '\x00',
+ '\x3e', '\x20', '\x63', '\xa6', '\x4f', '\xbc', '\xf0', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\xb2', '\xb9', '\x63', '\xa6',
+ '\x3f', '\xbd', '\x9a', '\x0a', '\x00', '\x38', '\x63', '\xa6',
+ '\x4f', '\xbc', '\x90', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\xb2', '\xb9', '\x44', '\xb8', '\x2b', '\xb6', '\x63', '\xa6',
+ '\xb1', '\xb9', '\x4a', '\x54', '\x0f', '\x5f', '\x80', '\xff',
+ '\x63', '\xa6', '\x4f', '\xbc', '\x98', '\x00', '\x4f', '\xcc',
+ '\x55', '\x00', '\xb2', '\xb9', '\x10', '\xe0', '\x0f', '\x05',
+ '\x0f', '\x02', '\xe7', '\x04', '\x60', '\xb6', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x03', '\x00', '\x35', '\x35', '\x0a', '\x31',
+ '\xd8', '\x8b', '\xc8', '\x82', '\x12', '\xd0', '\x68', '\x46',
+ '\x6f', '\xae', '\x4e', '\x18', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\xd2', '\xe0', '\x7a', '\x86',
+ '\x65', '\x56', '\x94', '\x20', '\x81', '\x42', '\x90', '\xe0',
+ '\x74', '\x86', '\xc2', '\x03', '\x60', '\xb6', '\x2f', '\xb2',
+ '\xe7', '\xb4', '\x6f', '\x1e', '\x04', '\x0a', '\x00', '\x38',
+ '\x63', '\xa6', '\xb1', '\xb9', '\x6a', '\x66', '\x60', '\xb6',
+ '\x30', '\xb2', '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9',
+ '\xc8', '\xa3', '\x6a', '\x67', '\xc8', '\x63', '\x60', '\xb6',
+ '\x2d', '\xb2', '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9',
+ '\x6a', '\x26', '\x2e', '\x02', '\xe7', '\x04', '\x63', '\xa6',
+ '\x60', '\xb6', '\xb1', '\xb9', '\xc8', '\xa3', '\x6a', '\x27',
+ '\x65', '\x56', '\x0a', '\x30', '\x01', '\x22', '\x68', '\x96',
+ '\xa4', '\x96', '\x04', '\xe0', '\x81', '\x92', '\x64', '\x96',
+ '\x19', '\x95', '\x63', '\xd6', '\x2d', '\x95', '\x6d', '\x96',
+ '\x24', '\xe1', '\x6d', '\xda', '\x0c', '\x91', '\xed', '\xdb',
+ '\x10', '\x91', '\xe6', '\x6b', '\x14', '\x91', '\xe2', '\x2b',
+ '\x62', '\x26', '\x10', '\xd0', '\x0f', '\x05', '\x24', '\xe1',
+ '\x29', '\x6a', '\x24', '\xe1', '\xe9', '\x9b', '\x81', '\x22',
+ '\xf5', '\x20', '\x0f', '\x05', '\x24', '\xe1', '\x6d', '\xda',
+ '\x06', '\x31', '\xed', '\xda', '\x1e', '\x30', '\x65', '\x56',
+ '\x06', '\x30', '\x01', '\x42', '\x81', '\x42', '\x81', '\x42',
+ '\x65', '\x56', '\x0c', '\x30', '\xe8', '\x46', '\x64', '\x46',
+ '\x69', '\xa0', '\x64', '\x06', '\x08', '\xe0', '\x63', '\xa6',
+ '\x61', '\xb0', '\x64', '\x06', '\x63', '\xa6', '\x4f', '\xbc',
+ '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd',
+ '\x52', '\x0a', '\x00', '\x38', '\x12', '\xe0', '\x41', '\xa2',
+ '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\x52', '\x0a', '\x00', '\x38', '\x7a', '\x86',
+ '\xbe', '\x8f', '\x04', '\xe2', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x90', '\xe2', '\xfe', '\x3b', '\x06', '\xa1',
+ '\xa0', '\x0b', '\xff', '\x2d', '\x16', '\x04', '\x6a', '\x26',
+ '\x3f', '\xbd', '\x3e', '\x0b', '\x00', '\x38', '\x6a', '\xa6',
+ '\xff', '\x2d', '\x86', '\x03', '\x41', '\xa2', '\x62', '\xa6',
+ '\x3f', '\xbd', '\x9a', '\x0a', '\x00', '\x38', '\x62', '\xa6',
+ '\x4f', '\xbc', '\x90', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\x52', '\x0a', '\x00', '\x38', '\x6f', '\x1e',
+ '\x04', '\x0a', '\x00', '\x38', '\x62', '\xa6', '\x7b', '\x86',
+ '\xb1', '\xb9', '\x6a', '\x36', '\x04', '\x21', '\x40', '\xbe',
+ '\x4b', '\xb4', '\x2b', '\xb6', '\x62', '\xa6', '\xb1', '\xb9',
+ '\x42', '\x92', '\xc0', '\x9a', '\x1c', '\x20', '\x63', '\xc6',
+ '\xf0', '\xc3', '\x53', '\x94', '\xe9', '\xc6', '\x14', '\x20',
+ '\x63', '\x06', '\x6a', '\xd6', '\xf0', '\xd3', '\x5a', '\x94',
+ '\xe9', '\xd6', '\x0a', '\x20', '\xd0', '\x03', '\x6c', '\x36',
+ '\x6d', '\xa6', '\x63', '\x06', '\xd0', '\x03', '\x6a', '\x07',
+ '\x62', '\xa6', '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc',
+ '\x55', '\x05', '\x3f', '\xbd', '\x52', '\x0a', '\x00', '\x38',
+ '\xef', '\x0e', '\xc0', '\x00', '\x1f', '\x00', '\xff', '\x3d',
+ '\x48', '\x02', '\x0f', '\x05', '\x60', '\x90', '\x0f', '\x05',
+ '\xef', '\x0e', '\xc4', '\x22', '\x01', '\x00', '\xb0', '\x30',
+ '\x0f', '\x05', '\x20', '\x90', '\x0f', '\x05', '\xef', '\x0e',
+ '\x58', '\x22', '\x01', '\x00', '\xff', '\x3d', '\x5a', '\x01',
+ '\x0f', '\x05', '\xef', '\x0e', '\x5b', '\x22', '\x01', '\x00',
+ '\xff', '\x3d', '\x4e', '\x01', '\x0f', '\x05', '\xff', '\xed',
+ '\xb6', '\x02', '\x0f', '\x05', '\xef', '\x0e', '\xda', '\x22',
+ '\x01', '\x00', '\xff', '\x3d', '\x9c', '\x01', '\x0f', '\x05',
+ '\x14', '\x90', '\x0f', '\x05', '\xef', '\x0e', '\xd6', '\x22',
+ '\x01', '\x00', '\xff', '\x3d', '\x8c', '\x01', '\x0f', '\x05',
+ '\xff', '\xed', '\x94', '\x02', '\x0f', '\x05', '\xef', '\x0e',
+ '\x49', '\x22', '\x04', '\x00', '\xc4', '\x30', '\x0f', '\x05',
+ '\xff', '\xed', '\x84', '\x02', '\x0f', '\x05', '\xef', '\x0e',
+ '\xd7', '\x00', '\x20', '\x00', '\xff', '\x3d', '\x6a', '\x01',
+ '\x0f', '\x05', '\x20', '\x90', '\x0f', '\x05', '\xef', '\x0e',
+ '\xc2', '\x00', '\x1f', '\x00', '\xff', '\x3d', '\x00', '\x02',
+ '\x0f', '\x05', '\xef', '\x0e', '\xc9', '\x00', '\x1f', '\x00',
+ '\xff', '\x3d', '\x18', '\x02', '\x0f', '\x05', '\xff', '\xed',
+ '\x56', '\x02', '\x0f', '\x05', '\xef', '\x0e', '\x4f', '\x00',
+ '\x98', '\x00', '\xff', '\x3d', '\x3c', '\x01', '\x0f', '\x05',
+ '\x12', '\x90', '\x0f', '\x05', '\xef', '\x0e', '\x43', '\x00',
+ '\x98', '\x00', '\x76', '\x30', '\x0f', '\x05', '\xff', '\xed',
+ '\x36', '\x02', '\x0f', '\x05', '\xef', '\x0e', '\xc2', '\x00',
+ '\x98', '\x00', '\xff', '\x2d', '\x2a', '\x02', '\x0f', '\x05',
+ '\x6f', '\x1e', '\x32', '\x19', '\x00', '\x38', '\x61', '\x1a',
+ '\x6f', '\xde', '\x00', '\x00', '\x20', '\x00', '\x06', '\x21',
+ '\xed', '\xdb', '\x0c', '\x21', '\x70', '\x8a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x01', '\x00', '\x10', '\x21', '\xe9', '\x9b',
+ '\x5f', '\xd2', '\x14', '\x21', '\xed', '\xdb', '\x6f', '\x9e',
+ '\x00', '\x00', '\x1f', '\x00', '\x18', '\x21', '\xe9', '\x9b',
+ '\x1f', '\xdc', '\xe1', '\x7f', '\x1c', '\x21', '\xed', '\xdb',
+ '\x41', '\x92', '\x20', '\x21', '\xe9', '\x9b', '\x6f', '\xde',
+ '\x00', '\x80', '\x1f', '\x00', '\x24', '\x21', '\xed', '\xdb',
+ '\x5f', '\xdc', '\x00', '\x20', '\x28', '\x21', '\xed', '\xdb',
+ '\x42', '\xd2', '\x2c', '\x21', '\xed', '\xdb', '\x6f', '\xde',
+ '\x00', '\xc0', '\x1f', '\x00', '\xff', '\xed', '\x16', '\x01',
+ '\x0f', '\x05', '\x6f', '\x1e', '\x2e', '\x19', '\x00', '\x38',
+ '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00', '\x20', '\x00',
+ '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a',
+ '\x5f', '\x9c', '\x00', '\x40', '\x10', '\x21', '\xe9', '\x9b',
+ '\x41', '\xd2', '\x14', '\x21', '\xed', '\xdb', '\x18', '\x21',
+ '\xe9', '\x9b', '\x5f', '\x9c', '\x00', '\x20', '\x1c', '\x21',
+ '\xe9', '\x9b', '\x42', '\x92', '\x20', '\x21', '\xe9', '\x9b',
+ '\x1f', '\x9c', '\xfe', '\x7f', '\x24', '\x21', '\xe9', '\x9b',
+ '\x28', '\x21', '\xe9', '\x9b', '\x2c', '\x21', '\xed', '\xdb',
+ '\x6f', '\x9e', '\x00', '\x00', '\x01', '\x00', '\x30', '\x21',
+ '\xe9', '\x9b', '\x34', '\x21', '\xe9', '\x9b', '\x58', '\xe0',
+ '\x5f', '\xd2', '\x6f', '\x1e', '\x26', '\x19', '\x00', '\x38',
+ '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00', '\x10', '\x00',
+ '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a',
+ '\x5f', '\x9c', '\x00', '\x40', '\x10', '\x21', '\xe9', '\x9b',
+ '\x41', '\xd2', '\x14', '\x21', '\xed', '\xdb', '\x18', '\x21',
+ '\xe9', '\x9b', '\x5f', '\x9c', '\x00', '\x20', '\x1c', '\x21',
+ '\xe9', '\x9b', '\x42', '\x92', '\x20', '\x21', '\xe9', '\x9b',
+ '\x1f', '\x9c', '\xfe', '\x7f', '\x24', '\x21', '\xe9', '\x9b',
+ '\x28', '\x21', '\xe9', '\x9b', '\x2c', '\x21', '\xed', '\xdb',
+ '\x6f', '\x9e', '\x00', '\x00', '\x01', '\x00', '\x30', '\x21',
+ '\xe9', '\x9b', '\x34', '\x21', '\xe9', '\x9b', '\x4f', '\xd2',
+ '\x38', '\x21', '\xed', '\xdb', '\xff', '\xed', '\x3e', '\x01',
+ '\x0f', '\x05', '\x6f', '\x1e', '\x2a', '\x19', '\x00', '\x38',
+ '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00', '\x10', '\x00',
+ '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a',
+ '\x6f', '\xde', '\x00', '\x00', '\x01', '\x00', '\x10', '\x21',
+ '\xed', '\xdb', '\x4f', '\x92', '\x14', '\x21', '\xe9', '\x9b',
+ '\x6f', '\xde', '\x00', '\x00', '\x0f', '\x00', '\x18', '\x21',
+ '\xed', '\xdb', '\x1f', '\x9c', '\xf1', '\x7f', '\x1c', '\x21',
+ '\xe9', '\x9b', '\x41', '\x92', '\x20', '\x21', '\xe9', '\x9b',
+ '\x6f', '\xde', '\x00', '\x80', '\x0f', '\x00', '\x24', '\x21',
+ '\xed', '\xdb', '\x5f', '\xdc', '\x00', '\x20', '\x28', '\x21',
+ '\xed', '\xdb', '\x42', '\xd2', '\x2c', '\x21', '\xed', '\xdb',
+ '\x6f', '\xde', '\x00', '\xc0', '\x0f', '\x00', '\x30', '\x21',
+ '\xed', '\xdb', '\x5f', '\xdc', '\x00', '\x40', '\x34', '\x21',
+ '\xed', '\xdb', '\x38', '\x21', '\xe9', '\x9b', '\xce', '\xe0',
+ '\x0f', '\x05', '\x6f', '\x1e', '\x2e', '\x19', '\x00', '\x38',
+ '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00', '\x20', '\x00',
+ '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a',
+ '\x5f', '\xdc', '\x00', '\x20', '\x10', '\x21', '\xed', '\xdb',
+ '\x48', '\x92', '\x14', '\x21', '\xe9', '\x9b', '\x6f', '\x9e',
+ '\x00', '\x00', '\x01', '\x00', '\x18', '\x21', '\xe9', '\x9b',
+ '\x1c', '\x21', '\xe9', '\x9b', '\x62', '\xe0', '\x5f', '\xd2',
+ '\x6f', '\x1e', '\x32', '\x19', '\x00', '\x38', '\x61', '\x1a',
+ '\x6f', '\x9e', '\x00', '\x00', '\x20', '\x00', '\x06', '\x21',
+ '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a', '\x6f', '\xde',
+ '\x00', '\x00', '\x01', '\x00', '\x10', '\x21', '\xed', '\xdb',
+ '\x26', '\xe0', '\x5f', '\x92', '\x6f', '\x1e', '\x36', '\x19',
+ '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00',
+ '\x40', '\x00', '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21',
+ '\x70', '\x8a', '\x6f', '\xde', '\x00', '\x00', '\x01', '\x00',
+ '\x10', '\x21', '\xed', '\xdb', '\x4f', '\x9c', '\x3f', '\x00',
+ '\x14', '\x21', '\xe9', '\x9b', '\x6f', '\xde', '\x00', '\x00',
+ '\x1f', '\x00', '\x18', '\x21', '\xed', '\xdb', '\x5f', '\x9c',
+ '\x00', '\x20', '\x1c', '\x21', '\xe9', '\x9b', '\x48', '\xd2',
+ '\x20', '\x21', '\xed', '\xdb', '\x30', '\xe0', '\x0f', '\x05',
+ '\x04', '\x21', '\x49', '\x9a', '\x6f', '\xae', '\x6a', '\x18',
+ '\x00', '\x38', '\xcf', '\x9e', '\x01', '\x00', '\x08', '\x30',
+ '\x0f', '\x05', '\x6f', '\xae', '\x7c', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\x62', '\xaa',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x42', '\x03', '\x00', '\x38',
+ '\x7a', '\x86', '\xbe', '\x3f', '\x3e', '\x0d', '\x6f', '\x3e',
+ '\x12', '\x03', '\x00', '\x38', '\x6f', '\xae', '\x94', '\x18',
+ '\x00', '\x38', '\xb3', '\xb9', '\x04', '\x21', '\x40', '\x9e',
+ '\xcf', '\x9e', '\x01', '\x00', '\x0c', '\x20', '\x42', '\xd2',
+ '\x6f', '\xae', '\x9c', '\x18', '\x00', '\x38', '\xb3', '\xb9',
+ '\x42', '\xd2', '\xc0', '\xda', '\x32', '\x20', '\x47', '\xc2',
+ '\x06', '\x21', '\x6d', '\x9e', '\xc1', '\x93', '\xed', '\x9b',
+ '\x62', '\xd6', '\x0c', '\xd1', '\x69', '\x9a', '\xc1', '\x93',
+ '\x0c', '\xd1', '\xe9', '\x9b', '\x10', '\xd1', '\x69', '\x9a',
+ '\xc1', '\x93', '\x10', '\xd1', '\xe9', '\x9b', '\x81', '\xc2',
+ '\xe9', '\x60', '\x0c', '\xd2', '\x6f', '\xae', '\x9e', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38',
+ '\x6f', '\x0e', '\x12', '\x03', '\x00', '\x38', '\x6f', '\xae',
+ '\xa0', '\x18', '\x00', '\x38', '\xb0', '\xb9', '\x61', '\xa6',
+ '\xb0', '\xb9', '\x6f', '\xae', '\xd2', '\x17', '\x00', '\x38',
+ '\xb0', '\xb9', '\x62', '\xaa', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x42', '\x03', '\x00', '\x38', '\x41', '\xa2', '\xbe', '\x3f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x8c', '\xe2',
+ '\xfe', '\x2b', '\x6a', '\x16', '\x6b', '\x26', '\x6f', '\x0e',
+ '\x9a', '\x0a', '\x00', '\x38', '\xb0', '\xb9', '\x61', '\xa6',
+ '\x4f', '\xbc', '\x80', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\x52', '\x0a', '\x00', '\x38', '\x61', '\xa6',
+ '\xb0', '\xb9', '\x04', '\x11', '\x49', '\x9a', '\xcf', '\x9e',
+ '\x02', '\x00', '\x10', '\x20', '\x0f', '\x05', '\x6f', '\x9e',
+ '\x30', '\x00', '\x30', '\x00', '\x61', '\x29', '\xe9', '\x9b',
+ '\xbe', '\x2f', '\x3e', '\x0d', '\x4f', '\x9c', '\x30', '\x00',
+ '\x61', '\x29', '\xd9', '\x9b', '\xbe', '\x2f', '\x3e', '\x0d',
+ '\x84', '\xe2', '\xfe', '\x0b', '\x06', '\xa1', '\xeb', '\xba',
+ '\x10', '\x10', '\x0f', '\x05', '\x7a', '\x86', '\x7f', '\xb6',
+ '\xbe', '\x0f', '\x10', '\xa1', '\x6a', '\xaa', '\x7f', '\xb6',
+ '\xbe', '\x0f', '\x70', '\x86', '\x0c', '\xa1', '\xeb', '\xba',
+ '\x22', '\x10', '\x7d', '\x86', '\x14', '\xa1', '\xed', '\xda',
+ '\x10', '\x00', '\x79', '\x86', '\x10', '\xa1', '\x6c', '\xca',
+ '\x01', '\x92', '\x14', '\xa1', '\xe9', '\x9a', '\xf9', '\x10',
+ '\x2c', '\xd6', '\x0c', '\xa1', '\x29', '\xda', '\xe9', '\xb6',
+ '\xd1', '\x10', '\x0f', '\x05', '\x01', '\x02', '\xc7', '\x02',
+ '\xd3', '\x80', '\x0c', '\xa2', '\x7a', '\x86', '\x7f', '\xb6',
+ '\xbe', '\x0f', '\x84', '\xe2', '\xfe', '\x0b', '\x6a', '\x06',
+ '\x6b', '\xa6', '\x6d', '\xb6', '\x7d', '\x86', '\xeb', '\xd6',
+ '\x48', '\xa0', '\x0f', '\x05', '\x60', '\x9a', '\x2d', '\x96',
+ '\x49', '\xa5', '\x59', '\x9a', '\x4c', '\xd5', '\xd9', '\x9a',
+ '\x32', '\x30', '\x02', '\xd2', '\x82', '\xd2', '\x6b', '\x96',
+ '\x2a', '\x96', '\xe9', '\xa6', '\x20', '\x00', '\x6a', '\xc6',
+ '\x60', '\xc9', '\x59', '\x9a', '\xdf', '\x9e', '\xff', '\xff',
+ '\x0a', '\x30', '\x02', '\xc2', '\x82', '\xc2', '\x42', '\xa2',
+ '\x7f', '\xb6', '\xbe', '\x0f', '\x6b', '\x96', '\x2a', '\x96',
+ '\xe9', '\xc6', '\xe5', '\x10', '\x0f', '\x05', '\x41', '\xa2',
+ '\x7f', '\xb6', '\xbe', '\x0f', '\xeb', '\xd6', '\xbd', '\xb0',
+ '\x0f', '\x05', '\x7a', '\x86', '\x7f', '\xb6', '\xbe', '\x0f',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x90', '\xe2', '\xfe', '\x3b',
+ '\x73', '\x86', '\x72', '\x86', '\x6f', '\x0e', '\x3a', '\x19',
+ '\x00', '\x38', '\x41', '\x12', '\x04', '\x01', '\xc1', '\x1b',
+ '\xcf', '\x1e', '\x01', '\x00', '\x04', '\x30', '\x42', '\x92',
+ '\x44', '\x92', '\x05', '\x01', '\xc9', '\x9b', '\x60', '\xa6',
+ '\x3f', '\xbd', '\x2e', '\x0d', '\x00', '\x38', '\x6a', '\xa6',
+ '\x0c', '\x20', '\x0f', '\x05', '\xc1', '\x13', '\xcf', '\x1e',
+ '\x03', '\x00', '\xd9', '\x80', '\x0f', '\x05', '\x06', '\x01',
+ '\x23', '\x3a', '\x0f', '\x0c', '\x6c', '\x00', '\x01', '\x22',
+ '\xc1', '\x22', '\xc7', '\x80', '\x63', '\xa6', '\xbe', '\x3f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x98', '\xe2',
+ '\xfe', '\x5b', '\x6a', '\x16', '\x6b', '\x56', '\x6c', '\x36',
+ '\x70', '\x86', '\xed', '\x06', '\x74', '\xa0', '\x6d', '\x46',
+ '\x05', '\x11', '\x49', '\x9a', '\xcf', '\x9e', '\x02', '\x00',
+ '\x12', '\x20', '\x0f', '\x05', '\x43', '\x05', '\x59', '\x9a',
+ '\xdf', '\x9e', '\xff', '\xff', '\x54', '\x30', '\x42', '\x22',
+ '\x05', '\x11', '\x49', '\x9a', '\xcf', '\x9e', '\x04', '\x00',
+ '\x0e', '\x20', '\x61', '\xa6', '\x43', '\x05', '\x69', '\x9a',
+ '\xff', '\x92', '\x3e', '\x30', '\x44', '\x22', '\x61', '\xa6',
+ '\x3f', '\xbd', '\x9a', '\x0a', '\x00', '\x38', '\x61', '\xa6',
+ '\x4f', '\xbc', '\xa0', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\x52', '\x0a', '\x00', '\x38', '\x65', '\xb6',
+ '\x20', '\xb6', '\x63', '\xc6', '\x20', '\xc6', '\x61', '\xa6',
+ '\x3f', '\xbd', '\x26', '\x0a', '\x00', '\x38', '\x6a', '\x26',
+ '\x61', '\xa6', '\x65', '\xb6', '\x20', '\xb6', '\x3f', '\xbd',
+ '\xc6', '\x0a', '\x00', '\x38', '\x6a', '\xa6', '\xf3', '\x20',
+ '\x61', '\xa6', '\x22', '\x06', '\xe4', '\x06', '\x91', '\xb0',
+ '\x0f', '\x05', '\xbe', '\x5f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\xa4', '\xe2', '\xfe', '\x8b', '\x6a', '\x16',
+ '\x6b', '\x06', '\x6c', '\x86', '\x3f', '\xbd', '\x58', '\x12',
+ '\x00', '\x38', '\x6a', '\x96', '\x1a', '\x30', '\x41', '\xa2',
+ '\x60', '\xd6', '\x28', '\xd6', '\xe9', '\xd6', '\x14', '\x80',
+ '\x0f', '\x05', '\x6f', '\xae', '\xa4', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\x42', '\xa2',
+ '\xbe', '\x8f', '\x3e', '\x0d', '\x6f', '\xce', '\x40', '\x19',
+ '\x00', '\x38', '\x6c', '\xca', '\xec', '\x06', '\x1e', '\x10',
+ '\xec', '\xd6', '\x6f', '\x9e', '\x12', '\x1a', '\x00', '\x38',
+ '\x09', '\x91', '\x70', '\x8a', '\x16', '\x91', '\xe1', '\x1b',
+ '\xac', '\x06', '\x1a', '\x91', '\xe0', '\x0b', '\x1e', '\x91',
+ '\xe8', '\x8b', '\x74', '\xe0', '\x0f', '\x05', '\x5a', '\x80',
+ '\x6c', '\x96', '\x6f', '\xde', '\x12', '\x1a', '\x00', '\x38',
+ '\x01', '\xd1', '\xe1', '\x1b', '\x05', '\xd1', '\xe0', '\x0b',
+ '\xa0', '\x96', '\x09', '\xd1', '\xe9', '\x9b', '\x29', '\x16',
+ '\x16', '\xd1', '\xe1', '\x1b', '\x1a', '\xd1', '\x70', '\x8a',
+ '\x68', '\xc6', '\xa9', '\xc6', '\x1e', '\xd1', '\xec', '\xcb',
+ '\x46', '\xe0', '\x0f', '\x05', '\x6f', '\xae', '\xc0', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38',
+ '\x44', '\xa2', '\xbe', '\x8f', '\x3e', '\x0d', '\x6f', '\xae',
+ '\xd4', '\x18', '\x00', '\x38', '\x3f', '\xbd', '\x12', '\x03',
+ '\x00', '\x38', '\x60', '\xa6', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x42', '\x03', '\x00', '\x38', '\x43', '\xa2', '\xbe', '\x8f',
+ '\x3e', '\x0d', '\x6f', '\x9e', '\x12', '\x1a', '\x00', '\x38',
+ '\x01', '\x91', '\xe1', '\x1b', '\x05', '\x91', '\xe0', '\x0b',
+ '\x09', '\x91', '\xe8', '\x8b', '\x1e', '\x91', '\x70', '\x8a',
+ '\x6f', '\xce', '\x12', '\x1a', '\x00', '\x38', '\x7c', '\x0a',
+ '\x0d', '\xc1', '\x70', '\x8a', '\x11', '\xc1', '\x70', '\x8a',
+ '\x15', '\xc1', '\x79', '\x0e', '\x7f', '\x0d', '\x34', '\x1a',
+ '\x00', '\x38', '\x70', '\x8a', '\x7f', '\x0d', '\x38', '\x1a',
+ '\x00', '\x38', '\x70', '\x8a', '\x0d', '\x91', '\xe8', '\x8a',
+ '\xff', '\x8d', '\xc0', '\x01', '\x75', '\x86', '\x65', '\x56',
+ '\x04', '\x20', '\x6c', '\xd6', '\x15', '\xd2', '\x65', '\x96',
+ '\x29', '\x55', '\x65', '\x36', '\x23', '\x95', '\x09', '\xd1',
+ '\x69', '\x9a', '\x24', '\x30', '\x2c', '\x36', '\x0d', '\xd1',
+ '\xe9', '\x9a', '\x1c', '\x80', '\x0f', '\x05', '\x09', '\x31',
+ '\x69', '\x9a', '\x10', '\x30', '\x0f', '\x05', '\x83', '\x0b',
+ '\x0a', '\x20', '\x0f', '\x05', '\x0d', '\x31', '\xe9', '\x9a',
+ '\x06', '\x20', '\x0f', '\x05', '\x65', '\x56', '\x35', '\x35',
+ '\x11', '\x31', '\x63', '\x3a', '\xca', '\x32', '\x4d', '\x90',
+ '\x65', '\x96', '\x29', '\x55', '\x65', '\x36', '\x23', '\x95',
+ '\x2f', '\x3e', '\x12', '\x1a', '\x00', '\x38', '\x05', '\x31',
+ '\x64', '\x4a', '\x0d', '\x31', '\x69', '\x9a', '\x29', '\x46',
+ '\x01', '\x31', '\x27', '\x9a', '\x65', '\xa6', '\xc3', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\x2f', '\xae', '\x3a', '\x19', '\x00', '\x38', '\x64', '\xb6',
+ '\x3f', '\xbd', '\xa8', '\x11', '\x00', '\x38', '\x83', '\x0b',
+ '\x24', '\x30', '\x6a', '\x66', '\x65', '\xa6', '\xc3', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\x2f', '\xae', '\x3a', '\x19', '\x00', '\x38', '\x64', '\xb6',
+ '\x3f', '\xbd', '\xc6', '\x0a', '\x00', '\x38', '\x6a', '\xa6',
+ '\xe5', '\x20', '\x65', '\xa6', '\x73', '\x0a', '\x65', '\x26',
+ '\xc3', '\x23', '\xa5', '\x26', '\xc2', '\x23', '\xa5', '\x26',
+ '\xc2', '\x23', '\x2f', '\x2e', '\x3a', '\x19', '\x00', '\x38',
+ '\x62', '\xa6', '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc',
+ '\x55', '\x05', '\x3f', '\xbd', '\x52', '\x0a', '\x00', '\x38',
+ '\x62', '\xa6', '\x64', '\xb6', '\x67', '\xc6', '\x66', '\xd6',
+ '\x3f', '\xbd', '\xfa', '\x11', '\x00', '\x38', '\x4a', '\xa6',
+ '\x28', '\x20', '\x7b', '\x86', '\x0d', '\x31', '\x69', '\xde',
+ '\x26', '\xd6', '\xe9', '\xdb', '\x11', '\x31', '\x70', '\x8a',
+ '\x62', '\xaa', '\x24', '\xa6', '\x3f', '\xbd', '\x42', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\xde', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\xaa', '\xe0',
+ '\x0f', '\x05', '\xcf', '\xae', '\x01', '\x00', '\x4c', '\x30',
+ '\x0f', '\x05', '\xcf', '\xae', '\x02', '\x00', '\x46', '\x20',
+ '\x65', '\xa6', '\x62', '\xaa', '\x24', '\xa6', '\x6f', '\x1e',
+ '\x42', '\x03', '\x00', '\x38', '\x7b', '\x86', '\xb1', '\xb9',
+ '\x6f', '\x0e', '\x12', '\x03', '\x00', '\x38', '\x6f', '\xae',
+ '\xf2', '\x18', '\x00', '\x38', '\xb0', '\xb9', '\x66', '\xa6',
+ '\x7b', '\x86', '\xb1', '\xb9', '\x6f', '\xae', '\xfe', '\x18',
+ '\x00', '\x38', '\xb0', '\xb9', '\x62', '\xa6', '\x64', '\xb6',
+ '\x3f', '\xbd', '\x5a', '\x11', '\x00', '\x38', '\x41', '\x92',
+ '\xc3', '\x9b', '\x11', '\x31', '\x6d', '\x9e', '\x01', '\x92',
+ '\x58', '\xe0', '\xed', '\x9b', '\x65', '\xa6', '\xc3', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\x6f', '\xad', '\x3a', '\x19', '\x00', '\x38', '\x62', '\xae',
+ '\x24', '\xa6', '\x6f', '\x1e', '\x42', '\x03', '\x00', '\x38',
+ '\x7b', '\x86', '\xb1', '\xb9', '\x6f', '\x0e', '\x12', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\x06', '\x19', '\x00', '\x38',
+ '\xb0', '\xb9', '\x66', '\xa6', '\x7b', '\x86', '\xb1', '\xb9',
+ '\x6f', '\xae', '\xfe', '\x18', '\x00', '\x38', '\xb0', '\xb9',
+ '\x62', '\xa6', '\x64', '\xb6', '\x67', '\xc6', '\x66', '\xd6',
+ '\x3f', '\xbd', '\xaa', '\x12', '\x00', '\x38', '\x0d', '\x31',
+ '\x6d', '\x9e', '\x26', '\x96', '\xed', '\x9b', '\x11', '\x31',
+ '\x70', '\x8a', '\x6f', '\xce', '\x12', '\x1a', '\x00', '\x38',
+ '\x0d', '\xc1', '\x69', '\x9a', '\x7f', '\x0d', '\x34', '\x1a',
+ '\x00', '\x38', '\x29', '\x9a', '\xe8', '\x96', '\xff', '\x1d',
+ '\x44', '\xfe', '\x0f', '\x05', '\x75', '\x86', '\x6f', '\x2e',
+ '\x3a', '\x19', '\x00', '\x38', '\x6f', '\x1e', '\x12', '\x1a',
+ '\x00', '\x38', '\x09', '\x11', '\xa0', '\x0b', '\x4c', '\x30',
+ '\x7b', '\x86', '\x62', '\xaa', '\x3f', '\xbd', '\x42', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\x12', '\x19', '\x00', '\x38',
+ '\x3f', '\xbd', '\x12', '\x03', '\x00', '\x38', '\x70', '\x86',
+ '\x09', '\x11', '\xe0', '\x0a', '\x22', '\x00', '\x0f', '\x05',
+ '\x05', '\x11', '\x29', '\x0a', '\x01', '\x11', '\x6d', '\xda',
+ '\x62', '\x99', '\x59', '\x9a', '\x4d', '\x05', '\xd9', '\x9a',
+ '\xff', '\x2d', '\x9a', '\xfd', '\x0f', '\x05', '\x02', '\x02',
+ '\x09', '\x11', '\xe0', '\x0a', '\xe3', '\x10', '\x0f', '\x05',
+ '\x6f', '\xae', '\x22', '\x19', '\x00', '\x38', '\x3f', '\xbd',
+ '\x12', '\x03', '\x00', '\x38', '\x0f', '\x2c', '\x6c', '\x00',
+ '\x01', '\x52', '\xc1', '\x52', '\xa5', '\x80', '\x15', '\x12',
+ '\x7a', '\x86', '\xbe', '\x8f', '\x3e', '\x0d', '\x00', '\x00',
+ '\x7f', '\xb6', '\x0f', '\x05', '\x00', '\x00', '\x00', '\x00',
+ '\x0d', '\x0a', '\x0d', '\x0a', '\x44', '\x65', '\x76', '\x69',
+ '\x63', '\x65', '\x20', '\x49', '\x44', '\x20', '\x3d', '\x20',
+ '\x00', '\x00', '\x43', '\x68', '\x65', '\x63', '\x6b', '\x73',
+ '\x75', '\x6d', '\x20', '\x6f', '\x66', '\x20', '\x62', '\x6f',
+ '\x6f', '\x74', '\x6c', '\x6f', '\x61', '\x64', '\x65', '\x72',
+ '\x20', '\x69', '\x73', '\x20', '\x00', '\x00', '\x57', '\x61',
+ '\x69', '\x74', '\x69', '\x6e', '\x67', '\x20', '\x66', '\x6f',
+ '\x72', '\x20', '\x6c', '\x6f', '\x61', '\x64', '\x20', '\x69',
+ '\x6e', '\x66', '\x6f', '\x2e', '\x0d', '\x0a', '\x00', '\x00',
+ '\x47', '\x6f', '\x74', '\x20', '\x6c', '\x6f', '\x61', '\x64',
+ '\x20', '\x69', '\x6e', '\x66', '\x6f', '\x2e', '\x0d', '\x0a',
+ '\x00', '\x00', '\x50', '\x41', '\x43', '\x4b', '\x45', '\x54',
+ '\x5f', '\x49', '\x4e', '\x46', '\x4f', '\x0d', '\x0a', '\x00',
+ '\x53', '\x45', '\x54', '\x5f', '\x52', '\x45', '\x47', '\x49',
+ '\x53', '\x54', '\x45', '\x52', '\x0d', '\x0a', '\x00', '\x00',
+ '\x47', '\x45', '\x54', '\x5f', '\x52', '\x45', '\x47', '\x49',
+ '\x53', '\x54', '\x45', '\x52', '\x0d', '\x0a', '\x00', '\x00',
+ '\x50', '\x41', '\x55', '\x53', '\x45', '\x5f', '\x4c', '\x4f',
+ '\x4f', '\x50', '\x0d', '\x0a', '\x00', '\x00', '\x4d', '\x45',
+ '\x4d', '\x5f', '\x56', '\x45', '\x52', '\x49', '\x46', '\x59',
+ '\x0d', '\x0a', '\x00', '\x00', '\x76', '\x65', '\x72', '\x69',
+ '\x66', '\x79', '\x20', '\x66', '\x61', '\x69', '\x6c', '\x65',
+ '\x64', '\x0d', '\x0a', '\x00', '\x4d', '\x45', '\x4d', '\x5f',
+ '\x54', '\x45', '\x53', '\x54', '\x0d', '\x0a', '\x00', '\x00',
+ '\x23', '\x23', '\x23', '\x20', '\x4d', '\x65', '\x6d', '\x6f',
+ '\x72', '\x79', '\x20', '\x74', '\x65', '\x73', '\x74', '\x20',
+ '\x66', '\x61', '\x69', '\x6c', '\x65', '\x64', '\x20', '\x61',
+ '\x74', '\x20', '\x00', '\x00', '\x50', '\x61', '\x73', '\x73',
+ '\x65', '\x64', '\x20', '\x6d', '\x65', '\x6d', '\x6f', '\x72',
+ '\x79', '\x20', '\x74', '\x65', '\x73', '\x74', '\x2e', '\x0d',
+ '\x0a', '\x00', '\x4d', '\x45', '\x4d', '\x5f', '\x44', '\x55',
+ '\x4d', '\x50', '\x0d', '\x0a', '\x00', '\x00', '\x4d', '\x45',
+ '\x4d', '\x5f', '\x43', '\x4c', '\x45', '\x41', '\x52', '\x0d',
+ '\x0a', '\x00', '\x46', '\x4c', '\x41', '\x53', '\x48', '\x0d',
+ '\x0a', '\x00', '\x4a', '\x55', '\x4d', '\x50', '\x0d', '\x0a',
+ '\x00', '\x00', '\x45', '\x4e', '\x44', '\x0d', '\x0a', '\x00',
+ '\x23', '\x23', '\x23', '\x20', '\x55', '\x6e', '\x6b', '\x6e',
+ '\x6f', '\x77', '\x6e', '\x20', '\x74', '\x79', '\x70', '\x65',
+ '\x3a', '\x20', '\x00', '\x00', '\x43', '\x68', '\x65', '\x63',
+ '\x6b', '\x73', '\x75', '\x6d', '\x20', '\x6f', '\x66', '\x20',
+ '\x66', '\x69', '\x6c', '\x65', '\x20', '\x69', '\x73', '\x20',
+ '\x00', '\x00', '\x23', '\x23', '\x23', '\x20', '\x4d', '\x65',
+ '\x6d', '\x6f', '\x72', '\x79', '\x20', '\x74', '\x65', '\x73',
+ '\x74', '\x20', '\x31', '\x20', '\x66', '\x61', '\x69', '\x6c',
+ '\x65', '\x64', '\x20', '\x61', '\x74', '\x20', '\x00', '\x00',
+ '\x23', '\x23', '\x23', '\x20', '\x4d', '\x65', '\x6d', '\x6f',
+ '\x72', '\x79', '\x20', '\x74', '\x65', '\x73', '\x74', '\x20',
+ '\x32', '\x20', '\x66', '\x61', '\x69', '\x6c', '\x65', '\x64',
+ '\x20', '\x61', '\x74', '\x20', '\x00', '\x00', '\x20', '\x3a',
+ '\x00', '\x00', '\x38', '\x4d', '\x62', '\x20', '\x42', '\x42',
+ '\x00', '\x00', '\x38', '\x4d', '\x62', '\x20', '\x54', '\x42',
+ '\x00', '\x00', '\x31', '\x36', '\x4d', '\x62', '\x20', '\x42',
+ '\x42', '\x00', '\x31', '\x36', '\x4d', '\x62', '\x20', '\x54',
+ '\x42', '\x00', '\x33', '\x32', '\x4d', '\x62', '\x20', '\x54',
+ '\x42', '\x00', '\x55', '\x6e', '\x73', '\x75', '\x70', '\x70',
+ '\x6f', '\x72', '\x74', '\x65', '\x64', '\x20', '\x69', '\x6e',
+ '\x74', '\x65', '\x72', '\x6c', '\x65', '\x61', '\x76', '\x65',
+ '\x21', '\x0a', '\x00', '\x00', '\x46', '\x6f', '\x75', '\x6e',
+ '\x64', '\x20', '\x31', '\x20', '\x78', '\x20', '\x43', '\x46',
+ '\x49', '\x20', '\x61', '\x74', '\x20', '\x00', '\x54', '\x6f',
+ '\x6f', '\x20', '\x6d', '\x61', '\x6e', '\x79', '\x20', '\x72',
+ '\x65', '\x67', '\x69', '\x6f', '\x6e', '\x73', '\x20', '\x6f',
+ '\x6e', '\x20', '\x63', '\x68', '\x69', '\x70', '\x21', '\x0a',
+ '\x00', '\x00', '\x4e', '\x6f', '\x20', '\x73', '\x69', '\x6e',
+ '\x67', '\x6c', '\x65', '\x20', '\x78', '\x31', '\x36', '\x20',
+ '\x61', '\x74', '\x20', '\x00', '\x4e', '\x6f', '\x20', '\x69',
+ '\x6e', '\x74', '\x65', '\x72', '\x6c', '\x65', '\x61', '\x76',
+ '\x65', '\x64', '\x20', '\x78', '\x31', '\x36', '\x20', '\x61',
+ '\x74', '\x20', '\x00', '\x00', '\x46', '\x6f', '\x75', '\x6e',
+ '\x64', '\x20', '\x00', '\x00', '\x31', '\x00', '\x32', '\x00',
+ '\x20', '\x78', '\x20', '\x00', '\x46', '\x61', '\x74', '\x61',
+ '\x6c', '\x3a', '\x20', '\x66', '\x6c', '\x61', '\x73', '\x68',
+ '\x20', '\x69', '\x73', '\x20', '\x74', '\x6f', '\x6f', '\x20',
+ '\x73', '\x6d', '\x61', '\x6c', '\x6c', '\x2e', '\x0a', '\x00',
+ '\x53', '\x65', '\x63', '\x74', '\x6f', '\x72', '\x20', '\x65',
+ '\x72', '\x61', '\x73', '\x65', '\x20', '\x65', '\x72', '\x72',
+ '\x6f', '\x72', '\x0a', '\x00', '\x45', '\x72', '\x72', '\x6f',
+ '\x72', '\x20', '\x61', '\x74', '\x20', '\x00', '\x3a', '\x20',
+ '\x4e', '\x6f', '\x20', '\x6e', '\x65', '\x65', '\x64', '\x20',
+ '\x74', '\x6f', '\x20', '\x77', '\x72', '\x69', '\x74', '\x65',
+ '\x0a', '\x00', '\x3a', '\x20', '\x45', '\x72', '\x61', '\x73',
+ '\x69', '\x6e', '\x67', '\x20', '\x00', '\x00', '\x20', '\x62',
+ '\x79', '\x74', '\x65', '\x73', '\x0a', '\x00', '\x3a', '\x20',
+ '\x57', '\x72', '\x69', '\x74', '\x69', '\x6e', '\x67', '\x20',
+ '\x00', '\x00', '\x3a', '\x20', '\x56', '\x65', '\x72', '\x69',
+ '\x66', '\x79', '\x69', '\x6e', '\x67', '\x2e', '\x2e', '\x2e',
+ '\x00', '\x00', '\x4f', '\x4b', '\x0a', '\x00', '\xfa', '\x17',
+ '\x00', '\x38', '\x02', '\x18', '\x00', '\x38', '\x0a', '\x18',
+ '\x00', '\x38', '\x12', '\x18', '\x00', '\x38', '\x1a', '\x18',
+ '\x00', '\x38', '\x00', '\x00', '\x00', '\x80', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x84', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x54', '\x68', '\x69', '\x73',
+ '\x20', '\x62', '\x6f', '\x6f', '\x74', '\x6c', '\x6f', '\x61',
+ '\x64', '\x65', '\x72', '\x20', '\x77', '\x61', '\x73', '\x20',
+ '\x62', '\x75', '\x69', '\x6c', '\x74', '\x20', '\x62', '\x79',
+ '\x20', '\x72', '\x6f', '\x6f', '\x74', '\x20', '\x6f', '\x6e',
+ '\x20', '\x57', '\x65', '\x64', '\x20', '\x4d', '\x61', '\x79',
+ '\x20', '\x31', '\x36', '\x20', '\x32', '\x31', '\x3a', '\x33',
+ '\x31', '\x3a', '\x34', '\x34', '\x20', '\x43', '\x45', '\x53',
+ '\x54', '\x20', '\x32', '\x30', '\x30', '\x37', '\x2e', '\x0d',
+ '\x0a', '\x00'
+};
diff --git a/package/etrax-tools/src/e100boot/sbl/ser_noleds_ima.c b/package/etrax-tools/src/e100boot/sbl/ser_noleds_ima.c
new file mode 100644
index 000000000..70c599308
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/ser_noleds_ima.c
@@ -0,0 +1,807 @@
+
+/* cconv 1.2 12/16/97, Copyright (C) 1997, Axis Communications AB */
+
+const char ser_noleds_ima[] =
+{
+ '\x0f', '\x05', '\x0f', '\x05', '\x6f', '\xee', '\x00', '\x1f',
+ '\x00', '\x38', '\x3f', '\x0d', '\x08', '\x01', '\x00', '\x38',
+ '\x78', '\x56', '\x34', '\x12', '\x21', '\x43', '\x65', '\x87',
+ '\x6f', '\xde', '\x20', '\x00', '\x00', '\xb0', '\x5f', '\x9c',
+ '\x65', '\x6f', '\xed', '\x9b', '\x5f', '\x9c', '\x25', '\x2f',
+ '\x7f', '\x0d', '\xdc', '\x15', '\x00', '\x38', '\xe9', '\x9b',
+ '\xed', '\x9b', '\x3f', '\x0d', '\x28', '\x01', '\x00', '\x38',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x7f', '\x0d', '\x7e', '\x1a',
+ '\x00', '\x38', '\x70', '\x8a', '\x6f', '\x9e', '\x20', '\x00',
+ '\x00', '\xb0', '\x69', '\x9a', '\x79', '\x67', '\x7f', '\x0d',
+ '\x32', '\x1a', '\x00', '\x38', '\xe9', '\x9b', '\x6f', '\x9e',
+ '\x22', '\x00', '\x00', '\xb0', '\x59', '\x9a', '\x59', '\x94',
+ '\x7f', '\x0d', '\x9a', '\x1a', '\x00', '\x38', '\xe9', '\x9b',
+ '\x6f', '\x9e', '\x04', '\x00', '\x00', '\xb0', '\x69', '\x9a',
+ '\x06', '\x93', '\xe1', '\x93', '\x81', '\x92', '\x7f', '\x0d',
+ '\x82', '\x1a', '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\x0d',
+ '\x44', '\x1a', '\x00', '\x38', '\x70', '\x4a', '\x3f', '\xbd',
+ '\x28', '\x02', '\x00', '\x38', '\x3f', '\xbd', '\xac', '\x02',
+ '\x00', '\x38', '\x3f', '\xbd', '\xcc', '\x01', '\x00', '\x38',
+ '\x6a', '\xa6', '\xf7', '\x30', '\x0f', '\x05', '\x6f', '\x9e',
+ '\x00', '\x01', '\x00', '\x38', '\x69', '\x9a', '\x7f', '\x0d',
+ '\x7e', '\x1a', '\x00', '\x38', '\xe9', '\x9a', '\x24', '\x80',
+ '\x0f', '\x05', '\x6f', '\x9e', '\x82', '\x1a', '\x00', '\x38',
+ '\x49', '\x9a', '\xcf', '\x9e', '\x01', '\x00', '\xd3', '\x20',
+ '\x0f', '\x05', '\x6f', '\xde', '\xd4', '\x01', '\x00', '\xb0',
+ '\x4d', '\x9a', '\x38', '\x93', '\x41', '\x93', '\xcd', '\x9b',
+ '\xc1', '\xe0', '\x0f', '\x05', '\x3e', '\xbe', '\x3f', '\x0d',
+ '\x6c', '\x03', '\x00', '\x38', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x3f', '\xbd', '\x68', '\x02', '\x00', '\x38', '\x6a', '\xa6',
+ '\x16', '\x20', '\x41', '\x92', '\x3f', '\xbd', '\xf4', '\x01',
+ '\x00', '\x38', '\x6a', '\xa6', '\x0a', '\x30', '\x79', '\x86',
+ '\x3f', '\xbd', '\xac', '\x02', '\x00', '\x38', '\x79', '\x86',
+ '\x69', '\xa6', '\x3e', '\x0d', '\x84', '\xe2', '\x6f', '\x9e',
+ '\x22', '\x00', '\x00', '\xb0', '\x59', '\x9a', '\x59', '\x94',
+ '\xee', '\x9b', '\x6f', '\xce', '\x9a', '\x1a', '\x00', '\x38',
+ '\x6c', '\x9a', '\x6e', '\xda', '\xad', '\x96', '\xb9', '\x96',
+ '\xdf', '\x9c', '\x80', '\x25', '\x0a', '\xd0', '\x0f', '\x05',
+ '\x6e', '\x9a', '\xec', '\x9b', '\x04', '\xe0', '\x41', '\xa2',
+ '\x7a', '\x86', '\x7f', '\xb6', '\x04', '\xe2', '\x00', '\x00',
+ '\x6f', '\x9e', '\xdc', '\x15', '\x00', '\x38', '\x79', '\x8a',
+ '\x7f', '\x0d', '\x64', '\x00', '\x00', '\xb0', '\x70', '\x8a',
+ '\x4f', '\xde', '\x55', '\x00', '\x7f', '\x0d', '\x63', '\x00',
+ '\x00', '\xb0', '\xcd', '\xdb', '\x0b', '\xd2', '\x7f', '\x0d',
+ '\x62', '\x00', '\x00', '\xb0', '\xcd', '\xdb', '\xa0', '\xd2',
+ '\xc9', '\xdb', '\x7f', '\x0d', '\x61', '\x00', '\x00', '\xb0',
+ '\xcd', '\xdb', '\x41', '\x92', '\x7f', '\x0d', '\x84', '\x1a',
+ '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\xb6', '\x0f', '\x05',
+ '\x6f', '\x9e', '\x60', '\x00', '\x00', '\xb0', '\x69', '\x9a',
+ '\x59', '\xb4', '\x1f', '\xbf', '\xff', '\x01', '\x88', '\x93',
+ '\x2e', '\xa0', '\x0f', '\x05', '\x6f', '\xce', '\x7e', '\x1a',
+ '\x00', '\x38', '\x6c', '\x9a', '\x6f', '\xde', '\x04', '\x01',
+ '\x00', '\x38', '\x6d', '\x99', '\xcb', '\xbb', '\x01', '\x92',
+ '\xec', '\x9b', '\x6f', '\x9e', '\x22', '\x00', '\x00', '\xb0',
+ '\x49', '\x9a', '\x49', '\x94', '\x7f', '\x0d', '\x9a', '\x1a',
+ '\x00', '\x38', '\xe9', '\x9b', '\x7f', '\xb6', '\x41', '\xa2',
+ '\x7f', '\xb6', '\x7a', '\x86', '\x6f', '\x9e', '\x61', '\x00',
+ '\x00', '\xb0', '\x49', '\x9a', '\x85', '\x93', '\xf5', '\xa0',
+ '\x0f', '\x05', '\x4f', '\x9e', '\x2b', '\x00', '\x7f', '\x0d',
+ '\xdc', '\x15', '\x00', '\x38', '\xc9', '\x9b', '\x7f', '\x0d',
+ '\x60', '\x00', '\x00', '\xb0', '\xc9', '\x9b', '\x7f', '\xb6',
+ '\x0f', '\x05', '\x8a', '\x0b', '\x28', '\x30', '\x0f', '\x05',
+ '\x6f', '\x9e', '\x61', '\x00', '\x00', '\xb0', '\x49', '\x9a',
+ '\x85', '\x93', '\x14', '\xa0', '\x0f', '\x05', '\x6f', '\x9e',
+ '\xdc', '\x15', '\x00', '\x38', '\x4a', '\xde', '\xc9', '\xdb',
+ '\x7f', '\x0d', '\x60', '\x00', '\x00', '\xb0', '\xcd', '\xdb',
+ '\x8a', '\x0b', '\xdd', '\x20', '\x0f', '\x05', '\x7f', '\xb6',
+ '\x0f', '\x05', '\xfc', '\xe1', '\x7e', '\xbe', '\x8e', '\xe2',
+ '\x4f', '\x9e', '\x30', '\x00', '\x01', '\xe1', '\xc9', '\x9b',
+ '\x4f', '\xde', '\x78', '\x00', '\x02', '\xe1', '\xcd', '\xdb',
+ '\x4d', '\x92', '\x0b', '\xe1', '\xc9', '\x9b', '\x4a', '\xd2',
+ '\x0c', '\xe1', '\xcd', '\xdb', '\x0d', '\xe1', '\x70', '\x0a',
+ '\x4b', '\xb6', '\x06', '\x20', '\x7c', '\x86', '\x0b', '\xe1',
+ '\x70', '\x0a', '\x6c', '\x96', '\xc2', '\x93', '\x6a', '\xb6',
+ '\xe9', '\xb7', '\x4b', '\xd6', '\x0f', '\xd3', '\xcf', '\xde',
+ '\x09', '\x00', '\x04', '\x80', '\x49', '\x92', '\x07', '\xd2',
+ '\xac', '\x96', '\x4e', '\xb2', '\x2e', '\xb6', '\x2b', '\x96',
+ '\x30', '\xd2', '\xf3', '\x91', '\xcd', '\xdb', '\x01', '\xc2',
+ '\xc8', '\xc2', '\xd9', '\x20', '\x6c', '\x96', '\x6e', '\xa6',
+ '\x01', '\xa2', '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38',
+ '\x0e', '\xe2', '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe',
+ '\x84', '\xe2', '\xfe', '\x0b', '\x6f', '\x0e', '\xd2', '\x02',
+ '\x00', '\x38', '\x6f', '\xae', '\xe0', '\x15', '\x00', '\x38',
+ '\xb0', '\xb9', '\x6f', '\xae', '\x32', '\x1a', '\x00', '\x38',
+ '\x6a', '\xaa', '\x7a', '\x67', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x02', '\x03', '\x00', '\x38', '\x6f', '\xae', '\xac', '\x19',
+ '\x00', '\x38', '\xb0', '\xb9', '\x6f', '\x9e', '\xf0', '\x00',
+ '\x00', '\x38', '\xef', '\x9e', '\xf2', '\x19', '\x00', '\x38',
+ '\x0e', '\x30', '\x70', '\x86', '\x09', '\x0c', '\xef', '\x9e',
+ '\xf2', '\x19', '\x00', '\x38', '\xf7', '\x20', '\x0f', '\x05',
+ '\x6f', '\xae', '\xf2', '\x15', '\x00', '\x38', '\x3f', '\xbd',
+ '\xd2', '\x02', '\x00', '\x38', '\x60', '\xa6', '\x41', '\xb2',
+ '\x3f', '\xbd', '\x02', '\x03', '\x00', '\x38', '\x3f', '\xbd',
+ '\xe2', '\x03', '\x00', '\x38', '\x3f', '\x0d', '\x28', '\x01',
+ '\x00', '\x38', '\xbe', '\x0f', '\x3e', '\x0d', '\xff', '\xe0',
+ '\x0f', '\x05', '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2',
+ '\xfe', '\x0b', '\x6f', '\x0e', '\xd2', '\x02', '\x00', '\x38',
+ '\x6f', '\xae', '\x0e', '\x16', '\x00', '\x38', '\xb0', '\xb9',
+ '\x3f', '\xbd', '\xac', '\x02', '\x00', '\x38', '\x6f', '\xae',
+ '\x00', '\x1f', '\x00', '\x38', '\x5f', '\xbc', '\xec', '\x01',
+ '\x3f', '\xbd', '\x60', '\x07', '\x00', '\x38', '\x6f', '\xae',
+ '\x28', '\x16', '\x00', '\x38', '\xb0', '\xb9', '\x3f', '\xbd',
+ '\x26', '\x04', '\x00', '\x38', '\xbe', '\x0f', '\x3e', '\xbe',
+ '\x3f', '\x0d', '\xde', '\x03', '\x00', '\x38', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x98', '\xe2', '\xfe', '\x4b', '\x6f', '\xde',
+ '\x00', '\x1f', '\x00', '\x38', '\x6d', '\x9a', '\x79', '\x67',
+ '\xed', '\x9f', '\xef', '\xde', '\xec', '\x20', '\x00', '\x38',
+ '\xf3', '\x20', '\x0f', '\x05', '\x6f', '\x3e', '\x00', '\x1f',
+ '\x00', '\x38', '\xa3', '\x0b', '\xff', '\x3d', '\xfe', '\x02',
+ '\x0f', '\x05', '\x63', '\x9a', '\x81', '\x92', '\xcf', '\x9d',
+ '\x0b', '\x00', '\x5f', '\x95', '\x3f', '\xf8', '\x54', '\x02',
+ '\x22', '\x01', '\x18', '\x00', '\x62', '\x00', '\x90', '\x00',
+ '\x96', '\x01', '\xc8', '\x01', '\xe4', '\x00', '\x00', '\x02',
+ '\xb8', '\x00', '\x9a', '\x02', '\xce', '\x02', '\x6f', '\xae',
+ '\x3a', '\x16', '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02',
+ '\x00', '\x38', '\x6f', '\x0e', '\x02', '\x03', '\x00', '\x38',
+ '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x6f', '\x0e', '\x86', '\x1a', '\x00', '\x38', '\x60', '\x9a',
+ '\x81', '\x92', '\xe0', '\x9b', '\x3f', '\xbd', '\xac', '\x02',
+ '\x00', '\x38', '\x60', '\x9a', '\x01', '\x92', '\xe0', '\x9b',
+ '\x62', '\xaa', '\x61', '\xba', '\x3f', '\xbd', '\x60', '\x07',
+ '\x00', '\x38', '\xff', '\xed', '\x88', '\x02', '\x0c', '\x32',
+ '\x6f', '\xae', '\x48', '\x16', '\x00', '\x38', '\x3f', '\xbd',
+ '\xd2', '\x02', '\x00', '\x38', '\x6f', '\x0e', '\x02', '\x03',
+ '\x00', '\x38', '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x61', '\x1a', '\x72', '\x09', '\xe1', '\x1b',
+ '\xff', '\xed', '\x5a', '\x02', '\x0c', '\x32', '\x6f', '\xae',
+ '\x58', '\x16', '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02',
+ '\x00', '\x38', '\x6f', '\x1e', '\x02', '\x03', '\x00', '\x38',
+ '\x04', '\x31', '\x60', '\xae', '\x41', '\xb2', '\xb1', '\xb9',
+ '\x60', '\xaa', '\x6a', '\xaa', '\x41', '\xb2', '\xb1', '\xb9',
+ '\xff', '\xed', '\x32', '\x02', '\x08', '\x32', '\x6f', '\xae',
+ '\x68', '\x16', '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02',
+ '\x00', '\x38', '\x04', '\x31', '\x60', '\xae', '\x41', '\xb2',
+ '\x3f', '\xbd', '\x02', '\x03', '\x00', '\x38', '\x60', '\xaa',
+ '\xff', '\x3d', '\xc0', '\x01', '\x0f', '\x05', '\x81', '\xa2',
+ '\xfd', '\x20', '\x0f', '\x05', '\xff', '\xed', '\x06', '\x02',
+ '\x08', '\x32', '\x6f', '\x4e', '\xd2', '\x02', '\x00', '\x38',
+ '\x6f', '\xae', '\x76', '\x16', '\x00', '\x38', '\xb4', '\xb9',
+ '\x6f', '\x0e', '\x02', '\x03', '\x00', '\x38', '\x04', '\x31',
+ '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31',
+ '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x62', '\x2a',
+ '\x62', '\x2a', '\xe1', '\x2a', '\xff', '\x3d', '\xb8', '\x01',
+ '\x0f', '\x05', '\x6f', '\xae', '\x84', '\x16', '\x00', '\x38',
+ '\xb4', '\xb9', '\xff', '\xed', '\xd0', '\x01', '\x0f', '\x05',
+ '\x6f', '\x4e', '\xd2', '\x02', '\x00', '\x38', '\x6f', '\xae',
+ '\x94', '\x16', '\x00', '\x38', '\xb4', '\xb9', '\x6f', '\x2e',
+ '\x02', '\x03', '\x00', '\x38', '\x04', '\x31', '\x61', '\xae',
+ '\x41', '\xb2', '\xb2', '\xb9', '\x08', '\x31', '\x60', '\xae',
+ '\x41', '\xb2', '\xb2', '\xb9', '\x61', '\xaa', '\x60', '\xba',
+ '\x6e', '\xc6', '\x14', '\xc2', '\x3f', '\xbd', '\x5e', '\x08',
+ '\x00', '\x38', '\x6a', '\xa6', '\x30', '\x20', '\x0f', '\x05',
+ '\x6f', '\xae', '\xa0', '\x16', '\x00', '\x38', '\xb4', '\xb9',
+ '\x14', '\xe1', '\x6a', '\xaa', '\x41', '\xb2', '\xb2', '\xb9',
+ '\x14', '\xe1', '\x6a', '\xaa', '\x6a', '\xb6', '\x0f', '\xbc',
+ '\x40', '\x00', '\x8f', '\xac', '\x40', '\x00', '\x3c', '\xa3',
+ '\x3c', '\xb3', '\x3f', '\xbd', '\x06', '\x09', '\x00', '\x38',
+ '\xff', '\xed', '\x6a', '\x01', '\x0f', '\x05', '\x6f', '\xae',
+ '\xbc', '\x16', '\x00', '\x38', '\xb4', '\xb9', '\xff', '\xed',
+ '\x54', '\x01', '\x0c', '\x32', '\x6f', '\xae', '\xd2', '\x16',
+ '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38',
+ '\x6f', '\x0e', '\x02', '\x03', '\x00', '\x38', '\x04', '\x31',
+ '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x08', '\x31',
+ '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9', '\x62', '\xaa',
+ '\x61', '\xba', '\x3f', '\xbd', '\x06', '\x09', '\x00', '\x38',
+ '\xff', '\xed', '\x22', '\x01', '\x0c', '\x32', '\x6f', '\xae',
+ '\xde', '\x16', '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02',
+ '\x00', '\x38', '\x6f', '\x0e', '\x02', '\x03', '\x00', '\x38',
+ '\x04', '\x31', '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x08', '\x31', '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x62', '\xaa', '\xe1', '\xaa', '\xda', '\x90', '\x0f', '\x05',
+ '\x7a', '\x0e', '\x08', '\x31', '\xea', '\xaa', '\xf9', '\x80',
+ '\x0f', '\x05', '\xea', '\xe0', '\x0c', '\x32', '\x6f', '\xae',
+ '\xea', '\x16', '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02',
+ '\x00', '\x38', '\x6f', '\x0e', '\x02', '\x03', '\x00', '\x38',
+ '\x04', '\x31', '\x61', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x08', '\x31', '\x64', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x0c', '\x31', '\x62', '\xae', '\x41', '\xb2', '\xb0', '\xb9',
+ '\x6f', '\x0e', '\xa6', '\x12', '\x00', '\x38', '\x61', '\xaa',
+ '\x64', '\xba', '\x62', '\xca', '\xb0', '\xb9', '\x6a', '\xa6',
+ '\xac', '\x30', '\x10', '\x32', '\xc3', '\xa2', '\xae', '\x20',
+ '\x7a', '\x86', '\x62', '\xca', '\xef', '\xcd', '\x00', '\x00',
+ '\x01', '\x00', '\x64', '\xba', '\xb0', '\xb9', '\x9e', '\xe0',
+ '\x0f', '\x05', '\x6f', '\xde', '\x10', '\x1a', '\x00', '\x38',
+ '\x6d', '\x9a', '\x7f', '\x0d', '\xc0', '\x01', '\x00', '\xb0',
+ '\xe9', '\x9b', '\x04', '\xd1', '\x59', '\x98', '\x7f', '\x0d',
+ '\xc4', '\x01', '\x00', '\xb0', '\xe9', '\x9b', '\x6f', '\x1e',
+ '\xd2', '\x02', '\x00', '\x38', '\x6f', '\xae', '\xf2', '\x16',
+ '\x00', '\x38', '\xb1', '\xb9', '\x04', '\x31', '\x60', '\xae',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x02', '\x03', '\x00', '\x38',
+ '\x6f', '\xae', '\xfa', '\x16', '\x00', '\x38', '\xb1', '\xb9',
+ '\x60', '\x9a', '\xb9', '\x09', '\x50', '\xe0', '\x08', '\x32',
+ '\x6f', '\xae', '\x6e', '\x16', '\x00', '\x38', '\x3f', '\xbd',
+ '\xd2', '\x02', '\x00', '\x38', '\x6f', '\x0e', '\x02', '\x03',
+ '\x00', '\x38', '\x04', '\x31', '\x61', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x08', '\x31', '\x62', '\xae', '\x41', '\xb2',
+ '\xb0', '\xb9', '\x61', '\x1a', '\x61', '\x9a', '\x08', '\x30',
+ '\x81', '\x92', '\xe1', '\x9b', '\x20', '\xe0', '\x62', '\x3a',
+ '\x1c', '\xe0', '\x0c', '\x32', '\x6f', '\xae', '\x00', '\x17',
+ '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38',
+ '\x63', '\xaa', '\x41', '\xb2', '\x3f', '\xbd', '\x02', '\x03',
+ '\x00', '\x38', '\x0a', '\xe0', '\x0f', '\x05', '\xa3', '\x0b',
+ '\xff', '\x2d', '\x06', '\xfd', '\x0f', '\x05', '\x6f', '\xae',
+ '\xfa', '\x16', '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02',
+ '\x00', '\x38', '\xbe', '\x4f', '\x04', '\xe2', '\x3e', '\x0d',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x8c', '\xe2', '\xfe', '\x2b',
+ '\x6a', '\x26', '\x6b', '\x06', '\x7f', '\x0d', '\x7e', '\x1a',
+ '\x00', '\x38', '\x70', '\x8a', '\x7f', '\x0d', '\x04', '\x01',
+ '\x00', '\x38', '\xea', '\xab', '\x6f', '\x9e', '\x82', '\x1a',
+ '\x00', '\x38', '\x49', '\x9a', '\xcf', '\x9e', '\x01', '\x00',
+ '\x86', '\x20', '\x0f', '\x05', '\x6f', '\xde', '\x36', '\x1a',
+ '\x00', '\x38', '\x08', '\xd1', '\xea', '\xab', '\x7f', '\x0d',
+ '\x00', '\x01', '\x00', '\x38', '\xeb', '\xbb', '\x6b', '\x96',
+ '\x04', '\x92', '\xdf', '\x9d', '\xdc', '\x05', '\xdd', '\x9b',
+ '\x6f', '\x9e', '\xa4', '\x01', '\x00', '\xb0', '\x69', '\xda',
+ '\x6f', '\xde', '\x00', '\x1a', '\x00', '\x38', '\xe9', '\xdb',
+ '\x6f', '\xde', '\xd4', '\x01', '\x00', '\xb0', '\x4d', '\x9a',
+ '\x38', '\x93', '\x44', '\x93', '\xcd', '\x9b', '\x6f', '\xde',
+ '\xd4', '\x01', '\x00', '\xb0', '\x4d', '\x9a', '\x07', '\x93',
+ '\xcf', '\x9e', '\x04', '\x00', '\xf7', '\x30', '\x0f', '\x05',
+ '\x4d', '\x9a', '\x38', '\x93', '\x41', '\x93', '\xcd', '\x9b',
+ '\x3f', '\xbd', '\xcc', '\x01', '\x00', '\x38', '\x6a', '\xa6',
+ '\xf7', '\x30', '\x0f', '\x05', '\x6f', '\xce', '\x7e', '\x1a',
+ '\x00', '\x38', '\xec', '\x0a', '\x10', '\x80', '\x0f', '\x05',
+ '\x6f', '\xde', '\xd4', '\x01', '\x00', '\xb0', '\x4d', '\x9a',
+ '\x38', '\x93', '\x41', '\x93', '\xcd', '\x9b', '\xec', '\x0a',
+ '\xd7', '\x90', '\x71', '\x86', '\x22', '\xe0', '\x62', '\x96',
+ '\x7f', '\x0d', '\x7e', '\x1a', '\x00', '\x38', '\xeb', '\xba',
+ '\x14', '\x80', '\x71', '\x86', '\x3f', '\xbd', '\xcc', '\x01',
+ '\x00', '\x38', '\x7f', '\x0d', '\x7e', '\x1a', '\x00', '\x38',
+ '\xe0', '\x0a', '\xf1', '\x90', '\x71', '\x86', '\x62', '\x96',
+ '\x20', '\x96', '\xe9', '\x26', '\x0e', '\x30', '\x62', '\xd6',
+ '\x0d', '\x1c', '\x62', '\x96', '\x20', '\x96', '\xe9', '\xd6',
+ '\xf7', '\x20', '\x0f', '\x05', '\x6f', '\xae', '\x14', '\x17',
+ '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38',
+ '\x61', '\xa6', '\x41', '\xb2', '\xbe', '\x2f', '\x3e', '\xbe',
+ '\x3f', '\x0d', '\x02', '\x03', '\x00', '\x38', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x8c', '\xe2', '\xfe', '\x2b', '\x6b', '\x06',
+ '\x6c', '\x26', '\xeb', '\xa6', '\x40', '\x00', '\x6a', '\xc6',
+ '\xe0', '\xc6', '\x32', '\x00', '\x71', '\x86', '\x6c', '\xb6',
+ '\x6c', '\x96', '\x79', '\x87', '\x61', '\xd6', '\xc3', '\xd3',
+ '\xed', '\x97', '\x49', '\xd6', '\xcb', '\x9b', '\x4b', '\x9a',
+ '\xcd', '\x96', '\x0c', '\x30', '\x7d', '\x87', '\x6f', '\xae',
+ '\x2a', '\x17', '\x00', '\x38', '\x40', '\xe0', '\xe2', '\xbb',
+ '\xcb', '\xdf', '\x01', '\x12', '\xc4', '\x12', '\x06', '\x30',
+ '\xe0', '\xb6', '\xd7', '\x10', '\x6c', '\x96', '\x04', '\xc2',
+ '\xe0', '\xc6', '\xc5', '\x10', '\x0f', '\x05', '\xe0', '\xa6',
+ '\x4e', '\x00', '\x6a', '\xc6', '\xe0', '\xc6', '\x40', '\x00',
+ '\x71', '\x86', '\x6c', '\xa6', '\x61', '\x96', '\xc3', '\x93',
+ '\x6c', '\xd6', '\xe9', '\xd7', '\x4a', '\x9a', '\xcd', '\x96',
+ '\x22', '\x30', '\x01', '\x12', '\x81', '\x12', '\xe2', '\xab',
+ '\x6f', '\xae', '\x48', '\x17', '\x00', '\x38', '\x3f', '\xbd',
+ '\xd2', '\x02', '\x00', '\x38', '\x62', '\xaa', '\x41', '\xb2',
+ '\x3f', '\xbd', '\x02', '\x03', '\x00', '\x38', '\x7a', '\x86',
+ '\xbe', '\x2f', '\x3e', '\x0d', '\xc4', '\x12', '\x08', '\x30',
+ '\x01', '\xa2', '\xe0', '\xa6', '\xc9', '\x10', '\x61', '\x96',
+ '\x04', '\xc2', '\xe0', '\xc6', '\xb7', '\x10', '\x0f', '\x05',
+ '\x41', '\xa2', '\xbe', '\x2f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x94', '\xe2', '\xfe', '\x4b', '\x6b', '\x26',
+ '\xeb', '\xa6', '\x5a', '\x90', '\x6a', '\x06', '\x60', '\xa6',
+ '\x7b', '\x86', '\x3f', '\xbd', '\x02', '\x03', '\x00', '\x38',
+ '\x6f', '\xae', '\x66', '\x17', '\x00', '\x38', '\x3f', '\xbd',
+ '\xd2', '\x02', '\x00', '\x38', '\xe2', '\x06', '\x2a', '\x90',
+ '\x74', '\x86', '\x60', '\x16', '\x60', '\x36', '\x6f', '\xae',
+ '\xbc', '\x17', '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02',
+ '\x00', '\x38', '\x63', '\xae', '\x7b', '\x86', '\x3f', '\xbd',
+ '\x02', '\x03', '\x00', '\x38', '\x01', '\x42', '\xc4', '\x42',
+ '\x08', '\x30', '\x04', '\x12', '\xe2', '\x16', '\xdf', '\x80',
+ '\x0f', '\x05', '\x6f', '\xae', '\x24', '\x16', '\x00', '\x38',
+ '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38', '\x10', '\x02',
+ '\xe2', '\x06', '\xad', '\x80', '\x60', '\xa6', '\xbe', '\x4f',
+ '\x3e', '\x0d', '\x00', '\x00', '\x05', '\xa1', '\x49', '\x98',
+ '\xc2', '\x92', '\x0a', '\x30', '\xc4', '\x92', '\x0e', '\x30',
+ '\x0f', '\x05', '\x7f', '\xb6', '\x7a', '\x86', '\x6a', '\xb9',
+ '\x5a', '\xa8', '\x7f', '\xb6', '\x0f', '\x05', '\x6a', '\xb9',
+ '\x6a', '\xaa', '\x7f', '\xb6', '\x0f', '\x05', '\x6a', '\xd6',
+ '\x05', '\xa1', '\x4a', '\xaa', '\x4a', '\x94', '\xc2', '\x92',
+ '\x0a', '\x30', '\xc4', '\x92', '\x10', '\x30', '\x0f', '\x05',
+ '\x7f', '\xb6', '\x7a', '\x86', '\x5c', '\xca', '\x6d', '\xb9',
+ '\xdc', '\xcb', '\x7f', '\xb6', '\x4a', '\xa4', '\x6c', '\xca',
+ '\x6d', '\xb9', '\xec', '\xcb', '\x4a', '\xa4', '\x7f', '\xb6',
+ '\x0f', '\x05', '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2',
+ '\xee', '\xbb', '\x04', '\xa1', '\x49', '\x9a', '\xcf', '\x9e',
+ '\x01', '\x00', '\x06', '\x20', '\x0f', '\x05', '\x24', '\xe0',
+ '\xc1', '\xc3', '\xcf', '\x9e', '\x02', '\x00', '\x0c', '\x20',
+ '\x6b', '\x96', '\xd0', '\x93', '\x69', '\xb7', '\xee', '\xbb',
+ '\x12', '\xe0', '\xc2', '\xc3', '\x6f', '\xae', '\x92', '\x17',
+ '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38',
+ '\x0c', '\xe0', '\x0f', '\x05', '\x6c', '\xb6', '\x6e', '\xc6',
+ '\x3f', '\xbd', '\x96', '\x09', '\x00', '\x38', '\x04', '\xe2',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x84', '\xe2',
+ '\xfe', '\x0b', '\x6a', '\x06', '\x4f', '\xbc', '\xaa', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd', '\xc2', '\x09',
+ '\x00', '\x38', '\x60', '\xa6', '\x4f', '\xbc', '\x55', '\x00',
+ '\x5f', '\xcc', '\xaa', '\x02', '\xbe', '\x0f', '\x3e', '\xbe',
+ '\x3f', '\x0d', '\xc2', '\x09', '\x00', '\x38', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x90', '\xe2', '\xfe', '\x3b', '\x6a', '\x26',
+ '\x04', '\xa1', '\x49', '\x9a', '\xcf', '\x9e', '\x02', '\x00',
+ '\x42', '\x20', '\x6b', '\x36', '\x6f', '\x0e', '\x74', '\x09',
+ '\x00', '\x38', '\xb0', '\xb9', '\x6a', '\x16', '\x62', '\xa6',
+ '\x63', '\xb6', '\xb0', '\xb9', '\x61', '\xd6', '\xf0', '\xd3',
+ '\x1f', '\xdf', '\x40', '\x00', '\x6a', '\x96', '\xf0', '\x93',
+ '\x1f', '\x9f', '\x40', '\x00', '\xe9', '\xd6', '\x14', '\x20',
+ '\x7c', '\x86', '\x2f', '\x1f', '\x40', '\x00', '\x00', '\x00',
+ '\x2f', '\xaf', '\x40', '\x00', '\x00', '\x00', '\xea', '\x16',
+ '\x04', '\x30', '\x0f', '\x05', '\x41', '\xc2', '\x6c', '\xa6',
+ '\xbe', '\x3f', '\x3e', '\x0d', '\x6f', '\x1e', '\x74', '\x09',
+ '\x00', '\x38', '\xb1', '\xb9', '\x4a', '\x04', '\x0f', '\x0f',
+ '\x40', '\x00', '\x62', '\xa6', '\x63', '\xb6', '\xb1', '\xb9',
+ '\x2f', '\xaf', '\x40', '\x00', '\x00', '\x00', '\xea', '\x06',
+ '\x3a', '\x25', '\xbe', '\x3f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\xa8', '\xe2', '\xfe', '\x8b', '\x6a', '\x36',
+ '\x04', '\xa1', '\x44', '\x9e', '\xcf', '\x9e', '\x02', '\x00',
+ '\x04', '\x20', '\x41', '\x72', '\x42', '\x72', '\x6f', '\x2e',
+ '\xc2', '\x09', '\x00', '\x38', '\x4f', '\xbc', '\x98', '\x00',
+ '\x4f', '\xcc', '\x55', '\x00', '\xb2', '\xb9', '\x50', '\xb2',
+ '\xe7', '\xb4', '\x6f', '\x1e', '\x74', '\x09', '\x00', '\x38',
+ '\x63', '\xa6', '\xb1', '\xb9', '\xcf', '\xae', '\x51', '\x00',
+ '\xff', '\x2d', '\x9c', '\x01', '\x63', '\xa6', '\x51', '\xb2',
+ '\xe7', '\xb4', '\xb1', '\xb9', '\xcf', '\xae', '\x52', '\x00',
+ '\xff', '\x2d', '\x8c', '\x01', '\x63', '\xa6', '\x52', '\xb2',
+ '\xe7', '\xb4', '\xb1', '\xb9', '\xcf', '\xae', '\x59', '\x00',
+ '\xff', '\x2d', '\x7c', '\x01', '\x63', '\xa6', '\x24', '\xe1',
+ '\x70', '\x8a', '\x6f', '\xae', '\xac', '\x17', '\x00', '\x38',
+ '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38', '\x63', '\xaa',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x02', '\x03', '\x00', '\x38',
+ '\x4f', '\xbc', '\x27', '\x00', '\xe7', '\xb4', '\x63', '\xa6',
+ '\xb1', '\xb9', '\x41', '\x92', '\xea', '\x94', '\x06', '\x32',
+ '\xe3', '\x9b', '\x86', '\x32', '\x4f', '\xbc', '\x2c', '\x00',
+ '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9', '\x6a', '\x86',
+ '\x55', '\xb2', '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9',
+ '\x6a', '\x06', '\x6a', '\xb6', '\x04', '\xb2', '\xe7', '\xb4',
+ '\x63', '\xa6', '\xb1', '\xb9', '\xcf', '\xae', '\x30', '\x00',
+ '\x3e', '\x20', '\x63', '\xa6', '\x4f', '\xbc', '\xf0', '\x00',
+ '\x5f', '\xcc', '\x55', '\x05', '\xb2', '\xb9', '\x63', '\xa6',
+ '\x3f', '\xbd', '\x0a', '\x0a', '\x00', '\x38', '\x63', '\xa6',
+ '\x4f', '\xbc', '\x90', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\xb2', '\xb9', '\x44', '\xb8', '\x2b', '\xb6', '\x63', '\xa6',
+ '\xb1', '\xb9', '\x4a', '\x54', '\x0f', '\x5f', '\x80', '\xff',
+ '\x63', '\xa6', '\x4f', '\xbc', '\x98', '\x00', '\x4f', '\xcc',
+ '\x55', '\x00', '\xb2', '\xb9', '\x10', '\xe0', '\x0f', '\x05',
+ '\x0f', '\x02', '\xe7', '\x04', '\x60', '\xb6', '\xb1', '\xb9',
+ '\xcf', '\xae', '\x03', '\x00', '\x35', '\x35', '\x0a', '\x31',
+ '\xd8', '\x8b', '\xc8', '\x82', '\x12', '\xd0', '\x68', '\x46',
+ '\x6f', '\xae', '\xbe', '\x17', '\x00', '\x38', '\x3f', '\xbd',
+ '\xd2', '\x02', '\x00', '\x38', '\xd2', '\xe0', '\x7a', '\x86',
+ '\x65', '\x56', '\x94', '\x20', '\x81', '\x42', '\x90', '\xe0',
+ '\x74', '\x86', '\xc2', '\x03', '\x60', '\xb6', '\x2f', '\xb2',
+ '\xe7', '\xb4', '\x6f', '\x1e', '\x74', '\x09', '\x00', '\x38',
+ '\x63', '\xa6', '\xb1', '\xb9', '\x6a', '\x66', '\x60', '\xb6',
+ '\x30', '\xb2', '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9',
+ '\xc8', '\xa3', '\x6a', '\x67', '\xc8', '\x63', '\x60', '\xb6',
+ '\x2d', '\xb2', '\xe7', '\xb4', '\x63', '\xa6', '\xb1', '\xb9',
+ '\x6a', '\x26', '\x2e', '\x02', '\xe7', '\x04', '\x63', '\xa6',
+ '\x60', '\xb6', '\xb1', '\xb9', '\xc8', '\xa3', '\x6a', '\x27',
+ '\x65', '\x56', '\x0a', '\x30', '\x01', '\x22', '\x68', '\x96',
+ '\xa4', '\x96', '\x04', '\xe0', '\x81', '\x92', '\x64', '\x96',
+ '\x19', '\x95', '\x63', '\xd6', '\x2d', '\x95', '\x6d', '\x96',
+ '\x24', '\xe1', '\x6d', '\xda', '\x0c', '\x91', '\xed', '\xdb',
+ '\x10', '\x91', '\xe6', '\x6b', '\x14', '\x91', '\xe2', '\x2b',
+ '\x62', '\x26', '\x10', '\xd0', '\x0f', '\x05', '\x24', '\xe1',
+ '\x29', '\x6a', '\x24', '\xe1', '\xe9', '\x9b', '\x81', '\x22',
+ '\xf5', '\x20', '\x0f', '\x05', '\x24', '\xe1', '\x6d', '\xda',
+ '\x06', '\x31', '\xed', '\xda', '\x1e', '\x30', '\x65', '\x56',
+ '\x06', '\x30', '\x01', '\x42', '\x81', '\x42', '\x81', '\x42',
+ '\x65', '\x56', '\x0c', '\x30', '\xe8', '\x46', '\x64', '\x46',
+ '\x69', '\xa0', '\x64', '\x06', '\x08', '\xe0', '\x63', '\xa6',
+ '\x61', '\xb0', '\x64', '\x06', '\x63', '\xa6', '\x4f', '\xbc',
+ '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05', '\x3f', '\xbd',
+ '\xc2', '\x09', '\x00', '\x38', '\x12', '\xe0', '\x41', '\xa2',
+ '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\xc2', '\x09', '\x00', '\x38', '\x7a', '\x86',
+ '\xbe', '\x8f', '\x04', '\xe2', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\x90', '\xe2', '\xfe', '\x3b', '\x06', '\xa1',
+ '\xa0', '\x0b', '\xff', '\x2d', '\x16', '\x04', '\x6a', '\x26',
+ '\x3f', '\xbd', '\xae', '\x0a', '\x00', '\x38', '\x6a', '\xa6',
+ '\xff', '\x2d', '\x86', '\x03', '\x41', '\xa2', '\x62', '\xa6',
+ '\x3f', '\xbd', '\x0a', '\x0a', '\x00', '\x38', '\x62', '\xa6',
+ '\x4f', '\xbc', '\x90', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\xc2', '\x09', '\x00', '\x38', '\x6f', '\x1e',
+ '\x74', '\x09', '\x00', '\x38', '\x62', '\xa6', '\x7b', '\x86',
+ '\xb1', '\xb9', '\x6a', '\x36', '\x04', '\x21', '\x40', '\xbe',
+ '\x4b', '\xb4', '\x2b', '\xb6', '\x62', '\xa6', '\xb1', '\xb9',
+ '\x42', '\x92', '\xc0', '\x9a', '\x1c', '\x20', '\x63', '\xc6',
+ '\xf0', '\xc3', '\x53', '\x94', '\xe9', '\xc6', '\x14', '\x20',
+ '\x63', '\x06', '\x6a', '\xd6', '\xf0', '\xd3', '\x5a', '\x94',
+ '\xe9', '\xd6', '\x0a', '\x20', '\xd0', '\x03', '\x6c', '\x36',
+ '\x6d', '\xa6', '\x63', '\x06', '\xd0', '\x03', '\x6a', '\x07',
+ '\x62', '\xa6', '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc',
+ '\x55', '\x05', '\x3f', '\xbd', '\xc2', '\x09', '\x00', '\x38',
+ '\xef', '\x0e', '\xc0', '\x00', '\x1f', '\x00', '\xff', '\x3d',
+ '\x48', '\x02', '\x0f', '\x05', '\x60', '\x90', '\x0f', '\x05',
+ '\xef', '\x0e', '\xc4', '\x22', '\x01', '\x00', '\xb0', '\x30',
+ '\x0f', '\x05', '\x20', '\x90', '\x0f', '\x05', '\xef', '\x0e',
+ '\x58', '\x22', '\x01', '\x00', '\xff', '\x3d', '\x5a', '\x01',
+ '\x0f', '\x05', '\xef', '\x0e', '\x5b', '\x22', '\x01', '\x00',
+ '\xff', '\x3d', '\x4e', '\x01', '\x0f', '\x05', '\xff', '\xed',
+ '\xb6', '\x02', '\x0f', '\x05', '\xef', '\x0e', '\xda', '\x22',
+ '\x01', '\x00', '\xff', '\x3d', '\x9c', '\x01', '\x0f', '\x05',
+ '\x14', '\x90', '\x0f', '\x05', '\xef', '\x0e', '\xd6', '\x22',
+ '\x01', '\x00', '\xff', '\x3d', '\x8c', '\x01', '\x0f', '\x05',
+ '\xff', '\xed', '\x94', '\x02', '\x0f', '\x05', '\xef', '\x0e',
+ '\x49', '\x22', '\x04', '\x00', '\xc4', '\x30', '\x0f', '\x05',
+ '\xff', '\xed', '\x84', '\x02', '\x0f', '\x05', '\xef', '\x0e',
+ '\xd7', '\x00', '\x20', '\x00', '\xff', '\x3d', '\x6a', '\x01',
+ '\x0f', '\x05', '\x20', '\x90', '\x0f', '\x05', '\xef', '\x0e',
+ '\xc2', '\x00', '\x1f', '\x00', '\xff', '\x3d', '\x00', '\x02',
+ '\x0f', '\x05', '\xef', '\x0e', '\xc9', '\x00', '\x1f', '\x00',
+ '\xff', '\x3d', '\x18', '\x02', '\x0f', '\x05', '\xff', '\xed',
+ '\x56', '\x02', '\x0f', '\x05', '\xef', '\x0e', '\x4f', '\x00',
+ '\x98', '\x00', '\xff', '\x3d', '\x3c', '\x01', '\x0f', '\x05',
+ '\x12', '\x90', '\x0f', '\x05', '\xef', '\x0e', '\x43', '\x00',
+ '\x98', '\x00', '\x76', '\x30', '\x0f', '\x05', '\xff', '\xed',
+ '\x36', '\x02', '\x0f', '\x05', '\xef', '\x0e', '\xc2', '\x00',
+ '\x98', '\x00', '\xff', '\x2d', '\x2a', '\x02', '\x0f', '\x05',
+ '\x6f', '\x1e', '\xa2', '\x18', '\x00', '\x38', '\x61', '\x1a',
+ '\x6f', '\xde', '\x00', '\x00', '\x20', '\x00', '\x06', '\x21',
+ '\xed', '\xdb', '\x0c', '\x21', '\x70', '\x8a', '\x6f', '\x9e',
+ '\x00', '\x00', '\x01', '\x00', '\x10', '\x21', '\xe9', '\x9b',
+ '\x5f', '\xd2', '\x14', '\x21', '\xed', '\xdb', '\x6f', '\x9e',
+ '\x00', '\x00', '\x1f', '\x00', '\x18', '\x21', '\xe9', '\x9b',
+ '\x1f', '\xdc', '\xe1', '\x7f', '\x1c', '\x21', '\xed', '\xdb',
+ '\x41', '\x92', '\x20', '\x21', '\xe9', '\x9b', '\x6f', '\xde',
+ '\x00', '\x80', '\x1f', '\x00', '\x24', '\x21', '\xed', '\xdb',
+ '\x5f', '\xdc', '\x00', '\x20', '\x28', '\x21', '\xed', '\xdb',
+ '\x42', '\xd2', '\x2c', '\x21', '\xed', '\xdb', '\x6f', '\xde',
+ '\x00', '\xc0', '\x1f', '\x00', '\xff', '\xed', '\x16', '\x01',
+ '\x0f', '\x05', '\x6f', '\x1e', '\x9e', '\x18', '\x00', '\x38',
+ '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00', '\x20', '\x00',
+ '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a',
+ '\x5f', '\x9c', '\x00', '\x40', '\x10', '\x21', '\xe9', '\x9b',
+ '\x41', '\xd2', '\x14', '\x21', '\xed', '\xdb', '\x18', '\x21',
+ '\xe9', '\x9b', '\x5f', '\x9c', '\x00', '\x20', '\x1c', '\x21',
+ '\xe9', '\x9b', '\x42', '\x92', '\x20', '\x21', '\xe9', '\x9b',
+ '\x1f', '\x9c', '\xfe', '\x7f', '\x24', '\x21', '\xe9', '\x9b',
+ '\x28', '\x21', '\xe9', '\x9b', '\x2c', '\x21', '\xed', '\xdb',
+ '\x6f', '\x9e', '\x00', '\x00', '\x01', '\x00', '\x30', '\x21',
+ '\xe9', '\x9b', '\x34', '\x21', '\xe9', '\x9b', '\x58', '\xe0',
+ '\x5f', '\xd2', '\x6f', '\x1e', '\x96', '\x18', '\x00', '\x38',
+ '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00', '\x10', '\x00',
+ '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a',
+ '\x5f', '\x9c', '\x00', '\x40', '\x10', '\x21', '\xe9', '\x9b',
+ '\x41', '\xd2', '\x14', '\x21', '\xed', '\xdb', '\x18', '\x21',
+ '\xe9', '\x9b', '\x5f', '\x9c', '\x00', '\x20', '\x1c', '\x21',
+ '\xe9', '\x9b', '\x42', '\x92', '\x20', '\x21', '\xe9', '\x9b',
+ '\x1f', '\x9c', '\xfe', '\x7f', '\x24', '\x21', '\xe9', '\x9b',
+ '\x28', '\x21', '\xe9', '\x9b', '\x2c', '\x21', '\xed', '\xdb',
+ '\x6f', '\x9e', '\x00', '\x00', '\x01', '\x00', '\x30', '\x21',
+ '\xe9', '\x9b', '\x34', '\x21', '\xe9', '\x9b', '\x4f', '\xd2',
+ '\x38', '\x21', '\xed', '\xdb', '\xff', '\xed', '\x3e', '\x01',
+ '\x0f', '\x05', '\x6f', '\x1e', '\x9a', '\x18', '\x00', '\x38',
+ '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00', '\x10', '\x00',
+ '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a',
+ '\x6f', '\xde', '\x00', '\x00', '\x01', '\x00', '\x10', '\x21',
+ '\xed', '\xdb', '\x4f', '\x92', '\x14', '\x21', '\xe9', '\x9b',
+ '\x6f', '\xde', '\x00', '\x00', '\x0f', '\x00', '\x18', '\x21',
+ '\xed', '\xdb', '\x1f', '\x9c', '\xf1', '\x7f', '\x1c', '\x21',
+ '\xe9', '\x9b', '\x41', '\x92', '\x20', '\x21', '\xe9', '\x9b',
+ '\x6f', '\xde', '\x00', '\x80', '\x0f', '\x00', '\x24', '\x21',
+ '\xed', '\xdb', '\x5f', '\xdc', '\x00', '\x20', '\x28', '\x21',
+ '\xed', '\xdb', '\x42', '\xd2', '\x2c', '\x21', '\xed', '\xdb',
+ '\x6f', '\xde', '\x00', '\xc0', '\x0f', '\x00', '\x30', '\x21',
+ '\xed', '\xdb', '\x5f', '\xdc', '\x00', '\x40', '\x34', '\x21',
+ '\xed', '\xdb', '\x38', '\x21', '\xe9', '\x9b', '\xce', '\xe0',
+ '\x0f', '\x05', '\x6f', '\x1e', '\x9e', '\x18', '\x00', '\x38',
+ '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00', '\x20', '\x00',
+ '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a',
+ '\x5f', '\xdc', '\x00', '\x20', '\x10', '\x21', '\xed', '\xdb',
+ '\x48', '\x92', '\x14', '\x21', '\xe9', '\x9b', '\x6f', '\x9e',
+ '\x00', '\x00', '\x01', '\x00', '\x18', '\x21', '\xe9', '\x9b',
+ '\x1c', '\x21', '\xe9', '\x9b', '\x62', '\xe0', '\x5f', '\xd2',
+ '\x6f', '\x1e', '\xa2', '\x18', '\x00', '\x38', '\x61', '\x1a',
+ '\x6f', '\x9e', '\x00', '\x00', '\x20', '\x00', '\x06', '\x21',
+ '\xe9', '\x9b', '\x0c', '\x21', '\x70', '\x8a', '\x6f', '\xde',
+ '\x00', '\x00', '\x01', '\x00', '\x10', '\x21', '\xed', '\xdb',
+ '\x26', '\xe0', '\x5f', '\x92', '\x6f', '\x1e', '\xa6', '\x18',
+ '\x00', '\x38', '\x61', '\x1a', '\x6f', '\x9e', '\x00', '\x00',
+ '\x40', '\x00', '\x06', '\x21', '\xe9', '\x9b', '\x0c', '\x21',
+ '\x70', '\x8a', '\x6f', '\xde', '\x00', '\x00', '\x01', '\x00',
+ '\x10', '\x21', '\xed', '\xdb', '\x4f', '\x9c', '\x3f', '\x00',
+ '\x14', '\x21', '\xe9', '\x9b', '\x6f', '\xde', '\x00', '\x00',
+ '\x1f', '\x00', '\x18', '\x21', '\xed', '\xdb', '\x5f', '\x9c',
+ '\x00', '\x20', '\x1c', '\x21', '\xe9', '\x9b', '\x48', '\xd2',
+ '\x20', '\x21', '\xed', '\xdb', '\x30', '\xe0', '\x0f', '\x05',
+ '\x04', '\x21', '\x49', '\x9a', '\x6f', '\xae', '\xda', '\x17',
+ '\x00', '\x38', '\xcf', '\x9e', '\x01', '\x00', '\x08', '\x30',
+ '\x0f', '\x05', '\x6f', '\xae', '\xec', '\x17', '\x00', '\x38',
+ '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38', '\x62', '\xaa',
+ '\x41', '\xb2', '\x3f', '\xbd', '\x02', '\x03', '\x00', '\x38',
+ '\x7a', '\x86', '\xbe', '\x3f', '\x3e', '\x0d', '\x6f', '\x3e',
+ '\xd2', '\x02', '\x00', '\x38', '\x6f', '\xae', '\x04', '\x18',
+ '\x00', '\x38', '\xb3', '\xb9', '\x04', '\x21', '\x40', '\x9e',
+ '\xcf', '\x9e', '\x01', '\x00', '\x0c', '\x20', '\x42', '\xd2',
+ '\x6f', '\xae', '\x0c', '\x18', '\x00', '\x38', '\xb3', '\xb9',
+ '\x42', '\xd2', '\xc0', '\xda', '\x32', '\x20', '\x47', '\xc2',
+ '\x06', '\x21', '\x6d', '\x9e', '\xc1', '\x93', '\xed', '\x9b',
+ '\x62', '\xd6', '\x0c', '\xd1', '\x69', '\x9a', '\xc1', '\x93',
+ '\x0c', '\xd1', '\xe9', '\x9b', '\x10', '\xd1', '\x69', '\x9a',
+ '\xc1', '\x93', '\x10', '\xd1', '\xe9', '\x9b', '\x81', '\xc2',
+ '\xe9', '\x60', '\x0c', '\xd2', '\x6f', '\xae', '\x0e', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38',
+ '\x6f', '\x0e', '\xd2', '\x02', '\x00', '\x38', '\x6f', '\xae',
+ '\x10', '\x18', '\x00', '\x38', '\xb0', '\xb9', '\x61', '\xa6',
+ '\xb0', '\xb9', '\x6f', '\xae', '\x42', '\x17', '\x00', '\x38',
+ '\xb0', '\xb9', '\x62', '\xaa', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x02', '\x03', '\x00', '\x38', '\x41', '\xa2', '\xbe', '\x3f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x8c', '\xe2',
+ '\xfe', '\x2b', '\x6a', '\x16', '\x6b', '\x26', '\x6f', '\x0e',
+ '\x0a', '\x0a', '\x00', '\x38', '\xb0', '\xb9', '\x61', '\xa6',
+ '\x4f', '\xbc', '\x80', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\xc2', '\x09', '\x00', '\x38', '\x61', '\xa6',
+ '\xb0', '\xb9', '\x04', '\x11', '\x49', '\x9a', '\xcf', '\x9e',
+ '\x02', '\x00', '\x10', '\x20', '\x0f', '\x05', '\x6f', '\x9e',
+ '\x30', '\x00', '\x30', '\x00', '\x61', '\x29', '\xe9', '\x9b',
+ '\xbe', '\x2f', '\x3e', '\x0d', '\x4f', '\x9c', '\x30', '\x00',
+ '\x61', '\x29', '\xd9', '\x9b', '\xbe', '\x2f', '\x3e', '\x0d',
+ '\x84', '\xe2', '\xfe', '\x0b', '\x06', '\xa1', '\xeb', '\xba',
+ '\x10', '\x10', '\x0f', '\x05', '\x7a', '\x86', '\x7f', '\xb6',
+ '\xbe', '\x0f', '\x10', '\xa1', '\x6a', '\xaa', '\x7f', '\xb6',
+ '\xbe', '\x0f', '\x70', '\x86', '\x0c', '\xa1', '\xeb', '\xba',
+ '\x22', '\x10', '\x7d', '\x86', '\x14', '\xa1', '\xed', '\xda',
+ '\x10', '\x00', '\x79', '\x86', '\x10', '\xa1', '\x6c', '\xca',
+ '\x01', '\x92', '\x14', '\xa1', '\xe9', '\x9a', '\xf9', '\x10',
+ '\x2c', '\xd6', '\x0c', '\xa1', '\x29', '\xda', '\xe9', '\xb6',
+ '\xd1', '\x10', '\x0f', '\x05', '\x01', '\x02', '\xc7', '\x02',
+ '\xd3', '\x80', '\x0c', '\xa2', '\x7a', '\x86', '\x7f', '\xb6',
+ '\xbe', '\x0f', '\x84', '\xe2', '\xfe', '\x0b', '\x6a', '\x06',
+ '\x6b', '\xa6', '\x6d', '\xb6', '\x7d', '\x86', '\xeb', '\xd6',
+ '\x48', '\xa0', '\x0f', '\x05', '\x60', '\x9a', '\x2d', '\x96',
+ '\x49', '\xa5', '\x59', '\x9a', '\x4c', '\xd5', '\xd9', '\x9a',
+ '\x32', '\x30', '\x02', '\xd2', '\x82', '\xd2', '\x6b', '\x96',
+ '\x2a', '\x96', '\xe9', '\xa6', '\x20', '\x00', '\x6a', '\xc6',
+ '\x60', '\xc9', '\x59', '\x9a', '\xdf', '\x9e', '\xff', '\xff',
+ '\x0a', '\x30', '\x02', '\xc2', '\x82', '\xc2', '\x42', '\xa2',
+ '\x7f', '\xb6', '\xbe', '\x0f', '\x6b', '\x96', '\x2a', '\x96',
+ '\xe9', '\xc6', '\xe5', '\x10', '\x0f', '\x05', '\x41', '\xa2',
+ '\x7f', '\xb6', '\xbe', '\x0f', '\xeb', '\xd6', '\xbd', '\xb0',
+ '\x0f', '\x05', '\x7a', '\x86', '\x7f', '\xb6', '\xbe', '\x0f',
+ '\xfc', '\xe1', '\x7e', '\xbe', '\x90', '\xe2', '\xfe', '\x3b',
+ '\x73', '\x86', '\x72', '\x86', '\x6f', '\x0e', '\xaa', '\x18',
+ '\x00', '\x38', '\x41', '\x12', '\x04', '\x01', '\xc1', '\x1b',
+ '\xcf', '\x1e', '\x01', '\x00', '\x04', '\x30', '\x42', '\x92',
+ '\x44', '\x92', '\x05', '\x01', '\xc9', '\x9b', '\x60', '\xa6',
+ '\x3f', '\xbd', '\x9e', '\x0c', '\x00', '\x38', '\x6a', '\xa6',
+ '\x0c', '\x20', '\x0f', '\x05', '\xc1', '\x13', '\xcf', '\x1e',
+ '\x03', '\x00', '\xd9', '\x80', '\x0f', '\x05', '\x06', '\x01',
+ '\x23', '\x3a', '\x0f', '\x0c', '\x6c', '\x00', '\x01', '\x22',
+ '\xc1', '\x22', '\xc7', '\x80', '\x63', '\xa6', '\xbe', '\x3f',
+ '\x3e', '\x0d', '\xfc', '\xe1', '\x7e', '\xbe', '\x98', '\xe2',
+ '\xfe', '\x5b', '\x6a', '\x16', '\x6b', '\x56', '\x6c', '\x36',
+ '\x70', '\x86', '\xed', '\x06', '\x74', '\xa0', '\x6d', '\x46',
+ '\x05', '\x11', '\x49', '\x9a', '\xcf', '\x9e', '\x02', '\x00',
+ '\x12', '\x20', '\x0f', '\x05', '\x43', '\x05', '\x59', '\x9a',
+ '\xdf', '\x9e', '\xff', '\xff', '\x54', '\x30', '\x42', '\x22',
+ '\x05', '\x11', '\x49', '\x9a', '\xcf', '\x9e', '\x04', '\x00',
+ '\x0e', '\x20', '\x61', '\xa6', '\x43', '\x05', '\x69', '\x9a',
+ '\xff', '\x92', '\x3e', '\x30', '\x44', '\x22', '\x61', '\xa6',
+ '\x3f', '\xbd', '\x0a', '\x0a', '\x00', '\x38', '\x61', '\xa6',
+ '\x4f', '\xbc', '\xa0', '\x00', '\x5f', '\xcc', '\x55', '\x05',
+ '\x3f', '\xbd', '\xc2', '\x09', '\x00', '\x38', '\x65', '\xb6',
+ '\x20', '\xb6', '\x63', '\xc6', '\x20', '\xc6', '\x61', '\xa6',
+ '\x3f', '\xbd', '\x96', '\x09', '\x00', '\x38', '\x6a', '\x26',
+ '\x61', '\xa6', '\x65', '\xb6', '\x20', '\xb6', '\x3f', '\xbd',
+ '\x36', '\x0a', '\x00', '\x38', '\x6a', '\xa6', '\xf3', '\x20',
+ '\x61', '\xa6', '\x22', '\x06', '\xe4', '\x06', '\x91', '\xb0',
+ '\x0f', '\x05', '\xbe', '\x5f', '\x3e', '\x0d', '\xfc', '\xe1',
+ '\x7e', '\xbe', '\xa4', '\xe2', '\xfe', '\x8b', '\x6a', '\x16',
+ '\x6b', '\x06', '\x6c', '\x86', '\x3f', '\xbd', '\xc8', '\x11',
+ '\x00', '\x38', '\x6a', '\x96', '\x1a', '\x30', '\x41', '\xa2',
+ '\x60', '\xd6', '\x28', '\xd6', '\xe9', '\xd6', '\x14', '\x80',
+ '\x0f', '\x05', '\x6f', '\xae', '\x14', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38', '\x42', '\xa2',
+ '\xbe', '\x8f', '\x3e', '\x0d', '\x6f', '\xce', '\xb0', '\x18',
+ '\x00', '\x38', '\x6c', '\xca', '\xec', '\x06', '\x1e', '\x10',
+ '\xec', '\xd6', '\x6f', '\x9e', '\x82', '\x19', '\x00', '\x38',
+ '\x09', '\x91', '\x70', '\x8a', '\x16', '\x91', '\xe1', '\x1b',
+ '\xac', '\x06', '\x1a', '\x91', '\xe0', '\x0b', '\x1e', '\x91',
+ '\xe8', '\x8b', '\x74', '\xe0', '\x0f', '\x05', '\x5a', '\x80',
+ '\x6c', '\x96', '\x6f', '\xde', '\x82', '\x19', '\x00', '\x38',
+ '\x01', '\xd1', '\xe1', '\x1b', '\x05', '\xd1', '\xe0', '\x0b',
+ '\xa0', '\x96', '\x09', '\xd1', '\xe9', '\x9b', '\x29', '\x16',
+ '\x16', '\xd1', '\xe1', '\x1b', '\x1a', '\xd1', '\x70', '\x8a',
+ '\x68', '\xc6', '\xa9', '\xc6', '\x1e', '\xd1', '\xec', '\xcb',
+ '\x46', '\xe0', '\x0f', '\x05', '\x6f', '\xae', '\x30', '\x18',
+ '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38',
+ '\x44', '\xa2', '\xbe', '\x8f', '\x3e', '\x0d', '\x6f', '\xae',
+ '\x44', '\x18', '\x00', '\x38', '\x3f', '\xbd', '\xd2', '\x02',
+ '\x00', '\x38', '\x60', '\xa6', '\x41', '\xb2', '\x3f', '\xbd',
+ '\x02', '\x03', '\x00', '\x38', '\x43', '\xa2', '\xbe', '\x8f',
+ '\x3e', '\x0d', '\x6f', '\x9e', '\x82', '\x19', '\x00', '\x38',
+ '\x01', '\x91', '\xe1', '\x1b', '\x05', '\x91', '\xe0', '\x0b',
+ '\x09', '\x91', '\xe8', '\x8b', '\x1e', '\x91', '\x70', '\x8a',
+ '\x6f', '\xce', '\x82', '\x19', '\x00', '\x38', '\x7c', '\x0a',
+ '\x0d', '\xc1', '\x70', '\x8a', '\x11', '\xc1', '\x70', '\x8a',
+ '\x15', '\xc1', '\x79', '\x0e', '\x7f', '\x0d', '\xa4', '\x19',
+ '\x00', '\x38', '\x70', '\x8a', '\x7f', '\x0d', '\xa8', '\x19',
+ '\x00', '\x38', '\x70', '\x8a', '\x0d', '\x91', '\xe8', '\x8a',
+ '\xff', '\x8d', '\xc0', '\x01', '\x75', '\x86', '\x65', '\x56',
+ '\x04', '\x20', '\x6c', '\xd6', '\x15', '\xd2', '\x65', '\x96',
+ '\x29', '\x55', '\x65', '\x36', '\x23', '\x95', '\x09', '\xd1',
+ '\x69', '\x9a', '\x24', '\x30', '\x2c', '\x36', '\x0d', '\xd1',
+ '\xe9', '\x9a', '\x1c', '\x80', '\x0f', '\x05', '\x09', '\x31',
+ '\x69', '\x9a', '\x10', '\x30', '\x0f', '\x05', '\x83', '\x0b',
+ '\x0a', '\x20', '\x0f', '\x05', '\x0d', '\x31', '\xe9', '\x9a',
+ '\x06', '\x20', '\x0f', '\x05', '\x65', '\x56', '\x35', '\x35',
+ '\x11', '\x31', '\x63', '\x3a', '\xca', '\x32', '\x4d', '\x90',
+ '\x65', '\x96', '\x29', '\x55', '\x65', '\x36', '\x23', '\x95',
+ '\x2f', '\x3e', '\x82', '\x19', '\x00', '\x38', '\x05', '\x31',
+ '\x64', '\x4a', '\x0d', '\x31', '\x69', '\x9a', '\x29', '\x46',
+ '\x01', '\x31', '\x27', '\x9a', '\x65', '\xa6', '\xc3', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\x2f', '\xae', '\xaa', '\x18', '\x00', '\x38', '\x64', '\xb6',
+ '\x3f', '\xbd', '\x18', '\x11', '\x00', '\x38', '\x83', '\x0b',
+ '\x24', '\x30', '\x6a', '\x66', '\x65', '\xa6', '\xc3', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\x2f', '\xae', '\xaa', '\x18', '\x00', '\x38', '\x64', '\xb6',
+ '\x3f', '\xbd', '\x36', '\x0a', '\x00', '\x38', '\x6a', '\xa6',
+ '\xe5', '\x20', '\x65', '\xa6', '\x73', '\x0a', '\x65', '\x26',
+ '\xc3', '\x23', '\xa5', '\x26', '\xc2', '\x23', '\xa5', '\x26',
+ '\xc2', '\x23', '\x2f', '\x2e', '\xaa', '\x18', '\x00', '\x38',
+ '\x62', '\xa6', '\x4f', '\xbc', '\xf0', '\x00', '\x5f', '\xcc',
+ '\x55', '\x05', '\x3f', '\xbd', '\xc2', '\x09', '\x00', '\x38',
+ '\x62', '\xa6', '\x64', '\xb6', '\x67', '\xc6', '\x66', '\xd6',
+ '\x3f', '\xbd', '\x6a', '\x11', '\x00', '\x38', '\x4a', '\xa6',
+ '\x28', '\x20', '\x7b', '\x86', '\x0d', '\x31', '\x69', '\xde',
+ '\x26', '\xd6', '\xe9', '\xdb', '\x11', '\x31', '\x70', '\x8a',
+ '\x62', '\xaa', '\x24', '\xa6', '\x3f', '\xbd', '\x02', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\x4e', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38', '\xaa', '\xe0',
+ '\x0f', '\x05', '\xcf', '\xae', '\x01', '\x00', '\x4c', '\x30',
+ '\x0f', '\x05', '\xcf', '\xae', '\x02', '\x00', '\x46', '\x20',
+ '\x65', '\xa6', '\x62', '\xaa', '\x24', '\xa6', '\x6f', '\x1e',
+ '\x02', '\x03', '\x00', '\x38', '\x7b', '\x86', '\xb1', '\xb9',
+ '\x6f', '\x0e', '\xd2', '\x02', '\x00', '\x38', '\x6f', '\xae',
+ '\x62', '\x18', '\x00', '\x38', '\xb0', '\xb9', '\x66', '\xa6',
+ '\x7b', '\x86', '\xb1', '\xb9', '\x6f', '\xae', '\x6e', '\x18',
+ '\x00', '\x38', '\xb0', '\xb9', '\x62', '\xa6', '\x64', '\xb6',
+ '\x3f', '\xbd', '\xca', '\x10', '\x00', '\x38', '\x41', '\x92',
+ '\xc3', '\x9b', '\x11', '\x31', '\x6d', '\x9e', '\x01', '\x92',
+ '\x58', '\xe0', '\xed', '\x9b', '\x65', '\xa6', '\xc3', '\xa3',
+ '\xa5', '\xa6', '\xc2', '\xa3', '\xa5', '\xa6', '\xc2', '\xa3',
+ '\x6f', '\xad', '\xaa', '\x18', '\x00', '\x38', '\x62', '\xae',
+ '\x24', '\xa6', '\x6f', '\x1e', '\x02', '\x03', '\x00', '\x38',
+ '\x7b', '\x86', '\xb1', '\xb9', '\x6f', '\x0e', '\xd2', '\x02',
+ '\x00', '\x38', '\x6f', '\xae', '\x76', '\x18', '\x00', '\x38',
+ '\xb0', '\xb9', '\x66', '\xa6', '\x7b', '\x86', '\xb1', '\xb9',
+ '\x6f', '\xae', '\x6e', '\x18', '\x00', '\x38', '\xb0', '\xb9',
+ '\x62', '\xa6', '\x64', '\xb6', '\x67', '\xc6', '\x66', '\xd6',
+ '\x3f', '\xbd', '\x1a', '\x12', '\x00', '\x38', '\x0d', '\x31',
+ '\x6d', '\x9e', '\x26', '\x96', '\xed', '\x9b', '\x11', '\x31',
+ '\x70', '\x8a', '\x6f', '\xce', '\x82', '\x19', '\x00', '\x38',
+ '\x0d', '\xc1', '\x69', '\x9a', '\x7f', '\x0d', '\xa4', '\x19',
+ '\x00', '\x38', '\x29', '\x9a', '\xe8', '\x96', '\xff', '\x1d',
+ '\x44', '\xfe', '\x0f', '\x05', '\x75', '\x86', '\x6f', '\x2e',
+ '\xaa', '\x18', '\x00', '\x38', '\x6f', '\x1e', '\x82', '\x19',
+ '\x00', '\x38', '\x09', '\x11', '\xa0', '\x0b', '\x4c', '\x30',
+ '\x7b', '\x86', '\x62', '\xaa', '\x3f', '\xbd', '\x02', '\x03',
+ '\x00', '\x38', '\x6f', '\xae', '\x82', '\x18', '\x00', '\x38',
+ '\x3f', '\xbd', '\xd2', '\x02', '\x00', '\x38', '\x70', '\x86',
+ '\x09', '\x11', '\xe0', '\x0a', '\x22', '\x00', '\x0f', '\x05',
+ '\x05', '\x11', '\x29', '\x0a', '\x01', '\x11', '\x6d', '\xda',
+ '\x62', '\x99', '\x59', '\x9a', '\x4d', '\x05', '\xd9', '\x9a',
+ '\xff', '\x2d', '\x9a', '\xfd', '\x0f', '\x05', '\x02', '\x02',
+ '\x09', '\x11', '\xe0', '\x0a', '\xe3', '\x10', '\x0f', '\x05',
+ '\x6f', '\xae', '\x92', '\x18', '\x00', '\x38', '\x3f', '\xbd',
+ '\xd2', '\x02', '\x00', '\x38', '\x0f', '\x2c', '\x6c', '\x00',
+ '\x01', '\x52', '\xc1', '\x52', '\xa5', '\x80', '\x15', '\x12',
+ '\x7a', '\x86', '\xbe', '\x8f', '\x3e', '\x0d', '\x00', '\x00',
+ '\x7f', '\xb6', '\x0f', '\x05', '\x00', '\x00', '\x00', '\x00',
+ '\x0d', '\x0a', '\x0d', '\x0a', '\x44', '\x65', '\x76', '\x69',
+ '\x63', '\x65', '\x20', '\x49', '\x44', '\x20', '\x3d', '\x20',
+ '\x00', '\x00', '\x43', '\x68', '\x65', '\x63', '\x6b', '\x73',
+ '\x75', '\x6d', '\x20', '\x6f', '\x66', '\x20', '\x62', '\x6f',
+ '\x6f', '\x74', '\x6c', '\x6f', '\x61', '\x64', '\x65', '\x72',
+ '\x20', '\x69', '\x73', '\x20', '\x00', '\x00', '\x57', '\x61',
+ '\x69', '\x74', '\x69', '\x6e', '\x67', '\x20', '\x66', '\x6f',
+ '\x72', '\x20', '\x6c', '\x6f', '\x61', '\x64', '\x20', '\x69',
+ '\x6e', '\x66', '\x6f', '\x2e', '\x0d', '\x0a', '\x00', '\x00',
+ '\x47', '\x6f', '\x74', '\x20', '\x6c', '\x6f', '\x61', '\x64',
+ '\x20', '\x69', '\x6e', '\x66', '\x6f', '\x2e', '\x0d', '\x0a',
+ '\x00', '\x00', '\x50', '\x41', '\x43', '\x4b', '\x45', '\x54',
+ '\x5f', '\x49', '\x4e', '\x46', '\x4f', '\x0d', '\x0a', '\x00',
+ '\x53', '\x45', '\x54', '\x5f', '\x52', '\x45', '\x47', '\x49',
+ '\x53', '\x54', '\x45', '\x52', '\x0d', '\x0a', '\x00', '\x00',
+ '\x47', '\x45', '\x54', '\x5f', '\x52', '\x45', '\x47', '\x49',
+ '\x53', '\x54', '\x45', '\x52', '\x0d', '\x0a', '\x00', '\x00',
+ '\x50', '\x41', '\x55', '\x53', '\x45', '\x5f', '\x4c', '\x4f',
+ '\x4f', '\x50', '\x0d', '\x0a', '\x00', '\x00', '\x4d', '\x45',
+ '\x4d', '\x5f', '\x56', '\x45', '\x52', '\x49', '\x46', '\x59',
+ '\x0d', '\x0a', '\x00', '\x00', '\x76', '\x65', '\x72', '\x69',
+ '\x66', '\x79', '\x20', '\x66', '\x61', '\x69', '\x6c', '\x65',
+ '\x64', '\x0d', '\x0a', '\x00', '\x4d', '\x45', '\x4d', '\x5f',
+ '\x54', '\x45', '\x53', '\x54', '\x0d', '\x0a', '\x00', '\x00',
+ '\x23', '\x23', '\x23', '\x20', '\x4d', '\x65', '\x6d', '\x6f',
+ '\x72', '\x79', '\x20', '\x74', '\x65', '\x73', '\x74', '\x20',
+ '\x66', '\x61', '\x69', '\x6c', '\x65', '\x64', '\x20', '\x61',
+ '\x74', '\x20', '\x00', '\x00', '\x50', '\x61', '\x73', '\x73',
+ '\x65', '\x64', '\x20', '\x6d', '\x65', '\x6d', '\x6f', '\x72',
+ '\x79', '\x20', '\x74', '\x65', '\x73', '\x74', '\x2e', '\x0d',
+ '\x0a', '\x00', '\x4d', '\x45', '\x4d', '\x5f', '\x44', '\x55',
+ '\x4d', '\x50', '\x0d', '\x0a', '\x00', '\x00', '\x4d', '\x45',
+ '\x4d', '\x5f', '\x43', '\x4c', '\x45', '\x41', '\x52', '\x0d',
+ '\x0a', '\x00', '\x46', '\x4c', '\x41', '\x53', '\x48', '\x0d',
+ '\x0a', '\x00', '\x4a', '\x55', '\x4d', '\x50', '\x0d', '\x0a',
+ '\x00', '\x00', '\x45', '\x4e', '\x44', '\x0d', '\x0a', '\x00',
+ '\x23', '\x23', '\x23', '\x20', '\x55', '\x6e', '\x6b', '\x6e',
+ '\x6f', '\x77', '\x6e', '\x20', '\x74', '\x79', '\x70', '\x65',
+ '\x3a', '\x20', '\x00', '\x00', '\x43', '\x68', '\x65', '\x63',
+ '\x6b', '\x73', '\x75', '\x6d', '\x20', '\x6f', '\x66', '\x20',
+ '\x66', '\x69', '\x6c', '\x65', '\x20', '\x69', '\x73', '\x20',
+ '\x00', '\x00', '\x23', '\x23', '\x23', '\x20', '\x4d', '\x65',
+ '\x6d', '\x6f', '\x72', '\x79', '\x20', '\x74', '\x65', '\x73',
+ '\x74', '\x20', '\x31', '\x20', '\x66', '\x61', '\x69', '\x6c',
+ '\x65', '\x64', '\x20', '\x61', '\x74', '\x20', '\x00', '\x00',
+ '\x23', '\x23', '\x23', '\x20', '\x4d', '\x65', '\x6d', '\x6f',
+ '\x72', '\x79', '\x20', '\x74', '\x65', '\x73', '\x74', '\x20',
+ '\x32', '\x20', '\x66', '\x61', '\x69', '\x6c', '\x65', '\x64',
+ '\x20', '\x61', '\x74', '\x20', '\x00', '\x00', '\x20', '\x3a',
+ '\x00', '\x00', '\x38', '\x4d', '\x62', '\x20', '\x42', '\x42',
+ '\x00', '\x00', '\x38', '\x4d', '\x62', '\x20', '\x54', '\x42',
+ '\x00', '\x00', '\x31', '\x36', '\x4d', '\x62', '\x20', '\x42',
+ '\x42', '\x00', '\x31', '\x36', '\x4d', '\x62', '\x20', '\x54',
+ '\x42', '\x00', '\x33', '\x32', '\x4d', '\x62', '\x20', '\x54',
+ '\x42', '\x00', '\x55', '\x6e', '\x73', '\x75', '\x70', '\x70',
+ '\x6f', '\x72', '\x74', '\x65', '\x64', '\x20', '\x69', '\x6e',
+ '\x74', '\x65', '\x72', '\x6c', '\x65', '\x61', '\x76', '\x65',
+ '\x21', '\x0a', '\x00', '\x00', '\x46', '\x6f', '\x75', '\x6e',
+ '\x64', '\x20', '\x31', '\x20', '\x78', '\x20', '\x43', '\x46',
+ '\x49', '\x20', '\x61', '\x74', '\x20', '\x00', '\x54', '\x6f',
+ '\x6f', '\x20', '\x6d', '\x61', '\x6e', '\x79', '\x20', '\x72',
+ '\x65', '\x67', '\x69', '\x6f', '\x6e', '\x73', '\x20', '\x6f',
+ '\x6e', '\x20', '\x63', '\x68', '\x69', '\x70', '\x21', '\x0a',
+ '\x00', '\x00', '\x4e', '\x6f', '\x20', '\x73', '\x69', '\x6e',
+ '\x67', '\x6c', '\x65', '\x20', '\x78', '\x31', '\x36', '\x20',
+ '\x61', '\x74', '\x20', '\x00', '\x4e', '\x6f', '\x20', '\x69',
+ '\x6e', '\x74', '\x65', '\x72', '\x6c', '\x65', '\x61', '\x76',
+ '\x65', '\x64', '\x20', '\x78', '\x31', '\x36', '\x20', '\x61',
+ '\x74', '\x20', '\x00', '\x00', '\x46', '\x6f', '\x75', '\x6e',
+ '\x64', '\x20', '\x00', '\x00', '\x31', '\x00', '\x32', '\x00',
+ '\x20', '\x78', '\x20', '\x00', '\x46', '\x61', '\x74', '\x61',
+ '\x6c', '\x3a', '\x20', '\x66', '\x6c', '\x61', '\x73', '\x68',
+ '\x20', '\x69', '\x73', '\x20', '\x74', '\x6f', '\x6f', '\x20',
+ '\x73', '\x6d', '\x61', '\x6c', '\x6c', '\x2e', '\x0a', '\x00',
+ '\x53', '\x65', '\x63', '\x74', '\x6f', '\x72', '\x20', '\x65',
+ '\x72', '\x61', '\x73', '\x65', '\x20', '\x65', '\x72', '\x72',
+ '\x6f', '\x72', '\x0a', '\x00', '\x45', '\x72', '\x72', '\x6f',
+ '\x72', '\x20', '\x61', '\x74', '\x20', '\x00', '\x3a', '\x20',
+ '\x4e', '\x6f', '\x20', '\x6e', '\x65', '\x65', '\x64', '\x20',
+ '\x74', '\x6f', '\x20', '\x77', '\x72', '\x69', '\x74', '\x65',
+ '\x0a', '\x00', '\x3a', '\x20', '\x45', '\x72', '\x61', '\x73',
+ '\x69', '\x6e', '\x67', '\x20', '\x00', '\x00', '\x20', '\x62',
+ '\x79', '\x74', '\x65', '\x73', '\x0a', '\x00', '\x3a', '\x20',
+ '\x57', '\x72', '\x69', '\x74', '\x69', '\x6e', '\x67', '\x20',
+ '\x00', '\x00', '\x3a', '\x20', '\x56', '\x65', '\x72', '\x69',
+ '\x66', '\x79', '\x69', '\x6e', '\x67', '\x2e', '\x2e', '\x2e',
+ '\x00', '\x00', '\x4f', '\x4b', '\x0a', '\x00', '\x6a', '\x17',
+ '\x00', '\x38', '\x72', '\x17', '\x00', '\x38', '\x7a', '\x17',
+ '\x00', '\x38', '\x82', '\x17', '\x00', '\x38', '\x8a', '\x17',
+ '\x00', '\x38', '\x00', '\x00', '\x00', '\x80', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
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+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
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+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00', '\x00',
+ '\x00', '\x00', '\x00', '\x00', '\x54', '\x68', '\x69', '\x73',
+ '\x20', '\x62', '\x6f', '\x6f', '\x74', '\x6c', '\x6f', '\x61',
+ '\x64', '\x65', '\x72', '\x20', '\x77', '\x61', '\x73', '\x20',
+ '\x62', '\x75', '\x69', '\x6c', '\x74', '\x20', '\x62', '\x79',
+ '\x20', '\x72', '\x6f', '\x6f', '\x74', '\x20', '\x6f', '\x6e',
+ '\x20', '\x57', '\x65', '\x64', '\x20', '\x4d', '\x61', '\x79',
+ '\x20', '\x31', '\x36', '\x20', '\x32', '\x31', '\x3a', '\x33',
+ '\x31', '\x3a', '\x34', '\x36', '\x20', '\x43', '\x45', '\x53',
+ '\x54', '\x20', '\x32', '\x30', '\x30', '\x37', '\x2e', '\x0d',
+ '\x0a', '\x00'
+};
diff --git a/package/etrax-tools/src/e100boot/sbl/serial.c b/package/etrax-tools/src/e100boot/sbl/serial.c
new file mode 100644
index 000000000..95a02299e
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/serial.c
@@ -0,0 +1,637 @@
+/*!***************************************************************************
+*!
+*! FILE NAME : serial.c
+*!
+*! DESCRIPTION: Serial boot stuff for e100boot.
+*!
+*! ---------------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! 1996 Ronny Raneup Initial version
+*! 2002 05 02 Ronny Ranerup Moved it into this file
+*! ---------------------------------------------------------------------------
+*! (C) Copyright 1999-2003 Axis Communications AB, LUND, SWEDEN
+*!***************************************************************************/
+
+/************************** Include files ********************************/
+
+#include <conf.h>
+#include <e100boot.h>
+#include <serial.h>
+#include <common.h>
+
+/************************** Type definitions *****************************/
+
+/************************** Global variables *****************************/
+
+FILE *serialFd;
+int set_baudrate = 9600; /* Baudrate for serial boot (after bootloader). */
+
+/************************** Constants and macros *************************/
+
+/************************** Function prototypes **************************/
+
+int SetControlMode(FILE *fd, int value, int onoff);
+int SetInputMode(FILE *fd, int value, int onoff);
+int SetLocalMode(FILE *fd, int value, int onoff);
+int SetOutputMode(FILE *fd, int value, int onoff);
+int WaitForRead(int s, int usecs);
+int WaitForWrite(int s, int usecs);
+void setBaudRate(unsigned int b);
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SerBoot
+*#
+*# DESCRIPTION: The main serial boot routine.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000 01 07 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+SerBoot(void)
+{
+ int seq = 0;
+ struct packet_buf *p;
+ int got_new_ack = 0;
+ int connected = 0;
+ char rec_buf;
+
+ while ((p = create_packet(seq))) {
+ int offset = 0;
+ int tr_len = 0;
+ static char fName[MAX_STRING_LEN] = {0,};
+
+ if (strcmp(fName, p->boot_file->fileName) != 0) {
+ while (connected && got_new_ack == 0) {
+ WaitForRead(fileno(serialFd), 1000000); /* Did we get data? */
+
+ if(fread(&rec_buf, 1, 1, serialFd) > 0) {
+ fwrite(&rec_buf, 1, 1, stderr);
+ if (rec_buf == '+') {
+ printf("# Got ack.\n");
+ got_new_ack = 1;
+ }
+ }
+ }
+
+ strcpy(fName, p->boot_file->fileName);
+ printf("# transmitting file '%s'\n", fName);
+ got_new_ack = 0;
+ }
+
+ printf("# transmitting %d bytes at baudrate %d.\n", (int)p->size, p->baud_rate);
+
+ // setBaudRate(p->baud_rate);
+
+ while (tr_len != p->size) {
+
+ if (WaitForRead(fileno(serialFd), 0)) { /* Did we get data? */
+ // static int connected = 0;
+ char rec_buf = 0;
+ int rec_len = 0;
+
+ if((rec_len = fread(&rec_buf, 1, 1, serialFd)) > 0) {
+ if (rec_buf == '+') {
+ if (!connected++) {
+ printf("# Got ack.\n");
+ }
+ else {
+ got_new_ack = 1;
+ printf("# Got ack.\n");
+ }
+ fwrite(&rec_buf, rec_len, 1, stderr);
+ }
+ }
+ }
+
+ if (tr_len < p->size) { /* send one byte */
+ while (!(WaitForWrite(fileno(serialFd), 1000000))) { }
+ fwrite(&p->data[offset+tr_len], 1, 1, serialFd);
+ tr_len++;
+ }
+ }
+
+ seq++; /* We have transmitted entire packet. */
+ }
+
+ printf("# Transmission done. Just listening now.\n");
+
+ while(1) {
+ if (WaitForRead(fileno(serialFd), 10000000)) { /* Did we get data? */
+ char rec_buf;
+ int rec_len = 0;
+
+ if((rec_len = fread(&rec_buf, 1, 1, serialFd)) > 0) {
+ fwrite(&rec_buf, rec_len, 1, stderr);
+ }
+ }
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetupSerial
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 970325 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetupSerial(void)
+{
+ int baudRates[] = {0, 50, 75, 110, 134, 150, 200, 300, 600,
+ 1200, 1800, 2400, 4800, 9600, 19200, 38400, 57600, 115200};
+ struct termios ti;
+ int baudrate;
+
+ if ((serialFd = fopen(device, "r+")) == NULL) {
+ perror("Can't open modem");
+ return FALSE;
+ }
+
+ /* Important. Remember this!!!!!!! */
+ /* setvbuf(serialFd, NULL, _IONBF, 0); */
+
+ setvbuf(serialFd, NULL, _IONBF, 0);
+ setvbuf(stdout, NULL, _IONBF, 0);
+
+ if (fcntl(fileno(serialFd), F_SETFL, O_NONBLOCK) == -1) {
+ perror("fcntl");
+ return FALSE;
+ }
+
+ tcflush(fileno(serialFd), TCIOFLUSH);
+
+ if (tcgetattr(fileno(serialFd), &ti)) {
+ perror("tcgetattr");
+ return FALSE;
+ }
+
+ ti.c_cc[VMIN] = 1;
+ ti.c_cc[VTIME] = 0;
+ ti.c_cc[VSTART] = 0x11;
+ ti.c_cc[VSTOP] = 0x13;
+
+ if (tcsetattr(fileno(serialFd), TCSANOW, &ti)) {
+ perror("tcsetattr");
+ return FALSE;
+ }
+
+ //if (db3) printf("outspeed: %d, inspeed: %d\n", baudRates[cfgetospeed(&ti)], baudRates[cfgetispeed(&ti)]);
+ {
+ int new_baudrate = 0;
+
+ if (set_baudrate <= 50) {
+ baudrate = B50;
+ new_baudrate = 50;
+ }
+ else if (set_baudrate <= 75) {
+ baudrate = B75;
+ new_baudrate = 75;
+ }
+ else if (set_baudrate <= 110) {
+ baudrate = B110;
+ new_baudrate = 110;
+ }
+ else if (set_baudrate <= 134) {
+ baudrate = B134;
+ new_baudrate = 134;
+ }
+ else if (set_baudrate <= 150) {
+ baudrate = B150;
+ new_baudrate = 150;
+ }
+ else if (set_baudrate <= 200) {
+ baudrate = B200;
+ new_baudrate = 200;
+ }
+ else if (set_baudrate <= 300) {
+ baudrate = B300;
+ new_baudrate = 300;
+ }
+ else if (set_baudrate <= 600) {
+ baudrate = B600;
+ new_baudrate = 600;
+ }
+ else if (set_baudrate <= 1200) {
+ baudrate = B1200;
+ new_baudrate = 1200;
+ }
+ else if (set_baudrate <= 1800) {
+ baudrate = B1800;
+ new_baudrate = 1800;
+ }
+ else if (set_baudrate <= 2400) {
+ baudrate = B2400;
+ new_baudrate = 2400;
+ }
+ else if (set_baudrate <= 4800) {
+ baudrate = B4800;
+ new_baudrate = 4800;
+ }
+ else if (set_baudrate <= 9600) {
+ baudrate = B9600;
+ new_baudrate = 9600;
+ }
+ else if (set_baudrate <= 19200) {
+ baudrate = B19200;
+ new_baudrate = 19200;
+ }
+ else if (set_baudrate <= 38400)
+ baudrate = B38400;
+#if defined(B57600) /* POSIX only defines <= 38400 */
+ else if (set_baudrate <= 57600) {
+ baudrate = B57600;
+ new_baudrate = 57600;
+ }
+#endif
+#if defined(B115200)
+ else if (set_baudrate <= 115200) {
+ baudrate = B115200;
+ new_baudrate = 115200;
+ }
+#endif
+#if defined(B230400)
+ else if (set_baudrate <= 230400) {
+ baudrate = B230400;
+ new_baudrate = 230400;
+ }
+#endif
+ else {
+ baudrate = B38400;
+ }
+
+ cfsetispeed(&ti, B9600);
+ cfsetospeed(&ti, baudrate);
+ tcsetattr(fileno(serialFd), TCSANOW, &ti);
+
+ // printf("* baudrate set to %d\n", new_baudrate);
+ set_baudrate = new_baudrate;
+
+ if (db3) printf("outspeed: %d, inspeed: %d\n", baudRates[cfgetospeed(&ti)], baudRates[cfgetispeed(&ti)]);
+ }
+
+ cfmakeraw(&ti);
+
+ SetInputMode(serialFd, IXON, FALSE);
+ SetInputMode(serialFd, IXOFF, FALSE);
+ SetInputMode(serialFd, IXANY, FALSE);
+ SetInputMode(serialFd, ICRNL, FALSE);
+ SetInputMode(serialFd, IGNPAR, TRUE);
+ SetInputMode(serialFd, IGNBRK, TRUE);
+ SetInputMode(serialFd, IGNPAR, TRUE);
+ SetInputMode(serialFd, INPCK, FALSE);
+
+ SetOutputMode(serialFd, OPOST, FALSE);
+ SetOutputMode(serialFd, ONLCR, FALSE);
+#ifdef OXTABS
+ SetOutputMode(serialFd, OXTABS, FALSE);
+#endif
+
+#ifdef ENOEOT
+ SetOutputMode(serialFd, ENOEOT, FALSE);
+#endif
+
+ SetLocalMode(serialFd, ECHO, FALSE);
+ SetLocalMode(serialFd, ISIG, FALSE);
+
+ SetLocalMode(serialFd, ICANON, FALSE);
+
+ SetControlMode(serialFd, PARENB, FALSE);
+ SetControlMode(serialFd, CLOCAL, TRUE);
+ SetControlMode(serialFd, CREAD, TRUE);
+
+ /* Disable hardware flow control. */
+#if defined(CRTSCTS)
+
+ SetControlMode(serialFd, CRTSCTS, FALSE);
+#if defined(CRTSXOFF)
+ SetControlMode(serialFd, CRTSXOFF, FALSE);
+#endif
+
+#elif defined(CCTS_OFLOW)
+
+ SetControlMode(serialFd, CCTS_OFLOW, FALSE);
+ SetControlMode(serialFd, CRTS_IFLOW, FALSE);
+
+#elif defined(CNEW_RTSCTS)
+
+ SetControlMode(serialFd, CNEW_RTSCTS, FALSE);
+
+#else
+ printf("Cannot set hardware flow control. Set it manually with a terminal program.\n");
+#endif
+
+ return TRUE;
+}
+
+void
+setBaudRate(unsigned int b)
+{
+ int baudRates[] = {0, 50, 75, 110, 134, 150, 200, 300, 600,
+ 1200, 1800, 2400, 4800, 9600, 19200, 38400, 57600, 115200};
+ struct termios ti;
+
+ if (tcgetattr(fileno(serialFd), &ti)) {
+ perror("tcgetattr");
+ exit(EXIT_FAILURE);
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetInputMode
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 970325 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetInputMode(FILE *fd, int value, int onoff)
+{
+ struct termios settings;
+ int result;
+
+ result = tcgetattr(fileno(fd), &settings);
+ if (result < 0)
+ {
+ perror("error in tcgetattr");
+ return FALSE;
+ }
+
+ if (onoff)
+ settings.c_iflag |= value;
+ else
+ settings.c_iflag &= ~value;
+
+ result = tcsetattr(fileno(fd), TCSANOW, &settings);
+ if (result < 0)
+ {
+ perror("error in tcgetattr");
+ return FALSE;
+ }
+
+ return 1;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetOutputMode
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2001 May 16 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetOutputMode(FILE *fd, int value, int onoff)
+{
+ struct termios settings;
+ int result;
+
+ result = tcgetattr(fileno(fd), &settings);
+ if (result < 0)
+ {
+ perror("error in tcgetattr");
+ return FALSE;
+ }
+
+ if (onoff)
+ settings.c_oflag |= value;
+ else
+ settings.c_oflag &= ~value;
+
+ result = tcsetattr(fileno(fd), TCSANOW, &settings);
+ if (result < 0)
+ {
+ perror("error in tcgetattr");
+ return FALSE;
+ }
+
+ return 1;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetControlMode
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 970325 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetControlMode(FILE *fd, int value, int onoff)
+{
+#if !defined(_WIN32)
+ struct termios settings;
+ int result;
+
+ result = tcgetattr(fileno(fd), &settings);
+ if (result < 0)
+ {
+ perror("error in tcgetattr");
+ return FALSE;
+ }
+
+ if (onoff)
+ settings.c_cflag |= value;
+ else
+ settings.c_cflag &= ~value;
+
+ result = tcsetattr(fileno(fd), TCSANOW, &settings);
+ if (result < 0)
+ {
+ perror("error in tcgetattr");
+ return FALSE;
+ }
+#endif
+
+ return TRUE;
+}
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetLocalMode
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 970325 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetLocalMode(FILE *fd, int value, int onoff)
+{
+#if !defined(_WIN32)
+ struct termios settings;
+ int result;
+
+ result = tcgetattr(fileno(fd), &settings);
+ if (result < 0)
+ {
+ perror("error in tcgetattr");
+ return FALSE;
+ }
+
+ if (onoff)
+ settings.c_lflag |= value;
+ else
+ settings.c_lflag &= ~value;
+
+ result = tcsetattr(fileno(fd), TCSANOW, &settings);
+ if (result < 0)
+ {
+ perror("error in tcgetattr");
+ return FALSE;
+ }
+#endif
+
+ return TRUE;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: WaitForRead
+*#
+*# PARAMETERS: Timeout in usecs.
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961001 ronny Initial version
+*# 971204 ronny usecs was a only one tenth of what it should be.
+*#
+*#***************************************************************************/
+
+int
+WaitForRead(int s, int usecs)
+{
+ fd_set mask;
+ int ret;
+ struct timeval tm;
+
+ tm.tv_sec = usecs/1000000;
+ tm.tv_usec = usecs%1000000;
+
+ FD_ZERO(&mask);
+ FD_SET(s, &mask);
+
+ if ((ret = select(FD_SETSIZE, &mask, NULL, NULL, &tm)) == -1) {
+ printf("<<< select failed with return: %d.\n", ret);
+ return FALSE;
+ }
+ else {
+ if (db3) printf("* select returned OK:%d\n", ret);
+ }
+
+ if (FD_ISSET(s, &mask) == 0) {
+ if (db2) printf("<<< WaitForRead. No data to read.\n");
+ return FALSE;
+ }
+
+ if (db3) printf("<<< WaitForRead OK. Returned:%d.\n", ret);
+
+ return TRUE;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: WaitForWrite
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000-11-20 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+WaitForWrite(int s, int usecs)
+{
+ fd_set mask;
+ int ret;
+ struct timeval tm;
+
+ tm.tv_sec = usecs/1000000;
+ tm.tv_usec = usecs%1000000;
+
+ FD_ZERO(&mask);
+ FD_SET(s, &mask);
+
+ if ((ret = select(FD_SETSIZE, NULL, &mask, NULL, &tm)) == -1) {
+ printf("<<< select failed with return: %d.\n", ret);
+ return FALSE;
+ }
+ else {
+ if (db3) printf("* select returned OK:%d\n", ret);
+ }
+
+ if (FD_ISSET(s, &mask) == 0) {
+ if (db2) printf("<<< WaitForWrite. No data to read.\n");
+ return FALSE;
+ }
+
+ if (db3) printf("<<< WaitForWrite OK. Returned:%d.\n", ret);
+
+ return TRUE;
+}
diff --git a/package/etrax-tools/src/e100boot/sbl/serial.h b/package/etrax-tools/src/e100boot/sbl/serial.h
new file mode 100644
index 000000000..98e68200c
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/serial.h
@@ -0,0 +1,26 @@
+/*!***************************************************************************
+*!
+*! FILE NAME : serial.h
+*!
+*! DESCRIPTION: Serial boot stuff for e100boot.
+*!
+*! ---------------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! 1996 Ronny Raneup Initial version
+*! 2002 05 02 Ronny Ranerup Moved it into this file
+*! ---------------------------------------------------------------------------
+*! (C) Copyright 1999, 2000, 2001, 2002 Axis Communications AB, LUND, SWEDEN
+*!***************************************************************************/
+/************************** Include files ********************************/
+/************************** Type definitions *****************************/
+/************************** Global variables *****************************/
+
+extern int set_baudrate; /* Baudrate for serial boot (after bootloader). */
+
+/************************** Constants and macros *************************/
+/************************** Function prototypes **************************/
+int SetupSerial (void);
+void SerBoot (void);
diff --git a/package/etrax-tools/src/e100boot/sbl/win32/Makefile b/package/etrax-tools/src/e100boot/sbl/win32/Makefile
new file mode 100644
index 000000000..cb8911a0a
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/win32/Makefile
@@ -0,0 +1,8 @@
+%.o : %.c
+ gcc -mno-cygwin -c -g -Wall -I ../ -I ../../cbl/src/ -I ../../wpdpack/Include -o $@ $<
+
+etrax100boot : common.o network.o boot_images.o
+ gcc -mno-cygwin -g -Wall -L ../../wpdpack/Lib -o $@ $^ -lwpcap -lpacket -lws2_32
+
+clean :
+ rm -f *.o etrax100boot
diff --git a/package/etrax-tools/src/e100boot/sbl/win32/boot_images.c b/package/etrax-tools/src/e100boot/sbl/win32/boot_images.c
new file mode 100755
index 000000000..a09dc9ddb
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/win32/boot_images.c
@@ -0,0 +1,35 @@
+/* boot_images.c - Collection of the different boot images
+ * Johan Adolfsson Axis Communications AB
+ * $Id: boot_images.c,v 1.1 2004/01/26 10:52:40 mikaelp Exp $
+ */
+
+#include <stdio.h>
+#include "boot_images.h"
+
+/* We include the C files here to the size etc. easy */
+#include "net_ima.c"
+#include "ser_ima.c"
+#include "net_noleds_ima.c"
+#include "ser_noleds_ima.c"
+
+struct boot_image_info_type boot_image_info[] =
+{
+ { INTERNAL_NW, net_ima, sizeof net_ima, "Network boot (default)"},
+ { INTERNAL_SER, ser_ima, sizeof ser_ima, "Serial boot"},
+ { INTERNAL_SER_NOLEDS, ser_noleds_ima, sizeof ser_noleds_ima, "Serial boot, no leds"},
+ { INTERNAL_NW_NOLEDS, net_noleds_ima, sizeof net_noleds_ima, "Network boot, no leds"},
+
+ { "DBGNONE", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+ { "DBG0", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+ { "DBG1", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+ { "DBG2", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+ { "DBG3", net_ima, sizeof net_ima, "Obsolete (use INTERNAL_NW instead)" },
+
+ { "DBGNONE_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+ { "DBG0_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+ { "DBG1_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+ { "DBG2_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+ { "DBG3_NOLEDS", net_noleds_ima, sizeof net_noleds_ima, "Obsolete (use INTERNAL_NW_NOLEDS instead)" },
+
+ { NULL, NULL, 0, NULL } /* End of array */
+};
diff --git a/package/etrax-tools/src/e100boot/sbl/win32/common.c b/package/etrax-tools/src/e100boot/sbl/win32/common.c
new file mode 100644
index 000000000..fd47a5310
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/win32/common.c
@@ -0,0 +1,1651 @@
+/*!***************************************************************************
+*!
+*! FILE NAME : common.c
+*!
+*! DESCRIPTION: Common functions for e100boot.
+*!
+*! ---------------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! ??? ? ???? Ronny Ranerup Initial version
+*! ---------------------------------------------------------------------------
+*! (C) Copyright 1999-2003 Axis Communications AB, LUND, SWEDEN
+*!***************************************************************************/
+/* $Id: common.c,v 1.1 2004/01/26 10:52:40 mikaelp Exp $ */
+
+/************************** Version **************************************/
+
+char version[] = "Time-stamp: $Id: common.c,v 1.1 2004/01/26 10:52:40 mikaelp Exp $";
+
+/************************** Include files ********************************/
+
+#define WIN32_LEAN_AND_MEAN
+#include <windows.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <io.h>
+#include <winsock2.h>
+
+#include <e100boot.h>
+#include <pcap.h>
+#include "boot_images.h"
+#include <reg_des.h>
+#include <sv_addr_ag.h>
+#include <common.h>
+
+#include <serial.h>
+#include <network.h>
+
+/************************** Constants and macros *************************/
+
+#define BOOT_CMDS_FILE "BOOT_CMDS"
+
+/************************** Type definitions *****************************/
+
+struct label_t {
+ struct label_t *prev;
+ udword addr;
+ char *name;
+};
+
+/************************** Global variables *****************************/
+
+char needle[MAX_STRING_LEN] = "END"; /* search needle for --find */
+int needle_len = 3;
+
+int exitonfind = FALSE;
+
+int doing_flash = FALSE; /* Just a flag to see if we should
+ warn that it might take some
+ time. */
+
+int toFiles = FALSE; /* Dump all packets to files. */
+int cmdsOnly = FALSE; /* Just dump boot cmds to file. */
+int netBoot = TRUE; /* Do network boot? */
+int serBoot = FALSE; /* Do serial boot? */
+
+struct label_t *loop_label = NULL;
+struct label_t *label = NULL;
+
+struct packet_buf *first_packet = NULL;
+struct packet_buf *last_packet = NULL;
+
+struct packet_buf *boot_cmds_packet;
+
+int create_boot_loader = TRUE;
+
+/* We use the INTERNAL boot image as default */
+char boot_loader_file[MAX_STRING_LEN] = INTERNAL_NW;
+
+int noleds = FALSE; /* Use boot images that doesn't toggle leds? */
+
+struct boot_files_T *first_boot_file = NULL;
+struct boot_files_T *last_boot_file = NULL;
+
+unsigned int boot_cmds[SIZE_OF_BOOT_CMDS / sizeof(unsigned int)];
+int boot_cmds_cnt = 0;
+
+int svboot = FALSE;
+
+int quiet = 0;
+
+struct packet_header_T send_packet;
+struct packet_header_T *receive_packet;
+
+int seq_nr = 0;
+
+/* debug flags */
+int db1 = FALSE;
+int db2 = FALSE;
+int db3 = FALSE;
+int db4 = FALSE;
+
+char device[MAX_STRING_LEN] = "";
+
+
+/************************** Function prototypes **************************/
+
+FILE *Fopen (const char *name, const char *mode);
+int main (int argc, const char *argv[]);
+int GetNumberOption (int *argNr, int argCount, const char *argVect[], unsigned int *ret, const char *option, int base);
+int GetStringOption (int *argNr, int argCount, const char *argVect[], char *ret, const char *option);
+int GetRegisterOption (int *argNr, int argCount, const char *argVect[], unsigned int *ret, const char *option, int base);
+struct boot_files_T* allocate_boot_file (struct boot_files_T *bf);
+struct packet_buf* CreateNewBootPacket (void);
+struct packet_buf* allocate_packet (struct packet_buf *p);
+void SigHandler (int sig);
+void CreateBootLoader (void);
+void FinishBootCmds (void);
+void ParseArgs (int argc, const char *argv[]);
+void PrintHelp (void);
+void CreateBootCmds (void);
+void handle_labels (void);
+void new_label (struct label_t **label, udword addr, const char *name);
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: main
+*#
+*# PARAMETERS: Command line arguments.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+main(int argc, const char *argv[])
+{
+ ParseArgs(argc, argv);
+
+ if (cmdsOnly) {
+ /* We make this a special case to avoid messing up other code. */
+ CreateBootCmds();
+ FinishBootCmds();
+ SendToDevice(&boot_cmds_packet->data[SIZE_OF_HEADER],SIZE_OF_BOOT_CMDS);
+ exit(EXIT_SUCCESS);
+ }
+
+ if (netBoot && !toFiles) {
+ /* Do not bother with this if we just want to write the packets to
+ files. Means you do not have to be root to run --tofiles. */
+ net_init();
+ }
+ else if (serBoot) {
+ /*if (!SetupSerial())*/ {
+ exit(0);
+ }
+ }
+
+ CreateBootLoader();
+ CreateBootCmds();
+ FinishBootCmds();
+
+ printf("Starting boot...\n");
+ if (doing_flash) {
+ printf("We're doing a flash write, this may take up to a few minutes...\n");
+ }
+
+ if (toFiles) {
+ udword seq = 0;
+ struct packet_buf *p;
+
+ while((p = create_packet(seq++))) {
+ SendToDevice(p->data, p->size);
+ }
+
+ exit(EXIT_SUCCESS);
+ }
+
+ if (netBoot) {
+ NetBoot();
+ }
+ else if (serBoot) {
+ /*SerBoot();*/
+ }
+
+ printf("Done.\n");
+ return EXIT_SUCCESS;
+} /* main */
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: free_packet
+*#
+*# PARAMETERS: struct to free
+*#
+*# DESCRIPTION: Frees struct and data in struct.
+*#
+*# RETURNS: Pointer to next struct.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000 02 07 ronny Initial version
+*#
+*#***************************************************************************/
+
+struct packet_buf*
+free_packet(struct packet_buf *p)
+{
+ struct packet_buf *next_p;
+
+ next_p = p->next;
+ free(p->data);
+ free(p);
+ return(next_p);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: create_packet
+*#
+*# PARAMETERS: Sequence number of desired packet.
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000 06 28 ronny Initial version
+*#
+*#***************************************************************************/
+
+struct packet_buf*
+create_packet(udword seq)
+{
+ struct packet_buf *p = first_packet;
+ /* Should check last first? */
+
+ if (db4) printf("> create_packet seq %d\n", seq);
+
+ while (p) {
+ if (p->seq == seq) {
+ return(p);
+ }
+ p = p->next;
+ }
+
+ return(CreateNewBootPacket());
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: find_string
+*#
+*# PARAMETERS: New string to search.
+*#
+*# DESCRIPTION: Searches a number of strings for needle[], including strings
+*# overlapping between different calls.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 020502 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+find_string(char *str)
+{
+ static int matched = 0;
+ int hs[MAX_STRING_LEN];
+ static int cur_hs = 0;
+ static int hs_len = 0;
+ static int last_hs = 0;
+
+ static int cur_needle = 0;
+
+ if (!needle[0]) {
+ return;
+ }
+ // printf("# adding >%s<\n", str);
+
+ {
+ int c = 0;
+ int s = 0;
+
+ while((c = str[s])) {
+ // printf("\n# cur_hs %d, hs_len %d\n", cur_hs, hs_len);
+ {
+ int i;
+
+ for(i = 0; i != hs_len; i++) {
+ // printf("hs[%d] = %d(%c)\n", i, (int)hs[i], hs[i] < 32 ? 'X' : hs[i]);
+ }
+ }
+
+ if (cur_hs == hs_len) {
+ // printf("adding char %d(%c) at hs[%d]\n", (int)c, c < 32 ? 'X' : c, hs_len);
+ hs[hs_len] = c;
+ hs_len++;
+ s++;
+ }
+
+ // printf("testing %d at cur_hs %d against %d at cur_needle %d\n",
+ // (int)hs[cur_hs], cur_hs, (int)needle[cur_needle], cur_needle);
+
+ if (hs[cur_hs] == needle[cur_needle]) {
+ if (cur_needle+1 == needle_len) {
+ int exitcode = EXIT_SUCCESS;
+
+ // printf("\nFound needle from --find option.\n");
+ if (exitonfind) {
+ int ret;
+ // printf("scanf (s=%d)'%s'\n", s, &str[s+1]);
+ ret = sscanf(&str[s+1], "%i", &exitcode);
+ // printf("ret %d, '%s'\n", ret, &str[s+1]);
+ }
+ printf("Exiting with code %d\n", exitcode);
+ exit(exitcode);
+ }
+ cur_needle++;
+ cur_hs++;
+ }
+ else {
+ // printf("no match, shifting hs.\n");
+ {
+ int i;
+ for(i=0; i!= hs_len-1; i++) {
+ hs[i] = hs[i+1];
+ }
+ }
+ hs_len--;
+ cur_needle = 0;
+ cur_hs = 0;
+ }
+ }
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: Fopen
+*#
+*# PARAMETERS: Name and mode, both strings.
+*#
+*# DESCRIPTION: Opens a file and returns its fd, or NULL.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+FILE *
+Fopen(const char *name, const char *mode)
+{
+ FILE *fd;
+
+ if (db2) printf(">>> Fopen '%s', mode '%s'\n", name, mode);
+
+ fd = fopen(name, mode);
+
+ if (fd == NULL) {
+ printf("<<< Fopen failed on '%s', mode '%s'\n", name, mode);
+ return ((FILE*) NULL);
+ }
+
+ if (strncmp(mode, "a", 1) == 0) {
+ if (db3) printf("* Append mode, seeking to end.\n");
+ fseek(fd, 0L, SEEK_SET);
+ }
+
+ if (db2) printf("<<< Fopen: '%s'\n", name);
+
+ return(fd);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: ParseArgs
+*#
+*# PARAMETERS: Standard command line args.
+*#
+*# DESCRIPTION: Parses command line arguments.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+void
+ParseArgs (int argc, const char *argv[])
+{
+ int argi;
+ int i;
+ int printHelp = FALSE;
+ int exitCode = EXIT_SUCCESS;
+ char dbStr[MAX_STRING_LEN]; /* Debug option string. */
+ int number;
+ int argCount;
+ const char **argVect;
+ struct stat st;
+
+ if (db4) printf(">>> ParseArgs\n");
+ argCount = argc;
+ argVect = argv;
+
+ for (argi = 1; argi < argCount; argi++) {
+ if (db4) printf("argv[%d] = '%s'\n", argi, argVect[argi]);
+ if (strncmp(argVect[argi], "--from", 6) == 0) {
+ if (GetStringOption(&argi, argCount, argVect, host1, "--from") == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ else {
+ printf("Host: %s %s\n", host1, host2);
+ if (sscanf(host1, "%x-%x-%x-%x-%x-%x", &i, &i, &i, &i, &i, &i) == 6) {
+ printf("Ethernet address\n");
+ }
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--device", 8) == 0) {
+ if (GetStringOption(&argi, argCount, argVect, device, "--device") == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--network", 9) == 0) {
+ netBoot = TRUE;
+ serBoot = FALSE;
+ strcpy(boot_loader_file, INTERNAL_NW);
+ }
+
+ else if (strncmp(argVect[argi], "--serial", 8) == 0) {
+ serBoot = TRUE;
+ netBoot = FALSE;
+ strcpy(device, "/dev/ttyS0");
+ strcpy(boot_loader_file, INTERNAL_SER);
+ }
+
+ else if (strncmp(argVect[argi], "--noleds", 8) == 0) {
+ noleds = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--images", 8) == 0) {
+ int i = 0;
+
+ printf("Internal images:\n");
+
+ while(boot_image_info[i].name) {
+ printf("'%s', %s, size %lu bytes.\n",
+ boot_image_info[i].name,
+ boot_image_info[i].info,
+ boot_image_info[i].len
+ );
+ i++;
+ }
+ exit(EXIT_SUCCESS);
+ }
+
+ else if (strncmp(argv[argi], "--baudrate", 10) == 0) {
+ /* if (GetNumberOption (&argi, argCount, argVect, &set_baudrate, "--baudrate", 10) == 0)*/ {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--tofiles", 9) == 0) {
+ toFiles = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--cmdsonly", 10) == 0) {
+ cmdsOnly = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--to", 4) == 0) {
+ if ((GetStringOption(&argi, argCount, argVect, host2, "--to") == 0)) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ else {
+ printf("Host: %s %s\n", host1, host2);
+ both_addresses = TRUE;
+ if (sscanf(host2, "%x-%x-%x-%x-%x-%x", &i, &i, &i, &i, &i, &i) == 6) {
+ printf("Ethernet address\n");
+ }
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--printp", 8) == 0) {
+ pPacket = 1;
+ }
+
+ else if (strncmp(argVect[argi], "--printascii", 11) == 0) {
+ pPacket = 1;
+ printPacketType = ASCII;
+ }
+
+ else if (strncmp(argVect[argi], "--printudec", 11) == 0) {
+ pPacket = 1;
+ printPacketType = UDEC;
+ }
+
+ else if (strncmp(argVect[argi], "--printhex", 10) == 0) {
+ pPacket = 1;
+ printPacketType = HEX;
+ }
+
+ else if (strncmp(argVect[argi], "--bpl", 5) == 0) {
+ if (GetNumberOption(&argi, argCount, argVect, &p_packet_bpl, "--bpl", 10) == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--promisc", 11) == 0) {
+ promisc = 1;
+ }
+
+ else if (strncmp(argVect[argi], "--5400", 6) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb0000000;
+ boot_cmds[boot_cmds_cnt++] = 0x000095b6;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb0000008;
+ boot_cmds[boot_cmds_cnt++] = 0x0000e751;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb000000c;
+ boot_cmds[boot_cmds_cnt++] = 0x12604040;
+ }
+
+ else if (strncmp(argVect[argi], "--5600", 6) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb0000000;
+ boot_cmds[boot_cmds_cnt++] = 0x000095b6;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb0000008;
+ boot_cmds[boot_cmds_cnt++] = 0x00006751;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = 0xb000000c;
+ boot_cmds[boot_cmds_cnt++] = 0x12204040;
+ }
+
+ else if (strncmp(argVect[argi], "--testcardlx", 12) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x12604040;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_TIMING;
+ boot_cmds[boot_cmds_cnt++] = 0x0000e751;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_WAITSTATES;
+ boot_cmds[boot_cmds_cnt++] = 0x00b395b5;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_BUS_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x00000207;
+ }
+
+ else if (strncmp(argVect[argi], "--testcard", 10) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_WAITSTATES;
+ boot_cmds[boot_cmds_cnt++] = 0x000010b3;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_TIMING;
+ boot_cmds[boot_cmds_cnt++] = 0x00006543;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x12966060;
+ }
+
+ else if (strncmp(argVect[argi], "--devboard", 10) == 0) {
+ /* Printing on serial port will not work until PORT_PB is set... */
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_PORT_PB_SET;
+ boot_cmds[boot_cmds_cnt++] = 0x01001ef3;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_PORT_PA_SET;
+ boot_cmds[boot_cmds_cnt++] = 0x00001df0;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_WAITSTATES;
+ boot_cmds[boot_cmds_cnt++] = 0x000095a6;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x1a200040;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_DRAM_TIMING;
+ boot_cmds[boot_cmds_cnt++] = 0x00005611;
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ boot_cmds[boot_cmds_cnt++] = (unsigned int)R_BUS_CONFIG;
+ boot_cmds[boot_cmds_cnt++] = 0x00000104;
+ }
+
+ else if (strncmp(argVect[argi], "--verify", 8) == 0) {
+ boot_cmds[boot_cmds_cnt++] = MEM_VERIFY;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--verify", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--verify", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--setreg", 8) == 0) {
+ boot_cmds[boot_cmds_cnt++] = SET_REGISTER;
+ if ((argVect[argi+1][0] >= 'A') && (argVect[argi+1][0] <= 'Z')) {
+ GetRegisterOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--setreg", 16);
+ }
+ else {
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--setreg", 16);
+ }
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--setreg", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--getreg", 8) == 0) {
+ boot_cmds[boot_cmds_cnt++] = GET_REGISTER;
+ if ((argVect[argi+1][0] >= 'A') && (argVect[argi+1][0] <= 'Z')) {
+ GetRegisterOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--getreg", 16);
+ }
+ else {
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--getreg", 16);
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--pause", 7) == 0) {
+ boot_cmds[boot_cmds_cnt++] = PAUSE_LOOP;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--pause", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--memtest", 9) == 0) {
+ boot_cmds[boot_cmds_cnt++] = MEM_TEST;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memtest", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memtest", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--loop", 6) == 0) {
+ char str[MAX_STRING_LEN];
+ boot_cmds[boot_cmds_cnt++] = LOOP;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--loop", 16);
+ GetStringOption(&argi, argCount, argVect, str, argVect[argi]);
+ new_label(&loop_label, boot_cmds_cnt+1, str);
+ boot_cmds_cnt++;
+ }
+
+ else if (strncmp(argVect[argi], "--label", 7) == 0) {
+ char str[MAX_STRING_LEN];
+ GetStringOption(&argi, argCount, argVect, str, "--label");
+ new_label(&label, boot_cmds_cnt, str);
+ }
+
+ else if (strncmp(argVect[argi], "--memdump", 9) == 0) {
+ boot_cmds[boot_cmds_cnt++] = MEM_DUMP;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memdump", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memdump", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--memclear", 10) == 0) {
+ boot_cmds[boot_cmds_cnt++] = MEM_CLEAR;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memclear", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--memclear", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--flash", 7) == 0) {
+ boot_cmds[boot_cmds_cnt++] = FLASH;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--flash", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--flash", 16);
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--flash", 16);
+ doing_flash = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--jump", 6) == 0) {
+ boot_cmds[boot_cmds_cnt++] = JUMP;
+ GetNumberOption(&argi, argCount, argVect, &boot_cmds[boot_cmds_cnt++], "--jump", 16);
+ }
+
+ else if (strncmp(argVect[argi], "--file", 6) == 0) {
+ char str[MAX_STRING_LEN];
+ boot_cmds[boot_cmds_cnt++] = PACKET_INFO;
+ GetStringOption(&argi, argCount, argVect,
+ str, "--file"); /* file name */
+ GetNumberOption(&argi, argCount, argVect,
+ &boot_cmds[boot_cmds_cnt++], str, 16); /* address */
+ last_boot_file = allocate_boot_file(last_boot_file);
+ first_boot_file = first_boot_file ? first_boot_file : last_boot_file;
+ last_boot_file->fileName = malloc(strlen(str) + 1);
+ strcpy(last_boot_file->fileName, str);
+ last_boot_file->size_p = &boot_cmds[boot_cmds_cnt];
+ last_boot_file->fd = NULL;
+ last_boot_file->size_sent = 0;
+ if (strncmp(str, "-", 1) != 0) {
+ if (stat(last_boot_file->fileName, &st) == -1) {
+ printf("Cannot get size of file '%s'. %s.\n",
+ last_boot_file->fileName, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ if (db2) printf("* size is %d 0x%8.8x\n",
+ (int)st.st_size, (unsigned int)st.st_size);
+ last_boot_file->size = st.st_size;
+ boot_cmds[boot_cmds_cnt++] = st.st_size;
+ }
+ else {
+ GetNumberOption(&argi, argCount, argVect,
+ &last_boot_file->size , str, 16); /* size */
+
+ boot_cmds[boot_cmds_cnt++] = last_boot_file->size;
+ printf("* size is %d 0x%8.8x\n", last_boot_file->size,
+ last_boot_file->size);
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--bootfile", 10) == 0) {
+ GetStringOption(&argi, argCount, argVect,
+ boot_loader_file, "--bootfile");
+ }
+
+ else if (strncmp(argVect[argi], "-d", 2) == 0) {
+ if (GetNumberOption (&argi, argCount, argVect, &number, "-d", 10) == 0) {
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ else {
+ sprintf(dbStr, "%d", number);
+ for (i = 0; i != (int) strlen(dbStr); i++) {
+ switch (dbStr[i] - '0') {
+ case 1:
+ db1 = TRUE;
+ break;
+ case 2:
+ db2 = TRUE;
+ break;
+ case 3:
+ db3 = TRUE;
+ break;
+ case 4:
+ db4 = TRUE;
+ break;
+ default:
+ printf("ERROR! Debug level %d is not defined.\n", dbStr[i] - '0');
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ break;
+ }
+ }
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--find", 6) == 0) {
+ GetStringOption(&argi, argCount, argVect, needle, "--find");
+ /* convert control characters like /n to the real ascii valure */
+ {
+ int i;
+ int j = 0;
+ char c;
+ int esc = 0;
+
+ for (i = 0; (c = needle[i]); i++,j++) {
+// printf("c = %d, i %d, j %d\n", (int)c, i, j);
+ if (c == '\\') {
+// printf("esc\n");
+ esc = 1;
+ continue;
+ }
+ else if (esc) {
+ esc = 0;
+ switch(c) {
+ case 'r':
+ c = '\r';
+ break;
+
+ case 'n':
+ c = '\n';
+ break;
+
+ case '\\':
+ c = '\\';
+ break;
+
+ default:
+ printf("Uknown escape sequence '\\%c'\n", c);
+ exit(EXIT_FAILURE);
+ }
+ j--;
+ }
+ // printf("setting j %d to %d\n", j, (int)c);
+ needle[j] = c;
+ }
+ needle_len = j;
+ }
+
+ for (i = 0; needle[i]; i++) {
+ //printf("i = %d, c %d\n", i,(int)needle[i]);
+ }
+ }
+
+ else if (strncmp(argVect[argi], "--exitonfind", 12) == 0) {
+ exitonfind = TRUE;
+ }
+
+ else if (strncmp(argVect[argi], "--help", 6) == 0) {
+ printHelp = TRUE;
+ }
+
+ else {
+ printf("ERROR! Don't understand option '%s'\n", argVect[argi]);
+ printHelp = TRUE;
+ exitCode = EXIT_FAILURE;
+ }
+ }
+
+ if (printHelp == TRUE) {
+ PrintHelp();
+ exit(exitCode);
+ }
+
+ if (noleds) {
+ strcpy(&boot_loader_file[strlen(boot_loader_file)], "_NOLEDS");
+ }
+
+ handle_labels();
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: handle_labels
+*#
+*# PARAMETERS: global loop_label, label
+*#
+*# DESCRIPTION: Checks and matches labels from --loop and --label commands
+*# and inserts the resolved addresses into boot commands.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 20020204 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+handle_labels(void)
+{
+ struct label_t *ll = loop_label;
+ struct label_t *l = label;
+ struct label_t *last_l = l;
+
+ while(ll) {
+ int match = 0;
+
+ l = last_l;
+ while(l) {
+ match = 0;
+
+ if (l->name && ll->name && (strcmp(l->name, ll->name) == 0)) {
+ match = 1;
+ boot_cmds[ll->addr] = IO_BUF_START+(l->addr*4);
+ break;
+ }
+ l = l->prev;
+ }
+ if (!match) {
+ printf("Error. No label '%s' defined as needed by --loop command.\n", ll->name);
+ exit(EXIT_FAILURE);
+ }
+ ll = ll->prev;
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: new_label
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 20020201 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+new_label(struct label_t **label, udword addr, const char *name)
+{
+ struct label_t *new_p;
+
+ new_p = malloc(sizeof(struct label_t));
+
+ if (*label == NULL) { /* first one? */
+ *label = new_p;
+ new_p->prev = NULL;
+ }
+ else {
+ new_p->prev = *label;
+ }
+ *label = new_p;
+ new_p->addr = boot_cmds_cnt;
+ new_p->name = malloc(strlen(name));
+ strcpy(new_p->name, name);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetStringOption
+*#
+*# PARAMETERS: int *argNr : Returns next argc here.
+*# int argCount : Index of last argument.
+*# char *argVect[] : argv.
+*# char *ret : Copy string here.
+*# char *option : Name of the option.
+*#
+*# DESCRIPTION: Extracts a string option from argv, and updates argnr.
+*# Returns TRUE/FALSE and string in *ret.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*# 961203 ronny Handles filenames with spaces within 'file name'.
+*#
+*#***************************************************************************/
+
+int
+GetStringOption(int *argNr, int argCount, const char *argVect[], char *ret,
+ const char *option)
+{
+ int startChar = strlen(option);
+
+ *ret = '\0';
+
+ /* Are there any more chars after option? If not skip to next argv. */
+ if (strlen(argVect[*argNr]) <= (unsigned int)startChar) {
+ (*argNr)++;
+ startChar = 0;
+ }
+
+ /* Any args left? */
+ if (*argNr >= argCount) {
+ printf("ERROR! The option '%s' needs a string argument.\n", option);
+ PrintHelp();
+ exit(EXIT_FAILURE);
+ }
+
+ /* avoid stack overflow hacks */
+ if (strlen(&argVect[*argNr][startChar]) > MAX_STRING_LEN) {
+ printf("Argument '%s' longer than maximum allowable %d characters.\n",
+ &argVect[*argNr][startChar], MAX_STRING_LEN);
+ exit(EXIT_FAILURE);
+ }
+
+ strcpy(ret, &argVect[*argNr][startChar]);
+ if (db4) printf("<<< GetStringOption '%s'\n", ret);
+
+ return TRUE;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetNumberOption
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+GetNumberOption(int *argNr, int argCount, const char *argVect[],
+ unsigned int *ret, const char *option, int base)
+{
+ int startChar = 0;
+ int add_io_base = 0;
+
+ (*argNr)++;
+
+ if (*argNr >= argCount) {
+ printf("ERROR! The option '%s' needs a number argument.\n", option);
+ PrintHelp();
+ exit(EXIT_FAILURE);
+ }
+
+ if (argVect[*argNr][startChar] == '+') {
+ add_io_base = 1;
+ startChar++;
+ }
+
+ *ret = strtoul(&argVect[*argNr][startChar], NULL, base);
+
+ if (add_io_base) {
+ *ret += IO_BUF_START;
+ if (*ret < IO_BUF_START || *ret >= IO_BUF_END) {
+ printf("ERROR! '%s' is outside the IO buffer (option '%s').\n",
+ argVect[*argNr], option);
+ exit(EXIT_FAILURE);
+ }
+ }
+
+ if (db4) printf("<<< GetNumberOption %08x\r\n", *ret);
+
+ return TRUE;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetRegisterOption
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+GetRegisterOption(int *argNr, int argCount, const char *argVect[],
+ unsigned int *ret, const char *option, int base)
+{
+ int startChar = 0;
+
+ (*argNr)++;
+
+ if (*argNr >= argCount) {
+ printf("Error! The option '%s' needs a register name.\n", option);
+ PrintHelp();
+ exit(EXIT_FAILURE);
+ }
+
+ {
+ int r = 0;
+
+ while (reg_des[r].name) {
+ if (strcmp(reg_des[r].name, argVect[*argNr]) == 0) {
+ *ret = reg_des[r].addr;
+ return TRUE;
+ break;
+ }
+ r++;
+ }
+ }
+
+ printf("Error! Didn't find a register name matching '%s'.\n",
+ argVect[*argNr]);
+
+ exit(EXIT_FAILURE);
+
+ return FALSE;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: PrintHelp
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Prints help info.
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+PrintHelp(void)
+{
+ printf("e100boot version %s.\n", version);
+
+ printf("\ne100boot [--device devicename] [--file filename|- addr [size]]\n"
+ " [--flash ram-source flash-offset size]\n"
+ " [--pause iter]\n"
+ " [--memtest addr addr]\n"
+ " [--memclear addr addr] [--memdump addr addr]\n"
+ " [--setreg addr|regname val] [--getreg addr|regname]\n"
+ " [--verify addr val] [--label label] [--loop addr label]\n"
+ " [--5400] [--5600] [--testcard] [--devboard]\n"
+ " [--testcardlx] [--network] [--serial]\n"
+ " [--baudrate baudrate] [--bootfile file] [--jump addr]\n"
+ " [--tofiles] [--cmdsonly] [--images] [--noleds]\n"
+ " [--help]\n\n");
+
+ printf(" The commands sent to the cbl, and which are parsed by the cbl,\n"
+ " are stored at 0x%8.8x-0x%8.8x.\n\n", IO_BUF_START, IO_BUF_END);
+
+ printf(" See the man page for more details about e100boot.\n\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: CreateBootLoader
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Creates boot packets from boot file or internal loader.
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+void
+CreateBootLoader(void)
+{
+ struct stat st;
+ char *buf = NULL;
+ // int size_pos = 0x18;
+ // int addr_pos = 0x28;
+ struct packet_header_T *ph;
+ int packet_size;
+ int header_size;
+ int buf_cnt = 0;
+ int i;
+ udword sum = 0;
+
+ if (create_boot_loader) {
+ int image_nbr = 0;
+ int found = 0;
+ const struct boot_image_info_type *info;
+
+ if (db4) printf("> CreateBootLoader\n");
+
+ info = &boot_image_info[image_nbr];
+
+ /* Use internal boot loader? */
+ while (!found && info->name != NULL) {
+ if (strcmp(boot_loader_file, info->name) == 0) {
+ st.st_size = info->len;
+ buf = (char*) malloc(st.st_size);
+ memcpy(buf, info->ptr, st.st_size); /* unnecessary? */
+ found = TRUE;
+ printf("Using internal boot loader: %s - %s.\n",
+ info->name, info->info);
+ }
+ else {
+ image_nbr++;
+ info = &boot_image_info[image_nbr];
+ }
+ }
+
+ /* No internal? Load it from file instead. */
+ if (!found) {
+ FILE *fd;
+
+ /* We didn't find an internal match, load the boot file from disk. */
+ if ((fd = Fopen(boot_loader_file, "r")) == NULL) {
+ printf("Cannot open bootloader '%s'. %s.\n",
+ boot_loader_file, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ if (fstat(fileno(fd), &st) == -1) {
+ printf("Cannot get filestatus of bootloader '%s'. %s.\n",
+ boot_loader_file, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+
+ buf = (char*) malloc(st.st_size);
+ // printf("CreateBootLoader: buf = (char*) malloc(st.st_size); 2\n");
+ if (read(fileno(fd), buf, st.st_size) != st.st_size) {
+ printf("Read fewer bytes than there should be in %s.\n",
+ boot_loader_file);
+ exit(EXIT_FAILURE);
+ }
+
+ fclose(fd);
+ }
+
+ /* Alright, got loader in buf[] and size in st. */
+ if (netBoot) {
+ /* The etrax code for all boot methods are linked to adress
+ 380000f0 but since network boot starts execution at 380000f4
+ we have two nops in the beginning of the code which we do not
+ transmit to etrax in the network case. The link adress
+ doesn't change though. */
+ buf += 4;
+ st.st_size -= 4;
+ packet_size = DATA_SIZE;
+ }
+ else {
+ packet_size = st.st_size;
+ }
+
+ /* Hack binary, insert size and address. */
+
+#define SIZE_PATTERN 0x12345678
+#define ADDR_PATTERN 0x87654321
+#define SIZE_POS (netBoot ? 0x0c : 0x10)
+#define ADDR_POS (netBoot ? 0x10 : 0x14)
+
+ if (*(udword*)&buf[SIZE_POS] != SIZE_PATTERN) {
+ printf("Bootloader corrupt. Should contain ret/nop (0x%8.8x) at 0x%x, but contains %x\n",
+ SIZE_PATTERN, SIZE_POS, *(udword*)&buf[SIZE_POS]);
+ exit(EXIT_FAILURE);
+ }
+
+ /* How much data to load except data in first packet. */
+
+ if (netBoot) {
+ *(udword*)(&buf[SIZE_POS]) = st.st_size - DATA_SIZE;
+ }
+ else {
+ *(udword*)(&buf[SIZE_POS]) = st.st_size - 784;
+ }
+
+ if (db3) printf("Inserting boot size 0x%x at 0x%x.\n",
+ (unsigned int) *(udword*)(&buf[SIZE_POS]),
+ (unsigned int)&buf[SIZE_POS]);
+
+ if (*(udword*)&buf[ADDR_POS] != ADDR_PATTERN) {
+ printf("Bootloader corrupt. Should contain ret/nop (0x%8.8x) at 0x%x, but contains %x\n",
+ ADDR_PATTERN, ADDR_POS, *(udword*)&buf[ADDR_POS]);
+ exit(EXIT_FAILURE);
+ }
+
+ if (netBoot) {
+ *(udword*)(&buf[ADDR_POS]) = BOOT_ADDRESS + DATA_SIZE;
+ }
+ else {
+ *(udword*)(&buf[ADDR_POS]) = BOOT_ADDRESS-4 + 784;
+ }
+
+ if (db3) printf("Inserting boot address 0x%x at 0x%x.\n",
+ (unsigned int)*(udword*)(&buf[ADDR_POS]),
+ (unsigned int)&buf[ADDR_POS]);
+
+
+ for (i = 0; i != st.st_size; i++) {
+ sum += ((byte*)buf)[i];
+ }
+ if (db1) printf("Checksum 0x%x, bytes %d\n", sum, i);
+
+ if (db4) {
+ int i;
+
+ for(i=0; i<st.st_size; i+=8) {
+ int j;
+
+ printf("0x%8.8x[%4.4x]: ", BOOT_ADDRESS+i, i);
+ for(j=0; i+j<st.st_size && j<8; j++) {
+ printf("%2.2x ", (unsigned char) buf[i+j]);
+ }
+ printf("\n");
+ }
+ }
+ /* Now create list of packets. */
+ while (buf_cnt <= st.st_size) {
+
+ header_size = seq_nr == 0 ?
+ SIZE_OF_FIRST_HEADER : sizeof(struct packet_header_T);
+
+ if (netBoot) {
+ packet_size = ((st.st_size - buf_cnt) < DATA_SIZE ?
+ st.st_size - buf_cnt : DATA_SIZE) + header_size;
+ }
+ else {
+ packet_size = st.st_size;
+ header_size = 0;
+ }
+
+ if (db4) printf("seq_nr %d, header_size %d, packet_size %d\n",
+ seq_nr, header_size, packet_size);
+
+ last_packet = allocate_packet(last_packet);
+
+ first_packet = first_packet ? first_packet : last_packet;
+
+ last_packet->size = packet_size;
+ last_packet->data = (char*)malloc(packet_size);
+ last_packet->seq = seq_nr;
+ last_packet->baud_rate = 9600;
+
+ last_packet->boot_file = allocate_boot_file(NULL);
+ last_packet->boot_file->fileName = boot_loader_file;
+
+ // printf("last_packet->size %8.8x\n", last_packet->size);
+ // printf("last_packet->data %8.8x\n",last_packet->data);
+
+ if (netBoot) {
+ ph = (struct packet_header_T*) last_packet->data;
+ memcpy(ph->dest, dst_addr_of_device, 6);
+ memcpy(ph->src, eth_addr_local, 6);
+ ph->length = htons(packet_size);
+ ph->snap1 = htonl(SNAP1);
+ ph->snap2 = htonl(SNAP2);
+ ph->tag = htonl(SERVER_TAG);
+ ph->seq = htonl(seq_nr);
+ if (seq_nr != 0) {
+ ph->type = htonl(BOOT_PACKET);
+ ph->id = htonl(0);
+ }
+ }
+
+ memcpy(&last_packet->data[header_size], &buf[buf_cnt],
+ packet_size - header_size);
+ if (db3) DecodeSvintoBoot(last_packet->data);
+
+ if (netBoot) {
+ buf_cnt += DATA_SIZE;
+ }
+ else {
+ buf_cnt += packet_size +1;
+ }
+
+ seq_nr++;
+ }
+ }
+
+ if (db4) printf("< CreateBootLoader\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: allocate_packet
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+struct packet_buf*
+allocate_packet(struct packet_buf *p)
+{
+ if (db4) printf("> allocate_packet\n");
+
+ if (p) {
+ p->next = (struct packet_buf*) malloc(sizeof(struct packet_buf));
+ p = p->next;
+ }
+ else {
+ p = (struct packet_buf*) malloc(sizeof(struct packet_buf));
+ }
+ p->next = NULL;
+
+ return(p);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: allocate_boot_file
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+struct boot_files_T*
+allocate_boot_file(struct boot_files_T *bf)
+{
+ if (bf) {
+ bf->next = (struct boot_files_T*) malloc(sizeof(struct boot_files_T));
+ bf = bf->next;
+ }
+ else {
+ bf = (struct boot_files_T*) malloc(sizeof(struct boot_files_T));
+ }
+ bf->next = NULL;
+
+ return(bf);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: CreateBootCmds
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Creates a boot packet from the boot commands. The data is
+*# filled in later by FinishBootCmds().
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980818 ronny Initial version
+*#***************************************************************************/
+
+void
+CreateBootCmds(void)
+{
+ struct packet_header_T *ph;
+
+ if (db4) printf("***> CreateBootCmds\n");
+
+ last_packet = allocate_packet(last_packet);
+
+ boot_cmds_packet = last_packet;
+
+ last_packet->boot_file = allocate_boot_file(NULL);
+ last_packet->boot_file->fileName = BOOT_CMDS_FILE;
+ last_packet->baud_rate = 9600;
+
+ last_packet->size = netBoot ? SIZE_OF_BOOT_CMDS + sizeof(struct packet_header_T)
+ : SIZE_OF_BOOT_CMDS;
+
+ last_packet->data = (char *) malloc(last_packet->size);
+ last_packet->seq = seq_nr;
+
+ if (netBoot) {
+ /* Create packet header. */
+ ph = (struct packet_header_T *) last_packet->data;
+ memcpy(ph->dest, dst_addr_of_device, 6);
+ memcpy(ph->src, eth_addr_local, 6);
+ ph->length = htons(last_packet->size);
+ ph->snap1 = htonl(SNAP1);
+ ph->snap2 = htonl(SNAP2);
+ ph->tag = htonl(SERVER_TAG);
+ ph->seq = htonl(seq_nr);
+ seq_nr++;
+ ph->type = htonl(BOOT_CMDS);
+ ph->id = htonl(0);
+ }
+
+ if (db3) DecodeSvintoBoot(last_packet->data);
+ if (db4) printf("<*** CreateBootCmds\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: FinishBootCmds
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Copies the boot commands into the correct packet and changes
+*# the dwords to network order.
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+void
+FinishBootCmds(void)
+{
+ int i;
+ unsigned int offset = 0;
+
+ for (i = 0; i != boot_cmds_cnt; i++) {
+ boot_cmds[i] = htonl(boot_cmds[i]);
+ if (db3) printf("%8.8x\n", boot_cmds[i]);
+ }
+
+ /* Copy boot commands into packet. */
+ if (netBoot) {
+ offset = sizeof(struct packet_header_T);
+ }
+
+ memcpy(&boot_cmds_packet->data[offset], boot_cmds,
+ boot_cmds_cnt * sizeof(udword));
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: CreateNewBootPacket
+*#
+*# PARAMETERS: None.
+*#
+*# DESCRIPTION: Creates next packet for the files specified by '--file'.
+*#
+*# RETURNS: Next packet, or NULL.
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960909 ronny Initial version
+*#***************************************************************************/
+
+struct packet_buf*
+CreateNewBootPacket(void)
+{
+ static char buf[DATA_SIZE];
+ struct packet_header_T *ph;
+ int packet_size;
+ int header_size;
+ int i;
+ udword sum;
+ int size = 0;
+ int padding = 0;
+
+ static struct boot_files_T *bf = NULL;
+
+ if (db3) printf("> CreateNewBootPacket\n");
+
+ bf = bf ? bf : first_boot_file;
+
+ while (bf) {
+ if (!bf->fd) {
+ if (strcmp(bf->fileName, "-") == 0) {
+ bf->fd = stdin;
+ }
+ else {
+ bf->fd = fopen(bf->fileName, "rb");
+ }
+
+ if (bf->fd == NULL) {
+ printf("Cannot open boot file %s. Exiting\n", bf->fileName);
+ exit(EXIT_FAILURE);
+ }
+ if (db3) printf("Opening boot file %s\n", bf->fileName);
+ }
+
+ if (!padding) {
+ size = fread(buf, 1, DATA_SIZE, bf->fd);
+ if (size == 0) {
+ if (db3) printf("Nothing more to read. Read: %d/%d\n",
+ bf->size_sent, bf->size);
+ padding = 1;
+ }
+ }
+
+ if (padding) {
+ if (bf->size_sent < bf->size) {
+ if (db3) printf("padding...\n");
+ size = (bf->size - bf->size_sent > DATA_SIZE) ?
+ DATA_SIZE : bf->size - bf->size_sent;
+ memset(buf, 0, size);
+ }
+ else {
+ if (db3) printf("All written\n");
+ padding = 0;
+ size = 0;
+ }
+ }
+
+ if (size != 0) {
+ if (db3) printf("size: %d %d/%d\n", size, bf->size_sent, bf->size);
+ bf->size_sent += size;
+ last_packet = allocate_packet(last_packet);
+
+ /* Calculate checksum. */
+ sum = 0;
+ for (i = 0; i != size; i++) {
+ sum += ((byte*)buf)[i];
+ }
+ if (db2) printf("Checksum 0x%x, bytes %d\n", sum, i);
+
+ /* Figure out size of packet. */
+ if (netBoot) {
+ header_size = seq_nr == 0 ?
+ SIZE_OF_FIRST_HEADER : sizeof(struct packet_header_T);
+
+ packet_size = ((size) < DATA_SIZE ? size : DATA_SIZE) + header_size;
+ }
+ else {
+ header_size = 0;
+ packet_size = size;
+ }
+
+ if (packet_size < 60) { /* CRC adds 4 bytes to 64 */
+ printf(
+ "Last packet from file '%s', is smaller than 64 bytes. \n"
+ "This is not allowed in the Ethernet standard. Will pad with %d "
+ "bytes.\n", bf->fileName, 60-packet_size);
+
+ *(bf->size_p) += 60-packet_size;
+ packet_size = 60;
+ }
+
+ last_packet->size = packet_size;
+ last_packet->data = (char*)malloc(packet_size);
+ last_packet->boot_file = bf;
+ last_packet->baud_rate = 0;/*set_baudrate;*/
+
+ /* printf("size %8.8x\n", last_packet->size);*/
+ /* printf("data %8.8x\n",last_packet->data);*/
+
+ if (netBoot) {
+ /* Initialize ethernet header. */
+ ph = (struct packet_header_T*) last_packet->data;
+ memcpy(ph->dest, dst_addr_of_device, 6);
+ memcpy(ph->src, eth_addr_local, 6);
+ /* printf("packet_size %d\n", packet_size);*/
+ ph->length = htons(packet_size);
+ ph->snap1 = htonl(SNAP1);
+ ph->snap2 = htonl(SNAP2);
+ ph->tag = htonl(SERVER_TAG);
+ ph->seq = htonl(seq_nr);
+ last_packet->seq = seq_nr;
+ if (seq_nr != 0) {
+ ph->type = htonl(BOOT_PACKET);
+ ph->id = htonl(0); /* id doesn't matter, we send to a unicast address */
+ }
+ }
+
+ /* Copy data in place. */
+ memcpy(&last_packet->data[header_size], buf, packet_size - header_size);
+ if (db2) DecodeSvintoBoot(last_packet->data);
+ /* PrintPacket(last_packet->data, last_packet->size, HEX);*/
+ seq_nr++;
+
+ if (db3) printf("< CreateNewBootPacket\n");
+ return(last_packet);
+ }
+ else { /* Nothing read from fd. */
+ fclose(bf->fd);
+ bf = bf->next;
+ }
+ }
+
+ if (db3) printf("< CreateNewBootPacket\n");
+ return(NULL);
+}
+
+/****************** END OF FILE common.c ************************************/
diff --git a/package/etrax-tools/src/e100boot/sbl/win32/network.c b/package/etrax-tools/src/e100boot/sbl/win32/network.c
new file mode 100755
index 000000000..7ea557627
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sbl/win32/network.c
@@ -0,0 +1,681 @@
+/*!***************************************************************************
+*!
+*! FILE NAME : network.c
+*!
+*! DESCRIPTION: Network boot stuff for e100boot.
+*!
+*! ---------------------------------------------------------------------------
+*! HISTORY
+*!
+*! DATE NAME CHANGES
+*! ---- ---- -------
+*! 1996 Ronny Raneup Initial version
+*! 2002 05 02 Ronny Ranerup Moved it into this file
+*! ---------------------------------------------------------------------------
+*! (C) Copyright 1999, 2000, 2001, 2002 Axis Communications AB, LUND, SWEDEN
+*!***************************************************************************/
+
+/************************** Include files ********************************/
+
+#include <stdio.h>
+#define WIN32_LEAN_AND_MEAN
+#include <windows.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <ctype.h>
+#include <sys/timeb.h>
+#include <winsock2.h>
+
+#include <pcap.h>
+#include <Packet32.h>
+#include <Ntddndis.h>
+
+#include <e100boot.h>
+#include <common.h>
+#include <network.h>
+
+/************************** Constants and macros *************************/
+
+#define CRC_LEN 4
+
+/************************** Type definitions *****************************/
+
+/************************** Global variables *****************************/
+
+udword highest_ack_received;
+udword last_ack_received = -1;
+int new_ack = FALSE;
+int got_new_packet = FALSE;
+
+unsigned char dst_addr_of_device[] = { 0x01, 0x40, 0x8c, 0x00, 0x01, 0x00 };
+unsigned char src_addr_of_device[] = { 0x02, 0x40, 0x8c, 0x00, 0x01, 0x00 };
+unsigned char eth_addr_local[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+struct sockaddr sock_addr;
+int pPacket = 0;
+pcap_t *pd;
+
+pcap_handler handler;
+
+struct packet_buf first_rec_packet;
+struct packet_buf *last_rec_packet = &first_rec_packet;
+
+int promisc = 1; /* promiscuous mode */
+int all_ids = TRUE;
+
+int both_addresses = FALSE;
+int p_packet_bpl = 8;
+int printPacketType = CHAR;
+
+unsigned int id;
+int one_id_only = TRUE;
+
+unsigned char buf[16000]; /* pcap buffer */
+
+const struct pcap_pkthdr *hdrG;
+
+char host1[MAX_STRING_LEN]; /* name of ethernet host */
+char host2[MAX_STRING_LEN]; /* name of ethernet host */
+
+/************************** Function prototypes **************************/
+
+int gettimeofday (struct timeval *tv, void*);
+int timeout (struct timeval *tvThen, int ms);
+int highest_seq_received (void);
+struct packet_buf* ack_on_seq (int seq);
+struct packet_buf* packet_with_seq (int seq);
+struct timeval timeval_subtract (struct timeval *x, struct timeval *y);
+void GetNextPacket (void);
+void PrintPacket (const unsigned char *p, int size, int type);
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: net_init
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2002 05 02 ronny Initial version
+*#
+*#***************************************************************************/
+void
+net_init(void)
+{
+ pcap_if_t* alldevs;
+ pcap_if_t* d;
+ char errbuf[PCAP_ERRBUF_SIZE];
+ LPADAPTER pAdapter;
+ char pOidDataBuf[sizeof(PACKET_OID_DATA)-1+sizeof(eth_addr_local)];
+ PPACKET_OID_DATA pOidData;
+
+ if (strlen(device) == 0) {
+ /* Retrieve the device list */
+ if (pcap_findalldevs(&alldevs, errbuf) == -1) {
+ fprintf(stderr,"Error finding devices: %s\n", errbuf);
+ exit(EXIT_FAILURE);
+ }
+
+ if (alldevs == NULL) {
+ printf("\nNo network adapters found!\n");
+ exit(EXIT_FAILURE);
+ }
+
+ /* Use first device/interface */
+ d = alldevs;
+ if (db1) printf("Using device %s (%s)\n", d->name,
+ (d->description ? d->description :
+ "No description available"));
+ strcpy(device, d->name);
+ pcap_freealldevs(alldevs);
+ }
+
+ if ((pd = pcap_open_live(device, 200, promisc, -1, errbuf)) == NULL) {
+ printf("Error opening device %s\n", errbuf);
+ exit(EXIT_FAILURE);
+ }
+
+ /* Determine Ethernet address */
+ if ((pAdapter = PacketOpenAdapter(device)) == NULL) {
+ printf("Error opening packet adapter!\n");
+ exit(EXIT_FAILURE);
+ }
+
+ pOidData = &pOidDataBuf[0];
+ pOidData->Oid = OID_802_3_CURRENT_ADDRESS;
+ pOidData->Length = sizeof(eth_addr_local);
+ if (!PacketRequest(pAdapter, FALSE, pOidData)) {
+ printf("Error obtaining adapter Ethernet address!\n");
+ exit(EXIT_FAILURE);
+ }
+
+ PacketCloseAdapter(pAdapter);
+ pAdapter = NULL;
+
+ memcpy(eth_addr_local, pOidData->Data, sizeof(eth_addr_local));
+ if (db1) printf("Ethernet adress for device is %2.2x-%2.2x-%2.2x-%2.2x-%2.2x-%2.2x\n",
+ eth_addr_local[0],
+ eth_addr_local[1],
+ eth_addr_local[2],
+ eth_addr_local[3],
+ eth_addr_local[4],
+ eth_addr_local[5]);
+
+ handler = (pcap_handler) Handler;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: NetBoot
+*#
+*# DESCRIPTION: The main network boot routine.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000 01 07 ronny Initial version
+*# 2002 05 02 ronny Fixed segv bug
+*#
+*#***************************************************************************/
+
+void
+NetBoot(void)
+{
+ struct packet_buf *p;
+ struct timeval tv;
+
+ gettimeofday(&tv, NULL);
+
+ p = create_packet(0);
+ SendToDevice(p->data, p->size);
+
+ while(1) {
+ static int all_trans = FALSE;
+
+ if (got_new_packet) {
+ got_new_packet = FALSE;
+
+ if (new_ack && first_packet) {
+ if (db4) {
+ printf("* got ACK %d.\n", last_ack_received);
+ printf("* ACK wanted %d.\n", first_packet->seq);
+ }
+ if (last_ack_received == first_packet->seq) {
+ if (!(p = create_packet(first_packet->seq+1))) {
+ //break;
+ }
+ first_packet = free_packet(first_packet);
+ }
+ }
+ }
+
+ if (new_ack || timeout(&tv, 500)) {
+ if (p) {
+ SendToDevice(p->data, p->size);
+ }
+ new_ack = FALSE;
+ gettimeofday(&tv, NULL);
+ }
+
+ GetNextPacket();
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetNextPacket
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+GetNextPacket(void)
+{
+ int ret;
+
+ if (db2) printf("> GetNextPacket\n");
+
+ /* got_new_packet = FALSE;*/
+ if ((ret = pcap_dispatch(pd, 1, handler, buf)) == -1) {
+ pcap_perror(pd, "Error in pcap_dispatch");
+ exit(EXIT_FAILURE);
+ }
+
+ if (db2) printf("< GetNextPacket\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: Handler
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+Handler(unsigned char *buf, const struct pcap_pkthdr *hdr,
+ const unsigned char *p)
+{
+ const unsigned char *src = &p[6];
+ const unsigned char *dst = &p[0];
+ struct packet_header_T *h = (struct packet_header_T*)p;
+
+ if (db2) printf("> Handler\n");
+ got_new_packet = TRUE;
+ if ((!memcmp(src, eth_addr_local, 6) && !memcmp(dst, dst_addr_of_device, 6))
+ || (!memcmp(src, src_addr_of_device, 6) && !memcmp(dst, eth_addr_local, 6))) {
+ if (db1) printf("#RX######################################################\n");
+ if (db1) printf("Length: %u(0x%x)\n", (udword)hdr->len, (udword)hdr->len);
+ if (pPacket) PrintPacket(p, hdr->caplen, printPacketType);
+ DecodeSvintoBoot(p);
+ /* should clean up this... */
+ if ((ntohl(h->type) == ACK)) {
+ if (all_ids || (ntohl(h->id) == id)) {
+ if (all_ids && one_id_only) {
+ if (ntohl(h->id) == 0) {
+ all_ids = FALSE;
+ id = ntohl(h->id);
+ printf("Booting device with random id %8.8x.\n", id);
+ }
+ }
+ }
+ else {
+ printf("Got ACK from a new id, %8.8lx. Ignoring.\n",
+ (unsigned long)ntohl(h->id));
+ return;
+ }
+ new_ack = TRUE;
+ last_ack_received = ntohl(h->seq);
+ if (last_ack_received > highest_ack_received) {
+ highest_ack_received = last_ack_received;
+ }
+ }
+
+ if (db1) printf("#########################################################\n");
+
+ }
+ if (db2) printf("< Handler\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: ack_on_seq
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980817 ronny Initial version
+*#
+*#***************************************************************************/
+
+struct packet_buf *
+packet_with_seq(int seq)
+{
+ static int last_seq = 0;
+ struct packet_buf *p = first_packet;
+ struct packet_header_T *h;
+
+ if (seq < last_seq) {
+ p = first_packet;
+ }
+
+ while(p) {
+ h = (struct packet_header_T*)p->data;
+ if (ntohl(h->seq) == seq) {
+ return(p);
+ }
+ p = p->next;
+ }
+ return(NULL);
+}
+
+struct packet_buf *
+ack_on_seq(int seq)
+{
+ struct packet_buf *p = &first_rec_packet;
+ struct packet_header_T *h;
+
+ if (db1) printf("***> ack_on_seq: %d.\n", seq);
+
+ while (p) {
+ /* printf("\nPacket at %x.\n", p);*/
+ /* DecodeSvintoBoot(p->data);*/
+ h = (struct packet_header_T*)p->data;
+ if ( (ntohl(h->type) == ACK) && (ntohl(h->seq) == seq) ) {
+ if (all_ids || ntohl(h->id) == id) {
+ printf("***< ack_on_seq %d, ok.\n", seq);
+ return(p);
+ }
+ }
+ p = p->next;
+ }
+ if (db1) printf("***< ack_on_seq, no.\n");
+ return(NULL);
+}
+
+int
+highest_seq_received(void)
+{
+ struct packet_buf *p = &first_rec_packet;
+ struct packet_header_T *h;
+ int highest_seq = -1;
+
+ if (db1) printf("***> highest_seq_received\n");
+
+ while (p) {
+ /* printf("\nPacket at %x.\n", p);*/
+ /* DecodeSvintoBoot(p->data);*/
+ h = (struct packet_header_T*)p->data;
+ if ((ntohl(h->type) == ACK) && (all_ids || (ntohl(h->id) == id))) {
+ if ((int)ntohl(h->seq) > highest_seq) {
+ highest_seq = ntohl(h->seq);
+ if (db4) printf("Highest seq: %d\n", highest_seq);
+ }
+ }
+ p = p->next;
+ }
+
+ if (db1) printf("***< highest_seq_received: %d\n", highest_seq);
+ return(highest_seq);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: PrintPacket
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+PrintPacket(const unsigned char *p, int size, int type)
+{
+ int i;
+
+ /* printf("size %d\n", size);*/
+ for (i = 0; i != size; i++) {
+ if (i % p_packet_bpl == 0)
+ printf("\n%-4.4d: ", i);
+ if (type == UDEC)
+ printf("%-3d ", p[i]);
+ else if (type == HEX)
+ printf("%-2.2x ", p[i]);
+ else if (type == CHAR) {
+ if (isprint(p[i]))
+ printf("%-3c ", p[i]);
+ else
+ printf("%-3d ", p[i]);
+ }
+ else if (type == ASCII) {
+ if (isprint(p[i]))
+ printf("%c", p[i]);
+ else
+ printf(".");
+ }
+ }
+ printf("\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: DecodeSvintoBoot
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION: Decodes packets that follow the e100boot protocol.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961022 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+DecodeSvintoBoot(const unsigned char *p)
+{
+ char *str;
+ volatile struct packet_header_T *ph = (struct packet_header_T*)p;
+
+ /* printf("size %d \n", sizeof(struct packet_header_T));*/
+
+ if (db4) printf("\n>DecodeSvintoBoot. Packet at 0x%x\n", (unsigned int)p);
+ if (db1) {
+ printf("%2.2x-%2.2x-%2.2x-%2.2x-%2.2x-%2.2x -> ", p[6],p[7],p[8],p[9],p[10], p[11]);
+ printf("%2.2x-%2.2x-%2.2x-%2.2x-%2.2x-%2.2x\n", p[0],p[1],p[2],p[3],p[4], p[5]);
+
+ printf("length : %4.4lx\n", (long)ntohs(ph->length));
+ printf("snap1 : %8.8lx\n", (long)ntohl(ph->snap1));
+ printf("snap2 : %8.8lx\n", (long)ntohl(ph->snap2));
+
+ switch (ntohl(ph->tag)) {
+ case 0xffffffff:
+ str = "(host > ETRAX)";
+ break;
+ case 0xfffffffe:
+ str = "(host < ETRAX)";
+ break;
+ default:
+ str = "(unknown)";
+ break;
+ }
+ printf("tag : %8.8lx %s\n", (unsigned long)ntohl(ph->tag), str);
+ printf("seq : %8.8lx\n", (unsigned long)ntohl(ph->seq));
+ }
+
+ switch (ntohl(ph->type)) {
+
+ case STRING:
+ str = "(STRING)";
+ fprintf(stderr, "%s", &p[sizeof(struct packet_header_T)]);
+ find_string((char*)&p[sizeof(struct packet_header_T)]);
+ break;
+
+ case NET_INT: {
+ char search_str[20];
+
+ str = "(NET_INT)";
+ sprintf(search_str, "0x%8.8lx", ntohl(*(udword*)&p[sizeof(struct packet_header_T)]));
+ fprintf(stderr, search_str);
+ find_string(search_str);
+ break;
+ }
+
+ case NET_INT_NL: {
+ char search_str[20];
+
+ str = "(NET_INT_NL)";
+ sprintf(search_str, "0x%8.8lx\n", ntohl(*(udword*)&p[sizeof(struct packet_header_T)]));
+ fprintf(stderr, search_str);
+ find_string(search_str);
+ break;
+ }
+
+ case ACK:
+ str = "(ACK)";
+ break;
+
+ case BOOT_PACKET:
+ str = "(bootpacket)";
+ break;
+
+ case BOOT_CMDS:
+ str = "(bootcmds)";
+ break;
+
+ default:
+ str = "(unknown)";
+ break;
+ }
+
+ if (db1) {
+ printf("(type : %8.8lx %s)\n", (unsigned long)ntohl(ph->type), str);
+ printf("(id : %8.8lx)\n", (unsigned long)ntohl(ph->id));
+ id = ntohl(ph->id);
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SendToDevice
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980818 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+SendToDevice(unsigned char *data, int data_len)
+{
+ char fName[MAX_STRING_LEN];
+ FILE *fd;
+ struct packet_header_T *h = (struct packet_header_T*) data;
+
+ if (db1) printf("***> SendToDevice\n");
+
+ if (db2) printf("Sending %d bytes at 0x%x to %s.\n", data_len, (unsigned int)data, device);
+ if (db1) printf("#TX######################################################\n");
+ if (db1) DecodeSvintoBoot(data);
+
+ if (db1) printf("#########################################################\n");
+ if (toFiles || cmdsOnly) {
+ if (cmdsOnly) { /* use a simpler name */
+ sprintf(fName, "e100boot.cmds");
+ }
+ else {
+ sprintf(fName, "e100boot.seq%lu", (unsigned long)ntohl(h->seq));
+ }
+ if (db2) printf("Writing packet to file '%s'.\n", fName);
+ if ((fd = fopen(fName, "w+")) == NULL) {
+ printf("Cannot open/create '%s'. %s.\n", fName, strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ fwrite(data, data_len, 1, fd);
+ fclose(fd);
+ }
+ else if (pcap_sendpacket(pd, data, data_len) < 0) {
+ perror("pcap_sendpacket failed!\n");
+ exit(EXIT_FAILURE);
+ }
+
+ if (db1) printf("<*** SendToDevice\n");
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: timeout
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 980817 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+timeout(struct timeval *tvThen, int ms)
+{
+ struct timeval tvNow;
+ struct timeval tvDiff;
+
+ (void) gettimeofday(&tvNow, NULL);
+ tvDiff = timeval_subtract(&tvNow, tvThen);
+ if (db4) printf("sec %d.%d\n", (int)tvDiff.tv_sec, (int)tvDiff.tv_usec);
+ if (ms * 1000 < (tvDiff.tv_sec * 1000000 + tvDiff.tv_usec)) {
+ if (db4) printf("TIMEOUT\n");
+ return(TRUE);
+ }
+
+ return(FALSE);
+}
+
+/****************************************************************************
+ *#
+ *# FUNCTION NAME: timeval_subtract
+ *#
+ *# PARAMETERS:
+ *#
+ *# DESCRIPTION: Subtract x-y, and return result.
+ *#
+ *# DATE NAME CHANGES
+ *# ---- ---- -------
+ *# 970128 ronny Initial version
+ *#
+ *#***************************************************************************/
+
+struct timeval
+timeval_subtract(struct timeval *x, struct timeval *y)
+{
+ struct timeval diff;
+
+ diff.tv_sec = x->tv_sec - y->tv_sec;
+ diff.tv_usec = x->tv_usec - y->tv_usec;
+
+ if (diff.tv_usec < 0) {
+ diff.tv_sec--;
+ diff.tv_usec = 1000000 + diff.tv_usec;
+ }
+
+ return diff;
+}
+
+int
+gettimeofday(struct timeval *tv, void* tz_void)
+{
+ struct _timeb tb;
+ _ftime(&tb);
+ tv->tv_sec = tb.time;
+ tv->tv_usec = tb.millitm * 1000;
+ return 0;
+}
diff --git a/package/etrax-tools/src/e100boot/sendserial/Makefile b/package/etrax-tools/src/e100boot/sendserial/Makefile
new file mode 100644
index 000000000..e47179ebe
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sendserial/Makefile
@@ -0,0 +1,3 @@
+
+sendserial: sendserial.c
+ gcc -Wall -g -o sendserial sendserial.c
diff --git a/package/etrax-tools/src/e100boot/sendserial/sendserial.c b/package/etrax-tools/src/e100boot/sendserial/sendserial.c
new file mode 100644
index 000000000..4767bfd84
--- /dev/null
+++ b/package/etrax-tools/src/e100boot/sendserial/sendserial.c
@@ -0,0 +1,769 @@
+#include <termios.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <signal.h>
+#include <fcntl.h>
+#include <string.h>
+#include <ctype.h>
+
+#define TRUE 1
+#define FALSE 0
+
+#define db1 0
+#define db2 0
+#define db3 0
+#define db4 0
+
+#define XON ('')
+#define XOFF ('')
+
+#define START_STR_SIZE 100
+#define SERIAL_BUF_SIZE 1
+
+int GetNumberOption (int *argNr, int argCount, char *argVect[], int *ret, char *option);
+int GetStringOption (int *argNr, int argCount, char *argVect[], char *ret, char *option);
+int WaitForRead (int s, int usecs);
+int WaitForWrite (int s, int usecs);
+int SetupSerial ();
+int SetInputMode (FILE *fd, int value, int onoff);
+int SetControlMode (FILE *fd, int value, int onoff);
+int SetLocalMode (FILE *fd, int value, int onoff);
+void ParseArgs (int argc, char *argv[]);
+
+FILE *modemFd;
+char dev[100] = "/dev/ttyS0";
+char filename[100] = "";
+char serial_buf[SERIAL_BUF_SIZE];
+int baudRates[] = {0, 50, 75, 110, 134, 150, 200, 300, 600,
+ 1200, 1800, 2400, 4800, 9600, 19200, 38400, 57600, 115200};
+int check = FALSE;
+int dotime = FALSE;
+int got_start = TRUE;
+int loop = FALSE;
+int crtcts = FALSE;
+int do_print = TRUE;
+int received;
+int set_baudrate = 9600;
+int xonxoff = FALSE;
+struct timeval start;
+struct timeval stop;
+
+
+int
+main(int argc, char *argv[])
+{
+ FILE *fd;
+ char *buf;
+ int ret;
+ struct stat st;
+
+ ParseArgs(argc, argv);
+ SetupSerial();
+
+ if (strcmp(filename, "") != 0) {
+
+ /* Read file. */
+ if ((fd = fopen(filename, "r")) == NULL) {
+ perror("Can't open file\n");
+ exit(0);
+ }
+
+ if (fstat(fileno(fd), &st) != 0) {
+ perror("stat failed\n");
+ exit(0);
+ }
+
+ buf = malloc(st.st_size);
+ if (fread(buf, 1, st.st_size, fd) != st.st_size) {
+ printf("fread failed\n");
+ }
+
+ fclose(fd);
+
+ printf("# sendserial transmitting %d bytes at baudrate %d.\n", (int)st.st_size, set_baudrate);
+ printf("# transmitting...\n");
+ /* Write file. */
+ {
+ int tr_len = 0;
+ int rec_len = 0;
+ char rec_buf[1000];
+ int connected = 0;
+
+ // while (tr_len != st.st_size) {
+ while (1) {
+ if (WaitForRead(fileno(modemFd), 0)) {
+ if((rec_len = fread(rec_buf, 1, 1, modemFd)) > 0) {
+ if (!connected++) {
+ printf("# connected!\n");
+ }
+ fwrite(rec_buf, rec_len, 1, stdout);
+ }
+ }
+ if (tr_len < st.st_size) {
+ while (!(WaitForWrite(fileno(modemFd), 1000000))) { }
+ fwrite(&buf[tr_len], 1, 1, modemFd);
+ tr_len++;
+ }
+ else if (tr_len++ == st.st_size) {
+ printf("# ...transmission done.\n");
+ }
+ }
+ }
+
+ exit(0);
+
+ do {
+ ret = fwrite(buf, 1, st.st_size, modemFd);
+ printf("Wrote %d bytes of %d.\n", ret, (int)st.st_size);
+ } while(loop);
+ }
+
+ {
+ int rec_len = 0;
+ char rec_buf[1000];
+
+ while (loop) {
+ if (WaitForRead(fileno(modemFd), 1000000)) {
+ if((rec_len = fread(rec_buf, 1, 1, modemFd)) > 0) {
+ fwrite(rec_buf, rec_len, 1, stdout);
+ }
+ }
+ }
+ }
+
+ return 1;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: ParseArgs
+*#
+*# PARAMETERS: argc,argv
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*#
+*#***************************************************************************/
+
+void
+ParseArgs (int argc, char *argv[])
+{
+ int argi;
+
+ for (argi=1; argi < argc; argi++) {
+
+ if (strncmp(argv[argi], "--xonxoff", 9) == 0) {
+ printf("xonxoff\n");
+ xonxoff = TRUE;
+ }
+
+ else if (strncmp(argv[argi], "--crtcts", 8) == 0) {
+ printf("crtcts\n");
+ crtcts = TRUE;
+ }
+
+ else if (strncmp(argv[argi], "--loop", 6) == 0) {
+ printf("loop\n");
+ loop = TRUE;
+ }
+
+ else if (strncmp(argv[argi], "--time", 6) == 0) {
+ dotime = TRUE;
+ got_start = FALSE;
+ }
+
+ else if (strncmp(argv[argi], "--check", 6) == 0) {
+ check = TRUE;
+ }
+
+ else if (strncmp(argv[argi], "--noprint", 9) == 0) {
+ do_print = FALSE;
+ }
+
+ else if (strncmp(argv[argi], "--device", 8) == 0) {
+ if (GetStringOption (&argi, argc, argv, dev, "--device") == 0) {
+ printf("--device name\n");
+ exit(0);
+ }
+ }
+
+ else if (strncmp(argv[argi], "--file", 6) == 0) {
+ if (GetStringOption (&argi, argc, argv, filename, "--file") == 0) {
+ printf("--file name\n");
+ exit(0);
+ }
+ }
+
+ else if (strncmp(argv[argi], "--baudrate", 10) == 0) {
+ if (GetNumberOption (&argi, argc, argv, &set_baudrate, "--baudrate") == 0) {
+ printf("--baudrate baudrate\n");
+ exit(0);
+ }
+ }
+ else {
+ printf("'%s' unknown command\n", argv[argi]);
+ printf("\nsendserial --file fname [--device dname] [--baudrate baudrate] [--xonxoff] [--crtcts]\n\n");
+ printf("%dbps on %s default. No handshake.\n", set_baudrate, dev);
+ exit(1);
+ }
+ }
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetNumberOption
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+GetNumberOption(int *argNr, int argCount, char *argVect[], int *ret, char *option)
+{
+ int startChar = strlen(option);
+
+ if (strlen(argVect[*argNr]) <= (unsigned int) startChar) {
+ (*argNr)++;
+ startChar = 0;
+ }
+
+ if (*argNr > argCount) {
+ printf("ERROR! The option '%s' needs a number argument.\n", option);
+ return (0);
+ }
+
+ *ret = atoi(&argVect[*argNr][startChar]);
+ return (1);
+
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: GetStringOption
+*#
+*# PARAMETERS: int *argNr : Returns next argc here.
+*# int argCount : Index of last argument.
+*# char *argVect[] : argv.
+*# char *ret : Copy string here.
+*# char *option : Name of the option.
+*#
+*# DESCRIPTION: Extracts a string option from argv, and updates argnr.
+*# Returns TRUE/FALSE and string in *ret.
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 960930 ronny Initial version
+*# 961203 ronny Handles filenames with spaces within 'file name'.
+*#
+*#***************************************************************************/
+
+int
+GetStringOption(int *argNr, int argCount, char *argVect[], char *ret, char *option)
+{
+ int startChar = strlen(option);
+ char tmp[256];
+
+ strcpy(ret, "");
+
+ /* Are there any more chars after option? If not skip to next argv. */
+ if (strlen(argVect[*argNr]) <= (unsigned int)startChar) {
+ (*argNr)++;
+ startChar = 0;
+ }
+
+ /* Any args left? */
+ if (*argNr >= argCount) {
+ printf("ERROR! The option '%s' needs a string argument.\n", option);
+ return (FALSE);
+ }
+
+ strcpy(ret, &argVect[*argNr][startChar]);
+
+ if (ret[0] == '\'' || ret[0] == '\"') {
+ if (db3) printf("Inside string\n");
+ strcpy(tmp, &ret[1]);
+ do {
+ if (tmp[strlen(tmp) - 1 ] == '\'' || tmp[strlen(tmp) - 1] == '\"') {
+ tmp[strlen(tmp) - 1] = '\0';
+ break;
+ }
+
+ (*argNr)++;
+
+ if (*argNr >= argCount) {
+ printf("ERROR! Mismatched ' or \" in options.\n");
+ return (FALSE);
+ }
+
+ strcat(tmp, &argVect[*argNr][0]);
+ if (db3) printf("tmp %s\n", tmp);
+ } while (1);
+
+ strcpy(ret, tmp);
+ }
+ if (db4) printf("<<< GetStringOption %s\n", ret);
+ return (TRUE);
+
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetupSerial
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 970325 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetupSerial()
+{
+
+ struct termios ti;
+ int baudrate;
+
+ if ((modemFd = fopen(dev, "r+")) == NULL) {
+ perror("Can't open modem\n");
+ return(FALSE);
+ }
+
+ /* Important. Remember this!!!!!!! */
+ /* setvbuf(modemFd, NULL, _IONBF, 0); */
+
+ setvbuf(modemFd, NULL, _IONBF, 0);
+ setvbuf(stdout, NULL, _IONBF, 0);
+
+ if (fcntl(fileno(modemFd), F_SETFL, O_NONBLOCK) == -1) {
+ perror("fcntl: ");
+ exit(0);
+ }
+
+ tcflush(fileno(modemFd), TCIOFLUSH);
+
+ if (tcgetattr (fileno(modemFd), &ti)) {
+ perror("tcgetattr");
+ return(FALSE);
+ }
+
+ if (db4) printf("VTIME:%d\n", ti.c_cc[VTIME]);
+ if (db4) printf("VMIN:%d\n", ti.c_cc[VMIN]);
+
+ ti.c_cc[VMIN] = 1;
+ ti.c_cc[VTIME] = 0;
+ ti.c_cc[VSTART] = XON;
+ ti.c_cc[VSTOP] = XOFF;
+
+ if (tcsetattr (fileno(modemFd), TCSANOW, &ti)) {
+ perror("tcsetattr");
+ return(FALSE);
+ }
+
+ //if (db3) printf("outspeed: %d, inspeed: %d\n", baudRates[cfgetospeed(&ti)], baudRates[cfgetispeed(&ti)]);
+ {
+ int new_baudrate = 0;
+
+ if (set_baudrate <= 50) {
+ baudrate = B50;
+ new_baudrate = 50;
+ }
+ else if (set_baudrate <= 75) {
+ baudrate = B75;
+ new_baudrate = 75;
+ }
+ else if (set_baudrate <= 110) {
+ baudrate = B110;
+ new_baudrate = 110;
+ }
+ else if (set_baudrate <= 134) {
+ baudrate = B134;
+ new_baudrate = 134;
+ }
+ else if (set_baudrate <= 150) {
+ baudrate = B150;
+ new_baudrate = 150;
+ }
+ else if (set_baudrate <= 200) {
+ baudrate = B200;
+ new_baudrate = 200;
+ }
+ else if (set_baudrate <= 300) {
+ baudrate = B300;
+ new_baudrate = 300;
+ }
+ else if (set_baudrate <= 600) {
+ baudrate = B600;
+ new_baudrate = 600;
+ }
+ else if (set_baudrate <= 1200) {
+ baudrate = B1200;
+ new_baudrate = 1200;
+ }
+ else if (set_baudrate <= 1800) {
+ baudrate = B1800;
+ new_baudrate = 1800;
+ }
+ else if (set_baudrate <= 2400) {
+ baudrate = B2400;
+ new_baudrate = 2400;
+ }
+ else if (set_baudrate <= 4800) {
+ baudrate = B4800;
+ new_baudrate = 4800;
+ }
+ else if (set_baudrate <= 9600) {
+ baudrate = B9600;
+ new_baudrate = 9600;
+ }
+ else if (set_baudrate <= 19200) {
+ baudrate = B19200;
+ new_baudrate = 19200;
+ }
+ else if (set_baudrate <= 38400)
+ baudrate = B38400;
+#if defined (B57600) /* POSIX only defines >= 38400 */
+ else if (set_baudrate <= 57600) {
+ baudrate = B57600;
+ new_baudrate = 57600;
+ }
+#endif
+#if defined (B115200)
+ else if (set_baudrate <= 115200) {
+ baudrate = B115200;
+ new_baudrate = 115200;
+ }
+#endif
+#if defined (B230400)
+ else if (set_baudrate <= 230400) {
+ baudrate = B230400;
+ new_baudrate = 230400;
+ }
+#endif
+ else {
+ baudrate = B38400;
+ }
+
+ cfsetispeed(&ti, B9600);
+ cfsetospeed(&ti, baudrate);
+ tcsetattr(fileno(modemFd), TCSANOW, &ti);
+
+ // printf("* baudrate set to %d\n", new_baudrate);
+ set_baudrate = new_baudrate;
+
+ if (db3) printf("outspeed: %d, inspeed: %d\n", baudRates[cfgetospeed(&ti)], baudRates[cfgetispeed(&ti)]);
+ }
+
+ cfmakeraw(&ti);
+
+ SetInputMode(modemFd, IXON, FALSE);
+ SetInputMode(modemFd, IXOFF, xonxoff); /* input */
+ SetInputMode(modemFd, IXANY, FALSE);
+ SetInputMode(modemFd, ICRNL, FALSE);
+ SetInputMode(modemFd, IGNPAR, TRUE);
+ SetInputMode(modemFd, IGNBRK, TRUE);
+ SetInputMode(modemFd, IGNPAR, TRUE);
+ SetInputMode(modemFd, INPCK, FALSE);
+
+ SetLocalMode(modemFd, ECHO, FALSE);
+ SetLocalMode(modemFd, ISIG, FALSE);
+
+ SetLocalMode(modemFd, ICANON, FALSE);
+
+ SetControlMode(modemFd, PARENB, FALSE);
+ SetControlMode(modemFd, CLOCAL, TRUE);
+
+ /* Disable hardware flow control. */
+#if defined(CRTSCTS)
+
+ SetControlMode(modemFd, CRTSCTS, crtcts);
+#if defined(CRTSXOFF)
+ SetControlMode(modemFd, CRTSXOFF, crtcts);
+#endif
+
+#elif defined(CCTS_OFLOW)
+
+ SetControlMode(modemFd, CCTS_OFLOW, crtcts);
+ SetControlMode(modemFd, CRTS_IFLOW, crtcts);
+
+#elif defined(CNEW_RTSCTS)
+
+ SetControlMode(modemFd, CNEW_RTSCTS, crtcts);
+
+#else
+ printf("Cannot set hardware flow control. Set it manually with a terminal program.\n");
+#endif
+
+ return(TRUE);
+
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetInputMode
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 970325 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetInputMode (FILE *fd, int value, int onoff)
+{
+ struct termios settings;
+ int result;
+
+ result = tcgetattr(fileno(fd), &settings);
+ if (result < 0)
+ {
+ perror ("error in tcgetattr");
+ return (FALSE);
+ }
+
+ if (onoff)
+ settings.c_iflag |= value;
+ else
+ settings.c_iflag &= ~value;
+
+ result = tcsetattr(fileno(fd), TCSANOW, &settings);
+ if (result < 0)
+ {
+ perror ("error in tcgetattr");
+ return(FALSE);
+ }
+
+ return 1;
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetControlMode
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 970325 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetControlMode (FILE *fd, int value, int onoff)
+{
+
+#if !defined(_WIN32)
+
+ struct termios settings;
+ int result;
+
+ result = tcgetattr (fileno(fd), &settings);
+ if (result < 0)
+ {
+ perror ("error in tcgetattr");
+ return (FALSE);
+ }
+
+ if (onoff)
+ settings.c_cflag |= value;
+ else
+ settings.c_cflag &= ~value;
+
+ result = tcsetattr (fileno(fd), TCSANOW, &settings);
+ if (result < 0)
+ {
+ perror ("error in tcgetattr");
+ return(FALSE);
+ }
+
+#endif
+
+ return (TRUE);
+}
+/****************************************************************************
+*#
+*# FUNCTION NAME: SetLocalMode
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 970325 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+SetLocalMode (FILE *fd, int value, int onoff)
+{
+
+#if !defined(_WIN32)
+
+ struct termios settings;
+ int result;
+
+ result = tcgetattr (fileno(fd), &settings);
+ if (result < 0)
+ {
+ perror ("error in tcgetattr");
+ return (FALSE);
+ }
+
+ if (onoff)
+ settings.c_lflag |= value;
+ else
+ settings.c_lflag &= ~value;
+
+ result = tcsetattr (fileno(fd), TCSANOW, &settings);
+ if (result < 0)
+ {
+ perror ("error in tcgetattr");
+ return(FALSE);
+ }
+
+#endif
+
+ return (TRUE);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: WaitForRead
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 961001 ronny Initial version
+*# 971204 ronny usecs was a only one tenth of what it should be.
+*#
+*#***************************************************************************/
+
+int
+WaitForRead(int s, int usecs)
+{
+ fd_set mask;
+ int ret;
+ struct timeval tm;
+
+ tm.tv_sec = usecs/1000000;
+ tm.tv_usec = usecs%1000000;
+
+ FD_ZERO(&mask);
+ FD_SET(s, &mask);
+
+ if ((ret = select(FD_SETSIZE, &mask, NULL, NULL, &tm)) == -1) {
+ printf("<<< select failed with return: %d.\n", ret);
+ return(FALSE);
+ }
+ else {
+ if (db3) printf("* select returned OK:%d\n", ret);
+ }
+
+ if (FD_ISSET(s, &mask) == 0) {
+ if (db2) printf("<<< WaitForRead. No data to read.\n");
+ return (FALSE);
+ }
+
+ if (db3) printf("<<< WaitForRead OK. Returned:%d.\n", ret);
+
+ return(TRUE);
+}
+
+/****************************************************************************
+*#
+*# FUNCTION NAME: WaitForWrite
+*#
+*# PARAMETERS:
+*#
+*# DESCRIPTION:
+*#
+*#---------------------------------------------------------------------------
+*# HISTORY
+*#
+*# DATE NAME CHANGES
+*# ---- ---- -------
+*# 2000-11-20 ronny Initial version
+*#
+*#***************************************************************************/
+
+int
+WaitForWrite(int s, int usecs)
+{
+ fd_set mask;
+ int ret;
+ struct timeval tm;
+
+ tm.tv_sec = usecs/1000000;
+ tm.tv_usec = usecs%1000000;
+
+ FD_ZERO(&mask);
+ FD_SET(s, &mask);
+
+ if ((ret = select(FD_SETSIZE, NULL, &mask, NULL, &tm)) == -1) {
+ printf("<<< select failed with return: %d.\n", ret);
+ return(FALSE);
+ }
+ else {
+ if (db3) printf("* select returned OK:%d\n", ret);
+ }
+
+ if (FD_ISSET(s, &mask) == 0) {
+ if (db2) printf("<<< WaitForWrite. No data to read.\n");
+ return (FALSE);
+ }
+
+ if (db3) printf("<<< WaitForWrite OK. Returned:%d.\n", ret);
+
+ return(TRUE);
+}
+
diff --git a/package/etrax-tools/src/mkfimage.c b/package/etrax-tools/src/mkfimage.c
new file mode 100644
index 000000000..b1897fbd7
--- /dev/null
+++ b/package/etrax-tools/src/mkfimage.c
@@ -0,0 +1,72 @@
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+#include <string.h>
+#include <stdlib.h>
+
+int main(int argc, char **argv){
+ unsigned char *buffer = malloc(64 * 1024);
+ struct stat s;
+ unsigned int size_vmlinux = 0, real_size_vmlinux = 0;
+ const unsigned char *magic_str = "ACME_PART_MAGIC";
+ unsigned int loop;
+ unsigned char *magic;
+
+ if(argc != 3){
+ printf("%s in out\n", argv[0]);
+ return 1;
+ }
+
+ printf("Generating image\n");
+
+ FILE *vmlinux = fopen(argv[1], "r");
+ FILE *vmlinux_out = fopen(argv[2], "w");
+ if((!vmlinux) || (!vmlinux_out)){
+ printf("Error opening a file\n");
+ return 1;
+ }
+
+ stat(argv[1], &s);
+ size_vmlinux = s.st_size;
+ real_size_vmlinux = (size_vmlinux & 0xffff0000) + 0x10000;
+
+ printf("vmlinux = 0x%.08X / 0x%.08X\n", size_vmlinux, real_size_vmlinux);
+
+ unsigned int t = fread(buffer, 1, 64 * 1024, vmlinux);
+ for(loop = 0; loop < (64 * 1024) - sizeof(magic_str); loop++){
+ if(buffer[loop] == magic_str[0]){
+ if((magic = strstr(&buffer[loop], magic_str))){
+ //printf("Magic at 0x%.08X %p %p\n", magic - buffer, magic, buffer);
+ printf("Found Magic %X%X%X%X\n",
+ buffer[loop + strlen(magic_str)],
+ buffer[loop + strlen(magic_str) + 2],
+ buffer[loop + strlen(magic_str) + 1],
+ buffer[loop + strlen(magic_str) + 3]);
+
+ buffer[loop + strlen(magic_str)] = real_size_vmlinux >> 24;
+ buffer[loop + strlen(magic_str) + 2] = (real_size_vmlinux >> 16) & 0xff;
+ buffer[loop + strlen(magic_str) + 1] = (real_size_vmlinux >> 8) & 0xff;
+ buffer[loop + strlen(magic_str) + 3] = (real_size_vmlinux) & 0xff;
+
+ printf("Replaced with %.02X%.02X%.02X%.02X\n",
+ buffer[loop + strlen(magic_str)],
+ buffer[loop + strlen(magic_str) + 2],
+ buffer[loop + strlen(magic_str) + 1],
+ buffer[loop + strlen(magic_str) + 3]);
+
+ }
+ }
+ }
+
+ fwrite(buffer, 1, 64 * 1024, vmlinux_out);
+ real_size_vmlinux -= 64 * 1024;
+ do {
+ real_size_vmlinux -= 64 * 1024;
+ memset(buffer, 0, 64 * 1024);
+ fread(buffer, 1, 64 * 1024, vmlinux);
+ fwrite(buffer, 1, 64 * 1024, vmlinux_out);
+ } while (real_size_vmlinux);
+
+ return 0;
+}