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-rw-r--r--mk/kernel-ver.mk8
-rw-r--r--target/arm/cubox-i/patches/3.15-rc7/rmk.patch12452
-rw-r--r--target/arm/cubox-i/patches/3.15/rmk.patch6640
-rw-r--r--target/arm/cubox-i/patches/3.15/sdma-firmware-cubox-i.patch (renamed from target/arm/cubox-i/patches/3.15-rc7/sdma-firmware-cubox-i.patch)0
-rw-r--r--target/config/Config.in.kernelversion.choice4
-rw-r--r--target/config/Config.in.kernelversion.default2
-rw-r--r--target/linux/patches/3.15-rc8/bsd-compatibility.patch (renamed from target/linux/patches/3.15-rc7/bsd-compatibility.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/cleankernel.patch (renamed from target/linux/patches/3.15-rc7/cleankernel.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/defaults.patch (renamed from target/linux/patches/3.15-rc7/defaults.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/disable-netfilter.patch (renamed from target/linux/patches/3.15-rc7/disable-netfilter.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/export-symbol-for-exmap.patch (renamed from target/linux/patches/3.15-rc7/export-symbol-for-exmap.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/gemalto.patch (renamed from target/linux/patches/3.15-rc7/gemalto.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/initramfs-nosizelimit.patch (renamed from target/linux/patches/3.15-rc7/initramfs-nosizelimit.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/lemote-rfkill.patch (renamed from target/linux/patches/3.15-rc7/lemote-rfkill.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/microblaze-axi.patch (renamed from target/linux/patches/3.15-rc7/microblaze-axi.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/microblaze-ethernet.patch (renamed from target/linux/patches/3.15-rc7/microblaze-ethernet.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/mkpiggy.patch (renamed from target/linux/patches/3.15-rc7/mkpiggy.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/mtd-rootfs.patch (renamed from target/linux/patches/3.15-rc7/mtd-rootfs.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/nfsv3-tcp.patch (renamed from target/linux/patches/3.15-rc7/nfsv3-tcp.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/non-static.patch (renamed from target/linux/patches/3.15-rc7/non-static.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/patch-yaffs2 (renamed from target/linux/patches/3.15-rc7/patch-yaffs2)0
-rw-r--r--target/linux/patches/3.15-rc8/ppc64-missing-zlib.patch (renamed from target/linux/patches/3.15-rc7/ppc64-missing-zlib.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/relocs.patch (renamed from target/linux/patches/3.15-rc7/relocs.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/sgidefs.patch (renamed from target/linux/patches/3.15-rc7/sgidefs.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/sortext.patch (renamed from target/linux/patches/3.15-rc7/sortext.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/startup.patch (renamed from target/linux/patches/3.15-rc7/startup.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/tcp-fastopen.patch (renamed from target/linux/patches/3.15-rc7/tcp-fastopen.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/uuid.patch (renamed from target/linux/patches/3.15-rc7/uuid.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/wlan-cf.patch (renamed from target/linux/patches/3.15-rc7/wlan-cf.patch)0
-rw-r--r--target/linux/patches/3.15-rc8/xargs.patch (renamed from target/linux/patches/3.15-rc7/xargs.patch)0
-rw-r--r--target/mips/mikrotik-rb532/patches/3.15-rc7/rb532-pci.patch11
-rw-r--r--target/mips/mikrotik-rb532/patches/3.15-rc8/rb532-serial.patch (renamed from target/mips/mikrotik-rb532/patches/3.15-rc7/rb532-serial.patch)0
32 files changed, 6647 insertions, 12470 deletions
diff --git a/mk/kernel-ver.mk b/mk/kernel-ver.mk
index 0dff546b8..62184295a 100644
--- a/mk/kernel-ver.mk
+++ b/mk/kernel-ver.mk
@@ -1,8 +1,8 @@
-ifeq ($(ADK_KERNEL_VERSION_3_15_RC7),y)
-KERNEL_VERSION:= 3.15-rc7
-KERNEL_MOD_VERSION:= 3.15.0-rc7
+ifeq ($(ADK_KERNEL_VERSION_3_15),y)
+KERNEL_VERSION:= 3.15
+KERNEL_MOD_VERSION:= 3.15.0
KERNEL_RELEASE:= 1
-KERNEL_MD5SUM:= a56d456b69b2e984aea0329bed0bda4d
+KERNEL_MD5SUM:= 97ca1625bb40368dc41b9a7971549071
endif
ifeq ($(ADK_KERNEL_VERSION_3_14_5),y)
KERNEL_VERSION:= 3.14.5
diff --git a/target/arm/cubox-i/patches/3.15-rc7/rmk.patch b/target/arm/cubox-i/patches/3.15-rc7/rmk.patch
deleted file mode 100644
index 83afb1a78..000000000
--- a/target/arm/cubox-i/patches/3.15-rc7/rmk.patch
+++ /dev/null
@@ -1,12452 +0,0 @@
-diff -Nur linux-3.15-rc6.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts linux-3.15-rc6/arch/arm/boot/dts/imx6dl-hummingboard.dts
---- linux-3.15-rc6.orig/arch/arm/boot/dts/imx6dl-hummingboard.dts 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/boot/dts/imx6dl-hummingboard.dts 2014-05-23 11:26:48.244939835 +0200
-@@ -67,6 +67,14 @@
- status = "okay";
- };
-
-+&hdmi {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
-+ ddc-i2c-bus = <&i2c2>;
-+ status = "okay";
-+ crtcs = <&ipu1 0>;
-+};
-+
- &i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
-@@ -82,6 +90,13 @@
- */
- };
-
-+&i2c2 {
-+ clock-frequency = <100000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
-+ status = "okay";
-+};
-+
- &iomuxc {
- hummingboard {
- pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
-@@ -97,6 +112,12 @@
- >;
- };
-
-+ pinctrl_hummingboard_hdmi: hummingboard-hdmi {
-+ fsl,pins = <
-+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
-+ >;
-+ };
-+
- pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
-@@ -104,6 +125,13 @@
- >;
- };
-
-+ pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
-+ fsl,pins = <
-+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
-+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-+ >;
-+ };
-+
- pinctrl_hummingboard_spdif: hummingboard-spdif {
- fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
- };
-diff -Nur linux-3.15-rc6.orig/arch/arm/boot/dts/imx6q-cubox-i.dts linux-3.15-rc6/arch/arm/boot/dts/imx6q-cubox-i.dts
---- linux-3.15-rc6.orig/arch/arm/boot/dts/imx6q-cubox-i.dts 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/boot/dts/imx6q-cubox-i.dts 2014-05-23 11:26:48.244939835 +0200
-@@ -13,4 +13,8 @@
-
- &sata {
- status = "okay";
-+ fsl,transmit-level-mV = <1104>;
-+ fsl,transmit-boost-mdB = <0>;
-+ fsl,transmit-atten-16ths = <9>;
-+ fsl,no-spread-spectrum;
- };
-diff -Nur linux-3.15-rc6.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi linux-3.15-rc6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
---- linux-3.15-rc6.orig/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi 2014-05-23 11:26:48.244939835 +0200
-@@ -12,6 +12,19 @@
- pinctrl-0 = <&pinctrl_cubox_i_ir>;
- };
-
-+ pwmleds {
-+ compatible = "pwm-leds";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_cubox_i_pwm1>;
-+
-+ front {
-+ active-low;
-+ label = "imx6:red:front";
-+ max-brightness = <248>;
-+ pwms = <&pwm1 0 50000>;
-+ };
-+ };
-+
- regulators {
- compatible = "simple-bus";
-
-@@ -55,6 +68,21 @@
- };
- };
-
-+&hdmi {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_cubox_i_hdmi>;
-+ ddc-i2c-bus = <&i2c2>;
-+ status = "okay";
-+ crtcs = <&ipu1 0>;
-+};
-+
-+&i2c2 {
-+ clock-frequency = <100000>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_cubox_i_i2c2>;
-+ status = "okay";
-+};
-+
- &i2c3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_cubox_i_i2c3>;
-@@ -69,6 +97,19 @@
-
- &iomuxc {
- cubox_i {
-+ pinctrl_cubox_i_hdmi: cubox-i-hdmi {
-+ fsl,pins = <
-+ MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
-+ >;
-+ };
-+
-+ pinctrl_cubox_i_i2c2: cubox-i-i2c2 {
-+ fsl,pins = <
-+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
-+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
-+ >;
-+ };
-+
- pinctrl_cubox_i_i2c3: cubox-i-i2c3 {
- fsl,pins = <
- MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
-@@ -82,6 +123,10 @@
- >;
- };
-
-+ pinctrl_cubox_i_pwm1: cubox-i-pwm1-front-led {
-+ fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0>;
-+ };
-+
- pinctrl_cubox_i_spdif: cubox-i-spdif {
- fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
- };
-@@ -111,6 +156,28 @@
- MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
- >;
- };
-+
-+ pinctrl_cubox_i_usdhc2_100mhz: cubox-i-usdhc2-100mhz {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
-+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
-+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
-+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
-+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
-+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130b9
-+ >;
-+ };
-+
-+ pinctrl_cubox_i_usdhc2_200mhz: cubox-i-usdhc2-200mhz {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170f9
-+ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100f9
-+ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
-+ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
-+ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
-+ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x130f9
-+ >;
-+ };
- };
- };
-
-@@ -130,9 +197,19 @@
- status = "okay";
- };
-
-+&uart4 {
-+ status = "okay";
-+};
-+
-+&usdhc1 {
-+ status = "okay";
-+};
-+
- &usdhc2 {
-- pinctrl-names = "default";
-+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2>;
-+ pinctrl-1 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_100mhz>;
-+ pinctrl-2 = <&pinctrl_cubox_i_usdhc2_aux &pinctrl_cubox_i_usdhc2_200mhz>;
- vmmc-supply = <&reg_3p3v>;
- cd-gpios = <&gpio1 4 0>;
- status = "okay";
-diff -Nur linux-3.15-rc6.orig/arch/arm/boot/dts/imx6qdl.dtsi linux-3.15-rc6/arch/arm/boot/dts/imx6qdl.dtsi
---- linux-3.15-rc6.orig/arch/arm/boot/dts/imx6qdl.dtsi 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/boot/dts/imx6qdl.dtsi 2014-05-23 11:26:48.244939835 +0200
-@@ -128,6 +128,8 @@
- cache-level = <2>;
- arm,tag-latency = <4 2 3>;
- arm,data-latency = <4 2 3>;
-+ arm,dynamic-clk-gating;
-+ arm,standby-mode;
- };
-
- pcie: pcie@0x01000000 {
-diff -Nur linux-3.15-rc6.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi linux-3.15-rc6/arch/arm/boot/dts/imx6qdl-microsom.dtsi
---- linux-3.15-rc6.orig/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/boot/dts/imx6qdl-microsom.dtsi 2014-05-23 11:26:48.244939835 +0200
-@@ -1,9 +1,69 @@
- /*
- * Copyright (C) 2013,2014 Russell King
- */
-+#include <dt-bindings/gpio/gpio.h>
-+/ {
-+ regulators {
-+ compatible = "simple-bus";
-+
-+ reg_brcm_osc: brcm-osc-reg {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio5 5 0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_microsom_brcm_osc_reg>;
-+ regulator-name = "brcm_osc_reg";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ regulator-always-on;
-+ regulator-boot-on;
-+ };
-+
-+ reg_brcm: brcm-reg {
-+ compatible = "regulator-fixed";
-+ enable-active-high;
-+ gpio = <&gpio3 19 0>;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_microsom_brcm_reg>;
-+ regulator-name = "brcm_reg";
-+ regulator-min-microvolt = <3300000>;
-+ regulator-max-microvolt = <3300000>;
-+ startup-delay-us = <200000>;
-+ };
-+ };
-+};
-
- &iomuxc {
- microsom {
-+ pinctrl_microsom_brcm_osc_reg: microsom-brcm-osc-reg {
-+ fsl,pins = <
-+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x40013070
-+ >;
-+ };
-+
-+ pinctrl_microsom_brcm_reg: microsom-brcm-reg {
-+ fsl,pins = <
-+ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x40013070
-+ >;
-+ };
-+
-+ pinctrl_microsom_brcm_wifi: microsom-brcm-wifi {
-+ fsl,pins = <
-+ MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x1b0b0
-+ MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x40013070
-+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x40013070
-+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x40013070
-+ >;
-+ };
-+
-+ pinctrl_microsom_brcm_bt: microsom-brcm-bt {
-+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x40013070
-+ MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x40013070
-+ MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x40013070
-+ >;
-+ };
-+
- pinctrl_microsom_uart1: microsom-uart1 {
- fsl,pins = <
- MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
-@@ -11,6 +71,15 @@
- >;
- };
-
-+ pinctrl_microsom_uart4_1: microsom-uart4 {
-+ fsl,pins = <
-+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
-+ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
-+ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
-+ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
-+ >;
-+ };
-+
- pinctrl_microsom_usbotg: microsom-usbotg {
- /*
- * Similar to pinctrl_usbotg_2, but we want it
-@@ -18,6 +87,17 @@
- */
- fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>;
- };
-+
-+ pinctrl_microsom_usdhc1: microsom-usdhc1 {
-+ fsl,pins = <
-+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
-+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
-+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
-+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
-+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
-+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
-+ >;
-+ };
- };
- };
-
-@@ -27,7 +107,25 @@
- status = "okay";
- };
-
-+/* UART4 - Connected to optional BRCM Wifi/BT/FM */
-+&uart4 {
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4_1>;
-+ fsl,uart-has-rtscts;
-+};
-+
- &usbotg {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_microsom_usbotg>;
- };
-+
-+/* USDHC1 - Connected to optional BRCM Wifi/BT/FM */
-+&usdhc1 {
-+ card-external-vcc-supply = <&reg_brcm>;
-+ card-reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>, <&gpio6 0 GPIO_ACTIVE_LOW>;
-+ keep-power-in-suspend;
-+ non-removable;
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&pinctrl_microsom_brcm_wifi &pinctrl_microsom_usdhc1>;
-+ vmmc-supply = <&reg_brcm>;
-+};
-diff -Nur linux-3.15-rc6.orig/arch/arm/boot/dts/imx6sl.dtsi linux-3.15-rc6/arch/arm/boot/dts/imx6sl.dtsi
---- linux-3.15-rc6.orig/arch/arm/boot/dts/imx6sl.dtsi 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/boot/dts/imx6sl.dtsi 2014-05-23 11:26:48.244939835 +0200
-@@ -111,6 +111,8 @@
- cache-level = <2>;
- arm,tag-latency = <4 2 3>;
- arm,data-latency = <4 2 3>;
-+ arm,dynamic-clk-gating;
-+ arm,standby-mode;
- };
-
- pmu {
-diff -Nur linux-3.15-rc6.orig/arch/arm/boot/dts/marco.dtsi linux-3.15-rc6/arch/arm/boot/dts/marco.dtsi
---- linux-3.15-rc6.orig/arch/arm/boot/dts/marco.dtsi 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/boot/dts/marco.dtsi 2014-05-23 11:26:48.244939835 +0200
-@@ -36,7 +36,7 @@
- ranges = <0x40000000 0x40000000 0xa0000000>;
-
- l2-cache-controller@c0030000 {
-- compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
-+ compatible = "arm,pl310-cache";
- reg = <0xc0030000 0x1000>;
- interrupts = <0 59 0>;
- arm,tag-latency = <1 1 1>;
-diff -Nur linux-3.15-rc6.orig/arch/arm/boot/dts/prima2.dtsi linux-3.15-rc6/arch/arm/boot/dts/prima2.dtsi
---- linux-3.15-rc6.orig/arch/arm/boot/dts/prima2.dtsi 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/boot/dts/prima2.dtsi 2014-05-23 11:26:48.244939835 +0200
-@@ -48,7 +48,7 @@
- ranges = <0x40000000 0x40000000 0x80000000>;
-
- l2-cache-controller@80040000 {
-- compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
-+ compatible = "arm,pl310-cache";
- reg = <0x80040000 0x1000>;
- interrupts = <59>;
- arm,tag-latency = <1 1 1>;
-diff -Nur linux-3.15-rc6.orig/arch/arm/configs/imx_v6_v7_defconfig linux-3.15-rc6/arch/arm/configs/imx_v6_v7_defconfig
---- linux-3.15-rc6.orig/arch/arm/configs/imx_v6_v7_defconfig 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/configs/imx_v6_v7_defconfig 2014-05-23 11:26:48.248939848 +0200
-@@ -245,6 +245,7 @@
- CONFIG_DRM_IMX_LDB=y
- CONFIG_DRM_IMX_IPUV3_CORE=y
- CONFIG_DRM_IMX_IPUV3=y
-+CONFIG_DRM_IMX_HDMI=y
- CONFIG_COMMON_CLK_DEBUG=y
- # CONFIG_IOMMU_SUPPORT is not set
- CONFIG_PWM=y
-diff -Nur linux-3.15-rc6.orig/arch/arm/include/asm/hardware/cache-l2x0.h linux-3.15-rc6/arch/arm/include/asm/hardware/cache-l2x0.h
---- linux-3.15-rc6.orig/arch/arm/include/asm/hardware/cache-l2x0.h 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/include/asm/hardware/cache-l2x0.h 2014-05-23 11:26:48.248939848 +0200
-@@ -26,8 +26,8 @@
- #define L2X0_CACHE_TYPE 0x004
- #define L2X0_CTRL 0x100
- #define L2X0_AUX_CTRL 0x104
--#define L2X0_TAG_LATENCY_CTRL 0x108
--#define L2X0_DATA_LATENCY_CTRL 0x10C
-+#define L310_TAG_LATENCY_CTRL 0x108
-+#define L310_DATA_LATENCY_CTRL 0x10C
- #define L2X0_EVENT_CNT_CTRL 0x200
- #define L2X0_EVENT_CNT1_CFG 0x204
- #define L2X0_EVENT_CNT0_CFG 0x208
-@@ -54,53 +54,93 @@
- #define L2X0_LOCKDOWN_WAY_D_BASE 0x900
- #define L2X0_LOCKDOWN_WAY_I_BASE 0x904
- #define L2X0_LOCKDOWN_STRIDE 0x08
--#define L2X0_ADDR_FILTER_START 0xC00
--#define L2X0_ADDR_FILTER_END 0xC04
-+#define L310_ADDR_FILTER_START 0xC00
-+#define L310_ADDR_FILTER_END 0xC04
- #define L2X0_TEST_OPERATION 0xF00
- #define L2X0_LINE_DATA 0xF10
- #define L2X0_LINE_TAG 0xF30
- #define L2X0_DEBUG_CTRL 0xF40
--#define L2X0_PREFETCH_CTRL 0xF60
--#define L2X0_POWER_CTRL 0xF80
--#define L2X0_DYNAMIC_CLK_GATING_EN (1 << 1)
--#define L2X0_STNDBY_MODE_EN (1 << 0)
-+#define L310_PREFETCH_CTRL 0xF60
-+#define L310_POWER_CTRL 0xF80
-+#define L310_DYNAMIC_CLK_GATING_EN (1 << 1)
-+#define L310_STNDBY_MODE_EN (1 << 0)
-
- /* Registers shifts and masks */
- #define L2X0_CACHE_ID_PART_MASK (0xf << 6)
- #define L2X0_CACHE_ID_PART_L210 (1 << 6)
-+#define L2X0_CACHE_ID_PART_L220 (2 << 6)
- #define L2X0_CACHE_ID_PART_L310 (3 << 6)
- #define L2X0_CACHE_ID_RTL_MASK 0x3f
--#define L2X0_CACHE_ID_RTL_R0P0 0x0
--#define L2X0_CACHE_ID_RTL_R1P0 0x2
--#define L2X0_CACHE_ID_RTL_R2P0 0x4
--#define L2X0_CACHE_ID_RTL_R3P0 0x5
--#define L2X0_CACHE_ID_RTL_R3P1 0x6
--#define L2X0_CACHE_ID_RTL_R3P2 0x8
--
--#define L2X0_AUX_CTRL_MASK 0xc0000fff
-+#define L210_CACHE_ID_RTL_R0P2_02 0x00
-+#define L210_CACHE_ID_RTL_R0P1 0x01
-+#define L210_CACHE_ID_RTL_R0P2_01 0x02
-+#define L210_CACHE_ID_RTL_R0P3 0x03
-+#define L210_CACHE_ID_RTL_R0P4 0x0b
-+#define L210_CACHE_ID_RTL_R0P5 0x0f
-+#define L220_CACHE_ID_RTL_R1P7_01REL0 0x06
-+#define L310_CACHE_ID_RTL_R0P0 0x00
-+#define L310_CACHE_ID_RTL_R1P0 0x02
-+#define L310_CACHE_ID_RTL_R2P0 0x04
-+#define L310_CACHE_ID_RTL_R3P0 0x05
-+#define L310_CACHE_ID_RTL_R3P1 0x06
-+#define L310_CACHE_ID_RTL_R3P1_50REL0 0x07
-+#define L310_CACHE_ID_RTL_R3P2 0x08
-+#define L310_CACHE_ID_RTL_R3P3 0x09
-+
-+/* L2C auxiliary control register - bits common to L2C-210/220/310 */
-+#define L2C_AUX_CTRL_WAY_SIZE_SHIFT 17
-+#define L2C_AUX_CTRL_WAY_SIZE_MASK (7 << 17)
-+#define L2C_AUX_CTRL_WAY_SIZE(n) ((n) << 17)
-+#define L2C_AUX_CTRL_EVTMON_ENABLE BIT(20)
-+#define L2C_AUX_CTRL_PARITY_ENABLE BIT(21)
-+#define L2C_AUX_CTRL_SHARED_OVERRIDE BIT(22)
-+/* L2C-210/220 common bits */
- #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0
--#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7
-+#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK (7 << 0)
- #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3
--#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3)
-+#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (7 << 3)
- #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6
--#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6)
-+#define L2X0_AUX_CTRL_TAG_LATENCY_MASK (7 << 6)
- #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9
--#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9)
--#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16
--#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17
--#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17)
--#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22
--#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26
--#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27
--#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT 28
--#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29
--#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30
--
--#define L2X0_LATENCY_CTRL_SETUP_SHIFT 0
--#define L2X0_LATENCY_CTRL_RD_SHIFT 4
--#define L2X0_LATENCY_CTRL_WR_SHIFT 8
--
--#define L2X0_ADDR_FILTER_EN 1
-+#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (7 << 9)
-+#define L2X0_AUX_CTRL_ASSOC_SHIFT 13
-+#define L2X0_AUX_CTRL_ASSOC_MASK (15 << 13)
-+/* L2C-210 specific bits */
-+#define L210_AUX_CTRL_WRAP_DISABLE BIT(12)
-+#define L210_AUX_CTRL_WA_OVERRIDE BIT(23)
-+#define L210_AUX_CTRL_EXCLUSIVE_ABORT BIT(24)
-+/* L2C-220 specific bits */
-+#define L220_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
-+#define L220_AUX_CTRL_FWA_SHIFT 23
-+#define L220_AUX_CTRL_FWA_MASK (3 << 23)
-+#define L220_AUX_CTRL_NS_LOCKDOWN BIT(26)
-+#define L220_AUX_CTRL_NS_INT_CTRL BIT(27)
-+/* L2C-310 specific bits */
-+#define L310_AUX_CTRL_FULL_LINE_ZERO BIT(0) /* R2P0+ */
-+#define L310_AUX_CTRL_HIGHPRIO_SO_DEV BIT(10) /* R2P0+ */
-+#define L310_AUX_CTRL_STORE_LIMITATION BIT(11) /* R2P0+ */
-+#define L310_AUX_CTRL_EXCLUSIVE_CACHE BIT(12)
-+#define L310_AUX_CTRL_ASSOCIATIVITY_16 BIT(16)
-+#define L310_AUX_CTRL_CACHE_REPLACE_RR BIT(25) /* R2P0+ */
-+#define L310_AUX_CTRL_NS_LOCKDOWN BIT(26)
-+#define L310_AUX_CTRL_NS_INT_CTRL BIT(27)
-+#define L310_AUX_CTRL_DATA_PREFETCH BIT(28)
-+#define L310_AUX_CTRL_INSTR_PREFETCH BIT(29)
-+#define L310_AUX_CTRL_EARLY_BRESP BIT(30) /* R2P0+ */
-+
-+#define L310_LATENCY_CTRL_SETUP(n) ((n) << 0)
-+#define L310_LATENCY_CTRL_RD(n) ((n) << 4)
-+#define L310_LATENCY_CTRL_WR(n) ((n) << 8)
-+
-+#define L310_ADDR_FILTER_EN 1
-+
-+#define L310_PREFETCH_CTRL_OFFSET_MASK 0x1f
-+#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR BIT(23)
-+#define L310_PREFETCH_CTRL_PREFETCH_DROP BIT(24)
-+#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP BIT(27)
-+#define L310_PREFETCH_CTRL_DATA_PREFETCH BIT(28)
-+#define L310_PREFETCH_CTRL_INSTR_PREFETCH BIT(29)
-+#define L310_PREFETCH_CTRL_DBL_LINEFILL BIT(30)
-
- #define L2X0_CTRL_EN 1
-
-diff -Nur linux-3.15-rc6.orig/arch/arm/include/asm/outercache.h linux-3.15-rc6/arch/arm/include/asm/outercache.h
---- linux-3.15-rc6.orig/arch/arm/include/asm/outercache.h 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/include/asm/outercache.h 2014-05-23 11:26:48.248939848 +0200
-@@ -21,6 +21,7 @@
- #ifndef __ASM_OUTERCACHE_H
- #define __ASM_OUTERCACHE_H
-
-+#include <linux/bug.h>
- #include <linux/types.h>
-
- struct outer_cache_fns {
-@@ -28,53 +29,84 @@
- void (*clean_range)(unsigned long, unsigned long);
- void (*flush_range)(unsigned long, unsigned long);
- void (*flush_all)(void);
-- void (*inv_all)(void);
- void (*disable)(void);
- #ifdef CONFIG_OUTER_CACHE_SYNC
- void (*sync)(void);
- #endif
-- void (*set_debug)(unsigned long);
- void (*resume)(void);
-+
-+ /* This is an ARM L2C thing */
-+ void (*write_sec)(unsigned long, unsigned);
- };
-
- extern struct outer_cache_fns outer_cache;
-
- #ifdef CONFIG_OUTER_CACHE
--
-+/**
-+ * outer_inv_range - invalidate range of outer cache lines
-+ * @start: starting physical address, inclusive
-+ * @end: end physical address, exclusive
-+ */
- static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
- {
- if (outer_cache.inv_range)
- outer_cache.inv_range(start, end);
- }
-+
-+/**
-+ * outer_clean_range - clean dirty outer cache lines
-+ * @start: starting physical address, inclusive
-+ * @end: end physical address, exclusive
-+ */
- static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
- {
- if (outer_cache.clean_range)
- outer_cache.clean_range(start, end);
- }
-+
-+/**
-+ * outer_flush_range - clean and invalidate outer cache lines
-+ * @start: starting physical address, inclusive
-+ * @end: end physical address, exclusive
-+ */
- static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
- {
- if (outer_cache.flush_range)
- outer_cache.flush_range(start, end);
- }
-
-+/**
-+ * outer_flush_all - clean and invalidate all cache lines in the outer cache
-+ *
-+ * Note: depending on implementation, this may not be atomic - it must
-+ * only be called with interrupts disabled and no other active outer
-+ * cache masters.
-+ *
-+ * It is intended that this function is only used by implementations
-+ * needing to override the outer_cache.disable() method due to security.
-+ * (Some implementations perform this as a clean followed by an invalidate.)
-+ */
- static inline void outer_flush_all(void)
- {
- if (outer_cache.flush_all)
- outer_cache.flush_all();
- }
-
--static inline void outer_inv_all(void)
--{
-- if (outer_cache.inv_all)
-- outer_cache.inv_all();
--}
--
--static inline void outer_disable(void)
--{
-- if (outer_cache.disable)
-- outer_cache.disable();
--}
--
-+/**
-+ * outer_disable - clean, invalidate and disable the outer cache
-+ *
-+ * Disable the outer cache, ensuring that any data contained in the outer
-+ * cache is pushed out to lower levels of system memory. The note and
-+ * conditions above concerning outer_flush_all() applies here.
-+ */
-+extern void outer_disable(void);
-+
-+/**
-+ * outer_resume - restore the cache configuration and re-enable outer cache
-+ *
-+ * Restore any configuration that the cache had when previously enabled,
-+ * and re-enable the outer cache.
-+ */
- static inline void outer_resume(void)
- {
- if (outer_cache.resume)
-@@ -90,13 +122,18 @@
- static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
- { }
- static inline void outer_flush_all(void) { }
--static inline void outer_inv_all(void) { }
- static inline void outer_disable(void) { }
- static inline void outer_resume(void) { }
-
- #endif
-
- #ifdef CONFIG_OUTER_CACHE_SYNC
-+/**
-+ * outer_sync - perform a sync point for outer cache
-+ *
-+ * Ensure that all outer cache operations are complete and any store
-+ * buffers are drained.
-+ */
- static inline void outer_sync(void)
- {
- if (outer_cache.sync)
-diff -Nur linux-3.15-rc6.orig/arch/arm/Kconfig linux-3.15-rc6/arch/arm/Kconfig
---- linux-3.15-rc6.orig/arch/arm/Kconfig 2014-05-21 23:42:02.000000000 +0200
-+++ linux-3.15-rc6/arch/arm/Kconfig 2014-05-23 11:26:48.248939848 +0200
-@@ -1230,19 +1230,6 @@
- register of the Cortex-A9 which reduces the linefill issuing
- capabilities of the processor.
-
--config PL310_ERRATA_588369
-- bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
-- depends on CACHE_L2X0
-- help
-- The PL310 L2 cache controller implements three types of Clean &
-- Invalidate maintenance operations: by Physical Address
-- (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
-- They are architecturally defined to behave as the execution of a
-- clean operation followed immediately by an invalidate operation,
-- both performing to the same memory location. This functionality
-- is not correctly implemented in PL310 as clean lines are not
-- invalidated as a result of these operations.
--
- config ARM_ERRATA_643719
- bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
- depends on CPU_V7 && SMP
-@@ -1265,17 +1252,6 @@
- tables. The workaround changes the TLB flushing routines to invalidate
- entries regardless of the ASID.
-
--config PL310_ERRATA_727915
-- bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
-- depends on CACHE_L2X0
-- help
-- PL310 implements the Clean & Invalidate by Way L2 cache maintenance
-- operation (offset 0x7FC). This operation runs in background so that
-- PL310 can handle normal accesses while it is in progress. Under very
-- rare circumstances, due to this erratum, write data can be lost when
-- PL310 treats a cacheable write transaction during a Clean &
-- Invalidate by Way operation.
--
- config ARM_ERRATA_743622
- bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
- depends on CPU_V7
-@@ -1301,21 +1277,6 @@
- operation is received by a CPU before the ICIALLUIS has completed,
- potentially leading to corrupted entries in the cache or TLB.
-
--config PL310_ERRATA_753970
-- bool "PL310 errata: cache sync operation may be faulty"
-- depends on CACHE_PL310
-- help
-- This option enables the workaround for the 753970 PL310 (r3p0) erratum.
--
-- Under some condition the effect of cache sync operation on
-- the store buffer still remains when the operation completes.
-- This means that the store buffer is always asked to drain and
-- this prevents it from merging any further writes. The workaround
-- is to replace the normal offset of cache sync operation (0x730)
-- by another offset targeting an unmapped PL310 register 0x740.
-- This has the same effect as the cache sync operation: store buffer
-- drain and waiting for all buffers empty.
--
- config ARM_ERRATA_754322
- bool "ARM errata: possible faulty MMU translations following an ASID switch"
- depends on CPU_V7
-@@ -1364,18 +1325,6 @@
- relevant cache maintenance functions and sets a specific bit