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authorWaldemar Brodkorb <wbrodkorb@conet.de>2018-09-21 18:34:51 (GMT)
committerWaldemar Brodkorb <wbrodkorb@conet.de>2018-09-21 18:34:51 (GMT)
commit4ce36c95b8d641123613767cd2ad673dea82a516 (patch)
tree8ac04315c2a6bd38cebff73bb7501ef9f4ce27e3
parent37935120c7c9ff32fa25bc72c94eaa5055649716 (diff)
riscv: add PLIC
-rw-r--r--target/riscv64/kernel/qemu-riscv642
1 files changed, 1 insertions, 1 deletions
diff --git a/target/riscv64/kernel/qemu-riscv64 b/target/riscv64/kernel/qemu-riscv64
index 0b18267..4991fbd 100644
--- a/target/riscv64/kernel/qemu-riscv64
+++ b/target/riscv64/kernel/qemu-riscv64
@@ -1,5 +1,5 @@
CONFIG_RISCV=y
-CONFIG_RISCV_PLIC=y
+CONFIG_SIFIVE_PLIC=y
CONFIG_HVC_RISCV_SBI=y
CONFIG_CMDLINE_BOOL=y
CONFIG_SECTION_MISMATCH_WARN_ONLY=y